1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
82 static char version[] __devinitdata =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
99 module_param(num_queues, int, 0);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
128 struct workqueue_struct *bnx2x_wq;
130 enum bnx2x_board_type {
149 /* indexed by board_type, above */
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
220 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
221 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
222 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
223 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
224 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
225 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
226 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
227 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
228 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
229 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
230 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
231 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
250 u32 addr, dma_addr_t mapping)
252 REG_WR(bp, addr, U64_LO(mapping));
253 REG_WR(bp, addr + 4, U64_HI(mapping));
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257 dma_addr_t mapping, u16 abs_fid)
259 u32 addr = XSEM_REG_FAST_MEMORY +
260 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
262 __storm_memset_dma_mapping(bp, addr, mapping);
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
270 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
272 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
274 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
281 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
283 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
285 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
287 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
291 static void storm_memset_eq_data(struct bnx2x *bp,
292 struct event_ring_data *eq_data,
295 size_t size = sizeof(struct event_ring_data);
297 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
299 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
305 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
306 REG_WR16(bp, addr, eq_prod);
310 * locking is done by mcp
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
314 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
317 PCICFG_VENDOR_ID_OFFSET);
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
327 PCICFG_VENDOR_ID_OFFSET);
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
345 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
349 REG_WR(bp, dmae_reg_go_c[idx], 1);
352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
354 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
360 return opcode & ~DMAE_CMD_SRC_RESET;
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364 bool with_comp, u8 comp_type)
368 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369 (dst_type << DMAE_COMMAND_DST_SHIFT));
371 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
373 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
375 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
376 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
379 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
381 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
384 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389 struct dmae_command *dmae,
390 u8 src_type, u8 dst_type)
392 memset(dmae, 0, sizeof(struct dmae_command));
395 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396 true, DMAE_COMP_PCI);
398 /* fill in the completion parameters */
399 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401 dmae->comp_val = DMAE_COMP_VAL;
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406 struct dmae_command *dmae)
408 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
413 * Lock the dmae channel. Disable BHs to prevent a dead-lock
414 * as long as this code is called both from syscall context and
415 * from ndo_set_rx_mode() flow that may be called from BH.
417 spin_lock_bh(&bp->dmae_lock);
419 /* reset completion */
422 /* post the command on the channel used for initializations */
423 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
425 /* wait for completion */
427 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
430 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
431 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
432 BNX2X_ERR("DMAE timeout!\n");
439 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440 BNX2X_ERR("DMAE PCI error!\n");
445 spin_unlock_bh(&bp->dmae_lock);
449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
452 struct dmae_command dmae;
454 if (!bp->dmae_ready) {
455 u32 *data = bnx2x_sp(bp, wb_data[0]);
458 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
460 bnx2x_init_str_wr(bp, dst_addr, data, len32);
464 /* set opcode and fixed command fields */
465 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
467 /* fill in addresses and len */
468 dmae.src_addr_lo = U64_LO(dma_addr);
469 dmae.src_addr_hi = U64_HI(dma_addr);
470 dmae.dst_addr_lo = dst_addr >> 2;
471 dmae.dst_addr_hi = 0;
474 /* issue the command and wait for completion */
475 bnx2x_issue_dmae_with_comp(bp, &dmae);
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
480 struct dmae_command dmae;
482 if (!bp->dmae_ready) {
483 u32 *data = bnx2x_sp(bp, wb_data[0]);
487 for (i = 0; i < len32; i++)
488 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
490 for (i = 0; i < len32; i++)
491 data[i] = REG_RD(bp, src_addr + i*4);
496 /* set opcode and fixed command fields */
497 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
499 /* fill in addresses and len */
500 dmae.src_addr_lo = src_addr >> 2;
501 dmae.src_addr_hi = 0;
502 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
513 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
516 while (len > dmae_wr_max) {
517 bnx2x_write_dmae(bp, phys_addr + offset,
518 addr + offset, dmae_wr_max);
519 offset += dmae_wr_max * 4;
523 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
526 static int bnx2x_mc_assert(struct bnx2x *bp)
530 u32 row0, row1, row2, row3;
533 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
534 XSTORM_ASSERT_LIST_INDEX_OFFSET);
536 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
538 /* print the asserts */
539 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
541 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
542 XSTORM_ASSERT_LIST_OFFSET(i));
543 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
544 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
545 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
547 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
550 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552 i, row3, row2, row1, row0);
560 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
561 TSTORM_ASSERT_LIST_INDEX_OFFSET);
563 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
565 /* print the asserts */
566 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
568 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
569 TSTORM_ASSERT_LIST_OFFSET(i));
570 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
571 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
572 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
574 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
577 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i, row3, row2, row1, row0);
587 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
588 CSTORM_ASSERT_LIST_INDEX_OFFSET);
590 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
592 /* print the asserts */
593 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
595 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
596 CSTORM_ASSERT_LIST_OFFSET(i));
597 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
598 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
599 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
601 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
604 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606 i, row3, row2, row1, row0);
614 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
615 USTORM_ASSERT_LIST_INDEX_OFFSET);
617 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
619 /* print the asserts */
620 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
622 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
623 USTORM_ASSERT_LIST_OFFSET(i));
624 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
625 USTORM_ASSERT_LIST_OFFSET(i) + 4);
626 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_OFFSET(i) + 8);
628 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629 USTORM_ASSERT_LIST_OFFSET(i) + 12);
631 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633 i, row3, row2, row1, row0);
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
649 u32 trace_shmem_base;
651 BNX2X_ERR("NO MCP - can not dump\n");
654 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655 (bp->common.bc_ver & 0xff0000) >> 16,
656 (bp->common.bc_ver & 0xff00) >> 8,
657 (bp->common.bc_ver & 0xff));
659 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
660 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
661 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
663 if (BP_PATH(bp) == 0)
664 trace_shmem_base = bp->common.shmem_base;
666 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667 addr = trace_shmem_base - 0x800;
669 /* validate TRCB signature */
670 mark = REG_RD(bp, addr);
671 if (mark != MFW_TRACE_SIGNATURE) {
672 BNX2X_ERR("Trace buffer signature is missing.");
676 /* read cyclic buffer pointer */
678 mark = REG_RD(bp, addr);
679 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
680 + ((mark + 0x3) & ~0x3) - 0x08000000;
681 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
684 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685 for (word = 0; word < 8; word++)
686 data[word] = htonl(REG_RD(bp, offset + 4*word));
688 pr_cont("%s", (char *)data);
690 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691 for (word = 0; word < 8; word++)
692 data[word] = htonl(REG_RD(bp, offset + 4*word));
694 pr_cont("%s", (char *)data);
696 printk("%s" "end of fw dump\n", lvl);
699 static void bnx2x_fw_dump(struct bnx2x *bp)
701 bnx2x_fw_dump_lvl(bp, KERN_ERR);
704 void bnx2x_panic_dump(struct bnx2x *bp)
708 struct hc_sp_status_block_data sp_sb_data;
709 int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711 u16 start = 0, end = 0;
715 bp->stats_state = STATS_STATE_DISABLED;
716 bp->eth_stats.unrecoverable_error++;
717 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
719 BNX2X_ERR("begin crash dump -----------------\n");
723 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724 bp->def_idx, bp->def_att_idx, bp->attn_state,
725 bp->spq_prod_idx, bp->stats_counter);
726 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727 bp->def_status_blk->atten_status_block.attn_bits,
728 bp->def_status_blk->atten_status_block.attn_bits_ack,
729 bp->def_status_blk->atten_status_block.status_block_id,
730 bp->def_status_blk->atten_status_block.attn_bits_index);
732 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
734 bp->def_status_blk->sp_sb.index_values[i],
735 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
737 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
739 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
742 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743 sp_sb_data.igu_sb_id,
744 sp_sb_data.igu_seg_id,
745 sp_sb_data.p_func.pf_id,
746 sp_sb_data.p_func.vnic_id,
747 sp_sb_data.p_func.vf_id,
748 sp_sb_data.p_func.vf_valid,
752 for_each_eth_queue(bp, i) {
753 struct bnx2x_fastpath *fp = &bp->fp[i];
755 struct hc_status_block_data_e2 sb_data_e2;
756 struct hc_status_block_data_e1x sb_data_e1x;
757 struct hc_status_block_sm *hc_sm_p =
759 sb_data_e1x.common.state_machine :
760 sb_data_e2.common.state_machine;
761 struct hc_index_data *hc_index_p =
763 sb_data_e1x.index_data :
764 sb_data_e2.index_data;
767 struct bnx2x_fp_txdata txdata;
770 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771 i, fp->rx_bd_prod, fp->rx_bd_cons,
773 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775 fp->rx_sge_prod, fp->last_max_sge,
776 le16_to_cpu(fp->fp_hc_idx));
779 for_each_cos_in_tx_queue(fp, cos)
781 txdata = *fp->txdata_ptr[cos];
782 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783 i, txdata.tx_pkt_prod,
784 txdata.tx_pkt_cons, txdata.tx_bd_prod,
786 le16_to_cpu(*txdata.tx_cons_sb));
789 loop = CHIP_IS_E1x(bp) ?
790 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
798 BNX2X_ERR(" run indexes (");
799 for (j = 0; j < HC_SB_MAX_SM; j++)
801 fp->sb_running_index[j],
802 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
804 BNX2X_ERR(" indexes (");
805 for (j = 0; j < loop; j++)
807 fp->sb_index_values[j],
808 (j == loop - 1) ? ")" : " ");
810 data_size = CHIP_IS_E1x(bp) ?
811 sizeof(struct hc_status_block_data_e1x) :
812 sizeof(struct hc_status_block_data_e2);
813 data_size /= sizeof(u32);
814 sb_data_p = CHIP_IS_E1x(bp) ?
815 (u32 *)&sb_data_e1x :
817 /* copy sb data in here */
818 for (j = 0; j < data_size; j++)
819 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
820 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
823 if (!CHIP_IS_E1x(bp)) {
824 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
825 sb_data_e2.common.p_func.pf_id,
826 sb_data_e2.common.p_func.vf_id,
827 sb_data_e2.common.p_func.vf_valid,
828 sb_data_e2.common.p_func.vnic_id,
829 sb_data_e2.common.same_igu_sb_1b,
830 sb_data_e2.common.state);
832 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
833 sb_data_e1x.common.p_func.pf_id,
834 sb_data_e1x.common.p_func.vf_id,
835 sb_data_e1x.common.p_func.vf_valid,
836 sb_data_e1x.common.p_func.vnic_id,
837 sb_data_e1x.common.same_igu_sb_1b,
838 sb_data_e1x.common.state);
842 for (j = 0; j < HC_SB_MAX_SM; j++) {
843 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
844 j, hc_sm_p[j].__flags,
845 hc_sm_p[j].igu_sb_id,
846 hc_sm_p[j].igu_seg_id,
847 hc_sm_p[j].time_to_expire,
848 hc_sm_p[j].timer_value);
852 for (j = 0; j < loop; j++) {
853 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
855 hc_index_p[j].timeout);
859 #ifdef BNX2X_STOP_ON_ERROR
862 for_each_rx_queue(bp, i) {
863 struct bnx2x_fastpath *fp = &bp->fp[i];
865 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
866 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
867 for (j = start; j != end; j = RX_BD(j + 1)) {
868 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
869 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
871 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
872 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
875 start = RX_SGE(fp->rx_sge_prod);
876 end = RX_SGE(fp->last_max_sge);
877 for (j = start; j != end; j = RX_SGE(j + 1)) {
878 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
879 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
881 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
882 i, j, rx_sge[1], rx_sge[0], sw_page->page);
885 start = RCQ_BD(fp->rx_comp_cons - 10);
886 end = RCQ_BD(fp->rx_comp_cons + 503);
887 for (j = start; j != end; j = RCQ_BD(j + 1)) {
888 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
890 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
891 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
896 for_each_tx_queue(bp, i) {
897 struct bnx2x_fastpath *fp = &bp->fp[i];
898 for_each_cos_in_tx_queue(fp, cos) {
899 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
901 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
902 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
903 for (j = start; j != end; j = TX_BD(j + 1)) {
904 struct sw_tx_bd *sw_bd =
905 &txdata->tx_buf_ring[j];
907 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
908 i, cos, j, sw_bd->skb,
912 start = TX_BD(txdata->tx_bd_cons - 10);
913 end = TX_BD(txdata->tx_bd_cons + 254);
914 for (j = start; j != end; j = TX_BD(j + 1)) {
915 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
917 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
918 i, cos, j, tx_bd[0], tx_bd[1],
926 BNX2X_ERR("end crash dump -----------------\n");
932 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
935 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
936 #define FLR_WAIT_INTERVAL 50 /* usec */
937 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
939 struct pbf_pN_buf_regs {
946 struct pbf_pN_cmd_regs {
952 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
953 struct pbf_pN_buf_regs *regs,
956 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
957 u32 cur_cnt = poll_count;
959 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
960 crd = crd_start = REG_RD(bp, regs->crd);
961 init_crd = REG_RD(bp, regs->init_crd);
963 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
964 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
965 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
967 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
968 (init_crd - crd_start))) {
970 udelay(FLR_WAIT_INTERVAL);
971 crd = REG_RD(bp, regs->crd);
972 crd_freed = REG_RD(bp, regs->crd_freed);
974 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
976 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
978 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
979 regs->pN, crd_freed);
983 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
984 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
987 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
988 struct pbf_pN_cmd_regs *regs,
991 u32 occup, to_free, freed, freed_start;
992 u32 cur_cnt = poll_count;
994 occup = to_free = REG_RD(bp, regs->lines_occup);
995 freed = freed_start = REG_RD(bp, regs->lines_freed);
997 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
998 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1000 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1002 udelay(FLR_WAIT_INTERVAL);
1003 occup = REG_RD(bp, regs->lines_occup);
1004 freed = REG_RD(bp, regs->lines_freed);
1006 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1008 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1010 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1015 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1016 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1019 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1020 u32 expected, u32 poll_count)
1022 u32 cur_cnt = poll_count;
1025 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1026 udelay(FLR_WAIT_INTERVAL);
1031 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1032 char *msg, u32 poll_cnt)
1034 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1036 BNX2X_ERR("%s usage count=%d\n", msg, val);
1042 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1044 /* adjust polling timeout */
1045 if (CHIP_REV_IS_EMUL(bp))
1046 return FLR_POLL_CNT * 2000;
1048 if (CHIP_REV_IS_FPGA(bp))
1049 return FLR_POLL_CNT * 120;
1051 return FLR_POLL_CNT;
1054 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1056 struct pbf_pN_cmd_regs cmd_regs[] = {
1057 {0, (CHIP_IS_E3B0(bp)) ?
1058 PBF_REG_TQ_OCCUPANCY_Q0 :
1059 PBF_REG_P0_TQ_OCCUPANCY,
1060 (CHIP_IS_E3B0(bp)) ?
1061 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1062 PBF_REG_P0_TQ_LINES_FREED_CNT},
1063 {1, (CHIP_IS_E3B0(bp)) ?
1064 PBF_REG_TQ_OCCUPANCY_Q1 :
1065 PBF_REG_P1_TQ_OCCUPANCY,
1066 (CHIP_IS_E3B0(bp)) ?
1067 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1068 PBF_REG_P1_TQ_LINES_FREED_CNT},
1069 {4, (CHIP_IS_E3B0(bp)) ?
1070 PBF_REG_TQ_OCCUPANCY_LB_Q :
1071 PBF_REG_P4_TQ_OCCUPANCY,
1072 (CHIP_IS_E3B0(bp)) ?
1073 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1074 PBF_REG_P4_TQ_LINES_FREED_CNT}
1077 struct pbf_pN_buf_regs buf_regs[] = {
1078 {0, (CHIP_IS_E3B0(bp)) ?
1079 PBF_REG_INIT_CRD_Q0 :
1080 PBF_REG_P0_INIT_CRD ,
1081 (CHIP_IS_E3B0(bp)) ?
1084 (CHIP_IS_E3B0(bp)) ?
1085 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1086 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1087 {1, (CHIP_IS_E3B0(bp)) ?
1088 PBF_REG_INIT_CRD_Q1 :
1089 PBF_REG_P1_INIT_CRD,
1090 (CHIP_IS_E3B0(bp)) ?
1093 (CHIP_IS_E3B0(bp)) ?
1094 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1095 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1096 {4, (CHIP_IS_E3B0(bp)) ?
1097 PBF_REG_INIT_CRD_LB_Q :
1098 PBF_REG_P4_INIT_CRD,
1099 (CHIP_IS_E3B0(bp)) ?
1100 PBF_REG_CREDIT_LB_Q :
1102 (CHIP_IS_E3B0(bp)) ?
1103 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1104 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1109 /* Verify the command queues are flushed P0, P1, P4 */
1110 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1111 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1114 /* Verify the transmission buffers are flushed P0, P1, P4 */
1115 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1116 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1119 #define OP_GEN_PARAM(param) \
1120 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1122 #define OP_GEN_TYPE(type) \
1123 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1125 #define OP_GEN_AGG_VECT(index) \
1126 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1129 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1132 struct sdm_op_gen op_gen = {0};
1134 u32 comp_addr = BAR_CSTRORM_INTMEM +
1135 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1138 if (REG_RD(bp, comp_addr)) {
1139 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1143 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1144 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1145 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1146 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1148 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1149 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1151 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1152 BNX2X_ERR("FW final cleanup did not succeed\n");
1153 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1154 (REG_RD(bp, comp_addr)));
1157 /* Zero completion for nxt FLR */
1158 REG_WR(bp, comp_addr, 0);
1163 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1168 pos = pci_pcie_cap(dev);
1172 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1173 return status & PCI_EXP_DEVSTA_TRPND;
1176 /* PF FLR specific routines
1178 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1181 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1182 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1183 CFC_REG_NUM_LCIDS_INSIDE_PF,
1184 "CFC PF usage counter timed out",
1189 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1190 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1191 DORQ_REG_PF_USAGE_CNT,
1192 "DQ PF usage counter timed out",
1196 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1197 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1198 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1199 "QM PF usage counter timed out",
1203 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1204 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1205 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1206 "Timers VNIC usage counter timed out",
1209 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1210 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1211 "Timers NUM_SCANS usage counter timed out",
1215 /* Wait DMAE PF usage counter to zero */
1216 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1217 dmae_reg_go_c[INIT_DMAE_C(bp)],
1218 "DMAE dommand register timed out",
1225 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1229 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1230 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1232 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1233 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1235 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1236 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1238 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1239 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1241 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1242 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1244 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1245 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1247 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1248 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1250 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1251 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1255 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1257 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1259 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1261 /* Re-enable PF target read access */
1262 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1264 /* Poll HW usage counters */
1265 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1266 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1269 /* Zero the igu 'trailing edge' and 'leading edge' */
1271 /* Send the FW cleanup command */
1272 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1277 /* Verify TX hw is flushed */
1278 bnx2x_tx_hw_flushed(bp, poll_cnt);
1280 /* Wait 100ms (not adjusted according to platform) */
1283 /* Verify no pending pci transactions */
1284 if (bnx2x_is_pcie_pending(bp->pdev))
1285 BNX2X_ERR("PCIE Transactions still pending\n");
1288 bnx2x_hw_enable_status(bp);
1291 * Master enable - Due to WB DMAE writes performed before this
1292 * register is re-initialized as part of the regular function init
1294 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1299 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1301 int port = BP_PORT(bp);
1302 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1303 u32 val = REG_RD(bp, addr);
1304 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1305 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1306 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1309 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1310 HC_CONFIG_0_REG_INT_LINE_EN_0);
1311 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1312 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1314 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1316 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1317 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1318 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1319 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1321 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1322 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1323 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1324 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1326 if (!CHIP_IS_E1(bp)) {
1328 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1330 REG_WR(bp, addr, val);
1332 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1337 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1340 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1341 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1343 REG_WR(bp, addr, val);
1345 * Ensure that HC_CONFIG is written before leading/trailing edge config
1350 if (!CHIP_IS_E1(bp)) {
1351 /* init leading/trailing edge */
1353 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1355 /* enable nig and gpio3 attention */
1360 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1361 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1364 /* Make sure that interrupts are indeed enabled from here on */
1368 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1371 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1372 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1373 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1375 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1378 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1379 IGU_PF_CONF_SINGLE_ISR_EN);
1380 val |= (IGU_PF_CONF_FUNC_EN |
1381 IGU_PF_CONF_MSI_MSIX_EN |
1382 IGU_PF_CONF_ATTN_BIT_EN);
1385 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1387 val &= ~IGU_PF_CONF_INT_LINE_EN;
1388 val |= (IGU_PF_CONF_FUNC_EN |
1389 IGU_PF_CONF_MSI_MSIX_EN |
1390 IGU_PF_CONF_ATTN_BIT_EN |
1391 IGU_PF_CONF_SINGLE_ISR_EN);
1393 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1394 val |= (IGU_PF_CONF_FUNC_EN |
1395 IGU_PF_CONF_INT_LINE_EN |
1396 IGU_PF_CONF_ATTN_BIT_EN |
1397 IGU_PF_CONF_SINGLE_ISR_EN);
1400 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1401 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1403 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1405 if (val & IGU_PF_CONF_INT_LINE_EN)
1406 pci_intx(bp->pdev, true);
1410 /* init leading/trailing edge */
1412 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1414 /* enable nig and gpio3 attention */
1419 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1420 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1422 /* Make sure that interrupts are indeed enabled from here on */
1426 void bnx2x_int_enable(struct bnx2x *bp)
1428 if (bp->common.int_block == INT_BLOCK_HC)
1429 bnx2x_hc_int_enable(bp);
1431 bnx2x_igu_int_enable(bp);
1434 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1436 int port = BP_PORT(bp);
1437 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1438 u32 val = REG_RD(bp, addr);
1441 * in E1 we must use only PCI configuration space to disable
1442 * MSI/MSIX capablility
1443 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1445 if (CHIP_IS_E1(bp)) {
1446 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1447 * Use mask register to prevent from HC sending interrupts
1448 * after we exit the function
1450 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1452 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1453 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1454 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1456 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1457 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1458 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1459 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1461 DP(NETIF_MSG_IFDOWN,
1462 "write %x to HC %d (addr 0x%x)\n",
1465 /* flush all outstanding writes */
1468 REG_WR(bp, addr, val);
1469 if (REG_RD(bp, addr) != val)
1470 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1473 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1475 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1477 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1478 IGU_PF_CONF_INT_LINE_EN |
1479 IGU_PF_CONF_ATTN_BIT_EN);
1481 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1483 /* flush all outstanding writes */
1486 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1487 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1488 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1491 void bnx2x_int_disable(struct bnx2x *bp)
1493 if (bp->common.int_block == INT_BLOCK_HC)
1494 bnx2x_hc_int_disable(bp);
1496 bnx2x_igu_int_disable(bp);
1499 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1501 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1505 /* prevent the HW from sending interrupts */
1506 bnx2x_int_disable(bp);
1508 /* make sure all ISRs are done */
1510 synchronize_irq(bp->msix_table[0].vector);
1515 for_each_eth_queue(bp, i)
1516 synchronize_irq(bp->msix_table[offset++].vector);
1518 synchronize_irq(bp->pdev->irq);
1520 /* make sure sp_task is not running */
1521 cancel_delayed_work(&bp->sp_task);
1522 cancel_delayed_work(&bp->period_task);
1523 flush_workqueue(bnx2x_wq);
1529 * General service functions
1532 /* Return true if succeeded to acquire the lock */
1533 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1536 u32 resource_bit = (1 << resource);
1537 int func = BP_FUNC(bp);
1538 u32 hw_lock_control_reg;
1540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1541 "Trying to take a lock on resource %d\n", resource);
1543 /* Validating that the resource is within range */
1544 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1547 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1552 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1554 hw_lock_control_reg =
1555 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1557 /* Try to acquire the lock */
1558 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1559 lock_status = REG_RD(bp, hw_lock_control_reg);
1560 if (lock_status & resource_bit)
1563 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1564 "Failed to get a lock on resource %d\n", resource);
1569 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1571 * @bp: driver handle
1573 * Returns the recovery leader resource id according to the engine this function
1574 * belongs to. Currently only only 2 engines is supported.
1576 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1579 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1581 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1585 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1587 * @bp: driver handle
1589 * Tries to aquire a leader lock for current engine.
1591 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1593 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1597 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1600 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1602 struct bnx2x *bp = fp->bp;
1603 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1604 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1605 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1606 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1609 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1610 fp->index, cid, command, bp->state,
1611 rr_cqe->ramrod_cqe.ramrod_type);
1614 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1615 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1616 drv_cmd = BNX2X_Q_CMD_UPDATE;
1619 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1620 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1621 drv_cmd = BNX2X_Q_CMD_SETUP;
1624 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1625 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1626 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1629 case (RAMROD_CMD_ID_ETH_HALT):
1630 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1631 drv_cmd = BNX2X_Q_CMD_HALT;
1634 case (RAMROD_CMD_ID_ETH_TERMINATE):
1635 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1636 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1639 case (RAMROD_CMD_ID_ETH_EMPTY):
1640 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1641 drv_cmd = BNX2X_Q_CMD_EMPTY;
1645 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1646 command, fp->index);
1650 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1651 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1652 /* q_obj->complete_cmd() failure means that this was
1653 * an unexpected completion.
1655 * In this case we don't want to increase the bp->spq_left
1656 * because apparently we haven't sent this command the first
1659 #ifdef BNX2X_STOP_ON_ERROR
1665 smp_mb__before_atomic_inc();
1666 atomic_inc(&bp->cq_spq_left);
1667 /* push the change in bp->spq_left and towards the memory */
1668 smp_mb__after_atomic_inc();
1670 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1672 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1673 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1674 /* if Q update ramrod is completed for last Q in AFEX vif set
1675 * flow, then ACK MCP at the end
1677 * mark pending ACK to MCP bit.
1678 * prevent case that both bits are cleared.
1679 * At the end of load/unload driver checks that
1680 * sp_state is cleaerd, and this order prevents
1683 smp_mb__before_clear_bit();
1684 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1686 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1687 smp_mb__after_clear_bit();
1689 /* schedule workqueue to send ack to MCP */
1690 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1696 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1697 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1699 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1701 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1705 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1707 struct bnx2x *bp = netdev_priv(dev_instance);
1708 u16 status = bnx2x_ack_int(bp);
1713 /* Return here if interrupt is shared and it's not for us */
1714 if (unlikely(status == 0)) {
1715 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1718 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1720 #ifdef BNX2X_STOP_ON_ERROR
1721 if (unlikely(bp->panic))
1725 for_each_eth_queue(bp, i) {
1726 struct bnx2x_fastpath *fp = &bp->fp[i];
1728 mask = 0x2 << (fp->index + CNIC_PRESENT);
1729 if (status & mask) {
1730 /* Handle Rx or Tx according to SB id */
1731 prefetch(fp->rx_cons_sb);
1732 for_each_cos_in_tx_queue(fp, cos)
1733 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1734 prefetch(&fp->sb_running_index[SM_RX_ID]);
1735 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1742 if (status & (mask | 0x1)) {
1743 struct cnic_ops *c_ops = NULL;
1745 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1747 c_ops = rcu_dereference(bp->cnic_ops);
1749 c_ops->cnic_handler(bp->cnic_data, NULL);
1757 if (unlikely(status & 0x1)) {
1758 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1765 if (unlikely(status))
1766 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1775 * General service functions
1778 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1781 u32 resource_bit = (1 << resource);
1782 int func = BP_FUNC(bp);
1783 u32 hw_lock_control_reg;
1786 /* Validating that the resource is within range */
1787 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1788 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1789 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1794 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1796 hw_lock_control_reg =
1797 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1800 /* Validating that the resource is not already taken */
1801 lock_status = REG_RD(bp, hw_lock_control_reg);
1802 if (lock_status & resource_bit) {
1803 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1804 lock_status, resource_bit);
1808 /* Try for 5 second every 5ms */
1809 for (cnt = 0; cnt < 1000; cnt++) {
1810 /* Try to acquire the lock */
1811 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit)
1818 BNX2X_ERR("Timeout\n");
1822 int bnx2x_release_leader_lock(struct bnx2x *bp)
1824 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1827 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1830 u32 resource_bit = (1 << resource);
1831 int func = BP_FUNC(bp);
1832 u32 hw_lock_control_reg;
1834 /* Validating that the resource is within range */
1835 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1836 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1837 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1844 hw_lock_control_reg =
1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1848 /* Validating that the resource is currently taken */
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (!(lock_status & resource_bit)) {
1851 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1852 lock_status, resource_bit);
1856 REG_WR(bp, hw_lock_control_reg, resource_bit);
1861 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1863 /* The GPIO should be swapped if swap register is set and active */
1864 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1865 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1866 int gpio_shift = gpio_num +
1867 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1868 u32 gpio_mask = (1 << gpio_shift);
1872 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1873 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1877 /* read GPIO value */
1878 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1880 /* get the requested pin value */
1881 if ((gpio_reg & gpio_mask) == gpio_mask)
1886 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1891 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1893 /* The GPIO should be swapped if swap register is set and active */
1894 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1895 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1896 int gpio_shift = gpio_num +
1897 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1898 u32 gpio_mask = (1 << gpio_shift);
1901 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1902 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1907 /* read GPIO and mask except the float bits */
1908 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1911 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1913 "Set GPIO %d (shift %d) -> output low\n",
1914 gpio_num, gpio_shift);
1915 /* clear FLOAT and set CLR */
1916 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1917 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1920 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1922 "Set GPIO %d (shift %d) -> output high\n",
1923 gpio_num, gpio_shift);
1924 /* clear FLOAT and set SET */
1925 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1926 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1929 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1931 "Set GPIO %d (shift %d) -> input\n",
1932 gpio_num, gpio_shift);
1934 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1941 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1942 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1952 /* Any port swapping should be handled by caller. */
1954 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1955 /* read GPIO and mask except the float bits */
1956 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1957 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1959 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1963 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1965 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1968 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1969 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1971 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1974 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1975 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1977 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1981 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1987 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1996 /* The GPIO should be swapped if swap register is set and active */
1997 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1998 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1999 int gpio_shift = gpio_num +
2000 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2001 u32 gpio_mask = (1 << gpio_shift);
2004 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2005 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2009 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2011 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2014 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2016 "Clear GPIO INT %d (shift %d) -> output low\n",
2017 gpio_num, gpio_shift);
2018 /* clear SET and set CLR */
2019 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2020 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2023 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2025 "Set GPIO INT %d (shift %d) -> output high\n",
2026 gpio_num, gpio_shift);
2027 /* clear CLR and set SET */
2028 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2029 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2036 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2042 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2044 u32 spio_mask = (1 << spio_num);
2047 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2048 (spio_num > MISC_REGISTERS_SPIO_7)) {
2049 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2053 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2054 /* read SPIO and mask except the float bits */
2055 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2058 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2060 /* clear FLOAT and set CLR */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2065 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2067 /* clear FLOAT and set SET */
2068 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2069 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2072 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2073 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2075 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2082 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2090 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2091 switch (bp->link_vars.ieee_fc &
2092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2093 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2094 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2098 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2099 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2103 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2104 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2108 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2114 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2116 if (!BP_NOMCP(bp)) {
2118 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2119 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2121 * Initialize link parameters structure variables
2122 * It is recommended to turn off RX FC for jumbo frames
2123 * for better performance
2125 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2126 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2128 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2130 bnx2x_acquire_phy_lock(bp);
2132 if (load_mode == LOAD_DIAG) {
2133 struct link_params *lp = &bp->link_params;
2134 lp->loopback_mode = LOOPBACK_XGXS;
2135 /* do PHY loopback at 10G speed, if possible */
2136 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2137 if (lp->speed_cap_mask[cfx_idx] &
2138 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2139 lp->req_line_speed[cfx_idx] =
2142 lp->req_line_speed[cfx_idx] =
2147 if (load_mode == LOAD_LOOPBACK_EXT) {
2148 struct link_params *lp = &bp->link_params;
2149 lp->loopback_mode = LOOPBACK_EXT;
2152 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2154 bnx2x_release_phy_lock(bp);
2156 bnx2x_calc_fc_adv(bp);
2158 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2159 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2160 bnx2x_link_report(bp);
2162 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2163 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2166 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2170 void bnx2x_link_set(struct bnx2x *bp)
2172 if (!BP_NOMCP(bp)) {
2173 bnx2x_acquire_phy_lock(bp);
2174 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2175 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2176 bnx2x_release_phy_lock(bp);
2178 bnx2x_calc_fc_adv(bp);
2180 BNX2X_ERR("Bootcode is missing - can not set link\n");
2183 static void bnx2x__link_reset(struct bnx2x *bp)
2185 if (!BP_NOMCP(bp)) {
2186 bnx2x_acquire_phy_lock(bp);
2187 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2188 bnx2x_release_phy_lock(bp);
2190 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2193 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2197 if (!BP_NOMCP(bp)) {
2198 bnx2x_acquire_phy_lock(bp);
2199 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2201 bnx2x_release_phy_lock(bp);
2203 BNX2X_ERR("Bootcode is missing - can not test link\n");
2209 /* Calculates the sum of vn_min_rates.
2210 It's needed for further normalizing of the min_rates.
2212 sum of vn_min_rates.
2214 0 - if all the min_rates are 0.
2215 In the later case fainess algorithm should be deactivated.
2216 If not all min_rates are zero then those that are zeroes will be set to 1.
2218 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2219 struct cmng_init_input *input)
2224 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2225 u32 vn_cfg = bp->mf_config[vn];
2226 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2227 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2229 /* Skip hidden vns */
2230 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2232 /* If min rate is zero - set it to 1 */
2233 else if (!vn_min_rate)
2234 vn_min_rate = DEF_MIN_RATE;
2238 input->vnic_min_rate[vn] = vn_min_rate;
2241 /* if ETS or all min rates are zeros - disable fairness */
2242 if (BNX2X_IS_ETS_ENABLED(bp)) {
2243 input->flags.cmng_enables &=
2244 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2245 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2246 } else if (all_zero) {
2247 input->flags.cmng_enables &=
2248 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2250 "All MIN values are zeroes fairness will be disabled\n");
2252 input->flags.cmng_enables |=
2253 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2256 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2257 struct cmng_init_input *input)
2260 u32 vn_cfg = bp->mf_config[vn];
2262 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2265 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2268 /* maxCfg in percents of linkspeed */
2269 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2270 } else /* SD modes */
2271 /* maxCfg is absolute in 100Mb units */
2272 vn_max_rate = maxCfg * 100;
2275 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2277 input->vnic_max_rate[vn] = vn_max_rate;
2281 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2283 if (CHIP_REV_IS_SLOW(bp))
2284 return CMNG_FNS_NONE;
2286 return CMNG_FNS_MINMAX;
2288 return CMNG_FNS_NONE;
2291 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2293 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2296 return; /* what should be the default bvalue in this case */
2298 /* For 2 port configuration the absolute function number formula
2300 * abs_func = 2 * vn + BP_PORT + BP_PATH
2302 * and there are 4 functions per port
2304 * For 4 port configuration it is
2305 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2307 * and there are 2 functions per port
2309 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2310 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2312 if (func >= E1H_FUNC_MAX)
2316 MF_CFG_RD(bp, func_mf_config[func].config);
2318 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2319 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2320 bp->flags |= MF_FUNC_DIS;
2322 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2323 bp->flags &= ~MF_FUNC_DIS;
2327 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2329 struct cmng_init_input input;
2330 memset(&input, 0, sizeof(struct cmng_init_input));
2332 input.port_rate = bp->link_vars.line_speed;
2334 if (cmng_type == CMNG_FNS_MINMAX) {
2337 /* read mf conf from shmem */
2339 bnx2x_read_mf_cfg(bp);
2341 /* vn_weight_sum and enable fairness if not 0 */
2342 bnx2x_calc_vn_min(bp, &input);
2344 /* calculate and set min-max rate for each vn */
2346 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2347 bnx2x_calc_vn_max(bp, vn, &input);
2349 /* always enable rate shaping and fairness */
2350 input.flags.cmng_enables |=
2351 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2353 bnx2x_init_cmng(&input, &bp->cmng);
2357 /* rate shaping and fairness are disabled */
2359 "rate shaping and fairness are disabled\n");
2362 static void storm_memset_cmng(struct bnx2x *bp,
2363 struct cmng_init *cmng,
2367 size_t size = sizeof(struct cmng_struct_per_port);
2369 u32 addr = BAR_XSTRORM_INTMEM +
2370 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2372 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2374 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2375 int func = func_by_vn(bp, vn);
2377 addr = BAR_XSTRORM_INTMEM +
2378 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2379 size = sizeof(struct rate_shaping_vars_per_vn);
2380 __storm_memset_struct(bp, addr, size,
2381 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2383 addr = BAR_XSTRORM_INTMEM +
2384 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2385 size = sizeof(struct fairness_vars_per_vn);
2386 __storm_memset_struct(bp, addr, size,
2387 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2391 /* This function is called upon link interrupt */
2392 static void bnx2x_link_attn(struct bnx2x *bp)
2394 /* Make sure that we are synced with the current statistics */
2395 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2397 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2399 if (bp->link_vars.link_up) {
2401 /* dropless flow control */
2402 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2403 int port = BP_PORT(bp);
2404 u32 pause_enabled = 0;
2406 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2409 REG_WR(bp, BAR_USTRORM_INTMEM +
2410 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2414 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2415 struct host_port_stats *pstats;
2417 pstats = bnx2x_sp(bp, port_stats);
2418 /* reset old mac stats */
2419 memset(&(pstats->mac_stx[0]), 0,
2420 sizeof(struct mac_stx));
2422 if (bp->state == BNX2X_STATE_OPEN)
2423 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2426 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2427 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2429 if (cmng_fns != CMNG_FNS_NONE) {
2430 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2431 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2433 /* rate shaping and fairness are disabled */
2435 "single function mode without fairness\n");
2438 __bnx2x_link_report(bp);
2441 bnx2x_link_sync_notify(bp);
2444 void bnx2x__link_status_update(struct bnx2x *bp)
2446 if (bp->state != BNX2X_STATE_OPEN)
2449 /* read updated dcb configuration */
2450 bnx2x_dcbx_pmf_update(bp);
2452 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2454 if (bp->link_vars.link_up)
2455 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2457 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2459 /* indicate link status */
2460 bnx2x_link_report(bp);
2463 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2464 u16 vlan_val, u8 allowed_prio)
2466 struct bnx2x_func_state_params func_params = {0};
2467 struct bnx2x_func_afex_update_params *f_update_params =
2468 &func_params.params.afex_update;
2470 func_params.f_obj = &bp->func_obj;
2471 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2473 /* no need to wait for RAMROD completion, so don't
2474 * set RAMROD_COMP_WAIT flag
2477 f_update_params->vif_id = vifid;
2478 f_update_params->afex_default_vlan = vlan_val;
2479 f_update_params->allowed_priorities = allowed_prio;
2481 /* if ramrod can not be sent, response to MCP immediately */
2482 if (bnx2x_func_state_change(bp, &func_params) < 0)
2483 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2488 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2489 u16 vif_index, u8 func_bit_map)
2491 struct bnx2x_func_state_params func_params = {0};
2492 struct bnx2x_func_afex_viflists_params *update_params =
2493 &func_params.params.afex_viflists;
2497 /* validate only LIST_SET and LIST_GET are received from switch */
2498 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2499 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2502 func_params.f_obj = &bp->func_obj;
2503 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2505 /* set parameters according to cmd_type */
2506 update_params->afex_vif_list_command = cmd_type;
2507 update_params->vif_list_index = cpu_to_le16(vif_index);
2508 update_params->func_bit_map =
2509 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2510 update_params->func_to_clear = 0;
2512 (cmd_type == VIF_LIST_RULE_GET) ?
2513 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2514 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2516 /* if ramrod can not be sent, respond to MCP immediately for
2517 * SET and GET requests (other are not triggered from MCP)
2519 rc = bnx2x_func_state_change(bp, &func_params);
2521 bnx2x_fw_command(bp, drv_msg_code, 0);
2526 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2528 struct afex_stats afex_stats;
2529 u32 func = BP_ABS_FUNC(bp);
2536 u32 addr_to_write, vifid, addrs, stats_type, i;
2538 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2539 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2541 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2542 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2545 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2546 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2547 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2549 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2551 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2555 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2556 addr_to_write = SHMEM2_RD(bp,
2557 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2558 stats_type = SHMEM2_RD(bp,
2559 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2562 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2565 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2567 /* write response to scratchpad, for MCP */
2568 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2569 REG_WR(bp, addr_to_write + i*sizeof(u32),
2570 *(((u32 *)(&afex_stats))+i));
2572 /* send ack message to MCP */
2573 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2576 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2577 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2578 bp->mf_config[BP_VN(bp)] = mf_config;
2580 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2583 /* if VIF_SET is "enabled" */
2584 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2585 /* set rate limit directly to internal RAM */
2586 struct cmng_init_input cmng_input;
2587 struct rate_shaping_vars_per_vn m_rs_vn;
2588 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2589 u32 addr = BAR_XSTRORM_INTMEM +
2590 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2592 bp->mf_config[BP_VN(bp)] = mf_config;
2594 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2595 m_rs_vn.vn_counter.rate =
2596 cmng_input.vnic_max_rate[BP_VN(bp)];
2597 m_rs_vn.vn_counter.quota =
2598 (m_rs_vn.vn_counter.rate *
2599 RS_PERIODIC_TIMEOUT_USEC) / 8;
2601 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2603 /* read relevant values from mf_cfg struct in shmem */
2605 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2606 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2607 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2609 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2610 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2611 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2612 vlan_prio = (mf_config &
2613 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2614 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2615 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2618 func_mf_config[func].afex_config) &
2619 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2620 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2623 func_mf_config[func].afex_config) &
2624 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2625 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2627 /* send ramrod to FW, return in case of failure */
2628 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2632 bp->afex_def_vlan_tag = vlan_val;
2633 bp->afex_vlan_mode = vlan_mode;
2635 /* notify link down because BP->flags is disabled */
2636 bnx2x_link_report(bp);
2638 /* send INVALID VIF ramrod to FW */
2639 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2641 /* Reset the default afex VLAN */
2642 bp->afex_def_vlan_tag = -1;
2647 static void bnx2x_pmf_update(struct bnx2x *bp)
2649 int port = BP_PORT(bp);
2653 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2656 * We need the mb() to ensure the ordering between the writing to
2657 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2661 /* queue a periodic task */
2662 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2664 bnx2x_dcbx_pmf_update(bp);
2666 /* enable nig attention */
2667 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2668 if (bp->common.int_block == INT_BLOCK_HC) {
2669 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2670 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2671 } else if (!CHIP_IS_E1x(bp)) {
2672 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2673 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2676 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2684 * General service functions
2687 /* send the MCP a request, block until there is a reply */
2688 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2690 int mb_idx = BP_FW_MB_IDX(bp);
2694 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2696 mutex_lock(&bp->fw_mb_mutex);
2698 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2699 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2701 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2702 (command | seq), param);
2705 /* let the FW do it's magic ... */
2708 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2710 /* Give the FW up to 5 second (500*10ms) */
2711 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2713 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2714 cnt*delay, rc, seq);
2716 /* is this a reply to our command? */
2717 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2718 rc &= FW_MSG_CODE_MASK;
2721 BNX2X_ERR("FW failed to respond!\n");
2725 mutex_unlock(&bp->fw_mb_mutex);
2731 static void storm_memset_func_cfg(struct bnx2x *bp,
2732 struct tstorm_eth_function_common_config *tcfg,
2735 size_t size = sizeof(struct tstorm_eth_function_common_config);
2737 u32 addr = BAR_TSTRORM_INTMEM +
2738 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2740 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2743 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2745 if (CHIP_IS_E1x(bp)) {
2746 struct tstorm_eth_function_common_config tcfg = {0};
2748 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2751 /* Enable the function in the FW */
2752 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2753 storm_memset_func_en(bp, p->func_id, 1);
2756 if (p->func_flgs & FUNC_FLG_SPQ) {
2757 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2758 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2759 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2764 * bnx2x_get_tx_only_flags - Return common flags
2768 * @zero_stats TRUE if statistics zeroing is needed
2770 * Return the flags that are common for the Tx-only and not normal connections.
2772 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2773 struct bnx2x_fastpath *fp,
2776 unsigned long flags = 0;
2778 /* PF driver will always initialize the Queue to an ACTIVE state */
2779 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2781 /* tx only connections collect statistics (on the same index as the
2782 * parent connection). The statistics are zeroed when the parent
2783 * connection is initialized.
2786 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2788 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2794 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2795 struct bnx2x_fastpath *fp,
2798 unsigned long flags = 0;
2800 /* calculate other queue flags */
2802 __set_bit(BNX2X_Q_FLG_OV, &flags);
2804 if (IS_FCOE_FP(fp)) {
2805 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2806 /* For FCoE - force usage of default priority (for afex) */
2807 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2810 if (!fp->disable_tpa) {
2811 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2812 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2813 if (fp->mode == TPA_MODE_GRO)
2814 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2818 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2819 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2822 /* Always set HW VLAN stripping */
2823 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2825 /* configure silent vlan removal */
2827 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2830 return flags | bnx2x_get_common_flags(bp, fp, true);
2833 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2834 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2837 gen_init->stat_id = bnx2x_stats_id(fp);
2838 gen_init->spcl_id = fp->cl_id;
2840 /* Always use mini-jumbo MTU for FCoE L2 ring */
2842 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2844 gen_init->mtu = bp->dev->mtu;
2846 gen_init->cos = cos;
2849 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2850 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2851 struct bnx2x_rxq_setup_params *rxq_init)
2855 u16 tpa_agg_size = 0;
2857 if (!fp->disable_tpa) {
2858 pause->sge_th_lo = SGE_TH_LO(bp);
2859 pause->sge_th_hi = SGE_TH_HI(bp);
2861 /* validate SGE ring has enough to cross high threshold */
2862 WARN_ON(bp->dropless_fc &&
2863 pause->sge_th_hi + FW_PREFETCH_CNT >
2864 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2866 tpa_agg_size = min_t(u32,
2867 (min_t(u32, 8, MAX_SKB_FRAGS) *
2868 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2869 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2871 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2872 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2873 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2877 /* pause - not for e1 */
2878 if (!CHIP_IS_E1(bp)) {
2879 pause->bd_th_lo = BD_TH_LO(bp);
2880 pause->bd_th_hi = BD_TH_HI(bp);
2882 pause->rcq_th_lo = RCQ_TH_LO(bp);
2883 pause->rcq_th_hi = RCQ_TH_HI(bp);
2885 * validate that rings have enough entries to cross
2888 WARN_ON(bp->dropless_fc &&
2889 pause->bd_th_hi + FW_PREFETCH_CNT >
2891 WARN_ON(bp->dropless_fc &&
2892 pause->rcq_th_hi + FW_PREFETCH_CNT >
2893 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2899 rxq_init->dscr_map = fp->rx_desc_mapping;
2900 rxq_init->sge_map = fp->rx_sge_mapping;
2901 rxq_init->rcq_map = fp->rx_comp_mapping;
2902 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2904 /* This should be a maximum number of data bytes that may be
2905 * placed on the BD (not including paddings).
2907 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2908 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2910 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2911 rxq_init->tpa_agg_sz = tpa_agg_size;
2912 rxq_init->sge_buf_sz = sge_sz;
2913 rxq_init->max_sges_pkt = max_sge;
2914 rxq_init->rss_engine_id = BP_FUNC(bp);
2915 rxq_init->mcast_engine_id = BP_FUNC(bp);
2917 /* Maximum number or simultaneous TPA aggregation for this Queue.
2919 * For PF Clients it should be the maximum avaliable number.
2920 * VF driver(s) may want to define it to a smaller value.
2922 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2924 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2925 rxq_init->fw_sb_id = fp->fw_sb_id;
2928 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2930 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2931 /* configure silent vlan removal
2932 * if multi function mode is afex, then mask default vlan
2934 if (IS_MF_AFEX(bp)) {
2935 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2936 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2940 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2941 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2944 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2945 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2946 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2947 txq_init->fw_sb_id = fp->fw_sb_id;
2950 * set the tss leading client id for TX classfication ==
2951 * leading RSS client id
2953 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2955 if (IS_FCOE_FP(fp)) {
2956 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2957 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2961 static void bnx2x_pf_init(struct bnx2x *bp)
2963 struct bnx2x_func_init_params func_init = {0};
2964 struct event_ring_data eq_data = { {0} };
2967 if (!CHIP_IS_E1x(bp)) {
2968 /* reset IGU PF statistics: MSIX + ATTN */
2970 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2971 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2972 (CHIP_MODE_IS_4_PORT(bp) ?
2973 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2975 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2976 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2977 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2978 (CHIP_MODE_IS_4_PORT(bp) ?
2979 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2982 /* function setup flags */
2983 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2985 /* This flag is relevant for E1x only.
2986 * E2 doesn't have a TPA configuration in a function level.
2988 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2990 func_init.func_flgs = flags;
2991 func_init.pf_id = BP_FUNC(bp);
2992 func_init.func_id = BP_FUNC(bp);
2993 func_init.spq_map = bp->spq_mapping;
2994 func_init.spq_prod = bp->spq_prod_idx;
2996 bnx2x_func_init(bp, &func_init);
2998 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3001 * Congestion management values depend on the link rate
3002 * There is no active link so initial link rate is set to 10 Gbps.
3003 * When the link comes up The congestion management values are
3004 * re-calculated according to the actual link rate.
3006 bp->link_vars.line_speed = SPEED_10000;
3007 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3009 /* Only the PMF sets the HW */
3011 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3013 /* init Event Queue */
3014 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3015 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3016 eq_data.producer = bp->eq_prod;
3017 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3018 eq_data.sb_id = DEF_SB_ID;
3019 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3023 static void bnx2x_e1h_disable(struct bnx2x *bp)
3025 int port = BP_PORT(bp);
3027 bnx2x_tx_disable(bp);
3029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3032 static void bnx2x_e1h_enable(struct bnx2x *bp)
3034 int port = BP_PORT(bp);
3036 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3038 /* Tx queue should be only reenabled */
3039 netif_tx_wake_all_queues(bp->dev);
3042 * Should not call netif_carrier_on since it will be called if the link
3043 * is up when checking for link state
3047 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3049 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3051 struct eth_stats_info *ether_stat =
3052 &bp->slowpath->drv_info_to_mcp.ether_stat;
3054 /* leave last char as NULL */
3055 memcpy(ether_stat->version, DRV_MODULE_VERSION,
3056 ETH_STAT_INFO_VERSION_LEN - 1);
3058 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3059 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3060 ether_stat->mac_local);
3062 ether_stat->mtu_size = bp->dev->mtu;
3064 if (bp->dev->features & NETIF_F_RXCSUM)
3065 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3066 if (bp->dev->features & NETIF_F_TSO)
3067 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3068 ether_stat->feature_flags |= bp->common.boot_mode;
3070 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3072 ether_stat->txq_size = bp->tx_ring_size;
3073 ether_stat->rxq_size = bp->rx_ring_size;
3076 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3079 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3080 struct fcoe_stats_info *fcoe_stat =
3081 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3083 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3084 bp->fip_mac, ETH_ALEN);
3086 fcoe_stat->qos_priority =
3087 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3089 /* insert FCoE stats from ramrod response */
3091 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3092 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3093 tstorm_queue_statistics;
3095 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3096 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3097 xstorm_queue_statistics;
3099 struct fcoe_statistics_params *fw_fcoe_stat =
3100 &bp->fw_stats_data->fcoe;
3102 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3103 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3105 ADD_64(fcoe_stat->rx_bytes_hi,
3106 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3107 fcoe_stat->rx_bytes_lo,
3108 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3110 ADD_64(fcoe_stat->rx_bytes_hi,
3111 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3112 fcoe_stat->rx_bytes_lo,
3113 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3115 ADD_64(fcoe_stat->rx_bytes_hi,
3116 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3117 fcoe_stat->rx_bytes_lo,
3118 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3120 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3121 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3123 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3124 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3126 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3129 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3132 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3133 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3135 ADD_64(fcoe_stat->tx_bytes_hi,
3136 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3137 fcoe_stat->tx_bytes_lo,
3138 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3140 ADD_64(fcoe_stat->tx_bytes_hi,
3141 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3142 fcoe_stat->tx_bytes_lo,
3143 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3145 ADD_64(fcoe_stat->tx_bytes_hi,
3146 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3147 fcoe_stat->tx_bytes_lo,
3148 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3150 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3151 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3153 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3154 fcoe_q_xstorm_stats->ucast_pkts_sent);
3156 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157 fcoe_q_xstorm_stats->bcast_pkts_sent);
3159 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160 fcoe_q_xstorm_stats->mcast_pkts_sent);
3163 /* ask L5 driver to add data to the struct */
3164 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3168 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3171 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3172 struct iscsi_stats_info *iscsi_stat =
3173 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3175 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3176 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3178 iscsi_stat->qos_priority =
3179 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3181 /* ask L5 driver to add data to the struct */
3182 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3186 /* called due to MCP event (on pmf):
3187 * reread new bandwidth configuration
3189 * notify others function about the change
3191 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3193 if (bp->link_vars.link_up) {
3194 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3195 bnx2x_link_sync_notify(bp);
3197 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3200 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3202 bnx2x_config_mf_bw(bp);
3203 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3206 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3208 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3209 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3212 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3214 enum drv_info_opcode op_code;
3215 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3217 /* if drv_info version supported by MFW doesn't match - send NACK */
3218 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3219 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3223 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3224 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3226 memset(&bp->slowpath->drv_info_to_mcp, 0,
3227 sizeof(union drv_info_to_mcp));
3230 case ETH_STATS_OPCODE:
3231 bnx2x_drv_info_ether_stat(bp);
3233 case FCOE_STATS_OPCODE:
3234 bnx2x_drv_info_fcoe_stat(bp);
3236 case ISCSI_STATS_OPCODE:
3237 bnx2x_drv_info_iscsi_stat(bp);
3240 /* if op code isn't supported - send NACK */
3241 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3245 /* if we got drv_info attn from MFW then these fields are defined in
3248 SHMEM2_WR(bp, drv_info_host_addr_lo,
3249 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3250 SHMEM2_WR(bp, drv_info_host_addr_hi,
3251 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3253 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3256 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3258 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3260 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3263 * This is the only place besides the function initialization
3264 * where the bp->flags can change so it is done without any
3267 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3268 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3269 bp->flags |= MF_FUNC_DIS;
3271 bnx2x_e1h_disable(bp);
3273 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3274 bp->flags &= ~MF_FUNC_DIS;
3276 bnx2x_e1h_enable(bp);
3278 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3280 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3281 bnx2x_config_mf_bw(bp);
3282 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3285 /* Report results to MCP */
3287 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3289 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3292 /* must be called under the spq lock */
3293 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3295 struct eth_spe *next_spe = bp->spq_prod_bd;
3297 if (bp->spq_prod_bd == bp->spq_last_bd) {
3298 bp->spq_prod_bd = bp->spq;
3299 bp->spq_prod_idx = 0;
3300 DP(BNX2X_MSG_SP, "end of spq\n");
3308 /* must be called under the spq lock */
3309 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3311 int func = BP_FUNC(bp);
3314 * Make sure that BD data is updated before writing the producer:
3315 * BD data is written to the memory, the producer is read from the
3316 * memory, thus we need a full memory barrier to ensure the ordering.
3320 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3326 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3328 * @cmd: command to check
3329 * @cmd_type: command type
3331 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3333 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3334 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3335 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3336 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3337 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3338 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3339 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3348 * bnx2x_sp_post - place a single command on an SP ring
3350 * @bp: driver handle
3351 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3352 * @cid: SW CID the command is related to
3353 * @data_hi: command private data address (high 32 bits)
3354 * @data_lo: command private data address (low 32 bits)
3355 * @cmd_type: command type (e.g. NONE, ETH)
3357 * SP data is handled as if it's always an address pair, thus data fields are
3358 * not swapped to little endian in upper functions. Instead this function swaps
3359 * data as if it's two u32 fields.
3361 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3362 u32 data_hi, u32 data_lo, int cmd_type)
3364 struct eth_spe *spe;
3366 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3368 #ifdef BNX2X_STOP_ON_ERROR
3369 if (unlikely(bp->panic)) {
3370 BNX2X_ERR("Can't post SP when there is panic\n");
3375 spin_lock_bh(&bp->spq_lock);
3378 if (!atomic_read(&bp->eq_spq_left)) {
3379 BNX2X_ERR("BUG! EQ ring full!\n");
3380 spin_unlock_bh(&bp->spq_lock);
3384 } else if (!atomic_read(&bp->cq_spq_left)) {
3385 BNX2X_ERR("BUG! SPQ ring full!\n");
3386 spin_unlock_bh(&bp->spq_lock);
3391 spe = bnx2x_sp_get_next(bp);
3393 /* CID needs port number to be encoded int it */
3394 spe->hdr.conn_and_cmd_data =
3395 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3398 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3400 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3401 SPE_HDR_FUNCTION_ID);
3403 spe->hdr.type = cpu_to_le16(type);
3405 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3406 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3409 * It's ok if the actual decrement is issued towards the memory
3410 * somewhere between the spin_lock and spin_unlock. Thus no
3411 * more explict memory barrier is needed.
3414 atomic_dec(&bp->eq_spq_left);
3416 atomic_dec(&bp->cq_spq_left);
3420 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3421 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3422 (u32)(U64_LO(bp->spq_mapping) +
3423 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3424 HW_CID(bp, cid), data_hi, data_lo, type,
3425 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3427 bnx2x_sp_prod_update(bp);
3428 spin_unlock_bh(&bp->spq_lock);
3432 /* acquire split MCP access lock register */
3433 static int bnx2x_acquire_alr(struct bnx2x *bp)
3439 for (j = 0; j < 1000; j++) {
3441 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3442 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3443 if (val & (1L << 31))
3448 if (!(val & (1L << 31))) {
3449 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3456 /* release split MCP access lock register */
3457 static void bnx2x_release_alr(struct bnx2x *bp)
3459 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3462 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3463 #define BNX2X_DEF_SB_IDX 0x0002
3465 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3467 struct host_sp_status_block *def_sb = bp->def_status_blk;
3470 barrier(); /* status block is written to by the chip */
3471 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3472 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3473 rc |= BNX2X_DEF_SB_ATT_IDX;
3476 if (bp->def_idx != def_sb->sp_sb.running_index) {
3477 bp->def_idx = def_sb->sp_sb.running_index;
3478 rc |= BNX2X_DEF_SB_IDX;
3481 /* Do not reorder: indecies reading should complete before handling */
3487 * slow path service functions
3490 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3492 int port = BP_PORT(bp);
3493 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3494 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3495 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3496 NIG_REG_MASK_INTERRUPT_PORT0;
3501 if (bp->attn_state & asserted)
3502 BNX2X_ERR("IGU ERROR\n");
3504 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3505 aeu_mask = REG_RD(bp, aeu_addr);
3507 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3508 aeu_mask, asserted);
3509 aeu_mask &= ~(asserted & 0x3ff);
3510 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3512 REG_WR(bp, aeu_addr, aeu_mask);
3513 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3515 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3516 bp->attn_state |= asserted;
3517 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3519 if (asserted & ATTN_HARD_WIRED_MASK) {
3520 if (asserted & ATTN_NIG_FOR_FUNC) {
3522 bnx2x_acquire_phy_lock(bp);
3524 /* save nig interrupt mask */
3525 nig_mask = REG_RD(bp, nig_int_mask_addr);
3527 /* If nig_mask is not set, no need to call the update
3531 REG_WR(bp, nig_int_mask_addr, 0);
3533 bnx2x_link_attn(bp);
3536 /* handle unicore attn? */
3538 if (asserted & ATTN_SW_TIMER_4_FUNC)
3539 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3541 if (asserted & GPIO_2_FUNC)
3542 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3544 if (asserted & GPIO_3_FUNC)
3545 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3547 if (asserted & GPIO_4_FUNC)
3548 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3551 if (asserted & ATTN_GENERAL_ATTN_1) {
3552 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3553 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3555 if (asserted & ATTN_GENERAL_ATTN_2) {
3556 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3557 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3559 if (asserted & ATTN_GENERAL_ATTN_3) {
3560 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3561 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3564 if (asserted & ATTN_GENERAL_ATTN_4) {
3565 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3566 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3568 if (asserted & ATTN_GENERAL_ATTN_5) {
3569 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3570 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3572 if (asserted & ATTN_GENERAL_ATTN_6) {
3573 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3574 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3578 } /* if hardwired */
3580 if (bp->common.int_block == INT_BLOCK_HC)
3581 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3582 COMMAND_REG_ATTN_BITS_SET);
3584 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3586 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3587 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3588 REG_WR(bp, reg_addr, asserted);
3590 /* now set back the mask */
3591 if (asserted & ATTN_NIG_FOR_FUNC) {
3592 REG_WR(bp, nig_int_mask_addr, nig_mask);
3593 bnx2x_release_phy_lock(bp);
3597 static void bnx2x_fan_failure(struct bnx2x *bp)
3599 int port = BP_PORT(bp);
3601 /* mark the failure */
3604 dev_info.port_hw_config[port].external_phy_config);
3606 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3607 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3608 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3611 /* log the failure */
3612 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3613 "Please contact OEM Support for assistance\n");
3616 * Scheudle device reset (unload)
3617 * This is due to some boards consuming sufficient power when driver is
3618 * up to overheat if fan fails.
3620 smp_mb__before_clear_bit();
3621 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3622 smp_mb__after_clear_bit();
3623 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3627 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3629 int port = BP_PORT(bp);
3633 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3634 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3636 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3638 val = REG_RD(bp, reg_offset);
3639 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3640 REG_WR(bp, reg_offset, val);
3642 BNX2X_ERR("SPIO5 hw attention\n");
3644 /* Fan failure attention */
3645 bnx2x_hw_reset_phy(&bp->link_params);
3646 bnx2x_fan_failure(bp);
3649 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3650 bnx2x_acquire_phy_lock(bp);
3651 bnx2x_handle_module_detect_int(&bp->link_params);
3652 bnx2x_release_phy_lock(bp);
3655 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3657 val = REG_RD(bp, reg_offset);
3658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3659 REG_WR(bp, reg_offset, val);
3661 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3662 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3667 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3671 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3673 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3674 BNX2X_ERR("DB hw attention 0x%x\n", val);
3675 /* DORQ discard attention */
3677 BNX2X_ERR("FATAL error from DORQ\n");
3680 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3682 int port = BP_PORT(bp);
3685 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3686 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3688 val = REG_RD(bp, reg_offset);
3689 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3690 REG_WR(bp, reg_offset, val);
3692 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3693 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3698 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3702 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3704 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3705 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3706 /* CFC error attention */
3708 BNX2X_ERR("FATAL error from CFC\n");
3711 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3712 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3713 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3714 /* RQ_USDMDP_FIFO_OVERFLOW */
3716 BNX2X_ERR("FATAL error from PXP\n");
3718 if (!CHIP_IS_E1x(bp)) {
3719 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3720 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3724 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3726 int port = BP_PORT(bp);
3729 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3730 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3732 val = REG_RD(bp, reg_offset);
3733 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3734 REG_WR(bp, reg_offset, val);
3736 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3737 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3742 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3746 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3748 if (attn & BNX2X_PMF_LINK_ASSERT) {
3749 int func = BP_FUNC(bp);
3751 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3752 bnx2x_read_mf_cfg(bp);
3753 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3754 func_mf_config[BP_ABS_FUNC(bp)].config);
3756 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3757 if (val & DRV_STATUS_DCC_EVENT_MASK)
3759 (val & DRV_STATUS_DCC_EVENT_MASK));
3761 if (val & DRV_STATUS_SET_MF_BW)
3762 bnx2x_set_mf_bw(bp);
3764 if (val & DRV_STATUS_DRV_INFO_REQ)
3765 bnx2x_handle_drv_info_req(bp);
3766 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3767 bnx2x_pmf_update(bp);
3770 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3771 bp->dcbx_enabled > 0)
3772 /* start dcbx state machine */
3773 bnx2x_dcbx_set_params(bp,
3774 BNX2X_DCBX_STATE_NEG_RECEIVED);
3775 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3776 bnx2x_handle_afex_cmd(bp,
3777 val & DRV_STATUS_AFEX_EVENT_MASK);
3778 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3779 bnx2x_handle_eee_event(bp);
3780 if (bp->link_vars.periodic_flags &
3781 PERIODIC_FLAGS_LINK_EVENT) {
3782 /* sync with link */
3783 bnx2x_acquire_phy_lock(bp);
3784 bp->link_vars.periodic_flags &=
3785 ~PERIODIC_FLAGS_LINK_EVENT;
3786 bnx2x_release_phy_lock(bp);
3788 bnx2x_link_sync_notify(bp);
3789 bnx2x_link_report(bp);
3791 /* Always call it here: bnx2x_link_report() will
3792 * prevent the link indication duplication.
3794 bnx2x__link_status_update(bp);
3795 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3797 BNX2X_ERR("MC assert!\n");
3798 bnx2x_mc_assert(bp);
3799 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3800 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3801 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3802 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3805 } else if (attn & BNX2X_MCP_ASSERT) {
3807 BNX2X_ERR("MCP assert!\n");
3808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3812 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3815 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3816 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3817 if (attn & BNX2X_GRC_TIMEOUT) {
3818 val = CHIP_IS_E1(bp) ? 0 :
3819 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3820 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3822 if (attn & BNX2X_GRC_RSV) {
3823 val = CHIP_IS_E1(bp) ? 0 :
3824 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3825 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3827 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3833 * 0-7 - Engine0 load counter.
3834 * 8-15 - Engine1 load counter.
3835 * 16 - Engine0 RESET_IN_PROGRESS bit.
3836 * 17 - Engine1 RESET_IN_PROGRESS bit.
3837 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3839 * 19 - Engine1 ONE_IS_LOADED.
3840 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3841 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3842 * just the one belonging to its engine).
3845 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3847 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3848 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3849 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3850 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3851 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3852 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3853 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3856 * Set the GLOBAL_RESET bit.
3858 * Should be run under rtnl lock
3860 void bnx2x_set_reset_global(struct bnx2x *bp)
3863 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3864 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3865 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3866 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3870 * Clear the GLOBAL_RESET bit.
3872 * Should be run under rtnl lock
3874 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3877 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3878 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3879 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3880 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3884 * Checks the GLOBAL_RESET bit.
3886 * should be run under rtnl lock
3888 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3890 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3892 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3893 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3897 * Clear RESET_IN_PROGRESS bit for the current engine.
3899 * Should be run under rtnl lock
3901 static void bnx2x_set_reset_done(struct bnx2x *bp)
3904 u32 bit = BP_PATH(bp) ?
3905 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3907 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3911 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3913 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3917 * Set RESET_IN_PROGRESS for the current engine.
3919 * should be run under rtnl lock
3921 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3924 u32 bit = BP_PATH(bp) ?
3925 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3926 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3927 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3931 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3932 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3936 * Checks the RESET_IN_PROGRESS bit for the given engine.
3937 * should be run under rtnl lock
3939 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3941 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3943 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3945 /* return false if bit is set */
3946 return (val & bit) ? false : true;
3950 * set pf load for the current pf.
3952 * should be run under rtnl lock
3954 void bnx2x_set_pf_load(struct bnx2x *bp)
3957 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3958 BNX2X_PATH0_LOAD_CNT_MASK;
3959 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3960 BNX2X_PATH0_LOAD_CNT_SHIFT;
3962 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3963 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3965 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3967 /* get the current counter value */
3968 val1 = (val & mask) >> shift;
3970 /* set bit of that PF */
3971 val1 |= (1 << bp->pf_num);
3973 /* clear the old value */
3976 /* set the new one */
3977 val |= ((val1 << shift) & mask);
3979 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3980 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3984 * bnx2x_clear_pf_load - clear pf load mark
3986 * @bp: driver handle
3988 * Should be run under rtnl lock.
3989 * Decrements the load counter for the current engine. Returns
3990 * whether other functions are still loaded
3992 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3995 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3996 BNX2X_PATH0_LOAD_CNT_MASK;
3997 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3998 BNX2X_PATH0_LOAD_CNT_SHIFT;
4000 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4001 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4002 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4004 /* get the current counter value */
4005 val1 = (val & mask) >> shift;
4007 /* clear bit of that PF */
4008 val1 &= ~(1 << bp->pf_num);
4010 /* clear the old value */
4013 /* set the new one */
4014 val |= ((val1 << shift) & mask);
4016 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4022 * Read the load status for the current engine.
4024 * should be run under rtnl lock
4026 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4028 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4029 BNX2X_PATH0_LOAD_CNT_MASK);
4030 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4031 BNX2X_PATH0_LOAD_CNT_SHIFT);
4032 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4034 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4036 val = (val & mask) >> shift;
4038 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4044 static void _print_next_block(int idx, const char *blk)
4046 pr_cont("%s%s", idx ? ", " : "", blk);
4049 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4054 for (i = 0; sig; i++) {
4055 cur_bit = ((u32)0x1 << i);
4056 if (sig & cur_bit) {
4058 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4060 _print_next_block(par_num++, "BRB");
4062 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4064 _print_next_block(par_num++, "PARSER");
4066 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4068 _print_next_block(par_num++, "TSDM");
4070 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4072 _print_next_block(par_num++,
4075 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4077 _print_next_block(par_num++, "TCM");
4079 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4081 _print_next_block(par_num++, "TSEMI");
4083 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4085 _print_next_block(par_num++, "XPB");
4097 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4098 bool *global, bool print)
4102 for (i = 0; sig; i++) {
4103 cur_bit = ((u32)0x1 << i);
4104 if (sig & cur_bit) {
4106 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4108 _print_next_block(par_num++, "PBF");
4110 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4112 _print_next_block(par_num++, "QM");
4114 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4116 _print_next_block(par_num++, "TM");
4118 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4120 _print_next_block(par_num++, "XSDM");
4122 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4124 _print_next_block(par_num++, "XCM");
4126 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4128 _print_next_block(par_num++, "XSEMI");
4130 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4132 _print_next_block(par_num++,
4135 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4137 _print_next_block(par_num++, "NIG");
4139 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4141 _print_next_block(par_num++,
4145 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4147 _print_next_block(par_num++, "DEBUG");
4149 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4151 _print_next_block(par_num++, "USDM");
4153 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4155 _print_next_block(par_num++, "UCM");
4157 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4159 _print_next_block(par_num++, "USEMI");
4161 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4163 _print_next_block(par_num++, "UPB");
4165 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4167 _print_next_block(par_num++, "CSDM");
4169 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4171 _print_next_block(par_num++, "CCM");
4183 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4188 for (i = 0; sig; i++) {
4189 cur_bit = ((u32)0x1 << i);
4190 if (sig & cur_bit) {
4192 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4194 _print_next_block(par_num++, "CSEMI");
4196 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4198 _print_next_block(par_num++, "PXP");
4200 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4202 _print_next_block(par_num++,
4203 "PXPPCICLOCKCLIENT");
4205 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4207 _print_next_block(par_num++, "CFC");
4209 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4211 _print_next_block(par_num++, "CDU");
4213 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4215 _print_next_block(par_num++, "DMAE");
4217 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4219 _print_next_block(par_num++, "IGU");
4221 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4223 _print_next_block(par_num++, "MISC");
4235 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4236 bool *global, bool print)
4240 for (i = 0; sig; i++) {
4241 cur_bit = ((u32)0x1 << i);
4242 if (sig & cur_bit) {
4244 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4246 _print_next_block(par_num++, "MCP ROM");
4249 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4251 _print_next_block(par_num++,
4255 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4257 _print_next_block(par_num++,
4261 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4263 _print_next_block(par_num++,
4277 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4282 for (i = 0; sig; i++) {
4283 cur_bit = ((u32)0x1 << i);
4284 if (sig & cur_bit) {
4286 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4288 _print_next_block(par_num++, "PGLUE_B");
4290 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4292 _print_next_block(par_num++, "ATC");
4304 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4307 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4308 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4309 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4310 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4311 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4313 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4314 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4315 sig[0] & HW_PRTY_ASSERT_SET_0,
4316 sig[1] & HW_PRTY_ASSERT_SET_1,
4317 sig[2] & HW_PRTY_ASSERT_SET_2,
4318 sig[3] & HW_PRTY_ASSERT_SET_3,
4319 sig[4] & HW_PRTY_ASSERT_SET_4);
4322 "Parity errors detected in blocks: ");
4323 par_num = bnx2x_check_blocks_with_parity0(
4324 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4325 par_num = bnx2x_check_blocks_with_parity1(
4326 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4327 par_num = bnx2x_check_blocks_with_parity2(
4328 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4329 par_num = bnx2x_check_blocks_with_parity3(
4330 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4331 par_num = bnx2x_check_blocks_with_parity4(
4332 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4343 * bnx2x_chk_parity_attn - checks for parity attentions.
4345 * @bp: driver handle
4346 * @global: true if there was a global attention
4347 * @print: show parity attention in syslog
4349 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4351 struct attn_route attn = { {0} };
4352 int port = BP_PORT(bp);
4354 attn.sig[0] = REG_RD(bp,
4355 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4357 attn.sig[1] = REG_RD(bp,
4358 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4360 attn.sig[2] = REG_RD(bp,
4361 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4363 attn.sig[3] = REG_RD(bp,
4364 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4367 if (!CHIP_IS_E1x(bp))
4368 attn.sig[4] = REG_RD(bp,
4369 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4372 return bnx2x_parity_attn(bp, global, print, attn.sig);
4376 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4379 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4381 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4382 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4383 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4384 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4385 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4386 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4387 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4388 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4389 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4390 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4392 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4393 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4395 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4396 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4397 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4398 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4399 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4400 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4401 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4402 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4404 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4405 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4406 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4407 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4408 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4409 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4410 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4411 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4412 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4413 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4414 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4415 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4416 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4417 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4418 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4421 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4422 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4423 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4424 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4425 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4430 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4432 struct attn_route attn, *group_mask;
4433 int port = BP_PORT(bp);
4438 bool global = false;
4440 /* need to take HW lock because MCP or other port might also
4441 try to handle this event */
4442 bnx2x_acquire_alr(bp);
4444 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4445 #ifndef BNX2X_STOP_ON_ERROR
4446 bp->recovery_state = BNX2X_RECOVERY_INIT;
4447 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4448 /* Disable HW interrupts */
4449 bnx2x_int_disable(bp);
4450 /* In case of parity errors don't handle attentions so that
4451 * other function would "see" parity errors.
4456 bnx2x_release_alr(bp);
4460 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4461 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4462 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4463 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4464 if (!CHIP_IS_E1x(bp))
4466 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4470 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4471 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4473 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4474 if (deasserted & (1 << index)) {
4475 group_mask = &bp->attn_group[index];
4477 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4479 group_mask->sig[0], group_mask->sig[1],
4480 group_mask->sig[2], group_mask->sig[3],
4481 group_mask->sig[4]);
4483 bnx2x_attn_int_deasserted4(bp,
4484 attn.sig[4] & group_mask->sig[4]);
4485 bnx2x_attn_int_deasserted3(bp,
4486 attn.sig[3] & group_mask->sig[3]);
4487 bnx2x_attn_int_deasserted1(bp,
4488 attn.sig[1] & group_mask->sig[1]);
4489 bnx2x_attn_int_deasserted2(bp,
4490 attn.sig[2] & group_mask->sig[2]);
4491 bnx2x_attn_int_deasserted0(bp,
4492 attn.sig[0] & group_mask->sig[0]);
4496 bnx2x_release_alr(bp);
4498 if (bp->common.int_block == INT_BLOCK_HC)
4499 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4500 COMMAND_REG_ATTN_BITS_CLR);
4502 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4505 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4506 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4507 REG_WR(bp, reg_addr, val);
4509 if (~bp->attn_state & deasserted)
4510 BNX2X_ERR("IGU ERROR\n");
4512 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4513 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4515 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4516 aeu_mask = REG_RD(bp, reg_addr);
4518 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4519 aeu_mask, deasserted);
4520 aeu_mask |= (deasserted & 0x3ff);
4521 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4523 REG_WR(bp, reg_addr, aeu_mask);
4524 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4526 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4527 bp->attn_state &= ~deasserted;
4528 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4531 static void bnx2x_attn_int(struct bnx2x *bp)
4533 /* read local copy of bits */
4534 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4536 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4538 u32 attn_state = bp->attn_state;
4540 /* look for changed bits */
4541 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4542 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4545 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4546 attn_bits, attn_ack, asserted, deasserted);
4548 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4549 BNX2X_ERR("BAD attention state\n");
4551 /* handle bits that were raised */
4553 bnx2x_attn_int_asserted(bp, asserted);
4556 bnx2x_attn_int_deasserted(bp, deasserted);
4559 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4560 u16 index, u8 op, u8 update)
4562 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4564 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4568 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4570 /* No memory barriers */
4571 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4572 mmiowb(); /* keep prod updates ordered */
4576 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4577 union event_ring_elem *elem)
4579 u8 err = elem->message.error;
4581 if (!bp->cnic_eth_dev.starting_cid ||
4582 (cid < bp->cnic_eth_dev.starting_cid &&
4583 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4586 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4588 if (unlikely(err)) {
4590 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4592 bnx2x_panic_dump(bp);
4594 bnx2x_cnic_cfc_comp(bp, cid, err);
4599 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4601 struct bnx2x_mcast_ramrod_params rparam;
4604 memset(&rparam, 0, sizeof(rparam));
4606 rparam.mcast_obj = &bp->mcast_obj;
4608 netif_addr_lock_bh(bp->dev);
4610 /* Clear pending state for the last command */
4611 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4613 /* If there are pending mcast commands - send them */
4614 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4615 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4617 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4621 netif_addr_unlock_bh(bp->dev);
4624 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4625 union event_ring_elem *elem)
4627 unsigned long ramrod_flags = 0;
4629 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4630 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4632 /* Always push next commands out, don't wait here */
4633 __set_bit(RAMROD_CONT, &ramrod_flags);
4635 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4636 case BNX2X_FILTER_MAC_PENDING:
4637 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4639 if (cid == BNX2X_ISCSI_ETH_CID(bp))
4640 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4643 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4646 case BNX2X_FILTER_MCAST_PENDING:
4647 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4648 /* This is only relevant for 57710 where multicast MACs are
4649 * configured as unicast MACs using the same ramrod.
4651 bnx2x_handle_mcast_eqe(bp);
4654 BNX2X_ERR("Unsupported classification command: %d\n",
4655 elem->message.data.eth_event.echo);
4659 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4662 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4664 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4669 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4672 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4674 netif_addr_lock_bh(bp->dev);
4676 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4678 /* Send rx_mode command again if was requested */
4679 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4680 bnx2x_set_storm_rx_mode(bp);
4682 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4684 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4685 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4687 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4690 netif_addr_unlock_bh(bp->dev);
4693 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4694 union event_ring_elem *elem)
4696 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4698 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4699 elem->message.data.vif_list_event.func_bit_map);
4700 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4701 elem->message.data.vif_list_event.func_bit_map);
4702 } else if (elem->message.data.vif_list_event.echo ==
4703 VIF_LIST_RULE_SET) {
4704 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4705 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4709 /* called with rtnl_lock */
4710 static void bnx2x_after_function_update(struct bnx2x *bp)
4713 struct bnx2x_fastpath *fp;
4714 struct bnx2x_queue_state_params queue_params = {NULL};
4715 struct bnx2x_queue_update_params *q_update_params =
4716 &queue_params.params.update;
4718 /* Send Q update command with afex vlan removal values for all Qs */
4719 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4721 /* set silent vlan removal values according to vlan mode */
4722 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4723 &q_update_params->update_flags);
4724 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4725 &q_update_params->update_flags);
4726 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4728 /* in access mode mark mask and value are 0 to strip all vlans */
4729 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4730 q_update_params->silent_removal_value = 0;
4731 q_update_params->silent_removal_mask = 0;
4733 q_update_params->silent_removal_value =
4734 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4735 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4738 for_each_eth_queue(bp, q) {
4739 /* Set the appropriate Queue object */
4741 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4743 /* send the ramrod */
4744 rc = bnx2x_queue_state_change(bp, &queue_params);
4746 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4752 fp = &bp->fp[FCOE_IDX(bp)];
4753 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4755 /* clear pending completion bit */
4756 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4758 /* mark latest Q bit */
4759 smp_mb__before_clear_bit();
4760 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4761 smp_mb__after_clear_bit();
4763 /* send Q update ramrod for FCoE Q */
4764 rc = bnx2x_queue_state_change(bp, &queue_params);
4766 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4769 /* If no FCoE ring - ACK MCP now */
4770 bnx2x_link_report(bp);
4771 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4774 /* If no FCoE ring - ACK MCP now */
4775 bnx2x_link_report(bp);
4776 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4777 #endif /* BCM_CNIC */
4780 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4781 struct bnx2x *bp, u32 cid)
4783 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4785 if (cid == BNX2X_FCOE_ETH_CID(bp))
4786 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4789 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4792 static void bnx2x_eq_int(struct bnx2x *bp)
4794 u16 hw_cons, sw_cons, sw_prod;
4795 union event_ring_elem *elem;
4799 struct bnx2x_queue_sp_obj *q_obj;
4800 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4801 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4803 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4805 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4806 * when we get the the next-page we nned to adjust so the loop
4807 * condition below will be met. The next element is the size of a
4808 * regular element and hence incrementing by 1
4810 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4813 /* This function may never run in parallel with itself for a
4814 * specific bp, thus there is no need in "paired" read memory
4817 sw_cons = bp->eq_cons;
4818 sw_prod = bp->eq_prod;
4820 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4821 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4823 for (; sw_cons != hw_cons;
4824 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4827 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4829 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4830 opcode = elem->message.opcode;
4833 /* handle eq element */
4835 case EVENT_RING_OPCODE_STAT_QUERY:
4836 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4837 "got statistics comp event %d\n",
4839 /* nothing to do with stats comp */
4842 case EVENT_RING_OPCODE_CFC_DEL:
4843 /* handle according to cid range */
4845 * we may want to verify here that the bp state is
4849 "got delete ramrod for MULTI[%d]\n", cid);
4851 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4854 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4856 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4863 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4864 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4865 if (f_obj->complete_cmd(bp, f_obj,
4866 BNX2X_F_CMD_TX_STOP))
4868 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4871 case EVENT_RING_OPCODE_START_TRAFFIC:
4872 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4873 if (f_obj->complete_cmd(bp, f_obj,
4874 BNX2X_F_CMD_TX_START))
4876 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4878 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4879 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4880 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4881 f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4883 /* We will perform the Queues update from sp_rtnl task
4884 * as all Queue SP operations should run under
4887 smp_mb__before_clear_bit();
4888 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4889 &bp->sp_rtnl_state);
4890 smp_mb__after_clear_bit();
4892 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4895 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4896 f_obj->complete_cmd(bp, f_obj,
4897 BNX2X_F_CMD_AFEX_VIFLISTS);
4898 bnx2x_after_afex_vif_lists(bp, elem);
4900 case EVENT_RING_OPCODE_FUNCTION_START:
4901 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4902 "got FUNC_START ramrod\n");
4903 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4908 case EVENT_RING_OPCODE_FUNCTION_STOP:
4909 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4910 "got FUNC_STOP ramrod\n");
4911 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4917 switch (opcode | bp->state) {
4918 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4920 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4921 BNX2X_STATE_OPENING_WAIT4_PORT):
4922 cid = elem->message.data.eth_event.echo &
4924 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4926 rss_raw->clear_pending(rss_raw);
4929 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4930 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4931 case (EVENT_RING_OPCODE_SET_MAC |
4932 BNX2X_STATE_CLOSING_WAIT4_HALT):
4933 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4935 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4937 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4938 BNX2X_STATE_CLOSING_WAIT4_HALT):
4939 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4940 bnx2x_handle_classification_eqe(bp, elem);
4943 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4945 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4947 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4948 BNX2X_STATE_CLOSING_WAIT4_HALT):
4949 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4950 bnx2x_handle_mcast_eqe(bp);
4953 case (EVENT_RING_OPCODE_FILTERS_RULES |
4955 case (EVENT_RING_OPCODE_FILTERS_RULES |
4957 case (EVENT_RING_OPCODE_FILTERS_RULES |
4958 BNX2X_STATE_CLOSING_WAIT4_HALT):
4959 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4960 bnx2x_handle_rx_mode_eqe(bp);
4963 /* unknown event log error and continue */
4964 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4965 elem->message.opcode, bp->state);
4971 smp_mb__before_atomic_inc();
4972 atomic_add(spqe_cnt, &bp->eq_spq_left);
4974 bp->eq_cons = sw_cons;
4975 bp->eq_prod = sw_prod;
4976 /* Make sure that above mem writes were issued towards the memory */
4979 /* update producer */
4980 bnx2x_update_eq_prod(bp, bp->eq_prod);
4983 static void bnx2x_sp_task(struct work_struct *work)
4985 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4988 status = bnx2x_update_dsb_idx(bp);
4989 /* if (status == 0) */
4990 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4992 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4995 if (status & BNX2X_DEF_SB_ATT_IDX) {
4997 status &= ~BNX2X_DEF_SB_ATT_IDX;
5000 /* SP events: STAT_QUERY and others */
5001 if (status & BNX2X_DEF_SB_IDX) {
5003 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5005 if ((!NO_FCOE(bp)) &&
5006 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5008 * Prevent local bottom-halves from running as
5009 * we are going to change the local NAPI list.
5012 napi_schedule(&bnx2x_fcoe(bp, napi));
5016 /* Handle EQ completions */
5019 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5020 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5022 status &= ~BNX2X_DEF_SB_IDX;
5025 if (unlikely(status))
5026 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5029 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5030 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5032 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5033 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5035 bnx2x_link_report(bp);
5036 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5040 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5042 struct net_device *dev = dev_instance;
5043 struct bnx2x *bp = netdev_priv(dev);
5045 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5046 IGU_INT_DISABLE, 0);
5048 #ifdef BNX2X_STOP_ON_ERROR
5049 if (unlikely(bp->panic))
5055 struct cnic_ops *c_ops;
5058 c_ops = rcu_dereference(bp->cnic_ops);
5060 c_ops->cnic_handler(bp->cnic_data, NULL);
5064 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5069 /* end of slow path */
5072 void bnx2x_drv_pulse(struct bnx2x *bp)
5074 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5075 bp->fw_drv_pulse_wr_seq);
5079 static void bnx2x_timer(unsigned long data)
5081 struct bnx2x *bp = (struct bnx2x *) data;
5083 if (!netif_running(bp->dev))
5086 if (!BP_NOMCP(bp)) {
5087 int mb_idx = BP_FW_MB_IDX(bp);
5091 ++bp->fw_drv_pulse_wr_seq;
5092 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5093 /* TBD - add SYSTEM_TIME */
5094 drv_pulse = bp->fw_drv_pulse_wr_seq;
5095 bnx2x_drv_pulse(bp);
5097 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5098 MCP_PULSE_SEQ_MASK);
5099 /* The delta between driver pulse and mcp response
5100 * should be 1 (before mcp response) or 0 (after mcp response)
5102 if ((drv_pulse != mcp_pulse) &&
5103 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5104 /* someone lost a heartbeat... */
5105 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5106 drv_pulse, mcp_pulse);
5110 if (bp->state == BNX2X_STATE_OPEN)
5111 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5113 mod_timer(&bp->timer, jiffies + bp->current_interval);
5116 /* end of Statistics */
5121 * nic init service functions
5124 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5127 if (!(len%4) && !(addr%4))
5128 for (i = 0; i < len; i += 4)
5129 REG_WR(bp, addr + i, fill);
5131 for (i = 0; i < len; i++)
5132 REG_WR8(bp, addr + i, fill);
5136 /* helper: writes FP SP data to FW - data_size in dwords */
5137 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5143 for (index = 0; index < data_size; index++)
5144 REG_WR(bp, BAR_CSTRORM_INTMEM +
5145 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5147 *(sb_data_p + index));
5150 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5154 struct hc_status_block_data_e2 sb_data_e2;
5155 struct hc_status_block_data_e1x sb_data_e1x;
5157 /* disable the function first */
5158 if (!CHIP_IS_E1x(bp)) {
5159 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5160 sb_data_e2.common.state = SB_DISABLED;
5161 sb_data_e2.common.p_func.vf_valid = false;
5162 sb_data_p = (u32 *)&sb_data_e2;
5163 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5165 memset(&sb_data_e1x, 0,
5166 sizeof(struct hc_status_block_data_e1x));
5167 sb_data_e1x.common.state = SB_DISABLED;
5168 sb_data_e1x.common.p_func.vf_valid = false;
5169 sb_data_p = (u32 *)&sb_data_e1x;
5170 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5172 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5174 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5175 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5176 CSTORM_STATUS_BLOCK_SIZE);
5177 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5178 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5179 CSTORM_SYNC_BLOCK_SIZE);
5182 /* helper: writes SP SB data to FW */
5183 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5184 struct hc_sp_status_block_data *sp_sb_data)
5186 int func = BP_FUNC(bp);
5188 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5189 REG_WR(bp, BAR_CSTRORM_INTMEM +
5190 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5192 *((u32 *)sp_sb_data + i));
5195 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5197 int func = BP_FUNC(bp);
5198 struct hc_sp_status_block_data sp_sb_data;
5199 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5201 sp_sb_data.state = SB_DISABLED;
5202 sp_sb_data.p_func.vf_valid = false;
5204 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5206 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5207 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5208 CSTORM_SP_STATUS_BLOCK_SIZE);
5209 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5210 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5211 CSTORM_SP_SYNC_BLOCK_SIZE);
5216 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5217 int igu_sb_id, int igu_seg_id)
5219 hc_sm->igu_sb_id = igu_sb_id;
5220 hc_sm->igu_seg_id = igu_seg_id;
5221 hc_sm->timer_value = 0xFF;
5222 hc_sm->time_to_expire = 0xFFFFFFFF;
5226 /* allocates state machine ids. */
5227 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5229 /* zero out state machine indices */
5231 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5234 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5235 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5236 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5237 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5241 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5242 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5245 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5246 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5247 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5248 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5249 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5250 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5251 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5252 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5255 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5256 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5260 struct hc_status_block_data_e2 sb_data_e2;
5261 struct hc_status_block_data_e1x sb_data_e1x;
5262 struct hc_status_block_sm *hc_sm_p;
5266 if (CHIP_INT_MODE_IS_BC(bp))
5267 igu_seg_id = HC_SEG_ACCESS_NORM;
5269 igu_seg_id = IGU_SEG_ACCESS_NORM;
5271 bnx2x_zero_fp_sb(bp, fw_sb_id);
5273 if (!CHIP_IS_E1x(bp)) {
5274 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5275 sb_data_e2.common.state = SB_ENABLED;
5276 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5277 sb_data_e2.common.p_func.vf_id = vfid;
5278 sb_data_e2.common.p_func.vf_valid = vf_valid;
5279 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5280 sb_data_e2.common.same_igu_sb_1b = true;
5281 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5282 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5283 hc_sm_p = sb_data_e2.common.state_machine;
5284 sb_data_p = (u32 *)&sb_data_e2;
5285 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5286 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5288 memset(&sb_data_e1x, 0,
5289 sizeof(struct hc_status_block_data_e1x));
5290 sb_data_e1x.common.state = SB_ENABLED;
5291 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5292 sb_data_e1x.common.p_func.vf_id = 0xff;
5293 sb_data_e1x.common.p_func.vf_valid = false;
5294 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5295 sb_data_e1x.common.same_igu_sb_1b = true;
5296 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5297 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5298 hc_sm_p = sb_data_e1x.common.state_machine;
5299 sb_data_p = (u32 *)&sb_data_e1x;
5300 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5301 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5304 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5305 igu_sb_id, igu_seg_id);
5306 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5307 igu_sb_id, igu_seg_id);
5309 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5311 /* write indecies to HW */
5312 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5315 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5316 u16 tx_usec, u16 rx_usec)
5318 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5320 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5321 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5323 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5324 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5326 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5327 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5331 static void bnx2x_init_def_sb(struct bnx2x *bp)
5333 struct host_sp_status_block *def_sb = bp->def_status_blk;
5334 dma_addr_t mapping = bp->def_status_blk_mapping;
5335 int igu_sp_sb_index;
5337 int port = BP_PORT(bp);
5338 int func = BP_FUNC(bp);
5339 int reg_offset, reg_offset_en5;
5342 struct hc_sp_status_block_data sp_sb_data;
5343 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5345 if (CHIP_INT_MODE_IS_BC(bp)) {
5346 igu_sp_sb_index = DEF_SB_IGU_ID;
5347 igu_seg_id = HC_SEG_ACCESS_DEF;
5349 igu_sp_sb_index = bp->igu_dsb_id;
5350 igu_seg_id = IGU_SEG_ACCESS_DEF;
5354 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5355 atten_status_block);
5356 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5360 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5361 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5362 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5363 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5364 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5366 /* take care of sig[0]..sig[4] */
5367 for (sindex = 0; sindex < 4; sindex++)
5368 bp->attn_group[index].sig[sindex] =
5369 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5371 if (!CHIP_IS_E1x(bp))
5373 * enable5 is separate from the rest of the registers,
5374 * and therefore the address skip is 4
5375 * and not 16 between the different groups
5377 bp->attn_group[index].sig[4] = REG_RD(bp,
5378 reg_offset_en5 + 0x4*index);
5380 bp->attn_group[index].sig[4] = 0;
5383 if (bp->common.int_block == INT_BLOCK_HC) {
5384 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5385 HC_REG_ATTN_MSG0_ADDR_L);
5387 REG_WR(bp, reg_offset, U64_LO(section));
5388 REG_WR(bp, reg_offset + 4, U64_HI(section));
5389 } else if (!CHIP_IS_E1x(bp)) {
5390 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5391 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5394 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5397 bnx2x_zero_sp_sb(bp);
5399 sp_sb_data.state = SB_ENABLED;
5400 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5401 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5402 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5403 sp_sb_data.igu_seg_id = igu_seg_id;
5404 sp_sb_data.p_func.pf_id = func;
5405 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5406 sp_sb_data.p_func.vf_id = 0xff;
5408 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5410 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5413 void bnx2x_update_coalesce(struct bnx2x *bp)
5417 for_each_eth_queue(bp, i)
5418 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5419 bp->tx_ticks, bp->rx_ticks);
5422 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5424 spin_lock_init(&bp->spq_lock);
5425 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5427 bp->spq_prod_idx = 0;
5428 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5429 bp->spq_prod_bd = bp->spq;
5430 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5433 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5436 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5437 union event_ring_elem *elem =
5438 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5440 elem->next_page.addr.hi =
5441 cpu_to_le32(U64_HI(bp->eq_mapping +
5442 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5443 elem->next_page.addr.lo =
5444 cpu_to_le32(U64_LO(bp->eq_mapping +
5445 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5448 bp->eq_prod = NUM_EQ_DESC;
5449 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5450 /* we want a warning message before it gets rought... */
5451 atomic_set(&bp->eq_spq_left,
5452 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5456 /* called with netif_addr_lock_bh() */
5457 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5458 unsigned long rx_mode_flags,
5459 unsigned long rx_accept_flags,
5460 unsigned long tx_accept_flags,
5461 unsigned long ramrod_flags)
5463 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5466 memset(&ramrod_param, 0, sizeof(ramrod_param));
5468 /* Prepare ramrod parameters */
5469 ramrod_param.cid = 0;
5470 ramrod_param.cl_id = cl_id;
5471 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5472 ramrod_param.func_id = BP_FUNC(bp);
5474 ramrod_param.pstate = &bp->sp_state;
5475 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5477 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5478 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5480 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5482 ramrod_param.ramrod_flags = ramrod_flags;
5483 ramrod_param.rx_mode_flags = rx_mode_flags;
5485 ramrod_param.rx_accept_flags = rx_accept_flags;
5486 ramrod_param.tx_accept_flags = tx_accept_flags;
5488 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5490 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5495 /* called with netif_addr_lock_bh() */
5496 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5498 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5499 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5504 /* Configure rx_mode of FCoE Queue */
5505 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5508 switch (bp->rx_mode) {
5509 case BNX2X_RX_MODE_NONE:
5511 * 'drop all' supersedes any accept flags that may have been
5512 * passed to the function.
5515 case BNX2X_RX_MODE_NORMAL:
5516 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5517 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5518 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5520 /* internal switching mode */
5521 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5522 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5523 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5526 case BNX2X_RX_MODE_ALLMULTI:
5527 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5528 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5529 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5531 /* internal switching mode */
5532 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5533 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5534 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5537 case BNX2X_RX_MODE_PROMISC:
5538 /* According to deffinition of SI mode, iface in promisc mode
5539 * should receive matched and unmatched (in resolution of port)
5542 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5543 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5544 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5545 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5547 /* internal switching mode */
5548 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5549 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5552 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5554 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5558 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5562 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5563 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5564 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5567 __set_bit(RAMROD_RX, &ramrod_flags);
5568 __set_bit(RAMROD_TX, &ramrod_flags);
5570 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5571 tx_accept_flags, ramrod_flags);
5574 static void bnx2x_init_internal_common(struct bnx2x *bp)
5580 * In switch independent mode, the TSTORM needs to accept
5581 * packets that failed classification, since approximate match
5582 * mac addresses aren't written to NIG LLH
5584 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5585 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5586 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5587 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5588 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5590 /* Zero this manually as its initialization is
5591 currently missing in the initTool */
5592 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5593 REG_WR(bp, BAR_USTRORM_INTMEM +
5594 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5595 if (!CHIP_IS_E1x(bp)) {
5596 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5597 CHIP_INT_MODE_IS_BC(bp) ?
5598 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5602 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5604 switch (load_code) {
5605 case FW_MSG_CODE_DRV_LOAD_COMMON:
5606 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5607 bnx2x_init_internal_common(bp);
5610 case FW_MSG_CODE_DRV_LOAD_PORT:
5614 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5615 /* internal memory per function is
5616 initialized inside bnx2x_pf_init */
5620 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5625 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5627 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5630 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5632 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5635 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5637 if (CHIP_IS_E1x(fp->bp))
5638 return BP_L_ID(fp->bp) + fp->index;
5639 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5640 return bnx2x_fp_igu_sb_id(fp);
5643 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5645 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5647 unsigned long q_type = 0;
5648 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5649 fp->rx_queue = fp_idx;
5651 fp->cl_id = bnx2x_fp_cl_id(fp);
5652 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5653 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5654 /* qZone id equals to FW (per path) client id */
5655 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5658 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5660 /* Setup SB indicies */
5661 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5663 /* Configure Queue State object */
5664 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5665 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5667 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5670 for_each_cos_in_tx_queue(fp, cos) {
5671 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5672 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5673 FP_COS_TO_TXQ(fp, cos, bp),
5674 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5675 cids[cos] = fp->txdata_ptr[cos]->cid;
5678 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5679 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5680 bnx2x_sp_mapping(bp, q_rdata), q_type);
5683 * Configure classification DBs: Always enable Tx switching
5685 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5687 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5688 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5690 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5691 fp->fw_sb_id, fp->igu_sb_id);
5693 bnx2x_update_fpsb_idx(fp);
5696 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5700 for (i = 1; i <= NUM_TX_RINGS; i++) {
5701 struct eth_tx_next_bd *tx_next_bd =
5702 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5704 tx_next_bd->addr_hi =
5705 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5706 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5707 tx_next_bd->addr_lo =
5708 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5709 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5712 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5713 txdata->tx_db.data.zero_fill1 = 0;
5714 txdata->tx_db.data.prod = 0;
5716 txdata->tx_pkt_prod = 0;
5717 txdata->tx_pkt_cons = 0;
5718 txdata->tx_bd_prod = 0;
5719 txdata->tx_bd_cons = 0;
5723 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5728 for_each_tx_queue(bp, i)
5729 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5730 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5733 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5737 for_each_eth_queue(bp, i)
5738 bnx2x_init_eth_fp(bp, i);
5741 bnx2x_init_fcoe_fp(bp);
5743 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5744 BNX2X_VF_ID_INVALID, false,
5745 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5749 /* Initialize MOD_ABS interrupts */
5750 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5751 bp->common.shmem_base, bp->common.shmem2_base,
5753 /* ensure status block indices were read */
5756 bnx2x_init_def_sb(bp);
5757 bnx2x_update_dsb_idx(bp);
5758 bnx2x_init_rx_rings(bp);
5759 bnx2x_init_tx_rings(bp);
5760 bnx2x_init_sp_ring(bp);
5761 bnx2x_init_eq_ring(bp);
5762 bnx2x_init_internal(bp, load_code);
5764 bnx2x_stats_init(bp);
5766 /* flush all before enabling interrupts */
5770 bnx2x_int_enable(bp);
5772 /* Check for SPIO5 */
5773 bnx2x_attn_int_deasserted0(bp,
5774 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5775 AEU_INPUTS_ATTN_BITS_SPIO5);
5778 /* end of nic init */
5781 * gzip service functions
5784 static int bnx2x_gunzip_init(struct bnx2x *bp)
5786 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5787 &bp->gunzip_mapping, GFP_KERNEL);
5788 if (bp->gunzip_buf == NULL)
5791 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5792 if (bp->strm == NULL)
5795 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5796 if (bp->strm->workspace == NULL)
5806 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5807 bp->gunzip_mapping);
5808 bp->gunzip_buf = NULL;
5811 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5815 static void bnx2x_gunzip_end(struct bnx2x *bp)
5818 vfree(bp->strm->workspace);
5823 if (bp->gunzip_buf) {
5824 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5825 bp->gunzip_mapping);
5826 bp->gunzip_buf = NULL;
5830 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5834 /* check gzip header */
5835 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5836 BNX2X_ERR("Bad gzip header\n");
5844 if (zbuf[3] & FNAME)
5845 while ((zbuf[n++] != 0) && (n < len));
5847 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5848 bp->strm->avail_in = len - n;
5849 bp->strm->next_out = bp->gunzip_buf;
5850 bp->strm->avail_out = FW_BUF_SIZE;
5852 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5856 rc = zlib_inflate(bp->strm, Z_FINISH);
5857 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5858 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5861 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5862 if (bp->gunzip_outlen & 0x3)
5864 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5866 bp->gunzip_outlen >>= 2;
5868 zlib_inflateEnd(bp->strm);
5870 if (rc == Z_STREAM_END)
5876 /* nic load/unload */
5879 * General service functions
5882 /* send a NIG loopback debug packet */
5883 static void bnx2x_lb_pckt(struct bnx2x *bp)
5887 /* Ethernet source and destination addresses */
5888 wb_write[0] = 0x55555555;
5889 wb_write[1] = 0x55555555;
5890 wb_write[2] = 0x20; /* SOP */
5891 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5893 /* NON-IP protocol */
5894 wb_write[0] = 0x09000000;
5895 wb_write[1] = 0x55555555;
5896 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5897 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5900 /* some of the internal memories
5901 * are not directly readable from the driver
5902 * to test them we send debug packets
5904 static int bnx2x_int_mem_test(struct bnx2x *bp)
5910 if (CHIP_REV_IS_FPGA(bp))
5912 else if (CHIP_REV_IS_EMUL(bp))
5917 /* Disable inputs of parser neighbor blocks */
5918 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5919 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5920 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5921 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5923 /* Write 0 to parser credits for CFC search request */
5924 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5926 /* send Ethernet packet */
5929 /* TODO do i reset NIG statistic? */
5930 /* Wait until NIG register shows 1 packet of size 0x10 */
5931 count = 1000 * factor;
5934 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5935 val = *bnx2x_sp(bp, wb_data[0]);
5943 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5947 /* Wait until PRS register shows 1 packet */
5948 count = 1000 * factor;
5950 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5958 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5962 /* Reset and init BRB, PRS */
5963 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5965 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5967 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5968 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5970 DP(NETIF_MSG_HW, "part2\n");
5972 /* Disable inputs of parser neighbor blocks */
5973 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5974 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5975 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5976 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5978 /* Write 0 to parser credits for CFC search request */
5979 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5981 /* send 10 Ethernet packets */
5982 for (i = 0; i < 10; i++)
5985 /* Wait until NIG register shows 10 + 1
5986 packets of size 11*0x10 = 0xb0 */
5987 count = 1000 * factor;
5990 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5991 val = *bnx2x_sp(bp, wb_data[0]);
5999 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6003 /* Wait until PRS register shows 2 packets */
6004 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6006 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6008 /* Write 1 to parser credits for CFC search request */
6009 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6011 /* Wait until PRS register shows 3 packets */
6012 msleep(10 * factor);
6013 /* Wait until NIG register shows 1 packet of size 0x10 */
6014 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6016 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6018 /* clear NIG EOP FIFO */
6019 for (i = 0; i < 11; i++)
6020 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6021 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6023 BNX2X_ERR("clear of NIG failed\n");
6027 /* Reset and init BRB, PRS, NIG */
6028 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6030 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6032 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6033 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6036 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6039 /* Enable inputs of parser neighbor blocks */
6040 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6041 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6042 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6043 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6045 DP(NETIF_MSG_HW, "done\n");
6050 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6052 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6053 if (!CHIP_IS_E1x(bp))
6054 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6056 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6057 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6058 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6060 * mask read length error interrupts in brb for parser
6061 * (parsing unit and 'checksum and crc' unit)
6062 * these errors are legal (PU reads fixed length and CAC can cause
6063 * read length error on truncated packets)
6065 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6066 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6067 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6068 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6069 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6070 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6071 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6072 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6073 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6074 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6075 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6076 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6077 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6078 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6079 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6080 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6081 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6082 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6083 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6085 if (CHIP_REV_IS_FPGA(bp))
6086 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6087 else if (!CHIP_IS_E1x(bp))
6088 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6089 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6090 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6091 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6092 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6093 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6095 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6096 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6097 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6098 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6099 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6101 if (!CHIP_IS_E1x(bp))
6102 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6103 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6105 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6106 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6107 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6108 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6111 static void bnx2x_reset_common(struct bnx2x *bp)
6116 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6119 if (CHIP_IS_E3(bp)) {
6120 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6121 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6124 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6127 static void bnx2x_setup_dmae(struct bnx2x *bp)
6130 spin_lock_init(&bp->dmae_lock);
6133 static void bnx2x_init_pxp(struct bnx2x *bp)
6136 int r_order, w_order;
6138 pci_read_config_word(bp->pdev,
6139 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
6140 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6141 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6143 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6145 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6149 bnx2x_init_pxp_arb(bp, r_order, w_order);
6152 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6162 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6163 SHARED_HW_CFG_FAN_FAILURE_MASK;
6165 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6169 * The fan failure mechanism is usually related to the PHY type since
6170 * the power consumption of the board is affected by the PHY. Currently,
6171 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6173 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6174 for (port = PORT_0; port < PORT_MAX; port++) {
6176 bnx2x_fan_failure_det_req(
6178 bp->common.shmem_base,
6179 bp->common.shmem2_base,
6183 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6185 if (is_required == 0)
6188 /* Fan failure is indicated by SPIO 5 */
6189 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6190 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6192 /* set to active low mode */
6193 val = REG_RD(bp, MISC_REG_SPIO_INT);
6194 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6195 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6196 REG_WR(bp, MISC_REG_SPIO_INT, val);
6198 /* enable interrupt to signal the IGU */
6199 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6200 val |= (1 << MISC_REGISTERS_SPIO_5);
6201 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6204 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6210 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6213 switch (BP_ABS_FUNC(bp)) {
6215 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6218 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6221 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6224 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6227 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6230 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6233 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6236 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6242 REG_WR(bp, offset, pretend_func_num);
6244 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6247 void bnx2x_pf_disable(struct bnx2x *bp)
6249 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6250 val &= ~IGU_PF_CONF_FUNC_EN;
6252 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6253 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6254 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6257 static void bnx2x__common_init_phy(struct bnx2x *bp)
6259 u32 shmem_base[2], shmem2_base[2];
6260 shmem_base[0] = bp->common.shmem_base;
6261 shmem2_base[0] = bp->common.shmem2_base;
6262 if (!CHIP_IS_E1x(bp)) {
6264 SHMEM2_RD(bp, other_shmem_base_addr);
6266 SHMEM2_RD(bp, other_shmem2_base_addr);
6268 bnx2x_acquire_phy_lock(bp);
6269 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6270 bp->common.chip_id);
6271 bnx2x_release_phy_lock(bp);
6275 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6277 * @bp: driver handle
6279 static int bnx2x_init_hw_common(struct bnx2x *bp)
6283 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6286 * take the UNDI lock to protect undi_unload flow from accessing
6287 * registers while we're resetting the chip
6289 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6291 bnx2x_reset_common(bp);
6292 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6295 if (CHIP_IS_E3(bp)) {
6296 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6297 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6299 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6301 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6303 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6305 if (!CHIP_IS_E1x(bp)) {
6309 * 4-port mode or 2-port mode we need to turn of master-enable
6310 * for everyone, after that, turn it back on for self.
6311 * so, we disregard multi-function or not, and always disable
6312 * for all functions on the given path, this means 0,2,4,6 for
6313 * path 0 and 1,3,5,7 for path 1
6315 for (abs_func_id = BP_PATH(bp);
6316 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6317 if (abs_func_id == BP_ABS_FUNC(bp)) {
6319 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6324 bnx2x_pretend_func(bp, abs_func_id);
6325 /* clear pf enable */
6326 bnx2x_pf_disable(bp);
6327 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6331 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6332 if (CHIP_IS_E1(bp)) {
6333 /* enable HW interrupt from PXP on USDM overflow
6334 bit 16 on INT_MASK_0 */
6335 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6338 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6342 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6343 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6344 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6345 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6346 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6347 /* make sure this value is 0 */
6348 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6350 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6351 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6352 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6353 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6354 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6357 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6359 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6360 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6362 /* let the HW do it's magic ... */
6364 /* finish PXP init */
6365 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6367 BNX2X_ERR("PXP2 CFG failed\n");
6370 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6372 BNX2X_ERR("PXP2 RD_INIT failed\n");
6376 /* Timers bug workaround E2 only. We need to set the entire ILT to
6377 * have entries with value "0" and valid bit on.
6378 * This needs to be done by the first PF that is loaded in a path
6379 * (i.e. common phase)
6381 if (!CHIP_IS_E1x(bp)) {
6382 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6383 * (i.e. vnic3) to start even if it is marked as "scan-off".
6384 * This occurs when a different function (func2,3) is being marked
6385 * as "scan-off". Real-life scenario for example: if a driver is being
6386 * load-unloaded while func6,7 are down. This will cause the timer to access
6387 * the ilt, translate to a logical address and send a request to read/write.
6388 * Since the ilt for the function that is down is not valid, this will cause
6389 * a translation error which is unrecoverable.
6390 * The Workaround is intended to make sure that when this happens nothing fatal
6391 * will occur. The workaround:
6392 * 1. First PF driver which loads on a path will:
6393 * a. After taking the chip out of reset, by using pretend,
6394 * it will write "0" to the following registers of
6396 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6397 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6398 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6399 * And for itself it will write '1' to
6400 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6401 * dmae-operations (writing to pram for example.)
6402 * note: can be done for only function 6,7 but cleaner this
6404 * b. Write zero+valid to the entire ILT.
6405 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6406 * VNIC3 (of that port). The range allocated will be the
6407 * entire ILT. This is needed to prevent ILT range error.
6408 * 2. Any PF driver load flow:
6409 * a. ILT update with the physical addresses of the allocated
6411 * b. Wait 20msec. - note that this timeout is needed to make
6412 * sure there are no requests in one of the PXP internal
6413 * queues with "old" ILT addresses.
6414 * c. PF enable in the PGLC.
6415 * d. Clear the was_error of the PF in the PGLC. (could have
6416 * occured while driver was down)
6417 * e. PF enable in the CFC (WEAK + STRONG)
6418 * f. Timers scan enable
6419 * 3. PF driver unload flow:
6420 * a. Clear the Timers scan_en.
6421 * b. Polling for scan_on=0 for that PF.
6422 * c. Clear the PF enable bit in the PXP.
6423 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6424 * e. Write zero+valid to all ILT entries (The valid bit must
6426 * f. If this is VNIC 3 of a port then also init
6427 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6428 * to the last enrty in the ILT.
6431 * Currently the PF error in the PGLC is non recoverable.
6432 * In the future the there will be a recovery routine for this error.
6433 * Currently attention is masked.
6434 * Having an MCP lock on the load/unload process does not guarantee that
6435 * there is no Timer disable during Func6/7 enable. This is because the
6436 * Timers scan is currently being cleared by the MCP on FLR.
6437 * Step 2.d can be done only for PF6/7 and the driver can also check if
6438 * there is error before clearing it. But the flow above is simpler and
6440 * All ILT entries are written by zero+valid and not just PF6/7
6441 * ILT entries since in the future the ILT entries allocation for
6442 * PF-s might be dynamic.
6444 struct ilt_client_info ilt_cli;
6445 struct bnx2x_ilt ilt;
6446 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6447 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6449 /* initialize dummy TM client */
6451 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6452 ilt_cli.client_num = ILT_CLIENT_TM;
6454 /* Step 1: set zeroes to all ilt page entries with valid bit on
6455 * Step 2: set the timers first/last ilt entry to point
6456 * to the entire range to prevent ILT range error for 3rd/4th
6457 * vnic (this code assumes existance of the vnic)
6459 * both steps performed by call to bnx2x_ilt_client_init_op()
6460 * with dummy TM client
6462 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6463 * and his brother are split registers
6465 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6466 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6467 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6469 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6470 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6471 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6475 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6476 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6478 if (!CHIP_IS_E1x(bp)) {
6479 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6480 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6481 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6483 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6485 /* let the HW do it's magic ... */
6488 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6489 } while (factor-- && (val != 1));
6492 BNX2X_ERR("ATC_INIT failed\n");
6497 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6499 /* clean the DMAE memory */
6501 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6503 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6505 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6507 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6509 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6511 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6512 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6513 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6514 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6516 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6519 /* QM queues pointers table */
6520 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6522 /* soft reset pulse */
6523 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6524 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6527 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6530 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6531 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6532 if (!CHIP_REV_IS_SLOW(bp))
6533 /* enable hw interrupt from doorbell Q */
6534 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6536 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6538 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6539 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6541 if (!CHIP_IS_E1(bp))
6542 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6544 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6545 if (IS_MF_AFEX(bp)) {
6546 /* configure that VNTag and VLAN headers must be
6547 * received in afex mode
6549 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6550 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6551 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6552 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6553 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6555 /* Bit-map indicating which L2 hdrs may appear
6556 * after the basic Ethernet header
6558 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6559 bp->path_has_ovlan ? 7 : 6);
6563 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6564 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6565 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6566 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6568 if (!CHIP_IS_E1x(bp)) {
6569 /* reset VFC memories */
6570 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6571 VFC_MEMORIES_RST_REG_CAM_RST |
6572 VFC_MEMORIES_RST_REG_RAM_RST);
6573 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6574 VFC_MEMORIES_RST_REG_CAM_RST |
6575 VFC_MEMORIES_RST_REG_RAM_RST);
6580 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6581 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6582 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6583 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6588 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6591 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6592 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6593 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6595 if (!CHIP_IS_E1x(bp)) {
6596 if (IS_MF_AFEX(bp)) {
6597 /* configure that VNTag and VLAN headers must be
6600 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6601 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6602 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6603 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6604 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6606 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6607 bp->path_has_ovlan ? 7 : 6);
6611 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6613 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6616 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6617 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6618 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6619 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6620 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6621 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6622 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6623 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6624 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6625 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6627 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6629 if (sizeof(union cdu_context) != 1024)
6630 /* we currently assume that a context is 1024 bytes */
6631 dev_alert(&bp->pdev->dev,
6632 "please adjust the size of cdu_context(%ld)\n",
6633 (long)sizeof(union cdu_context));
6635 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6636 val = (4 << 24) + (0 << 12) + 1024;
6637 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6639 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6640 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6641 /* enable context validation interrupt from CFC */
6642 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6644 /* set the thresholds to prevent CFC/CDU race */
6645 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6647 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6649 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6650 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6652 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6653 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6655 /* Reset PCIE errors for debug */
6656 REG_WR(bp, 0x2814, 0xffffffff);
6657 REG_WR(bp, 0x3820, 0xffffffff);
6659 if (!CHIP_IS_E1x(bp)) {
6660 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6661 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6662 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6663 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6664 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6665 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6666 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6667 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6668 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6669 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6670 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6673 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6674 if (!CHIP_IS_E1(bp)) {
6675 /* in E3 this done in per-port section */
6676 if (!CHIP_IS_E3(bp))
6677 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6679 if (CHIP_IS_E1H(bp))
6680 /* not applicable for E2 (and above ...) */
6681 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6683 if (CHIP_REV_IS_SLOW(bp))
6686 /* finish CFC init */
6687 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6689 BNX2X_ERR("CFC LL_INIT failed\n");
6692 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6694 BNX2X_ERR("CFC AC_INIT failed\n");
6697 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6699 BNX2X_ERR("CFC CAM_INIT failed\n");
6702 REG_WR(bp, CFC_REG_DEBUG0, 0);
6704 if (CHIP_IS_E1(bp)) {
6705 /* read NIG statistic
6706 to see if this is our first up since powerup */
6707 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6708 val = *bnx2x_sp(bp, wb_data[0]);
6710 /* do internal memory self test */
6711 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6712 BNX2X_ERR("internal mem self test failed\n");
6717 bnx2x_setup_fan_failure_detection(bp);
6719 /* clear PXP2 attentions */
6720 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6722 bnx2x_enable_blocks_attention(bp);
6723 bnx2x_enable_blocks_parity(bp);
6725 if (!BP_NOMCP(bp)) {
6726 if (CHIP_IS_E1x(bp))
6727 bnx2x__common_init_phy(bp);
6729 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6735 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6737 * @bp: driver handle
6739 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6741 int rc = bnx2x_init_hw_common(bp);
6746 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6748 bnx2x__common_init_phy(bp);
6753 static int bnx2x_init_hw_port(struct bnx2x *bp)
6755 int port = BP_PORT(bp);
6756 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6760 bnx2x__link_reset(bp);
6762 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6764 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6766 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6767 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6768 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6770 /* Timers bug workaround: disables the pf_master bit in pglue at
6771 * common phase, we need to enable it here before any dmae access are
6772 * attempted. Therefore we manually added the enable-master to the
6773 * port phase (it also happens in the function phase)
6775 if (!CHIP_IS_E1x(bp))
6776 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6778 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6779 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6780 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6781 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6783 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6784 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6785 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6786 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6788 /* QM cid (connection) count */
6789 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6792 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6793 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6794 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6797 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6799 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6800 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6803 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6804 else if (bp->dev->mtu > 4096) {
6805 if (bp->flags & ONE_PORT_FLAG)
6809 /* (24*1024 + val*4)/256 */
6810 low = 96 + (val/64) +
6811 ((val % 64) ? 1 : 0);
6814 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6815 high = low + 56; /* 14*1024/256 */
6816 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6817 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6820 if (CHIP_MODE_IS_4_PORT(bp))
6821 REG_WR(bp, (BP_PORT(bp) ?
6822 BRB1_REG_MAC_GUARANTIED_1 :
6823 BRB1_REG_MAC_GUARANTIED_0), 40);
6826 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6827 if (CHIP_IS_E3B0(bp)) {
6828 if (IS_MF_AFEX(bp)) {
6829 /* configure headers for AFEX mode */
6830 REG_WR(bp, BP_PORT(bp) ?
6831 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6832 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6833 REG_WR(bp, BP_PORT(bp) ?
6834 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6835 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6836 REG_WR(bp, BP_PORT(bp) ?
6837 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6838 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6840 /* Ovlan exists only if we are in multi-function +
6841 * switch-dependent mode, in switch-independent there
6842 * is no ovlan headers
6844 REG_WR(bp, BP_PORT(bp) ?
6845 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6846 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6847 (bp->path_has_ovlan ? 7 : 6));
6851 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6852 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6853 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6854 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6856 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6857 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6858 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6859 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6861 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6862 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6864 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6866 if (CHIP_IS_E1x(bp)) {
6867 /* configure PBF to work without PAUSE mtu 9000 */
6868 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6870 /* update threshold */
6871 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6872 /* update init credit */
6873 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6876 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6878 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6882 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6884 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6885 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6887 if (CHIP_IS_E1(bp)) {
6888 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6889 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6891 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6893 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6895 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6896 /* init aeu_mask_attn_func_0/1:
6897 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6898 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6899 * bits 4-7 are used for "per vn group attention" */
6900 val = IS_MF(bp) ? 0xF7 : 0x7;
6901 /* Enable DCBX attention for all but E1 */
6902 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6903 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6905 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6907 if (!CHIP_IS_E1x(bp)) {
6908 /* Bit-map indicating which L2 hdrs may appear after the
6909 * basic Ethernet header
6912 REG_WR(bp, BP_PORT(bp) ?
6913 NIG_REG_P1_HDRS_AFTER_BASIC :
6914 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6916 REG_WR(bp, BP_PORT(bp) ?
6917 NIG_REG_P1_HDRS_AFTER_BASIC :
6918 NIG_REG_P0_HDRS_AFTER_BASIC,
6919 IS_MF_SD(bp) ? 7 : 6);
6922 REG_WR(bp, BP_PORT(bp) ?
6923 NIG_REG_LLH1_MF_MODE :
6924 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6926 if (!CHIP_IS_E3(bp))
6927 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6929 if (!CHIP_IS_E1(bp)) {
6930 /* 0x2 disable mf_ov, 0x1 enable */
6931 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6932 (IS_MF_SD(bp) ? 0x1 : 0x2));
6934 if (!CHIP_IS_E1x(bp)) {
6936 switch (bp->mf_mode) {
6937 case MULTI_FUNCTION_SD:
6940 case MULTI_FUNCTION_SI:
6941 case MULTI_FUNCTION_AFEX:
6946 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6947 NIG_REG_LLH0_CLS_TYPE), val);
6950 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6951 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6952 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6957 /* If SPIO5 is set to generate interrupts, enable it for this port */
6958 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6959 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6960 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6961 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6962 val = REG_RD(bp, reg_addr);
6963 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6964 REG_WR(bp, reg_addr, val);
6970 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6976 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6978 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6980 wb_write[0] = ONCHIP_ADDR1(addr);
6981 wb_write[1] = ONCHIP_ADDR2(addr);
6982 REG_WR_DMAE(bp, reg, wb_write, 2);
6985 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6986 u8 idu_sb_id, bool is_Pf)
6988 u32 data, ctl, cnt = 100;
6989 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6990 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6991 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
6992 u32 sb_bit = 1 << (idu_sb_id%32);
6993 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
6994 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
6996 /* Not supported in BC mode */
6997 if (CHIP_INT_MODE_IS_BC(bp))
7000 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7001 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7002 IGU_REGULAR_CLEANUP_SET |
7003 IGU_REGULAR_BCLEANUP;
7005 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7006 func_encode << IGU_CTRL_REG_FID_SHIFT |
7007 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7009 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7010 data, igu_addr_data);
7011 REG_WR(bp, igu_addr_data, data);
7014 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7016 REG_WR(bp, igu_addr_ctl, ctl);
7020 /* wait for clean up to finish */
7021 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7025 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7027 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7028 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7032 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7034 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7037 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7039 u32 i, base = FUNC_ILT_BASE(func);
7040 for (i = base; i < base + ILT_PER_FUNC; i++)
7041 bnx2x_ilt_wr(bp, i, 0);
7044 static int bnx2x_init_hw_func(struct bnx2x *bp)
7046 int port = BP_PORT(bp);
7047 int func = BP_FUNC(bp);
7048 int init_phase = PHASE_PF0 + func;
7049 struct bnx2x_ilt *ilt = BP_ILT(bp);
7052 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7053 int i, main_mem_width, rc;
7055 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7057 /* FLR cleanup - hmmm */
7058 if (!CHIP_IS_E1x(bp)) {
7059 rc = bnx2x_pf_flr_clnup(bp);
7064 /* set MSI reconfigure capability */
7065 if (bp->common.int_block == INT_BLOCK_HC) {
7066 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7067 val = REG_RD(bp, addr);
7068 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7069 REG_WR(bp, addr, val);
7072 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7073 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7076 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7078 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7079 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7080 ilt->lines[cdu_ilt_start + i].page_mapping =
7081 bp->context[i].cxt_mapping;
7082 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7084 bnx2x_ilt_init_op(bp, INITOP_SET);
7087 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7089 /* T1 hash bits value determines the T1 number of entries */
7090 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7095 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7096 #endif /* BCM_CNIC */
7098 if (!CHIP_IS_E1x(bp)) {
7099 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7101 /* Turn on a single ISR mode in IGU if driver is going to use
7104 if (!(bp->flags & USING_MSIX_FLAG))
7105 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7107 * Timers workaround bug: function init part.
7108 * Need to wait 20msec after initializing ILT,
7109 * needed to make sure there are no requests in
7110 * one of the PXP internal queues with "old" ILT addresses
7114 * Master enable - Due to WB DMAE writes performed before this
7115 * register is re-initialized as part of the regular function
7118 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7119 /* Enable the function in IGU */
7120 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7125 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7127 if (!CHIP_IS_E1x(bp))
7128 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7130 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7131 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7132 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7133 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7134 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7135 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7136 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7137 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7138 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7139 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7140 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7141 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7142 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7144 if (!CHIP_IS_E1x(bp))
7145 REG_WR(bp, QM_REG_PF_EN, 1);
7147 if (!CHIP_IS_E1x(bp)) {
7148 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7149 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7150 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7151 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7153 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7155 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7156 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7157 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7158 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7159 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7160 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7161 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7162 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7163 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7164 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7165 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7166 if (!CHIP_IS_E1x(bp))
7167 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7169 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7171 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7173 if (!CHIP_IS_E1x(bp))
7174 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7177 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7178 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7181 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7183 /* HC init per function */
7184 if (bp->common.int_block == INT_BLOCK_HC) {
7185 if (CHIP_IS_E1H(bp)) {
7186 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7188 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7189 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7191 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7194 int num_segs, sb_idx, prod_offset;
7196 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7198 if (!CHIP_IS_E1x(bp)) {
7199 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7200 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7203 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7205 if (!CHIP_IS_E1x(bp)) {
7209 * E2 mode: address 0-135 match to the mapping memory;
7210 * 136 - PF0 default prod; 137 - PF1 default prod;
7211 * 138 - PF2 default prod; 139 - PF3 default prod;
7212 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7213 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7216 * E1.5 mode - In backward compatible mode;
7217 * for non default SB; each even line in the memory
7218 * holds the U producer and each odd line hold
7219 * the C producer. The first 128 producers are for
7220 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7221 * producers are for the DSB for each PF.
7222 * Each PF has five segments: (the order inside each
7223 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7224 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7225 * 144-147 attn prods;
7227 /* non-default-status-blocks */
7228 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7229 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7230 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7231 prod_offset = (bp->igu_base_sb + sb_idx) *
7234 for (i = 0; i < num_segs; i++) {
7235 addr = IGU_REG_PROD_CONS_MEMORY +
7236 (prod_offset + i) * 4;
7237 REG_WR(bp, addr, 0);
7239 /* send consumer update with value 0 */
7240 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7241 USTORM_ID, 0, IGU_INT_NOP, 1);
7242 bnx2x_igu_clear_sb(bp,
7243 bp->igu_base_sb + sb_idx);
7246 /* default-status-blocks */
7247 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7248 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7250 if (CHIP_MODE_IS_4_PORT(bp))
7251 dsb_idx = BP_FUNC(bp);
7253 dsb_idx = BP_VN(bp);
7255 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7256 IGU_BC_BASE_DSB_PROD + dsb_idx :
7257 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7260 * igu prods come in chunks of E1HVN_MAX (4) -
7261 * does not matters what is the current chip mode
7263 for (i = 0; i < (num_segs * E1HVN_MAX);
7265 addr = IGU_REG_PROD_CONS_MEMORY +
7266 (prod_offset + i)*4;
7267 REG_WR(bp, addr, 0);
7269 /* send consumer update with 0 */
7270 if (CHIP_INT_MODE_IS_BC(bp)) {
7271 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7272 USTORM_ID, 0, IGU_INT_NOP, 1);
7273 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7274 CSTORM_ID, 0, IGU_INT_NOP, 1);
7275 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7276 XSTORM_ID, 0, IGU_INT_NOP, 1);
7277 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7278 TSTORM_ID, 0, IGU_INT_NOP, 1);
7279 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7280 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7282 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7283 USTORM_ID, 0, IGU_INT_NOP, 1);
7284 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7285 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7287 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7289 /* !!! these should become driver const once
7290 rf-tool supports split-68 const */
7291 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7292 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7293 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7294 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7295 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7296 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7300 /* Reset PCIE errors for debug */
7301 REG_WR(bp, 0x2114, 0xffffffff);
7302 REG_WR(bp, 0x2120, 0xffffffff);
7304 if (CHIP_IS_E1x(bp)) {
7305 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7306 main_mem_base = HC_REG_MAIN_MEMORY +
7307 BP_PORT(bp) * (main_mem_size * 4);
7308 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7311 val = REG_RD(bp, main_mem_prty_clr);
7314 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7317 /* Clear "false" parity errors in MSI-X table */
7318 for (i = main_mem_base;
7319 i < main_mem_base + main_mem_size * 4;
7320 i += main_mem_width) {
7321 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7322 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7323 i, main_mem_width / 4);
7325 /* Clear HC parity attention */
7326 REG_RD(bp, main_mem_prty_clr);
7329 #ifdef BNX2X_STOP_ON_ERROR
7330 /* Enable STORMs SP logging */
7331 REG_WR8(bp, BAR_USTRORM_INTMEM +
7332 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7333 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7334 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7335 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7336 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7337 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7338 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7341 bnx2x_phy_probe(&bp->link_params);
7347 void bnx2x_free_mem(struct bnx2x *bp)
7352 bnx2x_free_fp_mem(bp);
7353 /* end of fastpath */
7355 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7356 sizeof(struct host_sp_status_block));
7358 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7359 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7361 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7362 sizeof(struct bnx2x_slowpath));
7364 for (i = 0; i < L2_ILT_LINES(bp); i++)
7365 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7366 bp->context[i].size);
7367 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7369 BNX2X_FREE(bp->ilt->lines);
7372 if (!CHIP_IS_E1x(bp))
7373 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7374 sizeof(struct host_hc_status_block_e2));
7376 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7377 sizeof(struct host_hc_status_block_e1x));
7379 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7382 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7384 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7385 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7388 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7391 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7393 /* number of queues for statistics is number of eth queues + FCoE */
7394 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7396 /* Total number of FW statistics requests =
7397 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7400 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7403 /* Request is built from stats_query_header and an array of
7404 * stats_query_cmd_group each of which contains
7405 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7406 * configured in the stats_query_header.
7408 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7409 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7411 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7412 num_groups * sizeof(struct stats_query_cmd_group);
7414 /* Data for statistics requests + stats_conter
7416 * stats_counter holds per-STORM counters that are incremented
7417 * when STORM has finished with the current request.
7419 * memory for FCoE offloaded statistics are counted anyway,
7420 * even if they will not be sent.
7422 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7423 sizeof(struct per_pf_stats) +
7424 sizeof(struct fcoe_statistics_params) +
7425 sizeof(struct per_queue_stats) * num_queue_stats +
7426 sizeof(struct stats_counter);
7428 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7429 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7432 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7433 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7435 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7436 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7438 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7439 bp->fw_stats_req_sz;
7443 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7444 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7445 BNX2X_ERR("Can't allocate memory\n");
7450 int bnx2x_alloc_mem(struct bnx2x *bp)
7452 int i, allocated, context_size;
7455 if (!CHIP_IS_E1x(bp))
7456 /* size = the status block + ramrod buffers */
7457 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7458 sizeof(struct host_hc_status_block_e2));
7460 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7461 sizeof(struct host_hc_status_block_e1x));
7463 /* allocate searcher T2 table */
7464 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7468 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7469 sizeof(struct host_sp_status_block));
7471 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7472 sizeof(struct bnx2x_slowpath));
7475 /* write address to which L5 should insert its values */
7476 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7479 /* Allocated memory for FW statistics */
7480 if (bnx2x_alloc_fw_stats_mem(bp))
7483 /* Allocate memory for CDU context:
7484 * This memory is allocated separately and not in the generic ILT
7485 * functions because CDU differs in few aspects:
7486 * 1. There are multiple entities allocating memory for context -
7487 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7488 * its own ILT lines.
7489 * 2. Since CDU page-size is not a single 4KB page (which is the case
7490 * for the other ILT clients), to be efficient we want to support
7491 * allocation of sub-page-size in the last entry.
7492 * 3. Context pointers are used by the driver to pass to FW / update
7493 * the context (for the other ILT clients the pointers are used just to
7494 * free the memory during unload).
7496 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7498 for (i = 0, allocated = 0; allocated < context_size; i++) {
7499 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7500 (context_size - allocated));
7501 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7502 &bp->context[i].cxt_mapping,
7503 bp->context[i].size);
7504 allocated += bp->context[i].size;
7506 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7508 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7511 /* Slow path ring */
7512 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7515 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7516 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7520 /* need to be done at the end, since it's self adjusting to amount
7521 * of memory available for RSS queues
7523 if (bnx2x_alloc_fp_mem(bp))
7529 BNX2X_ERR("Can't allocate memory\n");
7534 * Init service functions
7537 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7538 struct bnx2x_vlan_mac_obj *obj, bool set,
7539 int mac_type, unsigned long *ramrod_flags)
7542 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7544 memset(&ramrod_param, 0, sizeof(ramrod_param));
7546 /* Fill general parameters */
7547 ramrod_param.vlan_mac_obj = obj;
7548 ramrod_param.ramrod_flags = *ramrod_flags;
7550 /* Fill a user request section if needed */
7551 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7552 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7554 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7556 /* Set the command: ADD or DEL */
7558 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7560 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7563 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7565 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7569 int bnx2x_del_all_macs(struct bnx2x *bp,
7570 struct bnx2x_vlan_mac_obj *mac_obj,
7571 int mac_type, bool wait_for_comp)
7574 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7576 /* Wait for completion of requested */
7578 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7580 /* Set the mac type of addresses we want to clear */
7581 __set_bit(mac_type, &vlan_mac_flags);
7583 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7585 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7590 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7592 unsigned long ramrod_flags = 0;
7595 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7596 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7597 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7598 "Ignoring Zero MAC for STORAGE SD mode\n");
7603 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7605 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7606 /* Eth MAC is set on RSS leading client (fp[0]) */
7607 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7608 set, BNX2X_ETH_MAC, &ramrod_flags);
7611 int bnx2x_setup_leading(struct bnx2x *bp)
7613 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7617 * bnx2x_set_int_mode - configure interrupt mode
7619 * @bp: driver handle
7621 * In case of MSI-X it will also try to enable MSI-X.
7623 void bnx2x_set_int_mode(struct bnx2x *bp)
7627 bnx2x_enable_msi(bp);
7628 /* falling through... */
7630 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7631 BNX2X_DEV_INFO("set number of queues to 1\n");
7634 /* if we can't use MSI-X we only need one fp,
7635 * so try to enable MSI-X with the requested number of fp's
7636 * and fallback to MSI or legacy INTx with one fp
7638 if (bnx2x_enable_msix(bp) ||
7639 bp->flags & USING_SINGLE_MSIX_FLAG) {
7640 /* failed to enable multiple MSI-X */
7641 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7642 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7644 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7646 /* Try to enable MSI */
7647 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7648 !(bp->flags & DISABLE_MSI_FLAG))
7649 bnx2x_enable_msi(bp);
7655 /* must be called prioir to any HW initializations */
7656 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7658 return L2_ILT_LINES(bp);
7661 void bnx2x_ilt_set_info(struct bnx2x *bp)
7663 struct ilt_client_info *ilt_client;
7664 struct bnx2x_ilt *ilt = BP_ILT(bp);
7667 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7668 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7671 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7672 ilt_client->client_num = ILT_CLIENT_CDU;
7673 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7674 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7675 ilt_client->start = line;
7676 line += bnx2x_cid_ilt_lines(bp);
7678 line += CNIC_ILT_LINES;
7680 ilt_client->end = line - 1;
7682 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7685 ilt_client->page_size,
7687 ilog2(ilt_client->page_size >> 12));
7690 if (QM_INIT(bp->qm_cid_count)) {
7691 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7692 ilt_client->client_num = ILT_CLIENT_QM;
7693 ilt_client->page_size = QM_ILT_PAGE_SZ;
7694 ilt_client->flags = 0;
7695 ilt_client->start = line;
7697 /* 4 bytes for each cid */
7698 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7701 ilt_client->end = line - 1;
7704 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7707 ilt_client->page_size,
7709 ilog2(ilt_client->page_size >> 12));
7713 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7715 ilt_client->client_num = ILT_CLIENT_SRC;
7716 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7717 ilt_client->flags = 0;
7718 ilt_client->start = line;
7719 line += SRC_ILT_LINES;
7720 ilt_client->end = line - 1;
7723 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7726 ilt_client->page_size,
7728 ilog2(ilt_client->page_size >> 12));
7731 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7735 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7737 ilt_client->client_num = ILT_CLIENT_TM;
7738 ilt_client->page_size = TM_ILT_PAGE_SZ;
7739 ilt_client->flags = 0;
7740 ilt_client->start = line;
7741 line += TM_ILT_LINES;
7742 ilt_client->end = line - 1;
7745 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7748 ilt_client->page_size,
7750 ilog2(ilt_client->page_size >> 12));
7753 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7755 BUG_ON(line > ILT_MAX_LINES);
7759 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7761 * @bp: driver handle
7762 * @fp: pointer to fastpath
7763 * @init_params: pointer to parameters structure
7765 * parameters configured:
7766 * - HC configuration
7767 * - Queue's CDU context
7769 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7770 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7774 int cxt_index, cxt_offset;
7776 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7777 if (!IS_FCOE_FP(fp)) {
7778 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7779 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7781 /* If HC is supporterd, enable host coalescing in the transition
7784 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7785 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7788 init_params->rx.hc_rate = bp->rx_ticks ?
7789 (1000000 / bp->rx_ticks) : 0;
7790 init_params->tx.hc_rate = bp->tx_ticks ?
7791 (1000000 / bp->tx_ticks) : 0;
7794 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7798 * CQ index among the SB indices: FCoE clients uses the default
7799 * SB, therefore it's different.
7801 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7802 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7805 /* set maximum number of COSs supported by this queue */
7806 init_params->max_cos = fp->max_cos;
7808 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7809 fp->index, init_params->max_cos);
7811 /* set the context pointers queue object */
7812 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7813 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7814 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7816 init_params->cxts[cos] =
7817 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7821 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7822 struct bnx2x_queue_state_params *q_params,
7823 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7824 int tx_index, bool leading)
7826 memset(tx_only_params, 0, sizeof(*tx_only_params));
7828 /* Set the command */
7829 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7831 /* Set tx-only QUEUE flags: don't zero statistics */
7832 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7834 /* choose the index of the cid to send the slow path on */
7835 tx_only_params->cid_index = tx_index;
7837 /* Set general TX_ONLY_SETUP parameters */
7838 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7840 /* Set Tx TX_ONLY_SETUP parameters */
7841 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7844 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7845 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7846 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7847 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7849 /* send the ramrod */
7850 return bnx2x_queue_state_change(bp, q_params);
7855 * bnx2x_setup_queue - setup queue
7857 * @bp: driver handle
7858 * @fp: pointer to fastpath
7859 * @leading: is leading
7861 * This function performs 2 steps in a Queue state machine
7862 * actually: 1) RESET->INIT 2) INIT->SETUP
7865 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7868 struct bnx2x_queue_state_params q_params = {NULL};
7869 struct bnx2x_queue_setup_params *setup_params =
7870 &q_params.params.setup;
7871 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7872 &q_params.params.tx_only;
7876 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7878 /* reset IGU state skip FCoE L2 queue */
7879 if (!IS_FCOE_FP(fp))
7880 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7883 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7884 /* We want to wait for completion in this context */
7885 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7887 /* Prepare the INIT parameters */
7888 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7890 /* Set the command */
7891 q_params.cmd = BNX2X_Q_CMD_INIT;
7893 /* Change the state to INIT */
7894 rc = bnx2x_queue_state_change(bp, &q_params);
7896 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7900 DP(NETIF_MSG_IFUP, "init complete\n");
7903 /* Now move the Queue to the SETUP state... */
7904 memset(setup_params, 0, sizeof(*setup_params));
7906 /* Set QUEUE flags */
7907 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7909 /* Set general SETUP parameters */
7910 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7911 FIRST_TX_COS_INDEX);
7913 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7914 &setup_params->rxq_params);
7916 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7917 FIRST_TX_COS_INDEX);
7919 /* Set the command */
7920 q_params.cmd = BNX2X_Q_CMD_SETUP;
7922 /* Change the state to SETUP */
7923 rc = bnx2x_queue_state_change(bp, &q_params);
7925 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7929 /* loop through the relevant tx-only indices */
7930 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7931 tx_index < fp->max_cos;
7934 /* prepare and send tx-only ramrod*/
7935 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7936 tx_only_params, tx_index, leading);
7938 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7939 fp->index, tx_index);
7947 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7949 struct bnx2x_fastpath *fp = &bp->fp[index];
7950 struct bnx2x_fp_txdata *txdata;
7951 struct bnx2x_queue_state_params q_params = {NULL};
7954 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7956 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7957 /* We want to wait for completion in this context */
7958 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7961 /* close tx-only connections */
7962 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7963 tx_index < fp->max_cos;
7966 /* ascertain this is a normal queue*/
7967 txdata = fp->txdata_ptr[tx_index];
7969 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7972 /* send halt terminate on tx-only connection */
7973 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7974 memset(&q_params.params.terminate, 0,
7975 sizeof(q_params.params.terminate));
7976 q_params.params.terminate.cid_index = tx_index;
7978 rc = bnx2x_queue_state_change(bp, &q_params);
7982 /* send halt terminate on tx-only connection */
7983 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7984 memset(&q_params.params.cfc_del, 0,
7985 sizeof(q_params.params.cfc_del));
7986 q_params.params.cfc_del.cid_index = tx_index;
7987 rc = bnx2x_queue_state_change(bp, &q_params);
7991 /* Stop the primary connection: */
7992 /* ...halt the connection */
7993 q_params.cmd = BNX2X_Q_CMD_HALT;
7994 rc = bnx2x_queue_state_change(bp, &q_params);
7998 /* ...terminate the connection */
7999 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8000 memset(&q_params.params.terminate, 0,
8001 sizeof(q_params.params.terminate));
8002 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8003 rc = bnx2x_queue_state_change(bp, &q_params);
8006 /* ...delete cfc entry */
8007 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8008 memset(&q_params.params.cfc_del, 0,
8009 sizeof(q_params.params.cfc_del));
8010 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8011 return bnx2x_queue_state_change(bp, &q_params);
8015 static void bnx2x_reset_func(struct bnx2x *bp)
8017 int port = BP_PORT(bp);
8018 int func = BP_FUNC(bp);
8021 /* Disable the function in the FW */
8022 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8023 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8024 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8025 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8028 for_each_eth_queue(bp, i) {
8029 struct bnx2x_fastpath *fp = &bp->fp[i];
8030 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8031 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8037 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8038 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8042 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8043 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8046 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8047 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8051 if (bp->common.int_block == INT_BLOCK_HC) {
8052 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8053 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8055 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8056 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8060 /* Disable Timer scan */
8061 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8063 * Wait for at least 10ms and up to 2 second for the timers scan to
8066 for (i = 0; i < 200; i++) {
8068 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8073 bnx2x_clear_func_ilt(bp, func);
8075 /* Timers workaround bug for E2: if this is vnic-3,
8076 * we need to set the entire ilt range for this timers.
8078 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8079 struct ilt_client_info ilt_cli;
8080 /* use dummy TM client */
8081 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8083 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8084 ilt_cli.client_num = ILT_CLIENT_TM;
8086 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8089 /* this assumes that reset_port() called before reset_func()*/
8090 if (!CHIP_IS_E1x(bp))
8091 bnx2x_pf_disable(bp);
8096 static void bnx2x_reset_port(struct bnx2x *bp)
8098 int port = BP_PORT(bp);
8101 /* Reset physical Link */
8102 bnx2x__link_reset(bp);
8104 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8106 /* Do not rcv packets to BRB */
8107 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8108 /* Do not direct rcv packets that are not for MCP to the BRB */
8109 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8110 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8113 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8116 /* Check for BRB port occupancy */
8117 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8119 DP(NETIF_MSG_IFDOWN,
8120 "BRB1 is not empty %d blocks are occupied\n", val);
8122 /* TODO: Close Doorbell port? */
8125 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8127 struct bnx2x_func_state_params func_params = {NULL};
8129 /* Prepare parameters for function state transitions */
8130 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8132 func_params.f_obj = &bp->func_obj;
8133 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8135 func_params.params.hw_init.load_phase = load_code;
8137 return bnx2x_func_state_change(bp, &func_params);
8140 static int bnx2x_func_stop(struct bnx2x *bp)
8142 struct bnx2x_func_state_params func_params = {NULL};
8145 /* Prepare parameters for function state transitions */
8146 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8147 func_params.f_obj = &bp->func_obj;
8148 func_params.cmd = BNX2X_F_CMD_STOP;
8151 * Try to stop the function the 'good way'. If fails (in case
8152 * of a parity error during bnx2x_chip_cleanup()) and we are
8153 * not in a debug mode, perform a state transaction in order to
8154 * enable further HW_RESET transaction.
8156 rc = bnx2x_func_state_change(bp, &func_params);
8158 #ifdef BNX2X_STOP_ON_ERROR
8161 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8162 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8163 return bnx2x_func_state_change(bp, &func_params);
8171 * bnx2x_send_unload_req - request unload mode from the MCP.
8173 * @bp: driver handle
8174 * @unload_mode: requested function's unload mode
8176 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8178 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8181 int port = BP_PORT(bp);
8183 /* Select the UNLOAD request mode */
8184 if (unload_mode == UNLOAD_NORMAL)
8185 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8187 else if (bp->flags & NO_WOL_FLAG)
8188 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8191 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8192 u8 *mac_addr = bp->dev->dev_addr;
8196 /* The mac address is written to entries 1-4 to
8197 * preserve entry 0 which is used by the PMF
8199 u8 entry = (BP_VN(bp) + 1)*8;
8201 val = (mac_addr[0] << 8) | mac_addr[1];
8202 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8204 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8205 (mac_addr[4] << 8) | mac_addr[5];
8206 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8208 /* Enable the PME and clear the status */
8209 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8210 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8211 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8213 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8216 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8218 /* Send the request to the MCP */
8220 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8222 int path = BP_PATH(bp);
8224 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8225 path, load_count[path][0], load_count[path][1],
8226 load_count[path][2]);
8227 load_count[path][0]--;
8228 load_count[path][1 + port]--;
8229 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8230 path, load_count[path][0], load_count[path][1],
8231 load_count[path][2]);
8232 if (load_count[path][0] == 0)
8233 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8234 else if (load_count[path][1 + port] == 0)
8235 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8237 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8244 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8246 * @bp: driver handle
8248 void bnx2x_send_unload_done(struct bnx2x *bp)
8250 /* Report UNLOAD_DONE to MCP */
8252 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8255 static int bnx2x_func_wait_started(struct bnx2x *bp)
8258 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8264 * (assumption: No Attention from MCP at this stage)
8265 * PMF probably in the middle of TXdisable/enable transaction
8266 * 1. Sync IRS for default SB
8267 * 2. Sync SP queue - this guarantes us that attention handling started
8268 * 3. Wait, that TXdisable/enable transaction completes
8270 * 1+2 guranty that if DCBx attention was scheduled it already changed
8271 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8272 * received complettion for the transaction the state is TX_STOPPED.
8273 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8277 /* make sure default SB ISR is done */
8279 synchronize_irq(bp->msix_table[0].vector);
8281 synchronize_irq(bp->pdev->irq);
8283 flush_workqueue(bnx2x_wq);
8285 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8286 BNX2X_F_STATE_STARTED && tout--)
8289 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8290 BNX2X_F_STATE_STARTED) {
8291 #ifdef BNX2X_STOP_ON_ERROR
8292 BNX2X_ERR("Wrong function state\n");
8296 * Failed to complete the transaction in a "good way"
8297 * Force both transactions with CLR bit
8299 struct bnx2x_func_state_params func_params = {NULL};
8301 DP(NETIF_MSG_IFDOWN,
8302 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8304 func_params.f_obj = &bp->func_obj;
8305 __set_bit(RAMROD_DRV_CLR_ONLY,
8306 &func_params.ramrod_flags);
8308 /* STARTED-->TX_ST0PPED */
8309 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8310 bnx2x_func_state_change(bp, &func_params);
8312 /* TX_ST0PPED-->STARTED */
8313 func_params.cmd = BNX2X_F_CMD_TX_START;
8314 return bnx2x_func_state_change(bp, &func_params);
8321 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
8323 int port = BP_PORT(bp);
8326 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8329 /* Wait until tx fastpath tasks complete */
8330 for_each_tx_queue(bp, i) {
8331 struct bnx2x_fastpath *fp = &bp->fp[i];
8333 for_each_cos_in_tx_queue(fp, cos)
8334 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8335 #ifdef BNX2X_STOP_ON_ERROR
8341 /* Give HW time to discard old tx messages */
8342 usleep_range(1000, 1000);
8344 /* Clean all ETH MACs */
8345 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8348 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8350 /* Clean up UC list */
8351 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8354 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8358 if (!CHIP_IS_E1(bp))
8359 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8361 /* Set "drop all" (stop Rx).
8362 * We need to take a netif_addr_lock() here in order to prevent
8363 * a race between the completion code and this code.
8365 netif_addr_lock_bh(bp->dev);
8366 /* Schedule the rx_mode command */
8367 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8368 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8370 bnx2x_set_storm_rx_mode(bp);
8372 /* Cleanup multicast configuration */
8373 rparam.mcast_obj = &bp->mcast_obj;
8374 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8376 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8378 netif_addr_unlock_bh(bp->dev);
8383 * Send the UNLOAD_REQUEST to the MCP. This will return if
8384 * this function should perform FUNC, PORT or COMMON HW
8387 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8390 * (assumption: No Attention from MCP at this stage)
8391 * PMF probably in the middle of TXdisable/enable transaction
8393 rc = bnx2x_func_wait_started(bp);
8395 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8396 #ifdef BNX2X_STOP_ON_ERROR
8401 /* Close multi and leading connections
8402 * Completions for ramrods are collected in a synchronous way
8404 for_each_queue(bp, i)
8405 if (bnx2x_stop_queue(bp, i))
8406 #ifdef BNX2X_STOP_ON_ERROR
8411 /* If SP settings didn't get completed so far - something
8412 * very wrong has happen.
8414 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8415 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8417 #ifndef BNX2X_STOP_ON_ERROR
8420 rc = bnx2x_func_stop(bp);
8422 BNX2X_ERR("Function stop failed!\n");
8423 #ifdef BNX2X_STOP_ON_ERROR
8428 /* Disable HW interrupts, NAPI */
8429 bnx2x_netif_stop(bp, 1);
8430 /* Delete all NAPI objects */
8431 bnx2x_del_all_napi(bp);
8436 /* Reset the chip */
8437 rc = bnx2x_reset_hw(bp, reset_code);
8439 BNX2X_ERR("HW_RESET failed\n");
8442 /* Report UNLOAD_DONE to MCP */
8443 bnx2x_send_unload_done(bp);
8446 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8450 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8452 if (CHIP_IS_E1(bp)) {
8453 int port = BP_PORT(bp);
8454 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8455 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8457 val = REG_RD(bp, addr);
8459 REG_WR(bp, addr, val);
8461 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8462 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8463 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8464 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8468 /* Close gates #2, #3 and #4: */
8469 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8473 /* Gates #2 and #4a are closed/opened for "not E1" only */
8474 if (!CHIP_IS_E1(bp)) {
8476 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8478 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8482 if (CHIP_IS_E1x(bp)) {
8483 /* Prevent interrupts from HC on both ports */
8484 val = REG_RD(bp, HC_REG_CONFIG_1);
8485 REG_WR(bp, HC_REG_CONFIG_1,
8486 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8487 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8489 val = REG_RD(bp, HC_REG_CONFIG_0);
8490 REG_WR(bp, HC_REG_CONFIG_0,
8491 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8492 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8494 /* Prevent incomming interrupts in IGU */
8495 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8497 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8499 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8500 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8503 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8504 close ? "closing" : "opening");
8508 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8510 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8512 /* Do some magic... */
8513 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8514 *magic_val = val & SHARED_MF_CLP_MAGIC;
8515 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8519 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8521 * @bp: driver handle
8522 * @magic_val: old value of the `magic' bit.
8524 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8526 /* Restore the `magic' bit value... */
8527 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8528 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8529 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8533 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8535 * @bp: driver handle
8536 * @magic_val: old value of 'magic' bit.
8538 * Takes care of CLP configurations.
8540 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8543 u32 validity_offset;
8545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8547 /* Set `magic' bit in order to save MF config */
8548 if (!CHIP_IS_E1(bp))
8549 bnx2x_clp_reset_prep(bp, magic_val);
8551 /* Get shmem offset */
8552 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8553 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8555 /* Clear validity map flags */
8557 REG_WR(bp, shmem + validity_offset, 0);
8560 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8561 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8564 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8566 * @bp: driver handle
8568 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8570 /* special handling for emulation and FPGA,
8571 wait 10 times longer */
8572 if (CHIP_REV_IS_SLOW(bp))
8573 msleep(MCP_ONE_TIMEOUT*10);
8575 msleep(MCP_ONE_TIMEOUT);
8579 * initializes bp->common.shmem_base and waits for validity signature to appear
8581 static int bnx2x_init_shmem(struct bnx2x *bp)
8587 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8588 if (bp->common.shmem_base) {
8589 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8590 if (val & SHR_MEM_VALIDITY_MB)
8594 bnx2x_mcp_wait_one(bp);
8596 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8598 BNX2X_ERR("BAD MCP validity signature\n");
8603 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8605 int rc = bnx2x_init_shmem(bp);
8607 /* Restore the `magic' bit value */
8608 if (!CHIP_IS_E1(bp))
8609 bnx2x_clp_reset_done(bp, magic_val);
8614 static void bnx2x_pxp_prep(struct bnx2x *bp)
8616 if (!CHIP_IS_E1(bp)) {
8617 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8618 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8624 * Reset the whole chip except for:
8626 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8629 * - MISC (including AEU)
8633 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8635 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8636 u32 global_bits2, stay_reset2;
8639 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8640 * (per chip) blocks.
8643 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8644 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8646 /* Don't reset the following blocks */
8648 MISC_REGISTERS_RESET_REG_1_RST_HC |
8649 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8650 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8653 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8654 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8655 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8656 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8657 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8658 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8659 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8660 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8661 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8662 MISC_REGISTERS_RESET_REG_2_PGLC;
8665 * Keep the following blocks in reset:
8666 * - all xxMACs are handled by the bnx2x_link code.
8669 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8670 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8671 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8672 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8673 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8674 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8675 MISC_REGISTERS_RESET_REG_2_XMAC |
8676 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8678 /* Full reset masks according to the chip */
8679 reset_mask1 = 0xffffffff;
8682 reset_mask2 = 0xffff;
8683 else if (CHIP_IS_E1H(bp))
8684 reset_mask2 = 0x1ffff;
8685 else if (CHIP_IS_E2(bp))
8686 reset_mask2 = 0xfffff;
8687 else /* CHIP_IS_E3 */
8688 reset_mask2 = 0x3ffffff;
8690 /* Don't reset global blocks unless we need to */
8692 reset_mask2 &= ~global_bits2;
8695 * In case of attention in the QM, we need to reset PXP
8696 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8697 * because otherwise QM reset would release 'close the gates' shortly
8698 * before resetting the PXP, then the PSWRQ would send a write
8699 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8700 * read the payload data from PSWWR, but PSWWR would not
8701 * respond. The write queue in PGLUE would stuck, dmae commands
8702 * would not return. Therefore it's important to reset the second
8703 * reset register (containing the
8704 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8705 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8708 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8709 reset_mask2 & (~not_reset_mask2));
8711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8712 reset_mask1 & (~not_reset_mask1));
8717 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8718 reset_mask2 & (~stay_reset2));
8723 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8728 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8729 * It should get cleared in no more than 1s.
8731 * @bp: driver handle
8733 * It should get cleared in no more than 1s. Returns 0 if
8734 * pending writes bit gets cleared.
8736 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8742 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8747 usleep_range(1000, 1000);
8748 } while (cnt-- > 0);
8751 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8759 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8763 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8766 /* Empty the Tetris buffer, wait for 1s */
8768 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8769 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8770 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8771 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8772 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8773 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8774 ((port_is_idle_0 & 0x1) == 0x1) &&
8775 ((port_is_idle_1 & 0x1) == 0x1) &&
8776 (pgl_exp_rom2 == 0xffffffff))
8778 usleep_range(1000, 1000);
8779 } while (cnt-- > 0);
8782 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8783 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8784 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8791 /* Close gates #2, #3 and #4 */
8792 bnx2x_set_234_gates(bp, true);
8794 /* Poll for IGU VQs for 57712 and newer chips */
8795 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8799 /* TBD: Indicate that "process kill" is in progress to MCP */
8801 /* Clear "unprepared" bit */
8802 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8805 /* Make sure all is written to the chip before the reset */
8808 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8809 * PSWHST, GRC and PSWRD Tetris buffer.
8811 usleep_range(1000, 1000);
8813 /* Prepare to chip reset: */
8816 bnx2x_reset_mcp_prep(bp, &val);
8822 /* reset the chip */
8823 bnx2x_process_kill_chip_reset(bp, global);
8826 /* Recover after reset: */
8828 if (global && bnx2x_reset_mcp_comp(bp, val))
8831 /* TBD: Add resetting the NO_MCP mode DB here */
8836 /* Open the gates #2, #3 and #4 */
8837 bnx2x_set_234_gates(bp, false);
8839 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8840 * reset state, re-enable attentions. */
8845 int bnx2x_leader_reset(struct bnx2x *bp)
8848 bool global = bnx2x_reset_is_global(bp);
8851 /* if not going to reset MCP - load "fake" driver to reset HW while
8852 * driver is owner of the HW
8854 if (!global && !BP_NOMCP(bp)) {
8855 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8857 BNX2X_ERR("MCP response failure, aborting\n");
8859 goto exit_leader_reset;
8861 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8862 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8863 BNX2X_ERR("MCP unexpected resp, aborting\n");
8865 goto exit_leader_reset2;
8867 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8869 BNX2X_ERR("MCP response failure, aborting\n");
8871 goto exit_leader_reset2;
8875 /* Try to recover after the failure */
8876 if (bnx2x_process_kill(bp, global)) {
8877 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8880 goto exit_leader_reset2;
8884 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8887 bnx2x_set_reset_done(bp);
8889 bnx2x_clear_reset_global(bp);
8892 /* unload "fake driver" if it was loaded */
8893 if (!global && !BP_NOMCP(bp)) {
8894 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8895 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8899 bnx2x_release_leader_lock(bp);
8904 static void bnx2x_recovery_failed(struct bnx2x *bp)
8906 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8908 /* Disconnect this device */
8909 netif_device_detach(bp->dev);
8912 * Block ifup for all function on this engine until "process kill"
8915 bnx2x_set_reset_in_progress(bp);
8917 /* Shut down the power */
8918 bnx2x_set_power_state(bp, PCI_D3hot);
8920 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8926 * Assumption: runs under rtnl lock. This together with the fact
8927 * that it's called only from bnx2x_sp_rtnl() ensure that it
8928 * will never be called when netif_running(bp->dev) is false.
8930 static void bnx2x_parity_recover(struct bnx2x *bp)
8932 bool global = false;
8933 u32 error_recovered, error_unrecovered;
8936 DP(NETIF_MSG_HW, "Handling parity\n");
8938 switch (bp->recovery_state) {
8939 case BNX2X_RECOVERY_INIT:
8940 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8941 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8942 WARN_ON(!is_parity);
8944 /* Try to get a LEADER_LOCK HW lock */
8945 if (bnx2x_trylock_leader_lock(bp)) {
8946 bnx2x_set_reset_in_progress(bp);
8948 * Check if there is a global attention and if
8949 * there was a global attention, set the global
8954 bnx2x_set_reset_global(bp);
8959 /* Stop the driver */
8960 /* If interface has been removed - break */
8961 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8964 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8966 /* Ensure "is_leader", MCP command sequence and
8967 * "recovery_state" update values are seen on other
8973 case BNX2X_RECOVERY_WAIT:
8974 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8975 if (bp->is_leader) {
8976 int other_engine = BP_PATH(bp) ? 0 : 1;
8977 bool other_load_status =
8978 bnx2x_get_load_status(bp, other_engine);
8980 bnx2x_get_load_status(bp, BP_PATH(bp));
8981 global = bnx2x_reset_is_global(bp);
8984 * In case of a parity in a global block, let
8985 * the first leader that performs a
8986 * leader_reset() reset the global blocks in
8987 * order to clear global attentions. Otherwise
8988 * the the gates will remain closed for that
8992 (global && other_load_status)) {
8993 /* Wait until all other functions get
8996 schedule_delayed_work(&bp->sp_rtnl_task,
9000 /* If all other functions got down -
9001 * try to bring the chip back to
9002 * normal. In any case it's an exit
9003 * point for a leader.
9005 if (bnx2x_leader_reset(bp)) {
9006 bnx2x_recovery_failed(bp);
9010 /* If we are here, means that the
9011 * leader has succeeded and doesn't
9012 * want to be a leader any more. Try
9013 * to continue as a none-leader.
9017 } else { /* non-leader */
9018 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9019 /* Try to get a LEADER_LOCK HW lock as
9020 * long as a former leader may have
9021 * been unloaded by the user or
9022 * released a leadership by another
9025 if (bnx2x_trylock_leader_lock(bp)) {
9026 /* I'm a leader now! Restart a
9033 schedule_delayed_work(&bp->sp_rtnl_task,
9039 * If there was a global attention, wait
9040 * for it to be cleared.
9042 if (bnx2x_reset_is_global(bp)) {
9043 schedule_delayed_work(
9050 bp->eth_stats.recoverable_error;
9052 bp->eth_stats.unrecoverable_error;
9053 bp->recovery_state =
9054 BNX2X_RECOVERY_NIC_LOADING;
9055 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9056 error_unrecovered++;
9058 "Recovery failed. Power cycle needed\n");
9059 /* Disconnect this device */
9060 netif_device_detach(bp->dev);
9061 /* Shut down the power */
9062 bnx2x_set_power_state(
9066 bp->recovery_state =
9067 BNX2X_RECOVERY_DONE;
9071 bp->eth_stats.recoverable_error =
9073 bp->eth_stats.unrecoverable_error =
9085 static int bnx2x_close(struct net_device *dev);
9087 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9088 * scheduled on a general queue in order to prevent a dead lock.
9090 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9092 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9096 if (!netif_running(bp->dev))
9099 /* if stop on error is defined no recovery flows should be executed */
9100 #ifdef BNX2X_STOP_ON_ERROR
9101 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9102 "you will need to reboot when done\n");
9103 goto sp_rtnl_not_reset;
9106 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9108 * Clear all pending SP commands as we are going to reset the
9111 bp->sp_rtnl_state = 0;
9114 bnx2x_parity_recover(bp);
9119 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9121 * Clear all pending SP commands as we are going to reset the
9124 bp->sp_rtnl_state = 0;
9127 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9128 bnx2x_nic_load(bp, LOAD_NORMAL);
9132 #ifdef BNX2X_STOP_ON_ERROR
9135 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9136 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9137 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9138 bnx2x_after_function_update(bp);
9140 * in case of fan failure we need to reset id if the "stop on error"
9141 * debug flag is set, since we trying to prevent permanent overheating
9144 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9145 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9146 netif_device_detach(bp->dev);
9147 bnx2x_close(bp->dev);
9154 /* end of nic load/unload */
9156 static void bnx2x_period_task(struct work_struct *work)
9158 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9160 if (!netif_running(bp->dev))
9161 goto period_task_exit;
9163 if (CHIP_REV_IS_SLOW(bp)) {
9164 BNX2X_ERR("period task called on emulation, ignoring\n");
9165 goto period_task_exit;
9168 bnx2x_acquire_phy_lock(bp);
9170 * The barrier is needed to ensure the ordering between the writing to
9171 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9176 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9178 /* Re-queue task in 1 sec */
9179 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9182 bnx2x_release_phy_lock(bp);
9188 * Init service functions
9191 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9193 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9194 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9195 return base + (BP_ABS_FUNC(bp)) * stride;
9198 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9200 u32 reg = bnx2x_get_pretend_reg(bp);
9202 /* Flush all outstanding writes */
9205 /* Pretend to be function 0 */
9207 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9209 /* From now we are in the "like-E1" mode */
9210 bnx2x_int_disable(bp);
9212 /* Flush all outstanding writes */
9215 /* Restore the original function */
9216 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9220 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9223 bnx2x_int_disable(bp);
9225 bnx2x_undi_int_disable_e1h(bp);
9228 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9230 u32 val, base_addr, offset, mask, reset_reg;
9231 bool mac_stopped = false;
9232 u8 port = BP_PORT(bp);
9234 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9236 if (!CHIP_IS_E3(bp)) {
9237 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9238 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9239 if ((mask & reset_reg) && val) {
9241 BNX2X_DEV_INFO("Disable bmac Rx\n");
9242 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9243 : NIG_REG_INGRESS_BMAC0_MEM;
9244 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9245 : BIGMAC_REGISTER_BMAC_CONTROL;
9248 * use rd/wr since we cannot use dmae. This is safe
9249 * since MCP won't access the bus due to the request
9250 * to unload, and no function on the path can be
9251 * loaded at this time.
9253 wb_data[0] = REG_RD(bp, base_addr + offset);
9254 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9255 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9256 REG_WR(bp, base_addr + offset, wb_data[0]);
9257 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9260 BNX2X_DEV_INFO("Disable emac Rx\n");
9261 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9265 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9266 BNX2X_DEV_INFO("Disable xmac Rx\n");
9267 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9268 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9269 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9271 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9273 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9276 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9277 if (mask & reset_reg) {
9278 BNX2X_DEV_INFO("Disable umac Rx\n");
9279 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9280 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9290 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9291 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9292 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9293 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9295 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9299 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9301 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9302 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9304 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9305 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9307 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9311 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9313 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9315 BNX2X_ERR("MCP response failure, aborting\n");
9322 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9324 struct bnx2x_prev_path_list *tmp_list;
9327 if (down_trylock(&bnx2x_prev_sem))
9330 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9331 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9332 bp->pdev->bus->number == tmp_list->bus &&
9333 BP_PATH(bp) == tmp_list->path) {
9335 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9341 up(&bnx2x_prev_sem);
9346 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9348 struct bnx2x_prev_path_list *tmp_list;
9351 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9353 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9357 tmp_list->bus = bp->pdev->bus->number;
9358 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9359 tmp_list->path = BP_PATH(bp);
9361 rc = down_interruptible(&bnx2x_prev_sem);
9363 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9366 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9368 list_add(&tmp_list->list, &bnx2x_prev_list);
9369 up(&bnx2x_prev_sem);
9375 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9379 struct pci_dev *dev = bp->pdev;
9382 if (CHIP_IS_E1x(bp)) {
9383 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9387 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9388 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9389 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9394 pos = pci_pcie_cap(dev);
9398 /* Wait for Transaction Pending bit clean */
9399 for (i = 0; i < 4; i++) {
9401 msleep((1 << (i - 1)) * 100);
9403 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9404 if (!(status & PCI_EXP_DEVSTA_TRPND))
9409 "transaction is not cleared; proceeding with reset anyway\n");
9413 BNX2X_DEV_INFO("Initiating FLR\n");
9414 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9419 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9423 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9425 /* Test if previous unload process was already finished for this path */
9426 if (bnx2x_prev_is_path_marked(bp))
9427 return bnx2x_prev_mcp_done(bp);
9429 /* If function has FLR capabilities, and existing FW version matches
9430 * the one required, then FLR will be sufficient to clean any residue
9431 * left by previous driver
9433 rc = bnx2x_test_firmware_version(bp, false);
9436 /* fw version is good */
9437 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9438 rc = bnx2x_do_flr(bp);
9442 /* FLR was performed */
9443 BNX2X_DEV_INFO("FLR successful\n");
9447 BNX2X_DEV_INFO("Could not FLR\n");
9449 /* Close the MCP request, return failure*/
9450 rc = bnx2x_prev_mcp_done(bp);
9452 rc = BNX2X_PREV_WAIT_NEEDED;
9457 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9459 u32 reset_reg, tmp_reg = 0, rc;
9460 /* It is possible a previous function received 'common' answer,
9461 * but hasn't loaded yet, therefore creating a scenario of
9462 * multiple functions receiving 'common' on the same path.
9464 BNX2X_DEV_INFO("Common unload Flow\n");
9466 if (bnx2x_prev_is_path_marked(bp))
9467 return bnx2x_prev_mcp_done(bp);
9469 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9471 /* Reset should be performed after BRB is emptied */
9472 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9473 u32 timer_count = 1000;
9474 bool prev_undi = false;
9476 /* Close the MAC Rx to prevent BRB from filling up */
9477 bnx2x_prev_unload_close_mac(bp);
9479 /* Check if the UNDI driver was previously loaded
9480 * UNDI driver initializes CID offset for normal bell to 0x7
9482 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9483 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9484 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9485 if (tmp_reg == 0x7) {
9486 BNX2X_DEV_INFO("UNDI previously loaded\n");
9488 /* clear the UNDI indication */
9489 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9492 /* wait until BRB is empty */
9493 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9494 while (timer_count) {
9495 u32 prev_brb = tmp_reg;
9497 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9501 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9503 /* reset timer as long as BRB actually gets emptied */
9504 if (prev_brb > tmp_reg)
9509 /* If UNDI resides in memory, manually increment it */
9511 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9517 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9521 /* No packets are in the pipeline, path is ready for reset */
9522 bnx2x_reset_common(bp);
9524 rc = bnx2x_prev_mark_path(bp);
9526 bnx2x_prev_mcp_done(bp);
9530 return bnx2x_prev_mcp_done(bp);
9533 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9534 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9535 * the addresses of the transaction, resulting in was-error bit set in the pci
9536 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9537 * to clear the interrupt which detected this from the pglueb and the was done
9540 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9542 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9543 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9544 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9545 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9549 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9551 int time_counter = 10;
9552 u32 rc, fw, hw_lock_reg, hw_lock_val;
9553 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9555 /* clear hw from errors which may have resulted from an interrupted
9558 bnx2x_prev_interrupted_dmae(bp);
9560 /* Release previously held locks */
9561 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9562 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9563 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9565 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9567 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9568 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9569 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9570 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9573 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9574 REG_WR(bp, hw_lock_reg, 0xffffffff);
9576 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9578 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9579 BNX2X_DEV_INFO("Release previously held alr\n");
9580 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9585 /* Lock MCP using an unload request */
9586 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9588 BNX2X_ERR("MCP response failure, aborting\n");
9593 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9594 rc = bnx2x_prev_unload_common(bp);
9598 /* non-common reply from MCP night require looping */
9599 rc = bnx2x_prev_unload_uncommon(bp);
9600 if (rc != BNX2X_PREV_WAIT_NEEDED)
9604 } while (--time_counter);
9606 if (!time_counter || rc) {
9607 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9611 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9616 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9618 u32 val, val2, val3, val4, id, boot_mode;
9621 /* Get the chip revision id and number. */
9622 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9623 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9624 id = ((val & 0xffff) << 16);
9625 val = REG_RD(bp, MISC_REG_CHIP_REV);
9626 id |= ((val & 0xf) << 12);
9627 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9628 id |= ((val & 0xff) << 4);
9629 val = REG_RD(bp, MISC_REG_BOND_ID);
9631 bp->common.chip_id = id;
9633 /* force 57811 according to MISC register */
9634 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9635 if (CHIP_IS_57810(bp))
9636 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9637 (bp->common.chip_id & 0x0000FFFF);
9638 else if (CHIP_IS_57810_MF(bp))
9639 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9640 (bp->common.chip_id & 0x0000FFFF);
9641 bp->common.chip_id |= 0x1;
9644 /* Set doorbell size */
9645 bp->db_size = (1 << BNX2X_DB_SHIFT);
9647 if (!CHIP_IS_E1x(bp)) {
9648 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9650 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9652 val = (val >> 1) & 1;
9653 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9655 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9658 if (CHIP_MODE_IS_4_PORT(bp))
9659 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9661 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9663 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9664 bp->pfid = bp->pf_num; /* 0..7 */
9667 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9669 bp->link_params.chip_id = bp->common.chip_id;
9670 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9672 val = (REG_RD(bp, 0x2874) & 0x55);
9673 if ((bp->common.chip_id & 0x1) ||
9674 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9675 bp->flags |= ONE_PORT_FLAG;
9676 BNX2X_DEV_INFO("single port device\n");
9679 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9680 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9681 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9682 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9683 bp->common.flash_size, bp->common.flash_size);
9685 bnx2x_init_shmem(bp);
9689 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9690 MISC_REG_GENERIC_CR_1 :
9691 MISC_REG_GENERIC_CR_0));
9693 bp->link_params.shmem_base = bp->common.shmem_base;
9694 bp->link_params.shmem2_base = bp->common.shmem2_base;
9695 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9696 bp->common.shmem_base, bp->common.shmem2_base);
9698 if (!bp->common.shmem_base) {
9699 BNX2X_DEV_INFO("MCP not active\n");
9700 bp->flags |= NO_MCP_FLAG;
9704 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9705 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9707 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9708 SHARED_HW_CFG_LED_MODE_MASK) >>
9709 SHARED_HW_CFG_LED_MODE_SHIFT);
9711 bp->link_params.feature_config_flags = 0;
9712 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9713 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9714 bp->link_params.feature_config_flags |=
9715 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9717 bp->link_params.feature_config_flags &=
9718 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9720 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9721 bp->common.bc_ver = val;
9722 BNX2X_DEV_INFO("bc_ver %X\n", val);
9723 if (val < BNX2X_BC_VER) {
9724 /* for now only warn
9725 * later we might need to enforce this */
9726 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9729 bp->link_params.feature_config_flags |=
9730 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9731 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9733 bp->link_params.feature_config_flags |=
9734 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9735 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9736 bp->link_params.feature_config_flags |=
9737 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9738 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9739 bp->link_params.feature_config_flags |=
9740 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9741 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9742 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9743 BC_SUPPORTS_PFC_STATS : 0;
9745 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9746 BC_SUPPORTS_FCOE_FEATURES : 0;
9748 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9749 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9750 boot_mode = SHMEM_RD(bp,
9751 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9752 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9753 switch (boot_mode) {
9754 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9755 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9757 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9758 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9760 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9761 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9763 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9764 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9768 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9769 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9771 BNX2X_DEV_INFO("%sWoL capable\n",
9772 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9774 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9775 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9776 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9777 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9779 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9780 val, val2, val3, val4);
9783 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9784 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9786 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9788 int pfid = BP_FUNC(bp);
9791 u8 fid, igu_sb_cnt = 0;
9793 bp->igu_base_sb = 0xff;
9794 if (CHIP_INT_MODE_IS_BC(bp)) {
9796 igu_sb_cnt = bp->igu_sb_cnt;
9797 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9800 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9801 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9806 /* IGU in normal mode - read CAM */
9807 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9809 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9810 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9813 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9814 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9816 if (IGU_VEC(val) == 0)
9817 /* default status block */
9818 bp->igu_dsb_id = igu_sb_id;
9820 if (bp->igu_base_sb == 0xff)
9821 bp->igu_base_sb = igu_sb_id;
9827 #ifdef CONFIG_PCI_MSI
9829 * It's expected that number of CAM entries for this functions is equal
9830 * to the number evaluated based on the MSI-X table size. We want a
9831 * harsh warning if these values are different!
9833 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9836 if (igu_sb_cnt == 0)
9837 BNX2X_ERR("CAM configuration error\n");
9840 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9843 int cfg_size = 0, idx, port = BP_PORT(bp);
9845 /* Aggregation of supported attributes of all external phys */
9846 bp->port.supported[0] = 0;
9847 bp->port.supported[1] = 0;
9848 switch (bp->link_params.num_phys) {
9850 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9854 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9858 if (bp->link_params.multi_phy_config &
9859 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9860 bp->port.supported[1] =
9861 bp->link_params.phy[EXT_PHY1].supported;
9862 bp->port.supported[0] =
9863 bp->link_params.phy[EXT_PHY2].supported;
9865 bp->port.supported[0] =
9866 bp->link_params.phy[EXT_PHY1].supported;
9867 bp->port.supported[1] =
9868 bp->link_params.phy[EXT_PHY2].supported;
9874 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9875 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9877 dev_info.port_hw_config[port].external_phy_config),
9879 dev_info.port_hw_config[port].external_phy_config2));
9884 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9886 switch (switch_cfg) {
9888 bp->port.phy_addr = REG_RD(
9889 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9891 case SWITCH_CFG_10G:
9892 bp->port.phy_addr = REG_RD(
9893 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9896 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9897 bp->port.link_config[0]);
9901 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9902 /* mask what we support according to speed_cap_mask per configuration */
9903 for (idx = 0; idx < cfg_size; idx++) {
9904 if (!(bp->link_params.speed_cap_mask[idx] &
9905 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9906 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9908 if (!(bp->link_params.speed_cap_mask[idx] &
9909 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9910 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9912 if (!(bp->link_params.speed_cap_mask[idx] &
9913 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9914 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9916 if (!(bp->link_params.speed_cap_mask[idx] &
9917 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9918 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9920 if (!(bp->link_params.speed_cap_mask[idx] &
9921 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9922 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9923 SUPPORTED_1000baseT_Full);
9925 if (!(bp->link_params.speed_cap_mask[idx] &
9926 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9927 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9929 if (!(bp->link_params.speed_cap_mask[idx] &
9930 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9931 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9935 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9936 bp->port.supported[1]);
9939 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9941 u32 link_config, idx, cfg_size = 0;
9942 bp->port.advertising[0] = 0;
9943 bp->port.advertising[1] = 0;
9944 switch (bp->link_params.num_phys) {
9953 for (idx = 0; idx < cfg_size; idx++) {
9954 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9955 link_config = bp->port.link_config[idx];
9956 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9957 case PORT_FEATURE_LINK_SPEED_AUTO:
9958 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9959 bp->link_params.req_line_speed[idx] =
9961 bp->port.advertising[idx] |=
9962 bp->port.supported[idx];
9963 if (bp->link_params.phy[EXT_PHY1].type ==
9964 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9965 bp->port.advertising[idx] |=
9966 (SUPPORTED_100baseT_Half |
9967 SUPPORTED_100baseT_Full);
9969 /* force 10G, no AN */
9970 bp->link_params.req_line_speed[idx] =
9972 bp->port.advertising[idx] |=
9973 (ADVERTISED_10000baseT_Full |
9979 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9980 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9981 bp->link_params.req_line_speed[idx] =
9983 bp->port.advertising[idx] |=
9984 (ADVERTISED_10baseT_Full |
9987 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9989 bp->link_params.speed_cap_mask[idx]);
9994 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9995 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9996 bp->link_params.req_line_speed[idx] =
9998 bp->link_params.req_duplex[idx] =
10000 bp->port.advertising[idx] |=
10001 (ADVERTISED_10baseT_Half |
10004 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10006 bp->link_params.speed_cap_mask[idx]);
10011 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10012 if (bp->port.supported[idx] &
10013 SUPPORTED_100baseT_Full) {
10014 bp->link_params.req_line_speed[idx] =
10016 bp->port.advertising[idx] |=
10017 (ADVERTISED_100baseT_Full |
10020 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10022 bp->link_params.speed_cap_mask[idx]);
10027 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10028 if (bp->port.supported[idx] &
10029 SUPPORTED_100baseT_Half) {
10030 bp->link_params.req_line_speed[idx] =
10032 bp->link_params.req_duplex[idx] =
10034 bp->port.advertising[idx] |=
10035 (ADVERTISED_100baseT_Half |
10038 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10040 bp->link_params.speed_cap_mask[idx]);
10045 case PORT_FEATURE_LINK_SPEED_1G:
10046 if (bp->port.supported[idx] &
10047 SUPPORTED_1000baseT_Full) {
10048 bp->link_params.req_line_speed[idx] =
10050 bp->port.advertising[idx] |=
10051 (ADVERTISED_1000baseT_Full |
10054 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10056 bp->link_params.speed_cap_mask[idx]);
10061 case PORT_FEATURE_LINK_SPEED_2_5G:
10062 if (bp->port.supported[idx] &
10063 SUPPORTED_2500baseX_Full) {
10064 bp->link_params.req_line_speed[idx] =
10066 bp->port.advertising[idx] |=
10067 (ADVERTISED_2500baseX_Full |
10070 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10072 bp->link_params.speed_cap_mask[idx]);
10077 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10078 if (bp->port.supported[idx] &
10079 SUPPORTED_10000baseT_Full) {
10080 bp->link_params.req_line_speed[idx] =
10082 bp->port.advertising[idx] |=
10083 (ADVERTISED_10000baseT_Full |
10086 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10088 bp->link_params.speed_cap_mask[idx]);
10092 case PORT_FEATURE_LINK_SPEED_20G:
10093 bp->link_params.req_line_speed[idx] = SPEED_20000;
10097 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10099 bp->link_params.req_line_speed[idx] =
10101 bp->port.advertising[idx] =
10102 bp->port.supported[idx];
10106 bp->link_params.req_flow_ctrl[idx] = (link_config &
10107 PORT_FEATURE_FLOW_CONTROL_MASK);
10108 if ((bp->link_params.req_flow_ctrl[idx] ==
10109 BNX2X_FLOW_CTRL_AUTO) &&
10110 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10111 bp->link_params.req_flow_ctrl[idx] =
10112 BNX2X_FLOW_CTRL_NONE;
10115 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10116 bp->link_params.req_line_speed[idx],
10117 bp->link_params.req_duplex[idx],
10118 bp->link_params.req_flow_ctrl[idx],
10119 bp->port.advertising[idx]);
10123 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10125 mac_hi = cpu_to_be16(mac_hi);
10126 mac_lo = cpu_to_be32(mac_lo);
10127 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10128 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10131 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10133 int port = BP_PORT(bp);
10135 u32 ext_phy_type, ext_phy_config, eee_mode;
10137 bp->link_params.bp = bp;
10138 bp->link_params.port = port;
10140 bp->link_params.lane_config =
10141 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10143 bp->link_params.speed_cap_mask[0] =
10145 dev_info.port_hw_config[port].speed_capability_mask);
10146 bp->link_params.speed_cap_mask[1] =
10148 dev_info.port_hw_config[port].speed_capability_mask2);
10149 bp->port.link_config[0] =
10150 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10152 bp->port.link_config[1] =
10153 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10155 bp->link_params.multi_phy_config =
10156 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10157 /* If the device is capable of WoL, set the default state according
10160 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10161 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10162 (config & PORT_FEATURE_WOL_ENABLED));
10164 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10165 bp->link_params.lane_config,
10166 bp->link_params.speed_cap_mask[0],
10167 bp->port.link_config[0]);
10169 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10170 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10171 bnx2x_phy_probe(&bp->link_params);
10172 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10174 bnx2x_link_settings_requested(bp);
10177 * If connected directly, work with the internal PHY, otherwise, work
10178 * with the external PHY
10182 dev_info.port_hw_config[port].external_phy_config);
10183 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10184 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10185 bp->mdio.prtad = bp->port.phy_addr;
10187 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10188 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10190 XGXS_EXT_PHY_ADDR(ext_phy_config);
10193 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10194 * In MF mode, it is set to cover self test cases
10197 bp->port.need_hw_lock = 1;
10199 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10200 bp->common.shmem_base,
10201 bp->common.shmem2_base);
10203 /* Configure link feature according to nvram value */
10204 eee_mode = (((SHMEM_RD(bp, dev_info.
10205 port_feature_config[port].eee_power_mode)) &
10206 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10207 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10208 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10209 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10210 EEE_MODE_ENABLE_LPI |
10211 EEE_MODE_OUTPUT_TIME;
10213 bp->link_params.eee_mode = 0;
10217 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10219 u32 no_flags = NO_ISCSI_FLAG;
10221 int port = BP_PORT(bp);
10223 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10224 drv_lic_key[port].max_iscsi_conn);
10226 /* Get the number of maximum allowed iSCSI connections */
10227 bp->cnic_eth_dev.max_iscsi_conn =
10228 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10229 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10231 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10232 bp->cnic_eth_dev.max_iscsi_conn);
10235 * If maximum allowed number of connections is zero -
10236 * disable the feature.
10238 if (!bp->cnic_eth_dev.max_iscsi_conn)
10239 bp->flags |= no_flags;
10241 bp->flags |= no_flags;
10246 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10249 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10250 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10251 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10252 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10255 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10256 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10257 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10258 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10261 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10264 int port = BP_PORT(bp);
10265 int func = BP_ABS_FUNC(bp);
10267 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10268 drv_lic_key[port].max_fcoe_conn);
10270 /* Get the number of maximum allowed FCoE connections */
10271 bp->cnic_eth_dev.max_fcoe_conn =
10272 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10273 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10275 /* Read the WWN: */
10278 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10280 dev_info.port_hw_config[port].
10281 fcoe_wwn_port_name_upper);
10282 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10284 dev_info.port_hw_config[port].
10285 fcoe_wwn_port_name_lower);
10288 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10290 dev_info.port_hw_config[port].
10291 fcoe_wwn_node_name_upper);
10292 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10294 dev_info.port_hw_config[port].
10295 fcoe_wwn_node_name_lower);
10296 } else if (!IS_MF_SD(bp)) {
10297 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10300 * Read the WWN info only if the FCoE feature is enabled for
10303 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
10304 bnx2x_get_ext_wwn_info(bp, func);
10306 } else if (IS_MF_FCOE_SD(bp))
10307 bnx2x_get_ext_wwn_info(bp, func);
10309 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10312 * If maximum allowed number of connections is zero -
10313 * disable the feature.
10315 if (!bp->cnic_eth_dev.max_fcoe_conn)
10316 bp->flags |= NO_FCOE_FLAG;
10318 bp->flags |= NO_FCOE_FLAG;
10322 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10325 * iSCSI may be dynamically disabled but reading
10326 * info here we will decrease memory usage by driver
10327 * if the feature is disabled for good
10329 bnx2x_get_iscsi_info(bp);
10330 bnx2x_get_fcoe_info(bp);
10333 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10336 int func = BP_ABS_FUNC(bp);
10337 int port = BP_PORT(bp);
10339 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10340 u8 *fip_mac = bp->fip_mac;
10343 /* Zero primary MAC configuration */
10344 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10346 if (BP_NOMCP(bp)) {
10347 BNX2X_ERROR("warning: random MAC workaround active\n");
10348 eth_hw_addr_random(bp->dev);
10349 } else if (IS_MF(bp)) {
10350 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10351 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10352 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10353 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10354 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10358 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10359 * FCoE MAC then the appropriate feature should be disabled.
10361 * In non SD mode features configuration comes from
10362 * struct func_ext_config.
10364 if (!IS_MF_SD(bp)) {
10365 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10366 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10367 val2 = MF_CFG_RD(bp, func_ext_config[func].
10368 iscsi_mac_addr_upper);
10369 val = MF_CFG_RD(bp, func_ext_config[func].
10370 iscsi_mac_addr_lower);
10371 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10372 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10375 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10377 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10378 val2 = MF_CFG_RD(bp, func_ext_config[func].
10379 fcoe_mac_addr_upper);
10380 val = MF_CFG_RD(bp, func_ext_config[func].
10381 fcoe_mac_addr_lower);
10382 bnx2x_set_mac_buf(fip_mac, val, val2);
10383 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10387 bp->flags |= NO_FCOE_FLAG;
10389 bp->mf_ext_config = cfg;
10391 } else { /* SD MODE */
10392 if (IS_MF_STORAGE_SD(bp)) {
10393 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10394 /* use primary mac as iscsi mac */
10395 memcpy(iscsi_mac, bp->dev->dev_addr,
10398 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10399 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10401 } else { /* FCoE */
10402 memcpy(fip_mac, bp->dev->dev_addr,
10404 BNX2X_DEV_INFO("SD FCoE MODE\n");
10405 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10408 /* Zero primary MAC configuration */
10409 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10413 if (IS_MF_FCOE_AFEX(bp))
10414 /* use FIP MAC as primary MAC */
10415 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10419 /* in SF read MACs from port configuration */
10420 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10421 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10422 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10425 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10427 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10429 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10431 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10432 fcoe_fip_mac_upper);
10433 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10434 fcoe_fip_mac_lower);
10435 bnx2x_set_mac_buf(fip_mac, val, val2);
10439 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10440 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10443 /* Disable iSCSI if MAC configuration is
10446 if (!is_valid_ether_addr(iscsi_mac)) {
10447 bp->flags |= NO_ISCSI_FLAG;
10448 memset(iscsi_mac, 0, ETH_ALEN);
10451 /* Disable FCoE if MAC configuration is
10454 if (!is_valid_ether_addr(fip_mac)) {
10455 bp->flags |= NO_FCOE_FLAG;
10456 memset(bp->fip_mac, 0, ETH_ALEN);
10460 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10461 dev_err(&bp->pdev->dev,
10462 "bad Ethernet MAC address configuration: %pM\n"
10463 "change it manually before bringing up the appropriate network interface\n",
10464 bp->dev->dev_addr);
10469 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10471 int /*abs*/func = BP_ABS_FUNC(bp);
10476 bnx2x_get_common_hwinfo(bp);
10479 * initialize IGU parameters
10481 if (CHIP_IS_E1x(bp)) {
10482 bp->common.int_block = INT_BLOCK_HC;
10484 bp->igu_dsb_id = DEF_SB_IGU_ID;
10485 bp->igu_base_sb = 0;
10487 bp->common.int_block = INT_BLOCK_IGU;
10489 /* do not allow device reset during IGU info preocessing */
10490 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10492 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10494 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10497 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10499 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10500 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10501 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10503 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10505 usleep_range(1000, 1000);
10508 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10509 dev_err(&bp->pdev->dev,
10510 "FORCING Normal Mode failed!!!\n");
10515 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10516 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10517 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10519 BNX2X_DEV_INFO("IGU Normal Mode\n");
10521 bnx2x_get_igu_cam_info(bp);
10523 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10527 * set base FW non-default (fast path) status block id, this value is
10528 * used to initialize the fw_sb_id saved on the fp/queue structure to
10529 * determine the id used by the FW.
10531 if (CHIP_IS_E1x(bp))
10532 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10534 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10535 * the same queue are indicated on the same IGU SB). So we prefer
10536 * FW and IGU SBs to be the same value.
10538 bp->base_fw_ndsb = bp->igu_base_sb;
10540 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10541 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10542 bp->igu_sb_cnt, bp->base_fw_ndsb);
10545 * Initialize MF configuration
10552 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10553 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10554 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10555 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10557 if (SHMEM2_HAS(bp, mf_cfg_addr))
10558 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10560 bp->common.mf_cfg_base = bp->common.shmem_base +
10561 offsetof(struct shmem_region, func_mb) +
10562 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10564 * get mf configuration:
10565 * 1. existence of MF configuration
10566 * 2. MAC address must be legal (check only upper bytes)
10567 * for Switch-Independent mode;
10568 * OVLAN must be legal for Switch-Dependent mode
10569 * 3. SF_MODE configures specific MF mode
10571 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10572 /* get mf configuration */
10574 dev_info.shared_feature_config.config);
10575 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10578 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10579 val = MF_CFG_RD(bp, func_mf_config[func].
10581 /* check for legal mac (upper bytes)*/
10582 if (val != 0xffff) {
10583 bp->mf_mode = MULTI_FUNCTION_SI;
10584 bp->mf_config[vn] = MF_CFG_RD(bp,
10585 func_mf_config[func].config);
10587 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10589 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10590 if ((!CHIP_IS_E1x(bp)) &&
10591 (MF_CFG_RD(bp, func_mf_config[func].
10592 mac_upper) != 0xffff) &&
10594 afex_driver_support))) {
10595 bp->mf_mode = MULTI_FUNCTION_AFEX;
10596 bp->mf_config[vn] = MF_CFG_RD(bp,
10597 func_mf_config[func].config);
10599 BNX2X_DEV_INFO("can not configure afex mode\n");
10602 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10603 /* get OV configuration */
10604 val = MF_CFG_RD(bp,
10605 func_mf_config[FUNC_0].e1hov_tag);
10606 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10608 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10609 bp->mf_mode = MULTI_FUNCTION_SD;
10610 bp->mf_config[vn] = MF_CFG_RD(bp,
10611 func_mf_config[func].config);
10613 BNX2X_DEV_INFO("illegal OV for SD\n");
10616 /* Unknown configuration: reset mf_config */
10617 bp->mf_config[vn] = 0;
10618 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10622 BNX2X_DEV_INFO("%s function mode\n",
10623 IS_MF(bp) ? "multi" : "single");
10625 switch (bp->mf_mode) {
10626 case MULTI_FUNCTION_SD:
10627 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10628 FUNC_MF_CFG_E1HOV_TAG_MASK;
10629 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10631 bp->path_has_ovlan = true;
10633 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10634 func, bp->mf_ov, bp->mf_ov);
10636 dev_err(&bp->pdev->dev,
10637 "No valid MF OV for func %d, aborting\n",
10642 case MULTI_FUNCTION_AFEX:
10643 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10645 case MULTI_FUNCTION_SI:
10646 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10651 dev_err(&bp->pdev->dev,
10652 "VN %d is in a single function mode, aborting\n",
10659 /* check if other port on the path needs ovlan:
10660 * Since MF configuration is shared between ports
10661 * Possible mixed modes are only
10662 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10664 if (CHIP_MODE_IS_4_PORT(bp) &&
10665 !bp->path_has_ovlan &&
10667 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10668 u8 other_port = !BP_PORT(bp);
10669 u8 other_func = BP_PATH(bp) + 2*other_port;
10670 val = MF_CFG_RD(bp,
10671 func_mf_config[other_func].e1hov_tag);
10672 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10673 bp->path_has_ovlan = true;
10677 /* adjust igu_sb_cnt to MF for E1x */
10678 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10679 bp->igu_sb_cnt /= E1HVN_MAX;
10682 bnx2x_get_port_hwinfo(bp);
10684 /* Get MAC addresses */
10685 bnx2x_get_mac_hwinfo(bp);
10687 bnx2x_get_cnic_info(bp);
10692 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10694 int cnt, i, block_end, rodi;
10695 char vpd_start[BNX2X_VPD_LEN+1];
10696 char str_id_reg[VENDOR_ID_LEN+1];
10697 char str_id_cap[VENDOR_ID_LEN+1];
10699 char *vpd_extended_data = NULL;
10702 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10703 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10705 if (cnt < BNX2X_VPD_LEN)
10706 goto out_not_found;
10708 /* VPD RO tag should be first tag after identifier string, hence
10709 * we should be able to find it in first BNX2X_VPD_LEN chars
10711 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10712 PCI_VPD_LRDT_RO_DATA);
10714 goto out_not_found;
10716 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10717 pci_vpd_lrdt_size(&vpd_start[i]);
10719 i += PCI_VPD_LRDT_TAG_SIZE;
10721 if (block_end > BNX2X_VPD_LEN) {
10722 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10723 if (vpd_extended_data == NULL)
10724 goto out_not_found;
10726 /* read rest of vpd image into vpd_extended_data */
10727 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10728 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10729 block_end - BNX2X_VPD_LEN,
10730 vpd_extended_data + BNX2X_VPD_LEN);
10731 if (cnt < (block_end - BNX2X_VPD_LEN))
10732 goto out_not_found;
10733 vpd_data = vpd_extended_data;
10735 vpd_data = vpd_start;
10737 /* now vpd_data holds full vpd content in both cases */
10739 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10740 PCI_VPD_RO_KEYWORD_MFR_ID);
10742 goto out_not_found;
10744 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10746 if (len != VENDOR_ID_LEN)
10747 goto out_not_found;
10749 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10751 /* vendor specific info */
10752 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10753 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10754 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10755 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10757 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10758 PCI_VPD_RO_KEYWORD_VENDOR0);
10760 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10762 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10764 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10765 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10766 bp->fw_ver[len] = ' ';
10769 kfree(vpd_extended_data);
10773 kfree(vpd_extended_data);
10777 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10781 if (CHIP_REV_IS_FPGA(bp))
10782 SET_FLAGS(flags, MODE_FPGA);
10783 else if (CHIP_REV_IS_EMUL(bp))
10784 SET_FLAGS(flags, MODE_EMUL);
10786 SET_FLAGS(flags, MODE_ASIC);
10788 if (CHIP_MODE_IS_4_PORT(bp))
10789 SET_FLAGS(flags, MODE_PORT4);
10791 SET_FLAGS(flags, MODE_PORT2);
10793 if (CHIP_IS_E2(bp))
10794 SET_FLAGS(flags, MODE_E2);
10795 else if (CHIP_IS_E3(bp)) {
10796 SET_FLAGS(flags, MODE_E3);
10797 if (CHIP_REV(bp) == CHIP_REV_Ax)
10798 SET_FLAGS(flags, MODE_E3_A0);
10799 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10800 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10804 SET_FLAGS(flags, MODE_MF);
10805 switch (bp->mf_mode) {
10806 case MULTI_FUNCTION_SD:
10807 SET_FLAGS(flags, MODE_MF_SD);
10809 case MULTI_FUNCTION_SI:
10810 SET_FLAGS(flags, MODE_MF_SI);
10812 case MULTI_FUNCTION_AFEX:
10813 SET_FLAGS(flags, MODE_MF_AFEX);
10817 SET_FLAGS(flags, MODE_SF);
10819 #if defined(__LITTLE_ENDIAN)
10820 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10821 #else /*(__BIG_ENDIAN)*/
10822 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10824 INIT_MODE_FLAGS(bp) = flags;
10827 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10832 mutex_init(&bp->port.phy_mutex);
10833 mutex_init(&bp->fw_mb_mutex);
10834 spin_lock_init(&bp->stats_lock);
10836 mutex_init(&bp->cnic_mutex);
10839 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10840 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10841 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10842 rc = bnx2x_get_hwinfo(bp);
10846 bnx2x_set_modes_bitmap(bp);
10848 rc = bnx2x_alloc_mem_bp(bp);
10852 bnx2x_read_fwinfo(bp);
10854 func = BP_FUNC(bp);
10856 /* need to reset chip if undi was active */
10857 if (!BP_NOMCP(bp)) {
10860 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10861 DRV_MSG_SEQ_NUMBER_MASK;
10862 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10864 bnx2x_prev_unload(bp);
10868 if (CHIP_REV_IS_FPGA(bp))
10869 dev_err(&bp->pdev->dev, "FPGA detected\n");
10871 if (BP_NOMCP(bp) && (func == 0))
10872 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10874 bp->disable_tpa = disable_tpa;
10877 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10880 /* Set TPA flags */
10881 if (bp->disable_tpa) {
10882 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10883 bp->dev->features &= ~NETIF_F_LRO;
10885 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10886 bp->dev->features |= NETIF_F_LRO;
10889 if (CHIP_IS_E1(bp))
10890 bp->dropless_fc = 0;
10892 bp->dropless_fc = dropless_fc;
10896 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10898 /* make sure that the numbers are in the right granularity */
10899 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10900 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10902 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10904 init_timer(&bp->timer);
10905 bp->timer.expires = jiffies + bp->current_interval;
10906 bp->timer.data = (unsigned long) bp;
10907 bp->timer.function = bnx2x_timer;
10909 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10910 bnx2x_dcbx_init_params(bp);
10913 if (CHIP_IS_E1x(bp))
10914 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10916 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10919 /* multiple tx priority */
10920 if (CHIP_IS_E1x(bp))
10921 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10922 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10923 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10924 if (CHIP_IS_E3B0(bp))
10925 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10931 /****************************************************************************
10932 * General service functions
10933 ****************************************************************************/
10936 * net_device service functions
10939 /* called with rtnl_lock */
10940 static int bnx2x_open(struct net_device *dev)
10942 struct bnx2x *bp = netdev_priv(dev);
10943 bool global = false;
10944 int other_engine = BP_PATH(bp) ? 0 : 1;
10945 bool other_load_status, load_status;
10947 bp->stats_init = true;
10949 netif_carrier_off(dev);
10951 bnx2x_set_power_state(bp, PCI_D0);
10953 other_load_status = bnx2x_get_load_status(bp, other_engine);
10954 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10957 * If parity had happen during the unload, then attentions
10958 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10959 * want the first function loaded on the current engine to
10960 * complete the recovery.
10962 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10963 bnx2x_chk_parity_attn(bp, &global, true))
10966 * If there are attentions and they are in a global
10967 * blocks, set the GLOBAL_RESET bit regardless whether
10968 * it will be this function that will complete the
10972 bnx2x_set_reset_global(bp);
10975 * Only the first function on the current engine should
10976 * try to recover in open. In case of attentions in
10977 * global blocks only the first in the chip should try
10980 if ((!load_status &&
10981 (!global || !other_load_status)) &&
10982 bnx2x_trylock_leader_lock(bp) &&
10983 !bnx2x_leader_reset(bp)) {
10984 netdev_info(bp->dev, "Recovered in open\n");
10988 /* recovery has failed... */
10989 bnx2x_set_power_state(bp, PCI_D3hot);
10990 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10992 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10993 "If you still see this message after a few retries then power cycle is required.\n");
10998 bp->recovery_state = BNX2X_RECOVERY_DONE;
10999 return bnx2x_nic_load(bp, LOAD_OPEN);
11002 /* called with rtnl_lock */
11003 static int bnx2x_close(struct net_device *dev)
11005 struct bnx2x *bp = netdev_priv(dev);
11007 /* Unload the driver, release IRQs */
11008 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
11011 bnx2x_set_power_state(bp, PCI_D3hot);
11016 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11017 struct bnx2x_mcast_ramrod_params *p)
11019 int mc_count = netdev_mc_count(bp->dev);
11020 struct bnx2x_mcast_list_elem *mc_mac =
11021 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11022 struct netdev_hw_addr *ha;
11027 INIT_LIST_HEAD(&p->mcast_list);
11029 netdev_for_each_mc_addr(ha, bp->dev) {
11030 mc_mac->mac = bnx2x_mc_addr(ha);
11031 list_add_tail(&mc_mac->link, &p->mcast_list);
11035 p->mcast_list_len = mc_count;
11040 static void bnx2x_free_mcast_macs_list(
11041 struct bnx2x_mcast_ramrod_params *p)
11043 struct bnx2x_mcast_list_elem *mc_mac =
11044 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11052 * bnx2x_set_uc_list - configure a new unicast MACs list.
11054 * @bp: driver handle
11056 * We will use zero (0) as a MAC type for these MACs.
11058 static int bnx2x_set_uc_list(struct bnx2x *bp)
11061 struct net_device *dev = bp->dev;
11062 struct netdev_hw_addr *ha;
11063 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11064 unsigned long ramrod_flags = 0;
11066 /* First schedule a cleanup up of old configuration */
11067 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11069 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11073 netdev_for_each_uc_addr(ha, dev) {
11074 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11075 BNX2X_UC_LIST_MAC, &ramrod_flags);
11077 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11083 /* Execute the pending commands */
11084 __set_bit(RAMROD_CONT, &ramrod_flags);
11085 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11086 BNX2X_UC_LIST_MAC, &ramrod_flags);
11089 static int bnx2x_set_mc_list(struct bnx2x *bp)
11091 struct net_device *dev = bp->dev;
11092 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11095 rparam.mcast_obj = &bp->mcast_obj;
11097 /* first, clear all configured multicast MACs */
11098 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11100 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11104 /* then, configure a new MACs list */
11105 if (netdev_mc_count(dev)) {
11106 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11108 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11113 /* Now add the new MACs */
11114 rc = bnx2x_config_mcast(bp, &rparam,
11115 BNX2X_MCAST_CMD_ADD);
11117 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11120 bnx2x_free_mcast_macs_list(&rparam);
11127 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11128 void bnx2x_set_rx_mode(struct net_device *dev)
11130 struct bnx2x *bp = netdev_priv(dev);
11131 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11133 if (bp->state != BNX2X_STATE_OPEN) {
11134 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11138 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11140 if (dev->flags & IFF_PROMISC)
11141 rx_mode = BNX2X_RX_MODE_PROMISC;
11142 else if ((dev->flags & IFF_ALLMULTI) ||
11143 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11145 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11147 /* some multicasts */
11148 if (bnx2x_set_mc_list(bp) < 0)
11149 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11151 if (bnx2x_set_uc_list(bp) < 0)
11152 rx_mode = BNX2X_RX_MODE_PROMISC;
11155 bp->rx_mode = rx_mode;
11157 /* handle ISCSI SD mode */
11158 if (IS_MF_ISCSI_SD(bp))
11159 bp->rx_mode = BNX2X_RX_MODE_NONE;
11162 /* Schedule the rx_mode command */
11163 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11164 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11168 bnx2x_set_storm_rx_mode(bp);
11171 /* called with rtnl_lock */
11172 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11173 int devad, u16 addr)
11175 struct bnx2x *bp = netdev_priv(netdev);
11179 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11180 prtad, devad, addr);
11182 /* The HW expects different devad if CL22 is used */
11183 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11185 bnx2x_acquire_phy_lock(bp);
11186 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11187 bnx2x_release_phy_lock(bp);
11188 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11195 /* called with rtnl_lock */
11196 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11197 u16 addr, u16 value)
11199 struct bnx2x *bp = netdev_priv(netdev);
11203 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11204 prtad, devad, addr, value);
11206 /* The HW expects different devad if CL22 is used */
11207 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11209 bnx2x_acquire_phy_lock(bp);
11210 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11211 bnx2x_release_phy_lock(bp);
11215 /* called with rtnl_lock */
11216 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11218 struct bnx2x *bp = netdev_priv(dev);
11219 struct mii_ioctl_data *mdio = if_mii(ifr);
11221 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11222 mdio->phy_id, mdio->reg_num, mdio->val_in);
11224 if (!netif_running(dev))
11227 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11230 #ifdef CONFIG_NET_POLL_CONTROLLER
11231 static void poll_bnx2x(struct net_device *dev)
11233 struct bnx2x *bp = netdev_priv(dev);
11236 for_each_eth_queue(bp, i) {
11237 struct bnx2x_fastpath *fp = &bp->fp[i];
11238 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11243 static int bnx2x_validate_addr(struct net_device *dev)
11245 struct bnx2x *bp = netdev_priv(dev);
11247 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11248 BNX2X_ERR("Non-valid Ethernet address\n");
11249 return -EADDRNOTAVAIL;
11254 static const struct net_device_ops bnx2x_netdev_ops = {
11255 .ndo_open = bnx2x_open,
11256 .ndo_stop = bnx2x_close,
11257 .ndo_start_xmit = bnx2x_start_xmit,
11258 .ndo_select_queue = bnx2x_select_queue,
11259 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11260 .ndo_set_mac_address = bnx2x_change_mac_addr,
11261 .ndo_validate_addr = bnx2x_validate_addr,
11262 .ndo_do_ioctl = bnx2x_ioctl,
11263 .ndo_change_mtu = bnx2x_change_mtu,
11264 .ndo_fix_features = bnx2x_fix_features,
11265 .ndo_set_features = bnx2x_set_features,
11266 .ndo_tx_timeout = bnx2x_tx_timeout,
11267 #ifdef CONFIG_NET_POLL_CONTROLLER
11268 .ndo_poll_controller = poll_bnx2x,
11270 .ndo_setup_tc = bnx2x_setup_tc,
11272 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11273 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11277 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11279 struct device *dev = &bp->pdev->dev;
11281 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11282 bp->flags |= USING_DAC_FLAG;
11283 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11284 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11287 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11288 dev_err(dev, "System does not support DMA, aborting\n");
11295 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11296 struct net_device *dev,
11297 unsigned long board_type)
11302 bool chip_is_e1x = (board_type == BCM57710 ||
11303 board_type == BCM57711 ||
11304 board_type == BCM57711E);
11306 SET_NETDEV_DEV(dev, &pdev->dev);
11307 bp = netdev_priv(dev);
11313 rc = pci_enable_device(pdev);
11315 dev_err(&bp->pdev->dev,
11316 "Cannot enable PCI device, aborting\n");
11320 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11321 dev_err(&bp->pdev->dev,
11322 "Cannot find PCI device base address, aborting\n");
11324 goto err_out_disable;
11327 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11328 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11329 " base address, aborting\n");
11331 goto err_out_disable;
11334 if (atomic_read(&pdev->enable_cnt) == 1) {
11335 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11337 dev_err(&bp->pdev->dev,
11338 "Cannot obtain PCI resources, aborting\n");
11339 goto err_out_disable;
11342 pci_set_master(pdev);
11343 pci_save_state(pdev);
11346 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11347 if (bp->pm_cap == 0) {
11348 dev_err(&bp->pdev->dev,
11349 "Cannot find power management capability, aborting\n");
11351 goto err_out_release;
11354 if (!pci_is_pcie(pdev)) {
11355 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11357 goto err_out_release;
11360 rc = bnx2x_set_coherency_mask(bp);
11362 goto err_out_release;
11364 dev->mem_start = pci_resource_start(pdev, 0);
11365 dev->base_addr = dev->mem_start;
11366 dev->mem_end = pci_resource_end(pdev, 0);
11368 dev->irq = pdev->irq;
11370 bp->regview = pci_ioremap_bar(pdev, 0);
11371 if (!bp->regview) {
11372 dev_err(&bp->pdev->dev,
11373 "Cannot map register space, aborting\n");
11375 goto err_out_release;
11378 /* In E1/E1H use pci device function given by kernel.
11379 * In E2/E3 read physical function from ME register since these chips
11380 * support Physical Device Assignment where kernel BDF maybe arbitrary
11381 * (depending on hypervisor).
11384 bp->pf_num = PCI_FUNC(pdev->devfn);
11385 else {/* chip is E2/3*/
11386 pci_read_config_dword(bp->pdev,
11387 PCICFG_ME_REGISTER, &pci_cfg_dword);
11388 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11389 ME_REG_ABS_PF_NUM_SHIFT);
11391 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11393 bnx2x_set_power_state(bp, PCI_D0);
11395 /* clean indirect addresses */
11396 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11397 PCICFG_VENDOR_ID_OFFSET);
11399 * Clean the following indirect addresses for all functions since it
11400 * is not used by the driver.
11402 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11403 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11404 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11405 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11408 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11409 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11410 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11411 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11415 * Enable internal target-read (in case we are probed after PF FLR).
11416 * Must be done prior to any BAR read access. Only for 57712 and up
11419 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11421 dev->watchdog_timeo = TX_TIMEOUT;
11423 dev->netdev_ops = &bnx2x_netdev_ops;
11424 bnx2x_set_ethtool_ops(dev);
11426 dev->priv_flags |= IFF_UNICAST_FLT;
11428 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11429 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11430 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11431 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11433 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11434 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11436 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11437 if (bp->flags & USING_DAC_FLAG)
11438 dev->features |= NETIF_F_HIGHDMA;
11440 /* Add Loopback capability to the device */
11441 dev->hw_features |= NETIF_F_LOOPBACK;
11444 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11447 /* get_port_hwinfo() will set prtad and mmds properly */
11448 bp->mdio.prtad = MDIO_PRTAD_NONE;
11450 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11451 bp->mdio.dev = dev;
11452 bp->mdio.mdio_read = bnx2x_mdio_read;
11453 bp->mdio.mdio_write = bnx2x_mdio_write;
11458 if (atomic_read(&pdev->enable_cnt) == 1)
11459 pci_release_regions(pdev);
11462 pci_disable_device(pdev);
11463 pci_set_drvdata(pdev, NULL);
11469 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11470 int *width, int *speed)
11472 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11474 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11476 /* return value of 1=2.5GHz 2=5GHz */
11477 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11480 static int bnx2x_check_firmware(struct bnx2x *bp)
11482 const struct firmware *firmware = bp->firmware;
11483 struct bnx2x_fw_file_hdr *fw_hdr;
11484 struct bnx2x_fw_file_section *sections;
11485 u32 offset, len, num_ops;
11490 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11491 BNX2X_ERR("Wrong FW size\n");
11495 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11496 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11498 /* Make sure none of the offsets and sizes make us read beyond
11499 * the end of the firmware data */
11500 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11501 offset = be32_to_cpu(sections[i].offset);
11502 len = be32_to_cpu(sections[i].len);
11503 if (offset + len > firmware->size) {
11504 BNX2X_ERR("Section %d length is out of bounds\n", i);
11509 /* Likewise for the init_ops offsets */
11510 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11511 ops_offsets = (u16 *)(firmware->data + offset);
11512 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11514 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11515 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11516 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11521 /* Check FW version */
11522 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11523 fw_ver = firmware->data + offset;
11524 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11525 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11526 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11527 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11528 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11529 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11530 BCM_5710_FW_MAJOR_VERSION,
11531 BCM_5710_FW_MINOR_VERSION,
11532 BCM_5710_FW_REVISION_VERSION,
11533 BCM_5710_FW_ENGINEERING_VERSION);
11540 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11542 const __be32 *source = (const __be32 *)_source;
11543 u32 *target = (u32 *)_target;
11546 for (i = 0; i < n/4; i++)
11547 target[i] = be32_to_cpu(source[i]);
11551 Ops array is stored in the following format:
11552 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11554 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11556 const __be32 *source = (const __be32 *)_source;
11557 struct raw_op *target = (struct raw_op *)_target;
11560 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11561 tmp = be32_to_cpu(source[j]);
11562 target[i].op = (tmp >> 24) & 0xff;
11563 target[i].offset = tmp & 0xffffff;
11564 target[i].raw_data = be32_to_cpu(source[j + 1]);
11568 /* IRO array is stored in the following format:
11569 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11571 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11573 const __be32 *source = (const __be32 *)_source;
11574 struct iro *target = (struct iro *)_target;
11577 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11578 target[i].base = be32_to_cpu(source[j]);
11580 tmp = be32_to_cpu(source[j]);
11581 target[i].m1 = (tmp >> 16) & 0xffff;
11582 target[i].m2 = tmp & 0xffff;
11584 tmp = be32_to_cpu(source[j]);
11585 target[i].m3 = (tmp >> 16) & 0xffff;
11586 target[i].size = tmp & 0xffff;
11591 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11593 const __be16 *source = (const __be16 *)_source;
11594 u16 *target = (u16 *)_target;
11597 for (i = 0; i < n/2; i++)
11598 target[i] = be16_to_cpu(source[i]);
11601 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11603 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11604 bp->arr = kmalloc(len, GFP_KERNEL); \
11607 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11608 (u8 *)bp->arr, len); \
11611 static int bnx2x_init_firmware(struct bnx2x *bp)
11613 const char *fw_file_name;
11614 struct bnx2x_fw_file_hdr *fw_hdr;
11620 if (CHIP_IS_E1(bp))
11621 fw_file_name = FW_FILE_NAME_E1;
11622 else if (CHIP_IS_E1H(bp))
11623 fw_file_name = FW_FILE_NAME_E1H;
11624 else if (!CHIP_IS_E1x(bp))
11625 fw_file_name = FW_FILE_NAME_E2;
11627 BNX2X_ERR("Unsupported chip revision\n");
11630 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11632 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11634 BNX2X_ERR("Can't load firmware file %s\n",
11636 goto request_firmware_exit;
11639 rc = bnx2x_check_firmware(bp);
11641 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11642 goto request_firmware_exit;
11645 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11647 /* Initialize the pointers to the init arrays */
11649 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11652 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11655 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11658 /* STORMs firmware */
11659 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11660 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11661 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11662 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11663 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11664 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11665 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11666 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11667 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11668 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11669 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11670 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11671 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11672 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11673 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11674 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11676 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11681 kfree(bp->init_ops_offsets);
11682 init_offsets_alloc_err:
11683 kfree(bp->init_ops);
11684 init_ops_alloc_err:
11685 kfree(bp->init_data);
11686 request_firmware_exit:
11687 release_firmware(bp->firmware);
11688 bp->firmware = NULL;
11693 static void bnx2x_release_firmware(struct bnx2x *bp)
11695 kfree(bp->init_ops_offsets);
11696 kfree(bp->init_ops);
11697 kfree(bp->init_data);
11698 release_firmware(bp->firmware);
11699 bp->firmware = NULL;
11703 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11704 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11705 .init_hw_cmn = bnx2x_init_hw_common,
11706 .init_hw_port = bnx2x_init_hw_port,
11707 .init_hw_func = bnx2x_init_hw_func,
11709 .reset_hw_cmn = bnx2x_reset_common,
11710 .reset_hw_port = bnx2x_reset_port,
11711 .reset_hw_func = bnx2x_reset_func,
11713 .gunzip_init = bnx2x_gunzip_init,
11714 .gunzip_end = bnx2x_gunzip_end,
11716 .init_fw = bnx2x_init_firmware,
11717 .release_fw = bnx2x_release_firmware,
11720 void bnx2x__init_func_obj(struct bnx2x *bp)
11722 /* Prepare DMAE related driver resources */
11723 bnx2x_setup_dmae(bp);
11725 bnx2x_init_func_obj(bp, &bp->func_obj,
11726 bnx2x_sp(bp, func_rdata),
11727 bnx2x_sp_mapping(bp, func_rdata),
11728 bnx2x_sp(bp, func_afex_rdata),
11729 bnx2x_sp_mapping(bp, func_afex_rdata),
11730 &bnx2x_func_sp_drv);
11733 /* must be called after sriov-enable */
11734 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11736 int cid_count = BNX2X_L2_MAX_CID(bp);
11739 cid_count += CNIC_CID_MAX;
11741 return roundup(cid_count, QM_CID_ROUND);
11745 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11750 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11755 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11758 * If MSI-X is not supported - return number of SBs needed to support
11759 * one fast path queue: one FP queue + SB for CNIC
11762 return 1 + CNIC_PRESENT;
11765 * The value in the PCI configuration space is the index of the last
11766 * entry, namely one less than the actual size of the table, which is
11767 * exactly what we want to return from this function: number of all SBs
11768 * without the default SB.
11770 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11771 return control & PCI_MSIX_FLAGS_QSIZE;
11774 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11775 const struct pci_device_id *ent)
11777 struct net_device *dev = NULL;
11779 int pcie_width, pcie_speed;
11780 int rc, max_non_def_sbs;
11781 int rx_count, tx_count, rss_count, doorbell_size;
11783 * An estimated maximum supported CoS number according to the chip
11785 * We will try to roughly estimate the maximum number of CoSes this chip
11786 * may support in order to minimize the memory allocated for Tx
11787 * netdev_queue's. This number will be accurately calculated during the
11788 * initialization of bp->max_cos based on the chip versions AND chip
11789 * revision in the bnx2x_init_bp().
11791 u8 max_cos_est = 0;
11793 switch (ent->driver_data) {
11797 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11802 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11810 case BCM57840_4_10:
11811 case BCM57840_2_20:
11816 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11820 pr_err("Unknown board_type (%ld), aborting\n",
11825 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11827 WARN_ON(!max_non_def_sbs);
11829 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11830 rss_count = max_non_def_sbs - CNIC_PRESENT;
11832 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11833 rx_count = rss_count + FCOE_PRESENT;
11836 * Maximum number of netdev Tx queues:
11837 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11839 tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11841 /* dev zeroed in init_etherdev */
11842 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11846 bp = netdev_priv(dev);
11848 bp->igu_sb_cnt = max_non_def_sbs;
11849 bp->msg_enable = debug;
11850 pci_set_drvdata(pdev, dev);
11852 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11858 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11860 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11861 tx_count, rx_count);
11863 rc = bnx2x_init_bp(bp);
11865 goto init_one_exit;
11868 * Map doorbels here as we need the real value of bp->max_cos which
11869 * is initialized in bnx2x_init_bp().
11871 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11872 if (doorbell_size > pci_resource_len(pdev, 2)) {
11873 dev_err(&bp->pdev->dev,
11874 "Cannot map doorbells, bar size too small, aborting\n");
11876 goto init_one_exit;
11878 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11880 if (!bp->doorbells) {
11881 dev_err(&bp->pdev->dev,
11882 "Cannot map doorbell space, aborting\n");
11884 goto init_one_exit;
11887 /* calc qm_cid_count */
11888 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11891 /* disable FCOE L2 queue for E1x */
11892 if (CHIP_IS_E1x(bp))
11893 bp->flags |= NO_FCOE_FLAG;
11898 /* Set bp->num_queues for MSI-X mode*/
11899 bnx2x_set_num_queues(bp);
11901 /* Configure interrupt mode: try to enable MSI-X/MSI if
11904 bnx2x_set_int_mode(bp);
11906 rc = register_netdev(dev);
11908 dev_err(&pdev->dev, "Cannot register net device\n");
11909 goto init_one_exit;
11913 if (!NO_FCOE(bp)) {
11914 /* Add storage MAC address */
11916 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11921 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11924 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11925 board_info[ent->driver_data].name,
11926 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11928 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11929 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11930 "5GHz (Gen2)" : "2.5GHz",
11931 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11937 iounmap(bp->regview);
11940 iounmap(bp->doorbells);
11944 if (atomic_read(&pdev->enable_cnt) == 1)
11945 pci_release_regions(pdev);
11947 pci_disable_device(pdev);
11948 pci_set_drvdata(pdev, NULL);
11953 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11955 struct net_device *dev = pci_get_drvdata(pdev);
11959 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11962 bp = netdev_priv(dev);
11965 /* Delete storage MAC address */
11966 if (!NO_FCOE(bp)) {
11968 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11974 /* Delete app tlvs from dcbnl */
11975 bnx2x_dcbnl_update_applist(bp, true);
11978 unregister_netdev(dev);
11980 /* Power on: we can't let PCI layer write to us while we are in D3 */
11981 bnx2x_set_power_state(bp, PCI_D0);
11983 /* Disable MSI/MSI-X */
11984 bnx2x_disable_msi(bp);
11987 bnx2x_set_power_state(bp, PCI_D3hot);
11989 /* Make sure RESET task is not scheduled before continuing */
11990 cancel_delayed_work_sync(&bp->sp_rtnl_task);
11993 iounmap(bp->regview);
11996 iounmap(bp->doorbells);
11998 bnx2x_release_firmware(bp);
12000 bnx2x_free_mem_bp(bp);
12004 if (atomic_read(&pdev->enable_cnt) == 1)
12005 pci_release_regions(pdev);
12007 pci_disable_device(pdev);
12008 pci_set_drvdata(pdev, NULL);
12011 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12015 bp->state = BNX2X_STATE_ERROR;
12017 bp->rx_mode = BNX2X_RX_MODE_NONE;
12020 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12023 bnx2x_tx_disable(bp);
12025 bnx2x_netif_stop(bp, 0);
12026 /* Delete all NAPI objects */
12027 bnx2x_del_all_napi(bp);
12029 del_timer_sync(&bp->timer);
12031 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12034 bnx2x_free_irq(bp);
12036 /* Free SKBs, SGEs, TPA pool and driver internals */
12037 bnx2x_free_skbs(bp);
12039 for_each_rx_queue(bp, i)
12040 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12042 bnx2x_free_mem(bp);
12044 bp->state = BNX2X_STATE_CLOSED;
12046 netif_carrier_off(bp->dev);
12051 static void bnx2x_eeh_recover(struct bnx2x *bp)
12055 mutex_init(&bp->port.phy_mutex);
12058 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12059 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12060 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12061 BNX2X_ERR("BAD MCP validity signature\n");
12065 * bnx2x_io_error_detected - called when PCI error is detected
12066 * @pdev: Pointer to PCI device
12067 * @state: The current pci connection state
12069 * This function is called after a PCI bus error affecting
12070 * this device has been detected.
12072 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12073 pci_channel_state_t state)
12075 struct net_device *dev = pci_get_drvdata(pdev);
12076 struct bnx2x *bp = netdev_priv(dev);
12080 netif_device_detach(dev);
12082 if (state == pci_channel_io_perm_failure) {
12084 return PCI_ERS_RESULT_DISCONNECT;
12087 if (netif_running(dev))
12088 bnx2x_eeh_nic_unload(bp);
12090 pci_disable_device(pdev);
12094 /* Request a slot reset */
12095 return PCI_ERS_RESULT_NEED_RESET;
12099 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12100 * @pdev: Pointer to PCI device
12102 * Restart the card from scratch, as if from a cold-boot.
12104 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12106 struct net_device *dev = pci_get_drvdata(pdev);
12107 struct bnx2x *bp = netdev_priv(dev);
12111 if (pci_enable_device(pdev)) {
12112 dev_err(&pdev->dev,
12113 "Cannot re-enable PCI device after reset\n");
12115 return PCI_ERS_RESULT_DISCONNECT;
12118 pci_set_master(pdev);
12119 pci_restore_state(pdev);
12121 if (netif_running(dev))
12122 bnx2x_set_power_state(bp, PCI_D0);
12126 return PCI_ERS_RESULT_RECOVERED;
12130 * bnx2x_io_resume - called when traffic can start flowing again
12131 * @pdev: Pointer to PCI device
12133 * This callback is called when the error recovery driver tells us that
12134 * its OK to resume normal operation.
12136 static void bnx2x_io_resume(struct pci_dev *pdev)
12138 struct net_device *dev = pci_get_drvdata(pdev);
12139 struct bnx2x *bp = netdev_priv(dev);
12141 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12142 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12148 bnx2x_eeh_recover(bp);
12150 if (netif_running(dev))
12151 bnx2x_nic_load(bp, LOAD_NORMAL);
12153 netif_device_attach(dev);
12158 static struct pci_error_handlers bnx2x_err_handler = {
12159 .error_detected = bnx2x_io_error_detected,
12160 .slot_reset = bnx2x_io_slot_reset,
12161 .resume = bnx2x_io_resume,
12164 static struct pci_driver bnx2x_pci_driver = {
12165 .name = DRV_MODULE_NAME,
12166 .id_table = bnx2x_pci_tbl,
12167 .probe = bnx2x_init_one,
12168 .remove = __devexit_p(bnx2x_remove_one),
12169 .suspend = bnx2x_suspend,
12170 .resume = bnx2x_resume,
12171 .err_handler = &bnx2x_err_handler,
12174 static int __init bnx2x_init(void)
12178 pr_info("%s", version);
12180 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12181 if (bnx2x_wq == NULL) {
12182 pr_err("Cannot create workqueue\n");
12186 ret = pci_register_driver(&bnx2x_pci_driver);
12188 pr_err("Cannot register driver\n");
12189 destroy_workqueue(bnx2x_wq);
12194 static void __exit bnx2x_cleanup(void)
12196 struct list_head *pos, *q;
12197 pci_unregister_driver(&bnx2x_pci_driver);
12199 destroy_workqueue(bnx2x_wq);
12201 /* Free globablly allocated resources */
12202 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12203 struct bnx2x_prev_path_list *tmp =
12204 list_entry(pos, struct bnx2x_prev_path_list, list);
12210 void bnx2x_notify_link_changed(struct bnx2x *bp)
12212 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12215 module_init(bnx2x_init);
12216 module_exit(bnx2x_cleanup);
12220 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12222 * @bp: driver handle
12223 * @set: set or clear the CAM entry
12225 * This function will wait until the ramdord completion returns.
12226 * Return 0 if success, -ENODEV if ramrod doesn't return.
12228 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12230 unsigned long ramrod_flags = 0;
12232 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12233 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12234 &bp->iscsi_l2_mac_obj, true,
12235 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12238 /* count denotes the number of new completions we have seen */
12239 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12241 struct eth_spe *spe;
12242 int cxt_index, cxt_offset;
12244 #ifdef BNX2X_STOP_ON_ERROR
12245 if (unlikely(bp->panic))
12249 spin_lock_bh(&bp->spq_lock);
12250 BUG_ON(bp->cnic_spq_pending < count);
12251 bp->cnic_spq_pending -= count;
12254 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12255 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12256 & SPE_HDR_CONN_TYPE) >>
12257 SPE_HDR_CONN_TYPE_SHIFT;
12258 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12259 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12261 /* Set validation for iSCSI L2 client before sending SETUP
12264 if (type == ETH_CONNECTION_TYPE) {
12265 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12266 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12268 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12269 (cxt_index * ILT_PAGE_CIDS);
12270 bnx2x_set_ctx_validation(bp,
12271 &bp->context[cxt_index].
12272 vcxt[cxt_offset].eth,
12273 BNX2X_ISCSI_ETH_CID(bp));
12278 * There may be not more than 8 L2, not more than 8 L5 SPEs
12279 * and in the air. We also check that number of outstanding
12280 * COMMON ramrods is not more than the EQ and SPQ can
12283 if (type == ETH_CONNECTION_TYPE) {
12284 if (!atomic_read(&bp->cq_spq_left))
12287 atomic_dec(&bp->cq_spq_left);
12288 } else if (type == NONE_CONNECTION_TYPE) {
12289 if (!atomic_read(&bp->eq_spq_left))
12292 atomic_dec(&bp->eq_spq_left);
12293 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12294 (type == FCOE_CONNECTION_TYPE)) {
12295 if (bp->cnic_spq_pending >=
12296 bp->cnic_eth_dev.max_kwqe_pending)
12299 bp->cnic_spq_pending++;
12301 BNX2X_ERR("Unknown SPE type: %d\n", type);
12306 spe = bnx2x_sp_get_next(bp);
12307 *spe = *bp->cnic_kwq_cons;
12309 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12310 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12312 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12313 bp->cnic_kwq_cons = bp->cnic_kwq;
12315 bp->cnic_kwq_cons++;
12317 bnx2x_sp_prod_update(bp);
12318 spin_unlock_bh(&bp->spq_lock);
12321 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12322 struct kwqe_16 *kwqes[], u32 count)
12324 struct bnx2x *bp = netdev_priv(dev);
12327 #ifdef BNX2X_STOP_ON_ERROR
12328 if (unlikely(bp->panic)) {
12329 BNX2X_ERR("Can't post to SP queue while panic\n");
12334 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12335 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12336 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12340 spin_lock_bh(&bp->spq_lock);
12342 for (i = 0; i < count; i++) {
12343 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12345 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12348 *bp->cnic_kwq_prod = *spe;
12350 bp->cnic_kwq_pending++;
12352 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12353 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12354 spe->data.update_data_addr.hi,
12355 spe->data.update_data_addr.lo,
12356 bp->cnic_kwq_pending);
12358 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12359 bp->cnic_kwq_prod = bp->cnic_kwq;
12361 bp->cnic_kwq_prod++;
12364 spin_unlock_bh(&bp->spq_lock);
12366 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12367 bnx2x_cnic_sp_post(bp, 0);
12372 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12374 struct cnic_ops *c_ops;
12377 mutex_lock(&bp->cnic_mutex);
12378 c_ops = rcu_dereference_protected(bp->cnic_ops,
12379 lockdep_is_held(&bp->cnic_mutex));
12381 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12382 mutex_unlock(&bp->cnic_mutex);
12387 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12389 struct cnic_ops *c_ops;
12393 c_ops = rcu_dereference(bp->cnic_ops);
12395 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12402 * for commands that have no data
12404 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12406 struct cnic_ctl_info ctl = {0};
12410 return bnx2x_cnic_ctl_send(bp, &ctl);
12413 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12415 struct cnic_ctl_info ctl = {0};
12417 /* first we tell CNIC and only then we count this as a completion */
12418 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12419 ctl.data.comp.cid = cid;
12420 ctl.data.comp.error = err;
12422 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12423 bnx2x_cnic_sp_post(bp, 0);
12427 /* Called with netif_addr_lock_bh() taken.
12428 * Sets an rx_mode config for an iSCSI ETH client.
12430 * Completion should be checked outside.
12432 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12434 unsigned long accept_flags = 0, ramrod_flags = 0;
12435 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12436 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12439 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12440 * because it's the only way for UIO Queue to accept
12441 * multicasts (in non-promiscuous mode only one Queue per
12442 * function will receive multicast packets (leading in our
12445 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12446 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12447 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12448 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12450 /* Clear STOP_PENDING bit if START is requested */
12451 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12453 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12455 /* Clear START_PENDING bit if STOP is requested */
12456 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12458 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12459 set_bit(sched_state, &bp->sp_state);
12461 __set_bit(RAMROD_RX, &ramrod_flags);
12462 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12468 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12470 struct bnx2x *bp = netdev_priv(dev);
12473 switch (ctl->cmd) {
12474 case DRV_CTL_CTXTBL_WR_CMD: {
12475 u32 index = ctl->data.io.offset;
12476 dma_addr_t addr = ctl->data.io.dma_addr;
12478 bnx2x_ilt_wr(bp, index, addr);
12482 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12483 int count = ctl->data.credit.credit_count;
12485 bnx2x_cnic_sp_post(bp, count);
12489 /* rtnl_lock is held. */
12490 case DRV_CTL_START_L2_CMD: {
12491 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12492 unsigned long sp_bits = 0;
12494 /* Configure the iSCSI classification object */
12495 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12496 cp->iscsi_l2_client_id,
12497 cp->iscsi_l2_cid, BP_FUNC(bp),
12498 bnx2x_sp(bp, mac_rdata),
12499 bnx2x_sp_mapping(bp, mac_rdata),
12500 BNX2X_FILTER_MAC_PENDING,
12501 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12504 /* Set iSCSI MAC address */
12505 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12512 /* Start accepting on iSCSI L2 ring */
12514 netif_addr_lock_bh(dev);
12515 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12516 netif_addr_unlock_bh(dev);
12518 /* bits to wait on */
12519 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12520 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12522 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12523 BNX2X_ERR("rx_mode completion timed out!\n");
12528 /* rtnl_lock is held. */
12529 case DRV_CTL_STOP_L2_CMD: {
12530 unsigned long sp_bits = 0;
12532 /* Stop accepting on iSCSI L2 ring */
12533 netif_addr_lock_bh(dev);
12534 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12535 netif_addr_unlock_bh(dev);
12537 /* bits to wait on */
12538 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12539 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12541 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12542 BNX2X_ERR("rx_mode completion timed out!\n");
12547 /* Unset iSCSI L2 MAC */
12548 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12549 BNX2X_ISCSI_ETH_MAC, true);
12552 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12553 int count = ctl->data.credit.credit_count;
12555 smp_mb__before_atomic_inc();
12556 atomic_add(count, &bp->cq_spq_left);
12557 smp_mb__after_atomic_inc();
12560 case DRV_CTL_ULP_REGISTER_CMD: {
12561 int ulp_type = ctl->data.register_data.ulp_type;
12563 if (CHIP_IS_E3(bp)) {
12564 int idx = BP_FW_MB_IDX(bp);
12565 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12566 int path = BP_PATH(bp);
12567 int port = BP_PORT(bp);
12569 u32 scratch_offset;
12572 /* first write capability to shmem2 */
12573 if (ulp_type == CNIC_ULP_ISCSI)
12574 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12575 else if (ulp_type == CNIC_ULP_FCOE)
12576 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12577 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12579 if ((ulp_type != CNIC_ULP_FCOE) ||
12580 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12581 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12584 /* if reached here - should write fcoe capabilities */
12585 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12586 if (!scratch_offset)
12588 scratch_offset += offsetof(struct glob_ncsi_oem_data,
12589 fcoe_features[path][port]);
12590 host_addr = (u32 *) &(ctl->data.register_data.
12592 for (i = 0; i < sizeof(struct fcoe_capabilities);
12594 REG_WR(bp, scratch_offset + i,
12595 *(host_addr + i/4));
12600 case DRV_CTL_ULP_UNREGISTER_CMD: {
12601 int ulp_type = ctl->data.ulp_type;
12603 if (CHIP_IS_E3(bp)) {
12604 int idx = BP_FW_MB_IDX(bp);
12607 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12608 if (ulp_type == CNIC_ULP_ISCSI)
12609 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12610 else if (ulp_type == CNIC_ULP_FCOE)
12611 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12612 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12618 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12625 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12627 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12629 if (bp->flags & USING_MSIX_FLAG) {
12630 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12631 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12632 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12634 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12635 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12637 if (!CHIP_IS_E1x(bp))
12638 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12640 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12642 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12643 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12644 cp->irq_arr[1].status_blk = bp->def_status_blk;
12645 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12646 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12651 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12653 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12656 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12657 bnx2x_cid_ilt_lines(bp);
12658 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12659 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12660 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12662 if (NO_ISCSI_OOO(bp))
12663 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12666 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12669 struct bnx2x *bp = netdev_priv(dev);
12670 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12673 BNX2X_ERR("NULL ops received\n");
12677 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12681 bp->cnic_kwq_cons = bp->cnic_kwq;
12682 bp->cnic_kwq_prod = bp->cnic_kwq;
12683 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12685 bp->cnic_spq_pending = 0;
12686 bp->cnic_kwq_pending = 0;
12688 bp->cnic_data = data;
12691 cp->drv_state |= CNIC_DRV_STATE_REGD;
12692 cp->iro_arr = bp->iro_arr;
12694 bnx2x_setup_cnic_irq_info(bp);
12696 rcu_assign_pointer(bp->cnic_ops, ops);
12701 static int bnx2x_unregister_cnic(struct net_device *dev)
12703 struct bnx2x *bp = netdev_priv(dev);
12704 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12706 mutex_lock(&bp->cnic_mutex);
12708 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12709 mutex_unlock(&bp->cnic_mutex);
12711 kfree(bp->cnic_kwq);
12712 bp->cnic_kwq = NULL;
12717 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12719 struct bnx2x *bp = netdev_priv(dev);
12720 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12722 /* If both iSCSI and FCoE are disabled - return NULL in
12723 * order to indicate CNIC that it should not try to work
12724 * with this device.
12726 if (NO_ISCSI(bp) && NO_FCOE(bp))
12729 cp->drv_owner = THIS_MODULE;
12730 cp->chip_id = CHIP_ID(bp);
12731 cp->pdev = bp->pdev;
12732 cp->io_base = bp->regview;
12733 cp->io_base2 = bp->doorbells;
12734 cp->max_kwqe_pending = 8;
12735 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12736 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12737 bnx2x_cid_ilt_lines(bp);
12738 cp->ctx_tbl_len = CNIC_ILT_LINES;
12739 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12740 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12741 cp->drv_ctl = bnx2x_drv_ctl;
12742 cp->drv_register_cnic = bnx2x_register_cnic;
12743 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12744 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12745 cp->iscsi_l2_client_id =
12746 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12747 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12749 if (NO_ISCSI_OOO(bp))
12750 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12753 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12756 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12759 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12761 cp->ctx_tbl_offset,
12766 EXPORT_SYMBOL(bnx2x_cnic_probe);
12768 #endif /* BCM_CNIC */