drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62
  63 #include "bnx2x.h"
  64 #include "bnx2x_init.h"
  65 #include "bnx2x_init_ops.h"
  66 #include "bnx2x_cmn.h"
  67 #include "bnx2x_vfpf.h"
  68 #include "bnx2x_dcb.h"
  69 #include "bnx2x_sp.h"
  70 #include <linux/firmware.h>
  71 #include "bnx2x_fw_file_hdr.h"
  72 /* FW files */
  73 #define FW_FILE_VERSION                                 \
  74         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  75         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  76         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  77         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  78 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  79 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  80 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  81
  82 /* Time in jiffies before concluding the transmitter is hung */
  83 #define TX_TIMEOUT              (5*HZ)
  84
  85 static char version[] =
  86         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  87         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  88
  89 MODULE_AUTHOR("Eliezer Tamir");
  90 MODULE_DESCRIPTION("QLogic "
  91                    "BCM57710/57711/57711E/"
  92                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  93                    "57840/57840_MF Driver");
  94 MODULE_LICENSE("GPL");
  95 MODULE_VERSION(DRV_MODULE_VERSION);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  99
 100 int bnx2x_num_queues;
 101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 102 MODULE_PARM_DESC(num_queues,
 103                  " Set number of queues (default is as a number of CPUs)");
 104
 105 static int disable_tpa;
 106 module_param(disable_tpa, int, S_IRUGO);
 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 108
 109 static int int_mode;
 110 module_param(int_mode, int, S_IRUGO);
 111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 112                                 "(1 INT#x; 2 MSI)");
 113
 114 static int dropless_fc;
 115 module_param(dropless_fc, int, S_IRUGO);
 116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 117
 118 static int mrrs = -1;
 119 module_param(mrrs, int, S_IRUGO);
 120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 121
 122 static int debug;
 123 module_param(debug, int, S_IRUGO);
 124 MODULE_PARM_DESC(debug, " Default debug msglevel");
 125
 126 static struct workqueue_struct *bnx2x_wq;
 127 struct workqueue_struct *bnx2x_iov_wq;
 128
 129 struct bnx2x_mac_vals {
 130         u32 xmac_addr;
 131         u32 xmac_val;
 132         u32 emac_addr;
 133         u32 emac_val;
 134         u32 umac_addr[2];
 135         u32 umac_val[2];
 136         u32 bmac_addr;
 137         u32 bmac_val[2];
 138 };
 139
 140 enum bnx2x_board_type {
 141         BCM57710 = 0,
 142         BCM57711,
 143         BCM57711E,
 144         BCM57712,
 145         BCM57712_MF,
 146         BCM57712_VF,
 147         BCM57800,
 148         BCM57800_MF,
 149         BCM57800_VF,
 150         BCM57810,
 151         BCM57810_MF,
 152         BCM57810_VF,
 153         BCM57840_4_10,
 154         BCM57840_2_20,
 155         BCM57840_MF,
 156         BCM57840_VF,
 157         BCM57811,
 158         BCM57811_MF,
 159         BCM57840_O,
 160         BCM57840_MFO,
 161         BCM57811_VF
 162 };
 163
 164 /* indexed by board_type, above */
 165 static struct {
 166         char *name;
 167 } board_info[] = {
 168         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 169         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 170         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 171         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 172         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 173         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 175         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 176         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 178         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 179         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 180         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 181         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 182         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 184         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 185         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 186         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 187         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 188         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 189 };
 190
 191 #ifndef PCI_DEVICE_ID_NX2_57710
 192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711
 195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57711E
 198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712
 201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800
 210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810
 219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57840_O
 225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811
 246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 250 #endif
 251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 253 #endif
 254
 255 static const struct pci_device_id bnx2x_pci_tbl[] = {
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286
 287 /* Forward declaration */
 288 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 289 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 290 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 291
 292 /****************************************************************************
 293 * General service functions
 294 ****************************************************************************/
 295
 296 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 297
 298 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 299                                        u32 addr, dma_addr_t mapping)
 300 {
 301         REG_WR(bp,  addr, U64_LO(mapping));
 302         REG_WR(bp,  addr + 4, U64_HI(mapping));
 303 }
 304
 305 static void storm_memset_spq_addr(struct bnx2x *bp,
 306                                   dma_addr_t mapping, u16 abs_fid)
 307 {
 308         u32 addr = XSEM_REG_FAST_MEMORY +
 309                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 310
 311         __storm_memset_dma_mapping(bp, addr, mapping);
 312 }
 313
 314 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 315                                   u16 pf_id)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325 }
 326
 327 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 328                                  u8 enable)
 329 {
 330         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338 }
 339
 340 static void storm_memset_eq_data(struct bnx2x *bp,
 341                                  struct event_ring_data *eq_data,
 342                                 u16 pfid)
 343 {
 344         size_t size = sizeof(struct event_ring_data);
 345
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 347
 348         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 349 }
 350
 351 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 352                                  u16 pfid)
 353 {
 354         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 355         REG_WR16(bp, addr, eq_prod);
 356 }
 357
 358 /* used only at init
 359  * locking is done by mcp
 360  */
 361 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 362 {
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 366                                PCICFG_VENDOR_ID_OFFSET);
 367 }
 368
 369 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 370 {
 371         u32 val;
 372
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 374         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 376                                PCICFG_VENDOR_ID_OFFSET);
 377
 378         return val;
 379 }
 380
 381 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 382 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 383 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 384 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 385 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 386
 387 static void bnx2x_dp_dmae(struct bnx2x *bp,
 388                           struct dmae_command *dmae, int msglvl)
 389 {
 390         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 391         int i;
 392
 393         switch (dmae->opcode & DMAE_COMMAND_DST) {
 394         case DMAE_CMD_DST_PCI:
 395                 if (src_type == DMAE_CMD_SRC_PCI)
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 400                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 else
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_lo >> 2,
 408                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 break;
 412         case DMAE_CMD_DST_GRC:
 413                 if (src_type == DMAE_CMD_SRC_PCI)
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 416                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 418                            dmae->len, dmae->dst_addr_lo >> 2,
 419                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 420                            dmae->comp_val);
 421                 else
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src [%08x], len [%d*4], dst [%08x]\n"
 424                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_lo >> 2,
 426                            dmae->len, dmae->dst_addr_lo >> 2,
 427                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 428                            dmae->comp_val);
 429                 break;
 430         default:
 431                 if (src_type == DMAE_CMD_SRC_PCI)
 432                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 433                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 434                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 435                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 436                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 437                            dmae->comp_val);
 438                 else
 439                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 440                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 441                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 442                            dmae->opcode, dmae->src_addr_lo >> 2,
 443                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 444                            dmae->comp_val);
 445                 break;
 446         }
 447
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 449                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 450                    i, *(((u32 *)dmae) + i));
 451 }
 452
 453 /* copy command into DMAE command memory and set DMAE command go */
 454 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 455 {
 456         u32 cmd_offset;
 457         int i;
 458
 459         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 460         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 461                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 462         }
 463         REG_WR(bp, dmae_reg_go_c[idx], 1);
 464 }
 465
 466 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 467 {
 468         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 469                            DMAE_CMD_C_ENABLE);
 470 }
 471
 472 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 473 {
 474         return opcode & ~DMAE_CMD_SRC_RESET;
 475 }
 476
 477 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 478                              bool with_comp, u8 comp_type)
 479 {
 480         u32 opcode = 0;
 481
 482         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 483                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 484
 485         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 486
 487         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 488         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 489                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 490         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 491
 492 #ifdef __BIG_ENDIAN
 493         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 494 #else
 495         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 496 #endif
 497         if (with_comp)
 498                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 499         return opcode;
 500 }
 501
 502 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 503                                       struct dmae_command *dmae,
 504                                       u8 src_type, u8 dst_type)
 505 {
 506         memset(dmae, 0, sizeof(struct dmae_command));
 507
 508         /* set the opcode */
 509         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 510                                          true, DMAE_COMP_PCI);
 511
 512         /* fill in the completion parameters */
 513         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 515         dmae->comp_val = DMAE_COMP_VAL;
 516 }
 517
 518 /* issue a dmae command over the init-channel and wait for completion */
 519 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 520                                u32 *comp)
 521 {
 522         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 523         int rc = 0;
 524
 525         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 526
 527         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 528          * as long as this code is called both from syscall context and
 529          * from ndo_set_rx_mode() flow that may be called from BH.
 530          */
 531
 532         spin_lock_bh(&bp->dmae_lock);
 533
 534         /* reset completion */
 535         *comp = 0;
 536
 537         /* post the command on the channel used for initializations */
 538         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 539
 540         /* wait for completion */
 541         udelay(5);
 542         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 543
 544                 if (!cnt ||
 545                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 546                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 547                         BNX2X_ERR("DMAE timeout!\n");
 548                         rc = DMAE_TIMEOUT;
 549                         goto unlock;
 550                 }
 551                 cnt--;
 552                 udelay(50);
 553         }
 554         if (*comp & DMAE_PCI_ERR_FLAG) {
 555                 BNX2X_ERR("DMAE PCI error!\n");
 556                 rc = DMAE_PCI_ERROR;
 557         }
 558
 559 unlock:
 560
 561         spin_unlock_bh(&bp->dmae_lock);
 562
 563         return rc;
 564 }
 565
 566 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 567                       u32 len32)
 568 {
 569         int rc;
 570         struct dmae_command dmae;
 571
 572         if (!bp->dmae_ready) {
 573                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 574
 575                 if (CHIP_IS_E1(bp))
 576                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 577                 else
 578                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 579                 return;
 580         }
 581
 582         /* set opcode and fixed command fields */
 583         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 584
 585         /* fill in addresses and len */
 586         dmae.src_addr_lo = U64_LO(dma_addr);
 587         dmae.src_addr_hi = U64_HI(dma_addr);
 588         dmae.dst_addr_lo = dst_addr >> 2;
 589         dmae.dst_addr_hi = 0;
 590         dmae.len = len32;
 591
 592         /* issue the command and wait for completion */
 593         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 594         if (rc) {
 595                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 596 #ifdef BNX2X_STOP_ON_ERROR
 597                 bnx2x_panic();
 598 #endif
 599         }
 600 }
 601
 602 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 603 {
 604         int rc;
 605         struct dmae_command dmae;
 606
 607         if (!bp->dmae_ready) {
 608                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 609                 int i;
 610
 611                 if (CHIP_IS_E1(bp))
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 614                 else
 615                         for (i = 0; i < len32; i++)
 616                                 data[i] = REG_RD(bp, src_addr + i*4);
 617
 618                 return;
 619         }
 620
 621         /* set opcode and fixed command fields */
 622         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 623
 624         /* fill in addresses and len */
 625         dmae.src_addr_lo = src_addr >> 2;
 626         dmae.src_addr_hi = 0;
 627         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 629         dmae.len = len32;
 630
 631         /* issue the command and wait for completion */
 632         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 633         if (rc) {
 634                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 635 #ifdef BNX2X_STOP_ON_ERROR
 636                 bnx2x_panic();
 637 #endif
 638         }
 639 }
 640
 641 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 642                                       u32 addr, u32 len)
 643 {
 644         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 645         int offset = 0;
 646
 647         while (len > dmae_wr_max) {
 648                 bnx2x_write_dmae(bp, phys_addr + offset,
 649                                  addr + offset, dmae_wr_max);
 650                 offset += dmae_wr_max * 4;
 651                 len -= dmae_wr_max;
 652         }
 653
 654         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 655 }
 656
 657 enum storms {
 658            XSTORM,
 659            TSTORM,
 660            CSTORM,
 661            USTORM,
 662            MAX_STORMS
 663 };
 664
 665 #define STORMS_NUM 4
 666 #define REGS_IN_ENTRY 4
 667
 668 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 669                                               enum storms storm,
 670                                               int entry)
 671 {
 672         switch (storm) {
 673         case XSTORM:
 674                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 675         case TSTORM:
 676                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 677         case CSTORM:
 678                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 679         case USTORM:
 680                 return USTORM_ASSERT_LIST_OFFSET(entry);
 681         case MAX_STORMS:
 682         default:
 683                 BNX2X_ERR("unknown storm\n");
 684         }
 685         return -EINVAL;
 686 }
 687
 688 static int bnx2x_mc_assert(struct bnx2x *bp)
 689 {
 690         char last_idx;
 691         int i, j, rc = 0;
 692         enum storms storm;
 693         u32 regs[REGS_IN_ENTRY];
 694         u32 bar_storm_intmem[STORMS_NUM] = {
 695                 BAR_XSTRORM_INTMEM,
 696                 BAR_TSTRORM_INTMEM,
 697                 BAR_CSTRORM_INTMEM,
 698                 BAR_USTRORM_INTMEM
 699         };
 700         u32 storm_assert_list_index[STORMS_NUM] = {
 701                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 USTORM_ASSERT_LIST_INDEX_OFFSET
 705         };
 706         char *storms_string[STORMS_NUM] = {
 707                 "XSTORM",
 708                 "TSTORM",
 709                 "CSTORM",
 710                 "USTORM"
 711         };
 712
 713         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 714                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 715                                    storm_assert_list_index[storm]);
 716                 if (last_idx)
 717                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 718                                   storms_string[storm], last_idx);
 719
 720                 /* print the asserts */
 721                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 722                         /* read a single assert entry */
 723                         for (j = 0; j < REGS_IN_ENTRY; j++)
 724                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 725                                           bnx2x_get_assert_list_entry(bp,
 726                                                                       storm,
 727                                                                       i) +
 728                                           sizeof(u32) * j);
 729
 730                         /* log entry if it contains a valid assert */
 731                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 732                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 733                                           storms_string[storm], i, regs[3],
 734                                           regs[2], regs[1], regs[0]);
 735                                 rc++;
 736                         } else {
 737                                 break;
 738                         }
 739                 }
 740         }
 741
 742         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 743                   CHIP_IS_E1(bp) ? "everest1" :
 744                   CHIP_IS_E1H(bp) ? "everest1h" :
 745                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 746                   BCM_5710_FW_MAJOR_VERSION,
 747                   BCM_5710_FW_MINOR_VERSION,
 748                   BCM_5710_FW_REVISION_VERSION);
 749
 750         return rc;
 751 }
 752
 753 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 754 #define SCRATCH_BUFFER_SIZE(bp) \
 755         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 756
 757 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 758 {
 759         u32 addr, val;
 760         u32 mark, offset;
 761         __be32 data[9];
 762         int word;
 763         u32 trace_shmem_base;
 764         if (BP_NOMCP(bp)) {
 765                 BNX2X_ERR("NO MCP - can not dump\n");
 766                 return;
 767         }
 768         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 769                 (bp->common.bc_ver & 0xff0000) >> 16,
 770                 (bp->common.bc_ver & 0xff00) >> 8,
 771                 (bp->common.bc_ver & 0xff));
 772
 773         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 774         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 775                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 776
 777         if (BP_PATH(bp) == 0)
 778                 trace_shmem_base = bp->common.shmem_base;
 779         else
 780                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 781
 782         /* sanity */
 783         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 784             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 785                                 SCRATCH_BUFFER_SIZE(bp)) {
 786                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 787                           trace_shmem_base);
 788                 return;
 789         }
 790
 791         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 792
 793         /* validate TRCB signature */
 794         mark = REG_RD(bp, addr);
 795         if (mark != MFW_TRACE_SIGNATURE) {
 796                 BNX2X_ERR("Trace buffer signature is missing.");
 797                 return ;
 798         }
 799
 800         /* read cyclic buffer pointer */
 801         addr += 4;
 802         mark = REG_RD(bp, addr);
 803         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 804         if (mark >= trace_shmem_base || mark < addr + 4) {
 805                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 806                 return;
 807         }
 808         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 809
 810         printk("%s", lvl);
 811
 812         /* dump buffer after the mark */
 813         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 814                 for (word = 0; word < 8; word++)
 815                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 816                 data[8] = 0x0;
 817                 pr_cont("%s", (char *)data);
 818         }
 819
 820         /* dump buffer before the mark */
 821         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 822                 for (word = 0; word < 8; word++)
 823                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 824                 data[8] = 0x0;
 825                 pr_cont("%s", (char *)data);
 826         }
 827         printk("%s" "end of fw dump\n", lvl);
 828 }
 829
 830 static void bnx2x_fw_dump(struct bnx2x *bp)
 831 {
 832         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 833 }
 834
 835 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 836 {
 837         int port = BP_PORT(bp);
 838         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 839         u32 val = REG_RD(bp, addr);
 840
 841         /* in E1 we must use only PCI configuration space to disable
 842          * MSI/MSIX capability
 843          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 844          */
 845         if (CHIP_IS_E1(bp)) {
 846                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 847                  * Use mask register to prevent from HC sending interrupts
 848                  * after we exit the function
 849                  */
 850                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 851
 852                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 853                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 854                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 855         } else
 856                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 857                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 858                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 859                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 860
 861         DP(NETIF_MSG_IFDOWN,
 862            "write %x to HC %d (addr 0x%x)\n",
 863            val, port, addr);
 864
 865         /* flush all outstanding writes */
 866         mmiowb();
 867
 868         REG_WR(bp, addr, val);
 869         if (REG_RD(bp, addr) != val)
 870                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 871 }
 872
 873 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 874 {
 875         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 876
 877         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 878                  IGU_PF_CONF_INT_LINE_EN |
 879                  IGU_PF_CONF_ATTN_BIT_EN);
 880
 881         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 882
 883         /* flush all outstanding writes */
 884         mmiowb();
 885
 886         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 887         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 888                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 889 }
 890
 891 static void bnx2x_int_disable(struct bnx2x *bp)
 892 {
 893         if (bp->common.int_block == INT_BLOCK_HC)
 894                 bnx2x_hc_int_disable(bp);
 895         else
 896                 bnx2x_igu_int_disable(bp);
 897 }
 898
 899 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 900 {
 901         int i;
 902         u16 j;
 903         struct hc_sp_status_block_data sp_sb_data;
 904         int func = BP_FUNC(bp);
 905 #ifdef BNX2X_STOP_ON_ERROR
 906         u16 start = 0, end = 0;
 907         u8 cos;
 908 #endif
 909         if (IS_PF(bp) && disable_int)
 910                 bnx2x_int_disable(bp);
 911
 912         bp->stats_state = STATS_STATE_DISABLED;
 913         bp->eth_stats.unrecoverable_error++;
 914         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 915
 916         BNX2X_ERR("begin crash dump -----------------\n");
 917
 918         /* Indices */
 919         /* Common */
 920         if (IS_PF(bp)) {
 921                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 922                 int data_size, cstorm_offset;
 923
 924                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 925                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 926                           bp->spq_prod_idx, bp->stats_counter);
 927                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 928                           def_sb->atten_status_block.attn_bits,
 929                           def_sb->atten_status_block.attn_bits_ack,
 930                           def_sb->atten_status_block.status_block_id,
 931                           def_sb->atten_status_block.attn_bits_index);
 932                 BNX2X_ERR("     def (");
 933                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 934                         pr_cont("0x%x%s",
 935                                 def_sb->sp_sb.index_values[i],
 936                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 937
 938                 data_size = sizeof(struct hc_sp_status_block_data) /
 939                             sizeof(u32);
 940                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 941                 for (i = 0; i < data_size; i++)
 942                         *((u32 *)&sp_sb_data + i) =
 943                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 944                                            i * sizeof(u32));
 945
 946                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 947                         sp_sb_data.igu_sb_id,
 948                         sp_sb_data.igu_seg_id,
 949                         sp_sb_data.p_func.pf_id,
 950                         sp_sb_data.p_func.vnic_id,
 951                         sp_sb_data.p_func.vf_id,
 952                         sp_sb_data.p_func.vf_valid,
 953                         sp_sb_data.state);
 954         }
 955
 956         for_each_eth_queue(bp, i) {
 957                 struct bnx2x_fastpath *fp = &bp->fp[i];
 958                 int loop;
 959                 struct hc_status_block_data_e2 sb_data_e2;
 960                 struct hc_status_block_data_e1x sb_data_e1x;
 961                 struct hc_status_block_sm  *hc_sm_p =
 962                         CHIP_IS_E1x(bp) ?
 963                         sb_data_e1x.common.state_machine :
 964                         sb_data_e2.common.state_machine;
 965                 struct hc_index_data *hc_index_p =
 966                         CHIP_IS_E1x(bp) ?
 967                         sb_data_e1x.index_data :
 968                         sb_data_e2.index_data;
 969                 u8 data_size, cos;
 970                 u32 *sb_data_p;
 971                 struct bnx2x_fp_txdata txdata;
 972
 973                 if (!bp->fp)
 974                         break;
 975
 976                 if (!fp->rx_cons_sb)
 977                         continue;
 978
 979                 /* Rx */
 980                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 981                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 982                           fp->rx_comp_prod,
 983                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 984                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 985                           fp->rx_sge_prod, fp->last_max_sge,
 986                           le16_to_cpu(fp->fp_hc_idx));
 987
 988                 /* Tx */
 989                 for_each_cos_in_tx_queue(fp, cos)
 990                 {
 991                         if (!fp->txdata_ptr[cos])
 992                                 break;
 993
 994                         txdata = *fp->txdata_ptr[cos];
 995
 996                         if (!txdata.tx_cons_sb)
 997                                 continue;
 998
 999                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1000                                   i, txdata.tx_pkt_prod,
1001                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1002                                   txdata.tx_bd_cons,
1003                                   le16_to_cpu(*txdata.tx_cons_sb));
1004                 }
1005
1006                 loop = CHIP_IS_E1x(bp) ?
1007                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1008
1009                 /* host sb data */
1010
1011                 if (IS_FCOE_FP(fp))
1012                         continue;
1013
1014                 BNX2X_ERR("     run indexes (");
1015                 for (j = 0; j < HC_SB_MAX_SM; j++)
1016                         pr_cont("0x%x%s",
1017                                fp->sb_running_index[j],
1018                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1019
1020                 BNX2X_ERR("     indexes (");
1021                 for (j = 0; j < loop; j++)
1022                         pr_cont("0x%x%s",
1023                                fp->sb_index_values[j],
1024                                (j == loop - 1) ? ")" : " ");
1025
1026                 /* VF cannot access FW refelection for status block */
1027                 if (IS_VF(bp))
1028                         continue;
1029
1030                 /* fw sb data */
1031                 data_size = CHIP_IS_E1x(bp) ?
1032                         sizeof(struct hc_status_block_data_e1x) :
1033                         sizeof(struct hc_status_block_data_e2);
1034                 data_size /= sizeof(u32);
1035                 sb_data_p = CHIP_IS_E1x(bp) ?
1036                         (u32 *)&sb_data_e1x :
1037                         (u32 *)&sb_data_e2;
1038                 /* copy sb data in here */
1039                 for (j = 0; j < data_size; j++)
1040                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042                                 j * sizeof(u32));
1043
1044                 if (!CHIP_IS_E1x(bp)) {
1045                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1046                                 sb_data_e2.common.p_func.pf_id,
1047                                 sb_data_e2.common.p_func.vf_id,
1048                                 sb_data_e2.common.p_func.vf_valid,
1049                                 sb_data_e2.common.p_func.vnic_id,
1050                                 sb_data_e2.common.same_igu_sb_1b,
1051                                 sb_data_e2.common.state);
1052                 } else {
1053                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1054                                 sb_data_e1x.common.p_func.pf_id,
1055                                 sb_data_e1x.common.p_func.vf_id,
1056                                 sb_data_e1x.common.p_func.vf_valid,
1057                                 sb_data_e1x.common.p_func.vnic_id,
1058                                 sb_data_e1x.common.same_igu_sb_1b,
1059                                 sb_data_e1x.common.state);
1060                 }
1061
1062                 /* SB_SMs data */
1063                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1064                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065                                 j, hc_sm_p[j].__flags,
1066                                 hc_sm_p[j].igu_sb_id,
1067                                 hc_sm_p[j].igu_seg_id,
1068                                 hc_sm_p[j].time_to_expire,
1069                                 hc_sm_p[j].timer_value);
1070                 }
1071
1072                 /* Indices data */
1073                 for (j = 0; j < loop; j++) {
1074                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1075                                hc_index_p[j].flags,
1076                                hc_index_p[j].timeout);
1077                 }
1078         }
1079
1080 #ifdef BNX2X_STOP_ON_ERROR
1081         if (IS_PF(bp)) {
1082                 /* event queue */
1083                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084                 for (i = 0; i < NUM_EQ_DESC; i++) {
1085                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1086
1087                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088                                   i, bp->eq_ring[i].message.opcode,
1089                                   bp->eq_ring[i].message.error);
1090                         BNX2X_ERR("data: %x %x %x\n",
1091                                   data[0], data[1], data[2]);
1092                 }
1093         }
1094
1095         /* Rings */
1096         /* Rx */
1097         for_each_valid_rx_queue(bp, i) {
1098                 struct bnx2x_fastpath *fp = &bp->fp[i];
1099
1100                 if (!bp->fp)
1101                         break;
1102
1103                 if (!fp->rx_cons_sb)
1104                         continue;
1105
1106                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1107                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1108                 for (j = start; j != end; j = RX_BD(j + 1)) {
1109                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1110                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1111
1112                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1113                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1114                 }
1115
1116                 start = RX_SGE(fp->rx_sge_prod);
1117                 end = RX_SGE(fp->last_max_sge);
1118                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1119                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1120                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1121
1122                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1123                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1124                 }
1125
1126                 start = RCQ_BD(fp->rx_comp_cons - 10);
1127                 end = RCQ_BD(fp->rx_comp_cons + 503);
1128                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1129                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1130
1131                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1132                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1133                 }
1134         }
1135
1136         /* Tx */
1137         for_each_valid_tx_queue(bp, i) {
1138                 struct bnx2x_fastpath *fp = &bp->fp[i];
1139
1140                 if (!bp->fp)
1141                         break;
1142
1143                 for_each_cos_in_tx_queue(fp, cos) {
1144                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1145
1146                         if (!fp->txdata_ptr[cos])
1147                                 break;
1148
1149                         if (!txdata->tx_cons_sb)
1150                                 continue;
1151
1152                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1153                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1154                         for (j = start; j != end; j = TX_BD(j + 1)) {
1155                                 struct sw_tx_bd *sw_bd =
1156                                         &txdata->tx_buf_ring[j];
1157
1158                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1159                                           i, cos, j, sw_bd->skb,
1160                                           sw_bd->first_bd);
1161                         }
1162
1163                         start = TX_BD(txdata->tx_bd_cons - 10);
1164                         end = TX_BD(txdata->tx_bd_cons + 254);
1165                         for (j = start; j != end; j = TX_BD(j + 1)) {
1166                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1167
1168                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1169                                           i, cos, j, tx_bd[0], tx_bd[1],
1170                                           tx_bd[2], tx_bd[3]);
1171                         }
1172                 }
1173         }
1174 #endif
1175         if (IS_PF(bp)) {
1176                 bnx2x_fw_dump(bp);
1177                 bnx2x_mc_assert(bp);
1178         }
1179         BNX2X_ERR("end crash dump -----------------\n");
1180 }
1181
1182 /*
1183  * FLR Support for E2
1184  *
1185  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1186  * initialization.
1187  */
1188 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1189 #define FLR_WAIT_INTERVAL       50      /* usec */
1190 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1191
1192 struct pbf_pN_buf_regs {
1193         int pN;
1194         u32 init_crd;
1195         u32 crd;
1196         u32 crd_freed;
1197 };
1198
1199 struct pbf_pN_cmd_regs {
1200         int pN;
1201         u32 lines_occup;
1202         u32 lines_freed;
1203 };
1204
1205 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1206                                      struct pbf_pN_buf_regs *regs,
1207                                      u32 poll_count)
1208 {
1209         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1210         u32 cur_cnt = poll_count;
1211
1212         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1213         crd = crd_start = REG_RD(bp, regs->crd);
1214         init_crd = REG_RD(bp, regs->init_crd);
1215
1216         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1217         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1218         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1219
1220         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1221                (init_crd - crd_start))) {
1222                 if (cur_cnt--) {
1223                         udelay(FLR_WAIT_INTERVAL);
1224                         crd = REG_RD(bp, regs->crd);
1225                         crd_freed = REG_RD(bp, regs->crd_freed);
1226                 } else {
1227                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1228                            regs->pN);
1229                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1230                            regs->pN, crd);
1231                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1232                            regs->pN, crd_freed);
1233                         break;
1234                 }
1235         }
1236         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1237            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1238 }
1239
1240 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1241                                      struct pbf_pN_cmd_regs *regs,
1242                                      u32 poll_count)
1243 {
1244         u32 occup, to_free, freed, freed_start;
1245         u32 cur_cnt = poll_count;
1246
1247         occup = to_free = REG_RD(bp, regs->lines_occup);
1248         freed = freed_start = REG_RD(bp, regs->lines_freed);
1249
1250         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1251         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1252
1253         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1254                 if (cur_cnt--) {
1255                         udelay(FLR_WAIT_INTERVAL);
1256                         occup = REG_RD(bp, regs->lines_occup);
1257                         freed = REG_RD(bp, regs->lines_freed);
1258                 } else {
1259                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1260                            regs->pN);
1261                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1262                            regs->pN, occup);
1263                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1264                            regs->pN, freed);
1265                         break;
1266                 }
1267         }
1268         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1269            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1270 }
1271
1272 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1273                                     u32 expected, u32 poll_count)
1274 {
1275         u32 cur_cnt = poll_count;
1276         u32 val;
1277
1278         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1279                 udelay(FLR_WAIT_INTERVAL);
1280
1281         return val;
1282 }
1283
1284 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1285                                     char *msg, u32 poll_cnt)
1286 {
1287         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1288         if (val != 0) {
1289                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1290                 return 1;
1291         }
1292         return 0;
1293 }
1294
1295 /* Common routines with VF FLR cleanup */
1296 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1297 {
1298         /* adjust polling timeout */
1299         if (CHIP_REV_IS_EMUL(bp))
1300                 return FLR_POLL_CNT * 2000;
1301
1302         if (CHIP_REV_IS_FPGA(bp))
1303                 return FLR_POLL_CNT * 120;
1304
1305         return FLR_POLL_CNT;
1306 }
1307
1308 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1309 {
1310         struct pbf_pN_cmd_regs cmd_regs[] = {
1311                 {0, (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_OCCUPANCY_Q0 :
1313                         PBF_REG_P0_TQ_OCCUPANCY,
1314                     (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1316                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1317                 {1, (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_OCCUPANCY_Q1 :
1319                         PBF_REG_P1_TQ_OCCUPANCY,
1320                     (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1322                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1323                 {4, (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1325                         PBF_REG_P4_TQ_OCCUPANCY,
1326                     (CHIP_IS_E3B0(bp)) ?
1327                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1328                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1329         };
1330
1331         struct pbf_pN_buf_regs buf_regs[] = {
1332                 {0, (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_INIT_CRD_Q0 :
1334                         PBF_REG_P0_INIT_CRD ,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_CREDIT_Q0 :
1337                         PBF_REG_P0_CREDIT,
1338                     (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1340                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1341                 {1, (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_INIT_CRD_Q1 :
1343                         PBF_REG_P1_INIT_CRD,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_CREDIT_Q1 :
1346                         PBF_REG_P1_CREDIT,
1347                     (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1349                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1350                 {4, (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_INIT_CRD_LB_Q :
1352                         PBF_REG_P4_INIT_CRD,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_CREDIT_LB_Q :
1355                         PBF_REG_P4_CREDIT,
1356                     (CHIP_IS_E3B0(bp)) ?
1357                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1358                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1359         };
1360
1361         int i;
1362
1363         /* Verify the command queues are flushed P0, P1, P4 */
1364         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1365                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1366
1367         /* Verify the transmission buffers are flushed P0, P1, P4 */
1368         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1369                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1370 }
1371
1372 #define OP_GEN_PARAM(param) \
1373         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1374
1375 #define OP_GEN_TYPE(type) \
1376         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1377
1378 #define OP_GEN_AGG_VECT(index) \
1379         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1380
1381 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1382 {
1383         u32 op_gen_command = 0;
1384         u32 comp_addr = BAR_CSTRORM_INTMEM +
1385                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1386         int ret = 0;
1387
1388         if (REG_RD(bp, comp_addr)) {
1389                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1390                 return 1;
1391         }
1392
1393         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1394         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1395         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1396         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1397
1398         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1399         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1400
1401         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1402                 BNX2X_ERR("FW final cleanup did not succeed\n");
1403                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1404                    (REG_RD(bp, comp_addr)));
1405                 bnx2x_panic();
1406                 return 1;
1407         }
1408         /* Zero completion for next FLR */
1409         REG_WR(bp, comp_addr, 0);
1410
1411         return ret;
1412 }
1413
1414 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1415 {
1416         u16 status;
1417
1418         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1419         return status & PCI_EXP_DEVSTA_TRPND;
1420 }
1421
1422 /* PF FLR specific routines
1423 */
1424 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1425 {
1426         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1427         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1428                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1429                         "CFC PF usage counter timed out",
1430                         poll_cnt))
1431                 return 1;
1432
1433         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1434         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435                         DORQ_REG_PF_USAGE_CNT,
1436                         "DQ PF usage counter timed out",
1437                         poll_cnt))
1438                 return 1;
1439
1440         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1441         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1443                         "QM PF usage counter timed out",
1444                         poll_cnt))
1445                 return 1;
1446
1447         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1448         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1450                         "Timers VNIC usage counter timed out",
1451                         poll_cnt))
1452                 return 1;
1453         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1454                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1455                         "Timers NUM_SCANS usage counter timed out",
1456                         poll_cnt))
1457                 return 1;
1458
1459         /* Wait DMAE PF usage counter to zero */
1460         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1462                         "DMAE command register timed out",
1463                         poll_cnt))
1464                 return 1;
1465
1466         return 0;
1467 }
1468
1469 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1470 {
1471         u32 val;
1472
1473         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1474         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1477         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1484
1485         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1486         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1493
1494         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1495         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1496            val);
1497 }
1498
1499 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1500 {
1501         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1502
1503         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1504
1505         /* Re-enable PF target read access */
1506         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1507
1508         /* Poll HW usage counters */
1509         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1510         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1511                 return -EBUSY;
1512
1513         /* Zero the igu 'trailing edge' and 'leading edge' */
1514
1515         /* Send the FW cleanup command */
1516         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1517                 return -EBUSY;
1518
1519         /* ATC cleanup */
1520
1521         /* Verify TX hw is flushed */
1522         bnx2x_tx_hw_flushed(bp, poll_cnt);
1523
1524         /* Wait 100ms (not adjusted according to platform) */
1525         msleep(100);
1526
1527         /* Verify no pending pci transactions */
1528         if (bnx2x_is_pcie_pending(bp->pdev))
1529                 BNX2X_ERR("PCIE Transactions still pending\n");
1530
1531         /* Debug */
1532         bnx2x_hw_enable_status(bp);
1533
1534         /*
1535          * Master enable - Due to WB DMAE writes performed before this
1536          * register is re-initialized as part of the regular function init
1537          */
1538         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1539
1540         return 0;
1541 }
1542
1543 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1544 {
1545         int port = BP_PORT(bp);
1546         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1547         u32 val = REG_RD(bp, addr);
1548         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1549         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1550         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1551
1552         if (msix) {
1553                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1554                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1555                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1556                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1557                 if (single_msix)
1558                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1559         } else if (msi) {
1560                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1561                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1562                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1564         } else {
1565                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1566                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1567                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1568                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1569
1570                 if (!CHIP_IS_E1(bp)) {
1571                         DP(NETIF_MSG_IFUP,
1572                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1573
1574                         REG_WR(bp, addr, val);
1575
1576                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1577                 }
1578         }
1579
1580         if (CHIP_IS_E1(bp))
1581                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1582
1583         DP(NETIF_MSG_IFUP,
1584            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1585            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1586
1587         REG_WR(bp, addr, val);
1588         /*
1589          * Ensure that HC_CONFIG is written before leading/trailing edge config
1590          */
1591         mmiowb();
1592         barrier();
1593
1594         if (!CHIP_IS_E1(bp)) {
1595                 /* init leading/trailing edge */
1596                 if (IS_MF(bp)) {
1597                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1598                         if (bp->port.pmf)
1599                                 /* enable nig and gpio3 attention */
1600                                 val |= 0x1100;
1601                 } else
1602                         val = 0xffff;
1603
1604                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1605                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1606         }
1607
1608         /* Make sure that interrupts are indeed enabled from here on */
1609         mmiowb();
1610 }
1611
1612 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1613 {
1614         u32 val;
1615         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1616         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1617         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1618
1619         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1620
1621         if (msix) {
1622                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1623                          IGU_PF_CONF_SINGLE_ISR_EN);
1624                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1625                         IGU_PF_CONF_ATTN_BIT_EN);
1626
1627                 if (single_msix)
1628                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1629         } else if (msi) {
1630                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1631                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1632                         IGU_PF_CONF_ATTN_BIT_EN |
1633                         IGU_PF_CONF_SINGLE_ISR_EN);
1634         } else {
1635                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1636                 val |= (IGU_PF_CONF_INT_LINE_EN |
1637                         IGU_PF_CONF_ATTN_BIT_EN |
1638                         IGU_PF_CONF_SINGLE_ISR_EN);
1639         }
1640
1641         /* Clean previous status - need to configure igu prior to ack*/
1642         if ((!msix) || single_msix) {
1643                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1644                 bnx2x_ack_int(bp);
1645         }
1646
1647         val |= IGU_PF_CONF_FUNC_EN;
1648
1649         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1650            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1651
1652         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1653
1654         if (val & IGU_PF_CONF_INT_LINE_EN)
1655                 pci_intx(bp->pdev, true);
1656
1657         barrier();
1658
1659         /* init leading/trailing edge */
1660         if (IS_MF(bp)) {
1661                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1662                 if (bp->port.pmf)
1663                         /* enable nig and gpio3 attention */
1664                         val |= 0x1100;
1665         } else
1666                 val = 0xffff;
1667
1668         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1669         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1670
1671         /* Make sure that interrupts are indeed enabled from here on */
1672         mmiowb();
1673 }
1674
1675 void bnx2x_int_enable(struct bnx2x *bp)
1676 {
1677         if (bp->common.int_block == INT_BLOCK_HC)
1678                 bnx2x_hc_int_enable(bp);
1679         else
1680                 bnx2x_igu_int_enable(bp);
1681 }
1682
1683 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1684 {
1685         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1686         int i, offset;
1687
1688         if (disable_hw)
1689                 /* prevent the HW from sending interrupts */
1690                 bnx2x_int_disable(bp);
1691
1692         /* make sure all ISRs are done */
1693         if (msix) {
1694                 synchronize_irq(bp->msix_table[0].vector);
1695                 offset = 1;
1696                 if (CNIC_SUPPORT(bp))
1697                         offset++;
1698                 for_each_eth_queue(bp, i)
1699                         synchronize_irq(bp->msix_table[offset++].vector);
1700         } else
1701                 synchronize_irq(bp->pdev->irq);
1702
1703         /* make sure sp_task is not running */
1704         cancel_delayed_work(&bp->sp_task);
1705         cancel_delayed_work(&bp->period_task);
1706         flush_workqueue(bnx2x_wq);
1707 }
1708
1709 /* fast path */
1710
1711 /*
1712  * General service functions
1713  */
1714
1715 /* Return true if succeeded to acquire the lock */
1716 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1717 {
1718         u32 lock_status;
1719         u32 resource_bit = (1 << resource);
1720         int func = BP_FUNC(bp);
1721         u32 hw_lock_control_reg;
1722
1723         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1724            "Trying to take a lock on resource %d\n", resource);
1725
1726         /* Validating that the resource is within range */
1727         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1728                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1729                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1730                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1731                 return false;
1732         }
1733
1734         if (func <= 5)
1735                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1736         else
1737                 hw_lock_control_reg =
1738                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1739
1740         /* Try to acquire the lock */
1741         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1742         lock_status = REG_RD(bp, hw_lock_control_reg);
1743         if (lock_status & resource_bit)
1744                 return true;
1745
1746         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1747            "Failed to get a lock on resource %d\n", resource);
1748         return false;
1749 }
1750
1751 /**
1752  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1753  *
1754  * @bp: driver handle
1755  *
1756  * Returns the recovery leader resource id according to the engine this function
1757  * belongs to. Currently only only 2 engines is supported.
1758  */
1759 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1760 {
1761         if (BP_PATH(bp))
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1763         else
1764                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1765 }
1766
1767 /**
1768  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1769  *
1770  * @bp: driver handle
1771  *
1772  * Tries to acquire a leader lock for current engine.
1773  */
1774 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1775 {
1776         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1777 }
1778
1779 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1780
1781 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1782 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1783 {
1784         /* Set the interrupt occurred bit for the sp-task to recognize it
1785          * must ack the interrupt and transition according to the IGU
1786          * state machine.
1787          */
1788         atomic_set(&bp->interrupt_occurred, 1);
1789
1790         /* The sp_task must execute only after this bit
1791          * is set, otherwise we will get out of sync and miss all
1792          * further interrupts. Hence, the barrier.
1793          */
1794         smp_wmb();
1795
1796         /* schedule sp_task to workqueue */
1797         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1798 }
1799
1800 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1801 {
1802         struct bnx2x *bp = fp->bp;
1803         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1804         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1806         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1807
1808         DP(BNX2X_MSG_SP,
1809            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1810            fp->index, cid, command, bp->state,
1811            rr_cqe->ramrod_cqe.ramrod_type);
1812
1813         /* If cid is within VF range, replace the slowpath object with the
1814          * one corresponding to this VF
1815          */
1816         if (cid >= BNX2X_FIRST_VF_CID  &&
1817             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1818                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1819
1820         switch (command) {
1821         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1822                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1823                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1824                 break;
1825
1826         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1827                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1828                 drv_cmd = BNX2X_Q_CMD_SETUP;
1829                 break;
1830
1831         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1832                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1833                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1834                 break;
1835
1836         case (RAMROD_CMD_ID_ETH_HALT):
1837                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1838                 drv_cmd = BNX2X_Q_CMD_HALT;
1839                 break;
1840
1841         case (RAMROD_CMD_ID_ETH_TERMINATE):
1842                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1843                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1844                 break;
1845
1846         case (RAMROD_CMD_ID_ETH_EMPTY):
1847                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1848                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1849                 break;
1850
1851         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1852                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1853                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1854                 break;
1855
1856         default:
1857                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1858                           command, fp->index);
1859                 return;
1860         }
1861
1862         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1863             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1864                 /* q_obj->complete_cmd() failure means that this was
1865                  * an unexpected completion.
1866                  *
1867                  * In this case we don't want to increase the bp->spq_left
1868                  * because apparently we haven't sent this command the first
1869                  * place.
1870                  */
1871 #ifdef BNX2X_STOP_ON_ERROR
1872                 bnx2x_panic();
1873 #else
1874                 return;
1875 #endif
1876
1877         smp_mb__before_atomic();
1878         atomic_inc(&bp->cq_spq_left);
1879         /* push the change in bp->spq_left and towards the memory */
1880         smp_mb__after_atomic();
1881
1882         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1883
1884         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1885             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1886                 /* if Q update ramrod is completed for last Q in AFEX vif set
1887                  * flow, then ACK MCP at the end
1888                  *
1889                  * mark pending ACK to MCP bit.
1890                  * prevent case that both bits are cleared.
1891                  * At the end of load/unload driver checks that
1892                  * sp_state is cleared, and this order prevents
1893                  * races
1894                  */
1895                 smp_mb__before_atomic();
1896                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1897                 wmb();
1898                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1899                 smp_mb__after_atomic();
1900
1901                 /* schedule the sp task as mcp ack is required */
1902                 bnx2x_schedule_sp_task(bp);
1903         }
1904
1905         return;
1906 }
1907
1908 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1909 {
1910         struct bnx2x *bp = netdev_priv(dev_instance);
1911         u16 status = bnx2x_ack_int(bp);
1912         u16 mask;
1913         int i;
1914         u8 cos;
1915
1916         /* Return here if interrupt is shared and it's not for us */
1917         if (unlikely(status == 0)) {
1918                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1919                 return IRQ_NONE;
1920         }
1921         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1922
1923 #ifdef BNX2X_STOP_ON_ERROR
1924         if (unlikely(bp->panic))
1925                 return IRQ_HANDLED;
1926 #endif
1927
1928         for_each_eth_queue(bp, i) {
1929                 struct bnx2x_fastpath *fp = &bp->fp[i];
1930
1931                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1932                 if (status & mask) {
1933                         /* Handle Rx or Tx according to SB id */
1934                         for_each_cos_in_tx_queue(fp, cos)
1935                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1936                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1937                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1938                         status &= ~mask;
1939                 }
1940         }
1941
1942         if (CNIC_SUPPORT(bp)) {
1943                 mask = 0x2;
1944                 if (status & (mask | 0x1)) {
1945                         struct cnic_ops *c_ops = NULL;
1946
1947                         rcu_read_lock();
1948                         c_ops = rcu_dereference(bp->cnic_ops);
1949                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1950                                       CNIC_DRV_STATE_HANDLES_IRQ))
1951                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1952                         rcu_read_unlock();
1953
1954                         status &= ~mask;
1955                 }
1956         }
1957
1958         if (unlikely(status & 0x1)) {
1959
1960                 /* schedule sp task to perform default status block work, ack
1961                  * attentions and enable interrupts.
1962                  */
1963                 bnx2x_schedule_sp_task(bp);
1964
1965                 status &= ~0x1;
1966                 if (!status)
1967                         return IRQ_HANDLED;
1968         }
1969
1970         if (unlikely(status))
1971                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1972                    status);
1973
1974         return IRQ_HANDLED;
1975 }
1976
1977 /* Link */
1978
1979 /*
1980  * General service functions
1981  */
1982
1983 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1984 {
1985         u32 lock_status;
1986         u32 resource_bit = (1 << resource);
1987         int func = BP_FUNC(bp);
1988         u32 hw_lock_control_reg;
1989         int cnt;
1990
1991         /* Validating that the resource is within range */
1992         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1993                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1994                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1995                 return -EINVAL;
1996         }
1997
1998         if (func <= 5) {
1999                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2000         } else {
2001                 hw_lock_control_reg =
2002                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2003         }
2004
2005         /* Validating that the resource is not already taken */
2006         lock_status = REG_RD(bp, hw_lock_control_reg);
2007         if (lock_status & resource_bit) {
2008                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2009                    lock_status, resource_bit);
2010                 return -EEXIST;
2011         }
2012
2013         /* Try for 5 second every 5ms */
2014         for (cnt = 0; cnt < 1000; cnt++) {
2015                 /* Try to acquire the lock */
2016                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2017                 lock_status = REG_RD(bp, hw_lock_control_reg);
2018                 if (lock_status & resource_bit)
2019                         return 0;
2020
2021                 usleep_range(5000, 10000);
2022         }
2023         BNX2X_ERR("Timeout\n");
2024         return -EAGAIN;
2025 }
2026
2027 int bnx2x_release_leader_lock(struct bnx2x *bp)
2028 {
2029         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2030 }
2031
2032 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2033 {
2034         u32 lock_status;
2035         u32 resource_bit = (1 << resource);
2036         int func = BP_FUNC(bp);
2037         u32 hw_lock_control_reg;
2038
2039         /* Validating that the resource is within range */
2040         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2041                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2042                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2043                 return -EINVAL;
2044         }
2045
2046         if (func <= 5) {
2047                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2048         } else {
2049                 hw_lock_control_reg =
2050                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2051         }
2052
2053         /* Validating that the resource is currently taken */
2054         lock_status = REG_RD(bp, hw_lock_control_reg);
2055         if (!(lock_status & resource_bit)) {
2056                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2057                           lock_status, resource_bit);
2058                 return -EFAULT;
2059         }
2060
2061         REG_WR(bp, hw_lock_control_reg, resource_bit);
2062         return 0;
2063 }
2064
2065 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2066 {
2067         /* The GPIO should be swapped if swap register is set and active */
2068         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2069                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2070         int gpio_shift = gpio_num +
2071                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2072         u32 gpio_mask = (1 << gpio_shift);
2073         u32 gpio_reg;
2074         int value;
2075
2076         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2077                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2078                 return -EINVAL;
2079         }
2080
2081         /* read GPIO value */
2082         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2083
2084         /* get the requested pin value */
2085         if ((gpio_reg & gpio_mask) == gpio_mask)
2086                 value = 1;
2087         else
2088                 value = 0;
2089
2090         return value;
2091 }
2092
2093 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2094 {
2095         /* The GPIO should be swapped if swap register is set and active */
2096         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2097                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2098         int gpio_shift = gpio_num +
2099                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2100         u32 gpio_mask = (1 << gpio_shift);
2101         u32 gpio_reg;
2102
2103         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2104                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2105                 return -EINVAL;
2106         }
2107
2108         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2109         /* read GPIO and mask except the float bits */
2110         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2111
2112         switch (mode) {
2113         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2114                 DP(NETIF_MSG_LINK,
2115                    "Set GPIO %d (shift %d) -> output low\n",
2116                    gpio_num, gpio_shift);
2117                 /* clear FLOAT and set CLR */
2118                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2119                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2120                 break;
2121
2122         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2123                 DP(NETIF_MSG_LINK,
2124                    "Set GPIO %d (shift %d) -> output high\n",
2125                    gpio_num, gpio_shift);
2126                 /* clear FLOAT and set SET */
2127                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2128                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2129                 break;
2130
2131         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2132                 DP(NETIF_MSG_LINK,
2133                    "Set GPIO %d (shift %d) -> input\n",
2134                    gpio_num, gpio_shift);
2135                 /* set FLOAT */
2136                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2137                 break;
2138
2139         default:
2140                 break;
2141         }
2142
2143         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2144         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2145
2146         return 0;
2147 }
2148
2149 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2150 {
2151         u32 gpio_reg = 0;
2152         int rc = 0;
2153
2154         /* Any port swapping should be handled by caller. */
2155
2156         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2157         /* read GPIO and mask except the float bits */
2158         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2160         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2161         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2162
2163         switch (mode) {
2164         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2165                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2166                 /* set CLR */
2167                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2168                 break;
2169
2170         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2171                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2172                 /* set SET */
2173                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2174                 break;
2175
2176         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2177                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2178                 /* set FLOAT */
2179                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2180                 break;
2181
2182         default:
2183                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2184                 rc = -EINVAL;
2185                 break;
2186         }
2187
2188         if (rc == 0)
2189                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2190
2191         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2192
2193         return rc;
2194 }
2195
2196 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2197 {
2198         /* The GPIO should be swapped if swap register is set and active */
2199         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2200                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2201         int gpio_shift = gpio_num +
2202                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2203         u32 gpio_mask = (1 << gpio_shift);
2204         u32 gpio_reg;
2205
2206         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2207                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2208                 return -EINVAL;
2209         }
2210
2211         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2212         /* read GPIO int */
2213         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2214
2215         switch (mode) {
2216         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2217                 DP(NETIF_MSG_LINK,
2218                    "Clear GPIO INT %d (shift %d) -> output low\n",
2219                    gpio_num, gpio_shift);
2220                 /* clear SET and set CLR */
2221                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2222                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2223                 break;
2224
2225         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2226                 DP(NETIF_MSG_LINK,
2227                    "Set GPIO INT %d (shift %d) -> output high\n",
2228                    gpio_num, gpio_shift);
2229                 /* clear CLR and set SET */
2230                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2231                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2232                 break;
2233
2234         default:
2235                 break;
2236         }
2237
2238         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2239         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2240
2241         return 0;
2242 }
2243
2244 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2245 {
2246         u32 spio_reg;
2247
2248         /* Only 2 SPIOs are configurable */
2249         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2250                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2251                 return -EINVAL;
2252         }
2253
2254         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2255         /* read SPIO and mask except the float bits */
2256         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2257
2258         switch (mode) {
2259         case MISC_SPIO_OUTPUT_LOW:
2260                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2261                 /* clear FLOAT and set CLR */
2262                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2263                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2264                 break;
2265
2266         case MISC_SPIO_OUTPUT_HIGH:
2267                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2268                 /* clear FLOAT and set SET */
2269                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2271                 break;
2272
2273         case MISC_SPIO_INPUT_HI_Z:
2274                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2275                 /* set FLOAT */
2276                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2277                 break;
2278
2279         default:
2280                 break;
2281         }
2282
2283         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2284         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2285
2286         return 0;
2287 }
2288
2289 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2290 {
2291         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2292
2293         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2294                                            ADVERTISED_Pause);
2295         switch (bp->link_vars.ieee_fc &
2296                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2297         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2299                                                   ADVERTISED_Pause);
2300                 break;
2301
2302         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2304                 break;
2305
2306         default:
2307                 break;
2308         }
2309 }
2310
2311 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2312 {
2313         /* Initialize link parameters structure variables
2314          * It is recommended to turn off RX FC for jumbo frames
2315          *  for better performance
2316          */
2317         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2318                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2319         else
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2321 }
2322
2323 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2324 {
2325         u32 pause_enabled = 0;
2326
2327         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2328                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2329                         pause_enabled = 1;
2330
2331                 REG_WR(bp, BAR_USTRORM_INTMEM +
2332                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2333                        pause_enabled);
2334         }
2335
2336         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2337            pause_enabled ? "enabled" : "disabled");
2338 }
2339
2340 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2341 {
2342         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2343         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2344
2345         if (!BP_NOMCP(bp)) {
2346                 bnx2x_set_requested_fc(bp);
2347                 bnx2x_acquire_phy_lock(bp);
2348
2349                 if (load_mode == LOAD_DIAG) {
2350                         struct link_params *lp = &bp->link_params;
2351                         lp->loopback_mode = LOOPBACK_XGXS;
2352                         /* Prefer doing PHY loopback at highest speed */
2353                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2354                                 if (lp->speed_cap_mask[cfx_idx] &
2355                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2356                                         lp->req_line_speed[cfx_idx] =
2357                                         SPEED_20000;
2358                                 else if (lp->speed_cap_mask[cfx_idx] &
2359                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2360                                                 lp->req_line_speed[cfx_idx] =
2361                                                 SPEED_10000;
2362                                 else
2363                                         lp->req_line_speed[cfx_idx] =
2364                                         SPEED_1000;
2365                         }
2366                 }
2367
2368                 if (load_mode == LOAD_LOOPBACK_EXT) {
2369                         struct link_params *lp = &bp->link_params;
2370                         lp->loopback_mode = LOOPBACK_EXT;
2371                 }
2372
2373                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2374
2375                 bnx2x_release_phy_lock(bp);
2376
2377                 bnx2x_init_dropless_fc(bp);
2378
2379                 bnx2x_calc_fc_adv(bp);
2380
2381                 if (bp->link_vars.link_up) {
2382                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2383                         bnx2x_link_report(bp);
2384                 }
2385                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2386                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2387                 return rc;
2388         }
2389         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2390         return -EINVAL;
2391 }
2392
2393 void bnx2x_link_set(struct bnx2x *bp)
2394 {
2395         if (!BP_NOMCP(bp)) {
2396                 bnx2x_acquire_phy_lock(bp);
2397                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2398                 bnx2x_release_phy_lock(bp);
2399
2400                 bnx2x_init_dropless_fc(bp);
2401
2402                 bnx2x_calc_fc_adv(bp);
2403         } else
2404                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2405 }
2406
2407 static void bnx2x__link_reset(struct bnx2x *bp)
2408 {
2409         if (!BP_NOMCP(bp)) {
2410                 bnx2x_acquire_phy_lock(bp);
2411                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2412                 bnx2x_release_phy_lock(bp);
2413         } else
2414                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2415 }
2416
2417 void bnx2x_force_link_reset(struct bnx2x *bp)
2418 {
2419         bnx2x_acquire_phy_lock(bp);
2420         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2421         bnx2x_release_phy_lock(bp);
2422 }
2423
2424 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2425 {
2426         u8 rc = 0;
2427
2428         if (!BP_NOMCP(bp)) {
2429                 bnx2x_acquire_phy_lock(bp);
2430                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2431                                      is_serdes);
2432                 bnx2x_release_phy_lock(bp);
2433         } else
2434                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2435
2436         return rc;
2437 }
2438
2439 /* Calculates the sum of vn_min_rates.
2440    It's needed for further normalizing of the min_rates.
2441    Returns:
2442      sum of vn_min_rates.
2443        or
2444      0 - if all the min_rates are 0.
2445      In the later case fairness algorithm should be deactivated.
2446      If not all min_rates are zero then those that are zeroes will be set to 1.
2447  */
2448 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2449                                       struct cmng_init_input *input)
2450 {
2451         int all_zero = 1;
2452         int vn;
2453
2454         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455                 u32 vn_cfg = bp->mf_config[vn];
2456                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2457                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2458
2459                 /* Skip hidden vns */
2460                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2461                         vn_min_rate = 0;
2462                 /* If min rate is zero - set it to 1 */
2463                 else if (!vn_min_rate)
2464                         vn_min_rate = DEF_MIN_RATE;
2465                 else
2466                         all_zero = 0;
2467
2468                 input->vnic_min_rate[vn] = vn_min_rate;
2469         }
2470
2471         /* if ETS or all min rates are zeros - disable fairness */
2472         if (BNX2X_IS_ETS_ENABLED(bp)) {
2473                 input->flags.cmng_enables &=
2474                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2475                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2476         } else if (all_zero) {
2477                 input->flags.cmng_enables &=
2478                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2479                 DP(NETIF_MSG_IFUP,
2480                    "All MIN values are zeroes fairness will be disabled\n");
2481         } else
2482                 input->flags.cmng_enables |=
2483                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2484 }
2485
2486 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2487                                     struct cmng_init_input *input)
2488 {
2489         u16 vn_max_rate;
2490         u32 vn_cfg = bp->mf_config[vn];
2491
2492         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2493                 vn_max_rate = 0;
2494         else {
2495                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2496
2497                 if (IS_MF_PERCENT_BW(bp)) {
2498                         /* maxCfg in percents of linkspeed */
2499                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2500                 } else /* SD modes */
2501                         /* maxCfg is absolute in 100Mb units */
2502                         vn_max_rate = maxCfg * 100;
2503         }
2504
2505         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2506
2507         input->vnic_max_rate[vn] = vn_max_rate;
2508 }
2509
2510 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2511 {
2512         if (CHIP_REV_IS_SLOW(bp))
2513                 return CMNG_FNS_NONE;
2514         if (IS_MF(bp))
2515                 return CMNG_FNS_MINMAX;
2516
2517         return CMNG_FNS_NONE;
2518 }
2519
2520 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2521 {
2522         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2523
2524         if (BP_NOMCP(bp))
2525                 return; /* what should be the default value in this case */
2526
2527         /* For 2 port configuration the absolute function number formula
2528          * is:
2529          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2530          *
2531          *      and there are 4 functions per port
2532          *
2533          * For 4 port configuration it is
2534          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2535          *
2536          *      and there are 2 functions per port
2537          */
2538         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2539                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2540
2541                 if (func >= E1H_FUNC_MAX)
2542                         break;
2543
2544                 bp->mf_config[vn] =
2545                         MF_CFG_RD(bp, func_mf_config[func].config);
2546         }
2547         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2549                 bp->flags |= MF_FUNC_DIS;
2550         } else {
2551                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2552                 bp->flags &= ~MF_FUNC_DIS;
2553         }
2554 }
2555
2556 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2557 {
2558         struct cmng_init_input input;
2559         memset(&input, 0, sizeof(struct cmng_init_input));
2560
2561         input.port_rate = bp->link_vars.line_speed;
2562
2563         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2564                 int vn;
2565
2566                 /* read mf conf from shmem */
2567                 if (read_cfg)
2568                         bnx2x_read_mf_cfg(bp);
2569
2570                 /* vn_weight_sum and enable fairness if not 0 */
2571                 bnx2x_calc_vn_min(bp, &input);
2572
2573                 /* calculate and set min-max rate for each vn */
2574                 if (bp->port.pmf)
2575                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2576                                 bnx2x_calc_vn_max(bp, vn, &input);
2577
2578                 /* always enable rate shaping and fairness */
2579                 input.flags.cmng_enables |=
2580                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2581
2582                 bnx2x_init_cmng(&input, &bp->cmng);
2583                 return;
2584         }
2585
2586         /* rate shaping and fairness are disabled */
2587         DP(NETIF_MSG_IFUP,
2588            "rate shaping and fairness are disabled\n");
2589 }
2590
2591 static void storm_memset_cmng(struct bnx2x *bp,
2592                               struct cmng_init *cmng,
2593                               u8 port)
2594 {
2595         int vn;
2596         size_t size = sizeof(struct cmng_struct_per_port);
2597
2598         u32 addr = BAR_XSTRORM_INTMEM +
2599                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2600
2601         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2602
2603         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2604                 int func = func_by_vn(bp, vn);
2605
2606                 addr = BAR_XSTRORM_INTMEM +
2607                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2608                 size = sizeof(struct rate_shaping_vars_per_vn);
2609                 __storm_memset_struct(bp, addr, size,
2610                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2611
2612                 addr = BAR_XSTRORM_INTMEM +
2613                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2614                 size = sizeof(struct fairness_vars_per_vn);
2615                 __storm_memset_struct(bp, addr, size,
2616                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2617         }
2618 }
2619
2620 /* init cmng mode in HW according to local configuration */
2621 void bnx2x_set_local_cmng(struct bnx2x *bp)
2622 {
2623         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2624
2625         if (cmng_fns != CMNG_FNS_NONE) {
2626                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2627                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2628         } else {
2629                 /* rate shaping and fairness are disabled */
2630                 DP(NETIF_MSG_IFUP,
2631                    "single function mode without fairness\n");
2632         }
2633 }
2634
2635 /* This function is called upon link interrupt */
2636 static void bnx2x_link_attn(struct bnx2x *bp)
2637 {
2638         /* Make sure that we are synced with the current statistics */
2639         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2640
2641         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2642
2643         bnx2x_init_dropless_fc(bp);
2644
2645         if (bp->link_vars.link_up) {
2646
2647                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2648                         struct host_port_stats *pstats;
2649
2650                         pstats = bnx2x_sp(bp, port_stats);
2651                         /* reset old mac stats */
2652                         memset(&(pstats->mac_stx[0]), 0,
2653                                sizeof(struct mac_stx));
2654                 }
2655                 if (bp->state == BNX2X_STATE_OPEN)
2656                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2657         }
2658
2659         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2660                 bnx2x_set_local_cmng(bp);
2661
2662         __bnx2x_link_report(bp);
2663
2664         if (IS_MF(bp))
2665                 bnx2x_link_sync_notify(bp);
2666 }
2667
2668 void bnx2x__link_status_update(struct bnx2x *bp)
2669 {
2670         if (bp->state != BNX2X_STATE_OPEN)
2671                 return;
2672
2673         /* read updated dcb configuration */
2674         if (IS_PF(bp)) {
2675                 bnx2x_dcbx_pmf_update(bp);
2676                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2677                 if (bp->link_vars.link_up)
2678                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2679                 else
2680                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2681                         /* indicate link status */
2682                 bnx2x_link_report(bp);
2683
2684         } else { /* VF */
2685                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2686                                           SUPPORTED_10baseT_Full |
2687                                           SUPPORTED_100baseT_Half |
2688                                           SUPPORTED_100baseT_Full |
2689                                           SUPPORTED_1000baseT_Full |
2690                                           SUPPORTED_2500baseX_Full |
2691                                           SUPPORTED_10000baseT_Full |
2692                                           SUPPORTED_TP |
2693                                           SUPPORTED_FIBRE |
2694                                           SUPPORTED_Autoneg |
2695                                           SUPPORTED_Pause |
2696                                           SUPPORTED_Asym_Pause);
2697                 bp->port.advertising[0] = bp->port.supported[0];
2698
2699                 bp->link_params.bp = bp;
2700                 bp->link_params.port = BP_PORT(bp);
2701                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2702                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2703                 bp->link_params.req_line_speed[0] = SPEED_10000;
2704                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2705                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2706                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2707                 bp->link_vars.line_speed = SPEED_10000;
2708                 bp->link_vars.link_status =
2709                         (LINK_STATUS_LINK_UP |
2710                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2711                 bp->link_vars.link_up = 1;
2712                 bp->link_vars.duplex = DUPLEX_FULL;
2713                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2714                 __bnx2x_link_report(bp);
2715
2716                 bnx2x_sample_bulletin(bp);
2717
2718                 /* if bulletin board did not have an update for link status
2719                  * __bnx2x_link_report will report current status
2720                  * but it will NOT duplicate report in case of already reported
2721                  * during sampling bulletin board.
2722                  */
2723                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2724         }
2725 }
2726
2727 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2728                                   u16 vlan_val, u8 allowed_prio)
2729 {
2730         struct bnx2x_func_state_params func_params = {NULL};
2731         struct bnx2x_func_afex_update_params *f_update_params =
2732                 &func_params.params.afex_update;
2733
2734         func_params.f_obj = &bp->func_obj;
2735         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2736
2737         /* no need to wait for RAMROD completion, so don't
2738          * set RAMROD_COMP_WAIT flag
2739          */
2740
2741         f_update_params->vif_id = vifid;
2742         f_update_params->afex_default_vlan = vlan_val;
2743         f_update_params->allowed_priorities = allowed_prio;
2744
2745         /* if ramrod can not be sent, response to MCP immediately */
2746         if (bnx2x_func_state_change(bp, &func_params) < 0)
2747                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2748
2749         return 0;
2750 }
2751
2752 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2753                                           u16 vif_index, u8 func_bit_map)
2754 {
2755         struct bnx2x_func_state_params func_params = {NULL};
2756         struct bnx2x_func_afex_viflists_params *update_params =
2757                 &func_params.params.afex_viflists;
2758         int rc;
2759         u32 drv_msg_code;
2760
2761         /* validate only LIST_SET and LIST_GET are received from switch */
2762         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2763                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2764                           cmd_type);
2765
2766         func_params.f_obj = &bp->func_obj;
2767         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2768
2769         /* set parameters according to cmd_type */
2770         update_params->afex_vif_list_command = cmd_type;
2771         update_params->vif_list_index = vif_index;
2772         update_params->func_bit_map =
2773                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2774         update_params->func_to_clear = 0;
2775         drv_msg_code =
2776                 (cmd_type == VIF_LIST_RULE_GET) ?
2777                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2778                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2779
2780         /* if ramrod can not be sent, respond to MCP immediately for
2781          * SET and GET requests (other are not triggered from MCP)
2782          */
2783         rc = bnx2x_func_state_change(bp, &func_params);
2784         if (rc < 0)
2785                 bnx2x_fw_command(bp, drv_msg_code, 0);
2786
2787         return 0;
2788 }
2789
2790 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2791 {
2792         struct afex_stats afex_stats;
2793         u32 func = BP_ABS_FUNC(bp);
2794         u32 mf_config;
2795         u16 vlan_val;
2796         u32 vlan_prio;
2797         u16 vif_id;
2798         u8 allowed_prio;
2799         u8 vlan_mode;
2800         u32 addr_to_write, vifid, addrs, stats_type, i;
2801
2802         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2803                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2804                 DP(BNX2X_MSG_MCP,
2805                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2806                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2807         }
2808
2809         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2810                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2812                 DP(BNX2X_MSG_MCP,
2813                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2814                    vifid, addrs);
2815                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2816                                                addrs);
2817         }
2818
2819         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2820                 addr_to_write = SHMEM2_RD(bp,
2821                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2822                 stats_type = SHMEM2_RD(bp,
2823                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2824
2825                 DP(BNX2X_MSG_MCP,
2826                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2827                    addr_to_write);
2828
2829                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2830
2831                 /* write response to scratchpad, for MCP */
2832                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2833                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2834                                *(((u32 *)(&afex_stats))+i));
2835
2836                 /* send ack message to MCP */
2837                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2838         }
2839
2840         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2841                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2842                 bp->mf_config[BP_VN(bp)] = mf_config;
2843                 DP(BNX2X_MSG_MCP,
2844                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2845                    mf_config);
2846
2847                 /* if VIF_SET is "enabled" */
2848                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2849                         /* set rate limit directly to internal RAM */
2850                         struct cmng_init_input cmng_input;
2851                         struct rate_shaping_vars_per_vn m_rs_vn;
2852                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2853                         u32 addr = BAR_XSTRORM_INTMEM +
2854                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2855
2856                         bp->mf_config[BP_VN(bp)] = mf_config;
2857
2858                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2859                         m_rs_vn.vn_counter.rate =
2860                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2861                         m_rs_vn.vn_counter.quota =
2862                                 (m_rs_vn.vn_counter.rate *
2863                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2864
2865                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2866
2867                         /* read relevant values from mf_cfg struct in shmem */
2868                         vif_id =
2869                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2870                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2871                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2872                         vlan_val =
2873                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2874                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2875                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2876                         vlan_prio = (mf_config &
2877                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2878                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2879                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2880                         vlan_mode =
2881                                 (MF_CFG_RD(bp,
2882                                            func_mf_config[func].afex_config) &
2883                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2884                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2885                         allowed_prio =
2886                                 (MF_CFG_RD(bp,
2887                                            func_mf_config[func].afex_config) &
2888                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2889                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2890
2891                         /* send ramrod to FW, return in case of failure */
2892                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2893                                                    allowed_prio))
2894                                 return;
2895
2896                         bp->afex_def_vlan_tag = vlan_val;
2897                         bp->afex_vlan_mode = vlan_mode;
2898                 } else {
2899                         /* notify link down because BP->flags is disabled */
2900                         bnx2x_link_report(bp);
2901
2902                         /* send INVALID VIF ramrod to FW */
2903                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2904
2905                         /* Reset the default afex VLAN */
2906                         bp->afex_def_vlan_tag = -1;
2907                 }
2908         }
2909 }
2910
2911 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2912 {
2913         struct bnx2x_func_switch_update_params *switch_update_params;
2914         struct bnx2x_func_state_params func_params;
2915
2916         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2917         switch_update_params = &func_params.params.switch_update;
2918         func_params.f_obj = &bp->func_obj;
2919         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2920
2921         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2922                 int func = BP_ABS_FUNC(bp);
2923                 u32 val;
2924
2925                 /* Re-learn the S-tag from shmem */
2926                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2927                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2928                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2929                         bp->mf_ov = val;
2930                 } else {
2931                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2932                         goto fail;
2933                 }
2934
2935                 /* Configure new S-tag in LLH */
2936                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2937                        bp->mf_ov);
2938
2939                 /* Send Ramrod to update FW of change */
2940                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2941                           &switch_update_params->changes);
2942                 switch_update_params->vlan = bp->mf_ov;
2943
2944                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2945                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2946                                   bp->mf_ov);
2947                         goto fail;
2948                 } else {
2949                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2950                            bp->mf_ov);
2951                 }
2952         } else {
2953                 goto fail;
2954         }
2955
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2957         return;
2958 fail:
2959         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2960 }
2961
2962 static void bnx2x_pmf_update(struct bnx2x *bp)
2963 {
2964         int port = BP_PORT(bp);
2965         u32 val;
2966
2967         bp->port.pmf = 1;
2968         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2969
2970         /*
2971          * We need the mb() to ensure the ordering between the writing to
2972          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2973          */
2974         smp_mb();
2975
2976         /* queue a periodic task */
2977         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2978
2979         bnx2x_dcbx_pmf_update(bp);
2980
2981         /* enable nig attention */
2982         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2983         if (bp->common.int_block == INT_BLOCK_HC) {
2984                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2985                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2986         } else if (!CHIP_IS_E1x(bp)) {
2987                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2988                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2989         }
2990
2991         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2992 }
2993
2994 /* end of Link */
2995
2996 /* slow path */
2997
2998 /*
2999  * General service functions
3000  */
3001
3002 /* send the MCP a request, block until there is a reply */
3003 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3004 {
3005         int mb_idx = BP_FW_MB_IDX(bp);
3006         u32 seq;
3007         u32 rc = 0;
3008         u32 cnt = 1;
3009         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3010
3011         mutex_lock(&bp->fw_mb_mutex);
3012         seq = ++bp->fw_seq;
3013         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3014         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3015
3016         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3017                         (command | seq), param);
3018
3019         do {
3020                 /* let the FW do it's magic ... */
3021                 msleep(delay);
3022
3023                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3024
3025                 /* Give the FW up to 5 second (500*10ms) */
3026         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3027
3028         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3029            cnt*delay, rc, seq);
3030
3031         /* is this a reply to our command? */
3032         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3033                 rc &= FW_MSG_CODE_MASK;
3034         else {
3035                 /* FW BUG! */
3036                 BNX2X_ERR("FW failed to respond!\n");
3037                 bnx2x_fw_dump(bp);
3038                 rc = 0;
3039         }
3040         mutex_unlock(&bp->fw_mb_mutex);
3041
3042         return rc;
3043 }
3044
3045 static void storm_memset_func_cfg(struct bnx2x *bp,
3046                                  struct tstorm_eth_function_common_config *tcfg,
3047                                  u16 abs_fid)
3048 {
3049         size_t size = sizeof(struct tstorm_eth_function_common_config);
3050
3051         u32 addr = BAR_TSTRORM_INTMEM +
3052                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3053
3054         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3055 }
3056
3057 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3058 {
3059         if (CHIP_IS_E1x(bp)) {
3060                 struct tstorm_eth_function_common_config tcfg = {0};
3061
3062                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3063         }
3064
3065         /* Enable the function in the FW */
3066         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3067         storm_memset_func_en(bp, p->func_id, 1);
3068
3069         /* spq */
3070         if (p->spq_active) {
3071                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3072                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3073                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3074         }
3075 }
3076
3077 /**
3078  * bnx2x_get_common_flags - Return common flags
3079  *
3080  * @bp          device handle
3081  * @fp          queue handle
3082  * @zero_stats  TRUE if statistics zeroing is needed
3083  *
3084  * Return the flags that are common for the Tx-only and not normal connections.
3085  */
3086 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3087                                             struct bnx2x_fastpath *fp,
3088                                             bool zero_stats)
3089 {
3090         unsigned long flags = 0;
3091
3092         /* PF driver will always initialize the Queue to an ACTIVE state */
3093         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3094
3095         /* tx only connections collect statistics (on the same index as the
3096          * parent connection). The statistics are zeroed when the parent
3097          * connection is initialized.
3098          */
3099
3100         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3101         if (zero_stats)
3102                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3103
3104         if (bp->flags & TX_SWITCHING)
3105                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3106
3107         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3108         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3109
3110 #ifdef BNX2X_STOP_ON_ERROR
3111         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3112 #endif
3113
3114         return flags;
3115 }
3116
3117 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3118                                        struct bnx2x_fastpath *fp,
3119                                        bool leading)
3120 {
3121         unsigned long flags = 0;
3122
3123         /* calculate other queue flags */
3124         if (IS_MF_SD(bp))
3125                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3126
3127         if (IS_FCOE_FP(fp)) {
3128                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3129                 /* For FCoE - force usage of default priority (for afex) */
3130                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3131         }
3132
3133         if (fp->mode != TPA_MODE_DISABLED) {
3134                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3135                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3136                 if (fp->mode == TPA_MODE_GRO)
3137                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3138         }
3139
3140         if (leading) {
3141                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3142                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3143         }
3144
3145         /* Always set HW VLAN stripping */
3146         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3147
3148         /* configure silent vlan removal */
3149         if (IS_MF_AFEX(bp))
3150                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3151
3152         return flags | bnx2x_get_common_flags(bp, fp, true);
3153 }
3154
3155 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3156         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3157         u8 cos)
3158 {
3159         gen_init->stat_id = bnx2x_stats_id(fp);
3160         gen_init->spcl_id = fp->cl_id;
3161
3162         /* Always use mini-jumbo MTU for FCoE L2 ring */
3163         if (IS_FCOE_FP(fp))
3164                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3165         else
3166                 gen_init->mtu = bp->dev->mtu;
3167
3168         gen_init->cos = cos;
3169
3170         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3171 }
3172
3173 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3174         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3175         struct bnx2x_rxq_setup_params *rxq_init)
3176 {
3177         u8 max_sge = 0;
3178         u16 sge_sz = 0;
3179         u16 tpa_agg_size = 0;
3180
3181         if (fp->mode != TPA_MODE_DISABLED) {
3182                 pause->sge_th_lo = SGE_TH_LO(bp);
3183                 pause->sge_th_hi = SGE_TH_HI(bp);
3184
3185                 /* validate SGE ring has enough to cross high threshold */
3186                 WARN_ON(bp->dropless_fc &&
3187                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3188                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3189
3190                 tpa_agg_size = TPA_AGG_SIZE;
3191                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3192                         SGE_PAGE_SHIFT;
3193                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3194                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3195                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3196         }
3197
3198         /* pause - not for e1 */
3199         if (!CHIP_IS_E1(bp)) {
3200                 pause->bd_th_lo = BD_TH_LO(bp);
3201                 pause->bd_th_hi = BD_TH_HI(bp);
3202
3203                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3204                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3205                 /*
3206                  * validate that rings have enough entries to cross
3207                  * high thresholds
3208                  */
3209                 WARN_ON(bp->dropless_fc &&
3210                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3211                                 bp->rx_ring_size);
3212                 WARN_ON(bp->dropless_fc &&
3213                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3214                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3215
3216                 pause->pri_map = 1;
3217         }
3218
3219         /* rxq setup */
3220         rxq_init->dscr_map = fp->rx_desc_mapping;
3221         rxq_init->sge_map = fp->rx_sge_mapping;
3222         rxq_init->rcq_map = fp->rx_comp_mapping;
3223         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3224
3225         /* This should be a maximum number of data bytes that may be
3226          * placed on the BD (not including paddings).
3227          */
3228         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3229                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3230
3231         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3232         rxq_init->tpa_agg_sz = tpa_agg_size;
3233         rxq_init->sge_buf_sz = sge_sz;
3234         rxq_init->max_sges_pkt = max_sge;
3235         rxq_init->rss_engine_id = BP_FUNC(bp);
3236         rxq_init->mcast_engine_id = BP_FUNC(bp);
3237
3238         /* Maximum number or simultaneous TPA aggregation for this Queue.
3239          *
3240          * For PF Clients it should be the maximum available number.
3241          * VF driver(s) may want to define it to a smaller value.
3242          */
3243         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3244
3245         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3246         rxq_init->fw_sb_id = fp->fw_sb_id;
3247
3248         if (IS_FCOE_FP(fp))
3249                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3250         else
3251                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3252         /* configure silent vlan removal
3253          * if multi function mode is afex, then mask default vlan
3254          */
3255         if (IS_MF_AFEX(bp)) {
3256                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3257                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3258         }
3259 }
3260
3261 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3262         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3263         u8 cos)
3264 {
3265         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3266         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3267         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3268         txq_init->fw_sb_id = fp->fw_sb_id;
3269
3270         /*
3271          * set the tss leading client id for TX classification ==
3272          * leading RSS client id
3273          */
3274         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3275
3276         if (IS_FCOE_FP(fp)) {
3277                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3278                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3279         }
3280 }
3281
3282 static void bnx2x_pf_init(struct bnx2x *bp)
3283 {
3284         struct bnx2x_func_init_params func_init = {0};
3285         struct event_ring_data eq_data = { {0} };
3286
3287         if (!CHIP_IS_E1x(bp)) {
3288                 /* reset IGU PF statistics: MSIX + ATTN */
3289                 /* PF */
3290                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3291                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3292                            (CHIP_MODE_IS_4_PORT(bp) ?
3293                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3294                 /* ATTN */
3295                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3296                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3297                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3298                            (CHIP_MODE_IS_4_PORT(bp) ?
3299                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3300         }
3301
3302         func_init.spq_active = true;
3303         func_init.pf_id = BP_FUNC(bp);
3304         func_init.func_id = BP_FUNC(bp);
3305         func_init.spq_map = bp->spq_mapping;
3306         func_init.spq_prod = bp->spq_prod_idx;
3307
3308         bnx2x_func_init(bp, &func_init);
3309
3310         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3311
3312         /*
3313          * Congestion management values depend on the link rate
3314          * There is no active link so initial link rate is set to 10 Gbps.
3315          * When the link comes up The congestion management values are
3316          * re-calculated according to the actual link rate.
3317          */
3318         bp->link_vars.line_speed = SPEED_10000;
3319         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3320
3321         /* Only the PMF sets the HW */
3322         if (bp->port.pmf)
3323                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3324
3325         /* init Event Queue - PCI bus guarantees correct endianity*/
3326         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3327         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3328         eq_data.producer = bp->eq_prod;
3329         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3330         eq_data.sb_id = DEF_SB_ID;
3331         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3332 }
3333
3334 static void bnx2x_e1h_disable(struct bnx2x *bp)
3335 {
3336         int port = BP_PORT(bp);
3337
3338         bnx2x_tx_disable(bp);
3339
3340         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3341 }
3342
3343 static void bnx2x_e1h_enable(struct bnx2x *bp)
3344 {
3345         int port = BP_PORT(bp);
3346
3347         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3348                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3349
3350         /* Tx queue should be only re-enabled */
3351         netif_tx_wake_all_queues(bp->dev);
3352
3353         /*
3354          * Should not call netif_carrier_on since it will be called if the link
3355          * is up when checking for link state
3356          */
3357 }
3358
3359 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3360
3361 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3362 {
3363         struct eth_stats_info *ether_stat =
3364                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3365         struct bnx2x_vlan_mac_obj *mac_obj =
3366                 &bp->sp_objs->mac_obj;
3367         int i;
3368
3369         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3370                 ETH_STAT_INFO_VERSION_LEN);
3371
3372         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3373          * mac_local field in ether_stat struct. The base address is offset by 2
3374          * bytes to account for the field being 8 bytes but a mac address is
3375          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3376          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3377          * allocated by the ether_stat struct, so the macs will land in their
3378          * proper positions.
3379          */
3380         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3381                 memset(ether_stat->mac_local + i, 0,
3382                        sizeof(ether_stat->mac_local[0]));
3383         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3384                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3385                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3386                                 ETH_ALEN);
3387         ether_stat->mtu_size = bp->dev->mtu;
3388         if (bp->dev->features & NETIF_F_RXCSUM)
3389                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3390         if (bp->dev->features & NETIF_F_TSO)
3391                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3392         ether_stat->feature_flags |= bp->common.boot_mode;
3393
3394         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3395
3396         ether_stat->txq_size = bp->tx_ring_size;
3397         ether_stat->rxq_size = bp->rx_ring_size;
3398
3399 #ifdef CONFIG_BNX2X_SRIOV
3400         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3401 #endif
3402 }
3403
3404 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3405 {
3406         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3407         struct fcoe_stats_info *fcoe_stat =
3408                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3409
3410         if (!CNIC_LOADED(bp))
3411                 return;
3412
3413         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3414
3415         fcoe_stat->qos_priority =
3416                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3417
3418         /* insert FCoE stats from ramrod response */
3419         if (!NO_FCOE(bp)) {
3420                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3421                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3422                         tstorm_queue_statistics;
3423
3424                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3425                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3426                         xstorm_queue_statistics;
3427
3428                 struct fcoe_statistics_params *fw_fcoe_stat =
3429                         &bp->fw_stats_data->fcoe;
3430
3431                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3432                           fcoe_stat->rx_bytes_lo,
3433                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3434
3435                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3436                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3437                           fcoe_stat->rx_bytes_lo,
3438                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3439
3440                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3441                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3442                           fcoe_stat->rx_bytes_lo,
3443                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3444
3445                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3446                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3447                           fcoe_stat->rx_bytes_lo,
3448                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3449
3450                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3451                           fcoe_stat->rx_frames_lo,
3452                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3453
3454                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3455                           fcoe_stat->rx_frames_lo,
3456                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3457
3458                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3459                           fcoe_stat->rx_frames_lo,
3460                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3461
3462                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3463                           fcoe_stat->rx_frames_lo,
3464                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3465
3466                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3467                           fcoe_stat->tx_bytes_lo,
3468                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3469
3470                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3471                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3472                           fcoe_stat->tx_bytes_lo,
3473                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3474
3475                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3476                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3477                           fcoe_stat->tx_bytes_lo,
3478                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3479
3480                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3481                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3482                           fcoe_stat->tx_bytes_lo,
3483                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3484
3485                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3486                           fcoe_stat->tx_frames_lo,
3487                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3488
3489                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3490                           fcoe_stat->tx_frames_lo,
3491                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3492
3493                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3494                           fcoe_stat->tx_frames_lo,
3495                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3496
3497                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3498                           fcoe_stat->tx_frames_lo,
3499                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3500         }
3501
3502         /* ask L5 driver to add data to the struct */
3503         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3504 }
3505
3506 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3507 {
3508         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3509         struct iscsi_stats_info *iscsi_stat =
3510                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3511
3512         if (!CNIC_LOADED(bp))
3513                 return;
3514
3515         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3516                ETH_ALEN);
3517
3518         iscsi_stat->qos_priority =
3519                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3520
3521         /* ask L5 driver to add data to the struct */
3522         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3523 }
3524
3525 /* called due to MCP event (on pmf):
3526  *      reread new bandwidth configuration
3527  *      configure FW
3528  *      notify others function about the change
3529  */
3530 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3531 {
3532         if (bp->link_vars.link_up) {
3533                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3534                 bnx2x_link_sync_notify(bp);
3535         }
3536         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3537 }
3538
3539 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3540 {
3541         bnx2x_config_mf_bw(bp);
3542         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3543 }
3544
3545 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3546 {
3547         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3548         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3549 }
3550
3551 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3552 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3553
3554 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3555 {
3556         enum drv_info_opcode op_code;
3557         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3558         bool release = false;
3559         int wait;
3560
3561         /* if drv_info version supported by MFW doesn't match - send NACK */
3562         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3563                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3564                 return;
3565         }
3566
3567         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3568                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3569
3570         /* Must prevent other flows from accessing drv_info_to_mcp */
3571         mutex_lock(&bp->drv_info_mutex);
3572
3573         memset(&bp->slowpath->drv_info_to_mcp, 0,
3574                sizeof(union drv_info_to_mcp));
3575
3576         switch (op_code) {
3577         case ETH_STATS_OPCODE:
3578                 bnx2x_drv_info_ether_stat(bp);
3579                 break;
3580         case FCOE_STATS_OPCODE:
3581                 bnx2x_drv_info_fcoe_stat(bp);
3582                 break;
3583         case ISCSI_STATS_OPCODE:
3584                 bnx2x_drv_info_iscsi_stat(bp);
3585                 break;
3586         default:
3587                 /* if op code isn't supported - send NACK */
3588                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3589                 goto out;
3590         }
3591
3592         /* if we got drv_info attn from MFW then these fields are defined in
3593          * shmem2 for sure
3594          */
3595         SHMEM2_WR(bp, drv_info_host_addr_lo,
3596                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3597         SHMEM2_WR(bp, drv_info_host_addr_hi,
3598                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3599
3600         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3601
3602         /* Since possible management wants both this and get_driver_version
3603          * need to wait until management notifies us it finished utilizing
3604          * the buffer.
3605          */
3606         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3607                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3608         } else if (!bp->drv_info_mng_owner) {
3609                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3610
3611                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3612                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3613
3614                         /* Management is done; need to clear indication */
3615                         if (indication & bit) {
3616                                 SHMEM2_WR(bp, mfw_drv_indication,
3617                                           indication & ~bit);
3618                                 release = true;
3619                                 break;
3620                         }
3621
3622                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3623                 }
3624         }
3625         if (!release) {
3626                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3627                 bp->drv_info_mng_owner = true;
3628         }
3629
3630 out:
3631         mutex_unlock(&bp->drv_info_mutex);
3632 }
3633
3634 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3635 {
3636         u8 vals[4];
3637         int i = 0;
3638
3639         if (bnx2x_format) {
3640                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3641                            &vals[0], &vals[1], &vals[2], &vals[3]);
3642                 if (i > 0)
3643                         vals[0] -= '0';
3644         } else {
3645                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3646                            &vals[0], &vals[1], &vals[2], &vals[3]);
3647         }
3648
3649         while (i < 4)
3650                 vals[i++] = 0;
3651
3652         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3653 }
3654
3655 void bnx2x_update_mng_version(struct bnx2x *bp)
3656 {
3657         u32 iscsiver = DRV_VER_NOT_LOADED;
3658         u32 fcoever = DRV_VER_NOT_LOADED;
3659         u32 ethver = DRV_VER_NOT_LOADED;
3660         int idx = BP_FW_MB_IDX(bp);
3661         u8 *version;
3662
3663         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3664                 return;
3665
3666         mutex_lock(&bp->drv_info_mutex);
3667         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3668         if (bp->drv_info_mng_owner)
3669                 goto out;
3670
3671         if (bp->state != BNX2X_STATE_OPEN)
3672                 goto out;
3673
3674         /* Parse ethernet driver version */
3675         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3676         if (!CNIC_LOADED(bp))
3677                 goto out;
3678
3679         /* Try getting storage driver version via cnic */
3680         memset(&bp->slowpath->drv_info_to_mcp, 0,
3681                sizeof(union drv_info_to_mcp));
3682         bnx2x_drv_info_iscsi_stat(bp);
3683         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3684         iscsiver = bnx2x_update_mng_version_utility(version, false);
3685
3686         memset(&bp->slowpath->drv_info_to_mcp, 0,
3687                sizeof(union drv_info_to_mcp));
3688         bnx2x_drv_info_fcoe_stat(bp);
3689         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3690         fcoever = bnx2x_update_mng_version_utility(version, false);
3691
3692 out:
3693         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3694         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3695         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3696
3697         mutex_unlock(&bp->drv_info_mutex);
3698
3699         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3700            ethver, iscsiver, fcoever);
3701 }
3702
3703 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3704 {
3705         struct timeval epoc;
3706         u32 drv_ver;
3707         u32 valid_dump;
3708
3709         if (!SHMEM2_HAS(bp, drv_info))
3710                 return;
3711
3712         /* Update Driver load time */
3713         do_gettimeofday(&epoc);
3714         SHMEM2_WR(bp, drv_info.epoc, epoc.tv_sec);
3715
3716         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3717         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3718
3719         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3720
3721         /* Check & notify On-Chip dump. */
3722         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3723
3724         if (valid_dump & FIRST_DUMP_VALID)
3725                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3726
3727         if (valid_dump & SECOND_DUMP_VALID)
3728                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3729 }
3730
3731 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3732 {
3733         u32 cmd_ok, cmd_fail;
3734
3735         /* sanity */
3736         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3737             event & DRV_STATUS_OEM_EVENT_MASK) {
3738                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3739                 return;
3740         }
3741
3742         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3743                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3744                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3745         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3746                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3747                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3748         }
3749
3750         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3751
3752         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3753                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3754                 /* This is the only place besides the function initialization
3755                  * where the bp->flags can change so it is done without any
3756                  * locks
3757                  */
3758                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3759                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3760                         bp->flags |= MF_FUNC_DIS;
3761
3762                         bnx2x_e1h_disable(bp);
3763                 } else {
3764                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3765                         bp->flags &= ~MF_FUNC_DIS;
3766
3767                         bnx2x_e1h_enable(bp);
3768                 }
3769                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3770                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3771         }
3772
3773         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3774                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3775                 bnx2x_config_mf_bw(bp);
3776                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3777                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3778         }
3779
3780         /* Report results to MCP */
3781         if (event)
3782                 bnx2x_fw_command(bp, cmd_fail, 0);
3783         else
3784                 bnx2x_fw_command(bp, cmd_ok, 0);
3785 }
3786
3787 /* must be called under the spq lock */
3788 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3789 {
3790         struct eth_spe *next_spe = bp->spq_prod_bd;
3791
3792         if (bp->spq_prod_bd == bp->spq_last_bd) {
3793                 bp->spq_prod_bd = bp->spq;
3794                 bp->spq_prod_idx = 0;
3795                 DP(BNX2X_MSG_SP, "end of spq\n");
3796         } else {
3797                 bp->spq_prod_bd++;
3798                 bp->spq_prod_idx++;
3799         }
3800         return next_spe;
3801 }
3802
3803 /* must be called under the spq lock */
3804 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3805 {
3806         int func = BP_FUNC(bp);
3807
3808         /*
3809          * Make sure that BD data is updated before writing the producer:
3810          * BD data is written to the memory, the producer is read from the
3811          * memory, thus we need a full memory barrier to ensure the ordering.
3812          */
3813         mb();
3814
3815         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3816                  bp->spq_prod_idx);
3817         mmiowb();
3818 }
3819
3820 /**
3821  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3822  *
3823  * @cmd:        command to check
3824  * @cmd_type:   command type
3825  */
3826 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3827 {
3828         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3829             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3830             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3831             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3832             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3833             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3834             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3835                 return true;
3836         else
3837                 return false;
3838 }
3839
3840 /**
3841  * bnx2x_sp_post - place a single command on an SP ring
3842  *
3843  * @bp:         driver handle
3844  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3845  * @cid:        SW CID the command is related to
3846  * @data_hi:    command private data address (high 32 bits)
3847  * @data_lo:    command private data address (low 32 bits)
3848  * @cmd_type:   command type (e.g. NONE, ETH)
3849  *
3850  * SP data is handled as if it's always an address pair, thus data fields are
3851  * not swapped to little endian in upper functions. Instead this function swaps
3852  * data as if it's two u32 fields.
3853  */
3854 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3855                   u32 data_hi, u32 data_lo, int cmd_type)
3856 {
3857         struct eth_spe *spe;
3858         u16 type;
3859         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3860
3861 #ifdef BNX2X_STOP_ON_ERROR
3862         if (unlikely(bp->panic)) {
3863                 BNX2X_ERR("Can't post SP when there is panic\n");
3864                 return -EIO;
3865         }
3866 #endif
3867
3868         spin_lock_bh(&bp->spq_lock);
3869
3870         if (common) {
3871                 if (!atomic_read(&bp->eq_spq_left)) {
3872                         BNX2X_ERR("BUG! EQ ring full!\n");
3873                         spin_unlock_bh(&bp->spq_lock);
3874                         bnx2x_panic();
3875                         return -EBUSY;
3876                 }
3877         } else if (!atomic_read(&bp->cq_spq_left)) {
3878                         BNX2X_ERR("BUG! SPQ ring full!\n");
3879                         spin_unlock_bh(&bp->spq_lock);
3880                         bnx2x_panic();
3881                         return -EBUSY;
3882         }
3883
3884         spe = bnx2x_sp_get_next(bp);
3885
3886         /* CID needs port number to be encoded int it */
3887         spe->hdr.conn_and_cmd_data =
3888                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3889                                     HW_CID(bp, cid));
3890
3891         /* In some cases, type may already contain the func-id
3892          * mainly in SRIOV related use cases, so we add it here only
3893          * if it's not already set.
3894          */
3895         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3896                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3897                         SPE_HDR_CONN_TYPE;
3898                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3899                          SPE_HDR_FUNCTION_ID);
3900         } else {
3901                 type = cmd_type;
3902         }
3903
3904         spe->hdr.type = cpu_to_le16(type);
3905
3906         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3907         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3908
3909         /*
3910          * It's ok if the actual decrement is issued towards the memory
3911          * somewhere between the spin_lock and spin_unlock. Thus no
3912          * more explicit memory barrier is needed.
3913          */
3914         if (common)
3915                 atomic_dec(&bp->eq_spq_left);
3916         else
3917                 atomic_dec(&bp->cq_spq_left);
3918
3919         DP(BNX2X_MSG_SP,
3920            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3921            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3922            (u32)(U64_LO(bp->spq_mapping) +
3923            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3924            HW_CID(bp, cid), data_hi, data_lo, type,
3925            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3926
3927         bnx2x_sp_prod_update(bp);
3928         spin_unlock_bh(&bp->spq_lock);
3929         return 0;
3930 }
3931
3932 /* acquire split MCP access lock register */
3933 static int bnx2x_acquire_alr(struct bnx2x *bp)
3934 {
3935         u32 j, val;
3936         int rc = 0;
3937
3938         might_sleep();
3939         for (j = 0; j < 1000; j++) {
3940                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3941                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3942                 if (val & MCPR_ACCESS_LOCK_LOCK)
3943                         break;
3944
3945                 usleep_range(5000, 10000);
3946         }
3947         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3948                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3949                 rc = -EBUSY;
3950         }
3951
3952         return rc;
3953 }
3954
3955 /* release split MCP access lock register */
3956 static void bnx2x_release_alr(struct bnx2x *bp)
3957 {
3958         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3959 }
3960
3961 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3962 #define BNX2X_DEF_SB_IDX        0x0002
3963
3964 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3965 {
3966         struct host_sp_status_block *def_sb = bp->def_status_blk;
3967         u16 rc = 0;
3968
3969         barrier(); /* status block is written to by the chip */
3970         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3971                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3972                 rc |= BNX2X_DEF_SB_ATT_IDX;
3973         }
3974
3975         if (bp->def_idx != def_sb->sp_sb.running_index) {
3976                 bp->def_idx = def_sb->sp_sb.running_index;
3977                 rc |= BNX2X_DEF_SB_IDX;
3978         }
3979
3980         /* Do not reorder: indices reading should complete before handling */
3981         barrier();
3982         return rc;
3983 }
3984
3985 /*
3986  * slow path service functions
3987  */
3988
3989 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3990 {
3991         int port = BP_PORT(bp);
3992         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3993                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3994         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3995                                        NIG_REG_MASK_INTERRUPT_PORT0;
3996         u32 aeu_mask;
3997         u32 nig_mask = 0;
3998         u32 reg_addr;
3999
4000         if (bp->attn_state & asserted)
4001                 BNX2X_ERR("IGU ERROR\n");
4002
4003         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4004         aeu_mask = REG_RD(bp, aeu_addr);
4005
4006         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4007            aeu_mask, asserted);
4008         aeu_mask &= ~(asserted & 0x3ff);
4009         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4010
4011         REG_WR(bp, aeu_addr, aeu_mask);
4012         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4013
4014         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4015         bp->attn_state |= asserted;
4016         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4017
4018         if (asserted & ATTN_HARD_WIRED_MASK) {
4019                 if (asserted & ATTN_NIG_FOR_FUNC) {
4020
4021                         bnx2x_acquire_phy_lock(bp);
4022
4023                         /* save nig interrupt mask */
4024                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4025
4026                         /* If nig_mask is not set, no need to call the update
4027                          * function.
4028                          */
4029                         if (nig_mask) {
4030                                 REG_WR(bp, nig_int_mask_addr, 0);
4031
4032                                 bnx2x_link_attn(bp);
4033                         }
4034
4035                         /* handle unicore attn? */
4036                 }
4037                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4038                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4039
4040                 if (asserted & GPIO_2_FUNC)
4041                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4042
4043                 if (asserted & GPIO_3_FUNC)
4044                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4045
4046                 if (asserted & GPIO_4_FUNC)
4047                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4048
4049                 if (port == 0) {
4050                         if (asserted & ATTN_GENERAL_ATTN_1) {
4051                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4052                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4053                         }
4054                         if (asserted & ATTN_GENERAL_ATTN_2) {
4055                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4056                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4057                         }
4058                         if (asserted & ATTN_GENERAL_ATTN_3) {
4059                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4060                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4061                         }
4062                 } else {
4063                         if (asserted & ATTN_GENERAL_ATTN_4) {
4064                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4065                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4066                         }
4067                         if (asserted & ATTN_GENERAL_ATTN_5) {
4068                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4069                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4070                         }
4071                         if (asserted & ATTN_GENERAL_ATTN_6) {
4072                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4073                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4074                         }
4075                 }
4076
4077         } /* if hardwired */
4078
4079         if (bp->common.int_block == INT_BLOCK_HC)
4080                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4081                             COMMAND_REG_ATTN_BITS_SET);
4082         else
4083                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4084
4085         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4086            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4087         REG_WR(bp, reg_addr, asserted);
4088
4089         /* now set back the mask */
4090         if (asserted & ATTN_NIG_FOR_FUNC) {
4091                 /* Verify that IGU ack through BAR was written before restoring
4092                  * NIG mask. This loop should exit after 2-3 iterations max.
4093                  */
4094                 if (bp->common.int_block != INT_BLOCK_HC) {
4095                         u32 cnt = 0, igu_acked;
4096                         do {
4097                                 igu_acked = REG_RD(bp,
4098                                                    IGU_REG_ATTENTION_ACK_BITS);
4099                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4100                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4101                         if (!igu_acked)
4102                                 DP(NETIF_MSG_HW,
4103                                    "Failed to verify IGU ack on time\n");
4104                         barrier();
4105                 }
4106                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4107                 bnx2x_release_phy_lock(bp);
4108         }
4109 }
4110
4111 static void bnx2x_fan_failure(struct bnx2x *bp)
4112 {
4113         int port = BP_PORT(bp);
4114         u32 ext_phy_config;
4115         /* mark the failure */
4116         ext_phy_config =
4117                 SHMEM_RD(bp,
4118                          dev_info.port_hw_config[port].external_phy_config);
4119
4120         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4121         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4122         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4123                  ext_phy_config);
4124
4125         /* log the failure */
4126         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4127                             "Please contact OEM Support for assistance\n");
4128
4129         /* Schedule device reset (unload)
4130          * This is due to some boards consuming sufficient power when driver is
4131          * up to overheat if fan fails.
4132          */
4133         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4134 }
4135
4136 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4137 {
4138         int port = BP_PORT(bp);
4139         int reg_offset;
4140         u32 val;
4141
4142         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4143                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4144
4145         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4146
4147                 val = REG_RD(bp, reg_offset);
4148                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4149                 REG_WR(bp, reg_offset, val);
4150
4151                 BNX2X_ERR("SPIO5 hw attention\n");
4152
4153                 /* Fan failure attention */
4154                 bnx2x_hw_reset_phy(&bp->link_params);
4155                 bnx2x_fan_failure(bp);
4156         }
4157
4158         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4159                 bnx2x_acquire_phy_lock(bp);
4160                 bnx2x_handle_module_detect_int(&bp->link_params);
4161                 bnx2x_release_phy_lock(bp);
4162         }
4163
4164         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4165
4166                 val = REG_RD(bp, reg_offset);
4167                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4168                 REG_WR(bp, reg_offset, val);
4169
4170                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4171                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4172                 bnx2x_panic();
4173         }
4174 }
4175
4176 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4177 {
4178         u32 val;
4179
4180         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4181
4182                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4183                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4184                 /* DORQ discard attention */
4185                 if (val & 0x2)
4186                         BNX2X_ERR("FATAL error from DORQ\n");
4187         }
4188
4189         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4190
4191                 int port = BP_PORT(bp);
4192                 int reg_offset;
4193
4194                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4195                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4196
4197                 val = REG_RD(bp, reg_offset);
4198                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4199                 REG_WR(bp, reg_offset, val);
4200
4201                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4202                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4203                 bnx2x_panic();
4204         }
4205 }
4206
4207 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4208 {
4209         u32 val;
4210
4211         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4212
4213                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4214                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4215                 /* CFC error attention */
4216                 if (val & 0x2)
4217                         BNX2X_ERR("FATAL error from CFC\n");
4218         }
4219
4220         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4221                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4222                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4223                 /* RQ_USDMDP_FIFO_OVERFLOW */
4224                 if (val & 0x18000)
4225                         BNX2X_ERR("FATAL error from PXP\n");
4226
4227                 if (!CHIP_IS_E1x(bp)) {
4228                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4229                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4230                 }
4231         }
4232
4233         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4234
4235                 int port = BP_PORT(bp);
4236                 int reg_offset;
4237
4238                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4239                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4240
4241                 val = REG_RD(bp, reg_offset);
4242                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4243                 REG_WR(bp, reg_offset, val);
4244
4245                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4246                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4247                 bnx2x_panic();
4248         }
4249 }
4250
4251 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4252 {
4253         u32 val;
4254
4255         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4256
4257                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4258                         int func = BP_FUNC(bp);
4259
4260                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4261                         bnx2x_read_mf_cfg(bp);
4262                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4263                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4264                         val = SHMEM_RD(bp,
4265                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4266
4267                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4268                                    DRV_STATUS_OEM_EVENT_MASK))
4269                                 bnx2x_oem_event(bp,
4270                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4271                                                 DRV_STATUS_OEM_EVENT_MASK)));
4272
4273                         if (val & DRV_STATUS_SET_MF_BW)
4274                                 bnx2x_set_mf_bw(bp);
4275
4276                         if (val & DRV_STATUS_DRV_INFO_REQ)
4277                                 bnx2x_handle_drv_info_req(bp);
4278
4279                         if (val & DRV_STATUS_VF_DISABLED)
4280                                 bnx2x_schedule_iov_task(bp,
4281                                                         BNX2X_IOV_HANDLE_FLR);
4282
4283                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4284                                 bnx2x_pmf_update(bp);
4285
4286                         if (bp->port.pmf &&
4287                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4288                                 bp->dcbx_enabled > 0)
4289                                 /* start dcbx state machine */
4290                                 bnx2x_dcbx_set_params(bp,
4291                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4292                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4293                                 bnx2x_handle_afex_cmd(bp,
4294                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4295                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4296                                 bnx2x_handle_eee_event(bp);
4297
4298                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4299                                 bnx2x_handle_update_svid_cmd(bp);
4300
4301                         if (bp->link_vars.periodic_flags &
4302                             PERIODIC_FLAGS_LINK_EVENT) {
4303                                 /*  sync with link */
4304                                 bnx2x_acquire_phy_lock(bp);
4305                                 bp->link_vars.periodic_flags &=
4306                                         ~PERIODIC_FLAGS_LINK_EVENT;
4307                                 bnx2x_release_phy_lock(bp);
4308                                 if (IS_MF(bp))
4309                                         bnx2x_link_sync_notify(bp);
4310                                 bnx2x_link_report(bp);
4311                         }
4312                         /* Always call it here: bnx2x_link_report() will
4313                          * prevent the link indication duplication.
4314                          */
4315                         bnx2x__link_status_update(bp);
4316                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4317
4318                         BNX2X_ERR("MC assert!\n");
4319                         bnx2x_mc_assert(bp);
4320                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4321                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4322                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4323                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4324                         bnx2x_panic();
4325
4326                 } else if (attn & BNX2X_MCP_ASSERT) {
4327
4328                         BNX2X_ERR("MCP assert!\n");
4329                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4330                         bnx2x_fw_dump(bp);
4331
4332                 } else
4333                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4334         }
4335
4336         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4337                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4338                 if (attn & BNX2X_GRC_TIMEOUT) {
4339                         val = CHIP_IS_E1(bp) ? 0 :
4340                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4341                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4342                 }
4343                 if (attn & BNX2X_GRC_RSV) {
4344                         val = CHIP_IS_E1(bp) ? 0 :
4345                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4346                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4347                 }
4348                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4349         }
4350 }
4351
4352 /*
4353  * Bits map:
4354  * 0-7   - Engine0 load counter.
4355  * 8-15  - Engine1 load counter.
4356  * 16    - Engine0 RESET_IN_PROGRESS bit.
4357  * 17    - Engine1 RESET_IN_PROGRESS bit.
4358  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4359  *         on the engine
4360  * 19    - Engine1 ONE_IS_LOADED.
4361  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4362  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4363  *         just the one belonging to its engine).
4364  *
4365  */
4366 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4367
4368 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4369 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4370 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4371 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4372 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4373 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4374 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4375
4376 /*
4377  * Set the GLOBAL_RESET bit.
4378  *
4379  * Should be run under rtnl lock
4380  */
4381 void bnx2x_set_reset_global(struct bnx2x *bp)
4382 {
4383         u32 val;
4384         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4385         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4386         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4387         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4388 }
4389
4390 /*
4391  * Clear the GLOBAL_RESET bit.
4392  *
4393  * Should be run under rtnl lock
4394  */
4395 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4396 {
4397         u32 val;
4398         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4399         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4400         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4401         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4402 }
4403
4404 /*
4405  * Checks the GLOBAL_RESET bit.
4406  *
4407  * should be run under rtnl lock
4408  */
4409 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4410 {
4411         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4412
4413         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4414         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4415 }
4416
4417 /*
4418  * Clear RESET_IN_PROGRESS bit for the current engine.
4419  *
4420  * Should be run under rtnl lock
4421  */
4422 static void bnx2x_set_reset_done(struct bnx2x *bp)
4423 {
4424         u32 val;
4425         u32 bit = BP_PATH(bp) ?
4426                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4427         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4428         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4429
4430         /* Clear the bit */
4431         val &= ~bit;
4432         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4433
4434         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4435 }
4436
4437 /*
4438  * Set RESET_IN_PROGRESS for the current engine.
4439  *
4440  * should be run under rtnl lock
4441  */
4442 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4443 {
4444         u32 val;
4445         u32 bit = BP_PATH(bp) ?
4446                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4447         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4448         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4449
4450         /* Set the bit */
4451         val |= bit;
4452         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4453         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4454 }
4455
4456 /*
4457  * Checks the RESET_IN_PROGRESS bit for the given engine.
4458  * should be run under rtnl lock
4459  */
4460 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4461 {
4462         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4463         u32 bit = engine ?
4464                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4465
4466         /* return false if bit is set */
4467         return (val & bit) ? false : true;
4468 }
4469
4470 /*
4471  * set pf load for the current pf.
4472  *
4473  * should be run under rtnl lock
4474  */
4475 void bnx2x_set_pf_load(struct bnx2x *bp)
4476 {
4477         u32 val1, val;
4478         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4479                              BNX2X_PATH0_LOAD_CNT_MASK;
4480         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4481                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4482
4483         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4484         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4485
4486         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4487
4488         /* get the current counter value */
4489         val1 = (val & mask) >> shift;
4490
4491         /* set bit of that PF */
4492         val1 |= (1 << bp->pf_num);
4493
4494         /* clear the old value */
4495         val &= ~mask;
4496
4497         /* set the new one */
4498         val |= ((val1 << shift) & mask);
4499
4500         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4501         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4502 }
4503
4504 /**
4505  * bnx2x_clear_pf_load - clear pf load mark
4506  *
4507  * @bp:         driver handle
4508  *
4509  * Should be run under rtnl lock.
4510  * Decrements the load counter for the current engine. Returns
4511  * whether other functions are still loaded
4512  */
4513 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4514 {
4515         u32 val1, val;
4516         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4517                              BNX2X_PATH0_LOAD_CNT_MASK;
4518         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4519                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4520
4521         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4522         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4523         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4524
4525         /* get the current counter value */
4526         val1 = (val & mask) >> shift;
4527
4528         /* clear bit of that PF */
4529         val1 &= ~(1 << bp->pf_num);
4530
4531         /* clear the old value */
4532         val &= ~mask;
4533
4534         /* set the new one */
4535         val |= ((val1 << shift) & mask);
4536
4537         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4538         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4539         return val1 != 0;
4540 }
4541
4542 /*
4543  * Read the load status for the current engine.
4544  *
4545  * should be run under rtnl lock
4546  */
4547 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4548 {
4549         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4550                              BNX2X_PATH0_LOAD_CNT_MASK);
4551         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4552                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4553         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4554
4555         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4556
4557         val = (val & mask) >> shift;
4558
4559         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4560            engine, val);
4561
4562         return val != 0;
4563 }
4564
4565 static void _print_parity(struct bnx2x *bp, u32 reg)
4566 {
4567         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4568 }
4569
4570 static void _print_next_block(int idx, const char *blk)
4571 {
4572         pr_cont("%s%s", idx ? ", " : "", blk);
4573 }
4574
4575 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4576                                             int *par_num, bool print)
4577 {
4578         u32 cur_bit;
4579         bool res;
4580         int i;
4581
4582         res = false;
4583
4584         for (i = 0; sig; i++) {
4585                 cur_bit = (0x1UL << i);
4586                 if (sig & cur_bit) {
4587                         res |= true; /* Each bit is real error! */
4588
4589                         if (print) {
4590                                 switch (cur_bit) {
4591                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4592                                         _print_next_block((*par_num)++, "BRB");
4593                                         _print_parity(bp,
4594                                                       BRB1_REG_BRB1_PRTY_STS);
4595                                         break;
4596                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++,
4598                                                           "PARSER");
4599                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4600                                         break;
4601                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4602                                         _print_next_block((*par_num)++, "TSDM");
4603                                         _print_parity(bp,
4604                                                       TSDM_REG_TSDM_PRTY_STS);
4605                                         break;
4606                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4607                                         _print_next_block((*par_num)++,
4608                                                           "SEARCHER");
4609                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4610                                         break;
4611                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4612                                         _print_next_block((*par_num)++, "TCM");
4613                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4614                                         break;
4615                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4616                                         _print_next_block((*par_num)++,
4617                                                           "TSEMI");
4618                                         _print_parity(bp,
4619                                                       TSEM_REG_TSEM_PRTY_STS_0);
4620                                         _print_parity(bp,
4621                                                       TSEM_REG_TSEM_PRTY_STS_1);
4622                                         break;
4623                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4624                                         _print_next_block((*par_num)++, "XPB");
4625                                         _print_parity(bp, GRCBASE_XPB +
4626                                                           PB_REG_PB_PRTY_STS);
4627                                         break;
4628                                 }
4629                         }
4630
4631                         /* Clear the bit */
4632                         sig &= ~cur_bit;
4633                 }
4634         }
4635
4636         return res;
4637 }
4638
4639 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4640                                             int *par_num, bool *global,
4641                                             bool print)
4642 {
4643         u32 cur_bit;
4644         bool res;
4645         int i;
4646
4647         res = false;
4648
4649         for (i = 0; sig; i++) {
4650                 cur_bit = (0x1UL << i);
4651                 if (sig & cur_bit) {
4652                         res |= true; /* Each bit is real error! */
4653                         switch (cur_bit) {
4654                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4655                                 if (print) {
4656                                         _print_next_block((*par_num)++, "PBF");
4657                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4658                                 }
4659                                 break;
4660                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4661                                 if (print) {
4662                                         _print_next_block((*par_num)++, "QM");
4663                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4664                                 }
4665                                 break;
4666                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4667                                 if (print) {
4668                                         _print_next_block((*par_num)++, "TM");
4669                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4670                                 }
4671                                 break;
4672                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4673                                 if (print) {
4674                                         _print_next_block((*par_num)++, "XSDM");
4675                                         _print_parity(bp,
4676                                                       XSDM_REG_XSDM_PRTY_STS);
4677                                 }
4678                                 break;
4679                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4680                                 if (print) {
4681                                         _print_next_block((*par_num)++, "XCM");
4682                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4683                                 }
4684                                 break;
4685                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4686                                 if (print) {
4687                                         _print_next_block((*par_num)++,
4688                                                           "XSEMI");
4689                                         _print_parity(bp,
4690                                                       XSEM_REG_XSEM_PRTY_STS_0);
4691                                         _print_parity(bp,
4692                                                       XSEM_REG_XSEM_PRTY_STS_1);
4693                                 }
4694                                 break;
4695                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4696                                 if (print) {
4697                                         _print_next_block((*par_num)++,
4698                                                           "DOORBELLQ");
4699                                         _print_parity(bp,
4700                                                       DORQ_REG_DORQ_PRTY_STS);
4701                                 }
4702                                 break;
4703                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4704                                 if (print) {
4705                                         _print_next_block((*par_num)++, "NIG");
4706                                         if (CHIP_IS_E1x(bp)) {
4707                                                 _print_parity(bp,
4708                                                         NIG_REG_NIG_PRTY_STS);
4709                                         } else {
4710                                                 _print_parity(bp,
4711                                                         NIG_REG_NIG_PRTY_STS_0);
4712                                                 _print_parity(bp,
4713                                                         NIG_REG_NIG_PRTY_STS_1);
4714                                         }
4715                                 }
4716                                 break;
4717                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4718                                 if (print)
4719                                         _print_next_block((*par_num)++,
4720                                                           "VAUX PCI CORE");
4721                                 *global = true;
4722                                 break;
4723                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4724                                 if (print) {
4725                                         _print_next_block((*par_num)++,
4726                                                           "DEBUG");
4727                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4728                                 }
4729                                 break;
4730                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4731                                 if (print) {
4732                                         _print_next_block((*par_num)++, "USDM");
4733                                         _print_parity(bp,
4734                                                       USDM_REG_USDM_PRTY_STS);
4735                                 }
4736                                 break;
4737                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4738                                 if (print) {
4739                                         _print_next_block((*par_num)++, "UCM");
4740                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4741                                 }
4742                                 break;
4743                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4744                                 if (print) {
4745                                         _print_next_block((*par_num)++,
4746                                                           "USEMI");
4747                                         _print_parity(bp,
4748                                                       USEM_REG_USEM_PRTY_STS_0);
4749                                         _print_parity(bp,
4750                                                       USEM_REG_USEM_PRTY_STS_1);
4751                                 }
4752                                 break;
4753                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4754                                 if (print) {
4755                                         _print_next_block((*par_num)++, "UPB");
4756                                         _print_parity(bp, GRCBASE_UPB +
4757                                                           PB_REG_PB_PRTY_STS);
4758                                 }
4759                                 break;
4760                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4761                                 if (print) {
4762                                         _print_next_block((*par_num)++, "CSDM");
4763                                         _print_parity(bp,
4764                                                       CSDM_REG_CSDM_PRTY_STS);
4765                                 }
4766                                 break;
4767                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4768                                 if (print) {
4769                                         _print_next_block((*par_num)++, "CCM");
4770                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4771                                 }
4772                                 break;
4773                         }
4774
4775                         /* Clear the bit */
4776                         sig &= ~cur_bit;
4777                 }
4778         }
4779
4780         return res;
4781 }
4782
4783 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4784                                             int *par_num, bool print)
4785 {
4786         u32 cur_bit;
4787         bool res;
4788         int i;
4789
4790         res = false;
4791
4792         for (i = 0; sig; i++) {
4793                 cur_bit = (0x1UL << i);
4794                 if (sig & cur_bit) {
4795                         res = true; /* Each bit is real error! */
4796                         if (print) {
4797                                 switch (cur_bit) {
4798                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4799                                         _print_next_block((*par_num)++,
4800                                                           "CSEMI");
4801                                         _print_parity(bp,
4802                                                       CSEM_REG_CSEM_PRTY_STS_0);
4803                                         _print_parity(bp,
4804                                                       CSEM_REG_CSEM_PRTY_STS_1);
4805                                         break;
4806                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4807                                         _print_next_block((*par_num)++, "PXP");
4808                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4809                                         _print_parity(bp,
4810                                                       PXP2_REG_PXP2_PRTY_STS_0);
4811                                         _print_parity(bp,
4812                                                       PXP2_REG_PXP2_PRTY_STS_1);
4813                                         break;
4814                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4815                                         _print_next_block((*par_num)++,
4816                                                           "PXPPCICLOCKCLIENT");
4817                                         break;
4818                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4819                                         _print_next_block((*par_num)++, "CFC");
4820                                         _print_parity(bp,
4821                                                       CFC_REG_CFC_PRTY_STS);
4822                                         break;
4823                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4824                                         _print_next_block((*par_num)++, "CDU");
4825                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4826                                         break;
4827                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4828                                         _print_next_block((*par_num)++, "DMAE");
4829                                         _print_parity(bp,
4830                                                       DMAE_REG_DMAE_PRTY_STS);
4831                                         break;
4832                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4833                                         _print_next_block((*par_num)++, "IGU");
4834                                         if (CHIP_IS_E1x(bp))
4835                                                 _print_parity(bp,
4836                                                         HC_REG_HC_PRTY_STS);
4837                                         else
4838                                                 _print_parity(bp,
4839                                                         IGU_REG_IGU_PRTY_STS);
4840                                         break;
4841                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4842                                         _print_next_block((*par_num)++, "MISC");
4843                                         _print_parity(bp,
4844                                                       MISC_REG_MISC_PRTY_STS);
4845                                         break;
4846                                 }
4847                         }
4848
4849                         /* Clear the bit */
4850                         sig &= ~cur_bit;
4851                 }
4852         }
4853
4854         return res;
4855 }
4856
4857 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4858                                             int *par_num, bool *global,
4859                                             bool print)
4860 {
4861         bool res = false;
4862         u32 cur_bit;
4863         int i;
4864
4865         for (i = 0; sig; i++) {
4866                 cur_bit = (0x1UL << i);
4867                 if (sig & cur_bit) {
4868                         switch (cur_bit) {
4869                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4870                                 if (print)
4871                                         _print_next_block((*par_num)++,
4872                                                           "MCP ROM");
4873                                 *global = true;
4874                                 res = true;
4875                                 break;
4876                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4877                                 if (print)
4878                                         _print_next_block((*par_num)++,
4879                                                           "MCP UMP RX");
4880                                 *global = true;
4881                                 res = true;
4882                                 break;
4883                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4884                                 if (print)
4885                                         _print_next_block((*par_num)++,
4886                                                           "MCP UMP TX");
4887                                 *global = true;
4888                                 res = true;
4889                                 break;
4890                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4891                                 (*par_num)++;
4892                                 /* clear latched SCPAD PATIRY from MCP */
4893                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4894                                        1UL << 10);
4895                                 break;
4896                         }
4897
4898                         /* Clear the bit */
4899                         sig &= ~cur_bit;
4900                 }
4901         }
4902
4903         return res;
4904 }
4905
4906 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4907                                             int *par_num, bool print)
4908 {
4909         u32 cur_bit;
4910         bool res;
4911         int i;
4912
4913         res = false;
4914
4915         for (i = 0; sig; i++) {
4916                 cur_bit = (0x1UL << i);
4917                 if (sig & cur_bit) {
4918                         res = true; /* Each bit is real error! */
4919                         if (print) {
4920                                 switch (cur_bit) {
4921                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4922                                         _print_next_block((*par_num)++,
4923                                                           "PGLUE_B");
4924                                         _print_parity(bp,
4925                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4926                                         break;
4927                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4928                                         _print_next_block((*par_num)++, "ATC");
4929                                         _print_parity(bp,
4930                                                       ATC_REG_ATC_PRTY_STS);
4931                                         break;
4932                                 }
4933                         }
4934                         /* Clear the bit */
4935                         sig &= ~cur_bit;
4936                 }
4937         }
4938
4939         return res;
4940 }
4941
4942 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4943                               u32 *sig)
4944 {
4945         bool res = false;
4946
4947         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4948             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4949             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4950             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4951             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4952                 int par_num = 0;
4953
4954                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4955                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4956                           sig[0] & HW_PRTY_ASSERT_SET_0,
4957                           sig[1] & HW_PRTY_ASSERT_SET_1,
4958                           sig[2] & HW_PRTY_ASSERT_SET_2,
4959                           sig[3] & HW_PRTY_ASSERT_SET_3,
4960                           sig[4] & HW_PRTY_ASSERT_SET_4);
4961                 if (print) {
4962                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4963                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4964                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4965                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4966                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4967                                 netdev_err(bp->dev,
4968                                            "Parity errors detected in blocks: ");
4969                         } else {
4970                                 print = false;
4971                         }
4972                 }
4973                 res |= bnx2x_check_blocks_with_parity0(bp,
4974                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4975                 res |= bnx2x_check_blocks_with_parity1(bp,
4976                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4977                 res |= bnx2x_check_blocks_with_parity2(bp,
4978                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4979                 res |= bnx2x_check_blocks_with_parity3(bp,
4980                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4981                 res |= bnx2x_check_blocks_with_parity4(bp,
4982                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4983
4984                 if (print)
4985                         pr_cont("\n");
4986         }
4987
4988         return res;
4989 }
4990
4991 /**
4992  * bnx2x_chk_parity_attn - checks for parity attentions.
4993  *
4994  * @bp:         driver handle
4995  * @global:     true if there was a global attention
4996  * @print:      show parity attention in syslog
4997  */
4998 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4999 {
5000         struct attn_route attn = { {0} };
5001         int port = BP_PORT(bp);
5002
5003         attn.sig[0] = REG_RD(bp,
5004                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5005                              port*4);
5006         attn.sig[1] = REG_RD(bp,
5007                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5008                              port*4);
5009         attn.sig[2] = REG_RD(bp,
5010                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5011                              port*4);
5012         attn.sig[3] = REG_RD(bp,
5013                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5014                              port*4);
5015         /* Since MCP attentions can't be disabled inside the block, we need to
5016          * read AEU registers to see whether they're currently disabled
5017          */
5018         attn.sig[3] &= ((REG_RD(bp,
5019                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5020                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5021                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5022                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5023
5024         if (!CHIP_IS_E1x(bp))
5025                 attn.sig[4] = REG_RD(bp,
5026                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5027                                      port*4);
5028
5029         return bnx2x_parity_attn(bp, global, print, attn.sig);
5030 }
5031
5032 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5033 {
5034         u32 val;
5035         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5036
5037                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5038                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5039                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5040                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5041                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5042                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5043                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5044                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5045                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5046                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5047                 if (val &
5048                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5049                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5050                 if (val &
5051                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5052                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5053                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5054                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5055                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5056                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5057                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5058                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5059         }
5060         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5061                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5062                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5063                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5064                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5065                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5066                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5067                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5068                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5069                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5070                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5071                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5072                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5073                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5074                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5075         }
5076
5077         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5078                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5079                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5080                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5081                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5082         }
5083 }
5084
5085 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5086 {
5087         struct attn_route attn, *group_mask;
5088         int port = BP_PORT(bp);
5089         int index;
5090         u32 reg_addr;
5091         u32 val;
5092         u32 aeu_mask;
5093         bool global = false;
5094
5095         /* need to take HW lock because MCP or other port might also
5096            try to handle this event */
5097         bnx2x_acquire_alr(bp);
5098
5099         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5100 #ifndef BNX2X_STOP_ON_ERROR
5101                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5102                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5103                 /* Disable HW interrupts */
5104                 bnx2x_int_disable(bp);
5105                 /* In case of parity errors don't handle attentions so that
5106                  * other function would "see" parity errors.
5107                  */
5108 #else
5109                 bnx2x_panic();
5110 #endif
5111                 bnx2x_release_alr(bp);
5112                 return;
5113         }
5114
5115         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5116         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5117         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5118         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5119         if (!CHIP_IS_E1x(bp))
5120                 attn.sig[4] =
5121                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5122         else
5123                 attn.sig[4] = 0;
5124
5125         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5126            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5127
5128         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5129                 if (deasserted & (1 << index)) {
5130                         group_mask = &bp->attn_group[index];
5131
5132                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5133                            index,
5134                            group_mask->sig[0], group_mask->sig[1],
5135                            group_mask->sig[2], group_mask->sig[3],
5136                            group_mask->sig[4]);
5137
5138                         bnx2x_attn_int_deasserted4(bp,
5139                                         attn.sig[4] & group_mask->sig[4]);
5140                         bnx2x_attn_int_deasserted3(bp,
5141                                         attn.sig[3] & group_mask->sig[3]);
5142                         bnx2x_attn_int_deasserted1(bp,
5143                                         attn.sig[1] & group_mask->sig[1]);
5144                         bnx2x_attn_int_deasserted2(bp,
5145                                         attn.sig[2] & group_mask->sig[2]);
5146                         bnx2x_attn_int_deasserted0(bp,
5147                                         attn.sig[0] & group_mask->sig[0]);
5148                 }
5149         }
5150
5151         bnx2x_release_alr(bp);
5152
5153         if (bp->common.int_block == INT_BLOCK_HC)
5154                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5155                             COMMAND_REG_ATTN_BITS_CLR);
5156         else
5157                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5158
5159         val = ~deasserted;
5160         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5161            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5162         REG_WR(bp, reg_addr, val);
5163
5164         if (~bp->attn_state & deasserted)
5165                 BNX2X_ERR("IGU ERROR\n");
5166
5167         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5168                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5169
5170         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5171         aeu_mask = REG_RD(bp, reg_addr);
5172
5173         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5174            aeu_mask, deasserted);
5175         aeu_mask |= (deasserted & 0x3ff);
5176         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5177
5178         REG_WR(bp, reg_addr, aeu_mask);
5179         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5180
5181         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5182         bp->attn_state &= ~deasserted;
5183         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5184 }
5185
5186 static void bnx2x_attn_int(struct bnx2x *bp)
5187 {
5188         /* read local copy of bits */
5189         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5190                                                                 attn_bits);
5191         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5192                                                                 attn_bits_ack);
5193         u32 attn_state = bp->attn_state;
5194
5195         /* look for changed bits */
5196         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5197         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5198
5199         DP(NETIF_MSG_HW,
5200            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5201            attn_bits, attn_ack, asserted, deasserted);
5202
5203         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5204                 BNX2X_ERR("BAD attention state\n");
5205
5206         /* handle bits that were raised */
5207         if (asserted)
5208                 bnx2x_attn_int_asserted(bp, asserted);
5209
5210         if (deasserted)
5211                 bnx2x_attn_int_deasserted(bp, deasserted);
5212 }
5213
5214 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5215                       u16 index, u8 op, u8 update)
5216 {
5217         u32 igu_addr = bp->igu_base_addr;
5218         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5219         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5220                              igu_addr);
5221 }
5222
5223 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5224 {
5225         /* No memory barriers */
5226         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5227         mmiowb(); /* keep prod updates ordered */
5228 }
5229
5230 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5231                                       union event_ring_elem *elem)
5232 {
5233         u8 err = elem->message.error;
5234
5235         if (!bp->cnic_eth_dev.starting_cid  ||
5236             (cid < bp->cnic_eth_dev.starting_cid &&
5237             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5238                 return 1;
5239
5240         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5241
5242         if (unlikely(err)) {
5243
5244                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5245                           cid);
5246                 bnx2x_panic_dump(bp, false);
5247         }
5248         bnx2x_cnic_cfc_comp(bp, cid, err);
5249         return 0;
5250 }
5251
5252 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5253 {
5254         struct bnx2x_mcast_ramrod_params rparam;
5255         int rc;
5256
5257         memset(&rparam, 0, sizeof(rparam));
5258
5259         rparam.mcast_obj = &bp->mcast_obj;
5260
5261         netif_addr_lock_bh(bp->dev);
5262
5263         /* Clear pending state for the last command */
5264         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5265
5266         /* If there are pending mcast commands - send them */
5267         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5268                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5269                 if (rc < 0)
5270                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5271                                   rc);
5272         }
5273
5274         netif_addr_unlock_bh(bp->dev);
5275 }
5276
5277 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5278                                             union event_ring_elem *elem)
5279 {
5280         unsigned long ramrod_flags = 0;
5281         int rc = 0;
5282         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5283         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5284
5285         /* Always push next commands out, don't wait here */
5286         __set_bit(RAMROD_CONT, &ramrod_flags);
5287
5288         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5289                             >> BNX2X_SWCID_SHIFT) {
5290         case BNX2X_FILTER_MAC_PENDING:
5291                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5292                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5293                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5294                 else
5295                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5296
5297                 break;
5298         case BNX2X_FILTER_VLAN_PENDING:
5299                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5300                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5301                 break;
5302         case BNX2X_FILTER_MCAST_PENDING:
5303                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5304                 /* This is only relevant for 57710 where multicast MACs are
5305                  * configured as unicast MACs using the same ramrod.
5306                  */
5307                 bnx2x_handle_mcast_eqe(bp);
5308                 return;
5309         default:
5310                 BNX2X_ERR("Unsupported classification command: %d\n",
5311                           elem->message.data.eth_event.echo);
5312                 return;
5313         }
5314
5315         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5316
5317         if (rc < 0)
5318                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5319         else if (rc > 0)
5320                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5321 }
5322
5323 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5324
5325 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5326 {
5327         netif_addr_lock_bh(bp->dev);
5328
5329         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5330
5331         /* Send rx_mode command again if was requested */
5332         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5333                 bnx2x_set_storm_rx_mode(bp);
5334         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5335                                     &bp->sp_state))
5336                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5337         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5338                                     &bp->sp_state))
5339                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5340
5341         netif_addr_unlock_bh(bp->dev);
5342 }
5343
5344 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5345                                               union event_ring_elem *elem)
5346 {
5347         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5348                 DP(BNX2X_MSG_SP,
5349                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5350                    elem->message.data.vif_list_event.func_bit_map);
5351                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5352                         elem->message.data.vif_list_event.func_bit_map);
5353         } else if (elem->message.data.vif_list_event.echo ==
5354                    VIF_LIST_RULE_SET) {
5355                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5356                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5357         }
5358 }
5359
5360 /* called with rtnl_lock */
5361 static void bnx2x_after_function_update(struct bnx2x *bp)
5362 {
5363         int q, rc;
5364         struct bnx2x_fastpath *fp;
5365         struct bnx2x_queue_state_params queue_params = {NULL};
5366         struct bnx2x_queue_update_params *q_update_params =
5367                 &queue_params.params.update;
5368
5369         /* Send Q update command with afex vlan removal values for all Qs */
5370         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5371
5372         /* set silent vlan removal values according to vlan mode */
5373         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5374                   &q_update_params->update_flags);
5375         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5376                   &q_update_params->update_flags);
5377         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5378
5379         /* in access mode mark mask and value are 0 to strip all vlans */
5380         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5381                 q_update_params->silent_removal_value = 0;
5382                 q_update_params->silent_removal_mask = 0;
5383         } else {
5384                 q_update_params->silent_removal_value =
5385                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5386                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5387         }
5388
5389         for_each_eth_queue(bp, q) {
5390                 /* Set the appropriate Queue object */
5391                 fp = &bp->fp[q];
5392                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5393
5394                 /* send the ramrod */
5395                 rc = bnx2x_queue_state_change(bp, &queue_params);
5396                 if (rc < 0)
5397                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5398                                   q);
5399         }
5400
5401         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5402                 fp = &bp->fp[FCOE_IDX(bp)];
5403                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5404
5405                 /* clear pending completion bit */
5406                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5407
5408                 /* mark latest Q bit */
5409                 smp_mb__before_atomic();
5410                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5411                 smp_mb__after_atomic();
5412
5413                 /* send Q update ramrod for FCoE Q */
5414                 rc = bnx2x_queue_state_change(bp, &queue_params);
5415                 if (rc < 0)
5416                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5417                                   q);
5418         } else {
5419                 /* If no FCoE ring - ACK MCP now */
5420                 bnx2x_link_report(bp);
5421                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5422         }
5423 }
5424
5425 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5426         struct bnx2x *bp, u32 cid)
5427 {
5428         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5429
5430         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5431                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5432         else
5433                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5434 }
5435
5436 static void bnx2x_eq_int(struct bnx2x *bp)
5437 {
5438         u16 hw_cons, sw_cons, sw_prod;
5439         union event_ring_elem *elem;
5440         u8 echo;
5441         u32 cid;
5442         u8 opcode;
5443         int rc, spqe_cnt = 0;
5444         struct bnx2x_queue_sp_obj *q_obj;
5445         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5446         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5447
5448         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5449
5450         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5451          * when we get the next-page we need to adjust so the loop
5452          * condition below will be met. The next element is the size of a
5453          * regular element and hence incrementing by 1
5454          */
5455         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5456                 hw_cons++;
5457
5458         /* This function may never run in parallel with itself for a
5459          * specific bp, thus there is no need in "paired" read memory
5460          * barrier here.
5461          */
5462         sw_cons = bp->eq_cons;
5463         sw_prod = bp->eq_prod;
5464
5465         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5466                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5467
5468         for (; sw_cons != hw_cons;
5469               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5470
5471                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5472
5473                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5474                 if (!rc) {
5475                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5476                            rc);
5477                         goto next_spqe;
5478                 }
5479
5480                 /* elem CID originates from FW; actually LE */
5481                 cid = SW_CID((__force __le32)
5482                              elem->message.data.cfc_del_event.cid);
5483                 opcode = elem->message.opcode;
5484
5485                 /* handle eq element */
5486                 switch (opcode) {
5487                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5488                         bnx2x_vf_mbx_schedule(bp,
5489                                               &elem->message.data.vf_pf_event);
5490                         continue;
5491
5492                 case EVENT_RING_OPCODE_STAT_QUERY:
5493                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5494                                "got statistics comp event %d\n",
5495                                bp->stats_comp++);
5496                         /* nothing to do with stats comp */
5497                         goto next_spqe;
5498
5499                 case EVENT_RING_OPCODE_CFC_DEL:
5500                         /* handle according to cid range */
5501                         /*
5502                          * we may want to verify here that the bp state is
5503                          * HALTING
5504                          */
5505                         DP(BNX2X_MSG_SP,
5506                            "got delete ramrod for MULTI[%d]\n", cid);
5507
5508                         if (CNIC_LOADED(bp) &&
5509                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5510                                 goto next_spqe;
5511
5512                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5513
5514                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5515                                 break;
5516
5517                         goto next_spqe;
5518
5519                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5520                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5521                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5522                         if (f_obj->complete_cmd(bp, f_obj,
5523                                                 BNX2X_F_CMD_TX_STOP))
5524                                 break;
5525                         goto next_spqe;
5526
5527                 case EVENT_RING_OPCODE_START_TRAFFIC:
5528                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5529                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5530                         if (f_obj->complete_cmd(bp, f_obj,
5531                                                 BNX2X_F_CMD_TX_START))
5532                                 break;
5533                         goto next_spqe;
5534
5535                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5536                         echo = elem->message.data.function_update_event.echo;
5537                         if (echo == SWITCH_UPDATE) {
5538                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5539                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5540                                 if (f_obj->complete_cmd(
5541                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5542                                         break;
5543
5544                         } else {
5545                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5546
5547                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5548                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5549                                 f_obj->complete_cmd(bp, f_obj,
5550                                                     BNX2X_F_CMD_AFEX_UPDATE);
5551
5552                                 /* We will perform the Queues update from
5553                                  * sp_rtnl task as all Queue SP operations
5554                                  * should run under rtnl_lock.
5555                                  */
5556                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5557                         }
5558
5559                         goto next_spqe;
5560
5561                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5562                         f_obj->complete_cmd(bp, f_obj,
5563                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5564                         bnx2x_after_afex_vif_lists(bp, elem);
5565                         goto next_spqe;
5566                 case EVENT_RING_OPCODE_FUNCTION_START:
5567                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5568                            "got FUNC_START ramrod\n");
5569                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5570                                 break;
5571
5572                         goto next_spqe;
5573
5574                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5575                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5576                            "got FUNC_STOP ramrod\n");
5577                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5578                                 break;
5579
5580                         goto next_spqe;
5581
5582                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5583                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5584                            "got set_timesync ramrod completion\n");
5585                         if (f_obj->complete_cmd(bp, f_obj,
5586                                                 BNX2X_F_CMD_SET_TIMESYNC))
5587                                 break;
5588                         goto next_spqe;
5589                 }
5590
5591                 switch (opcode | bp->state) {
5592                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5593                       BNX2X_STATE_OPEN):
5594                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5595                       BNX2X_STATE_OPENING_WAIT4_PORT):
5596                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5597                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5598                         cid = elem->message.data.eth_event.echo &
5599                                 BNX2X_SWCID_MASK;
5600                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5601                            cid);
5602                         rss_raw->clear_pending(rss_raw);
5603                         break;
5604
5605                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5606                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5607                 case (EVENT_RING_OPCODE_SET_MAC |
5608                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5609                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5610                       BNX2X_STATE_OPEN):
5611                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5612                       BNX2X_STATE_DIAG):
5613                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5614                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5615                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5616                         bnx2x_handle_classification_eqe(bp, elem);
5617                         break;
5618
5619                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5620                       BNX2X_STATE_OPEN):
5621                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5622                       BNX2X_STATE_DIAG):
5623                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5624                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5625                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5626                         bnx2x_handle_mcast_eqe(bp);
5627                         break;
5628
5629                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5630                       BNX2X_STATE_OPEN):
5631                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5632                       BNX2X_STATE_DIAG):
5633                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5634                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5635                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5636                         bnx2x_handle_rx_mode_eqe(bp);
5637                         break;
5638                 default:
5639                         /* unknown event log error and continue */
5640                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5641                                   elem->message.opcode, bp->state);
5642                 }
5643 next_spqe:
5644                 spqe_cnt++;
5645         } /* for */
5646
5647         smp_mb__before_atomic();
5648         atomic_add(spqe_cnt, &bp->eq_spq_left);
5649
5650         bp->eq_cons = sw_cons;
5651         bp->eq_prod = sw_prod;
5652         /* Make sure that above mem writes were issued towards the memory */
5653         smp_wmb();
5654
5655         /* update producer */
5656         bnx2x_update_eq_prod(bp, bp->eq_prod);
5657 }
5658
5659 static void bnx2x_sp_task(struct work_struct *work)
5660 {
5661         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5662
5663         DP(BNX2X_MSG_SP, "sp task invoked\n");
5664
5665         /* make sure the atomic interrupt_occurred has been written */
5666         smp_rmb();
5667         if (atomic_read(&bp->interrupt_occurred)) {
5668
5669                 /* what work needs to be performed? */
5670                 u16 status = bnx2x_update_dsb_idx(bp);
5671
5672                 DP(BNX2X_MSG_SP, "status %x\n", status);
5673                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5674                 atomic_set(&bp->interrupt_occurred, 0);
5675
5676                 /* HW attentions */
5677                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5678                         bnx2x_attn_int(bp);
5679                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5680                 }
5681
5682                 /* SP events: STAT_QUERY and others */
5683                 if (status & BNX2X_DEF_SB_IDX) {
5684                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5685
5686                 if (FCOE_INIT(bp) &&
5687                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5688                                 /* Prevent local bottom-halves from running as
5689                                  * we are going to change the local NAPI list.
5690                                  */
5691                                 local_bh_disable();
5692                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5693                                 local_bh_enable();
5694                         }
5695
5696                         /* Handle EQ completions */
5697                         bnx2x_eq_int(bp);
5698                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5699                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5700
5701                         status &= ~BNX2X_DEF_SB_IDX;
5702                 }
5703
5704                 /* if status is non zero then perhaps something went wrong */
5705                 if (unlikely(status))
5706                         DP(BNX2X_MSG_SP,
5707                            "got an unknown interrupt! (status 0x%x)\n", status);
5708
5709                 /* ack status block only if something was actually handled */
5710                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5711                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5712         }
5713
5714         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5715         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5716                                &bp->sp_state)) {
5717                 bnx2x_link_report(bp);
5718                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5719         }
5720 }
5721
5722 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5723 {
5724         struct net_device *dev = dev_instance;
5725         struct bnx2x *bp = netdev_priv(dev);
5726
5727         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5728                      IGU_INT_DISABLE, 0);
5729
5730 #ifdef BNX2X_STOP_ON_ERROR
5731         if (unlikely(bp->panic))
5732                 return IRQ_HANDLED;
5733 #endif
5734
5735         if (CNIC_LOADED(bp)) {
5736                 struct cnic_ops *c_ops;
5737
5738                 rcu_read_lock();
5739                 c_ops = rcu_dereference(bp->cnic_ops);
5740                 if (c_ops)
5741                         c_ops->cnic_handler(bp->cnic_data, NULL);
5742                 rcu_read_unlock();
5743         }
5744
5745         /* schedule sp task to perform default status block work, ack
5746          * attentions and enable interrupts.
5747          */
5748         bnx2x_schedule_sp_task(bp);
5749
5750         return IRQ_HANDLED;
5751 }
5752
5753 /* end of slow path */
5754
5755 void bnx2x_drv_pulse(struct bnx2x *bp)
5756 {
5757         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5758                  bp->fw_drv_pulse_wr_seq);
5759 }
5760
5761 static void bnx2x_timer(unsigned long data)
5762 {
5763         struct bnx2x *bp = (struct bnx2x *) data;
5764
5765         if (!netif_running(bp->dev))
5766                 return;
5767
5768         if (IS_PF(bp) &&
5769             !BP_NOMCP(bp)) {
5770                 int mb_idx = BP_FW_MB_IDX(bp);
5771                 u16 drv_pulse;
5772                 u16 mcp_pulse;
5773
5774                 ++bp->fw_drv_pulse_wr_seq;
5775                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5776                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5777                 bnx2x_drv_pulse(bp);
5778
5779                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5780                              MCP_PULSE_SEQ_MASK);
5781                 /* The delta between driver pulse and mcp response
5782                  * should not get too big. If the MFW is more than 5 pulses
5783                  * behind, we should worry about it enough to generate an error
5784                  * log.
5785                  */
5786                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5787                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5788                                   drv_pulse, mcp_pulse);
5789         }
5790
5791         if (bp->state == BNX2X_STATE_OPEN)
5792                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5793
5794         /* sample pf vf bulletin board for new posts from pf */
5795         if (IS_VF(bp))
5796                 bnx2x_timer_sriov(bp);
5797
5798         mod_timer(&bp->timer, jiffies + bp->current_interval);
5799 }
5800
5801 /* end of Statistics */
5802
5803 /* nic init */
5804
5805 /*
5806  * nic init service functions
5807  */
5808
5809 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5810 {
5811         u32 i;
5812         if (!(len%4) && !(addr%4))
5813                 for (i = 0; i < len; i += 4)
5814                         REG_WR(bp, addr + i, fill);
5815         else
5816                 for (i = 0; i < len; i++)
5817                         REG_WR8(bp, addr + i, fill);
5818 }
5819
5820 /* helper: writes FP SP data to FW - data_size in dwords */
5821 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5822                                 int fw_sb_id,
5823                                 u32 *sb_data_p,
5824                                 u32 data_size)
5825 {
5826         int index;
5827         for (index = 0; index < data_size; index++)
5828                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5829                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5830                         sizeof(u32)*index,
5831                         *(sb_data_p + index));
5832 }
5833
5834 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5835 {
5836         u32 *sb_data_p;
5837         u32 data_size = 0;
5838         struct hc_status_block_data_e2 sb_data_e2;
5839         struct hc_status_block_data_e1x sb_data_e1x;
5840
5841         /* disable the function first */
5842         if (!CHIP_IS_E1x(bp)) {
5843                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5844                 sb_data_e2.common.state = SB_DISABLED;
5845                 sb_data_e2.common.p_func.vf_valid = false;
5846                 sb_data_p = (u32 *)&sb_data_e2;
5847                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5848         } else {
5849                 memset(&sb_data_e1x, 0,
5850                        sizeof(struct hc_status_block_data_e1x));
5851                 sb_data_e1x.common.state = SB_DISABLED;
5852                 sb_data_e1x.common.p_func.vf_valid = false;
5853                 sb_data_p = (u32 *)&sb_data_e1x;
5854                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5855         }
5856         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5857
5858         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5859                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5860                         CSTORM_STATUS_BLOCK_SIZE);
5861         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5862                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5863                         CSTORM_SYNC_BLOCK_SIZE);
5864 }
5865
5866 /* helper:  writes SP SB data to FW */
5867 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5868                 struct hc_sp_status_block_data *sp_sb_data)
5869 {
5870         int func = BP_FUNC(bp);
5871         int i;
5872         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5873                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5874                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5875                         i*sizeof(u32),
5876                         *((u32 *)sp_sb_data + i));
5877 }
5878
5879 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5880 {
5881         int func = BP_FUNC(bp);
5882         struct hc_sp_status_block_data sp_sb_data;
5883         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5884
5885         sp_sb_data.state = SB_DISABLED;
5886         sp_sb_data.p_func.vf_valid = false;
5887
5888         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5889
5890         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5891                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5892                         CSTORM_SP_STATUS_BLOCK_SIZE);
5893         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5894                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5895                         CSTORM_SP_SYNC_BLOCK_SIZE);
5896 }
5897
5898 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5899                                            int igu_sb_id, int igu_seg_id)
5900 {
5901         hc_sm->igu_sb_id = igu_sb_id;
5902         hc_sm->igu_seg_id = igu_seg_id;
5903         hc_sm->timer_value = 0xFF;
5904         hc_sm->time_to_expire = 0xFFFFFFFF;
5905 }
5906
5907 /* allocates state machine ids. */
5908 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5909 {
5910         /* zero out state machine indices */
5911         /* rx indices */
5912         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5913
5914         /* tx indices */
5915         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5916         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5917         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5918         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5919
5920         /* map indices */
5921         /* rx indices */
5922         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5923                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5924
5925         /* tx indices */
5926         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5927                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5928         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5929                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5930         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5931                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5932         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5933                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5934 }
5935
5936 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5937                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5938 {
5939         int igu_seg_id;
5940
5941         struct hc_status_block_data_e2 sb_data_e2;
5942         struct hc_status_block_data_e1x sb_data_e1x;
5943         struct hc_status_block_sm  *hc_sm_p;
5944         int data_size;
5945         u32 *sb_data_p;
5946
5947         if (CHIP_INT_MODE_IS_BC(bp))
5948                 igu_seg_id = HC_SEG_ACCESS_NORM;
5949         else
5950                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5951
5952         bnx2x_zero_fp_sb(bp, fw_sb_id);
5953
5954         if (!CHIP_IS_E1x(bp)) {
5955                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5956                 sb_data_e2.common.state = SB_ENABLED;
5957                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5958                 sb_data_e2.common.p_func.vf_id = vfid;
5959                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5960                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5961                 sb_data_e2.common.same_igu_sb_1b = true;
5962                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5963                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5964                 hc_sm_p = sb_data_e2.common.state_machine;
5965                 sb_data_p = (u32 *)&sb_data_e2;
5966                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5967                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5968         } else {
5969                 memset(&sb_data_e1x, 0,
5970                        sizeof(struct hc_status_block_data_e1x));
5971                 sb_data_e1x.common.state = SB_ENABLED;
5972                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5973                 sb_data_e1x.common.p_func.vf_id = 0xff;
5974                 sb_data_e1x.common.p_func.vf_valid = false;
5975                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5976                 sb_data_e1x.common.same_igu_sb_1b = true;
5977                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5978                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5979                 hc_sm_p = sb_data_e1x.common.state_machine;
5980                 sb_data_p = (u32 *)&sb_data_e1x;
5981                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5982                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5983         }
5984
5985         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5986                                        igu_sb_id, igu_seg_id);
5987         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5988                                        igu_sb_id, igu_seg_id);
5989
5990         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5991
5992         /* write indices to HW - PCI guarantees endianity of regpairs */
5993         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5994 }
5995
5996 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5997                                      u16 tx_usec, u16 rx_usec)
5998 {
5999         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6000                                     false, rx_usec);
6001         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6002                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6003                                        tx_usec);
6004         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6006                                        tx_usec);
6007         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6008                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6009                                        tx_usec);
6010 }
6011
6012 static void bnx2x_init_def_sb(struct bnx2x *bp)
6013 {
6014         struct host_sp_status_block *def_sb = bp->def_status_blk;
6015         dma_addr_t mapping = bp->def_status_blk_mapping;
6016         int igu_sp_sb_index;
6017         int igu_seg_id;
6018         int port = BP_PORT(bp);
6019         int func = BP_FUNC(bp);
6020         int reg_offset, reg_offset_en5;
6021         u64 section;
6022         int index;
6023         struct hc_sp_status_block_data sp_sb_data;
6024         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6025
6026         if (CHIP_INT_MODE_IS_BC(bp)) {
6027                 igu_sp_sb_index = DEF_SB_IGU_ID;
6028                 igu_seg_id = HC_SEG_ACCESS_DEF;
6029         } else {
6030                 igu_sp_sb_index = bp->igu_dsb_id;
6031                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6032         }
6033
6034         /* ATTN */
6035         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6036                                             atten_status_block);
6037         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6038
6039         bp->attn_state = 0;
6040
6041         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6042                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6043         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6044                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6045         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6046                 int sindex;
6047                 /* take care of sig[0]..sig[4] */
6048                 for (sindex = 0; sindex < 4; sindex++)
6049                         bp->attn_group[index].sig[sindex] =
6050                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6051
6052                 if (!CHIP_IS_E1x(bp))
6053                         /*
6054                          * enable5 is separate from the rest of the registers,
6055                          * and therefore the address skip is 4
6056                          * and not 16 between the different groups
6057                          */
6058                         bp->attn_group[index].sig[4] = REG_RD(bp,
6059                                         reg_offset_en5 + 0x4*index);
6060                 else
6061                         bp->attn_group[index].sig[4] = 0;
6062         }
6063
6064         if (bp->common.int_block == INT_BLOCK_HC) {
6065                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6066                                      HC_REG_ATTN_MSG0_ADDR_L);
6067
6068                 REG_WR(bp, reg_offset, U64_LO(section));
6069                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6070         } else if (!CHIP_IS_E1x(bp)) {
6071                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6072                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6073         }
6074
6075         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6076                                             sp_sb);
6077
6078         bnx2x_zero_sp_sb(bp);
6079
6080         /* PCI guarantees endianity of regpairs */
6081         sp_sb_data.state                = SB_ENABLED;
6082         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6083         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6084         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6085         sp_sb_data.igu_seg_id           = igu_seg_id;
6086         sp_sb_data.p_func.pf_id         = func;
6087         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6088         sp_sb_data.p_func.vf_id         = 0xff;
6089
6090         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6091
6092         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6093 }
6094
6095 void bnx2x_update_coalesce(struct bnx2x *bp)
6096 {
6097         int i;
6098
6099         for_each_eth_queue(bp, i)
6100                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6101                                          bp->tx_ticks, bp->rx_ticks);
6102 }
6103
6104 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6105 {
6106         spin_lock_init(&bp->spq_lock);
6107         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6108
6109         bp->spq_prod_idx = 0;
6110         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6111         bp->spq_prod_bd = bp->spq;
6112         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6113 }
6114
6115 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6116 {
6117         int i;
6118         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6119                 union event_ring_elem *elem =
6120                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6121
6122                 elem->next_page.addr.hi =
6123                         cpu_to_le32(U64_HI(bp->eq_mapping +
6124                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6125                 elem->next_page.addr.lo =
6126                         cpu_to_le32(U64_LO(bp->eq_mapping +
6127                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6128         }
6129         bp->eq_cons = 0;
6130         bp->eq_prod = NUM_EQ_DESC;
6131         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6132         /* we want a warning message before it gets wrought... */
6133         atomic_set(&bp->eq_spq_left,
6134                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6135 }
6136
6137 /* called with netif_addr_lock_bh() */
6138 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6139                                unsigned long rx_mode_flags,
6140                                unsigned long rx_accept_flags,
6141                                unsigned long tx_accept_flags,
6142                                unsigned long ramrod_flags)
6143 {
6144         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6145         int rc;
6146
6147         memset(&ramrod_param, 0, sizeof(ramrod_param));
6148
6149         /* Prepare ramrod parameters */
6150         ramrod_param.cid = 0;
6151         ramrod_param.cl_id = cl_id;
6152         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6153         ramrod_param.func_id = BP_FUNC(bp);
6154
6155         ramrod_param.pstate = &bp->sp_state;
6156         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6157
6158         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6159         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6160
6161         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6162
6163         ramrod_param.ramrod_flags = ramrod_flags;
6164         ramrod_param.rx_mode_flags = rx_mode_flags;
6165
6166         ramrod_param.rx_accept_flags = rx_accept_flags;
6167         ramrod_param.tx_accept_flags = tx_accept_flags;
6168
6169         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6170         if (rc < 0) {
6171                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6172                 return rc;
6173         }
6174
6175         return 0;
6176 }
6177
6178 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6179                                    unsigned long *rx_accept_flags,
6180                                    unsigned long *tx_accept_flags)
6181 {
6182         /* Clear the flags first */
6183         *rx_accept_flags = 0;
6184         *tx_accept_flags = 0;
6185
6186         switch (rx_mode) {
6187         case BNX2X_RX_MODE_NONE:
6188                 /*
6189                  * 'drop all' supersedes any accept flags that may have been
6190                  * passed to the function.
6191                  */
6192                 break;
6193         case BNX2X_RX_MODE_NORMAL:
6194                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6195                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6196                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6197
6198                 /* internal switching mode */
6199                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6200                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6201                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6202
6203                 if (bp->accept_any_vlan) {
6204                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6205                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6206                 }
6207
6208                 break;
6209         case BNX2X_RX_MODE_ALLMULTI:
6210                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6211                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6212                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6213
6214                 /* internal switching mode */
6215                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6216                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6217                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6218
6219                 if (bp->accept_any_vlan) {
6220                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6221                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6222                 }
6223
6224                 break;
6225         case BNX2X_RX_MODE_PROMISC:
6226                 /* According to definition of SI mode, iface in promisc mode
6227                  * should receive matched and unmatched (in resolution of port)
6228                  * unicast packets.
6229                  */
6230                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6231                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6232                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6233                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6234
6235                 /* internal switching mode */
6236                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6237                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6238
6239                 if (IS_MF_SI(bp))
6240                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6241                 else
6242                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6243
6244                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6245                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6246
6247                 break;
6248         default:
6249                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6250                 return -EINVAL;
6251         }
6252
6253         return 0;
6254 }
6255
6256 /* called with netif_addr_lock_bh() */
6257 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6258 {
6259         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6260         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6261         int rc;
6262
6263         if (!NO_FCOE(bp))
6264                 /* Configure rx_mode of FCoE Queue */
6265                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6266
6267         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6268                                      &tx_accept_flags);
6269         if (rc)
6270                 return rc;
6271
6272         __set_bit(RAMROD_RX, &ramrod_flags);
6273         __set_bit(RAMROD_TX, &ramrod_flags);
6274
6275         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6276                                    rx_accept_flags, tx_accept_flags,
6277                                    ramrod_flags);
6278 }
6279
6280 static void bnx2x_init_internal_common(struct bnx2x *bp)
6281 {
6282         int i;
6283
6284         /* Zero this manually as its initialization is
6285            currently missing in the initTool */
6286         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6287                 REG_WR(bp, BAR_USTRORM_INTMEM +
6288                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6289         if (!CHIP_IS_E1x(bp)) {
6290                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6291                         CHIP_INT_MODE_IS_BC(bp) ?
6292                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6293         }
6294 }
6295
6296 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6297 {
6298         switch (load_code) {
6299         case FW_MSG_CODE_DRV_LOAD_COMMON:
6300         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6301                 bnx2x_init_internal_common(bp);
6302                 /* no break */
6303
6304         case FW_MSG_CODE_DRV_LOAD_PORT:
6305                 /* nothing to do */
6306                 /* no break */
6307
6308         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6309                 /* internal memory per function is
6310                    initialized inside bnx2x_pf_init */
6311                 break;
6312
6313         default:
6314                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6315                 break;
6316         }
6317 }
6318
6319 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6320 {
6321         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6322 }
6323
6324 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6325 {
6326         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6327 }
6328
6329 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6330 {
6331         if (CHIP_IS_E1x(fp->bp))
6332                 return BP_L_ID(fp->bp) + fp->index;
6333         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6334                 return bnx2x_fp_igu_sb_id(fp);
6335 }
6336
6337 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6338 {
6339         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6340         u8 cos;
6341         unsigned long q_type = 0;
6342         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6343         fp->rx_queue = fp_idx;
6344         fp->cid = fp_idx;
6345         fp->cl_id = bnx2x_fp_cl_id(fp);
6346         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6347         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6348         /* qZone id equals to FW (per path) client id */
6349         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6350
6351         /* init shortcut */
6352         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6353
6354         /* Setup SB indices */
6355         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6356
6357         /* Configure Queue State object */
6358         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6359         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6360
6361         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6362
6363         /* init tx data */
6364         for_each_cos_in_tx_queue(fp, cos) {
6365                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6366                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6367                                   FP_COS_TO_TXQ(fp, cos, bp),
6368                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6369                 cids[cos] = fp->txdata_ptr[cos]->cid;
6370         }
6371
6372         /* nothing more for vf to do here */
6373         if (IS_VF(bp))
6374                 return;
6375
6376         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6377                       fp->fw_sb_id, fp->igu_sb_id);
6378         bnx2x_update_fpsb_idx(fp);
6379         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6380                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6381                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6382
6383         /**
6384          * Configure classification DBs: Always enable Tx switching
6385          */
6386         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6387
6388         DP(NETIF_MSG_IFUP,
6389            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6390            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6391            fp->igu_sb_id);
6392 }
6393
6394 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6395 {
6396         int i;
6397
6398         for (i = 1; i <= NUM_TX_RINGS; i++) {
6399                 struct eth_tx_next_bd *tx_next_bd =
6400                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6401
6402                 tx_next_bd->addr_hi =
6403                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6404                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6405                 tx_next_bd->addr_lo =
6406                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6407                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6408         }
6409
6410         *txdata->tx_cons_sb = cpu_to_le16(0);
6411
6412         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6413         txdata->tx_db.data.zero_fill1 = 0;
6414         txdata->tx_db.data.prod = 0;
6415
6416         txdata->tx_pkt_prod = 0;
6417         txdata->tx_pkt_cons = 0;
6418         txdata->tx_bd_prod = 0;
6419         txdata->tx_bd_cons = 0;
6420         txdata->tx_pkt = 0;
6421 }
6422
6423 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6424 {
6425         int i;
6426
6427         for_each_tx_queue_cnic(bp, i)
6428                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6429 }
6430
6431 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6432 {
6433         int i;
6434         u8 cos;
6435
6436         for_each_eth_queue(bp, i)
6437                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6438                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6439 }
6440
6441 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6442 {
6443         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6444         unsigned long q_type = 0;
6445
6446         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6447         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6448                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6449         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6450         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6451         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6452         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6453         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6454                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6455                           fp);
6456
6457         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6458
6459         /* qZone id equals to FW (per path) client id */
6460         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6461         /* init shortcut */
6462         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6463                 bnx2x_rx_ustorm_prods_offset(fp);
6464
6465         /* Configure Queue State object */
6466         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6467         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6468
6469         /* No multi-CoS for FCoE L2 client */
6470         BUG_ON(fp->max_cos != 1);
6471
6472         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6473                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6474                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6475
6476         DP(NETIF_MSG_IFUP,
6477            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6478            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6479            fp->igu_sb_id);
6480 }
6481
6482 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6483 {
6484         if (!NO_FCOE(bp))
6485                 bnx2x_init_fcoe_fp(bp);
6486
6487         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6488                       BNX2X_VF_ID_INVALID, false,
6489                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6490
6491         /* ensure status block indices were read */
6492         rmb();
6493         bnx2x_init_rx_rings_cnic(bp);
6494         bnx2x_init_tx_rings_cnic(bp);
6495
6496         /* flush all */
6497         mb();
6498         mmiowb();
6499 }
6500
6501 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6502 {
6503         int i;
6504
6505         /* Setup NIC internals and enable interrupts */
6506         for_each_eth_queue(bp, i)
6507                 bnx2x_init_eth_fp(bp, i);
6508
6509         /* ensure status block indices were read */
6510         rmb();
6511         bnx2x_init_rx_rings(bp);
6512         bnx2x_init_tx_rings(bp);
6513
6514         if (IS_PF(bp)) {
6515                 /* Initialize MOD_ABS interrupts */
6516                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6517                                        bp->common.shmem_base,
6518                                        bp->common.shmem2_base, BP_PORT(bp));
6519
6520                 /* initialize the default status block and sp ring */
6521                 bnx2x_init_def_sb(bp);
6522                 bnx2x_update_dsb_idx(bp);
6523                 bnx2x_init_sp_ring(bp);
6524         } else {
6525                 bnx2x_memset_stats(bp);
6526         }
6527 }
6528
6529 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6530 {
6531         bnx2x_init_eq_ring(bp);
6532         bnx2x_init_internal(bp, load_code);
6533         bnx2x_pf_init(bp);
6534         bnx2x_stats_init(bp);
6535
6536         /* flush all before enabling interrupts */
6537         mb();
6538         mmiowb();
6539
6540         bnx2x_int_enable(bp);
6541
6542         /* Check for SPIO5 */
6543         bnx2x_attn_int_deasserted0(bp,
6544                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6545                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6546 }
6547
6548 /* gzip service functions */
6549 static int bnx2x_gunzip_init(struct bnx2x *bp)
6550 {
6551         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6552                                             &bp->gunzip_mapping, GFP_KERNEL);
6553         if (bp->gunzip_buf  == NULL)
6554                 goto gunzip_nomem1;
6555
6556         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6557         if (bp->strm  == NULL)
6558                 goto gunzip_nomem2;
6559
6560         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6561         if (bp->strm->workspace == NULL)
6562                 goto gunzip_nomem3;
6563
6564         return 0;
6565
6566 gunzip_nomem3:
6567         kfree(bp->strm);
6568         bp->strm = NULL;
6569
6570 gunzip_nomem2:
6571         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6572                           bp->gunzip_mapping);
6573         bp->gunzip_buf = NULL;
6574
6575 gunzip_nomem1:
6576         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6577         return -ENOMEM;
6578 }
6579
6580 static void bnx2x_gunzip_end(struct bnx2x *bp)
6581 {
6582         if (bp->strm) {
6583                 vfree(bp->strm->workspace);
6584                 kfree(bp->strm);
6585                 bp->strm = NULL;
6586         }
6587
6588         if (bp->gunzip_buf) {
6589                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6590                                   bp->gunzip_mapping);
6591                 bp->gunzip_buf = NULL;
6592         }
6593 }
6594
6595 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6596 {
6597         int n, rc;
6598
6599         /* check gzip header */
6600         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6601                 BNX2X_ERR("Bad gzip header\n");
6602                 return -EINVAL;
6603         }
6604
6605         n = 10;
6606
6607 #define FNAME                           0x8
6608
6609         if (zbuf[3] & FNAME)
6610                 while ((zbuf[n++] != 0) && (n < len));
6611
6612         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6613         bp->strm->avail_in = len - n;
6614         bp->strm->next_out = bp->gunzip_buf;
6615         bp->strm->avail_out = FW_BUF_SIZE;
6616
6617         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6618         if (rc != Z_OK)
6619                 return rc;
6620
6621         rc = zlib_inflate(bp->strm, Z_FINISH);
6622         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6623                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6624                            bp->strm->msg);
6625
6626         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6627         if (bp->gunzip_outlen & 0x3)
6628                 netdev_err(bp->dev,
6629                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6630                                 bp->gunzip_outlen);
6631         bp->gunzip_outlen >>= 2;
6632
6633         zlib_inflateEnd(bp->strm);
6634
6635         if (rc == Z_STREAM_END)
6636                 return 0;
6637
6638         return rc;
6639 }
6640
6641 /* nic load/unload */
6642
6643 /*
6644  * General service functions
6645  */
6646
6647 /* send a NIG loopback debug packet */
6648 static void bnx2x_lb_pckt(struct bnx2x *bp)
6649 {
6650         u32 wb_write[3];
6651
6652         /* Ethernet source and destination addresses */
6653         wb_write[0] = 0x55555555;
6654         wb_write[1] = 0x55555555;
6655         wb_write[2] = 0x20;             /* SOP */
6656         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6657
6658         /* NON-IP protocol */
6659         wb_write[0] = 0x09000000;
6660         wb_write[1] = 0x55555555;
6661         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6662         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6663 }
6664
6665 /* some of the internal memories
6666  * are not directly readable from the driver
6667  * to test them we send debug packets
6668  */
6669 static int bnx2x_int_mem_test(struct bnx2x *bp)
6670 {
6671         int factor;
6672         int count, i;
6673         u32 val = 0;
6674
6675         if (CHIP_REV_IS_FPGA(bp))
6676                 factor = 120;
6677         else if (CHIP_REV_IS_EMUL(bp))
6678                 factor = 200;
6679         else
6680                 factor = 1;
6681
6682         /* Disable inputs of parser neighbor blocks */
6683         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6684         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6685         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6686         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6687
6688         /*  Write 0 to parser credits for CFC search request */
6689         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6690
6691         /* send Ethernet packet */
6692         bnx2x_lb_pckt(bp);
6693
6694         /* TODO do i reset NIG statistic? */
6695         /* Wait until NIG register shows 1 packet of size 0x10 */
6696         count = 1000 * factor;
6697         while (count) {
6698
6699                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6700                 val = *bnx2x_sp(bp, wb_data[0]);
6701                 if (val == 0x10)
6702                         break;
6703
6704                 usleep_range(10000, 20000);
6705                 count--;
6706         }
6707         if (val != 0x10) {
6708                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6709                 return -1;
6710         }
6711
6712         /* Wait until PRS register shows 1 packet */
6713         count = 1000 * factor;
6714         while (count) {
6715                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6716                 if (val == 1)
6717                         break;
6718
6719                 usleep_range(10000, 20000);
6720                 count--;
6721         }
6722         if (val != 0x1) {
6723                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6724                 return -2;
6725         }
6726
6727         /* Reset and init BRB, PRS */
6728         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6729         msleep(50);
6730         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6731         msleep(50);
6732         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6733         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6734
6735         DP(NETIF_MSG_HW, "part2\n");
6736
6737         /* Disable inputs of parser neighbor blocks */
6738         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6739         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6740         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6741         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6742
6743         /* Write 0 to parser credits for CFC search request */
6744         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6745
6746         /* send 10 Ethernet packets */
6747         for (i = 0; i < 10; i++)
6748                 bnx2x_lb_pckt(bp);
6749
6750         /* Wait until NIG register shows 10 + 1
6751            packets of size 11*0x10 = 0xb0 */
6752         count = 1000 * factor;
6753         while (count) {
6754
6755                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6756                 val = *bnx2x_sp(bp, wb_data[0]);
6757                 if (val == 0xb0)
6758                         break;
6759
6760                 usleep_range(10000, 20000);
6761                 count--;
6762         }
6763         if (val != 0xb0) {
6764                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6765                 return -3;
6766         }
6767
6768         /* Wait until PRS register shows 2 packets */
6769         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6770         if (val != 2)
6771                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6772
6773         /* Write 1 to parser credits for CFC search request */
6774         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6775
6776         /* Wait until PRS register shows 3 packets */
6777         msleep(10 * factor);
6778         /* Wait until NIG register shows 1 packet of size 0x10 */
6779         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6780         if (val != 3)
6781                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6782
6783         /* clear NIG EOP FIFO */
6784         for (i = 0; i < 11; i++)
6785                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6786         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6787         if (val != 1) {
6788                 BNX2X_ERR("clear of NIG failed\n");
6789                 return -4;
6790         }
6791
6792         /* Reset and init BRB, PRS, NIG */
6793         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6794         msleep(50);
6795         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6796         msleep(50);
6797         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6798         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6799         if (!CNIC_SUPPORT(bp))
6800                 /* set NIC mode */
6801                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6802
6803         /* Enable inputs of parser neighbor blocks */
6804         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6805         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6806         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6807         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6808
6809         DP(NETIF_MSG_HW, "done\n");
6810
6811         return 0; /* OK */
6812 }
6813
6814 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6815 {
6816         u32 val;
6817
6818         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6819         if (!CHIP_IS_E1x(bp))
6820                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6821         else
6822                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6823         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6824         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6825         /*
6826          * mask read length error interrupts in brb for parser
6827          * (parsing unit and 'checksum and crc' unit)
6828          * these errors are legal (PU reads fixed length and CAC can cause
6829          * read length error on truncated packets)
6830          */
6831         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6832         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6833         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6834         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6835         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6836         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6837 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6838 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6839         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6840         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6841         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6842 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6843 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6844         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6845         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6846         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6847         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6848 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6849 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6850
6851         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6852                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6853                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6854         if (!CHIP_IS_E1x(bp))
6855                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6856                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6857         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6858
6859         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6860         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6861         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6862 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6863
6864         if (!CHIP_IS_E1x(bp))
6865                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6866                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6867
6868         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6869         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6870 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6871         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6872 }
6873
6874 static void bnx2x_reset_common(struct bnx2x *bp)
6875 {
6876         u32 val = 0x1400;
6877
6878         /* reset_common */
6879         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6880                0xd3ffff7f);
6881
6882         if (CHIP_IS_E3(bp)) {
6883                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6884                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6885         }
6886
6887         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6888 }
6889
6890 static void bnx2x_setup_dmae(struct bnx2x *bp)
6891 {
6892         bp->dmae_ready = 0;
6893         spin_lock_init(&bp->dmae_lock);
6894 }
6895
6896 static void bnx2x_init_pxp(struct bnx2x *bp)
6897 {
6898         u16 devctl;
6899         int r_order, w_order;
6900
6901         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6902         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6903         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6904         if (bp->mrrs == -1)
6905                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6906         else {
6907                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6908                 r_order = bp->mrrs;
6909         }
6910
6911         bnx2x_init_pxp_arb(bp, r_order, w_order);
6912 }
6913
6914 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6915 {
6916         int is_required;
6917         u32 val;
6918         int port;
6919
6920         if (BP_NOMCP(bp))
6921                 return;
6922
6923         is_required = 0;
6924         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6925               SHARED_HW_CFG_FAN_FAILURE_MASK;
6926
6927         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6928                 is_required = 1;
6929
6930         /*
6931          * The fan failure mechanism is usually related to the PHY type since
6932          * the power consumption of the board is affected by the PHY. Currently,
6933          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6934          */
6935         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6936                 for (port = PORT_0; port < PORT_MAX; port++) {
6937                         is_required |=
6938                                 bnx2x_fan_failure_det_req(
6939                                         bp,
6940                                         bp->common.shmem_base,
6941                                         bp->common.shmem2_base,
6942                                         port);
6943                 }
6944
6945         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6946
6947         if (is_required == 0)
6948                 return;
6949
6950         /* Fan failure is indicated by SPIO 5 */
6951         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6952
6953         /* set to active low mode */
6954         val = REG_RD(bp, MISC_REG_SPIO_INT);
6955         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6956         REG_WR(bp, MISC_REG_SPIO_INT, val);
6957
6958         /* enable interrupt to signal the IGU */
6959         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6960         val |= MISC_SPIO_SPIO5;
6961         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6962 }
6963
6964 void bnx2x_pf_disable(struct bnx2x *bp)
6965 {
6966         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6967         val &= ~IGU_PF_CONF_FUNC_EN;
6968
6969         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6970         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6971         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6972 }
6973
6974 static void bnx2x__common_init_phy(struct bnx2x *bp)
6975 {
6976         u32 shmem_base[2], shmem2_base[2];
6977         /* Avoid common init in case MFW supports LFA */
6978         if (SHMEM2_RD(bp, size) >
6979             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6980                 return;
6981         shmem_base[0] =  bp->common.shmem_base;
6982         shmem2_base[0] = bp->common.shmem2_base;
6983         if (!CHIP_IS_E1x(bp)) {
6984                 shmem_base[1] =
6985                         SHMEM2_RD(bp, other_shmem_base_addr);
6986                 shmem2_base[1] =
6987                         SHMEM2_RD(bp, other_shmem2_base_addr);
6988         }
6989         bnx2x_acquire_phy_lock(bp);
6990         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6991                               bp->common.chip_id);
6992         bnx2x_release_phy_lock(bp);
6993 }
6994
6995 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6996 {
6997         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6998         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6999         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7000         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7001         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7002
7003         /* make sure this value is 0 */
7004         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7005
7006         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7007         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7008         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7009         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7010 }
7011
7012 static void bnx2x_set_endianity(struct bnx2x *bp)
7013 {
7014 #ifdef __BIG_ENDIAN
7015         bnx2x_config_endianity(bp, 1);
7016 #else
7017         bnx2x_config_endianity(bp, 0);
7018 #endif
7019 }
7020
7021 static void bnx2x_reset_endianity(struct bnx2x *bp)
7022 {
7023         bnx2x_config_endianity(bp, 0);
7024 }
7025
7026 /**
7027  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7028  *
7029  * @bp:         driver handle
7030  */
7031 static int bnx2x_init_hw_common(struct bnx2x *bp)
7032 {
7033         u32 val;
7034
7035         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7036
7037         /*
7038          * take the RESET lock to protect undi_unload flow from accessing
7039          * registers while we're resetting the chip
7040          */
7041         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7042
7043         bnx2x_reset_common(bp);
7044         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7045
7046         val = 0xfffc;
7047         if (CHIP_IS_E3(bp)) {
7048                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7049                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7050         }
7051         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7052
7053         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7054
7055         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7056
7057         if (!CHIP_IS_E1x(bp)) {
7058                 u8 abs_func_id;
7059
7060                 /**
7061                  * 4-port mode or 2-port mode we need to turn of master-enable
7062                  * for everyone, after that, turn it back on for self.
7063                  * so, we disregard multi-function or not, and always disable
7064                  * for all functions on the given path, this means 0,2,4,6 for
7065                  * path 0 and 1,3,5,7 for path 1
7066                  */
7067                 for (abs_func_id = BP_PATH(bp);
7068                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7069                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7070                                 REG_WR(bp,
7071                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7072                                     1);
7073                                 continue;
7074                         }
7075
7076                         bnx2x_pretend_func(bp, abs_func_id);
7077                         /* clear pf enable */
7078                         bnx2x_pf_disable(bp);
7079                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7080                 }
7081         }
7082
7083         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7084         if (CHIP_IS_E1(bp)) {
7085                 /* enable HW interrupt from PXP on USDM overflow
7086                    bit 16 on INT_MASK_0 */
7087                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7088         }
7089
7090         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7091         bnx2x_init_pxp(bp);
7092         bnx2x_set_endianity(bp);
7093         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7094
7095         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7096                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7097
7098         /* let the HW do it's magic ... */
7099         msleep(100);
7100         /* finish PXP init */
7101         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7102         if (val != 1) {
7103                 BNX2X_ERR("PXP2 CFG failed\n");
7104                 return -EBUSY;
7105         }
7106         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7107         if (val != 1) {
7108                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7109                 return -EBUSY;
7110         }
7111
7112         /* Timers bug workaround E2 only. We need to set the entire ILT to
7113          * have entries with value "0" and valid bit on.
7114          * This needs to be done by the first PF that is loaded in a path
7115          * (i.e. common phase)
7116          */
7117         if (!CHIP_IS_E1x(bp)) {
7118 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7119  * (i.e. vnic3) to start even if it is marked as "scan-off".
7120  * This occurs when a different function (func2,3) is being marked
7121  * as "scan-off". Real-life scenario for example: if a driver is being
7122  * load-unloaded while func6,7 are down. This will cause the timer to access
7123  * the ilt, translate to a logical address and send a request to read/write.
7124  * Since the ilt for the function that is down is not valid, this will cause
7125  * a translation error which is unrecoverable.
7126  * The Workaround is intended to make sure that when this happens nothing fatal
7127  * will occur. The workaround:
7128  *      1.  First PF driver which loads on a path will:
7129  *              a.  After taking the chip out of reset, by using pretend,
7130  *                  it will write "0" to the following registers of
7131  *                  the other vnics.
7132  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7133  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7134  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7135  *                  And for itself it will write '1' to
7136  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7137  *                  dmae-operations (writing to pram for example.)
7138  *                  note: can be done for only function 6,7 but cleaner this
7139  *                        way.
7140  *              b.  Write zero+valid to the entire ILT.
7141  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7142  *                  VNIC3 (of that port). The range allocated will be the
7143  *                  entire ILT. This is needed to prevent  ILT range error.
7144  *      2.  Any PF driver load flow:
7145  *              a.  ILT update with the physical addresses of the allocated
7146  *                  logical pages.
7147  *              b.  Wait 20msec. - note that this timeout is needed to make
7148  *                  sure there are no requests in one of the PXP internal
7149  *                  queues with "old" ILT addresses.
7150  *              c.  PF enable in the PGLC.
7151  *              d.  Clear the was_error of the PF in the PGLC. (could have
7152  *                  occurred while driver was down)
7153  *              e.  PF enable in the CFC (WEAK + STRONG)
7154  *              f.  Timers scan enable
7155  *      3.  PF driver unload flow:
7156  *              a.  Clear the Timers scan_en.
7157  *              b.  Polling for scan_on=0 for that PF.
7158  *              c.  Clear the PF enable bit in the PXP.
7159  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7160  *              e.  Write zero+valid to all ILT entries (The valid bit must
7161  *                  stay set)
7162  *              f.  If this is VNIC 3 of a port then also init
7163  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7164  *                  to the last entry in the ILT.
7165  *
7166  *      Notes:
7167  *      Currently the PF error in the PGLC is non recoverable.
7168  *      In the future the there will be a recovery routine for this error.
7169  *      Currently attention is masked.
7170  *      Having an MCP lock on the load/unload process does not guarantee that
7171  *      there is no Timer disable during Func6/7 enable. This is because the
7172  *      Timers scan is currently being cleared by the MCP on FLR.
7173  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7174  *      there is error before clearing it. But the flow above is simpler and
7175  *      more general.
7176  *      All ILT entries are written by zero+valid and not just PF6/7
7177  *      ILT entries since in the future the ILT entries allocation for
7178  *      PF-s might be dynamic.
7179  */
7180                 struct ilt_client_info ilt_cli;
7181                 struct bnx2x_ilt ilt;
7182                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7183                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7184
7185                 /* initialize dummy TM client */
7186                 ilt_cli.start = 0;
7187                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7188                 ilt_cli.client_num = ILT_CLIENT_TM;
7189
7190                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7191                  * Step 2: set the timers first/last ilt entry to point
7192                  * to the entire range to prevent ILT range error for 3rd/4th
7193                  * vnic (this code assumes existence of the vnic)
7194                  *
7195                  * both steps performed by call to bnx2x_ilt_client_init_op()
7196                  * with dummy TM client
7197                  *
7198                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7199                  * and his brother are split registers
7200                  */
7201                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7202                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7203                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7204
7205                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7206                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7207                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7208         }
7209
7210         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7211         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7212
7213         if (!CHIP_IS_E1x(bp)) {
7214                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7215                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7216                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7217
7218                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7219
7220                 /* let the HW do it's magic ... */
7221                 do {
7222                         msleep(200);
7223                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7224                 } while (factor-- && (val != 1));
7225
7226                 if (val != 1) {
7227                         BNX2X_ERR("ATC_INIT failed\n");
7228                         return -EBUSY;
7229                 }
7230         }
7231
7232         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7233
7234         bnx2x_iov_init_dmae(bp);
7235
7236         /* clean the DMAE memory */
7237         bp->dmae_ready = 1;
7238         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7239
7240         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7241
7242         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7243
7244         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7245
7246         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7247
7248         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7249         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7250         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7251         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7252
7253         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7254
7255         /* QM queues pointers table */
7256         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7257
7258         /* soft reset pulse */
7259         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7260         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7261
7262         if (CNIC_SUPPORT(bp))
7263                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7264
7265         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7266
7267         if (!CHIP_REV_IS_SLOW(bp))
7268                 /* enable hw interrupt from doorbell Q */
7269                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7270
7271         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7272
7273         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7274         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7275
7276         if (!CHIP_IS_E1(bp))
7277                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7278
7279         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7280                 if (IS_MF_AFEX(bp)) {
7281                         /* configure that VNTag and VLAN headers must be
7282                          * received in afex mode
7283                          */
7284                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7285                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7286                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7287                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7288                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7289                 } else {
7290                         /* Bit-map indicating which L2 hdrs may appear
7291                          * after the basic Ethernet header
7292                          */
7293                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7294                                bp->path_has_ovlan ? 7 : 6);
7295                 }
7296         }
7297
7298         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7299         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7300         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7301         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7302
7303         if (!CHIP_IS_E1x(bp)) {
7304                 /* reset VFC memories */
7305                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7306                            VFC_MEMORIES_RST_REG_CAM_RST |
7307                            VFC_MEMORIES_RST_REG_RAM_RST);
7308                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7309                            VFC_MEMORIES_RST_REG_CAM_RST |
7310                            VFC_MEMORIES_RST_REG_RAM_RST);
7311
7312                 msleep(20);
7313         }
7314
7315         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7316         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7317         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7318         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7319
7320         /* sync semi rtc */
7321         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7322                0x80000000);
7323         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7324                0x80000000);
7325
7326         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7327         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7328         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7329
7330         if (!CHIP_IS_E1x(bp)) {
7331                 if (IS_MF_AFEX(bp)) {
7332                         /* configure that VNTag and VLAN headers must be
7333                          * sent in afex mode
7334                          */
7335                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7336                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7337                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7338                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7339                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7340                 } else {
7341                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7342                                bp->path_has_ovlan ? 7 : 6);
7343                 }
7344         }
7345
7346         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7347
7348         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7349
7350         if (CNIC_SUPPORT(bp)) {
7351                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7352                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7353                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7354                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7355                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7356                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7357                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7358                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7359                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7360                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7361         }
7362         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7363
7364         if (sizeof(union cdu_context) != 1024)
7365                 /* we currently assume that a context is 1024 bytes */
7366                 dev_alert(&bp->pdev->dev,
7367                           "please adjust the size of cdu_context(%ld)\n",
7368                           (long)sizeof(union cdu_context));
7369
7370         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7371         val = (4 << 24) + (0 << 12) + 1024;
7372         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7373
7374         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7375         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7376         /* enable context validation interrupt from CFC */
7377         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7378
7379         /* set the thresholds to prevent CFC/CDU race */
7380         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7381
7382         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7383
7384         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7385                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7386
7387         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7388         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7389
7390         /* Reset PCIE errors for debug */
7391         REG_WR(bp, 0x2814, 0xffffffff);
7392         REG_WR(bp, 0x3820, 0xffffffff);
7393
7394         if (!CHIP_IS_E1x(bp)) {
7395                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7396                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7397                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7398                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7399                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7400                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7401                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7402                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7403                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7404                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7405                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7406         }
7407
7408         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7409         if (!CHIP_IS_E1(bp)) {
7410                 /* in E3 this done in per-port section */
7411                 if (!CHIP_IS_E3(bp))
7412                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7413         }
7414         if (CHIP_IS_E1H(bp))
7415                 /* not applicable for E2 (and above ...) */
7416                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7417
7418         if (CHIP_REV_IS_SLOW(bp))
7419                 msleep(200);
7420
7421         /* finish CFC init */
7422         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7423         if (val != 1) {
7424                 BNX2X_ERR("CFC LL_INIT failed\n");
7425                 return -EBUSY;
7426         }
7427         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7428         if (val != 1) {
7429                 BNX2X_ERR("CFC AC_INIT failed\n");
7430                 return -EBUSY;
7431         }
7432         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7433         if (val != 1) {
7434                 BNX2X_ERR("CFC CAM_INIT failed\n");
7435                 return -EBUSY;
7436         }
7437         REG_WR(bp, CFC_REG_DEBUG0, 0);
7438
7439         if (CHIP_IS_E1(bp)) {
7440                 /* read NIG statistic
7441                    to see if this is our first up since powerup */
7442                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7443                 val = *bnx2x_sp(bp, wb_data[0]);
7444
7445                 /* do internal memory self test */
7446                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7447                         BNX2X_ERR("internal mem self test failed\n");
7448                         return -EBUSY;
7449                 }
7450         }
7451
7452         bnx2x_setup_fan_failure_detection(bp);
7453
7454         /* clear PXP2 attentions */
7455         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7456
7457         bnx2x_enable_blocks_attention(bp);
7458         bnx2x_enable_blocks_parity(bp);
7459
7460         if (!BP_NOMCP(bp)) {
7461                 if (CHIP_IS_E1x(bp))
7462                         bnx2x__common_init_phy(bp);
7463         } else
7464                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7465
7466         if (SHMEM2_HAS(bp, netproc_fw_ver))
7467                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7468
7469         return 0;
7470 }
7471
7472 /**
7473  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7474  *
7475  * @bp:         driver handle
7476  */
7477 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7478 {
7479         int rc = bnx2x_init_hw_common(bp);
7480
7481         if (rc)
7482                 return rc;
7483
7484         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7485         if (!BP_NOMCP(bp))
7486                 bnx2x__common_init_phy(bp);
7487
7488         return 0;
7489 }
7490
7491 static int bnx2x_init_hw_port(struct bnx2x *bp)
7492 {
7493         int port = BP_PORT(bp);
7494         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7495         u32 low, high;
7496         u32 val, reg;
7497
7498         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7499
7500         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7501
7502         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7503         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7504         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7505
7506         /* Timers bug workaround: disables the pf_master bit in pglue at
7507          * common phase, we need to enable it here before any dmae access are
7508          * attempted. Therefore we manually added the enable-master to the
7509          * port phase (it also happens in the function phase)
7510          */
7511         if (!CHIP_IS_E1x(bp))
7512                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7513
7514         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7515         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7516         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7517         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7518
7519         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7520         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7522         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7523
7524         /* QM cid (connection) count */
7525         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7526
7527         if (CNIC_SUPPORT(bp)) {
7528                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7529                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7530                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7531         }
7532
7533         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7534
7535         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7536
7537         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7538
7539                 if (IS_MF(bp))
7540                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7541                 else if (bp->dev->mtu > 4096) {
7542                         if (bp->flags & ONE_PORT_FLAG)
7543                                 low = 160;
7544                         else {
7545                                 val = bp->dev->mtu;
7546                                 /* (24*1024 + val*4)/256 */
7547                                 low = 96 + (val/64) +
7548                                                 ((val % 64) ? 1 : 0);
7549                         }
7550                 } else
7551                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7552                 high = low + 56;        /* 14*1024/256 */
7553                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7554                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7555         }
7556
7557         if (CHIP_MODE_IS_4_PORT(bp))
7558                 REG_WR(bp, (BP_PORT(bp) ?
7559                             BRB1_REG_MAC_GUARANTIED_1 :
7560                             BRB1_REG_MAC_GUARANTIED_0), 40);
7561
7562         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7563         if (CHIP_IS_E3B0(bp)) {
7564                 if (IS_MF_AFEX(bp)) {
7565                         /* configure headers for AFEX mode */
7566                         REG_WR(bp, BP_PORT(bp) ?
7567                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7568                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7569                         REG_WR(bp, BP_PORT(bp) ?
7570                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7571                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7572                         REG_WR(bp, BP_PORT(bp) ?
7573                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7574                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7575                 } else {
7576                         /* Ovlan exists only if we are in multi-function +
7577                          * switch-dependent mode, in switch-independent there
7578                          * is no ovlan headers
7579                          */
7580                         REG_WR(bp, BP_PORT(bp) ?
7581                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7582                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7583                                (bp->path_has_ovlan ? 7 : 6));
7584                 }
7585         }
7586
7587         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7588         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7589         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7590         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7591
7592         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7593         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7594         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7595         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7596
7597         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7598         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7599
7600         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7601
7602         if (CHIP_IS_E1x(bp)) {
7603                 /* configure PBF to work without PAUSE mtu 9000 */
7604                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7605
7606                 /* update threshold */
7607                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7608                 /* update init credit */
7609                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7610
7611                 /* probe changes */
7612                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7613                 udelay(50);
7614                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7615         }
7616
7617         if (CNIC_SUPPORT(bp))
7618                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7619
7620         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7621         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7622
7623         if (CHIP_IS_E1(bp)) {
7624                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7625                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7626         }
7627         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7628
7629         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7630
7631         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7632         /* init aeu_mask_attn_func_0/1:
7633          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7634          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7635          *             bits 4-7 are used for "per vn group attention" */
7636         val = IS_MF(bp) ? 0xF7 : 0x7;
7637         /* Enable DCBX attention for all but E1 */
7638         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7639         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7640
7641         /* SCPAD_PARITY should NOT trigger close the gates */
7642         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7643         REG_WR(bp, reg,
7644                REG_RD(bp, reg) &
7645                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7646
7647         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7648         REG_WR(bp, reg,
7649                REG_RD(bp, reg) &
7650                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7651
7652         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7653
7654         if (!CHIP_IS_E1x(bp)) {
7655                 /* Bit-map indicating which L2 hdrs may appear after the
7656                  * basic Ethernet header
7657                  */
7658                 if (IS_MF_AFEX(bp))
7659                         REG_WR(bp, BP_PORT(bp) ?
7660                                NIG_REG_P1_HDRS_AFTER_BASIC :
7661                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7662                 else
7663                         REG_WR(bp, BP_PORT(bp) ?
7664                                NIG_REG_P1_HDRS_AFTER_BASIC :
7665                                NIG_REG_P0_HDRS_AFTER_BASIC,
7666                                IS_MF_SD(bp) ? 7 : 6);
7667
7668                 if (CHIP_IS_E3(bp))
7669                         REG_WR(bp, BP_PORT(bp) ?
7670                                    NIG_REG_LLH1_MF_MODE :
7671                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7672         }
7673         if (!CHIP_IS_E3(bp))
7674                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7675
7676         if (!CHIP_IS_E1(bp)) {
7677                 /* 0x2 disable mf_ov, 0x1 enable */
7678                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7679                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7680
7681                 if (!CHIP_IS_E1x(bp)) {
7682                         val = 0;
7683                         switch (bp->mf_mode) {
7684                         case MULTI_FUNCTION_SD:
7685                                 val = 1;
7686                                 break;
7687                         case MULTI_FUNCTION_SI:
7688                         case MULTI_FUNCTION_AFEX:
7689                                 val = 2;
7690                                 break;
7691                         }
7692
7693                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7694                                                   NIG_REG_LLH0_CLS_TYPE), val);
7695                 }
7696                 {
7697                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7698                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7699                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7700                 }
7701         }
7702
7703         /* If SPIO5 is set to generate interrupts, enable it for this port */
7704         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7705         if (val & MISC_SPIO_SPIO5) {
7706                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7707                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7708                 val = REG_RD(bp, reg_addr);
7709                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7710                 REG_WR(bp, reg_addr, val);
7711         }
7712
7713         return 0;
7714 }
7715
7716 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7717 {
7718         int reg;
7719         u32 wb_write[2];
7720
7721         if (CHIP_IS_E1(bp))
7722                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7723         else
7724                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7725
7726         wb_write[0] = ONCHIP_ADDR1(addr);
7727         wb_write[1] = ONCHIP_ADDR2(addr);
7728         REG_WR_DMAE(bp, reg, wb_write, 2);
7729 }
7730
7731 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7732 {
7733         u32 data, ctl, cnt = 100;
7734         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7735         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7736         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7737         u32 sb_bit =  1 << (idu_sb_id%32);
7738         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7739         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7740
7741         /* Not supported in BC mode */
7742         if (CHIP_INT_MODE_IS_BC(bp))
7743                 return;
7744
7745         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7746                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7747                 IGU_REGULAR_CLEANUP_SET                         |
7748                 IGU_REGULAR_BCLEANUP;
7749
7750         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7751               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7752               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7753
7754         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7755                          data, igu_addr_data);
7756         REG_WR(bp, igu_addr_data, data);
7757         mmiowb();
7758         barrier();
7759         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7760                           ctl, igu_addr_ctl);
7761         REG_WR(bp, igu_addr_ctl, ctl);
7762         mmiowb();
7763         barrier();
7764
7765         /* wait for clean up to finish */
7766         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7767                 msleep(20);
7768
7769         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7770                 DP(NETIF_MSG_HW,
7771                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7772                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7773         }
7774 }
7775
7776 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7777 {
7778         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7779 }
7780
7781 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7782 {
7783         u32 i, base = FUNC_ILT_BASE(func);
7784         for (i = base; i < base + ILT_PER_FUNC; i++)
7785                 bnx2x_ilt_wr(bp, i, 0);
7786 }
7787
7788 static void bnx2x_init_searcher(struct bnx2x *bp)
7789 {
7790         int port = BP_PORT(bp);
7791         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7792         /* T1 hash bits value determines the T1 number of entries */
7793         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7794 }
7795
7796 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7797 {
7798         int rc;
7799         struct bnx2x_func_state_params func_params = {NULL};
7800         struct bnx2x_func_switch_update_params *switch_update_params =
7801                 &func_params.params.switch_update;
7802
7803         /* Prepare parameters for function state transitions */
7804         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7805         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7806
7807         func_params.f_obj = &bp->func_obj;
7808         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7809
7810         /* Function parameters */
7811         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7812                   &switch_update_params->changes);
7813         if (suspend)
7814                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7815                           &switch_update_params->changes);
7816
7817         rc = bnx2x_func_state_change(bp, &func_params);
7818
7819         return rc;
7820 }
7821
7822 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7823 {
7824         int rc, i, port = BP_PORT(bp);
7825         int vlan_en = 0, mac_en[NUM_MACS];
7826
7827         /* Close input from network */
7828         if (bp->mf_mode == SINGLE_FUNCTION) {
7829                 bnx2x_set_rx_filter(&bp->link_params, 0);
7830         } else {
7831                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7832                                    NIG_REG_LLH0_FUNC_EN);
7833                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7834                           NIG_REG_LLH0_FUNC_EN, 0);
7835                 for (i = 0; i < NUM_MACS; i++) {
7836                         mac_en[i] = REG_RD(bp, port ?
7837                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7838                                               4 * i) :
7839                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7840                                               4 * i));
7841                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7842                                               4 * i) :
7843                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7844                 }
7845         }
7846
7847         /* Close BMC to host */
7848         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7849                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7850
7851         /* Suspend Tx switching to the PF. Completion of this ramrod
7852          * further guarantees that all the packets of that PF / child
7853          * VFs in BRB were processed by the Parser, so it is safe to
7854          * change the NIC_MODE register.
7855          */
7856         rc = bnx2x_func_switch_update(bp, 1);
7857         if (rc) {
7858                 BNX2X_ERR("Can't suspend tx-switching!\n");
7859                 return rc;
7860         }
7861
7862         /* Change NIC_MODE register */
7863         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7864
7865         /* Open input from network */
7866         if (bp->mf_mode == SINGLE_FUNCTION) {
7867                 bnx2x_set_rx_filter(&bp->link_params, 1);
7868         } else {
7869                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7870                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7871                 for (i = 0; i < NUM_MACS; i++) {
7872                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7873                                               4 * i) :
7874                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7875                                   mac_en[i]);
7876                 }
7877         }
7878
7879         /* Enable BMC to host */
7880         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7881                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7882
7883         /* Resume Tx switching to the PF */
7884         rc = bnx2x_func_switch_update(bp, 0);
7885         if (rc) {
7886                 BNX2X_ERR("Can't resume tx-switching!\n");
7887                 return rc;
7888         }
7889
7890         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7891         return 0;
7892 }
7893
7894 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7895 {
7896         int rc;
7897
7898         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7899
7900         if (CONFIGURE_NIC_MODE(bp)) {
7901                 /* Configure searcher as part of function hw init */
7902                 bnx2x_init_searcher(bp);
7903
7904                 /* Reset NIC mode */
7905                 rc = bnx2x_reset_nic_mode(bp);
7906                 if (rc)
7907                         BNX2X_ERR("Can't change NIC mode!\n");
7908                 return rc;
7909         }
7910
7911         return 0;
7912 }
7913
7914 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7915  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7916  * the addresses of the transaction, resulting in was-error bit set in the pci
7917  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7918  * to clear the interrupt which detected this from the pglueb and the was done
7919  * bit
7920  */
7921 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7922 {
7923         if (!CHIP_IS_E1x(bp))
7924                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7925                        1 << BP_ABS_FUNC(bp));
7926 }
7927
7928 static int bnx2x_init_hw_func(struct bnx2x *bp)
7929 {
7930         int port = BP_PORT(bp);
7931         int func = BP_FUNC(bp);
7932         int init_phase = PHASE_PF0 + func;
7933         struct bnx2x_ilt *ilt = BP_ILT(bp);
7934         u16 cdu_ilt_start;
7935         u32 addr, val;
7936         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7937         int i, main_mem_width, rc;
7938
7939         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7940
7941         /* FLR cleanup - hmmm */
7942         if (!CHIP_IS_E1x(bp)) {
7943                 rc = bnx2x_pf_flr_clnup(bp);
7944                 if (rc) {
7945                         bnx2x_fw_dump(bp);
7946                         return rc;
7947                 }
7948         }
7949
7950         /* set MSI reconfigure capability */
7951         if (bp->common.int_block == INT_BLOCK_HC) {
7952                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7953                 val = REG_RD(bp, addr);
7954                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7955                 REG_WR(bp, addr, val);
7956         }
7957
7958         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7959         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7960
7961         ilt = BP_ILT(bp);
7962         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7963
7964         if (IS_SRIOV(bp))
7965                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7966         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7967
7968         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7969          * those of the VFs, so start line should be reset
7970          */
7971         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7972         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7973                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7974                 ilt->lines[cdu_ilt_start + i].page_mapping =
7975                         bp->context[i].cxt_mapping;
7976                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7977         }
7978
7979         bnx2x_ilt_init_op(bp, INITOP_SET);
7980
7981         if (!CONFIGURE_NIC_MODE(bp)) {
7982                 bnx2x_init_searcher(bp);
7983                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7984                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7985         } else {
7986                 /* Set NIC mode */
7987                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7988                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7989         }
7990
7991         if (!CHIP_IS_E1x(bp)) {
7992                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7993
7994                 /* Turn on a single ISR mode in IGU if driver is going to use
7995                  * INT#x or MSI
7996                  */
7997                 if (!(bp->flags & USING_MSIX_FLAG))
7998                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7999                 /*
8000                  * Timers workaround bug: function init part.
8001                  * Need to wait 20msec after initializing ILT,
8002                  * needed to make sure there are no requests in
8003                  * one of the PXP internal queues with "old" ILT addresses
8004                  */
8005                 msleep(20);
8006                 /*
8007                  * Master enable - Due to WB DMAE writes performed before this
8008                  * register is re-initialized as part of the regular function
8009                  * init
8010                  */
8011                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8012                 /* Enable the function in IGU */
8013                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8014         }
8015
8016         bp->dmae_ready = 1;
8017
8018         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8019
8020         bnx2x_clean_pglue_errors(bp);
8021
8022         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8023         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8024         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8025         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8026         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8027         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8028         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8029         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8030         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8031         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8032         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8033         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8034         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8035
8036         if (!CHIP_IS_E1x(bp))
8037                 REG_WR(bp, QM_REG_PF_EN, 1);
8038
8039         if (!CHIP_IS_E1x(bp)) {
8040                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8041                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8042                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8043                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044         }
8045         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8046
8047         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8048         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8049         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8050
8051         bnx2x_iov_init_dq(bp);
8052
8053         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8054         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8055         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8056         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8057         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8058         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8059         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8060         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8061         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8062         if (!CHIP_IS_E1x(bp))
8063                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8064
8065         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8066
8067         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8068
8069         if (!CHIP_IS_E1x(bp))
8070                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8071
8072         if (IS_MF(bp)) {
8073                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8074                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8075                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8076                                bp->mf_ov);
8077                 }
8078         }
8079
8080         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8081
8082         /* HC init per function */
8083         if (bp->common.int_block == INT_BLOCK_HC) {
8084                 if (CHIP_IS_E1H(bp)) {
8085                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8086
8087                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8088                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8089                 }
8090                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8091
8092         } else {
8093                 int num_segs, sb_idx, prod_offset;
8094
8095                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8096
8097                 if (!CHIP_IS_E1x(bp)) {
8098                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8099                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8100                 }
8101
8102                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8103
8104                 if (!CHIP_IS_E1x(bp)) {
8105                         int dsb_idx = 0;
8106                         /**
8107                          * Producer memory:
8108                          * E2 mode: address 0-135 match to the mapping memory;
8109                          * 136 - PF0 default prod; 137 - PF1 default prod;
8110                          * 138 - PF2 default prod; 139 - PF3 default prod;
8111                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8112                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8113                          * 144-147 reserved.
8114                          *
8115                          * E1.5 mode - In backward compatible mode;
8116                          * for non default SB; each even line in the memory
8117                          * holds the U producer and each odd line hold
8118                          * the C producer. The first 128 producers are for
8119                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8120                          * producers are for the DSB for each PF.
8121                          * Each PF has five segments: (the order inside each
8122                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8123                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8124                          * 144-147 attn prods;
8125                          */
8126                         /* non-default-status-blocks */
8127                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8128                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8129                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8130                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8131                                         num_segs;
8132
8133                                 for (i = 0; i < num_segs; i++) {
8134                                         addr = IGU_REG_PROD_CONS_MEMORY +
8135                                                         (prod_offset + i) * 4;
8136                                         REG_WR(bp, addr, 0);
8137                                 }
8138                                 /* send consumer update with value 0 */
8139                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8140                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8141                                 bnx2x_igu_clear_sb(bp,
8142                                                    bp->igu_base_sb + sb_idx);
8143                         }
8144
8145                         /* default-status-blocks */
8146                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8147                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8148
8149                         if (CHIP_MODE_IS_4_PORT(bp))
8150                                 dsb_idx = BP_FUNC(bp);
8151                         else
8152                                 dsb_idx = BP_VN(bp);
8153
8154                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8155                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8156                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8157
8158                         /*
8159                          * igu prods come in chunks of E1HVN_MAX (4) -
8160                          * does not matters what is the current chip mode
8161                          */
8162                         for (i = 0; i < (num_segs * E1HVN_MAX);
8163                              i += E1HVN_MAX) {
8164                                 addr = IGU_REG_PROD_CONS_MEMORY +
8165                                                         (prod_offset + i)*4;
8166                                 REG_WR(bp, addr, 0);
8167                         }
8168                         /* send consumer update with 0 */
8169                         if (CHIP_INT_MODE_IS_BC(bp)) {
8170                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8171                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8172                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8173                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8174                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8175                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8176                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8177                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8178                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8179                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8180                         } else {
8181                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8182                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8183                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8184                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8185                         }
8186                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8187
8188                         /* !!! These should become driver const once
8189                            rf-tool supports split-68 const */
8190                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8191                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8192                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8193                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8194                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8195                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8196                 }
8197         }
8198
8199         /* Reset PCIE errors for debug */
8200         REG_WR(bp, 0x2114, 0xffffffff);
8201         REG_WR(bp, 0x2120, 0xffffffff);
8202
8203         if (CHIP_IS_E1x(bp)) {
8204                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8205                 main_mem_base = HC_REG_MAIN_MEMORY +
8206                                 BP_PORT(bp) * (main_mem_size * 4);
8207                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8208                 main_mem_width = 8;
8209
8210                 val = REG_RD(bp, main_mem_prty_clr);
8211                 if (val)
8212                         DP(NETIF_MSG_HW,
8213                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8214                            val);
8215
8216                 /* Clear "false" parity errors in MSI-X table */
8217                 for (i = main_mem_base;
8218                      i < main_mem_base + main_mem_size * 4;
8219                      i += main_mem_width) {
8220                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8221                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8222                                          i, main_mem_width / 4);
8223                 }
8224                 /* Clear HC parity attention */
8225                 REG_RD(bp, main_mem_prty_clr);
8226         }
8227
8228 #ifdef BNX2X_STOP_ON_ERROR
8229         /* Enable STORMs SP logging */
8230         REG_WR8(bp, BAR_USTRORM_INTMEM +
8231                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8232         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8233                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8234         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8235                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8236         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8237                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8238 #endif
8239
8240         bnx2x_phy_probe(&bp->link_params);
8241
8242         return 0;
8243 }
8244
8245 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8246 {
8247         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8248
8249         if (!CHIP_IS_E1x(bp))
8250                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8251                                sizeof(struct host_hc_status_block_e2));
8252         else
8253                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8254                                sizeof(struct host_hc_status_block_e1x));
8255
8256         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8257 }
8258
8259 void bnx2x_free_mem(struct bnx2x *bp)
8260 {
8261         int i;
8262
8263         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8264                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8265
8266         if (IS_VF(bp))
8267                 return;
8268
8269         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8270                        sizeof(struct host_sp_status_block));
8271
8272         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8273                        sizeof(struct bnx2x_slowpath));
8274
8275         for (i = 0; i < L2_ILT_LINES(bp); i++)
8276                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8277                                bp->context[i].size);
8278         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8279
8280         BNX2X_FREE(bp->ilt->lines);
8281
8282         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8283
8284         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8285                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8286
8287         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8288
8289         bnx2x_iov_free_mem(bp);
8290 }
8291
8292 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8293 {
8294         if (!CHIP_IS_E1x(bp)) {
8295                 /* size = the status block + ramrod buffers */
8296                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8297                                                     sizeof(struct host_hc_status_block_e2));
8298                 if (!bp->cnic_sb.e2_sb)
8299                         goto alloc_mem_err;
8300         } else {
8301                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8302                                                      sizeof(struct host_hc_status_block_e1x));
8303                 if (!bp->cnic_sb.e1x_sb)
8304                         goto alloc_mem_err;
8305         }
8306
8307         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8308                 /* allocate searcher T2 table, as it wasn't allocated before */
8309                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8310                 if (!bp->t2)
8311                         goto alloc_mem_err;
8312         }
8313
8314         /* write address to which L5 should insert its values */
8315         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8316                 &bp->slowpath->drv_info_to_mcp;
8317
8318         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8319                 goto alloc_mem_err;
8320
8321         return 0;
8322
8323 alloc_mem_err:
8324         bnx2x_free_mem_cnic(bp);
8325         BNX2X_ERR("Can't allocate memory\n");
8326         return -ENOMEM;
8327 }
8328
8329 int bnx2x_alloc_mem(struct bnx2x *bp)
8330 {
8331         int i, allocated, context_size;
8332
8333         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8334                 /* allocate searcher T2 table */
8335                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8336                 if (!bp->t2)
8337                         goto alloc_mem_err;
8338         }
8339
8340         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8341                                              sizeof(struct host_sp_status_block));
8342         if (!bp->def_status_blk)
8343                 goto alloc_mem_err;
8344
8345         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8346                                        sizeof(struct bnx2x_slowpath));
8347         if (!bp->slowpath)
8348                 goto alloc_mem_err;
8349
8350         /* Allocate memory for CDU context:
8351          * This memory is allocated separately and not in the generic ILT
8352          * functions because CDU differs in few aspects:
8353          * 1. There are multiple entities allocating memory for context -
8354          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8355          * its own ILT lines.
8356          * 2. Since CDU page-size is not a single 4KB page (which is the case
8357          * for the other ILT clients), to be efficient we want to support
8358          * allocation of sub-page-size in the last entry.
8359          * 3. Context pointers are used by the driver to pass to FW / update
8360          * the context (for the other ILT clients the pointers are used just to
8361          * free the memory during unload).
8362          */
8363         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8364
8365         for (i = 0, allocated = 0; allocated < context_size; i++) {
8366                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8367                                           (context_size - allocated));
8368                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8369                                                       bp->context[i].size);
8370                 if (!bp->context[i].vcxt)
8371                         goto alloc_mem_err;
8372                 allocated += bp->context[i].size;
8373         }
8374         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8375                                  GFP_KERNEL);
8376         if (!bp->ilt->lines)
8377                 goto alloc_mem_err;
8378
8379         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8380                 goto alloc_mem_err;
8381
8382         if (bnx2x_iov_alloc_mem(bp))
8383                 goto alloc_mem_err;
8384
8385         /* Slow path ring */
8386         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8387         if (!bp->spq)
8388                 goto alloc_mem_err;
8389
8390         /* EQ */
8391         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8392                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8393         if (!bp->eq_ring)
8394                 goto alloc_mem_err;
8395
8396         return 0;
8397
8398 alloc_mem_err:
8399         bnx2x_free_mem(bp);
8400         BNX2X_ERR("Can't allocate memory\n");
8401         return -ENOMEM;
8402 }
8403
8404 /*
8405  * Init service functions
8406  */
8407
8408 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8409                       struct bnx2x_vlan_mac_obj *obj, bool set,
8410                       int mac_type, unsigned long *ramrod_flags)
8411 {
8412         int rc;
8413         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8414
8415         memset(&ramrod_param, 0, sizeof(ramrod_param));
8416
8417         /* Fill general parameters */
8418         ramrod_param.vlan_mac_obj = obj;
8419         ramrod_param.ramrod_flags = *ramrod_flags;
8420
8421         /* Fill a user request section if needed */
8422         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8423                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8424
8425                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8426
8427                 /* Set the command: ADD or DEL */
8428                 if (set)
8429                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8430                 else
8431                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8432         }
8433
8434         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8435
8436         if (rc == -EEXIST) {
8437                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8438                 /* do not treat adding same MAC as error */
8439                 rc = 0;
8440         } else if (rc < 0)
8441                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8442
8443         return rc;
8444 }
8445
8446 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8447                        struct bnx2x_vlan_mac_obj *obj, bool set,
8448                        unsigned long *ramrod_flags)
8449 {
8450         int rc;
8451         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8452
8453         memset(&ramrod_param, 0, sizeof(ramrod_param));
8454
8455         /* Fill general parameters */
8456         ramrod_param.vlan_mac_obj = obj;
8457         ramrod_param.ramrod_flags = *ramrod_flags;
8458
8459         /* Fill a user request section if needed */
8460         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8461                 ramrod_param.user_req.u.vlan.vlan = vlan;
8462                 /* Set the command: ADD or DEL */
8463                 if (set)
8464                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8465                 else
8466                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8467         }
8468
8469         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8470
8471         if (rc == -EEXIST) {
8472                 /* Do not treat adding same vlan as error. */
8473                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8474                 rc = 0;
8475         } else if (rc < 0) {
8476                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8477         }
8478
8479         return rc;
8480 }
8481
8482 int bnx2x_del_all_macs(struct bnx2x *bp,
8483                        struct bnx2x_vlan_mac_obj *mac_obj,
8484                        int mac_type, bool wait_for_comp)
8485 {
8486         int rc;
8487         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8488
8489         /* Wait for completion of requested */
8490         if (wait_for_comp)
8491                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8492
8493         /* Set the mac type of addresses we want to clear */
8494         __set_bit(mac_type, &vlan_mac_flags);
8495
8496         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8497         if (rc < 0)
8498                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8499
8500         return rc;
8501 }
8502
8503 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8504 {
8505         if (IS_PF(bp)) {
8506                 unsigned long ramrod_flags = 0;
8507
8508                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8509                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8510                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8511                                          &bp->sp_objs->mac_obj, set,
8512                                          BNX2X_ETH_MAC, &ramrod_flags);
8513         } else { /* vf */
8514                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8515                                              bp->fp->index, set);
8516         }
8517 }
8518
8519 int bnx2x_setup_leading(struct bnx2x *bp)
8520 {
8521         if (IS_PF(bp))
8522                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8523         else /* VF */
8524                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8525 }
8526
8527 /**
8528  * bnx2x_set_int_mode - configure interrupt mode
8529  *
8530  * @bp:         driver handle
8531  *
8532  * In case of MSI-X it will also try to enable MSI-X.
8533  */
8534 int bnx2x_set_int_mode(struct bnx2x *bp)
8535 {
8536         int rc = 0;
8537
8538         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8539                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8540                 return -EINVAL;
8541         }
8542
8543         switch (int_mode) {
8544         case BNX2X_INT_MODE_MSIX:
8545                 /* attempt to enable msix */
8546                 rc = bnx2x_enable_msix(bp);
8547
8548                 /* msix attained */
8549                 if (!rc)
8550                         return 0;
8551
8552                 /* vfs use only msix */
8553                 if (rc && IS_VF(bp))
8554                         return rc;
8555
8556                 /* failed to enable multiple MSI-X */
8557                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8558                                bp->num_queues,
8559                                1 + bp->num_cnic_queues);
8560
8561                 /* falling through... */
8562         case BNX2X_INT_MODE_MSI:
8563                 bnx2x_enable_msi(bp);
8564
8565                 /* falling through... */
8566         case BNX2X_INT_MODE_INTX:
8567                 bp->num_ethernet_queues = 1;
8568                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8569                 BNX2X_DEV_INFO("set number of queues to 1\n");
8570                 break;
8571         default:
8572                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8573                 return -EINVAL;
8574         }
8575         return 0;
8576 }
8577
8578 /* must be called prior to any HW initializations */
8579 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8580 {
8581         if (IS_SRIOV(bp))
8582                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8583         return L2_ILT_LINES(bp);
8584 }
8585
8586 void bnx2x_ilt_set_info(struct bnx2x *bp)
8587 {
8588         struct ilt_client_info *ilt_client;
8589         struct bnx2x_ilt *ilt = BP_ILT(bp);
8590         u16 line = 0;
8591
8592         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8593         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8594
8595         /* CDU */
8596         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8597         ilt_client->client_num = ILT_CLIENT_CDU;
8598         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8599         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8600         ilt_client->start = line;
8601         line += bnx2x_cid_ilt_lines(bp);
8602
8603         if (CNIC_SUPPORT(bp))
8604                 line += CNIC_ILT_LINES;
8605         ilt_client->end = line - 1;
8606
8607         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8608            ilt_client->start,
8609            ilt_client->end,
8610            ilt_client->page_size,
8611            ilt_client->flags,
8612            ilog2(ilt_client->page_size >> 12));
8613
8614         /* QM */
8615         if (QM_INIT(bp->qm_cid_count)) {
8616                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8617                 ilt_client->client_num = ILT_CLIENT_QM;
8618                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8619                 ilt_client->flags = 0;
8620                 ilt_client->start = line;
8621
8622                 /* 4 bytes for each cid */
8623                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8624                                                          QM_ILT_PAGE_SZ);
8625
8626                 ilt_client->end = line - 1;
8627
8628                 DP(NETIF_MSG_IFUP,
8629                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8630                    ilt_client->start,
8631                    ilt_client->end,
8632                    ilt_client->page_size,
8633                    ilt_client->flags,
8634                    ilog2(ilt_client->page_size >> 12));
8635         }
8636
8637         if (CNIC_SUPPORT(bp)) {
8638                 /* SRC */
8639                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8640                 ilt_client->client_num = ILT_CLIENT_SRC;
8641                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8642                 ilt_client->flags = 0;
8643                 ilt_client->start = line;
8644                 line += SRC_ILT_LINES;
8645                 ilt_client->end = line - 1;
8646
8647                 DP(NETIF_MSG_IFUP,
8648                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8649                    ilt_client->start,
8650                    ilt_client->end,
8651                    ilt_client->page_size,
8652                    ilt_client->flags,
8653                    ilog2(ilt_client->page_size >> 12));
8654
8655                 /* TM */
8656                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8657                 ilt_client->client_num = ILT_CLIENT_TM;
8658                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8659                 ilt_client->flags = 0;
8660                 ilt_client->start = line;
8661                 line += TM_ILT_LINES;
8662                 ilt_client->end = line - 1;
8663
8664                 DP(NETIF_MSG_IFUP,
8665                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8666                    ilt_client->start,
8667                    ilt_client->end,
8668                    ilt_client->page_size,
8669                    ilt_client->flags,
8670                    ilog2(ilt_client->page_size >> 12));
8671         }
8672
8673         BUG_ON(line > ILT_MAX_LINES);
8674 }
8675
8676 /**
8677  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8678  *
8679  * @bp:                 driver handle
8680  * @fp:                 pointer to fastpath
8681  * @init_params:        pointer to parameters structure
8682  *
8683  * parameters configured:
8684  *      - HC configuration
8685  *      - Queue's CDU context
8686  */
8687 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8688         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8689 {
8690         u8 cos;
8691         int cxt_index, cxt_offset;
8692
8693         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8694         if (!IS_FCOE_FP(fp)) {
8695                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8696                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8697
8698                 /* If HC is supported, enable host coalescing in the transition
8699                  * to INIT state.
8700                  */
8701                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8702                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8703
8704                 /* HC rate */
8705                 init_params->rx.hc_rate = bp->rx_ticks ?
8706                         (1000000 / bp->rx_ticks) : 0;
8707                 init_params->tx.hc_rate = bp->tx_ticks ?
8708                         (1000000 / bp->tx_ticks) : 0;
8709
8710                 /* FW SB ID */
8711                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8712                         fp->fw_sb_id;
8713
8714                 /*
8715                  * CQ index among the SB indices: FCoE clients uses the default
8716                  * SB, therefore it's different.
8717                  */
8718                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8719                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8720         }
8721
8722         /* set maximum number of COSs supported by this queue */
8723         init_params->max_cos = fp->max_cos;
8724
8725         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8726             fp->index, init_params->max_cos);
8727
8728         /* set the context pointers queue object */
8729         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8730                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8731                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8732                                 ILT_PAGE_CIDS);
8733                 init_params->cxts[cos] =
8734                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8735         }
8736 }
8737
8738 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8739                         struct bnx2x_queue_state_params *q_params,
8740                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8741                         int tx_index, bool leading)
8742 {
8743         memset(tx_only_params, 0, sizeof(*tx_only_params));
8744
8745         /* Set the command */
8746         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8747
8748         /* Set tx-only QUEUE flags: don't zero statistics */
8749         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8750
8751         /* choose the index of the cid to send the slow path on */
8752         tx_only_params->cid_index = tx_index;
8753
8754         /* Set general TX_ONLY_SETUP parameters */
8755         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8756
8757         /* Set Tx TX_ONLY_SETUP parameters */
8758         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8759
8760         DP(NETIF_MSG_IFUP,
8761            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8762            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8763            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8764            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8765
8766         /* send the ramrod */
8767         return bnx2x_queue_state_change(bp, q_params);
8768 }
8769
8770 /**
8771  * bnx2x_setup_queue - setup queue
8772  *
8773  * @bp:         driver handle
8774  * @fp:         pointer to fastpath
8775  * @leading:    is leading
8776  *
8777  * This function performs 2 steps in a Queue state machine
8778  *      actually: 1) RESET->INIT 2) INIT->SETUP
8779  */
8780
8781 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8782                        bool leading)
8783 {
8784         struct bnx2x_queue_state_params q_params = {NULL};
8785         struct bnx2x_queue_setup_params *setup_params =
8786                                                 &q_params.params.setup;
8787         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8788                                                 &q_params.params.tx_only;
8789         int rc;
8790         u8 tx_index;
8791
8792         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8793
8794         /* reset IGU state skip FCoE L2 queue */
8795         if (!IS_FCOE_FP(fp))
8796                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8797                              IGU_INT_ENABLE, 0);
8798
8799         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8800         /* We want to wait for completion in this context */
8801         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8802
8803         /* Prepare the INIT parameters */
8804         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8805
8806         /* Set the command */
8807         q_params.cmd = BNX2X_Q_CMD_INIT;
8808
8809         /* Change the state to INIT */
8810         rc = bnx2x_queue_state_change(bp, &q_params);
8811         if (rc) {
8812                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8813                 return rc;
8814         }
8815
8816         DP(NETIF_MSG_IFUP, "init complete\n");
8817
8818         /* Now move the Queue to the SETUP state... */
8819         memset(setup_params, 0, sizeof(*setup_params));
8820
8821         /* Set QUEUE flags */
8822         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8823
8824         /* Set general SETUP parameters */
8825         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8826                                 FIRST_TX_COS_INDEX);
8827
8828         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8829                             &setup_params->rxq_params);
8830
8831         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8832                            FIRST_TX_COS_INDEX);
8833
8834         /* Set the command */
8835         q_params.cmd = BNX2X_Q_CMD_SETUP;
8836
8837         if (IS_FCOE_FP(fp))
8838                 bp->fcoe_init = true;
8839
8840         /* Change the state to SETUP */
8841         rc = bnx2x_queue_state_change(bp, &q_params);
8842         if (rc) {
8843                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8844                 return rc;
8845         }
8846
8847         /* loop through the relevant tx-only indices */
8848         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8849               tx_index < fp->max_cos;
8850               tx_index++) {
8851
8852                 /* prepare and send tx-only ramrod*/
8853                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8854                                           tx_only_params, tx_index, leading);
8855                 if (rc) {
8856                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8857                                   fp->index, tx_index);
8858                         return rc;
8859                 }
8860         }
8861
8862         return rc;
8863 }
8864
8865 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8866 {
8867         struct bnx2x_fastpath *fp = &bp->fp[index];
8868         struct bnx2x_fp_txdata *txdata;
8869         struct bnx2x_queue_state_params q_params = {NULL};
8870         int rc, tx_index;
8871
8872         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8873
8874         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8875         /* We want to wait for completion in this context */
8876         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8877
8878         /* close tx-only connections */
8879         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8880              tx_index < fp->max_cos;
8881              tx_index++){
8882
8883                 /* ascertain this is a normal queue*/
8884                 txdata = fp->txdata_ptr[tx_index];
8885
8886                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8887                                                         txdata->txq_index);
8888
8889                 /* send halt terminate on tx-only connection */
8890                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8891                 memset(&q_params.params.terminate, 0,
8892                        sizeof(q_params.params.terminate));
8893                 q_params.params.terminate.cid_index = tx_index;
8894
8895                 rc = bnx2x_queue_state_change(bp, &q_params);
8896                 if (rc)
8897                         return rc;
8898
8899                 /* send halt terminate on tx-only connection */
8900                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8901                 memset(&q_params.params.cfc_del, 0,
8902                        sizeof(q_params.params.cfc_del));
8903                 q_params.params.cfc_del.cid_index = tx_index;
8904                 rc = bnx2x_queue_state_change(bp, &q_params);
8905                 if (rc)
8906                         return rc;
8907         }
8908         /* Stop the primary connection: */
8909         /* ...halt the connection */
8910         q_params.cmd = BNX2X_Q_CMD_HALT;
8911         rc = bnx2x_queue_state_change(bp, &q_params);
8912         if (rc)
8913                 return rc;
8914
8915         /* ...terminate the connection */
8916         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8917         memset(&q_params.params.terminate, 0,
8918                sizeof(q_params.params.terminate));
8919         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8920         rc = bnx2x_queue_state_change(bp, &q_params);
8921         if (rc)
8922                 return rc;
8923         /* ...delete cfc entry */
8924         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8925         memset(&q_params.params.cfc_del, 0,
8926                sizeof(q_params.params.cfc_del));
8927         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8928         return bnx2x_queue_state_change(bp, &q_params);
8929 }
8930
8931 static void bnx2x_reset_func(struct bnx2x *bp)
8932 {
8933         int port = BP_PORT(bp);
8934         int func = BP_FUNC(bp);
8935         int i;
8936
8937         /* Disable the function in the FW */
8938         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8939         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8940         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8941         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8942
8943         /* FP SBs */
8944         for_each_eth_queue(bp, i) {
8945                 struct bnx2x_fastpath *fp = &bp->fp[i];
8946                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8947                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8948                            SB_DISABLED);
8949         }
8950
8951         if (CNIC_LOADED(bp))
8952                 /* CNIC SB */
8953                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8954                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8955                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8956
8957         /* SP SB */
8958         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8959                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8960                 SB_DISABLED);
8961
8962         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8963                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8964                        0);
8965
8966         /* Configure IGU */
8967         if (bp->common.int_block == INT_BLOCK_HC) {
8968                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8969                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8970         } else {
8971                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8972                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8973         }
8974
8975         if (CNIC_LOADED(bp)) {
8976                 /* Disable Timer scan */
8977                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8978                 /*
8979                  * Wait for at least 10ms and up to 2 second for the timers
8980                  * scan to complete
8981                  */
8982                 for (i = 0; i < 200; i++) {
8983                         usleep_range(10000, 20000);
8984                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8985                                 break;
8986                 }
8987         }
8988         /* Clear ILT */
8989         bnx2x_clear_func_ilt(bp, func);
8990
8991         /* Timers workaround bug for E2: if this is vnic-3,
8992          * we need to set the entire ilt range for this timers.
8993          */
8994         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8995                 struct ilt_client_info ilt_cli;
8996                 /* use dummy TM client */
8997                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8998                 ilt_cli.start = 0;
8999                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9000                 ilt_cli.client_num = ILT_CLIENT_TM;
9001
9002                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9003         }
9004
9005         /* this assumes that reset_port() called before reset_func()*/
9006         if (!CHIP_IS_E1x(bp))
9007                 bnx2x_pf_disable(bp);
9008
9009         bp->dmae_ready = 0;
9010 }
9011
9012 static void bnx2x_reset_port(struct bnx2x *bp)
9013 {
9014         int port = BP_PORT(bp);
9015         u32 val;
9016
9017         /* Reset physical Link */
9018         bnx2x__link_reset(bp);
9019
9020         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9021
9022         /* Do not rcv packets to BRB */
9023         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9024         /* Do not direct rcv packets that are not for MCP to the BRB */
9025         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9026                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9027
9028         /* Configure AEU */
9029         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9030
9031         msleep(100);
9032         /* Check for BRB port occupancy */
9033         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9034         if (val)
9035                 DP(NETIF_MSG_IFDOWN,
9036                    "BRB1 is not empty  %d blocks are occupied\n", val);
9037
9038         /* TODO: Close Doorbell port? */
9039 }
9040
9041 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9042 {
9043         struct bnx2x_func_state_params func_params = {NULL};
9044
9045         /* Prepare parameters for function state transitions */
9046         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9047
9048         func_params.f_obj = &bp->func_obj;
9049         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9050
9051         func_params.params.hw_init.load_phase = load_code;
9052
9053         return bnx2x_func_state_change(bp, &func_params);
9054 }
9055
9056 static int bnx2x_func_stop(struct bnx2x *bp)
9057 {
9058         struct bnx2x_func_state_params func_params = {NULL};
9059         int rc;
9060
9061         /* Prepare parameters for function state transitions */
9062         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9063         func_params.f_obj = &bp->func_obj;
9064         func_params.cmd = BNX2X_F_CMD_STOP;
9065
9066         /*
9067          * Try to stop the function the 'good way'. If fails (in case
9068          * of a parity error during bnx2x_chip_cleanup()) and we are
9069          * not in a debug mode, perform a state transaction in order to
9070          * enable further HW_RESET transaction.
9071          */
9072         rc = bnx2x_func_state_change(bp, &func_params);
9073         if (rc) {
9074 #ifdef BNX2X_STOP_ON_ERROR
9075                 return rc;
9076 #else
9077                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9078                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9079                 return bnx2x_func_state_change(bp, &func_params);
9080 #endif
9081         }
9082
9083         return 0;
9084 }
9085
9086 /**
9087  * bnx2x_send_unload_req - request unload mode from the MCP.
9088  *
9089  * @bp:                 driver handle
9090  * @unload_mode:        requested function's unload mode
9091  *
9092  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9093  */
9094 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9095 {
9096         u32 reset_code = 0;
9097         int port = BP_PORT(bp);
9098
9099         /* Select the UNLOAD request mode */
9100         if (unload_mode == UNLOAD_NORMAL)
9101                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9102
9103         else if (bp->flags & NO_WOL_FLAG)
9104                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9105
9106         else if (bp->wol) {
9107                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9108                 u8 *mac_addr = bp->dev->dev_addr;
9109                 struct pci_dev *pdev = bp->pdev;
9110                 u32 val;
9111                 u16 pmc;
9112
9113                 /* The mac address is written to entries 1-4 to
9114                  * preserve entry 0 which is used by the PMF
9115                  */
9116                 u8 entry = (BP_VN(bp) + 1)*8;
9117
9118                 val = (mac_addr[0] << 8) | mac_addr[1];
9119                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9120
9121                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9122                       (mac_addr[4] << 8) | mac_addr[5];
9123                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9124
9125                 /* Enable the PME and clear the status */
9126                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9127                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9128                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9129
9130                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9131
9132         } else
9133                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9134
9135         /* Send the request to the MCP */
9136         if (!BP_NOMCP(bp))
9137                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9138         else {
9139                 int path = BP_PATH(bp);
9140
9141                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9142                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9143                    bnx2x_load_count[path][2]);
9144                 bnx2x_load_count[path][0]--;
9145                 bnx2x_load_count[path][1 + port]--;
9146                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9147                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9148                    bnx2x_load_count[path][2]);
9149                 if (bnx2x_load_count[path][0] == 0)
9150                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9151                 else if (bnx2x_load_count[path][1 + port] == 0)
9152                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9153                 else
9154                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9155         }
9156
9157         return reset_code;
9158 }
9159
9160 /**
9161  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9162  *
9163  * @bp:         driver handle
9164  * @keep_link:          true iff link should be kept up
9165  */
9166 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9167 {
9168         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9169
9170         /* Report UNLOAD_DONE to MCP */
9171         if (!BP_NOMCP(bp))
9172                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9173 }
9174
9175 static int bnx2x_func_wait_started(struct bnx2x *bp)
9176 {
9177         int tout = 50;
9178         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9179
9180         if (!bp->port.pmf)
9181                 return 0;
9182
9183         /*
9184          * (assumption: No Attention from MCP at this stage)
9185          * PMF probably in the middle of TX disable/enable transaction
9186          * 1. Sync IRS for default SB
9187          * 2. Sync SP queue - this guarantees us that attention handling started
9188          * 3. Wait, that TX disable/enable transaction completes
9189          *
9190          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9191          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9192          * received completion for the transaction the state is TX_STOPPED.
9193          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9194          * transaction.
9195          */
9196
9197         /* make sure default SB ISR is done */
9198         if (msix)
9199                 synchronize_irq(bp->msix_table[0].vector);
9200         else
9201                 synchronize_irq(bp->pdev->irq);
9202
9203         flush_workqueue(bnx2x_wq);
9204         flush_workqueue(bnx2x_iov_wq);
9205
9206         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9207                                 BNX2X_F_STATE_STARTED && tout--)
9208                 msleep(20);
9209
9210         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9211                                                 BNX2X_F_STATE_STARTED) {
9212 #ifdef BNX2X_STOP_ON_ERROR
9213                 BNX2X_ERR("Wrong function state\n");
9214                 return -EBUSY;
9215 #else
9216                 /*
9217                  * Failed to complete the transaction in a "good way"
9218                  * Force both transactions with CLR bit
9219                  */
9220                 struct bnx2x_func_state_params func_params = {NULL};
9221
9222                 DP(NETIF_MSG_IFDOWN,
9223                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9224
9225                 func_params.f_obj = &bp->func_obj;
9226                 __set_bit(RAMROD_DRV_CLR_ONLY,
9227                                         &func_params.ramrod_flags);
9228
9229                 /* STARTED-->TX_ST0PPED */
9230                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9231                 bnx2x_func_state_change(bp, &func_params);
9232
9233                 /* TX_ST0PPED-->STARTED */
9234                 func_params.cmd = BNX2X_F_CMD_TX_START;
9235                 return bnx2x_func_state_change(bp, &func_params);
9236 #endif
9237         }
9238
9239         return 0;
9240 }
9241
9242 static void bnx2x_disable_ptp(struct bnx2x *bp)
9243 {
9244         int port = BP_PORT(bp);
9245
9246         /* Disable sending PTP packets to host */
9247         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9248                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9249
9250         /* Reset PTP event detection rules */
9251         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9252                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9253         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9254                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9255         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9256                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9257         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9258                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9259
9260         /* Disable the PTP feature */
9261         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9262                NIG_REG_P0_PTP_EN, 0x0);
9263 }
9264
9265 /* Called during unload, to stop PTP-related stuff */
9266 static void bnx2x_stop_ptp(struct bnx2x *bp)
9267 {
9268         /* Cancel PTP work queue. Should be done after the Tx queues are
9269          * drained to prevent additional scheduling.
9270          */
9271         cancel_work_sync(&bp->ptp_task);
9272
9273         if (bp->ptp_tx_skb) {
9274                 dev_kfree_skb_any(bp->ptp_tx_skb);
9275                 bp->ptp_tx_skb = NULL;
9276         }
9277
9278         /* Disable PTP in HW */
9279         bnx2x_disable_ptp(bp);
9280
9281         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9282 }
9283
9284 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9285 {
9286         int port = BP_PORT(bp);
9287         int i, rc = 0;
9288         u8 cos;
9289         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9290         u32 reset_code;
9291
9292         /* Wait until tx fastpath tasks complete */
9293         for_each_tx_queue(bp, i) {
9294                 struct bnx2x_fastpath *fp = &bp->fp[i];
9295
9296                 for_each_cos_in_tx_queue(fp, cos)
9297                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9298 #ifdef BNX2X_STOP_ON_ERROR
9299                 if (rc)
9300                         return;
9301 #endif
9302         }
9303
9304         /* Give HW time to discard old tx messages */
9305         usleep_range(1000, 2000);
9306
9307         /* Clean all ETH MACs */
9308         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9309                                 false);
9310         if (rc < 0)
9311                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9312
9313         /* Clean up UC list  */
9314         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9315                                 true);
9316         if (rc < 0)
9317                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9318                           rc);
9319
9320         /* Disable LLH */
9321         if (!CHIP_IS_E1(bp))
9322                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9323
9324         /* Set "drop all" (stop Rx).
9325          * We need to take a netif_addr_lock() here in order to prevent
9326          * a race between the completion code and this code.
9327          */
9328         netif_addr_lock_bh(bp->dev);
9329         /* Schedule the rx_mode command */
9330         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9331                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9332         else
9333                 bnx2x_set_storm_rx_mode(bp);
9334
9335         /* Cleanup multicast configuration */
9336         rparam.mcast_obj = &bp->mcast_obj;
9337         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9338         if (rc < 0)
9339                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9340
9341         netif_addr_unlock_bh(bp->dev);
9342
9343         bnx2x_iov_chip_cleanup(bp);
9344
9345         /*
9346          * Send the UNLOAD_REQUEST to the MCP. This will return if
9347          * this function should perform FUNC, PORT or COMMON HW
9348          * reset.
9349          */
9350         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9351
9352         /*
9353          * (assumption: No Attention from MCP at this stage)
9354          * PMF probably in the middle of TX disable/enable transaction
9355          */
9356         rc = bnx2x_func_wait_started(bp);
9357         if (rc) {
9358                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9359 #ifdef BNX2X_STOP_ON_ERROR
9360                 return;
9361 #endif
9362         }
9363
9364         /* Close multi and leading connections
9365          * Completions for ramrods are collected in a synchronous way
9366          */
9367         for_each_eth_queue(bp, i)
9368                 if (bnx2x_stop_queue(bp, i))
9369 #ifdef BNX2X_STOP_ON_ERROR
9370                         return;
9371 #else
9372                         goto unload_error;
9373 #endif
9374
9375         if (CNIC_LOADED(bp)) {
9376                 for_each_cnic_queue(bp, i)
9377                         if (bnx2x_stop_queue(bp, i))
9378 #ifdef BNX2X_STOP_ON_ERROR
9379                                 return;
9380 #else
9381                                 goto unload_error;
9382 #endif
9383         }
9384
9385         /* If SP settings didn't get completed so far - something
9386          * very wrong has happen.
9387          */
9388         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9389                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9390
9391 #ifndef BNX2X_STOP_ON_ERROR
9392 unload_error:
9393 #endif
9394         rc = bnx2x_func_stop(bp);
9395         if (rc) {
9396                 BNX2X_ERR("Function stop failed!\n");
9397 #ifdef BNX2X_STOP_ON_ERROR
9398                 return;
9399 #endif
9400         }
9401
9402         /* stop_ptp should be after the Tx queues are drained to prevent
9403          * scheduling to the cancelled PTP work queue. It should also be after
9404          * function stop ramrod is sent, since as part of this ramrod FW access
9405          * PTP registers.
9406          */
9407         if (bp->flags & PTP_SUPPORTED)
9408                 bnx2x_stop_ptp(bp);
9409
9410         /* Disable HW interrupts, NAPI */
9411         bnx2x_netif_stop(bp, 1);
9412         /* Delete all NAPI objects */
9413         bnx2x_del_all_napi(bp);
9414         if (CNIC_LOADED(bp))
9415                 bnx2x_del_all_napi_cnic(bp);
9416
9417         /* Release IRQs */
9418         bnx2x_free_irq(bp);
9419
9420         /* Reset the chip */
9421         rc = bnx2x_reset_hw(bp, reset_code);
9422         if (rc)
9423                 BNX2X_ERR("HW_RESET failed\n");
9424
9425         /* Report UNLOAD_DONE to MCP */
9426         bnx2x_send_unload_done(bp, keep_link);
9427 }
9428
9429 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9430 {
9431         u32 val;
9432
9433         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9434
9435         if (CHIP_IS_E1(bp)) {
9436                 int port = BP_PORT(bp);
9437                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9438                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9439
9440                 val = REG_RD(bp, addr);
9441                 val &= ~(0x300);
9442                 REG_WR(bp, addr, val);
9443         } else {
9444                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9445                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9446                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9447                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9448         }
9449 }
9450
9451 /* Close gates #2, #3 and #4: */
9452 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9453 {
9454         u32 val;
9455
9456         /* Gates #2 and #4a are closed/opened for "not E1" only */
9457         if (!CHIP_IS_E1(bp)) {
9458                 /* #4 */
9459                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9460                 /* #2 */
9461                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9462         }
9463
9464         /* #3 */
9465         if (CHIP_IS_E1x(bp)) {
9466                 /* Prevent interrupts from HC on both ports */
9467                 val = REG_RD(bp, HC_REG_CONFIG_1);
9468                 REG_WR(bp, HC_REG_CONFIG_1,
9469                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9470                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9471
9472                 val = REG_RD(bp, HC_REG_CONFIG_0);
9473                 REG_WR(bp, HC_REG_CONFIG_0,
9474                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9475                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9476         } else {
9477                 /* Prevent incoming interrupts in IGU */
9478                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9479
9480                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9481                        (!close) ?
9482                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9483                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9484         }
9485
9486         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9487                 close ? "closing" : "opening");
9488         mmiowb();
9489 }
9490
9491 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9492
9493 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9494 {
9495         /* Do some magic... */
9496         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9497         *magic_val = val & SHARED_MF_CLP_MAGIC;
9498         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9499 }
9500
9501 /**
9502  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9503  *
9504  * @bp:         driver handle
9505  * @magic_val:  old value of the `magic' bit.
9506  */
9507 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9508 {
9509         /* Restore the `magic' bit value... */
9510         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9511         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9512                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9513 }
9514
9515 /**
9516  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9517  *
9518  * @bp:         driver handle
9519  * @magic_val:  old value of 'magic' bit.
9520  *
9521  * Takes care of CLP configurations.
9522  */
9523 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9524 {
9525         u32 shmem;
9526         u32 validity_offset;
9527
9528         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9529
9530         /* Set `magic' bit in order to save MF config */
9531         if (!CHIP_IS_E1(bp))
9532                 bnx2x_clp_reset_prep(bp, magic_val);
9533
9534         /* Get shmem offset */
9535         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9536         validity_offset =
9537                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9538
9539         /* Clear validity map flags */
9540         if (shmem > 0)
9541                 REG_WR(bp, shmem + validity_offset, 0);
9542 }
9543
9544 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9545 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9546
9547 /**
9548  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9549  *
9550  * @bp: driver handle
9551  */
9552 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9553 {
9554         /* special handling for emulation and FPGA,
9555            wait 10 times longer */
9556         if (CHIP_REV_IS_SLOW(bp))
9557                 msleep(MCP_ONE_TIMEOUT*10);
9558         else
9559                 msleep(MCP_ONE_TIMEOUT);
9560 }
9561
9562 /*
9563  * initializes bp->common.shmem_base and waits for validity signature to appear
9564  */
9565 static int bnx2x_init_shmem(struct bnx2x *bp)
9566 {
9567         int cnt = 0;
9568         u32 val = 0;
9569
9570         do {
9571                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9572                 if (bp->common.shmem_base) {
9573                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9574                         if (val & SHR_MEM_VALIDITY_MB)
9575                                 return 0;
9576                 }
9577
9578                 bnx2x_mcp_wait_one(bp);
9579
9580         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9581
9582         BNX2X_ERR("BAD MCP validity signature\n");
9583
9584         return -ENODEV;
9585 }
9586
9587 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9588 {
9589         int rc = bnx2x_init_shmem(bp);
9590
9591         /* Restore the `magic' bit value */
9592         if (!CHIP_IS_E1(bp))
9593                 bnx2x_clp_reset_done(bp, magic_val);
9594
9595         return rc;
9596 }
9597
9598 static void bnx2x_pxp_prep(struct bnx2x *bp)
9599 {
9600         if (!CHIP_IS_E1(bp)) {
9601                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9602                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9603                 mmiowb();
9604         }
9605 }
9606
9607 /*
9608  * Reset the whole chip except for:
9609  *      - PCIE core
9610  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9611  *              one reset bit)
9612  *      - IGU
9613  *      - MISC (including AEU)
9614  *      - GRC
9615  *      - RBCN, RBCP
9616  */
9617 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9618 {
9619         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9620         u32 global_bits2, stay_reset2;
9621
9622         /*
9623          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9624          * (per chip) blocks.
9625          */
9626         global_bits2 =
9627                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9628                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9629
9630         /* Don't reset the following blocks.
9631          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9632          *            reset, as in 4 port device they might still be owned
9633          *            by the MCP (there is only one leader per path).
9634          */
9635         not_reset_mask1 =
9636                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9637                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9638                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9639
9640         not_reset_mask2 =
9641                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9642                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9643                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9644                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9645                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9646                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9647                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9648                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9649                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9650                 MISC_REGISTERS_RESET_REG_2_PGLC |
9651                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9652                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9653                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9654                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9655                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9656                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9657
9658         /*
9659          * Keep the following blocks in reset:
9660          *  - all xxMACs are handled by the bnx2x_link code.
9661          */
9662         stay_reset2 =
9663                 MISC_REGISTERS_RESET_REG_2_XMAC |
9664                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9665
9666         /* Full reset masks according to the chip */
9667         reset_mask1 = 0xffffffff;
9668
9669         if (CHIP_IS_E1(bp))
9670                 reset_mask2 = 0xffff;
9671         else if (CHIP_IS_E1H(bp))
9672                 reset_mask2 = 0x1ffff;
9673         else if (CHIP_IS_E2(bp))
9674                 reset_mask2 = 0xfffff;
9675         else /* CHIP_IS_E3 */
9676                 reset_mask2 = 0x3ffffff;
9677
9678         /* Don't reset global blocks unless we need to */
9679         if (!global)
9680                 reset_mask2 &= ~global_bits2;
9681
9682         /*
9683          * In case of attention in the QM, we need to reset PXP
9684          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9685          * because otherwise QM reset would release 'close the gates' shortly
9686          * before resetting the PXP, then the PSWRQ would send a write
9687          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9688          * read the payload data from PSWWR, but PSWWR would not
9689          * respond. The write queue in PGLUE would stuck, dmae commands
9690          * would not return. Therefore it's important to reset the second
9691          * reset register (containing the
9692          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9693          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9694          * bit).
9695          */
9696         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9697                reset_mask2 & (~not_reset_mask2));
9698
9699         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9700                reset_mask1 & (~not_reset_mask1));
9701
9702         barrier();
9703         mmiowb();
9704
9705         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9706                reset_mask2 & (~stay_reset2));
9707
9708         barrier();
9709         mmiowb();
9710
9711         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9712         mmiowb();
9713 }
9714
9715 /**
9716  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9717  * It should get cleared in no more than 1s.
9718  *
9719  * @bp: driver handle
9720  *
9721  * It should get cleared in no more than 1s. Returns 0 if
9722  * pending writes bit gets cleared.
9723  */
9724 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9725 {
9726         u32 cnt = 1000;
9727         u32 pend_bits = 0;
9728
9729         do {
9730                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9731
9732                 if (pend_bits == 0)
9733                         break;
9734
9735                 usleep_range(1000, 2000);
9736         } while (cnt-- > 0);
9737
9738         if (cnt <= 0) {
9739                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9740                           pend_bits);
9741                 return -EBUSY;
9742         }
9743
9744         return 0;
9745 }
9746
9747 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9748 {
9749         int cnt = 1000;
9750         u32 val = 0;
9751         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9752         u32 tags_63_32 = 0;
9753
9754         /* Empty the Tetris buffer, wait for 1s */
9755         do {
9756                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9757                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9758                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9759                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9760                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9761                 if (CHIP_IS_E3(bp))
9762                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9763
9764                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9765                     ((port_is_idle_0 & 0x1) == 0x1) &&
9766                     ((port_is_idle_1 & 0x1) == 0x1) &&
9767                     (pgl_exp_rom2 == 0xffffffff) &&
9768                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9769                         break;
9770                 usleep_range(1000, 2000);
9771         } while (cnt-- > 0);
9772
9773         if (cnt <= 0) {
9774                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9775                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9776                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9777                           pgl_exp_rom2);
9778                 return -EAGAIN;
9779         }
9780
9781         barrier();
9782
9783         /* Close gates #2, #3 and #4 */
9784         bnx2x_set_234_gates(bp, true);
9785
9786         /* Poll for IGU VQs for 57712 and newer chips */
9787         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9788                 return -EAGAIN;
9789
9790         /* TBD: Indicate that "process kill" is in progress to MCP */
9791
9792         /* Clear "unprepared" bit */
9793         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9794         barrier();
9795
9796         /* Make sure all is written to the chip before the reset */
9797         mmiowb();
9798
9799         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9800          * PSWHST, GRC and PSWRD Tetris buffer.
9801          */
9802         usleep_range(1000, 2000);
9803
9804         /* Prepare to chip reset: */
9805         /* MCP */
9806         if (global)
9807                 bnx2x_reset_mcp_prep(bp, &val);
9808
9809         /* PXP */
9810         bnx2x_pxp_prep(bp);
9811         barrier();
9812
9813         /* reset the chip */
9814         bnx2x_process_kill_chip_reset(bp, global);
9815         barrier();
9816
9817         /* clear errors in PGB */
9818         if (!CHIP_IS_E1x(bp))
9819                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9820
9821         /* Recover after reset: */
9822         /* MCP */
9823         if (global && bnx2x_reset_mcp_comp(bp, val))
9824                 return -EAGAIN;
9825
9826         /* TBD: Add resetting the NO_MCP mode DB here */
9827
9828         /* Open the gates #2, #3 and #4 */
9829         bnx2x_set_234_gates(bp, false);
9830
9831         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9832          * reset state, re-enable attentions. */
9833
9834         return 0;
9835 }
9836
9837 static int bnx2x_leader_reset(struct bnx2x *bp)
9838 {
9839         int rc = 0;
9840         bool global = bnx2x_reset_is_global(bp);
9841         u32 load_code;
9842
9843         /* if not going to reset MCP - load "fake" driver to reset HW while
9844          * driver is owner of the HW
9845          */
9846         if (!global && !BP_NOMCP(bp)) {
9847                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9848                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9849                 if (!load_code) {
9850                         BNX2X_ERR("MCP response failure, aborting\n");
9851                         rc = -EAGAIN;
9852                         goto exit_leader_reset;
9853                 }
9854                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9855                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9856                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9857                         rc = -EAGAIN;
9858                         goto exit_leader_reset2;
9859                 }
9860                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9861                 if (!load_code) {
9862                         BNX2X_ERR("MCP response failure, aborting\n");
9863                         rc = -EAGAIN;
9864                         goto exit_leader_reset2;
9865                 }
9866         }
9867
9868         /* Try to recover after the failure */
9869         if (bnx2x_process_kill(bp, global)) {
9870                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9871                           BP_PATH(bp));
9872                 rc = -EAGAIN;
9873                 goto exit_leader_reset2;
9874         }
9875
9876         /*
9877          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9878          * state.
9879          */
9880         bnx2x_set_reset_done(bp);
9881         if (global)
9882                 bnx2x_clear_reset_global(bp);
9883
9884 exit_leader_reset2:
9885         /* unload "fake driver" if it was loaded */
9886         if (!global && !BP_NOMCP(bp)) {
9887                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9888                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9889         }
9890 exit_leader_reset:
9891         bp->is_leader = 0;
9892         bnx2x_release_leader_lock(bp);
9893         smp_mb();
9894         return rc;
9895 }
9896
9897 static void bnx2x_recovery_failed(struct bnx2x *bp)
9898 {
9899         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9900
9901         /* Disconnect this device */
9902         netif_device_detach(bp->dev);
9903
9904         /*
9905          * Block ifup for all function on this engine until "process kill"
9906          * or power cycle.
9907          */
9908         bnx2x_set_reset_in_progress(bp);
9909
9910         /* Shut down the power */
9911         bnx2x_set_power_state(bp, PCI_D3hot);
9912
9913         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9914
9915         smp_mb();
9916 }
9917
9918 /*
9919  * Assumption: runs under rtnl lock. This together with the fact
9920  * that it's called only from bnx2x_sp_rtnl() ensure that it
9921  * will never be called when netif_running(bp->dev) is false.
9922  */
9923 static void bnx2x_parity_recover(struct bnx2x *bp)
9924 {
9925         bool global = false;
9926         u32 error_recovered, error_unrecovered;
9927         bool is_parity;
9928
9929         DP(NETIF_MSG_HW, "Handling parity\n");
9930         while (1) {
9931                 switch (bp->recovery_state) {
9932                 case BNX2X_RECOVERY_INIT:
9933                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9934                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9935                         WARN_ON(!is_parity);
9936
9937                         /* Try to get a LEADER_LOCK HW lock */
9938                         if (bnx2x_trylock_leader_lock(bp)) {
9939                                 bnx2x_set_reset_in_progress(bp);
9940                                 /*
9941                                  * Check if there is a global attention and if
9942                                  * there was a global attention, set the global
9943                                  * reset bit.
9944                                  */
9945
9946                                 if (global)
9947                                         bnx2x_set_reset_global(bp);
9948
9949                                 bp->is_leader = 1;
9950                         }
9951
9952                         /* Stop the driver */
9953                         /* If interface has been removed - break */
9954                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9955                                 return;
9956
9957                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9958
9959                         /* Ensure "is_leader", MCP command sequence and
9960                          * "recovery_state" update values are seen on other
9961                          * CPUs.
9962                          */
9963                         smp_mb();
9964                         break;
9965
9966                 case BNX2X_RECOVERY_WAIT:
9967                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9968                         if (bp->is_leader) {
9969                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9970                                 bool other_load_status =
9971                                         bnx2x_get_load_status(bp, other_engine);
9972                                 bool load_status =
9973                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9974                                 global = bnx2x_reset_is_global(bp);
9975
9976                                 /*
9977                                  * In case of a parity in a global block, let
9978                                  * the first leader that performs a
9979                                  * leader_reset() reset the global blocks in
9980                                  * order to clear global attentions. Otherwise
9981                                  * the gates will remain closed for that
9982                                  * engine.
9983                                  */
9984                                 if (load_status ||
9985                                     (global && other_load_status)) {
9986                                         /* Wait until all other functions get
9987                                          * down.
9988                                          */
9989                                         schedule_delayed_work(&bp->sp_rtnl_task,
9990                                                                 HZ/10);
9991                                         return;
9992                                 } else {
9993                                         /* If all other functions got down -
9994                                          * try to bring the chip back to
9995                                          * normal. In any case it's an exit
9996                                          * point for a leader.
9997                                          */
9998                                         if (bnx2x_leader_reset(bp)) {
9999                                                 bnx2x_recovery_failed(bp);
10000                                                 return;
10001                                         }
10002
10003                                         /* If we are here, means that the
10004                                          * leader has succeeded and doesn't
10005                                          * want to be a leader any more. Try
10006                                          * to continue as a none-leader.
10007                                          */
10008                                         break;
10009                                 }
10010                         } else { /* non-leader */
10011                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10012                                         /* Try to get a LEADER_LOCK HW lock as
10013                                          * long as a former leader may have
10014                                          * been unloaded by the user or
10015                                          * released a leadership by another
10016                                          * reason.
10017                                          */
10018                                         if (bnx2x_trylock_leader_lock(bp)) {
10019                                                 /* I'm a leader now! Restart a
10020                                                  * switch case.
10021                                                  */
10022                                                 bp->is_leader = 1;
10023                                                 break;
10024                                         }
10025
10026                                         schedule_delayed_work(&bp->sp_rtnl_task,
10027                                                                 HZ/10);
10028                                         return;
10029
10030                                 } else {
10031                                         /*
10032                                          * If there was a global attention, wait
10033                                          * for it to be cleared.
10034                                          */
10035                                         if (bnx2x_reset_is_global(bp)) {
10036                                                 schedule_delayed_work(
10037                                                         &bp->sp_rtnl_task,
10038                                                         HZ/10);
10039                                                 return;
10040                                         }
10041
10042                                         error_recovered =
10043                                           bp->eth_stats.recoverable_error;
10044                                         error_unrecovered =
10045                                           bp->eth_stats.unrecoverable_error;
10046                                         bp->recovery_state =
10047                                                 BNX2X_RECOVERY_NIC_LOADING;
10048                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10049                                                 error_unrecovered++;
10050                                                 netdev_err(bp->dev,
10051                                                            "Recovery failed. Power cycle needed\n");
10052                                                 /* Disconnect this device */
10053                                                 netif_device_detach(bp->dev);
10054                                                 /* Shut down the power */
10055                                                 bnx2x_set_power_state(
10056                                                         bp, PCI_D3hot);
10057                                                 smp_mb();
10058                                         } else {
10059                                                 bp->recovery_state =
10060                                                         BNX2X_RECOVERY_DONE;
10061                                                 error_recovered++;
10062                                                 smp_mb();
10063                                         }
10064                                         bp->eth_stats.recoverable_error =
10065                                                 error_recovered;
10066                                         bp->eth_stats.unrecoverable_error =
10067                                                 error_unrecovered;
10068
10069                                         return;
10070                                 }
10071                         }
10072                 default:
10073                         return;
10074                 }
10075         }
10076 }
10077
10078 #ifdef CONFIG_BNX2X_VXLAN
10079 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10080 {
10081         struct bnx2x_func_switch_update_params *switch_update_params;
10082         struct bnx2x_func_state_params func_params = {NULL};
10083         int rc;
10084
10085         switch_update_params = &func_params.params.switch_update;
10086
10087         /* Prepare parameters for function state transitions */
10088         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10089         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10090
10091         func_params.f_obj = &bp->func_obj;
10092         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10093
10094         /* Function parameters */
10095         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10096                   &switch_update_params->changes);
10097         switch_update_params->vxlan_dst_port = port;
10098         rc = bnx2x_func_state_change(bp, &func_params);
10099         if (rc)
10100                 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10101                           port, rc);
10102         return rc;
10103 }
10104
10105 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10106 {
10107         if (!netif_running(bp->dev))
10108                 return;
10109
10110         if (bp->vxlan_dst_port || !IS_PF(bp)) {
10111                 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10112                 return;
10113         }
10114
10115         bp->vxlan_dst_port = port;
10116         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10117 }
10118
10119 static void bnx2x_add_vxlan_port(struct net_device *netdev,
10120                                  sa_family_t sa_family, __be16 port)
10121 {
10122         struct bnx2x *bp = netdev_priv(netdev);
10123         u16 t_port = ntohs(port);
10124
10125         __bnx2x_add_vxlan_port(bp, t_port);
10126 }
10127
10128 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10129 {
10130         if (!bp->vxlan_dst_port || bp->vxlan_dst_port != port || !IS_PF(bp)) {
10131                 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10132                 return;
10133         }
10134
10135         if (netif_running(bp->dev)) {
10136                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10137         } else {
10138                 bp->vxlan_dst_port = 0;
10139                 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10140         }
10141 }
10142
10143 static void bnx2x_del_vxlan_port(struct net_device *netdev,
10144                                  sa_family_t sa_family, __be16 port)
10145 {
10146         struct bnx2x *bp = netdev_priv(netdev);
10147         u16 t_port = ntohs(port);
10148
10149         __bnx2x_del_vxlan_port(bp, t_port);
10150 }
10151 #endif
10152
10153 static int bnx2x_close(struct net_device *dev);
10154
10155 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10156  * scheduled on a general queue in order to prevent a dead lock.
10157  */
10158 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10159 {
10160         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10161 #ifdef CONFIG_BNX2X_VXLAN
10162         u16 port;
10163 #endif
10164
10165         rtnl_lock();
10166
10167         if (!netif_running(bp->dev)) {
10168                 rtnl_unlock();
10169                 return;
10170         }
10171
10172         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10173 #ifdef BNX2X_STOP_ON_ERROR
10174                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10175                           "you will need to reboot when done\n");
10176                 goto sp_rtnl_not_reset;
10177 #endif
10178                 /*
10179                  * Clear all pending SP commands as we are going to reset the
10180                  * function anyway.
10181                  */
10182                 bp->sp_rtnl_state = 0;
10183                 smp_mb();
10184
10185                 bnx2x_parity_recover(bp);
10186
10187                 rtnl_unlock();
10188                 return;
10189         }
10190
10191         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10192 #ifdef BNX2X_STOP_ON_ERROR
10193                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10194                           "you will need to reboot when done\n");
10195                 goto sp_rtnl_not_reset;
10196 #endif
10197
10198                 /*
10199                  * Clear all pending SP commands as we are going to reset the
10200                  * function anyway.
10201                  */
10202                 bp->sp_rtnl_state = 0;
10203                 smp_mb();
10204
10205                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10206                 bnx2x_nic_load(bp, LOAD_NORMAL);
10207
10208                 rtnl_unlock();
10209                 return;
10210         }
10211 #ifdef BNX2X_STOP_ON_ERROR
10212 sp_rtnl_not_reset:
10213 #endif
10214         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10215                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10216         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10217                 bnx2x_after_function_update(bp);
10218         /*
10219          * in case of fan failure we need to reset id if the "stop on error"
10220          * debug flag is set, since we trying to prevent permanent overheating
10221          * damage
10222          */
10223         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10224                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10225                 netif_device_detach(bp->dev);
10226                 bnx2x_close(bp->dev);
10227                 rtnl_unlock();
10228                 return;
10229         }
10230
10231         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10232                 DP(BNX2X_MSG_SP,
10233                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10234                 bnx2x_vfpf_set_mcast(bp->dev);
10235         }
10236         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10237                                &bp->sp_rtnl_state)){
10238                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10239                         bnx2x_tx_disable(bp);
10240                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10241                 }
10242         }
10243
10244         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10245                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10246                 bnx2x_set_rx_mode_inner(bp);
10247         }
10248
10249         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10250                                &bp->sp_rtnl_state))
10251                 bnx2x_pf_set_vfs_vlan(bp);
10252
10253         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10254                 bnx2x_dcbx_stop_hw_tx(bp);
10255                 bnx2x_dcbx_resume_hw_tx(bp);
10256         }
10257
10258         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10259                                &bp->sp_rtnl_state))
10260                 bnx2x_update_mng_version(bp);
10261
10262 #ifdef CONFIG_BNX2X_VXLAN
10263         port = bp->vxlan_dst_port;
10264         if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10265                                &bp->sp_rtnl_state)) {
10266                 if (!bnx2x_vxlan_port_update(bp, port))
10267                         netdev_info(bp->dev, "Added vxlan dest port %d", port);
10268                 else
10269                         bp->vxlan_dst_port = 0;
10270         }
10271
10272         if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10273                                &bp->sp_rtnl_state)) {
10274                 if (!bnx2x_vxlan_port_update(bp, 0)) {
10275                         netdev_info(bp->dev,
10276                                     "Deleted vxlan dest port %d", port);
10277                         bp->vxlan_dst_port = 0;
10278                         vxlan_get_rx_port(bp->dev);
10279                 }
10280         }
10281 #endif
10282
10283         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10284          * can be called from other contexts as well)
10285          */
10286         rtnl_unlock();
10287
10288         /* enable SR-IOV if applicable */
10289         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10290                                                &bp->sp_rtnl_state)) {
10291                 bnx2x_disable_sriov(bp);
10292                 bnx2x_enable_sriov(bp);
10293         }
10294 }
10295
10296 static void bnx2x_period_task(struct work_struct *work)
10297 {
10298         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10299
10300         if (!netif_running(bp->dev))
10301                 goto period_task_exit;
10302
10303         if (CHIP_REV_IS_SLOW(bp)) {
10304                 BNX2X_ERR("period task called on emulation, ignoring\n");
10305                 goto period_task_exit;
10306         }
10307
10308         bnx2x_acquire_phy_lock(bp);
10309         /*
10310          * The barrier is needed to ensure the ordering between the writing to
10311          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10312          * the reading here.
10313          */
10314         smp_mb();
10315         if (bp->port.pmf) {
10316                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10317
10318                 /* Re-queue task in 1 sec */
10319                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10320         }
10321
10322         bnx2x_release_phy_lock(bp);
10323 period_task_exit:
10324         return;
10325 }
10326
10327 /*
10328  * Init service functions
10329  */
10330
10331 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10332 {
10333         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10334         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10335         return base + (BP_ABS_FUNC(bp)) * stride;
10336 }
10337
10338 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10339                                          u8 port, u32 reset_reg,
10340                                          struct bnx2x_mac_vals *vals)
10341 {
10342         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10343         u32 base_addr;
10344
10345         if (!(mask & reset_reg))
10346                 return false;
10347
10348         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10349         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10350         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10351         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10352         REG_WR(bp, vals->umac_addr[port], 0);
10353
10354         return true;
10355 }
10356
10357 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10358                                         struct bnx2x_mac_vals *vals)
10359 {
10360         u32 val, base_addr, offset, mask, reset_reg;
10361         bool mac_stopped = false;
10362         u8 port = BP_PORT(bp);
10363
10364         /* reset addresses as they also mark which values were changed */
10365         memset(vals, 0, sizeof(*vals));
10366
10367         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10368
10369         if (!CHIP_IS_E3(bp)) {
10370                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10371                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10372                 if ((mask & reset_reg) && val) {
10373                         u32 wb_data[2];
10374                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10375                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10376                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10377                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10378                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10379
10380                         /*
10381                          * use rd/wr since we cannot use dmae. This is safe
10382                          * since MCP won't access the bus due to the request
10383                          * to unload, and no function on the path can be
10384                          * loaded at this time.
10385                          */
10386                         wb_data[0] = REG_RD(bp, base_addr + offset);
10387                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10388                         vals->bmac_addr = base_addr + offset;
10389                         vals->bmac_val[0] = wb_data[0];
10390                         vals->bmac_val[1] = wb_data[1];
10391                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10392                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10393                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10394                 }
10395                 BNX2X_DEV_INFO("Disable emac Rx\n");
10396                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10397                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10398                 REG_WR(bp, vals->emac_addr, 0);
10399                 mac_stopped = true;
10400         } else {
10401                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10402                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10403                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10404                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10405                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10406                                val & ~(1 << 1));
10407                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10408                                val | (1 << 1));
10409                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10410                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10411                         REG_WR(bp, vals->xmac_addr, 0);
10412                         mac_stopped = true;
10413                 }
10414
10415                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10416                                                             reset_reg, vals);
10417                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10418                                                             reset_reg, vals);
10419         }
10420
10421         if (mac_stopped)
10422                 msleep(20);
10423 }
10424
10425 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10426 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10427                                         0x1848 + ((f) << 4))
10428 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10429 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10430 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10431
10432 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10433 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10434 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10435
10436 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10437 {
10438         /* UNDI marks its presence in DORQ -
10439          * it initializes CID offset for normal bell to 0x7
10440          */
10441         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10442             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10443                 return false;
10444
10445         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10446                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10447                 return true;
10448         }
10449
10450         return false;
10451 }
10452
10453 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10454 {
10455         u16 rcq, bd;
10456         u32 addr, tmp_reg;
10457
10458         if (BP_FUNC(bp) < 2)
10459                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10460         else
10461                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10462
10463         tmp_reg = REG_RD(bp, addr);
10464         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10465         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10466
10467         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10468         REG_WR(bp, addr, tmp_reg);
10469
10470         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10471                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10472 }
10473
10474 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10475 {
10476         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10477                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10478         if (!rc) {
10479                 BNX2X_ERR("MCP response failure, aborting\n");
10480                 return -EBUSY;
10481         }
10482
10483         return 0;
10484 }
10485
10486 static struct bnx2x_prev_path_list *
10487                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10488 {
10489         struct bnx2x_prev_path_list *tmp_list;
10490
10491         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10492                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10493                     bp->pdev->bus->number == tmp_list->bus &&
10494                     BP_PATH(bp) == tmp_list->path)
10495                         return tmp_list;
10496
10497         return NULL;
10498 }
10499
10500 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10501 {
10502         struct bnx2x_prev_path_list *tmp_list;
10503         int rc;
10504
10505         rc = down_interruptible(&bnx2x_prev_sem);
10506         if (rc) {
10507                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10508                 return rc;
10509         }
10510
10511         tmp_list = bnx2x_prev_path_get_entry(bp);
10512         if (tmp_list) {
10513                 tmp_list->aer = 1;
10514                 rc = 0;
10515         } else {
10516                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10517                           BP_PATH(bp));
10518         }
10519
10520         up(&bnx2x_prev_sem);
10521
10522         return rc;
10523 }
10524
10525 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10526 {
10527         struct bnx2x_prev_path_list *tmp_list;
10528         bool rc = false;
10529
10530         if (down_trylock(&bnx2x_prev_sem))
10531                 return false;
10532
10533         tmp_list = bnx2x_prev_path_get_entry(bp);
10534         if (tmp_list) {
10535                 if (tmp_list->aer) {
10536                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10537                            BP_PATH(bp));
10538                 } else {
10539                         rc = true;
10540                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10541                                        BP_PATH(bp));
10542                 }
10543         }
10544
10545         up(&bnx2x_prev_sem);
10546
10547         return rc;
10548 }
10549
10550 bool bnx2x_port_after_undi(struct bnx2x *bp)
10551 {
10552         struct bnx2x_prev_path_list *entry;
10553         bool val;
10554
10555         down(&bnx2x_prev_sem);
10556
10557         entry = bnx2x_prev_path_get_entry(bp);
10558         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10559
10560         up(&bnx2x_prev_sem);
10561
10562         return val;
10563 }
10564
10565 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10566 {
10567         struct bnx2x_prev_path_list *tmp_list;
10568         int rc;
10569
10570         rc = down_interruptible(&bnx2x_prev_sem);
10571         if (rc) {
10572                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10573                 return rc;
10574         }
10575
10576         /* Check whether the entry for this path already exists */
10577         tmp_list = bnx2x_prev_path_get_entry(bp);
10578         if (tmp_list) {
10579                 if (!tmp_list->aer) {
10580                         BNX2X_ERR("Re-Marking the path.\n");
10581                 } else {
10582                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10583                            BP_PATH(bp));
10584                         tmp_list->aer = 0;
10585                 }
10586                 up(&bnx2x_prev_sem);
10587                 return 0;
10588         }
10589         up(&bnx2x_prev_sem);
10590
10591         /* Create an entry for this path and add it */
10592         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10593         if (!tmp_list) {
10594                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10595                 return -ENOMEM;
10596         }
10597
10598         tmp_list->bus = bp->pdev->bus->number;
10599         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10600         tmp_list->path = BP_PATH(bp);
10601         tmp_list->aer = 0;
10602         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10603
10604         rc = down_interruptible(&bnx2x_prev_sem);
10605         if (rc) {
10606                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10607                 kfree(tmp_list);
10608         } else {
10609                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10610                    BP_PATH(bp));
10611                 list_add(&tmp_list->list, &bnx2x_prev_list);
10612                 up(&bnx2x_prev_sem);
10613         }
10614
10615         return rc;
10616 }
10617
10618 static int bnx2x_do_flr(struct bnx2x *bp)
10619 {
10620         struct pci_dev *dev = bp->pdev;
10621
10622         if (CHIP_IS_E1x(bp)) {
10623                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10624                 return -EINVAL;
10625         }
10626
10627         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10628         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10629                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10630                           bp->common.bc_ver);
10631                 return -EINVAL;
10632         }
10633
10634         if (!pci_wait_for_pending_transaction(dev))
10635                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10636
10637         BNX2X_DEV_INFO("Initiating FLR\n");
10638         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10639
10640         return 0;
10641 }
10642
10643 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10644 {
10645         int rc;
10646
10647         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10648
10649         /* Test if previous unload process was already finished for this path */
10650         if (bnx2x_prev_is_path_marked(bp))
10651                 return bnx2x_prev_mcp_done(bp);
10652
10653         BNX2X_DEV_INFO("Path is unmarked\n");
10654
10655         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10656         if (bnx2x_prev_is_after_undi(bp))
10657                 goto out;
10658
10659         /* If function has FLR capabilities, and existing FW version matches
10660          * the one required, then FLR will be sufficient to clean any residue
10661          * left by previous driver
10662          */
10663         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10664
10665         if (!rc) {
10666                 /* fw version is good */
10667                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10668                 rc = bnx2x_do_flr(bp);
10669         }
10670
10671         if (!rc) {
10672                 /* FLR was performed */
10673                 BNX2X_DEV_INFO("FLR successful\n");
10674                 return 0;
10675         }
10676
10677         BNX2X_DEV_INFO("Could not FLR\n");
10678
10679 out:
10680         /* Close the MCP request, return failure*/
10681         rc = bnx2x_prev_mcp_done(bp);
10682         if (!rc)
10683                 rc = BNX2X_PREV_WAIT_NEEDED;
10684
10685         return rc;
10686 }
10687
10688 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10689 {
10690         u32 reset_reg, tmp_reg = 0, rc;
10691         bool prev_undi = false;
10692         struct bnx2x_mac_vals mac_vals;
10693
10694         /* It is possible a previous function received 'common' answer,
10695          * but hasn't loaded yet, therefore creating a scenario of
10696          * multiple functions receiving 'common' on the same path.
10697          */
10698         BNX2X_DEV_INFO("Common unload Flow\n");
10699
10700         memset(&mac_vals, 0, sizeof(mac_vals));
10701
10702         if (bnx2x_prev_is_path_marked(bp))
10703                 return bnx2x_prev_mcp_done(bp);
10704
10705         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10706
10707         /* Reset should be performed after BRB is emptied */
10708         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10709                 u32 timer_count = 1000;
10710
10711                 /* Close the MAC Rx to prevent BRB from filling up */
10712                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10713
10714                 /* close LLH filters for both ports towards the BRB */
10715                 bnx2x_set_rx_filter(&bp->link_params, 0);
10716                 bp->link_params.port ^= 1;
10717                 bnx2x_set_rx_filter(&bp->link_params, 0);
10718                 bp->link_params.port ^= 1;
10719
10720                 /* Check if the UNDI driver was previously loaded */
10721                 if (bnx2x_prev_is_after_undi(bp)) {
10722                         prev_undi = true;
10723                         /* clear the UNDI indication */
10724                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10725                         /* clear possible idle check errors */
10726                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10727                 }
10728                 if (!CHIP_IS_E1x(bp))
10729                         /* block FW from writing to host */
10730                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10731
10732                 /* wait until BRB is empty */
10733                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10734                 while (timer_count) {
10735                         u32 prev_brb = tmp_reg;
10736
10737                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10738                         if (!tmp_reg)
10739                                 break;
10740
10741                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10742
10743                         /* reset timer as long as BRB actually gets emptied */
10744                         if (prev_brb > tmp_reg)
10745                                 timer_count = 1000;
10746                         else
10747                                 timer_count--;
10748
10749                         /* If UNDI resides in memory, manually increment it */
10750                         if (prev_undi)
10751                                 bnx2x_prev_unload_undi_inc(bp, 1);
10752
10753                         udelay(10);
10754                 }
10755
10756                 if (!timer_count)
10757                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10758         }
10759
10760         /* No packets are in the pipeline, path is ready for reset */
10761         bnx2x_reset_common(bp);
10762
10763         if (mac_vals.xmac_addr)
10764                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10765         if (mac_vals.umac_addr[0])
10766                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10767         if (mac_vals.umac_addr[1])
10768                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10769         if (mac_vals.emac_addr)
10770                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10771         if (mac_vals.bmac_addr) {
10772                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10773                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10774         }
10775
10776         rc = bnx2x_prev_mark_path(bp, prev_undi);
10777         if (rc) {
10778                 bnx2x_prev_mcp_done(bp);
10779                 return rc;
10780         }
10781
10782         return bnx2x_prev_mcp_done(bp);
10783 }
10784
10785 static int bnx2x_prev_unload(struct bnx2x *bp)
10786 {
10787         int time_counter = 10;
10788         u32 rc, fw, hw_lock_reg, hw_lock_val;
10789         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10790
10791         /* clear hw from errors which may have resulted from an interrupted
10792          * dmae transaction.
10793          */
10794         bnx2x_clean_pglue_errors(bp);
10795
10796         /* Release previously held locks */
10797         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10798                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10799                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10800
10801         hw_lock_val = REG_RD(bp, hw_lock_reg);
10802         if (hw_lock_val) {
10803                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10804                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10805                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10806                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10807                 }
10808
10809                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10810                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10811         } else
10812                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10813
10814         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10815                 BNX2X_DEV_INFO("Release previously held alr\n");
10816                 bnx2x_release_alr(bp);
10817         }
10818
10819         do {
10820                 int aer = 0;
10821                 /* Lock MCP using an unload request */
10822                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10823                 if (!fw) {
10824                         BNX2X_ERR("MCP response failure, aborting\n");
10825                         rc = -EBUSY;
10826                         break;
10827                 }
10828
10829                 rc = down_interruptible(&bnx2x_prev_sem);
10830                 if (rc) {
10831                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10832                                   rc);
10833                 } else {
10834                         /* If Path is marked by EEH, ignore unload status */
10835                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10836                                  bnx2x_prev_path_get_entry(bp)->aer);
10837                         up(&bnx2x_prev_sem);
10838                 }
10839
10840                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10841                         rc = bnx2x_prev_unload_common(bp);
10842                         break;
10843                 }
10844
10845                 /* non-common reply from MCP might require looping */
10846                 rc = bnx2x_prev_unload_uncommon(bp);
10847                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10848                         break;
10849
10850                 msleep(20);
10851         } while (--time_counter);
10852
10853         if (!time_counter || rc) {
10854                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10855                 rc = -EPROBE_DEFER;
10856         }
10857
10858         /* Mark function if its port was used to boot from SAN */
10859         if (bnx2x_port_after_undi(bp))
10860                 bp->link_params.feature_config_flags |=
10861                         FEATURE_CONFIG_BOOT_FROM_SAN;
10862
10863         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10864
10865         return rc;
10866 }
10867
10868 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10869 {
10870         u32 val, val2, val3, val4, id, boot_mode;
10871         u16 pmc;
10872
10873         /* Get the chip revision id and number. */
10874         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10875         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10876         id = ((val & 0xffff) << 16);
10877         val = REG_RD(bp, MISC_REG_CHIP_REV);
10878         id |= ((val & 0xf) << 12);
10879
10880         /* Metal is read from PCI regs, but we can't access >=0x400 from
10881          * the configuration space (so we need to reg_rd)
10882          */
10883         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10884         id |= (((val >> 24) & 0xf) << 4);
10885         val = REG_RD(bp, MISC_REG_BOND_ID);
10886         id |= (val & 0xf);
10887         bp->common.chip_id = id;
10888
10889         /* force 57811 according to MISC register */
10890         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10891                 if (CHIP_IS_57810(bp))
10892                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10893                                 (bp->common.chip_id & 0x0000FFFF);
10894                 else if (CHIP_IS_57810_MF(bp))
10895                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10896                                 (bp->common.chip_id & 0x0000FFFF);
10897                 bp->common.chip_id |= 0x1;
10898         }
10899
10900         /* Set doorbell size */
10901         bp->db_size = (1 << BNX2X_DB_SHIFT);
10902
10903         if (!CHIP_IS_E1x(bp)) {
10904                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10905                 if ((val & 1) == 0)
10906                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10907                 else
10908                         val = (val >> 1) & 1;
10909                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10910                                                        "2_PORT_MODE");
10911                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10912                                                  CHIP_2_PORT_MODE;
10913
10914                 if (CHIP_MODE_IS_4_PORT(bp))
10915                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10916                 else
10917                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10918         } else {
10919                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10920                 bp->pfid = bp->pf_num;                  /* 0..7 */
10921         }
10922
10923         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10924
10925         bp->link_params.chip_id = bp->common.chip_id;
10926         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10927
10928         val = (REG_RD(bp, 0x2874) & 0x55);
10929         if ((bp->common.chip_id & 0x1) ||
10930             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10931                 bp->flags |= ONE_PORT_FLAG;
10932                 BNX2X_DEV_INFO("single port device\n");
10933         }
10934
10935         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10936         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10937                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10938         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10939                        bp->common.flash_size, bp->common.flash_size);
10940
10941         bnx2x_init_shmem(bp);
10942
10943         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10944                                         MISC_REG_GENERIC_CR_1 :
10945                                         MISC_REG_GENERIC_CR_0));
10946
10947         bp->link_params.shmem_base = bp->common.shmem_base;
10948         bp->link_params.shmem2_base = bp->common.shmem2_base;
10949         if (SHMEM2_RD(bp, size) >
10950             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10951                 bp->link_params.lfa_base =
10952                 REG_RD(bp, bp->common.shmem2_base +
10953                        (u32)offsetof(struct shmem2_region,
10954                                      lfa_host_addr[BP_PORT(bp)]));
10955         else
10956                 bp->link_params.lfa_base = 0;
10957         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10958                        bp->common.shmem_base, bp->common.shmem2_base);
10959
10960         if (!bp->common.shmem_base) {
10961                 BNX2X_DEV_INFO("MCP not active\n");
10962                 bp->flags |= NO_MCP_FLAG;
10963                 return;
10964         }
10965
10966         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10967         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10968
10969         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10970                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10971                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10972
10973         bp->link_params.feature_config_flags = 0;
10974         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10975         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10976                 bp->link_params.feature_config_flags |=
10977                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10978         else
10979                 bp->link_params.feature_config_flags &=
10980                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10981
10982         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10983         bp->common.bc_ver = val;
10984         BNX2X_DEV_INFO("bc_ver %X\n", val);
10985         if (val < BNX2X_BC_VER) {
10986                 /* for now only warn
10987                  * later we might need to enforce this */
10988                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10989                           BNX2X_BC_VER, val);
10990         }
10991         bp->link_params.feature_config_flags |=
10992                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10993                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10994
10995         bp->link_params.feature_config_flags |=
10996                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10997                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10998         bp->link_params.feature_config_flags |=
10999                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11000                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11001         bp->link_params.feature_config_flags |=
11002                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11003                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11004
11005         bp->link_params.feature_config_flags |=
11006                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11007                 FEATURE_CONFIG_MT_SUPPORT : 0;
11008
11009         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11010                         BC_SUPPORTS_PFC_STATS : 0;
11011
11012         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11013                         BC_SUPPORTS_FCOE_FEATURES : 0;
11014
11015         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11016                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11017
11018         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11019                         BC_SUPPORTS_RMMOD_CMD : 0;
11020
11021         boot_mode = SHMEM_RD(bp,
11022                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11023                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11024         switch (boot_mode) {
11025         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11026                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11027                 break;
11028         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11029                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11030                 break;
11031         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11032                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11033                 break;
11034         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11035                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11036                 break;
11037         }
11038
11039         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11040         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11041
11042         BNX2X_DEV_INFO("%sWoL capable\n",
11043                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11044
11045         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11046         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11047         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11048         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11049
11050         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11051                  val, val2, val3, val4);
11052 }
11053
11054 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11055 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11056
11057 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11058 {
11059         int pfid = BP_FUNC(bp);
11060         int igu_sb_id;
11061         u32 val;
11062         u8 fid, igu_sb_cnt = 0;
11063
11064         bp->igu_base_sb = 0xff;
11065         if (CHIP_INT_MODE_IS_BC(bp)) {
11066                 int vn = BP_VN(bp);
11067                 igu_sb_cnt = bp->igu_sb_cnt;
11068                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11069                         FP_SB_MAX_E1x;
11070
11071                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11072                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11073
11074                 return 0;
11075         }
11076
11077         /* IGU in normal mode - read CAM */
11078         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11079              igu_sb_id++) {
11080                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11081                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11082                         continue;
11083                 fid = IGU_FID(val);
11084                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11085                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11086                                 continue;
11087                         if (IGU_VEC(val) == 0)
11088                                 /* default status block */
11089                                 bp->igu_dsb_id = igu_sb_id;
11090                         else {
11091                                 if (bp->igu_base_sb == 0xff)
11092                                         bp->igu_base_sb = igu_sb_id;
11093                                 igu_sb_cnt++;
11094                         }
11095                 }
11096         }
11097
11098 #ifdef CONFIG_PCI_MSI
11099         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11100          * optional that number of CAM entries will not be equal to the value
11101          * advertised in PCI.
11102          * Driver should use the minimal value of both as the actual status
11103          * block count
11104          */
11105         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11106 #endif
11107
11108         if (igu_sb_cnt == 0) {
11109                 BNX2X_ERR("CAM configuration error\n");
11110                 return -EINVAL;
11111         }
11112
11113         return 0;
11114 }
11115
11116 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11117 {
11118         int cfg_size = 0, idx, port = BP_PORT(bp);
11119
11120         /* Aggregation of supported attributes of all external phys */
11121         bp->port.supported[0] = 0;
11122         bp->port.supported[1] = 0;
11123         switch (bp->link_params.num_phys) {
11124         case 1:
11125                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11126                 cfg_size = 1;
11127                 break;
11128         case 2:
11129                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11130                 cfg_size = 1;
11131                 break;
11132         case 3:
11133                 if (bp->link_params.multi_phy_config &
11134                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11135                         bp->port.supported[1] =
11136                                 bp->link_params.phy[EXT_PHY1].supported;
11137                         bp->port.supported[0] =
11138                                 bp->link_params.phy[EXT_PHY2].supported;
11139                 } else {
11140                         bp->port.supported[0] =
11141                                 bp->link_params.phy[EXT_PHY1].supported;
11142                         bp->port.supported[1] =
11143                                 bp->link_params.phy[EXT_PHY2].supported;
11144                 }
11145                 cfg_size = 2;
11146                 break;
11147         }
11148
11149         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11150                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11151                            SHMEM_RD(bp,
11152                            dev_info.port_hw_config[port].external_phy_config),
11153                            SHMEM_RD(bp,
11154                            dev_info.port_hw_config[port].external_phy_config2));
11155                         return;
11156         }
11157
11158         if (CHIP_IS_E3(bp))
11159                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11160         else {
11161                 switch (switch_cfg) {
11162                 case SWITCH_CFG_1G:
11163                         bp->port.phy_addr = REG_RD(
11164                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11165                         break;
11166                 case SWITCH_CFG_10G:
11167                         bp->port.phy_addr = REG_RD(
11168                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11169                         break;
11170                 default:
11171                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11172                                   bp->port.link_config[0]);
11173                         return;
11174                 }
11175         }
11176         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11177         /* mask what we support according to speed_cap_mask per configuration */
11178         for (idx = 0; idx < cfg_size; idx++) {
11179                 if (!(bp->link_params.speed_cap_mask[idx] &
11180                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11181                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11182
11183                 if (!(bp->link_params.speed_cap_mask[idx] &
11184                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11185                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11186
11187                 if (!(bp->link_params.speed_cap_mask[idx] &
11188                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11189                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11190
11191                 if (!(bp->link_params.speed_cap_mask[idx] &
11192                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11193                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11194
11195                 if (!(bp->link_params.speed_cap_mask[idx] &
11196                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11197                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11198                                                      SUPPORTED_1000baseT_Full);
11199
11200                 if (!(bp->link_params.speed_cap_mask[idx] &
11201                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11202                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11203
11204                 if (!(bp->link_params.speed_cap_mask[idx] &
11205                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11206                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11207
11208                 if (!(bp->link_params.speed_cap_mask[idx] &
11209                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11210                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11211         }
11212
11213         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11214                        bp->port.supported[1]);
11215 }
11216
11217 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11218 {
11219         u32 link_config, idx, cfg_size = 0;
11220         bp->port.advertising[0] = 0;
11221         bp->port.advertising[1] = 0;
11222         switch (bp->link_params.num_phys) {
11223         case 1:
11224         case 2:
11225                 cfg_size = 1;
11226                 break;
11227         case 3:
11228                 cfg_size = 2;
11229                 break;
11230         }
11231         for (idx = 0; idx < cfg_size; idx++) {
11232                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11233                 link_config = bp->port.link_config[idx];
11234                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11235                 case PORT_FEATURE_LINK_SPEED_AUTO:
11236                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11237                                 bp->link_params.req_line_speed[idx] =
11238                                         SPEED_AUTO_NEG;
11239                                 bp->port.advertising[idx] |=
11240                                         bp->port.supported[idx];
11241                                 if (bp->link_params.phy[EXT_PHY1].type ==
11242                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11243                                         bp->port.advertising[idx] |=
11244                                         (SUPPORTED_100baseT_Half |
11245                                          SUPPORTED_100baseT_Full);
11246                         } else {
11247                                 /* force 10G, no AN */
11248                                 bp->link_params.req_line_speed[idx] =
11249                                         SPEED_10000;
11250                                 bp->port.advertising[idx] |=
11251                                         (ADVERTISED_10000baseT_Full |
11252                                          ADVERTISED_FIBRE);
11253                                 continue;
11254                         }
11255                         break;
11256
11257                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11258                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11259                                 bp->link_params.req_line_speed[idx] =
11260                                         SPEED_10;
11261                                 bp->port.advertising[idx] |=
11262                                         (ADVERTISED_10baseT_Full |
11263                                          ADVERTISED_TP);
11264                         } else {
11265                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11266                                             link_config,
11267                                     bp->link_params.speed_cap_mask[idx]);
11268                                 return;
11269                         }
11270                         break;
11271
11272                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11273                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11274                                 bp->link_params.req_line_speed[idx] =
11275                                         SPEED_10;
11276                                 bp->link_params.req_duplex[idx] =
11277                                         DUPLEX_HALF;
11278                                 bp->port.advertising[idx] |=
11279                                         (ADVERTISED_10baseT_Half |
11280                                          ADVERTISED_TP);
11281                         } else {
11282                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11283                                             link_config,
11284                                           bp->link_params.speed_cap_mask[idx]);
11285                                 return;
11286                         }
11287                         break;
11288
11289                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11290                         if (bp->port.supported[idx] &
11291                             SUPPORTED_100baseT_Full) {
11292                                 bp->link_params.req_line_speed[idx] =
11293                                         SPEED_100;
11294                                 bp->port.advertising[idx] |=
11295                                         (ADVERTISED_100baseT_Full |
11296                                          ADVERTISED_TP);
11297                         } else {
11298                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11299                                             link_config,
11300                                           bp->link_params.speed_cap_mask[idx]);
11301                                 return;
11302                         }
11303                         break;
11304
11305                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11306                         if (bp->port.supported[idx] &
11307                             SUPPORTED_100baseT_Half) {
11308                                 bp->link_params.req_line_speed[idx] =
11309                                                                 SPEED_100;
11310                                 bp->link_params.req_duplex[idx] =
11311                                                                 DUPLEX_HALF;
11312                                 bp->port.advertising[idx] |=
11313                                         (ADVERTISED_100baseT_Half |
11314                                          ADVERTISED_TP);
11315                         } else {
11316                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11317                                     link_config,
11318                                     bp->link_params.speed_cap_mask[idx]);
11319                                 return;
11320                         }
11321                         break;
11322
11323                 case PORT_FEATURE_LINK_SPEED_1G:
11324                         if (bp->port.supported[idx] &
11325                             SUPPORTED_1000baseT_Full) {
11326                                 bp->link_params.req_line_speed[idx] =
11327                                         SPEED_1000;
11328                                 bp->port.advertising[idx] |=
11329                                         (ADVERTISED_1000baseT_Full |
11330                                          ADVERTISED_TP);
11331                         } else if (bp->port.supported[idx] &
11332                                    SUPPORTED_1000baseKX_Full) {
11333                                 bp->link_params.req_line_speed[idx] =
11334                                         SPEED_1000;
11335                                 bp->port.advertising[idx] |=
11336                                         ADVERTISED_1000baseKX_Full;
11337                         } else {
11338                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11339                                     link_config,
11340                                     bp->link_params.speed_cap_mask[idx]);
11341                                 return;
11342                         }
11343                         break;
11344
11345                 case PORT_FEATURE_LINK_SPEED_2_5G:
11346                         if (bp->port.supported[idx] &
11347                             SUPPORTED_2500baseX_Full) {
11348                                 bp->link_params.req_line_speed[idx] =
11349                                         SPEED_2500;
11350                                 bp->port.advertising[idx] |=
11351                                         (ADVERTISED_2500baseX_Full |
11352                                                 ADVERTISED_TP);
11353                         } else {
11354                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11355                                     link_config,
11356                                     bp->link_params.speed_cap_mask[idx]);
11357                                 return;
11358                         }
11359                         break;
11360
11361                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11362                         if (bp->port.supported[idx] &
11363                             SUPPORTED_10000baseT_Full) {
11364                                 bp->link_params.req_line_speed[idx] =
11365                                         SPEED_10000;
11366                                 bp->port.advertising[idx] |=
11367                                         (ADVERTISED_10000baseT_Full |
11368                                                 ADVERTISED_FIBRE);
11369                         } else if (bp->port.supported[idx] &
11370                                    SUPPORTED_10000baseKR_Full) {
11371                                 bp->link_params.req_line_speed[idx] =
11372                                         SPEED_10000;
11373                                 bp->port.advertising[idx] |=
11374                                         (ADVERTISED_10000baseKR_Full |
11375                                                 ADVERTISED_FIBRE);
11376                         } else {
11377                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11378                                     link_config,
11379                                     bp->link_params.speed_cap_mask[idx]);
11380                                 return;
11381                         }
11382                         break;
11383                 case PORT_FEATURE_LINK_SPEED_20G:
11384                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11385
11386                         break;
11387                 default:
11388                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11389                                   link_config);
11390                                 bp->link_params.req_line_speed[idx] =
11391                                                         SPEED_AUTO_NEG;
11392                                 bp->port.advertising[idx] =
11393                                                 bp->port.supported[idx];
11394                         break;
11395                 }
11396
11397                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11398                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11399                 if (bp->link_params.req_flow_ctrl[idx] ==
11400                     BNX2X_FLOW_CTRL_AUTO) {
11401                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11402                                 bp->link_params.req_flow_ctrl[idx] =
11403                                                         BNX2X_FLOW_CTRL_NONE;
11404                         else
11405                                 bnx2x_set_requested_fc(bp);
11406                 }
11407
11408                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11409                                bp->link_params.req_line_speed[idx],
11410                                bp->link_params.req_duplex[idx],
11411                                bp->link_params.req_flow_ctrl[idx],
11412                                bp->port.advertising[idx]);
11413         }
11414 }
11415
11416 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11417 {
11418         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11419         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11420         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11421         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11422 }
11423
11424 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11425 {
11426         int port = BP_PORT(bp);
11427         u32 config;
11428         u32 ext_phy_type, ext_phy_config, eee_mode;
11429
11430         bp->link_params.bp = bp;
11431         bp->link_params.port = port;
11432
11433         bp->link_params.lane_config =
11434                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11435
11436         bp->link_params.speed_cap_mask[0] =
11437                 SHMEM_RD(bp,
11438                          dev_info.port_hw_config[port].speed_capability_mask) &
11439                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11440         bp->link_params.speed_cap_mask[1] =
11441                 SHMEM_RD(bp,
11442                          dev_info.port_hw_config[port].speed_capability_mask2) &
11443                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11444         bp->port.link_config[0] =
11445                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11446
11447         bp->port.link_config[1] =
11448                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11449
11450         bp->link_params.multi_phy_config =
11451                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11452         /* If the device is capable of WoL, set the default state according
11453          * to the HW
11454          */
11455         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11456         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11457                    (config & PORT_FEATURE_WOL_ENABLED));
11458
11459         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11460             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11461                 bp->flags |= NO_ISCSI_FLAG;
11462         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11463             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11464                 bp->flags |= NO_FCOE_FLAG;
11465
11466         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11467                        bp->link_params.lane_config,
11468                        bp->link_params.speed_cap_mask[0],
11469                        bp->port.link_config[0]);
11470
11471         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11472                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11473         bnx2x_phy_probe(&bp->link_params);
11474         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11475
11476         bnx2x_link_settings_requested(bp);
11477
11478         /*
11479          * If connected directly, work with the internal PHY, otherwise, work
11480          * with the external PHY
11481          */
11482         ext_phy_config =
11483                 SHMEM_RD(bp,
11484                          dev_info.port_hw_config[port].external_phy_config);
11485         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11486         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11487                 bp->mdio.prtad = bp->port.phy_addr;
11488
11489         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11490                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11491                 bp->mdio.prtad =
11492                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11493
11494         /* Configure link feature according to nvram value */
11495         eee_mode = (((SHMEM_RD(bp, dev_info.
11496                       port_feature_config[port].eee_power_mode)) &
11497                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11498                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11499         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11500                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11501                                            EEE_MODE_ENABLE_LPI |
11502                                            EEE_MODE_OUTPUT_TIME;
11503         } else {
11504                 bp->link_params.eee_mode = 0;
11505         }
11506 }
11507
11508 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11509 {
11510         u32 no_flags = NO_ISCSI_FLAG;
11511         int port = BP_PORT(bp);
11512         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11513                                 drv_lic_key[port].max_iscsi_conn);
11514
11515         if (!CNIC_SUPPORT(bp)) {
11516                 bp->flags |= no_flags;
11517                 return;
11518         }
11519
11520         /* Get the number of maximum allowed iSCSI connections */
11521         bp->cnic_eth_dev.max_iscsi_conn =
11522                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11523                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11524
11525         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11526                        bp->cnic_eth_dev.max_iscsi_conn);
11527
11528         /*
11529          * If maximum allowed number of connections is zero -
11530          * disable the feature.
11531          */
11532         if (!bp->cnic_eth_dev.max_iscsi_conn)
11533                 bp->flags |= no_flags;
11534 }
11535
11536 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11537 {
11538         /* Port info */
11539         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11540                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11541         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11542                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11543
11544         /* Node info */
11545         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11546                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11547         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11548                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11549 }
11550
11551 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11552 {
11553         u8 count = 0;
11554
11555         if (IS_MF(bp)) {
11556                 u8 fid;
11557
11558                 /* iterate over absolute function ids for this path: */
11559                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11560                         if (IS_MF_SD(bp)) {
11561                                 u32 cfg = MF_CFG_RD(bp,
11562                                                     func_mf_config[fid].config);
11563
11564                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11565                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11566                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11567                                         count++;
11568                         } else {
11569                                 u32 cfg = MF_CFG_RD(bp,
11570                                                     func_ext_config[fid].
11571                                                                       func_cfg);
11572
11573                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11574                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11575                                         count++;
11576                         }
11577                 }
11578         } else { /* SF */
11579                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11580
11581                 for (port = 0; port < port_cnt; port++) {
11582                         u32 lic = SHMEM_RD(bp,
11583                                            drv_lic_key[port].max_fcoe_conn) ^
11584                                   FW_ENCODE_32BIT_PATTERN;
11585                         if (lic)
11586                                 count++;
11587                 }
11588         }
11589
11590         return count;
11591 }
11592
11593 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11594 {
11595         int port = BP_PORT(bp);
11596         int func = BP_ABS_FUNC(bp);
11597         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11598                                 drv_lic_key[port].max_fcoe_conn);
11599         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11600
11601         if (!CNIC_SUPPORT(bp)) {
11602                 bp->flags |= NO_FCOE_FLAG;
11603                 return;
11604         }
11605
11606         /* Get the number of maximum allowed FCoE connections */
11607         bp->cnic_eth_dev.max_fcoe_conn =
11608                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11609                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11610
11611         /* Calculate the number of maximum allowed FCoE tasks */
11612         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11613
11614         /* check if FCoE resources must be shared between different functions */
11615         if (num_fcoe_func)
11616                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11617
11618         /* Read the WWN: */
11619         if (!IS_MF(bp)) {
11620                 /* Port info */
11621                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11622                         SHMEM_RD(bp,
11623                                  dev_info.port_hw_config[port].
11624                                  fcoe_wwn_port_name_upper);
11625                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11626                         SHMEM_RD(bp,
11627                                  dev_info.port_hw_config[port].
11628                                  fcoe_wwn_port_name_lower);
11629
11630                 /* Node info */
11631                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11632                         SHMEM_RD(bp,
11633                                  dev_info.port_hw_config[port].
11634                                  fcoe_wwn_node_name_upper);
11635                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11636                         SHMEM_RD(bp,
11637                                  dev_info.port_hw_config[port].
11638                                  fcoe_wwn_node_name_lower);
11639         } else if (!IS_MF_SD(bp)) {
11640                 /* Read the WWN info only if the FCoE feature is enabled for
11641                  * this function.
11642                  */
11643                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11644                         bnx2x_get_ext_wwn_info(bp, func);
11645         } else {
11646                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11647                         bnx2x_get_ext_wwn_info(bp, func);
11648         }
11649
11650         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11651
11652         /*
11653          * If maximum allowed number of connections is zero -
11654          * disable the feature.
11655          */
11656         if (!bp->cnic_eth_dev.max_fcoe_conn)
11657                 bp->flags |= NO_FCOE_FLAG;
11658 }
11659
11660 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11661 {
11662         /*
11663          * iSCSI may be dynamically disabled but reading
11664          * info here we will decrease memory usage by driver
11665          * if the feature is disabled for good
11666          */
11667         bnx2x_get_iscsi_info(bp);
11668         bnx2x_get_fcoe_info(bp);
11669 }
11670
11671 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11672 {
11673         u32 val, val2;
11674         int func = BP_ABS_FUNC(bp);
11675         int port = BP_PORT(bp);
11676         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11677         u8 *fip_mac = bp->fip_mac;
11678
11679         if (IS_MF(bp)) {
11680                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11681                  * FCoE MAC then the appropriate feature should be disabled.
11682                  * In non SD mode features configuration comes from struct
11683                  * func_ext_config.
11684                  */
11685                 if (!IS_MF_SD(bp)) {
11686                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11687                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11688                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11689                                                  iscsi_mac_addr_upper);
11690                                 val = MF_CFG_RD(bp, func_ext_config[func].
11691                                                 iscsi_mac_addr_lower);
11692                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11693                                 BNX2X_DEV_INFO
11694                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11695                         } else {
11696                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11697                         }
11698
11699                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11700                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11701                                                  fcoe_mac_addr_upper);
11702                                 val = MF_CFG_RD(bp, func_ext_config[func].
11703                                                 fcoe_mac_addr_lower);
11704                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11705                                 BNX2X_DEV_INFO
11706                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11707                         } else {
11708                                 bp->flags |= NO_FCOE_FLAG;
11709                         }
11710
11711                         bp->mf_ext_config = cfg;
11712
11713                 } else { /* SD MODE */
11714                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11715                                 /* use primary mac as iscsi mac */
11716                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11717
11718                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11719                                 BNX2X_DEV_INFO
11720                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11721                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11722                                 /* use primary mac as fip mac */
11723                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11724                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11725                                 BNX2X_DEV_INFO
11726                                         ("Read FIP MAC: %pM\n", fip_mac);
11727                         }
11728                 }
11729
11730                 /* If this is a storage-only interface, use SAN mac as
11731                  * primary MAC. Notice that for SD this is already the case,
11732                  * as the SAN mac was copied from the primary MAC.
11733                  */
11734                 if (IS_MF_FCOE_AFEX(bp))
11735                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11736         } else {
11737                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11738                                 iscsi_mac_upper);
11739                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11740                                iscsi_mac_lower);
11741                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11742
11743                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11744                                 fcoe_fip_mac_upper);
11745                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11746                                fcoe_fip_mac_lower);
11747                 bnx2x_set_mac_buf(fip_mac, val, val2);
11748         }
11749
11750         /* Disable iSCSI OOO if MAC configuration is invalid. */
11751         if (!is_valid_ether_addr(iscsi_mac)) {
11752                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11753                 eth_zero_addr(iscsi_mac);
11754         }
11755
11756         /* Disable FCoE if MAC configuration is invalid. */
11757         if (!is_valid_ether_addr(fip_mac)) {
11758                 bp->flags |= NO_FCOE_FLAG;
11759                 eth_zero_addr(bp->fip_mac);
11760         }
11761 }
11762
11763 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11764 {
11765         u32 val, val2;
11766         int func = BP_ABS_FUNC(bp);
11767         int port = BP_PORT(bp);
11768
11769         /* Zero primary MAC configuration */
11770         eth_zero_addr(bp->dev->dev_addr);
11771
11772         if (BP_NOMCP(bp)) {
11773                 BNX2X_ERROR("warning: random MAC workaround active\n");
11774                 eth_hw_addr_random(bp->dev);
11775         } else if (IS_MF(bp)) {
11776                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11777                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11778                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11779                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11780                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11781
11782                 if (CNIC_SUPPORT(bp))
11783                         bnx2x_get_cnic_mac_hwinfo(bp);
11784         } else {
11785                 /* in SF read MACs from port configuration */
11786                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11787                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11788                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11789
11790                 if (CNIC_SUPPORT(bp))
11791                         bnx2x_get_cnic_mac_hwinfo(bp);
11792         }
11793
11794         if (!BP_NOMCP(bp)) {
11795                 /* Read physical port identifier from shmem */
11796                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11797                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11798                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11799                 bp->flags |= HAS_PHYS_PORT_ID;
11800         }
11801
11802         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11803
11804         if (!is_valid_ether_addr(bp->dev->dev_addr))
11805                 dev_err(&bp->pdev->dev,
11806                         "bad Ethernet MAC address configuration: %pM\n"
11807                         "change it manually before bringing up the appropriate network interface\n",
11808                         bp->dev->dev_addr);
11809 }
11810
11811 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11812 {
11813         int tmp;
11814         u32 cfg;
11815
11816         if (IS_VF(bp))
11817                 return false;
11818
11819         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11820                 /* Take function: tmp = func */
11821                 tmp = BP_ABS_FUNC(bp);
11822                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11823                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11824         } else {
11825                 /* Take port: tmp = port */
11826                 tmp = BP_PORT(bp);
11827                 cfg = SHMEM_RD(bp,
11828                                dev_info.port_hw_config[tmp].generic_features);
11829                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11830         }
11831         return cfg;
11832 }
11833
11834 static void validate_set_si_mode(struct bnx2x *bp)
11835 {
11836         u8 func = BP_ABS_FUNC(bp);
11837         u32 val;
11838
11839         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11840
11841         /* check for legal mac (upper bytes) */
11842         if (val != 0xffff) {
11843                 bp->mf_mode = MULTI_FUNCTION_SI;
11844                 bp->mf_config[BP_VN(bp)] =
11845                         MF_CFG_RD(bp, func_mf_config[func].config);
11846         } else
11847                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11848 }
11849
11850 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11851 {
11852         int /*abs*/func = BP_ABS_FUNC(bp);
11853         int vn, mfw_vn;
11854         u32 val = 0, val2 = 0;
11855         int rc = 0;
11856
11857         /* Validate that chip access is feasible */
11858         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11859                 dev_err(&bp->pdev->dev,
11860                         "Chip read returns all Fs. Preventing probe from continuing\n");
11861                 return -EINVAL;
11862         }
11863
11864         bnx2x_get_common_hwinfo(bp);
11865
11866         /*
11867          * initialize IGU parameters
11868          */
11869         if (CHIP_IS_E1x(bp)) {
11870                 bp->common.int_block = INT_BLOCK_HC;
11871
11872                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11873                 bp->igu_base_sb = 0;
11874         } else {
11875                 bp->common.int_block = INT_BLOCK_IGU;
11876
11877                 /* do not allow device reset during IGU info processing */
11878                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11879
11880                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11881
11882                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11883                         int tout = 5000;
11884
11885                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11886
11887                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11888                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11889                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11890
11891                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11892                                 tout--;
11893                                 usleep_range(1000, 2000);
11894                         }
11895
11896                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11897                                 dev_err(&bp->pdev->dev,
11898                                         "FORCING Normal Mode failed!!!\n");
11899                                 bnx2x_release_hw_lock(bp,
11900                                                       HW_LOCK_RESOURCE_RESET);
11901                                 return -EPERM;
11902                         }
11903                 }
11904
11905                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11906                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11907                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11908                 } else
11909                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11910
11911                 rc = bnx2x_get_igu_cam_info(bp);
11912                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11913                 if (rc)
11914                         return rc;
11915         }
11916
11917         /*
11918          * set base FW non-default (fast path) status block id, this value is
11919          * used to initialize the fw_sb_id saved on the fp/queue structure to
11920          * determine the id used by the FW.
11921          */
11922         if (CHIP_IS_E1x(bp))
11923                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11924         else /*
11925               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11926               * the same queue are indicated on the same IGU SB). So we prefer
11927               * FW and IGU SBs to be the same value.
11928               */
11929                 bp->base_fw_ndsb = bp->igu_base_sb;
11930
11931         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11932                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11933                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11934
11935         /*
11936          * Initialize MF configuration
11937          */
11938
11939         bp->mf_ov = 0;
11940         bp->mf_mode = 0;
11941         bp->mf_sub_mode = 0;
11942         vn = BP_VN(bp);
11943         mfw_vn = BP_FW_MB_IDX(bp);
11944
11945         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11946                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11947                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11948                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11949
11950                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11951                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11952                 else
11953                         bp->common.mf_cfg_base = bp->common.shmem_base +
11954                                 offsetof(struct shmem_region, func_mb) +
11955                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11956                 /*
11957                  * get mf configuration:
11958                  * 1. Existence of MF configuration
11959                  * 2. MAC address must be legal (check only upper bytes)
11960                  *    for  Switch-Independent mode;
11961                  *    OVLAN must be legal for Switch-Dependent mode
11962                  * 3. SF_MODE configures specific MF mode
11963                  */
11964                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11965                         /* get mf configuration */
11966                         val = SHMEM_RD(bp,
11967                                        dev_info.shared_feature_config.config);
11968                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11969
11970                         switch (val) {
11971                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11972                                 validate_set_si_mode(bp);
11973                                 break;
11974                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11975                                 if ((!CHIP_IS_E1x(bp)) &&
11976                                     (MF_CFG_RD(bp, func_mf_config[func].
11977                                                mac_upper) != 0xffff) &&
11978                                     (SHMEM2_HAS(bp,
11979                                                 afex_driver_support))) {
11980                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11981                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11982                                                 func_mf_config[func].config);
11983                                 } else {
11984                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11985                                 }
11986                                 break;
11987                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11988                                 /* get OV configuration */
11989                                 val = MF_CFG_RD(bp,
11990                                         func_mf_config[FUNC_0].e1hov_tag);
11991                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11992
11993                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11994                                         bp->mf_mode = MULTI_FUNCTION_SD;
11995                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11996                                                 func_mf_config[func].config);
11997                                 } else
11998                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11999                                 break;
12000                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12001                                 bp->mf_mode = MULTI_FUNCTION_SD;
12002                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12003                                 bp->mf_config[vn] =
12004                                         MF_CFG_RD(bp,
12005                                                   func_mf_config[func].config);
12006
12007                                 if (SHMEM2_HAS(bp, mtu_size)) {
12008                                         int mtu_idx = BP_FW_MB_IDX(bp);
12009                                         u16 mtu_size;
12010                                         u32 mtu;
12011
12012                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12013                                         mtu_size = (u16)mtu;
12014                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12015                                            mtu_size, mtu);
12016
12017                                         /* if valid: update device mtu */
12018                                         if (((mtu_size + ETH_HLEN) >=
12019                                              ETH_MIN_PACKET_SIZE) &&
12020                                             (mtu_size <=
12021                                              ETH_MAX_JUMBO_PACKET_SIZE))
12022                                                 bp->dev->mtu = mtu_size;
12023                                 }
12024                                 break;
12025                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12026                                 bp->mf_mode = MULTI_FUNCTION_SD;
12027                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12028                                 bp->mf_config[vn] =
12029                                         MF_CFG_RD(bp,
12030                                                   func_mf_config[func].config);
12031                                 break;
12032                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12033                                 bp->mf_config[vn] = 0;
12034                                 break;
12035                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12036                                 val2 = SHMEM_RD(bp,
12037                                         dev_info.shared_hw_config.config_3);
12038                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12039                                 switch (val2) {
12040                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12041                                         validate_set_si_mode(bp);
12042                                         bp->mf_sub_mode =
12043                                                         SUB_MF_MODE_NPAR1_DOT_5;
12044                                         break;
12045                                 default:
12046                                         /* Unknown configuration */
12047                                         bp->mf_config[vn] = 0;
12048                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12049                                                        val);
12050                                 }
12051                                 break;
12052                         default:
12053                                 /* Unknown configuration: reset mf_config */
12054                                 bp->mf_config[vn] = 0;
12055                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12056                         }
12057                 }
12058
12059                 BNX2X_DEV_INFO("%s function mode\n",
12060                                IS_MF(bp) ? "multi" : "single");
12061
12062                 switch (bp->mf_mode) {
12063                 case MULTI_FUNCTION_SD:
12064                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12065                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12066                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12067                                 bp->mf_ov = val;
12068                                 bp->path_has_ovlan = true;
12069
12070                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12071                                                func, bp->mf_ov, bp->mf_ov);
12072                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12073                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12074                                 dev_err(&bp->pdev->dev,
12075                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12076                                         func);
12077                                 bp->path_has_ovlan = true;
12078                         } else {
12079                                 dev_err(&bp->pdev->dev,
12080                                         "No valid MF OV for func %d, aborting\n",
12081                                         func);
12082                                 return -EPERM;
12083                         }
12084                         break;
12085                 case MULTI_FUNCTION_AFEX:
12086                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12087                         break;
12088                 case MULTI_FUNCTION_SI:
12089                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12090                                        func);
12091                         break;
12092                 default:
12093                         if (vn) {
12094                                 dev_err(&bp->pdev->dev,
12095                                         "VN %d is in a single function mode, aborting\n",
12096                                         vn);
12097                                 return -EPERM;
12098                         }
12099                         break;
12100                 }
12101
12102                 /* check if other port on the path needs ovlan:
12103                  * Since MF configuration is shared between ports
12104                  * Possible mixed modes are only
12105                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12106                  */
12107                 if (CHIP_MODE_IS_4_PORT(bp) &&
12108                     !bp->path_has_ovlan &&
12109                     !IS_MF(bp) &&
12110                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12111                         u8 other_port = !BP_PORT(bp);
12112                         u8 other_func = BP_PATH(bp) + 2*other_port;
12113                         val = MF_CFG_RD(bp,
12114                                         func_mf_config[other_func].e1hov_tag);
12115                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12116                                 bp->path_has_ovlan = true;
12117                 }
12118         }
12119
12120         /* adjust igu_sb_cnt to MF for E1H */
12121         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12122                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12123
12124         /* port info */
12125         bnx2x_get_port_hwinfo(bp);
12126
12127         /* Get MAC addresses */
12128         bnx2x_get_mac_hwinfo(bp);
12129
12130         bnx2x_get_cnic_info(bp);
12131
12132         return rc;
12133 }
12134
12135 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12136 {
12137         int cnt, i, block_end, rodi;
12138         char vpd_start[BNX2X_VPD_LEN+1];
12139         char str_id_reg[VENDOR_ID_LEN+1];
12140         char str_id_cap[VENDOR_ID_LEN+1];
12141         char *vpd_data;
12142         char *vpd_extended_data = NULL;
12143         u8 len;
12144
12145         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12146         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12147
12148         if (cnt < BNX2X_VPD_LEN)
12149                 goto out_not_found;
12150
12151         /* VPD RO tag should be first tag after identifier string, hence
12152          * we should be able to find it in first BNX2X_VPD_LEN chars
12153          */
12154         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12155                              PCI_VPD_LRDT_RO_DATA);
12156         if (i < 0)
12157                 goto out_not_found;
12158
12159         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12160                     pci_vpd_lrdt_size(&vpd_start[i]);
12161
12162         i += PCI_VPD_LRDT_TAG_SIZE;
12163
12164         if (block_end > BNX2X_VPD_LEN) {
12165                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12166                 if (vpd_extended_data  == NULL)
12167                         goto out_not_found;
12168
12169                 /* read rest of vpd image into vpd_extended_data */
12170                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12171                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12172                                    block_end - BNX2X_VPD_LEN,
12173                                    vpd_extended_data + BNX2X_VPD_LEN);
12174                 if (cnt < (block_end - BNX2X_VPD_LEN))
12175                         goto out_not_found;
12176                 vpd_data = vpd_extended_data;
12177         } else
12178                 vpd_data = vpd_start;
12179
12180         /* now vpd_data holds full vpd content in both cases */
12181
12182         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12183                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12184         if (rodi < 0)
12185                 goto out_not_found;
12186
12187         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12188
12189         if (len != VENDOR_ID_LEN)
12190                 goto out_not_found;
12191
12192         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12193
12194         /* vendor specific info */
12195         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12196         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12197         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12198             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12199
12200                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12201                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12202                 if (rodi >= 0) {
12203                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12204
12205                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12206
12207                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12208                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12209                                 bp->fw_ver[len] = ' ';
12210                         }
12211                 }
12212                 kfree(vpd_extended_data);
12213                 return;
12214         }
12215 out_not_found:
12216         kfree(vpd_extended_data);
12217         return;
12218 }
12219
12220 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12221 {
12222         u32 flags = 0;
12223
12224         if (CHIP_REV_IS_FPGA(bp))
12225                 SET_FLAGS(flags, MODE_FPGA);
12226         else if (CHIP_REV_IS_EMUL(bp))
12227                 SET_FLAGS(flags, MODE_EMUL);
12228         else
12229                 SET_FLAGS(flags, MODE_ASIC);
12230
12231         if (CHIP_MODE_IS_4_PORT(bp))
12232                 SET_FLAGS(flags, MODE_PORT4);
12233         else
12234                 SET_FLAGS(flags, MODE_PORT2);
12235
12236         if (CHIP_IS_E2(bp))
12237                 SET_FLAGS(flags, MODE_E2);
12238         else if (CHIP_IS_E3(bp)) {
12239                 SET_FLAGS(flags, MODE_E3);
12240                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12241                         SET_FLAGS(flags, MODE_E3_A0);
12242                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12243                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12244         }
12245
12246         if (IS_MF(bp)) {
12247                 SET_FLAGS(flags, MODE_MF);
12248                 switch (bp->mf_mode) {
12249                 case MULTI_FUNCTION_SD:
12250                         SET_FLAGS(flags, MODE_MF_SD);
12251                         break;
12252                 case MULTI_FUNCTION_SI:
12253                         SET_FLAGS(flags, MODE_MF_SI);
12254                         break;
12255                 case MULTI_FUNCTION_AFEX:
12256                         SET_FLAGS(flags, MODE_MF_AFEX);
12257                         break;
12258                 }
12259         } else
12260                 SET_FLAGS(flags, MODE_SF);
12261
12262 #if defined(__LITTLE_ENDIAN)
12263         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12264 #else /*(__BIG_ENDIAN)*/
12265         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12266 #endif
12267         INIT_MODE_FLAGS(bp) = flags;
12268 }
12269
12270 static int bnx2x_init_bp(struct bnx2x *bp)
12271 {
12272         int func;
12273         int rc;
12274
12275         mutex_init(&bp->port.phy_mutex);
12276         mutex_init(&bp->fw_mb_mutex);
12277         mutex_init(&bp->drv_info_mutex);
12278         sema_init(&bp->stats_lock, 1);
12279         bp->drv_info_mng_owner = false;
12280         INIT_LIST_HEAD(&bp->vlan_reg);
12281
12282         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12283         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12284         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12285         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12286         if (IS_PF(bp)) {
12287                 rc = bnx2x_get_hwinfo(bp);
12288                 if (rc)
12289                         return rc;
12290         } else {
12291                 eth_zero_addr(bp->dev->dev_addr);
12292         }
12293
12294         bnx2x_set_modes_bitmap(bp);
12295
12296         rc = bnx2x_alloc_mem_bp(bp);
12297         if (rc)
12298                 return rc;
12299
12300         bnx2x_read_fwinfo(bp);
12301
12302         func = BP_FUNC(bp);
12303
12304         /* need to reset chip if undi was active */
12305         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12306                 /* init fw_seq */
12307                 bp->fw_seq =
12308                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12309                                                         DRV_MSG_SEQ_NUMBER_MASK;
12310                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12311
12312                 rc = bnx2x_prev_unload(bp);
12313                 if (rc) {
12314                         bnx2x_free_mem_bp(bp);
12315                         return rc;
12316                 }
12317         }
12318
12319         if (CHIP_REV_IS_FPGA(bp))
12320                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12321
12322         if (BP_NOMCP(bp) && (func == 0))
12323                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12324
12325         bp->disable_tpa = disable_tpa;
12326         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12327         /* Reduce memory usage in kdump environment by disabling TPA */
12328         bp->disable_tpa |= is_kdump_kernel();
12329
12330         /* Set TPA flags */
12331         if (bp->disable_tpa) {
12332                 bp->dev->hw_features &= ~NETIF_F_LRO;
12333                 bp->dev->features &= ~NETIF_F_LRO;
12334         }
12335
12336         if (CHIP_IS_E1(bp))
12337                 bp->dropless_fc = 0;
12338         else
12339                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12340
12341         bp->mrrs = mrrs;
12342
12343         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12344         if (IS_VF(bp))
12345                 bp->rx_ring_size = MAX_RX_AVAIL;
12346
12347         /* make sure that the numbers are in the right granularity */
12348         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12349         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12350
12351         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12352
12353         init_timer(&bp->timer);
12354         bp->timer.expires = jiffies + bp->current_interval;
12355         bp->timer.data = (unsigned long) bp;
12356         bp->timer.function = bnx2x_timer;
12357
12358         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12359             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12360             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12361             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12362                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12363                 bnx2x_dcbx_init_params(bp);
12364         } else {
12365                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12366         }
12367
12368         if (CHIP_IS_E1x(bp))
12369                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12370         else
12371                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12372
12373         /* multiple tx priority */
12374         if (IS_VF(bp))
12375                 bp->max_cos = 1;
12376         else if (CHIP_IS_E1x(bp))
12377                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12378         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12379                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12380         else if (CHIP_IS_E3B0(bp))
12381                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12382         else
12383                 BNX2X_ERR("unknown chip %x revision %x\n",
12384                           CHIP_NUM(bp), CHIP_REV(bp));
12385         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12386
12387         /* We need at least one default status block for slow-path events,
12388          * second status block for the L2 queue, and a third status block for
12389          * CNIC if supported.
12390          */
12391         if (IS_VF(bp))
12392                 bp->min_msix_vec_cnt = 1;
12393         else if (CNIC_SUPPORT(bp))
12394                 bp->min_msix_vec_cnt = 3;
12395         else /* PF w/o cnic */
12396                 bp->min_msix_vec_cnt = 2;
12397         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12398
12399         bp->dump_preset_idx = 1;
12400
12401         if (CHIP_IS_E3B0(bp))
12402                 bp->flags |= PTP_SUPPORTED;
12403
12404         return rc;
12405 }
12406
12407 /****************************************************************************
12408 * General service functions
12409 ****************************************************************************/
12410
12411 /*
12412  * net_device service functions
12413  */
12414
12415 /* called with rtnl_lock */
12416 static int bnx2x_open(struct net_device *dev)
12417 {
12418         struct bnx2x *bp = netdev_priv(dev);
12419         int rc;
12420
12421         bp->stats_init = true;
12422
12423         netif_carrier_off(dev);
12424
12425         bnx2x_set_power_state(bp, PCI_D0);
12426
12427         /* If parity had happen during the unload, then attentions
12428          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12429          * want the first function loaded on the current engine to
12430          * complete the recovery.
12431          * Parity recovery is only relevant for PF driver.
12432          */
12433         if (IS_PF(bp)) {
12434                 int other_engine = BP_PATH(bp) ? 0 : 1;
12435                 bool other_load_status, load_status;
12436                 bool global = false;
12437
12438                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12439                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12440                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12441                     bnx2x_chk_parity_attn(bp, &global, true)) {
12442                         do {
12443                                 /* If there are attentions and they are in a
12444                                  * global blocks, set the GLOBAL_RESET bit
12445                                  * regardless whether it will be this function
12446                                  * that will complete the recovery or not.
12447                                  */
12448                                 if (global)
12449                                         bnx2x_set_reset_global(bp);
12450
12451                                 /* Only the first function on the current
12452                                  * engine should try to recover in open. In case
12453                                  * of attentions in global blocks only the first
12454                                  * in the chip should try to recover.
12455                                  */
12456                                 if ((!load_status &&
12457                                      (!global || !other_load_status)) &&
12458                                       bnx2x_trylock_leader_lock(bp) &&
12459                                       !bnx2x_leader_reset(bp)) {
12460                                         netdev_info(bp->dev,
12461                                                     "Recovered in open\n");
12462                                         break;
12463                                 }
12464
12465                                 /* recovery has failed... */
12466                                 bnx2x_set_power_state(bp, PCI_D3hot);
12467                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12468
12469                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12470                                           "If you still see this message after a few retries then power cycle is required.\n");
12471
12472                                 return -EAGAIN;
12473                         } while (0);
12474                 }
12475         }
12476
12477         bp->recovery_state = BNX2X_RECOVERY_DONE;
12478         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12479         if (rc)
12480                 return rc;
12481
12482 #ifdef CONFIG_BNX2X_VXLAN
12483         if (IS_PF(bp))
12484                 vxlan_get_rx_port(dev);
12485 #endif
12486
12487         return 0;
12488 }
12489
12490 /* called with rtnl_lock */
12491 static int bnx2x_close(struct net_device *dev)
12492 {
12493         struct bnx2x *bp = netdev_priv(dev);
12494
12495         /* Unload the driver, release IRQs */
12496         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12497
12498         return 0;
12499 }
12500
12501 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12502                                       struct bnx2x_mcast_ramrod_params *p)
12503 {
12504         int mc_count = netdev_mc_count(bp->dev);
12505         struct bnx2x_mcast_list_elem *mc_mac =
12506                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12507         struct netdev_hw_addr *ha;
12508
12509         if (!mc_mac)
12510                 return -ENOMEM;
12511
12512         INIT_LIST_HEAD(&p->mcast_list);
12513
12514         netdev_for_each_mc_addr(ha, bp->dev) {
12515                 mc_mac->mac = bnx2x_mc_addr(ha);
12516                 list_add_tail(&mc_mac->link, &p->mcast_list);
12517                 mc_mac++;
12518         }
12519
12520         p->mcast_list_len = mc_count;
12521
12522         return 0;
12523 }
12524
12525 static void bnx2x_free_mcast_macs_list(
12526         struct bnx2x_mcast_ramrod_params *p)
12527 {
12528         struct bnx2x_mcast_list_elem *mc_mac =
12529                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12530                                  link);
12531
12532         WARN_ON(!mc_mac);
12533         kfree(mc_mac);
12534 }
12535
12536 /**
12537  * bnx2x_set_uc_list - configure a new unicast MACs list.
12538  *
12539  * @bp: driver handle
12540  *
12541  * We will use zero (0) as a MAC type for these MACs.
12542  */
12543 static int bnx2x_set_uc_list(struct bnx2x *bp)
12544 {
12545         int rc;
12546         struct net_device *dev = bp->dev;
12547         struct netdev_hw_addr *ha;
12548         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12549         unsigned long ramrod_flags = 0;
12550
12551         /* First schedule a cleanup up of old configuration */
12552         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12553         if (rc < 0) {
12554                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12555                 return rc;
12556         }
12557
12558         netdev_for_each_uc_addr(ha, dev) {
12559                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12560                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12561                 if (rc == -EEXIST) {
12562                         DP(BNX2X_MSG_SP,
12563                            "Failed to schedule ADD operations: %d\n", rc);
12564                         /* do not treat adding same MAC as error */
12565                         rc = 0;
12566
12567                 } else if (rc < 0) {
12568
12569                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12570                                   rc);
12571                         return rc;
12572                 }
12573         }
12574
12575         /* Execute the pending commands */
12576         __set_bit(RAMROD_CONT, &ramrod_flags);
12577         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12578                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12579 }
12580
12581 static int bnx2x_set_mc_list(struct bnx2x *bp)
12582 {
12583         struct net_device *dev = bp->dev;
12584         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12585         int rc = 0;
12586
12587         rparam.mcast_obj = &bp->mcast_obj;
12588
12589         /* first, clear all configured multicast MACs */
12590         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12591         if (rc < 0) {
12592                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12593                 return rc;
12594         }
12595
12596         /* then, configure a new MACs list */
12597         if (netdev_mc_count(dev)) {
12598                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12599                 if (rc) {
12600                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12601                                   rc);
12602                         return rc;
12603                 }
12604
12605                 /* Now add the new MACs */
12606                 rc = bnx2x_config_mcast(bp, &rparam,
12607                                         BNX2X_MCAST_CMD_ADD);
12608                 if (rc < 0)
12609                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12610                                   rc);
12611
12612                 bnx2x_free_mcast_macs_list(&rparam);
12613         }
12614
12615         return rc;
12616 }
12617
12618 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12619 static void bnx2x_set_rx_mode(struct net_device *dev)
12620 {
12621         struct bnx2x *bp = netdev_priv(dev);
12622
12623         if (bp->state != BNX2X_STATE_OPEN) {
12624                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12625                 return;
12626         } else {
12627                 /* Schedule an SP task to handle rest of change */
12628                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12629                                        NETIF_MSG_IFUP);
12630         }
12631 }
12632
12633 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12634 {
12635         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12636
12637         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12638
12639         netif_addr_lock_bh(bp->dev);
12640
12641         if (bp->dev->flags & IFF_PROMISC) {
12642                 rx_mode = BNX2X_RX_MODE_PROMISC;
12643         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12644                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12645                     CHIP_IS_E1(bp))) {
12646                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12647         } else {
12648                 if (IS_PF(bp)) {
12649                         /* some multicasts */
12650                         if (bnx2x_set_mc_list(bp) < 0)
12651                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12652
12653                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12654                         netif_addr_unlock_bh(bp->dev);
12655                         if (bnx2x_set_uc_list(bp) < 0)
12656                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12657                         netif_addr_lock_bh(bp->dev);
12658                 } else {
12659                         /* configuring mcast to a vf involves sleeping (when we
12660                          * wait for the pf's response).
12661                          */
12662                         bnx2x_schedule_sp_rtnl(bp,
12663                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12664                 }
12665         }
12666
12667         bp->rx_mode = rx_mode;
12668         /* handle ISCSI SD mode */
12669         if (IS_MF_ISCSI_ONLY(bp))
12670                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12671
12672         /* Schedule the rx_mode command */
12673         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12674                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12675                 netif_addr_unlock_bh(bp->dev);
12676                 return;
12677         }
12678
12679         if (IS_PF(bp)) {
12680                 bnx2x_set_storm_rx_mode(bp);
12681                 netif_addr_unlock_bh(bp->dev);
12682         } else {
12683                 /* VF will need to request the PF to make this change, and so
12684                  * the VF needs to release the bottom-half lock prior to the
12685                  * request (as it will likely require sleep on the VF side)
12686                  */
12687                 netif_addr_unlock_bh(bp->dev);
12688                 bnx2x_vfpf_storm_rx_mode(bp);
12689         }
12690 }
12691
12692 /* called with rtnl_lock */
12693 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12694                            int devad, u16 addr)
12695 {
12696         struct bnx2x *bp = netdev_priv(netdev);
12697         u16 value;
12698         int rc;
12699
12700         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12701            prtad, devad, addr);
12702
12703         /* The HW expects different devad if CL22 is used */
12704         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12705
12706         bnx2x_acquire_phy_lock(bp);
12707         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12708         bnx2x_release_phy_lock(bp);
12709         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12710
12711         if (!rc)
12712                 rc = value;
12713         return rc;
12714 }
12715
12716 /* called with rtnl_lock */
12717 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12718                             u16 addr, u16 value)
12719 {
12720         struct bnx2x *bp = netdev_priv(netdev);
12721         int rc;
12722
12723         DP(NETIF_MSG_LINK,
12724            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12725            prtad, devad, addr, value);
12726
12727         /* The HW expects different devad if CL22 is used */
12728         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12729
12730         bnx2x_acquire_phy_lock(bp);
12731         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12732         bnx2x_release_phy_lock(bp);
12733         return rc;
12734 }
12735
12736 /* called with rtnl_lock */
12737 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12738 {
12739         struct bnx2x *bp = netdev_priv(dev);
12740         struct mii_ioctl_data *mdio = if_mii(ifr);
12741
12742         if (!netif_running(dev))
12743                 return -EAGAIN;
12744
12745         switch (cmd) {
12746         case SIOCSHWTSTAMP:
12747                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12748         default:
12749                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12750                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12751                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12752         }
12753 }
12754
12755 #ifdef CONFIG_NET_POLL_CONTROLLER
12756 static void poll_bnx2x(struct net_device *dev)
12757 {
12758         struct bnx2x *bp = netdev_priv(dev);
12759         int i;
12760
12761         for_each_eth_queue(bp, i) {
12762                 struct bnx2x_fastpath *fp = &bp->fp[i];
12763                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12764         }
12765 }
12766 #endif
12767
12768 static int bnx2x_validate_addr(struct net_device *dev)
12769 {
12770         struct bnx2x *bp = netdev_priv(dev);
12771
12772         /* query the bulletin board for mac address configured by the PF */
12773         if (IS_VF(bp))
12774                 bnx2x_sample_bulletin(bp);
12775
12776         if (!is_valid_ether_addr(dev->dev_addr)) {
12777                 BNX2X_ERR("Non-valid Ethernet address\n");
12778                 return -EADDRNOTAVAIL;
12779         }
12780         return 0;
12781 }
12782
12783 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12784                                   struct netdev_phys_item_id *ppid)
12785 {
12786         struct bnx2x *bp = netdev_priv(netdev);
12787
12788         if (!(bp->flags & HAS_PHYS_PORT_ID))
12789                 return -EOPNOTSUPP;
12790
12791         ppid->id_len = sizeof(bp->phys_port_id);
12792         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12793
12794         return 0;
12795 }
12796
12797 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12798                                               struct net_device *dev,
12799                                               netdev_features_t features)
12800 {
12801         features = vlan_features_check(skb, features);
12802         return vxlan_features_check(skb, features);
12803 }
12804
12805 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12806 {
12807         int rc;
12808
12809         if (IS_PF(bp)) {
12810                 unsigned long ramrod_flags = 0;
12811
12812                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12813                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12814                                         add, &ramrod_flags);
12815         } else {
12816                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12817         }
12818
12819         return rc;
12820 }
12821
12822 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12823 {
12824         struct bnx2x_vlan_entry *vlan;
12825         int rc = 0;
12826
12827         if (!bp->vlan_cnt) {
12828                 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12829                 return 0;
12830         }
12831
12832         list_for_each_entry(vlan, &bp->vlan_reg, link) {
12833                 /* Prepare for cleanup in case of errors */
12834                 if (rc) {
12835                         vlan->hw = false;
12836                         continue;
12837                 }
12838
12839                 if (!vlan->hw)
12840                         continue;
12841
12842                 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12843
12844                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12845                 if (rc) {
12846                         BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12847                         vlan->hw = false;
12848                         rc = -EINVAL;
12849                         continue;
12850                 }
12851         }
12852
12853         return rc;
12854 }
12855
12856 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12857 {
12858         struct bnx2x *bp = netdev_priv(dev);
12859         struct bnx2x_vlan_entry *vlan;
12860         bool hw = false;
12861         int rc = 0;
12862
12863         if (!netif_running(bp->dev)) {
12864                 DP(NETIF_MSG_IFUP,
12865                    "Ignoring VLAN configuration the interface is down\n");
12866                 return -EFAULT;
12867         }
12868
12869         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12870
12871         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12872         if (!vlan)
12873                 return -ENOMEM;
12874
12875         bp->vlan_cnt++;
12876         if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12877                 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12878                 bp->accept_any_vlan = true;
12879                 if (IS_PF(bp))
12880                         bnx2x_set_rx_mode_inner(bp);
12881                 else
12882                         bnx2x_vfpf_storm_rx_mode(bp);
12883         } else if (bp->vlan_cnt <= bp->vlan_credit) {
12884                 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12885                 hw = true;
12886         }
12887
12888         vlan->vid = vid;
12889         vlan->hw = hw;
12890
12891         if (!rc) {
12892                 list_add(&vlan->link, &bp->vlan_reg);
12893         } else {
12894                 bp->vlan_cnt--;
12895                 kfree(vlan);
12896         }
12897
12898         DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12899
12900         return rc;
12901 }
12902
12903 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12904 {
12905         struct bnx2x *bp = netdev_priv(dev);
12906         struct bnx2x_vlan_entry *vlan;
12907         int rc = 0;
12908
12909         if (!netif_running(bp->dev)) {
12910                 DP(NETIF_MSG_IFUP,
12911                    "Ignoring VLAN configuration the interface is down\n");
12912                 return -EFAULT;
12913         }
12914
12915         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12916
12917         if (!bp->vlan_cnt) {
12918                 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12919                 return -EINVAL;
12920         }
12921
12922         list_for_each_entry(vlan, &bp->vlan_reg, link)
12923                 if (vlan->vid == vid)
12924                         break;
12925
12926         if (vlan->vid != vid) {
12927                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12928                 return -EINVAL;
12929         }
12930
12931         if (vlan->hw)
12932                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12933
12934         list_del(&vlan->link);
12935         kfree(vlan);
12936
12937         bp->vlan_cnt--;
12938
12939         if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12940                 /* Configure all non-configured entries */
12941                 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12942                         if (vlan->hw)
12943                                 continue;
12944
12945                         rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12946                         if (rc) {
12947                                 BNX2X_ERR("Unable to config VLAN %d\n",
12948                                           vlan->vid);
12949                                 continue;
12950                         }
12951                         DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
12952                            vlan->vid);
12953                         vlan->hw = true;
12954                 }
12955                 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
12956                 bp->accept_any_vlan = false;
12957                 if (IS_PF(bp))
12958                         bnx2x_set_rx_mode_inner(bp);
12959                 else
12960                         bnx2x_vfpf_storm_rx_mode(bp);
12961         }
12962
12963         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
12964
12965         return rc;
12966 }
12967
12968 static const struct net_device_ops bnx2x_netdev_ops = {
12969         .ndo_open               = bnx2x_open,
12970         .ndo_stop               = bnx2x_close,
12971         .ndo_start_xmit         = bnx2x_start_xmit,
12972         .ndo_select_queue       = bnx2x_select_queue,
12973         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12974         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12975         .ndo_validate_addr      = bnx2x_validate_addr,
12976         .ndo_do_ioctl           = bnx2x_ioctl,
12977         .ndo_change_mtu         = bnx2x_change_mtu,
12978         .ndo_fix_features       = bnx2x_fix_features,
12979         .ndo_set_features       = bnx2x_set_features,
12980         .ndo_tx_timeout         = bnx2x_tx_timeout,
12981         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
12982         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
12983 #ifdef CONFIG_NET_POLL_CONTROLLER
12984         .ndo_poll_controller    = poll_bnx2x,
12985 #endif
12986         .ndo_setup_tc           = bnx2x_setup_tc,
12987 #ifdef CONFIG_BNX2X_SRIOV
12988         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12989         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12990         .ndo_get_vf_config      = bnx2x_get_vf_config,
12991 #endif
12992 #ifdef NETDEV_FCOE_WWNN
12993         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12994 #endif
12995
12996 #ifdef CONFIG_NET_RX_BUSY_POLL
12997         .ndo_busy_poll          = bnx2x_low_latency_recv,
12998 #endif
12999         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13000         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13001         .ndo_features_check     = bnx2x_features_check,
13002 #ifdef CONFIG_BNX2X_VXLAN
13003         .ndo_add_vxlan_port     = bnx2x_add_vxlan_port,
13004         .ndo_del_vxlan_port     = bnx2x_del_vxlan_port,
13005 #endif
13006 };
13007
13008 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13009 {
13010         struct device *dev = &bp->pdev->dev;
13011
13012         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13013             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13014                 dev_err(dev, "System does not support DMA, aborting\n");
13015                 return -EIO;
13016         }
13017
13018         return 0;
13019 }
13020
13021 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13022 {
13023         if (bp->flags & AER_ENABLED) {
13024                 pci_disable_pcie_error_reporting(bp->pdev);
13025                 bp->flags &= ~AER_ENABLED;
13026         }
13027 }
13028
13029 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13030                           struct net_device *dev, unsigned long board_type)
13031 {
13032         int rc;
13033         u32 pci_cfg_dword;
13034         bool chip_is_e1x = (board_type == BCM57710 ||
13035                             board_type == BCM57711 ||
13036                             board_type == BCM57711E);
13037
13038         SET_NETDEV_DEV(dev, &pdev->dev);
13039
13040         bp->dev = dev;
13041         bp->pdev = pdev;
13042
13043         rc = pci_enable_device(pdev);
13044         if (rc) {
13045                 dev_err(&bp->pdev->dev,
13046                         "Cannot enable PCI device, aborting\n");
13047                 goto err_out;
13048         }
13049
13050         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13051                 dev_err(&bp->pdev->dev,
13052                         "Cannot find PCI device base address, aborting\n");
13053                 rc = -ENODEV;
13054                 goto err_out_disable;
13055         }
13056
13057         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13058                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13059                 rc = -ENODEV;
13060                 goto err_out_disable;
13061         }
13062
13063         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13064         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13065             PCICFG_REVESION_ID_ERROR_VAL) {
13066                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13067                 rc = -ENODEV;
13068                 goto err_out_disable;
13069         }
13070
13071         if (atomic_read(&pdev->enable_cnt) == 1) {
13072                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13073                 if (rc) {
13074                         dev_err(&bp->pdev->dev,
13075                                 "Cannot obtain PCI resources, aborting\n");
13076                         goto err_out_disable;
13077                 }
13078
13079                 pci_set_master(pdev);
13080                 pci_save_state(pdev);
13081         }
13082
13083         if (IS_PF(bp)) {
13084                 if (!pdev->pm_cap) {
13085                         dev_err(&bp->pdev->dev,
13086                                 "Cannot find power management capability, aborting\n");
13087                         rc = -EIO;
13088                         goto err_out_release;
13089                 }
13090         }
13091
13092         if (!pci_is_pcie(pdev)) {
13093                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13094                 rc = -EIO;
13095                 goto err_out_release;
13096         }
13097
13098         rc = bnx2x_set_coherency_mask(bp);
13099         if (rc)
13100                 goto err_out_release;
13101
13102         dev->mem_start = pci_resource_start(pdev, 0);
13103         dev->base_addr = dev->mem_start;
13104         dev->mem_end = pci_resource_end(pdev, 0);
13105
13106         dev->irq = pdev->irq;
13107
13108         bp->regview = pci_ioremap_bar(pdev, 0);
13109         if (!bp->regview) {
13110                 dev_err(&bp->pdev->dev,
13111                         "Cannot map register space, aborting\n");
13112                 rc = -ENOMEM;
13113                 goto err_out_release;
13114         }
13115
13116         /* In E1/E1H use pci device function given by kernel.
13117          * In E2/E3 read physical function from ME register since these chips
13118          * support Physical Device Assignment where kernel BDF maybe arbitrary
13119          * (depending on hypervisor).
13120          */
13121         if (chip_is_e1x) {
13122                 bp->pf_num = PCI_FUNC(pdev->devfn);
13123         } else {
13124                 /* chip is E2/3*/
13125                 pci_read_config_dword(bp->pdev,
13126                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13127                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13128                                   ME_REG_ABS_PF_NUM_SHIFT);
13129         }
13130         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13131
13132         /* clean indirect addresses */
13133         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13134                                PCICFG_VENDOR_ID_OFFSET);
13135
13136         /* Set PCIe reset type to fundamental for EEH recovery */
13137         pdev->needs_freset = 1;
13138
13139         /* AER (Advanced Error reporting) configuration */
13140         rc = pci_enable_pcie_error_reporting(pdev);
13141         if (!rc)
13142                 bp->flags |= AER_ENABLED;
13143         else
13144                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13145
13146         /*
13147          * Clean the following indirect addresses for all functions since it
13148          * is not used by the driver.
13149          */
13150         if (IS_PF(bp)) {
13151                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13152                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13153                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13154                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13155
13156                 if (chip_is_e1x) {
13157                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13158                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13159                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13160                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13161                 }
13162
13163                 /* Enable internal target-read (in case we are probed after PF
13164                  * FLR). Must be done prior to any BAR read access. Only for
13165                  * 57712 and up
13166                  */
13167                 if (!chip_is_e1x)
13168                         REG_WR(bp,
13169                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13170         }
13171
13172         dev->watchdog_timeo = TX_TIMEOUT;
13173
13174         dev->netdev_ops = &bnx2x_netdev_ops;
13175         bnx2x_set_ethtool_ops(bp, dev);
13176
13177         dev->priv_flags |= IFF_UNICAST_FLT;
13178
13179         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13180                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13181                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13182                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13183         if (!chip_is_e1x) {
13184                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
13185                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
13186                 dev->hw_enc_features =
13187                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13188                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13189                         NETIF_F_GSO_IPIP |
13190                         NETIF_F_GSO_SIT |
13191                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
13192         }
13193
13194         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13195                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13196
13197         /* VF with OLD Hypervisor or old PF do not support filtering */
13198         if (IS_PF(bp)) {
13199                 if (CHIP_IS_E1x(bp))
13200                         bp->accept_any_vlan = true;
13201                 else
13202                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13203 #ifdef CONFIG_BNX2X_SRIOV
13204         } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13205                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13206 #endif
13207         }
13208
13209         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13210         dev->features |= NETIF_F_HIGHDMA;
13211
13212         /* Add Loopback capability to the device */
13213         dev->hw_features |= NETIF_F_LOOPBACK;
13214
13215 #ifdef BCM_DCBNL
13216         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13217 #endif
13218
13219         /* get_port_hwinfo() will set prtad and mmds properly */
13220         bp->mdio.prtad = MDIO_PRTAD_NONE;
13221         bp->mdio.mmds = 0;
13222         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13223         bp->mdio.dev = dev;
13224         bp->mdio.mdio_read = bnx2x_mdio_read;
13225         bp->mdio.mdio_write = bnx2x_mdio_write;
13226
13227         return 0;
13228
13229 err_out_release:
13230         if (atomic_read(&pdev->enable_cnt) == 1)
13231                 pci_release_regions(pdev);
13232
13233 err_out_disable:
13234         pci_disable_device(pdev);
13235
13236 err_out:
13237         return rc;
13238 }
13239
13240 static int bnx2x_check_firmware(struct bnx2x *bp)
13241 {
13242         const struct firmware *firmware = bp->firmware;
13243         struct bnx2x_fw_file_hdr *fw_hdr;
13244         struct bnx2x_fw_file_section *sections;
13245         u32 offset, len, num_ops;
13246         __be16 *ops_offsets;
13247         int i;
13248         const u8 *fw_ver;
13249
13250         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13251                 BNX2X_ERR("Wrong FW size\n");
13252                 return -EINVAL;
13253         }
13254
13255         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13256         sections = (struct bnx2x_fw_file_section *)fw_hdr;
13257
13258         /* Make sure none of the offsets and sizes make us read beyond
13259          * the end of the firmware data */
13260         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13261                 offset = be32_to_cpu(sections[i].offset);
13262                 len = be32_to_cpu(sections[i].len);
13263                 if (offset + len > firmware->size) {
13264                         BNX2X_ERR("Section %d length is out of bounds\n", i);
13265                         return -EINVAL;
13266                 }
13267         }
13268
13269         /* Likewise for the init_ops offsets */
13270         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13271         ops_offsets = (__force __be16 *)(firmware->data + offset);
13272         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13273
13274         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13275                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13276                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
13277                         return -EINVAL;
13278                 }
13279         }
13280
13281         /* Check FW version */
13282         offset = be32_to_cpu(fw_hdr->fw_version.offset);
13283         fw_ver = firmware->data + offset;
13284         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13285             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13286             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13287             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13288                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13289                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13290                        BCM_5710_FW_MAJOR_VERSION,
13291                        BCM_5710_FW_MINOR_VERSION,
13292                        BCM_5710_FW_REVISION_VERSION,
13293                        BCM_5710_FW_ENGINEERING_VERSION);
13294                 return -EINVAL;
13295         }
13296
13297         return 0;
13298 }
13299
13300 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13301 {
13302         const __be32 *source = (const __be32 *)_source;
13303         u32 *target = (u32 *)_target;
13304         u32 i;
13305
13306         for (i = 0; i < n/4; i++)
13307                 target[i] = be32_to_cpu(source[i]);
13308 }
13309
13310 /*
13311    Ops array is stored in the following format:
13312    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13313  */
13314 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13315 {
13316         const __be32 *source = (const __be32 *)_source;
13317         struct raw_op *target = (struct raw_op *)_target;
13318         u32 i, j, tmp;
13319
13320         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13321                 tmp = be32_to_cpu(source[j]);
13322                 target[i].op = (tmp >> 24) & 0xff;
13323                 target[i].offset = tmp & 0xffffff;
13324                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13325         }
13326 }
13327
13328 /* IRO array is stored in the following format:
13329  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13330  */
13331 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13332 {
13333         const __be32 *source = (const __be32 *)_source;
13334         struct iro *target = (struct iro *)_target;
13335         u32 i, j, tmp;
13336
13337         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13338                 target[i].base = be32_to_cpu(source[j]);
13339                 j++;
13340                 tmp = be32_to_cpu(source[j]);
13341                 target[i].m1 = (tmp >> 16) & 0xffff;
13342                 target[i].m2 = tmp & 0xffff;
13343                 j++;
13344                 tmp = be32_to_cpu(source[j]);
13345                 target[i].m3 = (tmp >> 16) & 0xffff;
13346                 target[i].size = tmp & 0xffff;
13347                 j++;
13348         }
13349 }
13350
13351 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13352 {
13353         const __be16 *source = (const __be16 *)_source;
13354         u16 *target = (u16 *)_target;
13355         u32 i;
13356
13357         for (i = 0; i < n/2; i++)
13358                 target[i] = be16_to_cpu(source[i]);
13359 }
13360
13361 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13362 do {                                                                    \
13363         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13364         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13365         if (!bp->arr)                                                   \
13366                 goto lbl;                                               \
13367         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13368              (u8 *)bp->arr, len);                                       \
13369 } while (0)
13370
13371 static int bnx2x_init_firmware(struct bnx2x *bp)
13372 {
13373         const char *fw_file_name;
13374         struct bnx2x_fw_file_hdr *fw_hdr;
13375         int rc;
13376
13377         if (bp->firmware)
13378                 return 0;
13379
13380         if (CHIP_IS_E1(bp))
13381                 fw_file_name = FW_FILE_NAME_E1;
13382         else if (CHIP_IS_E1H(bp))
13383                 fw_file_name = FW_FILE_NAME_E1H;
13384         else if (!CHIP_IS_E1x(bp))
13385                 fw_file_name = FW_FILE_NAME_E2;
13386         else {
13387                 BNX2X_ERR("Unsupported chip revision\n");
13388                 return -EINVAL;
13389         }
13390         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13391
13392         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13393         if (rc) {
13394                 BNX2X_ERR("Can't load firmware file %s\n",
13395                           fw_file_name);
13396                 goto request_firmware_exit;
13397         }
13398
13399         rc = bnx2x_check_firmware(bp);
13400         if (rc) {
13401                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13402                 goto request_firmware_exit;
13403         }
13404
13405         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13406
13407         /* Initialize the pointers to the init arrays */
13408         /* Blob */
13409         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13410
13411         /* Opcodes */
13412         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13413
13414         /* Offsets */
13415         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13416                             be16_to_cpu_n);
13417
13418         /* STORMs firmware */
13419         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13420                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13421         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13422                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13423         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13424                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13425         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13426                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13427         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13428                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13429         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13430                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13431         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13432                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13433         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13434                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13435         /* IRO */
13436         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13437
13438         return 0;
13439
13440 iro_alloc_err:
13441         kfree(bp->init_ops_offsets);
13442 init_offsets_alloc_err:
13443         kfree(bp->init_ops);
13444 init_ops_alloc_err:
13445         kfree(bp->init_data);
13446 request_firmware_exit:
13447         release_firmware(bp->firmware);
13448         bp->firmware = NULL;
13449
13450         return rc;
13451 }
13452
13453 static void bnx2x_release_firmware(struct bnx2x *bp)
13454 {
13455         kfree(bp->init_ops_offsets);
13456         kfree(bp->init_ops);
13457         kfree(bp->init_data);
13458         release_firmware(bp->firmware);
13459         bp->firmware = NULL;
13460 }
13461
13462 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13463         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13464         .init_hw_cmn      = bnx2x_init_hw_common,
13465         .init_hw_port     = bnx2x_init_hw_port,
13466         .init_hw_func     = bnx2x_init_hw_func,
13467
13468         .reset_hw_cmn     = bnx2x_reset_common,
13469         .reset_hw_port    = bnx2x_reset_port,
13470         .reset_hw_func    = bnx2x_reset_func,
13471
13472         .gunzip_init      = bnx2x_gunzip_init,
13473         .gunzip_end       = bnx2x_gunzip_end,
13474
13475         .init_fw          = bnx2x_init_firmware,
13476         .release_fw       = bnx2x_release_firmware,
13477 };
13478
13479 void bnx2x__init_func_obj(struct bnx2x *bp)
13480 {
13481         /* Prepare DMAE related driver resources */
13482         bnx2x_setup_dmae(bp);
13483
13484         bnx2x_init_func_obj(bp, &bp->func_obj,
13485                             bnx2x_sp(bp, func_rdata),
13486                             bnx2x_sp_mapping(bp, func_rdata),
13487                             bnx2x_sp(bp, func_afex_rdata),
13488                             bnx2x_sp_mapping(bp, func_afex_rdata),
13489                             &bnx2x_func_sp_drv);
13490 }
13491
13492 /* must be called after sriov-enable */
13493 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13494 {
13495         int cid_count = BNX2X_L2_MAX_CID(bp);
13496
13497         if (IS_SRIOV(bp))
13498                 cid_count += BNX2X_VF_CIDS;
13499
13500         if (CNIC_SUPPORT(bp))
13501                 cid_count += CNIC_CID_MAX;
13502
13503         return roundup(cid_count, QM_CID_ROUND);
13504 }
13505
13506 /**
13507  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13508  *
13509  * @dev:        pci device
13510  *
13511  */
13512 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13513 {
13514         int index;
13515         u16 control = 0;
13516
13517         /*
13518          * If MSI-X is not supported - return number of SBs needed to support
13519          * one fast path queue: one FP queue + SB for CNIC
13520          */
13521         if (!pdev->msix_cap) {
13522                 dev_info(&pdev->dev, "no msix capability found\n");
13523                 return 1 + cnic_cnt;
13524         }
13525         dev_info(&pdev->dev, "msix capability found\n");
13526
13527         /*
13528          * The value in the PCI configuration space is the index of the last
13529          * entry, namely one less than the actual size of the table, which is
13530          * exactly what we want to return from this function: number of all SBs
13531          * without the default SB.
13532          * For VFs there is no default SB, then we return (index+1).
13533          */
13534         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13535
13536         index = control & PCI_MSIX_FLAGS_QSIZE;
13537
13538         return index;
13539 }
13540
13541 static int set_max_cos_est(int chip_id)
13542 {
13543         switch (chip_id) {
13544         case BCM57710:
13545         case BCM57711:
13546         case BCM57711E:
13547                 return BNX2X_MULTI_TX_COS_E1X;
13548         case BCM57712:
13549         case BCM57712_MF:
13550                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13551         case BCM57800:
13552         case BCM57800_MF:
13553         case BCM57810:
13554         case BCM57810_MF:
13555         case BCM57840_4_10:
13556         case BCM57840_2_20:
13557         case BCM57840_O:
13558         case BCM57840_MFO:
13559         case BCM57840_MF:
13560         case BCM57811:
13561         case BCM57811_MF:
13562                 return BNX2X_MULTI_TX_COS_E3B0;
13563         case BCM57712_VF:
13564         case BCM57800_VF:
13565         case BCM57810_VF:
13566         case BCM57840_VF:
13567         case BCM57811_VF:
13568                 return 1;
13569         default:
13570                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13571                 return -ENODEV;
13572         }
13573 }
13574
13575 static int set_is_vf(int chip_id)
13576 {
13577         switch (chip_id) {
13578         case BCM57712_VF:
13579         case BCM57800_VF:
13580         case BCM57810_VF:
13581         case BCM57840_VF:
13582         case BCM57811_VF:
13583                 return true;
13584         default:
13585                 return false;
13586         }
13587 }
13588
13589 /* nig_tsgen registers relative address */
13590 #define tsgen_ctrl 0x0
13591 #define tsgen_freecount 0x10
13592 #define tsgen_synctime_t0 0x20
13593 #define tsgen_offset_t0 0x28
13594 #define tsgen_drift_t0 0x30
13595 #define tsgen_synctime_t1 0x58
13596 #define tsgen_offset_t1 0x60
13597 #define tsgen_drift_t1 0x68
13598
13599 /* FW workaround for setting drift */
13600 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13601                                           int best_val, int best_period)
13602 {
13603         struct bnx2x_func_state_params func_params = {NULL};
13604         struct bnx2x_func_set_timesync_params *set_timesync_params =
13605                 &func_params.params.set_timesync;
13606
13607         /* Prepare parameters for function state transitions */
13608         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13609         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13610
13611         func_params.f_obj = &bp->func_obj;
13612         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13613
13614         /* Function parameters */
13615         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13616         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13617         set_timesync_params->add_sub_drift_adjust_value =
13618                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13619         set_timesync_params->drift_adjust_value = best_val;
13620         set_timesync_params->drift_adjust_period = best_period;
13621
13622         return bnx2x_func_state_change(bp, &func_params);
13623 }
13624
13625 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13626 {
13627         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13628         int rc;
13629         int drift_dir = 1;
13630         int val, period, period1, period2, dif, dif1, dif2;
13631         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13632
13633         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13634
13635         if (!netif_running(bp->dev)) {
13636                 DP(BNX2X_MSG_PTP,
13637                    "PTP adjfreq called while the interface is down\n");
13638                 return -EFAULT;
13639         }
13640
13641         if (ppb < 0) {
13642                 ppb = -ppb;
13643                 drift_dir = 0;
13644         }
13645
13646         if (ppb == 0) {
13647                 best_val = 1;
13648                 best_period = 0x1FFFFFF;
13649         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13650                 best_val = 31;
13651                 best_period = 1;
13652         } else {
13653                 /* Changed not to allow val = 8, 16, 24 as these values
13654                  * are not supported in workaround.
13655                  */
13656                 for (val = 0; val <= 31; val++) {
13657                         if ((val & 0x7) == 0)
13658                                 continue;
13659                         period1 = val * 1000000 / ppb;
13660                         period2 = period1 + 1;
13661                         if (period1 != 0)
13662                                 dif1 = ppb - (val * 1000000 / period1);
13663                         else
13664                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13665                         if (dif1 < 0)
13666                                 dif1 = -dif1;
13667                         dif2 = ppb - (val * 1000000 / period2);
13668                         if (dif2 < 0)
13669                                 dif2 = -dif2;
13670                         dif = (dif1 < dif2) ? dif1 : dif2;
13671                         period = (dif1 < dif2) ? period1 : period2;
13672                         if (dif < best_dif) {
13673                                 best_dif = dif;
13674                                 best_val = val;
13675                                 best_period = period;
13676                         }
13677                 }
13678         }
13679
13680         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13681                                             best_period);
13682         if (rc) {
13683                 BNX2X_ERR("Failed to set drift\n");
13684                 return -EFAULT;
13685         }
13686
13687         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13688            best_period);
13689
13690         return 0;
13691 }
13692
13693 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13694 {
13695         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13696
13697         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13698
13699         timecounter_adjtime(&bp->timecounter, delta);
13700
13701         return 0;
13702 }
13703
13704 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13705 {
13706         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13707         u64 ns;
13708
13709         ns = timecounter_read(&bp->timecounter);
13710
13711         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13712
13713         *ts = ns_to_timespec64(ns);
13714
13715         return 0;
13716 }
13717
13718 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13719                              const struct timespec64 *ts)
13720 {
13721         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13722         u64 ns;
13723
13724         ns = timespec64_to_ns(ts);
13725
13726         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13727
13728         /* Re-init the timecounter */
13729         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13730
13731         return 0;
13732 }
13733
13734 /* Enable (or disable) ancillary features of the phc subsystem */
13735 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13736                             struct ptp_clock_request *rq, int on)
13737 {
13738         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13739
13740         BNX2X_ERR("PHC ancillary features are not supported\n");
13741         return -ENOTSUPP;
13742 }
13743
13744 static void bnx2x_register_phc(struct bnx2x *bp)
13745 {
13746         /* Fill the ptp_clock_info struct and register PTP clock*/
13747         bp->ptp_clock_info.owner = THIS_MODULE;
13748         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13749         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13750         bp->ptp_clock_info.n_alarm = 0;
13751         bp->ptp_clock_info.n_ext_ts = 0;
13752         bp->ptp_clock_info.n_per_out = 0;
13753         bp->ptp_clock_info.pps = 0;
13754         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13755         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13756         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13757         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13758         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13759
13760         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13761         if (IS_ERR(bp->ptp_clock)) {
13762                 bp->ptp_clock = NULL;
13763                 BNX2X_ERR("PTP clock registeration failed\n");
13764         }
13765 }
13766
13767 static int bnx2x_init_one(struct pci_dev *pdev,
13768                                     const struct pci_device_id *ent)
13769 {
13770         struct net_device *dev = NULL;
13771         struct bnx2x *bp;
13772         enum pcie_link_width pcie_width;
13773         enum pci_bus_speed pcie_speed;
13774         int rc, max_non_def_sbs;
13775         int rx_count, tx_count, rss_count, doorbell_size;
13776         int max_cos_est;
13777         bool is_vf;
13778         int cnic_cnt;
13779
13780         /* Management FW 'remembers' living interfaces. Allow it some time
13781          * to forget previously living interfaces, allowing a proper re-load.
13782          */
13783         if (is_kdump_kernel()) {
13784                 ktime_t now = ktime_get_boottime();
13785                 ktime_t fw_ready_time = ktime_set(5, 0);
13786
13787                 if (ktime_before(now, fw_ready_time))
13788                         msleep(ktime_ms_delta(fw_ready_time, now));
13789         }
13790
13791         /* An estimated maximum supported CoS number according to the chip
13792          * version.
13793          * We will try to roughly estimate the maximum number of CoSes this chip
13794          * may support in order to minimize the memory allocated for Tx
13795          * netdev_queue's. This number will be accurately calculated during the
13796          * initialization of bp->max_cos based on the chip versions AND chip
13797          * revision in the bnx2x_init_bp().
13798          */
13799         max_cos_est = set_max_cos_est(ent->driver_data);
13800         if (max_cos_est < 0)
13801                 return max_cos_est;
13802         is_vf = set_is_vf(ent->driver_data);
13803         cnic_cnt = is_vf ? 0 : 1;
13804
13805         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13806
13807         /* add another SB for VF as it has no default SB */
13808         max_non_def_sbs += is_vf ? 1 : 0;
13809
13810         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13811         rss_count = max_non_def_sbs - cnic_cnt;
13812
13813         if (rss_count < 1)
13814                 return -EINVAL;
13815
13816         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13817         rx_count = rss_count + cnic_cnt;
13818
13819         /* Maximum number of netdev Tx queues:
13820          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13821          */
13822         tx_count = rss_count * max_cos_est + cnic_cnt;
13823
13824         /* dev zeroed in init_etherdev */
13825         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13826         if (!dev)
13827                 return -ENOMEM;
13828
13829         bp = netdev_priv(dev);
13830
13831         bp->flags = 0;
13832         if (is_vf)
13833                 bp->flags |= IS_VF_FLAG;
13834
13835         bp->igu_sb_cnt = max_non_def_sbs;
13836         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13837         bp->msg_enable = debug;
13838         bp->cnic_support = cnic_cnt;
13839         bp->cnic_probe = bnx2x_cnic_probe;
13840
13841         pci_set_drvdata(pdev, dev);
13842
13843         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13844         if (rc < 0) {
13845                 free_netdev(dev);
13846                 return rc;
13847         }
13848
13849         BNX2X_DEV_INFO("This is a %s function\n",
13850                        IS_PF(bp) ? "physical" : "virtual");
13851         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13852         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13853         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13854                        tx_count, rx_count);
13855
13856         rc = bnx2x_init_bp(bp);
13857         if (rc)
13858                 goto init_one_exit;
13859
13860         /* Map doorbells here as we need the real value of bp->max_cos which
13861          * is initialized in bnx2x_init_bp() to determine the number of
13862          * l2 connections.
13863          */
13864         if (IS_VF(bp)) {
13865                 bp->doorbells = bnx2x_vf_doorbells(bp);
13866                 rc = bnx2x_vf_pci_alloc(bp);
13867                 if (rc)
13868                         goto init_one_exit;
13869         } else {
13870                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13871                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13872                         dev_err(&bp->pdev->dev,
13873                                 "Cannot map doorbells, bar size too small, aborting\n");
13874                         rc = -ENOMEM;
13875                         goto init_one_exit;
13876                 }
13877                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13878                                                 doorbell_size);
13879         }
13880         if (!bp->doorbells) {
13881                 dev_err(&bp->pdev->dev,
13882                         "Cannot map doorbell space, aborting\n");
13883                 rc = -ENOMEM;
13884                 goto init_one_exit;
13885         }
13886
13887         if (IS_VF(bp)) {
13888                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13889                 if (rc)
13890                         goto init_one_exit;
13891         }
13892
13893         /* Enable SRIOV if capability found in configuration space */
13894         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13895         if (rc)
13896                 goto init_one_exit;
13897
13898         /* calc qm_cid_count */
13899         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13900         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13901
13902         /* disable FCOE L2 queue for E1x*/
13903         if (CHIP_IS_E1x(bp))
13904                 bp->flags |= NO_FCOE_FLAG;
13905
13906         /* Set bp->num_queues for MSI-X mode*/
13907         bnx2x_set_num_queues(bp);
13908
13909         /* Configure interrupt mode: try to enable MSI-X/MSI if
13910          * needed.
13911          */
13912         rc = bnx2x_set_int_mode(bp);
13913         if (rc) {
13914                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13915                 goto init_one_exit;
13916         }
13917         BNX2X_DEV_INFO("set interrupts successfully\n");
13918
13919         /* register the net device */
13920         rc = register_netdev(dev);
13921         if (rc) {
13922                 dev_err(&pdev->dev, "Cannot register net device\n");
13923                 goto init_one_exit;
13924         }
13925         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13926
13927         if (!NO_FCOE(bp)) {
13928                 /* Add storage MAC address */
13929                 rtnl_lock();
13930                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13931                 rtnl_unlock();
13932         }
13933         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13934             pcie_speed == PCI_SPEED_UNKNOWN ||
13935             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13936                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13937         else
13938                 BNX2X_DEV_INFO(
13939                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13940                        board_info[ent->driver_data].name,
13941                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13942                        pcie_width,
13943                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13944                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13945                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13946                        "Unknown",
13947                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13948
13949         bnx2x_register_phc(bp);
13950
13951         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13952                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13953
13954         return 0;
13955
13956 init_one_exit:
13957         bnx2x_disable_pcie_error_reporting(bp);
13958
13959         if (bp->regview)
13960                 iounmap(bp->regview);
13961
13962         if (IS_PF(bp) && bp->doorbells)
13963                 iounmap(bp->doorbells);
13964
13965         free_netdev(dev);
13966
13967         if (atomic_read(&pdev->enable_cnt) == 1)
13968                 pci_release_regions(pdev);
13969
13970         pci_disable_device(pdev);
13971
13972         return rc;
13973 }
13974
13975 static void __bnx2x_remove(struct pci_dev *pdev,
13976                            struct net_device *dev,
13977                            struct bnx2x *bp,
13978                            bool remove_netdev)
13979 {
13980         if (bp->ptp_clock) {
13981                 ptp_clock_unregister(bp->ptp_clock);
13982                 bp->ptp_clock = NULL;
13983         }
13984
13985         /* Delete storage MAC address */
13986         if (!NO_FCOE(bp)) {
13987                 rtnl_lock();
13988                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13989                 rtnl_unlock();
13990         }
13991
13992 #ifdef BCM_DCBNL
13993         /* Delete app tlvs from dcbnl */
13994         bnx2x_dcbnl_update_applist(bp, true);
13995 #endif
13996
13997         if (IS_PF(bp) &&
13998             !BP_NOMCP(bp) &&
13999             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14000                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14001
14002         /* Close the interface - either directly or implicitly */
14003         if (remove_netdev) {
14004                 unregister_netdev(dev);
14005         } else {
14006                 rtnl_lock();
14007                 dev_close(dev);
14008                 rtnl_unlock();
14009         }
14010
14011         bnx2x_iov_remove_one(bp);
14012
14013         /* Power on: we can't let PCI layer write to us while we are in D3 */
14014         if (IS_PF(bp)) {
14015                 bnx2x_set_power_state(bp, PCI_D0);
14016                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14017
14018                 /* Set endianity registers to reset values in case next driver
14019                  * boots in different endianty environment.
14020                  */
14021                 bnx2x_reset_endianity(bp);
14022         }
14023
14024         /* Disable MSI/MSI-X */
14025         bnx2x_disable_msi(bp);
14026
14027         /* Power off */
14028         if (IS_PF(bp))
14029                 bnx2x_set_power_state(bp, PCI_D3hot);
14030
14031         /* Make sure RESET task is not scheduled before continuing */
14032         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14033
14034         /* send message via vfpf channel to release the resources of this vf */
14035         if (IS_VF(bp))
14036                 bnx2x_vfpf_release(bp);
14037
14038         /* Assumes no further PCIe PM changes will occur */
14039         if (system_state == SYSTEM_POWER_OFF) {
14040                 pci_wake_from_d3(pdev, bp->wol);
14041                 pci_set_power_state(pdev, PCI_D3hot);
14042         }
14043
14044         bnx2x_disable_pcie_error_reporting(bp);
14045         if (remove_netdev) {
14046                 if (bp->regview)
14047                         iounmap(bp->regview);
14048
14049                 /* For vfs, doorbells are part of the regview and were unmapped
14050                  * along with it. FW is only loaded by PF.
14051                  */
14052                 if (IS_PF(bp)) {
14053                         if (bp->doorbells)
14054                                 iounmap(bp->doorbells);
14055
14056                         bnx2x_release_firmware(bp);
14057                 } else {
14058                         bnx2x_vf_pci_dealloc(bp);
14059                 }
14060                 bnx2x_free_mem_bp(bp);
14061
14062                 free_netdev(dev);
14063
14064                 if (atomic_read(&pdev->enable_cnt) == 1)
14065                         pci_release_regions(pdev);
14066
14067                 pci_disable_device(pdev);
14068         }
14069 }
14070
14071 static void bnx2x_remove_one(struct pci_dev *pdev)
14072 {
14073         struct net_device *dev = pci_get_drvdata(pdev);
14074         struct bnx2x *bp;
14075
14076         if (!dev) {
14077                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14078                 return;
14079         }
14080         bp = netdev_priv(dev);
14081
14082         __bnx2x_remove(pdev, dev, bp, true);
14083 }
14084
14085 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14086 {
14087         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14088
14089         bp->rx_mode = BNX2X_RX_MODE_NONE;
14090
14091         if (CNIC_LOADED(bp))
14092                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14093
14094         /* Stop Tx */
14095         bnx2x_tx_disable(bp);
14096         /* Delete all NAPI objects */
14097         bnx2x_del_all_napi(bp);
14098         if (CNIC_LOADED(bp))
14099                 bnx2x_del_all_napi_cnic(bp);
14100         netdev_reset_tc(bp->dev);
14101
14102         del_timer_sync(&bp->timer);
14103         cancel_delayed_work_sync(&bp->sp_task);
14104         cancel_delayed_work_sync(&bp->period_task);
14105
14106         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14107                 bp->stats_state = STATS_STATE_DISABLED;
14108                 up(&bp->stats_lock);
14109         }
14110
14111         bnx2x_save_statistics(bp);
14112
14113         netif_carrier_off(bp->dev);
14114
14115         return 0;
14116 }
14117
14118 /**
14119  * bnx2x_io_error_detected - called when PCI error is detected
14120  * @pdev: Pointer to PCI device
14121  * @state: The current pci connection state
14122  *
14123  * This function is called after a PCI bus error affecting
14124  * this device has been detected.
14125  */
14126 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14127                                                 pci_channel_state_t state)
14128 {
14129         struct net_device *dev = pci_get_drvdata(pdev);
14130         struct bnx2x *bp = netdev_priv(dev);
14131
14132         rtnl_lock();
14133
14134         BNX2X_ERR("IO error detected\n");
14135
14136         netif_device_detach(dev);
14137
14138         if (state == pci_channel_io_perm_failure) {
14139                 rtnl_unlock();
14140                 return PCI_ERS_RESULT_DISCONNECT;
14141         }
14142
14143         if (netif_running(dev))
14144                 bnx2x_eeh_nic_unload(bp);
14145
14146         bnx2x_prev_path_mark_eeh(bp);
14147
14148         pci_disable_device(pdev);
14149
14150         rtnl_unlock();
14151
14152         /* Request a slot reset */
14153         return PCI_ERS_RESULT_NEED_RESET;
14154 }
14155
14156 /**
14157  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14158  * @pdev: Pointer to PCI device
14159  *
14160  * Restart the card from scratch, as if from a cold-boot.
14161  */
14162 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14163 {
14164         struct net_device *dev = pci_get_drvdata(pdev);
14165         struct bnx2x *bp = netdev_priv(dev);
14166         int i;
14167
14168         rtnl_lock();
14169         BNX2X_ERR("IO slot reset initializing...\n");
14170         if (pci_enable_device(pdev)) {
14171                 dev_err(&pdev->dev,
14172                         "Cannot re-enable PCI device after reset\n");
14173                 rtnl_unlock();
14174                 return PCI_ERS_RESULT_DISCONNECT;
14175         }
14176
14177         pci_set_master(pdev);
14178         pci_restore_state(pdev);
14179         pci_save_state(pdev);
14180
14181         if (netif_running(dev))
14182                 bnx2x_set_power_state(bp, PCI_D0);
14183
14184         if (netif_running(dev)) {
14185                 BNX2X_ERR("IO slot reset --> driver unload\n");
14186
14187                 /* MCP should have been reset; Need to wait for validity */
14188                 bnx2x_init_shmem(bp);
14189
14190                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14191                         u32 v;
14192
14193                         v = SHMEM2_RD(bp,
14194                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14195                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14196                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14197                 }
14198                 bnx2x_drain_tx_queues(bp);
14199                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14200                 bnx2x_netif_stop(bp, 1);
14201                 bnx2x_free_irq(bp);
14202
14203                 /* Report UNLOAD_DONE to MCP */
14204                 bnx2x_send_unload_done(bp, true);
14205
14206                 bp->sp_state = 0;
14207                 bp->port.pmf = 0;
14208
14209                 bnx2x_prev_unload(bp);
14210
14211                 /* We should have reseted the engine, so It's fair to
14212                  * assume the FW will no longer write to the bnx2x driver.
14213                  */
14214                 bnx2x_squeeze_objects(bp);
14215                 bnx2x_free_skbs(bp);
14216                 for_each_rx_queue(bp, i)
14217                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14218                 bnx2x_free_fp_mem(bp);
14219                 bnx2x_free_mem(bp);
14220
14221                 bp->state = BNX2X_STATE_CLOSED;
14222         }
14223
14224         rtnl_unlock();
14225
14226         /* If AER, perform cleanup of the PCIe registers */
14227         if (bp->flags & AER_ENABLED) {
14228                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14229                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14230                 else
14231                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14232         }
14233
14234         return PCI_ERS_RESULT_RECOVERED;
14235 }
14236
14237 /**
14238  * bnx2x_io_resume - called when traffic can start flowing again
14239  * @pdev: Pointer to PCI device
14240  *
14241  * This callback is called when the error recovery driver tells us that
14242  * its OK to resume normal operation.
14243  */
14244 static void bnx2x_io_resume(struct pci_dev *pdev)
14245 {
14246         struct net_device *dev = pci_get_drvdata(pdev);
14247         struct bnx2x *bp = netdev_priv(dev);
14248
14249         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14250                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14251                 return;
14252         }
14253
14254         rtnl_lock();
14255
14256         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14257                                                         DRV_MSG_SEQ_NUMBER_MASK;
14258
14259         if (netif_running(dev))
14260                 bnx2x_nic_load(bp, LOAD_NORMAL);
14261
14262         netif_device_attach(dev);
14263
14264         rtnl_unlock();
14265 }
14266
14267 static const struct pci_error_handlers bnx2x_err_handler = {
14268         .error_detected = bnx2x_io_error_detected,
14269         .slot_reset     = bnx2x_io_slot_reset,
14270         .resume         = bnx2x_io_resume,
14271 };
14272
14273 static void bnx2x_shutdown(struct pci_dev *pdev)
14274 {
14275         struct net_device *dev = pci_get_drvdata(pdev);
14276         struct bnx2x *bp;
14277
14278         if (!dev)
14279                 return;
14280
14281         bp = netdev_priv(dev);
14282         if (!bp)
14283                 return;
14284
14285         rtnl_lock();
14286         netif_device_detach(dev);
14287         rtnl_unlock();
14288
14289         /* Don't remove the netdevice, as there are scenarios which will cause
14290          * the kernel to hang, e.g., when trying to remove bnx2i while the
14291          * rootfs is mounted from SAN.
14292          */
14293         __bnx2x_remove(pdev, dev, bp, false);
14294 }
14295
14296 static struct pci_driver bnx2x_pci_driver = {
14297         .name        = DRV_MODULE_NAME,
14298         .id_table    = bnx2x_pci_tbl,
14299         .probe       = bnx2x_init_one,
14300         .remove      = bnx2x_remove_one,
14301         .suspend     = bnx2x_suspend,
14302         .resume      = bnx2x_resume,
14303         .err_handler = &bnx2x_err_handler,
14304 #ifdef CONFIG_BNX2X_SRIOV
14305         .sriov_configure = bnx2x_sriov_configure,
14306 #endif
14307         .shutdown    = bnx2x_shutdown,
14308 };
14309
14310 static int __init bnx2x_init(void)
14311 {
14312         int ret;
14313
14314         pr_info("%s", version);
14315
14316         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14317         if (bnx2x_wq == NULL) {
14318                 pr_err("Cannot create workqueue\n");
14319                 return -ENOMEM;
14320         }
14321         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14322         if (!bnx2x_iov_wq) {
14323                 pr_err("Cannot create iov workqueue\n");
14324                 destroy_workqueue(bnx2x_wq);
14325                 return -ENOMEM;
14326         }
14327
14328         ret = pci_register_driver(&bnx2x_pci_driver);
14329         if (ret) {
14330                 pr_err("Cannot register driver\n");
14331                 destroy_workqueue(bnx2x_wq);
14332                 destroy_workqueue(bnx2x_iov_wq);
14333         }
14334         return ret;
14335 }
14336
14337 static void __exit bnx2x_cleanup(void)
14338 {
14339         struct list_head *pos, *q;
14340
14341         pci_unregister_driver(&bnx2x_pci_driver);
14342
14343         destroy_workqueue(bnx2x_wq);
14344         destroy_workqueue(bnx2x_iov_wq);
14345
14346         /* Free globally allocated resources */
14347         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14348                 struct bnx2x_prev_path_list *tmp =
14349                         list_entry(pos, struct bnx2x_prev_path_list, list);
14350                 list_del(pos);
14351                 kfree(tmp);
14352         }
14353 }
14354
14355 void bnx2x_notify_link_changed(struct bnx2x *bp)
14356 {
14357         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14358 }
14359
14360 module_init(bnx2x_init);
14361 module_exit(bnx2x_cleanup);
14362
14363 /**
14364  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14365  *
14366  * @bp:         driver handle
14367  * @set:        set or clear the CAM entry
14368  *
14369  * This function will wait until the ramrod completion returns.
14370  * Return 0 if success, -ENODEV if ramrod doesn't return.
14371  */
14372 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14373 {
14374         unsigned long ramrod_flags = 0;
14375
14376         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14377         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14378                                  &bp->iscsi_l2_mac_obj, true,
14379                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14380 }
14381
14382 /* count denotes the number of new completions we have seen */
14383 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14384 {
14385         struct eth_spe *spe;
14386         int cxt_index, cxt_offset;
14387
14388 #ifdef BNX2X_STOP_ON_ERROR
14389         if (unlikely(bp->panic))
14390                 return;
14391 #endif
14392
14393         spin_lock_bh(&bp->spq_lock);
14394         BUG_ON(bp->cnic_spq_pending < count);
14395         bp->cnic_spq_pending -= count;
14396
14397         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14398                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14399                                 & SPE_HDR_CONN_TYPE) >>
14400                                 SPE_HDR_CONN_TYPE_SHIFT;
14401                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14402                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14403
14404                 /* Set validation for iSCSI L2 client before sending SETUP
14405                  *  ramrod
14406                  */
14407                 if (type == ETH_CONNECTION_TYPE) {
14408                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14409                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14410                                         ILT_PAGE_CIDS;
14411                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14412                                         (cxt_index * ILT_PAGE_CIDS);
14413                                 bnx2x_set_ctx_validation(bp,
14414                                         &bp->context[cxt_index].
14415                                                          vcxt[cxt_offset].eth,
14416                                         BNX2X_ISCSI_ETH_CID(bp));
14417                         }
14418                 }
14419
14420                 /*
14421                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14422                  * and in the air. We also check that number of outstanding
14423                  * COMMON ramrods is not more than the EQ and SPQ can
14424                  * accommodate.
14425                  */
14426                 if (type == ETH_CONNECTION_TYPE) {
14427                         if (!atomic_read(&bp->cq_spq_left))
14428                                 break;
14429                         else
14430                                 atomic_dec(&bp->cq_spq_left);
14431                 } else if (type == NONE_CONNECTION_TYPE) {
14432                         if (!atomic_read(&bp->eq_spq_left))
14433                                 break;
14434                         else
14435                                 atomic_dec(&bp->eq_spq_left);
14436                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14437                            (type == FCOE_CONNECTION_TYPE)) {
14438                         if (bp->cnic_spq_pending >=
14439                             bp->cnic_eth_dev.max_kwqe_pending)
14440                                 break;
14441                         else
14442                                 bp->cnic_spq_pending++;
14443                 } else {
14444                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14445                         bnx2x_panic();
14446                         break;
14447                 }
14448
14449                 spe = bnx2x_sp_get_next(bp);
14450                 *spe = *bp->cnic_kwq_cons;
14451
14452                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14453                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14454
14455                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14456                         bp->cnic_kwq_cons = bp->cnic_kwq;
14457                 else
14458                         bp->cnic_kwq_cons++;
14459         }
14460         bnx2x_sp_prod_update(bp);
14461         spin_unlock_bh(&bp->spq_lock);
14462 }
14463
14464 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14465                                struct kwqe_16 *kwqes[], u32 count)
14466 {
14467         struct bnx2x *bp = netdev_priv(dev);
14468         int i;
14469
14470 #ifdef BNX2X_STOP_ON_ERROR
14471         if (unlikely(bp->panic)) {
14472                 BNX2X_ERR("Can't post to SP queue while panic\n");
14473                 return -EIO;
14474         }
14475 #endif
14476
14477         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14478             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14479                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14480                 return -EAGAIN;
14481         }
14482
14483         spin_lock_bh(&bp->spq_lock);
14484
14485         for (i = 0; i < count; i++) {
14486                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14487
14488                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14489                         break;
14490
14491                 *bp->cnic_kwq_prod = *spe;
14492
14493                 bp->cnic_kwq_pending++;
14494
14495                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14496                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14497                    spe->data.update_data_addr.hi,
14498                    spe->data.update_data_addr.lo,
14499                    bp->cnic_kwq_pending);
14500
14501                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14502                         bp->cnic_kwq_prod = bp->cnic_kwq;
14503                 else
14504                         bp->cnic_kwq_prod++;
14505         }
14506
14507         spin_unlock_bh(&bp->spq_lock);
14508
14509         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14510                 bnx2x_cnic_sp_post(bp, 0);
14511
14512         return i;
14513 }
14514
14515 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14516 {
14517         struct cnic_ops *c_ops;
14518         int rc = 0;
14519
14520         mutex_lock(&bp->cnic_mutex);
14521         c_ops = rcu_dereference_protected(bp->cnic_ops,
14522                                           lockdep_is_held(&bp->cnic_mutex));
14523         if (c_ops)
14524                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14525         mutex_unlock(&bp->cnic_mutex);
14526
14527         return rc;
14528 }
14529
14530 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14531 {
14532         struct cnic_ops *c_ops;
14533         int rc = 0;
14534
14535         rcu_read_lock();
14536         c_ops = rcu_dereference(bp->cnic_ops);
14537         if (c_ops)
14538                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14539         rcu_read_unlock();
14540
14541         return rc;
14542 }
14543
14544 /*
14545  * for commands that have no data
14546  */
14547 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14548 {
14549         struct cnic_ctl_info ctl = {0};
14550
14551         ctl.cmd = cmd;
14552
14553         return bnx2x_cnic_ctl_send(bp, &ctl);
14554 }
14555
14556 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14557 {
14558         struct cnic_ctl_info ctl = {0};
14559
14560         /* first we tell CNIC and only then we count this as a completion */
14561         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14562         ctl.data.comp.cid = cid;
14563         ctl.data.comp.error = err;
14564
14565         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14566         bnx2x_cnic_sp_post(bp, 0);
14567 }
14568
14569 /* Called with netif_addr_lock_bh() taken.
14570  * Sets an rx_mode config for an iSCSI ETH client.
14571  * Doesn't block.
14572  * Completion should be checked outside.
14573  */
14574 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14575 {
14576         unsigned long accept_flags = 0, ramrod_flags = 0;
14577         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14578         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14579
14580         if (start) {
14581                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14582                  * because it's the only way for UIO Queue to accept
14583                  * multicasts (in non-promiscuous mode only one Queue per
14584                  * function will receive multicast packets (leading in our
14585                  * case).
14586                  */
14587                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14588                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14589                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14590                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14591
14592                 /* Clear STOP_PENDING bit if START is requested */
14593                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14594
14595                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14596         } else
14597                 /* Clear START_PENDING bit if STOP is requested */
14598                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14599
14600         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14601                 set_bit(sched_state, &bp->sp_state);
14602         else {
14603                 __set_bit(RAMROD_RX, &ramrod_flags);
14604                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14605                                     ramrod_flags);
14606         }
14607 }
14608
14609 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14610 {
14611         struct bnx2x *bp = netdev_priv(dev);
14612         int rc = 0;
14613
14614         switch (ctl->cmd) {
14615         case DRV_CTL_CTXTBL_WR_CMD: {
14616                 u32 index = ctl->data.io.offset;
14617                 dma_addr_t addr = ctl->data.io.dma_addr;
14618
14619                 bnx2x_ilt_wr(bp, index, addr);
14620                 break;
14621         }
14622
14623         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14624                 int count = ctl->data.credit.credit_count;
14625
14626                 bnx2x_cnic_sp_post(bp, count);
14627                 break;
14628         }
14629
14630         /* rtnl_lock is held.  */
14631         case DRV_CTL_START_L2_CMD: {
14632                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14633                 unsigned long sp_bits = 0;
14634
14635                 /* Configure the iSCSI classification object */
14636                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14637                                    cp->iscsi_l2_client_id,
14638                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14639                                    bnx2x_sp(bp, mac_rdata),
14640                                    bnx2x_sp_mapping(bp, mac_rdata),
14641                                    BNX2X_FILTER_MAC_PENDING,
14642                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14643                                    &bp->macs_pool);
14644
14645                 /* Set iSCSI MAC address */
14646                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14647                 if (rc)
14648                         break;
14649
14650                 mmiowb();
14651                 barrier();
14652
14653                 /* Start accepting on iSCSI L2 ring */
14654
14655                 netif_addr_lock_bh(dev);
14656                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14657                 netif_addr_unlock_bh(dev);
14658
14659                 /* bits to wait on */
14660                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14661                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14662
14663                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14664                         BNX2X_ERR("rx_mode completion timed out!\n");
14665
14666                 break;
14667         }
14668
14669         /* rtnl_lock is held.  */
14670         case DRV_CTL_STOP_L2_CMD: {
14671                 unsigned long sp_bits = 0;
14672
14673                 /* Stop accepting on iSCSI L2 ring */
14674                 netif_addr_lock_bh(dev);
14675                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14676                 netif_addr_unlock_bh(dev);
14677
14678                 /* bits to wait on */
14679                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14680                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14681
14682                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14683                         BNX2X_ERR("rx_mode completion timed out!\n");
14684
14685                 mmiowb();
14686                 barrier();
14687
14688                 /* Unset iSCSI L2 MAC */
14689                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14690                                         BNX2X_ISCSI_ETH_MAC, true);
14691                 break;
14692         }
14693         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14694                 int count = ctl->data.credit.credit_count;
14695
14696                 smp_mb__before_atomic();
14697                 atomic_add(count, &bp->cq_spq_left);
14698                 smp_mb__after_atomic();
14699                 break;
14700         }
14701         case DRV_CTL_ULP_REGISTER_CMD: {
14702                 int ulp_type = ctl->data.register_data.ulp_type;
14703
14704                 if (CHIP_IS_E3(bp)) {
14705                         int idx = BP_FW_MB_IDX(bp);
14706                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14707                         int path = BP_PATH(bp);
14708                         int port = BP_PORT(bp);
14709                         int i;
14710                         u32 scratch_offset;
14711                         u32 *host_addr;
14712
14713                         /* first write capability to shmem2 */
14714                         if (ulp_type == CNIC_ULP_ISCSI)
14715                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14716                         else if (ulp_type == CNIC_ULP_FCOE)
14717                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14718                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14719
14720                         if ((ulp_type != CNIC_ULP_FCOE) ||
14721                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14722                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14723                                 break;
14724
14725                         /* if reached here - should write fcoe capabilities */
14726                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14727                         if (!scratch_offset)
14728                                 break;
14729                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14730                                                    fcoe_features[path][port]);
14731                         host_addr = (u32 *) &(ctl->data.register_data.
14732                                               fcoe_features);
14733                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14734                              i += 4)
14735                                 REG_WR(bp, scratch_offset + i,
14736                                        *(host_addr + i/4));
14737                 }
14738                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14739                 break;
14740         }
14741
14742         case DRV_CTL_ULP_UNREGISTER_CMD: {
14743                 int ulp_type = ctl->data.ulp_type;
14744
14745                 if (CHIP_IS_E3(bp)) {
14746                         int idx = BP_FW_MB_IDX(bp);
14747                         u32 cap;
14748
14749                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14750                         if (ulp_type == CNIC_ULP_ISCSI)
14751                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14752                         else if (ulp_type == CNIC_ULP_FCOE)
14753                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14754                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14755                 }
14756                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14757                 break;
14758         }
14759
14760         default:
14761                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14762                 rc = -EINVAL;
14763         }
14764
14765         /* For storage-only interfaces, change driver state */
14766         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14767                 switch (ctl->drv_state) {
14768                 case DRV_NOP:
14769                         break;
14770                 case DRV_ACTIVE:
14771                         bnx2x_set_os_driver_state(bp,
14772                                                   OS_DRIVER_STATE_ACTIVE);
14773                         break;
14774                 case DRV_INACTIVE:
14775                         bnx2x_set_os_driver_state(bp,
14776                                                   OS_DRIVER_STATE_DISABLED);
14777                         break;
14778                 case DRV_UNLOADED:
14779                         bnx2x_set_os_driver_state(bp,
14780                                                   OS_DRIVER_STATE_NOT_LOADED);
14781                         break;
14782                 default:
14783                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14784                 }
14785         }
14786
14787         return rc;
14788 }
14789
14790 static int bnx2x_get_fc_npiv(struct net_device *dev,
14791                              struct cnic_fc_npiv_tbl *cnic_tbl)
14792 {
14793         struct bnx2x *bp = netdev_priv(dev);
14794         struct bdn_fc_npiv_tbl *tbl = NULL;
14795         u32 offset, entries;
14796         int rc = -EINVAL;
14797         int i;
14798
14799         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14800                 goto out;
14801
14802         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14803
14804         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14805         if (!tbl) {
14806                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14807                 goto out;
14808         }
14809
14810         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14811         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14812
14813         /* Read the table contents from nvram */
14814         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14815                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14816                 goto out;
14817         }
14818
14819         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14820          * the number of entries back to cpu endianness.
14821          */
14822         entries = tbl->fc_npiv_cfg.num_of_npiv;
14823         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14824         tbl->fc_npiv_cfg.num_of_npiv = entries;
14825
14826         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14827                 DP(BNX2X_MSG_MCP,
14828                    "No FC-NPIV table [valid, simply not present]\n");
14829                 goto out;
14830         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14831                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14832                           tbl->fc_npiv_cfg.num_of_npiv);
14833                 goto out;
14834         } else {
14835                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14836                    tbl->fc_npiv_cfg.num_of_npiv);
14837         }
14838
14839         /* Copy the data into cnic-provided struct */
14840         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14841         for (i = 0; i < cnic_tbl->count; i++) {
14842                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14843                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14844         }
14845
14846         rc = 0;
14847 out:
14848         kfree(tbl);
14849         return rc;
14850 }
14851
14852 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14853 {
14854         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14855
14856         if (bp->flags & USING_MSIX_FLAG) {
14857                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14858                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14859                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14860         } else {
14861                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14862                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14863         }
14864         if (!CHIP_IS_E1x(bp))
14865                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14866         else
14867                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14868
14869         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14870         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14871         cp->irq_arr[1].status_blk = bp->def_status_blk;
14872         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14873         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14874
14875         cp->num_irq = 2;
14876 }
14877
14878 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14879 {
14880         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14881
14882         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14883                              bnx2x_cid_ilt_lines(bp);
14884         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14885         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14886         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14887
14888         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14889            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14890            cp->iscsi_l2_cid);
14891
14892         if (NO_ISCSI_OOO(bp))
14893                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14894 }
14895
14896 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14897                                void *data)
14898 {
14899         struct bnx2x *bp = netdev_priv(dev);
14900         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14901         int rc;
14902
14903         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14904
14905         if (ops == NULL) {
14906                 BNX2X_ERR("NULL ops received\n");
14907                 return -EINVAL;
14908         }
14909
14910         if (!CNIC_SUPPORT(bp)) {
14911                 BNX2X_ERR("Can't register CNIC when not supported\n");
14912                 return -EOPNOTSUPP;
14913         }
14914
14915         if (!CNIC_LOADED(bp)) {
14916                 rc = bnx2x_load_cnic(bp);
14917                 if (rc) {
14918                         BNX2X_ERR("CNIC-related load failed\n");
14919                         return rc;
14920                 }
14921         }
14922
14923         bp->cnic_enabled = true;
14924
14925         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14926         if (!bp->cnic_kwq)
14927                 return -ENOMEM;
14928
14929         bp->cnic_kwq_cons = bp->cnic_kwq;
14930         bp->cnic_kwq_prod = bp->cnic_kwq;
14931         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14932
14933         bp->cnic_spq_pending = 0;
14934         bp->cnic_kwq_pending = 0;
14935
14936         bp->cnic_data = data;
14937
14938         cp->num_irq = 0;
14939         cp->drv_state |= CNIC_DRV_STATE_REGD;
14940         cp->iro_arr = bp->iro_arr;
14941
14942         bnx2x_setup_cnic_irq_info(bp);
14943
14944         rcu_assign_pointer(bp->cnic_ops, ops);
14945
14946         /* Schedule driver to read CNIC driver versions */
14947         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14948
14949         return 0;
14950 }
14951
14952 static int bnx2x_unregister_cnic(struct net_device *dev)
14953 {
14954         struct bnx2x *bp = netdev_priv(dev);
14955         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14956
14957         mutex_lock(&bp->cnic_mutex);
14958         cp->drv_state = 0;
14959         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14960         mutex_unlock(&bp->cnic_mutex);
14961         synchronize_rcu();
14962         bp->cnic_enabled = false;
14963         kfree(bp->cnic_kwq);
14964         bp->cnic_kwq = NULL;
14965
14966         return 0;
14967 }
14968
14969 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14970 {
14971         struct bnx2x *bp = netdev_priv(dev);
14972         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14973
14974         /* If both iSCSI and FCoE are disabled - return NULL in
14975          * order to indicate CNIC that it should not try to work
14976          * with this device.
14977          */
14978         if (NO_ISCSI(bp) && NO_FCOE(bp))
14979                 return NULL;
14980
14981         cp->drv_owner = THIS_MODULE;
14982         cp->chip_id = CHIP_ID(bp);
14983         cp->pdev = bp->pdev;
14984         cp->io_base = bp->regview;
14985         cp->io_base2 = bp->doorbells;
14986         cp->max_kwqe_pending = 8;
14987         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14988         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14989                              bnx2x_cid_ilt_lines(bp);
14990         cp->ctx_tbl_len = CNIC_ILT_LINES;
14991         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14992         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14993         cp->drv_ctl = bnx2x_drv_ctl;
14994         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
14995         cp->drv_register_cnic = bnx2x_register_cnic;
14996         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14997         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14998         cp->iscsi_l2_client_id =
14999                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15000         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15001
15002         if (NO_ISCSI_OOO(bp))
15003                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15004
15005         if (NO_ISCSI(bp))
15006                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15007
15008         if (NO_FCOE(bp))
15009                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15010
15011         BNX2X_DEV_INFO(
15012                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15013            cp->ctx_blk_size,
15014            cp->ctx_tbl_offset,
15015            cp->ctx_tbl_len,
15016            cp->starting_cid);
15017         return cp;
15018 }
15019
15020 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15021 {
15022         struct bnx2x *bp = fp->bp;
15023         u32 offset = BAR_USTRORM_INTMEM;
15024
15025         if (IS_VF(bp))
15026                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15027         else if (!CHIP_IS_E1x(bp))
15028                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15029         else
15030                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15031
15032         return offset;
15033 }
15034
15035 /* called only on E1H or E2.
15036  * When pretending to be PF, the pretend value is the function number 0...7
15037  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15038  * combination
15039  */
15040 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15041 {
15042         u32 pretend_reg;
15043
15044         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15045                 return -1;
15046
15047         /* get my own pretend register */
15048         pretend_reg = bnx2x_get_pretend_reg(bp);
15049         REG_WR(bp, pretend_reg, pretend_func_val);
15050         REG_RD(bp, pretend_reg);
15051         return 0;
15052 }
15053
15054 static void bnx2x_ptp_task(struct work_struct *work)
15055 {
15056         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15057         int port = BP_PORT(bp);
15058         u32 val_seq;
15059         u64 timestamp, ns;
15060         struct skb_shared_hwtstamps shhwtstamps;
15061
15062         /* Read Tx timestamp registers */
15063         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15064                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15065         if (val_seq & 0x10000) {
15066                 /* There is a valid timestamp value */
15067                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15068                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15069                 timestamp <<= 32;
15070                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15071                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15072                 /* Reset timestamp register to allow new timestamp */
15073                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15074                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15075                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15076
15077                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15078                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15079                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15080                 dev_kfree_skb_any(bp->ptp_tx_skb);
15081                 bp->ptp_tx_skb = NULL;
15082
15083                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15084                    timestamp, ns);
15085         } else {
15086                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15087                 /* Reschedule to keep checking for a valid timestamp value */
15088                 schedule_work(&bp->ptp_task);
15089         }
15090 }
15091
15092 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15093 {
15094         int port = BP_PORT(bp);
15095         u64 timestamp, ns;
15096
15097         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15098                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15099         timestamp <<= 32;
15100         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15101                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15102
15103         /* Reset timestamp register to allow new timestamp */
15104         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15105                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15106
15107         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15108
15109         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15110
15111         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15112            timestamp, ns);
15113 }
15114
15115 /* Read the PHC */
15116 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15117 {
15118         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15119         int port = BP_PORT(bp);
15120         u32 wb_data[2];
15121         u64 phc_cycles;
15122
15123         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15124                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15125         phc_cycles = wb_data[1];
15126         phc_cycles = (phc_cycles << 32) + wb_data[0];
15127
15128         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15129
15130         return phc_cycles;
15131 }
15132
15133 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15134 {
15135         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15136         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15137         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15138         bp->cyclecounter.shift = 1;
15139         bp->cyclecounter.mult = 1;
15140 }
15141
15142 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15143 {
15144         struct bnx2x_func_state_params func_params = {NULL};
15145         struct bnx2x_func_set_timesync_params *set_timesync_params =
15146                 &func_params.params.set_timesync;
15147
15148         /* Prepare parameters for function state transitions */
15149         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15150         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15151
15152         func_params.f_obj = &bp->func_obj;
15153         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15154
15155         /* Function parameters */
15156         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15157         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15158
15159         return bnx2x_func_state_change(bp, &func_params);
15160 }
15161
15162 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15163 {
15164         struct bnx2x_queue_state_params q_params;
15165         int rc, i;
15166
15167         /* send queue update ramrod to enable PTP packets */
15168         memset(&q_params, 0, sizeof(q_params));
15169         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15170         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15171         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15172                   &q_params.params.update.update_flags);
15173         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15174                   &q_params.params.update.update_flags);
15175
15176         /* send the ramrod on all the queues of the PF */
15177         for_each_eth_queue(bp, i) {
15178                 struct bnx2x_fastpath *fp = &bp->fp[i];
15179
15180                 /* Set the appropriate Queue object */
15181                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15182
15183                 /* Update the Queue state */
15184                 rc = bnx2x_queue_state_change(bp, &q_params);
15185                 if (rc) {
15186                         BNX2X_ERR("Failed to enable PTP packets\n");
15187                         return rc;
15188                 }
15189         }
15190
15191         return 0;
15192 }
15193
15194 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15195 {
15196         int port = BP_PORT(bp);
15197         int rc;
15198
15199         if (!bp->hwtstamp_ioctl_called)
15200                 return 0;
15201
15202         switch (bp->tx_type) {
15203         case HWTSTAMP_TX_ON:
15204                 bp->flags |= TX_TIMESTAMPING_EN;
15205                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15206                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15207                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15208                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15209                 break;
15210         case HWTSTAMP_TX_ONESTEP_SYNC:
15211                 BNX2X_ERR("One-step timestamping is not supported\n");
15212                 return -ERANGE;
15213         }
15214
15215         switch (bp->rx_filter) {
15216         case HWTSTAMP_FILTER_NONE:
15217                 break;
15218         case HWTSTAMP_FILTER_ALL:
15219         case HWTSTAMP_FILTER_SOME:
15220                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15221                 break;
15222         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15223         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15224         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15225                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15226                 /* Initialize PTP detection for UDP/IPv4 events */
15227                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15228                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15229                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15230                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15231                 break;
15232         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15233         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15234         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15235                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15236                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15237                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15238                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15239                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15240                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15241                 break;
15242         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15243         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15244         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15245                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15246                 /* Initialize PTP detection L2 events */
15247                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15248                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15249                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15250                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15251
15252                 break;
15253         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15254         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15255         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15256                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15257                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15258                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15259                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15260                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15261                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15262                 break;
15263         }
15264
15265         /* Indicate to FW that this PF expects recorded PTP packets */
15266         rc = bnx2x_enable_ptp_packets(bp);
15267         if (rc)
15268                 return rc;
15269
15270         /* Enable sending PTP packets to host */
15271         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15272                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15273
15274         return 0;
15275 }
15276
15277 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15278 {
15279         struct hwtstamp_config config;
15280         int rc;
15281
15282         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15283
15284         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15285                 return -EFAULT;
15286
15287         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15288            config.tx_type, config.rx_filter);
15289
15290         if (config.flags) {
15291                 BNX2X_ERR("config.flags is reserved for future use\n");
15292                 return -EINVAL;
15293         }
15294
15295         bp->hwtstamp_ioctl_called = 1;
15296         bp->tx_type = config.tx_type;
15297         bp->rx_filter = config.rx_filter;
15298
15299         rc = bnx2x_configure_ptp_filters(bp);
15300         if (rc)
15301                 return rc;
15302
15303         config.rx_filter = bp->rx_filter;
15304
15305         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15306                 -EFAULT : 0;
15307 }
15308
15309 /* Configures HW for PTP */
15310 static int bnx2x_configure_ptp(struct bnx2x *bp)
15311 {
15312         int rc, port = BP_PORT(bp);
15313         u32 wb_data[2];
15314
15315         /* Reset PTP event detection rules - will be configured in the IOCTL */
15316         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15317                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15318         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15319                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15320         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15321                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15322         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15323                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15324
15325         /* Disable PTP packets to host - will be configured in the IOCTL*/
15326         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15327                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15328
15329         /* Enable the PTP feature */
15330         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15331                NIG_REG_P0_PTP_EN, 0x3F);
15332
15333         /* Enable the free-running counter */
15334         wb_data[0] = 0;
15335         wb_data[1] = 0;
15336         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15337
15338         /* Reset drift register (offset register is not reset) */
15339         rc = bnx2x_send_reset_timesync_ramrod(bp);
15340         if (rc) {
15341                 BNX2X_ERR("Failed to reset PHC drift register\n");
15342                 return -EFAULT;
15343         }
15344
15345         /* Reset possibly old timestamps */
15346         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15347                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15348         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15349                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15350
15351         return 0;
15352 }
15353
15354 /* Called during load, to initialize PTP-related stuff */
15355 void bnx2x_init_ptp(struct bnx2x *bp)
15356 {
15357         int rc;
15358
15359         /* Configure PTP in HW */
15360         rc = bnx2x_configure_ptp(bp);
15361         if (rc) {
15362                 BNX2X_ERR("Stopping PTP initialization\n");
15363                 return;
15364         }
15365
15366         /* Init work queue for Tx timestamping */
15367         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15368
15369         /* Init cyclecounter and timecounter. This is done only in the first
15370          * load. If done in every load, PTP application will fail when doing
15371          * unload / load (e.g. MTU change) while it is running.
15372          */
15373         if (!bp->timecounter_init_done) {
15374                 bnx2x_init_cyclecounter(bp);
15375                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15376                                  ktime_to_ns(ktime_get_real()));
15377                 bp->timecounter_init_done = 1;
15378         }
15379
15380         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15381 }