1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
81 static char version[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 module_param(int_mode, int, 0);
107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 static int dropless_fc;
111 module_param(dropless_fc, int, 0);
112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 static int mrrs = -1;
115 module_param(mrrs, int, 0);
116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 module_param(debug, int, 0);
120 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 struct workqueue_struct *bnx2x_wq;
124 struct bnx2x_mac_vals {
135 enum bnx2x_board_type {
159 /* indexed by board_type, above */
163 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
164 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
165 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
166 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
167 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
168 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
169 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
170 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
171 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
172 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
173 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
174 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
175 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
176 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
177 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
178 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
179 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
180 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
181 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
182 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 #ifndef PCI_DEVICE_ID_NX2_57710
187 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189 #ifndef PCI_DEVICE_ID_NX2_57711
190 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192 #ifndef PCI_DEVICE_ID_NX2_57711E
193 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195 #ifndef PCI_DEVICE_ID_NX2_57712
196 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
199 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
202 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204 #ifndef PCI_DEVICE_ID_NX2_57800
205 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
208 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
211 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213 #ifndef PCI_DEVICE_ID_NX2_57810
214 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
217 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219 #ifndef PCI_DEVICE_ID_NX2_57840_O
220 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
223 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
226 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
229 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
232 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
235 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
238 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240 #ifndef PCI_DEVICE_ID_NX2_57811
241 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
244 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
247 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277 /* Global resources for unloading a previously loaded device */
278 #define BNX2X_PREV_WAIT_NEEDED 1
279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
280 static LIST_HEAD(bnx2x_prev_list);
281 /****************************************************************************
282 * General service functions
283 ****************************************************************************/
285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
286 u32 addr, dma_addr_t mapping)
288 REG_WR(bp, addr, U64_LO(mapping));
289 REG_WR(bp, addr + 4, U64_HI(mapping));
292 static void storm_memset_spq_addr(struct bnx2x *bp,
293 dma_addr_t mapping, u16 abs_fid)
295 u32 addr = XSEM_REG_FAST_MEMORY +
296 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
298 __storm_memset_dma_mapping(bp, addr, mapping);
301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
304 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
306 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
308 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
310 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
327 static void storm_memset_eq_data(struct bnx2x *bp,
328 struct event_ring_data *eq_data,
331 size_t size = sizeof(struct event_ring_data);
333 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
335 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
342 REG_WR16(bp, addr, eq_prod);
346 * locking is done by mcp
348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
350 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
351 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
353 PCICFG_VENDOR_ID_OFFSET);
356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
368 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
369 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
370 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
371 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
372 #define DMAE_DP_DST_NONE "dst_addr [none]"
374 static void bnx2x_dp_dmae(struct bnx2x *bp,
375 struct dmae_command *dmae, int msglvl)
377 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
380 switch (dmae->opcode & DMAE_COMMAND_DST) {
381 case DMAE_CMD_DST_PCI:
382 if (src_type == DMAE_CMD_SRC_PCI)
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
387 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
391 DP(msglvl, "DMAE: opcode 0x%08x\n"
392 "src [%08x], len [%d*4], dst [%x:%08x]\n"
393 "comp_addr [%x:%08x], comp_val 0x%08x\n",
394 dmae->opcode, dmae->src_addr_lo >> 2,
395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 case DMAE_CMD_DST_GRC:
400 if (src_type == DMAE_CMD_SRC_PCI)
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
405 dmae->len, dmae->dst_addr_lo >> 2,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_lo >> 2,
413 dmae->len, dmae->dst_addr_lo >> 2,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
418 if (src_type == DMAE_CMD_SRC_PCI)
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
421 "comp_addr [%x:%08x] comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
423 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_lo >> 2,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
435 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
436 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
437 i, *(((u32 *)dmae) + i));
440 /* copy command into DMAE command memory and set DMAE command go */
441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
446 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
448 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 REG_WR(bp, dmae_reg_go_c[idx], 1);
453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 return opcode & ~DMAE_CMD_SRC_RESET;
464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
465 bool with_comp, u8 comp_type)
469 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
470 (dst_type << DMAE_COMMAND_DST_SHIFT));
472 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
475 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
476 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
477 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
480 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
485 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
490 struct dmae_command *dmae,
491 u8 src_type, u8 dst_type)
493 memset(dmae, 0, sizeof(struct dmae_command));
496 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
497 true, DMAE_COMP_PCI);
499 /* fill in the completion parameters */
500 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
501 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_val = DMAE_COMP_VAL;
505 /* issue a dmae command over the init-channel and wait for completion */
506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
508 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
512 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
514 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
518 spin_lock_bh(&bp->dmae_lock);
520 /* reset completion */
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
526 /* wait for completion */
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
546 spin_unlock_bh(&bp->dmae_lock);
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
554 struct dmae_command dmae;
556 if (!bp->dmae_ready) {
557 u32 *data = bnx2x_sp(bp, wb_data[0]);
560 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
562 bnx2x_init_str_wr(bp, dst_addr, data, len32);
566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
569 /* fill in addresses and len */
570 dmae.src_addr_lo = U64_LO(dma_addr);
571 dmae.src_addr_hi = U64_HI(dma_addr);
572 dmae.dst_addr_lo = dst_addr >> 2;
573 dmae.dst_addr_hi = 0;
576 /* issue the command and wait for completion */
577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
579 BNX2X_ERR("DMAE returned failure %d\n", rc);
584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
587 struct dmae_command dmae;
589 if (!bp->dmae_ready) {
590 u32 *data = bnx2x_sp(bp, wb_data[0]);
594 for (i = 0; i < len32; i++)
595 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
597 for (i = 0; i < len32; i++)
598 data[i] = REG_RD(bp, src_addr + i*4);
603 /* set opcode and fixed command fields */
604 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
606 /* fill in addresses and len */
607 dmae.src_addr_lo = src_addr >> 2;
608 dmae.src_addr_hi = 0;
609 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
610 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
613 /* issue the command and wait for completion */
614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
616 BNX2X_ERR("DMAE returned failure %d\n", rc);
621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
624 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
627 while (len > dmae_wr_max) {
628 bnx2x_write_dmae(bp, phys_addr + offset,
629 addr + offset, dmae_wr_max);
630 offset += dmae_wr_max * 4;
634 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
637 static int bnx2x_mc_assert(struct bnx2x *bp)
641 u32 row0, row1, row2, row3;
644 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_INDEX_OFFSET);
647 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
649 /* print the asserts */
650 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
652 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
653 XSTORM_ASSERT_LIST_OFFSET(i));
654 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
655 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
656 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
657 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
658 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
659 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
661 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
662 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
663 i, row3, row2, row1, row0);
671 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_INDEX_OFFSET);
674 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
676 /* print the asserts */
677 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
679 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
680 TSTORM_ASSERT_LIST_OFFSET(i));
681 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
682 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
683 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
684 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
685 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
686 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
688 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
689 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
690 i, row3, row2, row1, row0);
698 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_INDEX_OFFSET);
701 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
703 /* print the asserts */
704 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
706 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
707 CSTORM_ASSERT_LIST_OFFSET(i));
708 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
709 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
710 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
711 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
712 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
713 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
715 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
716 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
717 i, row3, row2, row1, row0);
725 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_INDEX_OFFSET);
728 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
730 /* print the asserts */
731 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
733 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
734 USTORM_ASSERT_LIST_OFFSET(i));
735 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
736 USTORM_ASSERT_LIST_OFFSET(i) + 4);
737 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
738 USTORM_ASSERT_LIST_OFFSET(i) + 8);
739 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
740 USTORM_ASSERT_LIST_OFFSET(i) + 12);
742 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
743 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
744 i, row3, row2, row1, row0);
754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
760 u32 trace_shmem_base;
762 BNX2X_ERR("NO MCP - can not dump\n");
765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766 (bp->common.bc_ver & 0xff0000) >> 16,
767 (bp->common.bc_ver & 0xff00) >> 8,
768 (bp->common.bc_ver & 0xff));
770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
774 if (BP_PATH(bp) == 0)
775 trace_shmem_base = bp->common.shmem_base;
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778 addr = trace_shmem_base - 0x800;
780 /* validate TRCB signature */
781 mark = REG_RD(bp, addr);
782 if (mark != MFW_TRACE_SIGNATURE) {
783 BNX2X_ERR("Trace buffer signature is missing.");
787 /* read cyclic buffer pointer */
789 mark = REG_RD(bp, addr);
790 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
791 + ((mark + 0x3) & ~0x3) - 0x08000000;
792 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
796 /* dump buffer after the mark */
797 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
798 for (word = 0; word < 8; word++)
799 data[word] = htonl(REG_RD(bp, offset + 4*word));
801 pr_cont("%s", (char *)data);
804 /* dump buffer before the mark */
805 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
806 for (word = 0; word < 8; word++)
807 data[word] = htonl(REG_RD(bp, offset + 4*word));
809 pr_cont("%s", (char *)data);
811 printk("%s" "end of fw dump\n", lvl);
814 static void bnx2x_fw_dump(struct bnx2x *bp)
816 bnx2x_fw_dump_lvl(bp, KERN_ERR);
819 static void bnx2x_hc_int_disable(struct bnx2x *bp)
821 int port = BP_PORT(bp);
822 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
823 u32 val = REG_RD(bp, addr);
825 /* in E1 we must use only PCI configuration space to disable
826 * MSI/MSIX capability
827 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
829 if (CHIP_IS_E1(bp)) {
830 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
831 * Use mask register to prevent from HC sending interrupts
832 * after we exit the function
834 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
836 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
837 HC_CONFIG_0_REG_INT_LINE_EN_0 |
838 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
840 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
841 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
842 HC_CONFIG_0_REG_INT_LINE_EN_0 |
843 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
846 "write %x to HC %d (addr 0x%x)\n",
849 /* flush all outstanding writes */
852 REG_WR(bp, addr, val);
853 if (REG_RD(bp, addr) != val)
854 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
857 static void bnx2x_igu_int_disable(struct bnx2x *bp)
859 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
861 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
862 IGU_PF_CONF_INT_LINE_EN |
863 IGU_PF_CONF_ATTN_BIT_EN);
865 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
867 /* flush all outstanding writes */
870 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
871 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
872 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
875 static void bnx2x_int_disable(struct bnx2x *bp)
877 if (bp->common.int_block == INT_BLOCK_HC)
878 bnx2x_hc_int_disable(bp);
880 bnx2x_igu_int_disable(bp);
883 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
887 struct hc_sp_status_block_data sp_sb_data;
888 int func = BP_FUNC(bp);
889 #ifdef BNX2X_STOP_ON_ERROR
890 u16 start = 0, end = 0;
894 bnx2x_int_disable(bp);
896 bp->stats_state = STATS_STATE_DISABLED;
897 bp->eth_stats.unrecoverable_error++;
898 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
900 BNX2X_ERR("begin crash dump -----------------\n");
904 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
905 bp->def_idx, bp->def_att_idx, bp->attn_state,
906 bp->spq_prod_idx, bp->stats_counter);
907 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
908 bp->def_status_blk->atten_status_block.attn_bits,
909 bp->def_status_blk->atten_status_block.attn_bits_ack,
910 bp->def_status_blk->atten_status_block.status_block_id,
911 bp->def_status_blk->atten_status_block.attn_bits_index);
913 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
915 bp->def_status_blk->sp_sb.index_values[i],
916 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
918 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
919 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
920 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
923 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
924 sp_sb_data.igu_sb_id,
925 sp_sb_data.igu_seg_id,
926 sp_sb_data.p_func.pf_id,
927 sp_sb_data.p_func.vnic_id,
928 sp_sb_data.p_func.vf_id,
929 sp_sb_data.p_func.vf_valid,
932 for_each_eth_queue(bp, i) {
933 struct bnx2x_fastpath *fp = &bp->fp[i];
935 struct hc_status_block_data_e2 sb_data_e2;
936 struct hc_status_block_data_e1x sb_data_e1x;
937 struct hc_status_block_sm *hc_sm_p =
939 sb_data_e1x.common.state_machine :
940 sb_data_e2.common.state_machine;
941 struct hc_index_data *hc_index_p =
943 sb_data_e1x.index_data :
944 sb_data_e2.index_data;
947 struct bnx2x_fp_txdata txdata;
950 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
951 i, fp->rx_bd_prod, fp->rx_bd_cons,
953 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
954 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
955 fp->rx_sge_prod, fp->last_max_sge,
956 le16_to_cpu(fp->fp_hc_idx));
959 for_each_cos_in_tx_queue(fp, cos)
961 txdata = *fp->txdata_ptr[cos];
962 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
963 i, txdata.tx_pkt_prod,
964 txdata.tx_pkt_cons, txdata.tx_bd_prod,
966 le16_to_cpu(*txdata.tx_cons_sb));
969 loop = CHIP_IS_E1x(bp) ?
970 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
977 BNX2X_ERR(" run indexes (");
978 for (j = 0; j < HC_SB_MAX_SM; j++)
980 fp->sb_running_index[j],
981 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
983 BNX2X_ERR(" indexes (");
984 for (j = 0; j < loop; j++)
986 fp->sb_index_values[j],
987 (j == loop - 1) ? ")" : " ");
989 data_size = CHIP_IS_E1x(bp) ?
990 sizeof(struct hc_status_block_data_e1x) :
991 sizeof(struct hc_status_block_data_e2);
992 data_size /= sizeof(u32);
993 sb_data_p = CHIP_IS_E1x(bp) ?
994 (u32 *)&sb_data_e1x :
996 /* copy sb data in here */
997 for (j = 0; j < data_size; j++)
998 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
999 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1002 if (!CHIP_IS_E1x(bp)) {
1003 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1004 sb_data_e2.common.p_func.pf_id,
1005 sb_data_e2.common.p_func.vf_id,
1006 sb_data_e2.common.p_func.vf_valid,
1007 sb_data_e2.common.p_func.vnic_id,
1008 sb_data_e2.common.same_igu_sb_1b,
1009 sb_data_e2.common.state);
1011 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1012 sb_data_e1x.common.p_func.pf_id,
1013 sb_data_e1x.common.p_func.vf_id,
1014 sb_data_e1x.common.p_func.vf_valid,
1015 sb_data_e1x.common.p_func.vnic_id,
1016 sb_data_e1x.common.same_igu_sb_1b,
1017 sb_data_e1x.common.state);
1021 for (j = 0; j < HC_SB_MAX_SM; j++) {
1022 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1023 j, hc_sm_p[j].__flags,
1024 hc_sm_p[j].igu_sb_id,
1025 hc_sm_p[j].igu_seg_id,
1026 hc_sm_p[j].time_to_expire,
1027 hc_sm_p[j].timer_value);
1031 for (j = 0; j < loop; j++) {
1032 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1038 #ifdef BNX2X_STOP_ON_ERROR
1041 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1042 for (i = 0; i < NUM_EQ_DESC; i++) {
1043 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1045 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1046 i, bp->eq_ring[i].message.opcode,
1047 bp->eq_ring[i].message.error);
1048 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1053 for_each_valid_rx_queue(bp, i) {
1054 struct bnx2x_fastpath *fp = &bp->fp[i];
1056 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1057 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1058 for (j = start; j != end; j = RX_BD(j + 1)) {
1059 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1060 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1062 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1063 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1066 start = RX_SGE(fp->rx_sge_prod);
1067 end = RX_SGE(fp->last_max_sge);
1068 for (j = start; j != end; j = RX_SGE(j + 1)) {
1069 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1070 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1072 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1073 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1076 start = RCQ_BD(fp->rx_comp_cons - 10);
1077 end = RCQ_BD(fp->rx_comp_cons + 503);
1078 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1079 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1081 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1082 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1087 for_each_valid_tx_queue(bp, i) {
1088 struct bnx2x_fastpath *fp = &bp->fp[i];
1089 for_each_cos_in_tx_queue(fp, cos) {
1090 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1092 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1093 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1094 for (j = start; j != end; j = TX_BD(j + 1)) {
1095 struct sw_tx_bd *sw_bd =
1096 &txdata->tx_buf_ring[j];
1098 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1099 i, cos, j, sw_bd->skb,
1103 start = TX_BD(txdata->tx_bd_cons - 10);
1104 end = TX_BD(txdata->tx_bd_cons + 254);
1105 for (j = start; j != end; j = TX_BD(j + 1)) {
1106 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1108 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1109 i, cos, j, tx_bd[0], tx_bd[1],
1110 tx_bd[2], tx_bd[3]);
1116 bnx2x_mc_assert(bp);
1117 BNX2X_ERR("end crash dump -----------------\n");
1121 * FLR Support for E2
1123 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1126 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1127 #define FLR_WAIT_INTERVAL 50 /* usec */
1128 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1130 struct pbf_pN_buf_regs {
1137 struct pbf_pN_cmd_regs {
1143 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1144 struct pbf_pN_buf_regs *regs,
1147 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1148 u32 cur_cnt = poll_count;
1150 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1151 crd = crd_start = REG_RD(bp, regs->crd);
1152 init_crd = REG_RD(bp, regs->init_crd);
1154 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1155 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1156 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1158 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1159 (init_crd - crd_start))) {
1161 udelay(FLR_WAIT_INTERVAL);
1162 crd = REG_RD(bp, regs->crd);
1163 crd_freed = REG_RD(bp, regs->crd_freed);
1165 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1167 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1169 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1170 regs->pN, crd_freed);
1174 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1175 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1178 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1179 struct pbf_pN_cmd_regs *regs,
1182 u32 occup, to_free, freed, freed_start;
1183 u32 cur_cnt = poll_count;
1185 occup = to_free = REG_RD(bp, regs->lines_occup);
1186 freed = freed_start = REG_RD(bp, regs->lines_freed);
1188 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1189 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1191 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1193 udelay(FLR_WAIT_INTERVAL);
1194 occup = REG_RD(bp, regs->lines_occup);
1195 freed = REG_RD(bp, regs->lines_freed);
1197 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1199 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1201 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1206 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1207 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1210 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1211 u32 expected, u32 poll_count)
1213 u32 cur_cnt = poll_count;
1216 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1217 udelay(FLR_WAIT_INTERVAL);
1222 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1223 char *msg, u32 poll_cnt)
1225 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1227 BNX2X_ERR("%s usage count=%d\n", msg, val);
1233 /* Common routines with VF FLR cleanup */
1234 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1236 /* adjust polling timeout */
1237 if (CHIP_REV_IS_EMUL(bp))
1238 return FLR_POLL_CNT * 2000;
1240 if (CHIP_REV_IS_FPGA(bp))
1241 return FLR_POLL_CNT * 120;
1243 return FLR_POLL_CNT;
1246 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1248 struct pbf_pN_cmd_regs cmd_regs[] = {
1249 {0, (CHIP_IS_E3B0(bp)) ?
1250 PBF_REG_TQ_OCCUPANCY_Q0 :
1251 PBF_REG_P0_TQ_OCCUPANCY,
1252 (CHIP_IS_E3B0(bp)) ?
1253 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1254 PBF_REG_P0_TQ_LINES_FREED_CNT},
1255 {1, (CHIP_IS_E3B0(bp)) ?
1256 PBF_REG_TQ_OCCUPANCY_Q1 :
1257 PBF_REG_P1_TQ_OCCUPANCY,
1258 (CHIP_IS_E3B0(bp)) ?
1259 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1260 PBF_REG_P1_TQ_LINES_FREED_CNT},
1261 {4, (CHIP_IS_E3B0(bp)) ?
1262 PBF_REG_TQ_OCCUPANCY_LB_Q :
1263 PBF_REG_P4_TQ_OCCUPANCY,
1264 (CHIP_IS_E3B0(bp)) ?
1265 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1266 PBF_REG_P4_TQ_LINES_FREED_CNT}
1269 struct pbf_pN_buf_regs buf_regs[] = {
1270 {0, (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_INIT_CRD_Q0 :
1272 PBF_REG_P0_INIT_CRD ,
1273 (CHIP_IS_E3B0(bp)) ?
1276 (CHIP_IS_E3B0(bp)) ?
1277 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1278 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1279 {1, (CHIP_IS_E3B0(bp)) ?
1280 PBF_REG_INIT_CRD_Q1 :
1281 PBF_REG_P1_INIT_CRD,
1282 (CHIP_IS_E3B0(bp)) ?
1285 (CHIP_IS_E3B0(bp)) ?
1286 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1287 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1288 {4, (CHIP_IS_E3B0(bp)) ?
1289 PBF_REG_INIT_CRD_LB_Q :
1290 PBF_REG_P4_INIT_CRD,
1291 (CHIP_IS_E3B0(bp)) ?
1292 PBF_REG_CREDIT_LB_Q :
1294 (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1296 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1301 /* Verify the command queues are flushed P0, P1, P4 */
1302 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1303 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1305 /* Verify the transmission buffers are flushed P0, P1, P4 */
1306 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1307 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1310 #define OP_GEN_PARAM(param) \
1311 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1313 #define OP_GEN_TYPE(type) \
1314 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1316 #define OP_GEN_AGG_VECT(index) \
1317 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1319 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1321 u32 op_gen_command = 0;
1322 u32 comp_addr = BAR_CSTRORM_INTMEM +
1323 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1326 if (REG_RD(bp, comp_addr)) {
1327 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1331 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1332 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1333 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1334 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1336 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1337 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1339 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1340 BNX2X_ERR("FW final cleanup did not succeed\n");
1341 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1342 (REG_RD(bp, comp_addr)));
1346 /* Zero completion for next FLR */
1347 REG_WR(bp, comp_addr, 0);
1352 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1356 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1357 return status & PCI_EXP_DEVSTA_TRPND;
1360 /* PF FLR specific routines
1362 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1364 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1365 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366 CFC_REG_NUM_LCIDS_INSIDE_PF,
1367 "CFC PF usage counter timed out",
1371 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1372 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373 DORQ_REG_PF_USAGE_CNT,
1374 "DQ PF usage counter timed out",
1378 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1379 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1381 "QM PF usage counter timed out",
1385 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1386 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1388 "Timers VNIC usage counter timed out",
1391 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1393 "Timers NUM_SCANS usage counter timed out",
1397 /* Wait DMAE PF usage counter to zero */
1398 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1399 dmae_reg_go_c[INIT_DMAE_C(bp)],
1400 "DMAE command register timed out",
1407 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1411 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1412 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1414 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1415 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1417 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1418 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1420 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1421 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1423 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1424 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1426 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1427 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1429 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1430 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1432 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1433 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1437 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1439 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1441 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1443 /* Re-enable PF target read access */
1444 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1446 /* Poll HW usage counters */
1447 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1448 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1451 /* Zero the igu 'trailing edge' and 'leading edge' */
1453 /* Send the FW cleanup command */
1454 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1459 /* Verify TX hw is flushed */
1460 bnx2x_tx_hw_flushed(bp, poll_cnt);
1462 /* Wait 100ms (not adjusted according to platform) */
1465 /* Verify no pending pci transactions */
1466 if (bnx2x_is_pcie_pending(bp->pdev))
1467 BNX2X_ERR("PCIE Transactions still pending\n");
1470 bnx2x_hw_enable_status(bp);
1473 * Master enable - Due to WB DMAE writes performed before this
1474 * register is re-initialized as part of the regular function init
1476 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1481 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1483 int port = BP_PORT(bp);
1484 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1485 u32 val = REG_RD(bp, addr);
1486 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1487 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1488 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1491 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1492 HC_CONFIG_0_REG_INT_LINE_EN_0);
1493 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1496 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1498 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1499 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1500 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1503 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1504 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1505 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1506 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1508 if (!CHIP_IS_E1(bp)) {
1510 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1512 REG_WR(bp, addr, val);
1514 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1519 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1522 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1523 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1525 REG_WR(bp, addr, val);
1527 * Ensure that HC_CONFIG is written before leading/trailing edge config
1532 if (!CHIP_IS_E1(bp)) {
1533 /* init leading/trailing edge */
1535 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1537 /* enable nig and gpio3 attention */
1542 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1543 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1546 /* Make sure that interrupts are indeed enabled from here on */
1550 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1553 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1554 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1555 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1557 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1560 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1561 IGU_PF_CONF_SINGLE_ISR_EN);
1562 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563 IGU_PF_CONF_ATTN_BIT_EN);
1566 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1568 val &= ~IGU_PF_CONF_INT_LINE_EN;
1569 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1570 IGU_PF_CONF_ATTN_BIT_EN |
1571 IGU_PF_CONF_SINGLE_ISR_EN);
1573 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1574 val |= (IGU_PF_CONF_INT_LINE_EN |
1575 IGU_PF_CONF_ATTN_BIT_EN |
1576 IGU_PF_CONF_SINGLE_ISR_EN);
1579 /* Clean previous status - need to configure igu prior to ack*/
1580 if ((!msix) || single_msix) {
1581 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1585 val |= IGU_PF_CONF_FUNC_EN;
1587 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1588 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1590 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1592 if (val & IGU_PF_CONF_INT_LINE_EN)
1593 pci_intx(bp->pdev, true);
1597 /* init leading/trailing edge */
1599 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1601 /* enable nig and gpio3 attention */
1606 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1607 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1609 /* Make sure that interrupts are indeed enabled from here on */
1613 void bnx2x_int_enable(struct bnx2x *bp)
1615 if (bp->common.int_block == INT_BLOCK_HC)
1616 bnx2x_hc_int_enable(bp);
1618 bnx2x_igu_int_enable(bp);
1621 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1623 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1627 /* prevent the HW from sending interrupts */
1628 bnx2x_int_disable(bp);
1630 /* make sure all ISRs are done */
1632 synchronize_irq(bp->msix_table[0].vector);
1634 if (CNIC_SUPPORT(bp))
1636 for_each_eth_queue(bp, i)
1637 synchronize_irq(bp->msix_table[offset++].vector);
1639 synchronize_irq(bp->pdev->irq);
1641 /* make sure sp_task is not running */
1642 cancel_delayed_work(&bp->sp_task);
1643 cancel_delayed_work(&bp->period_task);
1644 flush_workqueue(bnx2x_wq);
1650 * General service functions
1653 /* Return true if succeeded to acquire the lock */
1654 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1657 u32 resource_bit = (1 << resource);
1658 int func = BP_FUNC(bp);
1659 u32 hw_lock_control_reg;
1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1662 "Trying to take a lock on resource %d\n", resource);
1664 /* Validating that the resource is within range */
1665 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1666 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1667 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1668 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1673 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1675 hw_lock_control_reg =
1676 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1678 /* Try to acquire the lock */
1679 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1680 lock_status = REG_RD(bp, hw_lock_control_reg);
1681 if (lock_status & resource_bit)
1684 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1685 "Failed to get a lock on resource %d\n", resource);
1690 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1692 * @bp: driver handle
1694 * Returns the recovery leader resource id according to the engine this function
1695 * belongs to. Currently only only 2 engines is supported.
1697 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1700 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1702 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1706 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1708 * @bp: driver handle
1710 * Tries to acquire a leader lock for current engine.
1712 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1714 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1717 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1719 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1720 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1722 /* Set the interrupt occurred bit for the sp-task to recognize it
1723 * must ack the interrupt and transition according to the IGU
1726 atomic_set(&bp->interrupt_occurred, 1);
1728 /* The sp_task must execute only after this bit
1729 * is set, otherwise we will get out of sync and miss all
1730 * further interrupts. Hence, the barrier.
1734 /* schedule sp_task to workqueue */
1735 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1738 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1740 struct bnx2x *bp = fp->bp;
1741 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1742 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1743 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1744 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1747 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1748 fp->index, cid, command, bp->state,
1749 rr_cqe->ramrod_cqe.ramrod_type);
1751 /* If cid is within VF range, replace the slowpath object with the
1752 * one corresponding to this VF
1754 if (cid >= BNX2X_FIRST_VF_CID &&
1755 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1756 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1759 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1760 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1761 drv_cmd = BNX2X_Q_CMD_UPDATE;
1764 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1765 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1766 drv_cmd = BNX2X_Q_CMD_SETUP;
1769 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1770 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1771 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1774 case (RAMROD_CMD_ID_ETH_HALT):
1775 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1776 drv_cmd = BNX2X_Q_CMD_HALT;
1779 case (RAMROD_CMD_ID_ETH_TERMINATE):
1780 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1781 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1784 case (RAMROD_CMD_ID_ETH_EMPTY):
1785 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1786 drv_cmd = BNX2X_Q_CMD_EMPTY;
1790 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1791 command, fp->index);
1795 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1796 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1797 /* q_obj->complete_cmd() failure means that this was
1798 * an unexpected completion.
1800 * In this case we don't want to increase the bp->spq_left
1801 * because apparently we haven't sent this command the first
1804 #ifdef BNX2X_STOP_ON_ERROR
1809 /* SRIOV: reschedule any 'in_progress' operations */
1810 bnx2x_iov_sp_event(bp, cid, true);
1812 smp_mb__before_atomic_inc();
1813 atomic_inc(&bp->cq_spq_left);
1814 /* push the change in bp->spq_left and towards the memory */
1815 smp_mb__after_atomic_inc();
1817 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1819 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1820 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1821 /* if Q update ramrod is completed for last Q in AFEX vif set
1822 * flow, then ACK MCP at the end
1824 * mark pending ACK to MCP bit.
1825 * prevent case that both bits are cleared.
1826 * At the end of load/unload driver checks that
1827 * sp_state is cleared, and this order prevents
1830 smp_mb__before_clear_bit();
1831 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1833 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1834 smp_mb__after_clear_bit();
1836 /* schedule the sp task as mcp ack is required */
1837 bnx2x_schedule_sp_task(bp);
1843 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1845 struct bnx2x *bp = netdev_priv(dev_instance);
1846 u16 status = bnx2x_ack_int(bp);
1851 /* Return here if interrupt is shared and it's not for us */
1852 if (unlikely(status == 0)) {
1853 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1856 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1858 #ifdef BNX2X_STOP_ON_ERROR
1859 if (unlikely(bp->panic))
1863 for_each_eth_queue(bp, i) {
1864 struct bnx2x_fastpath *fp = &bp->fp[i];
1866 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1867 if (status & mask) {
1868 /* Handle Rx or Tx according to SB id */
1869 for_each_cos_in_tx_queue(fp, cos)
1870 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1871 prefetch(&fp->sb_running_index[SM_RX_ID]);
1872 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1877 if (CNIC_SUPPORT(bp)) {
1879 if (status & (mask | 0x1)) {
1880 struct cnic_ops *c_ops = NULL;
1883 c_ops = rcu_dereference(bp->cnic_ops);
1884 if (c_ops && (bp->cnic_eth_dev.drv_state &
1885 CNIC_DRV_STATE_HANDLES_IRQ))
1886 c_ops->cnic_handler(bp->cnic_data, NULL);
1893 if (unlikely(status & 0x1)) {
1895 /* schedule sp task to perform default status block work, ack
1896 * attentions and enable interrupts.
1898 bnx2x_schedule_sp_task(bp);
1905 if (unlikely(status))
1906 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1915 * General service functions
1918 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1921 u32 resource_bit = (1 << resource);
1922 int func = BP_FUNC(bp);
1923 u32 hw_lock_control_reg;
1926 /* Validating that the resource is within range */
1927 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1928 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1929 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1934 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1936 hw_lock_control_reg =
1937 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1940 /* Validating that the resource is not already taken */
1941 lock_status = REG_RD(bp, hw_lock_control_reg);
1942 if (lock_status & resource_bit) {
1943 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1944 lock_status, resource_bit);
1948 /* Try for 5 second every 5ms */
1949 for (cnt = 0; cnt < 1000; cnt++) {
1950 /* Try to acquire the lock */
1951 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1952 lock_status = REG_RD(bp, hw_lock_control_reg);
1953 if (lock_status & resource_bit)
1956 usleep_range(5000, 10000);
1958 BNX2X_ERR("Timeout\n");
1962 int bnx2x_release_leader_lock(struct bnx2x *bp)
1964 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1967 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1970 u32 resource_bit = (1 << resource);
1971 int func = BP_FUNC(bp);
1972 u32 hw_lock_control_reg;
1974 /* Validating that the resource is within range */
1975 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1976 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1977 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1982 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984 hw_lock_control_reg =
1985 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 /* Validating that the resource is currently taken */
1989 lock_status = REG_RD(bp, hw_lock_control_reg);
1990 if (!(lock_status & resource_bit)) {
1991 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
1992 lock_status, resource_bit);
1996 REG_WR(bp, hw_lock_control_reg, resource_bit);
2000 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2002 /* The GPIO should be swapped if swap register is set and active */
2003 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2004 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2005 int gpio_shift = gpio_num +
2006 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2007 u32 gpio_mask = (1 << gpio_shift);
2011 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2012 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2016 /* read GPIO value */
2017 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2019 /* get the requested pin value */
2020 if ((gpio_reg & gpio_mask) == gpio_mask)
2025 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2030 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO and mask except the float bits */
2047 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2050 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2052 "Set GPIO %d (shift %d) -> output low\n",
2053 gpio_num, gpio_shift);
2054 /* clear FLOAT and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2059 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2061 "Set GPIO %d (shift %d) -> output high\n",
2062 gpio_num, gpio_shift);
2063 /* clear FLOAT and set SET */
2064 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2065 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2068 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2070 "Set GPIO %d (shift %d) -> input\n",
2071 gpio_num, gpio_shift);
2073 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2080 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2081 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2091 /* Any port swapping should be handled by caller. */
2093 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2094 /* read GPIO and mask except the float bits */
2095 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2096 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2097 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2098 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2101 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2102 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2104 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2107 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2108 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2110 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2113 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2114 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2116 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2120 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2126 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2133 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2135 /* The GPIO should be swapped if swap register is set and active */
2136 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2137 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2138 int gpio_shift = gpio_num +
2139 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2140 u32 gpio_mask = (1 << gpio_shift);
2143 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2144 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2148 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2150 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2153 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2155 "Clear GPIO INT %d (shift %d) -> output low\n",
2156 gpio_num, gpio_shift);
2157 /* clear SET and set CLR */
2158 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2159 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2162 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2164 "Set GPIO INT %d (shift %d) -> output high\n",
2165 gpio_num, gpio_shift);
2166 /* clear CLR and set SET */
2167 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2168 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2175 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2176 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2181 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2185 /* Only 2 SPIOs are configurable */
2186 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2187 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2192 /* read SPIO and mask except the float bits */
2193 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2196 case MISC_SPIO_OUTPUT_LOW:
2197 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2198 /* clear FLOAT and set CLR */
2199 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2200 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2203 case MISC_SPIO_OUTPUT_HIGH:
2204 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2205 /* clear FLOAT and set SET */
2206 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2207 spio_reg |= (spio << MISC_SPIO_SET_POS);
2210 case MISC_SPIO_INPUT_HI_Z:
2211 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2213 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2220 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2226 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2228 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2229 switch (bp->link_vars.ieee_fc &
2230 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2232 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2237 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2241 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2242 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2246 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2252 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2254 /* Initialize link parameters structure variables
2255 * It is recommended to turn off RX FC for jumbo frames
2256 * for better performance
2258 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2259 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2261 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2264 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2266 u32 pause_enabled = 0;
2268 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2269 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2272 REG_WR(bp, BAR_USTRORM_INTMEM +
2273 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2277 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2278 pause_enabled ? "enabled" : "disabled");
2281 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2283 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2284 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2286 if (!BP_NOMCP(bp)) {
2287 bnx2x_set_requested_fc(bp);
2288 bnx2x_acquire_phy_lock(bp);
2290 if (load_mode == LOAD_DIAG) {
2291 struct link_params *lp = &bp->link_params;
2292 lp->loopback_mode = LOOPBACK_XGXS;
2293 /* do PHY loopback at 10G speed, if possible */
2294 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2295 if (lp->speed_cap_mask[cfx_idx] &
2296 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2297 lp->req_line_speed[cfx_idx] =
2300 lp->req_line_speed[cfx_idx] =
2305 if (load_mode == LOAD_LOOPBACK_EXT) {
2306 struct link_params *lp = &bp->link_params;
2307 lp->loopback_mode = LOOPBACK_EXT;
2310 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2312 bnx2x_release_phy_lock(bp);
2314 bnx2x_init_dropless_fc(bp);
2316 bnx2x_calc_fc_adv(bp);
2318 if (bp->link_vars.link_up) {
2319 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2320 bnx2x_link_report(bp);
2322 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2323 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2326 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2330 void bnx2x_link_set(struct bnx2x *bp)
2332 if (!BP_NOMCP(bp)) {
2333 bnx2x_acquire_phy_lock(bp);
2334 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2335 bnx2x_release_phy_lock(bp);
2337 bnx2x_init_dropless_fc(bp);
2339 bnx2x_calc_fc_adv(bp);
2341 BNX2X_ERR("Bootcode is missing - can not set link\n");
2344 static void bnx2x__link_reset(struct bnx2x *bp)
2346 if (!BP_NOMCP(bp)) {
2347 bnx2x_acquire_phy_lock(bp);
2348 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2349 bnx2x_release_phy_lock(bp);
2351 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2354 void bnx2x_force_link_reset(struct bnx2x *bp)
2356 bnx2x_acquire_phy_lock(bp);
2357 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2358 bnx2x_release_phy_lock(bp);
2361 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2365 if (!BP_NOMCP(bp)) {
2366 bnx2x_acquire_phy_lock(bp);
2367 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2369 bnx2x_release_phy_lock(bp);
2371 BNX2X_ERR("Bootcode is missing - can not test link\n");
2376 /* Calculates the sum of vn_min_rates.
2377 It's needed for further normalizing of the min_rates.
2379 sum of vn_min_rates.
2381 0 - if all the min_rates are 0.
2382 In the later case fairness algorithm should be deactivated.
2383 If not all min_rates are zero then those that are zeroes will be set to 1.
2385 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2386 struct cmng_init_input *input)
2391 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2392 u32 vn_cfg = bp->mf_config[vn];
2393 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2394 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2396 /* Skip hidden vns */
2397 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2399 /* If min rate is zero - set it to 1 */
2400 else if (!vn_min_rate)
2401 vn_min_rate = DEF_MIN_RATE;
2405 input->vnic_min_rate[vn] = vn_min_rate;
2408 /* if ETS or all min rates are zeros - disable fairness */
2409 if (BNX2X_IS_ETS_ENABLED(bp)) {
2410 input->flags.cmng_enables &=
2411 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2412 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2413 } else if (all_zero) {
2414 input->flags.cmng_enables &=
2415 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2417 "All MIN values are zeroes fairness will be disabled\n");
2419 input->flags.cmng_enables |=
2420 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2423 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2424 struct cmng_init_input *input)
2427 u32 vn_cfg = bp->mf_config[vn];
2429 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2432 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2435 /* maxCfg in percents of linkspeed */
2436 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2437 } else /* SD modes */
2438 /* maxCfg is absolute in 100Mb units */
2439 vn_max_rate = maxCfg * 100;
2442 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2444 input->vnic_max_rate[vn] = vn_max_rate;
2447 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2449 if (CHIP_REV_IS_SLOW(bp))
2450 return CMNG_FNS_NONE;
2452 return CMNG_FNS_MINMAX;
2454 return CMNG_FNS_NONE;
2457 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2459 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2462 return; /* what should be the default value in this case */
2464 /* For 2 port configuration the absolute function number formula
2466 * abs_func = 2 * vn + BP_PORT + BP_PATH
2468 * and there are 4 functions per port
2470 * For 4 port configuration it is
2471 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2473 * and there are 2 functions per port
2475 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2476 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2478 if (func >= E1H_FUNC_MAX)
2482 MF_CFG_RD(bp, func_mf_config[func].config);
2484 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2485 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2486 bp->flags |= MF_FUNC_DIS;
2488 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2489 bp->flags &= ~MF_FUNC_DIS;
2493 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2495 struct cmng_init_input input;
2496 memset(&input, 0, sizeof(struct cmng_init_input));
2498 input.port_rate = bp->link_vars.line_speed;
2500 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2503 /* read mf conf from shmem */
2505 bnx2x_read_mf_cfg(bp);
2507 /* vn_weight_sum and enable fairness if not 0 */
2508 bnx2x_calc_vn_min(bp, &input);
2510 /* calculate and set min-max rate for each vn */
2512 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2513 bnx2x_calc_vn_max(bp, vn, &input);
2515 /* always enable rate shaping and fairness */
2516 input.flags.cmng_enables |=
2517 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2519 bnx2x_init_cmng(&input, &bp->cmng);
2523 /* rate shaping and fairness are disabled */
2525 "rate shaping and fairness are disabled\n");
2528 static void storm_memset_cmng(struct bnx2x *bp,
2529 struct cmng_init *cmng,
2533 size_t size = sizeof(struct cmng_struct_per_port);
2535 u32 addr = BAR_XSTRORM_INTMEM +
2536 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2538 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2540 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2541 int func = func_by_vn(bp, vn);
2543 addr = BAR_XSTRORM_INTMEM +
2544 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2545 size = sizeof(struct rate_shaping_vars_per_vn);
2546 __storm_memset_struct(bp, addr, size,
2547 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2549 addr = BAR_XSTRORM_INTMEM +
2550 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2551 size = sizeof(struct fairness_vars_per_vn);
2552 __storm_memset_struct(bp, addr, size,
2553 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2557 /* init cmng mode in HW according to local configuration */
2558 void bnx2x_set_local_cmng(struct bnx2x *bp)
2560 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2562 if (cmng_fns != CMNG_FNS_NONE) {
2563 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2564 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2566 /* rate shaping and fairness are disabled */
2568 "single function mode without fairness\n");
2572 /* This function is called upon link interrupt */
2573 static void bnx2x_link_attn(struct bnx2x *bp)
2575 /* Make sure that we are synced with the current statistics */
2576 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2578 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2580 bnx2x_init_dropless_fc(bp);
2582 if (bp->link_vars.link_up) {
2584 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2585 struct host_port_stats *pstats;
2587 pstats = bnx2x_sp(bp, port_stats);
2588 /* reset old mac stats */
2589 memset(&(pstats->mac_stx[0]), 0,
2590 sizeof(struct mac_stx));
2592 if (bp->state == BNX2X_STATE_OPEN)
2593 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2596 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2597 bnx2x_set_local_cmng(bp);
2599 __bnx2x_link_report(bp);
2602 bnx2x_link_sync_notify(bp);
2605 void bnx2x__link_status_update(struct bnx2x *bp)
2607 if (bp->state != BNX2X_STATE_OPEN)
2610 /* read updated dcb configuration */
2612 bnx2x_dcbx_pmf_update(bp);
2613 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2614 if (bp->link_vars.link_up)
2615 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2617 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2618 /* indicate link status */
2619 bnx2x_link_report(bp);
2622 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2623 SUPPORTED_10baseT_Full |
2624 SUPPORTED_100baseT_Half |
2625 SUPPORTED_100baseT_Full |
2626 SUPPORTED_1000baseT_Full |
2627 SUPPORTED_2500baseX_Full |
2628 SUPPORTED_10000baseT_Full |
2633 SUPPORTED_Asym_Pause);
2634 bp->port.advertising[0] = bp->port.supported[0];
2636 bp->link_params.bp = bp;
2637 bp->link_params.port = BP_PORT(bp);
2638 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2639 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2640 bp->link_params.req_line_speed[0] = SPEED_10000;
2641 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2642 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2643 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2644 bp->link_vars.line_speed = SPEED_10000;
2645 bp->link_vars.link_status =
2646 (LINK_STATUS_LINK_UP |
2647 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2648 bp->link_vars.link_up = 1;
2649 bp->link_vars.duplex = DUPLEX_FULL;
2650 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2651 __bnx2x_link_report(bp);
2652 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2656 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2657 u16 vlan_val, u8 allowed_prio)
2659 struct bnx2x_func_state_params func_params = {NULL};
2660 struct bnx2x_func_afex_update_params *f_update_params =
2661 &func_params.params.afex_update;
2663 func_params.f_obj = &bp->func_obj;
2664 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2666 /* no need to wait for RAMROD completion, so don't
2667 * set RAMROD_COMP_WAIT flag
2670 f_update_params->vif_id = vifid;
2671 f_update_params->afex_default_vlan = vlan_val;
2672 f_update_params->allowed_priorities = allowed_prio;
2674 /* if ramrod can not be sent, response to MCP immediately */
2675 if (bnx2x_func_state_change(bp, &func_params) < 0)
2676 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2681 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2682 u16 vif_index, u8 func_bit_map)
2684 struct bnx2x_func_state_params func_params = {NULL};
2685 struct bnx2x_func_afex_viflists_params *update_params =
2686 &func_params.params.afex_viflists;
2690 /* validate only LIST_SET and LIST_GET are received from switch */
2691 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2692 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2695 func_params.f_obj = &bp->func_obj;
2696 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2698 /* set parameters according to cmd_type */
2699 update_params->afex_vif_list_command = cmd_type;
2700 update_params->vif_list_index = vif_index;
2701 update_params->func_bit_map =
2702 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2703 update_params->func_to_clear = 0;
2705 (cmd_type == VIF_LIST_RULE_GET) ?
2706 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2707 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2709 /* if ramrod can not be sent, respond to MCP immediately for
2710 * SET and GET requests (other are not triggered from MCP)
2712 rc = bnx2x_func_state_change(bp, &func_params);
2714 bnx2x_fw_command(bp, drv_msg_code, 0);
2719 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2721 struct afex_stats afex_stats;
2722 u32 func = BP_ABS_FUNC(bp);
2729 u32 addr_to_write, vifid, addrs, stats_type, i;
2731 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2732 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2734 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2735 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2738 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2739 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2740 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2742 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2744 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2748 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2749 addr_to_write = SHMEM2_RD(bp,
2750 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2751 stats_type = SHMEM2_RD(bp,
2752 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2755 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2758 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2760 /* write response to scratchpad, for MCP */
2761 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2762 REG_WR(bp, addr_to_write + i*sizeof(u32),
2763 *(((u32 *)(&afex_stats))+i));
2765 /* send ack message to MCP */
2766 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2769 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2770 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2771 bp->mf_config[BP_VN(bp)] = mf_config;
2773 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2776 /* if VIF_SET is "enabled" */
2777 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2778 /* set rate limit directly to internal RAM */
2779 struct cmng_init_input cmng_input;
2780 struct rate_shaping_vars_per_vn m_rs_vn;
2781 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2782 u32 addr = BAR_XSTRORM_INTMEM +
2783 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2785 bp->mf_config[BP_VN(bp)] = mf_config;
2787 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2788 m_rs_vn.vn_counter.rate =
2789 cmng_input.vnic_max_rate[BP_VN(bp)];
2790 m_rs_vn.vn_counter.quota =
2791 (m_rs_vn.vn_counter.rate *
2792 RS_PERIODIC_TIMEOUT_USEC) / 8;
2794 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2796 /* read relevant values from mf_cfg struct in shmem */
2798 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2799 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2800 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2802 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2803 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2804 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2805 vlan_prio = (mf_config &
2806 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2807 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2808 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2811 func_mf_config[func].afex_config) &
2812 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2813 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2816 func_mf_config[func].afex_config) &
2817 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2818 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2820 /* send ramrod to FW, return in case of failure */
2821 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2825 bp->afex_def_vlan_tag = vlan_val;
2826 bp->afex_vlan_mode = vlan_mode;
2828 /* notify link down because BP->flags is disabled */
2829 bnx2x_link_report(bp);
2831 /* send INVALID VIF ramrod to FW */
2832 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2834 /* Reset the default afex VLAN */
2835 bp->afex_def_vlan_tag = -1;
2840 static void bnx2x_pmf_update(struct bnx2x *bp)
2842 int port = BP_PORT(bp);
2846 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2849 * We need the mb() to ensure the ordering between the writing to
2850 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2854 /* queue a periodic task */
2855 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2857 bnx2x_dcbx_pmf_update(bp);
2859 /* enable nig attention */
2860 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2861 if (bp->common.int_block == INT_BLOCK_HC) {
2862 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2863 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2864 } else if (!CHIP_IS_E1x(bp)) {
2865 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2866 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2869 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2877 * General service functions
2880 /* send the MCP a request, block until there is a reply */
2881 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2883 int mb_idx = BP_FW_MB_IDX(bp);
2887 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2889 mutex_lock(&bp->fw_mb_mutex);
2891 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2892 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2894 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2895 (command | seq), param);
2898 /* let the FW do it's magic ... */
2901 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2903 /* Give the FW up to 5 second (500*10ms) */
2904 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2906 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2907 cnt*delay, rc, seq);
2909 /* is this a reply to our command? */
2910 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2911 rc &= FW_MSG_CODE_MASK;
2914 BNX2X_ERR("FW failed to respond!\n");
2918 mutex_unlock(&bp->fw_mb_mutex);
2923 static void storm_memset_func_cfg(struct bnx2x *bp,
2924 struct tstorm_eth_function_common_config *tcfg,
2927 size_t size = sizeof(struct tstorm_eth_function_common_config);
2929 u32 addr = BAR_TSTRORM_INTMEM +
2930 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2932 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2935 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2937 if (CHIP_IS_E1x(bp)) {
2938 struct tstorm_eth_function_common_config tcfg = {0};
2940 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2943 /* Enable the function in the FW */
2944 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2945 storm_memset_func_en(bp, p->func_id, 1);
2948 if (p->func_flgs & FUNC_FLG_SPQ) {
2949 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2950 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2951 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2956 * bnx2x_get_common_flags - Return common flags
2960 * @zero_stats TRUE if statistics zeroing is needed
2962 * Return the flags that are common for the Tx-only and not normal connections.
2964 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2965 struct bnx2x_fastpath *fp,
2968 unsigned long flags = 0;
2970 /* PF driver will always initialize the Queue to an ACTIVE state */
2971 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2973 /* tx only connections collect statistics (on the same index as the
2974 * parent connection). The statistics are zeroed when the parent
2975 * connection is initialized.
2978 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2980 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2982 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2983 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2985 #ifdef BNX2X_STOP_ON_ERROR
2986 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2992 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2993 struct bnx2x_fastpath *fp,
2996 unsigned long flags = 0;
2998 /* calculate other queue flags */
3000 __set_bit(BNX2X_Q_FLG_OV, &flags);
3002 if (IS_FCOE_FP(fp)) {
3003 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3004 /* For FCoE - force usage of default priority (for afex) */
3005 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3008 if (!fp->disable_tpa) {
3009 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3010 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3011 if (fp->mode == TPA_MODE_GRO)
3012 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3016 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3017 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3020 /* Always set HW VLAN stripping */
3021 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3023 /* configure silent vlan removal */
3025 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3027 return flags | bnx2x_get_common_flags(bp, fp, true);
3030 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3031 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3034 gen_init->stat_id = bnx2x_stats_id(fp);
3035 gen_init->spcl_id = fp->cl_id;
3037 /* Always use mini-jumbo MTU for FCoE L2 ring */
3039 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3041 gen_init->mtu = bp->dev->mtu;
3043 gen_init->cos = cos;
3046 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3047 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3048 struct bnx2x_rxq_setup_params *rxq_init)
3052 u16 tpa_agg_size = 0;
3054 if (!fp->disable_tpa) {
3055 pause->sge_th_lo = SGE_TH_LO(bp);
3056 pause->sge_th_hi = SGE_TH_HI(bp);
3058 /* validate SGE ring has enough to cross high threshold */
3059 WARN_ON(bp->dropless_fc &&
3060 pause->sge_th_hi + FW_PREFETCH_CNT >
3061 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3063 tpa_agg_size = TPA_AGG_SIZE;
3064 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3066 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3067 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3068 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3071 /* pause - not for e1 */
3072 if (!CHIP_IS_E1(bp)) {
3073 pause->bd_th_lo = BD_TH_LO(bp);
3074 pause->bd_th_hi = BD_TH_HI(bp);
3076 pause->rcq_th_lo = RCQ_TH_LO(bp);
3077 pause->rcq_th_hi = RCQ_TH_HI(bp);
3079 * validate that rings have enough entries to cross
3082 WARN_ON(bp->dropless_fc &&
3083 pause->bd_th_hi + FW_PREFETCH_CNT >
3085 WARN_ON(bp->dropless_fc &&
3086 pause->rcq_th_hi + FW_PREFETCH_CNT >
3087 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3093 rxq_init->dscr_map = fp->rx_desc_mapping;
3094 rxq_init->sge_map = fp->rx_sge_mapping;
3095 rxq_init->rcq_map = fp->rx_comp_mapping;
3096 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3098 /* This should be a maximum number of data bytes that may be
3099 * placed on the BD (not including paddings).
3101 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3102 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3104 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3105 rxq_init->tpa_agg_sz = tpa_agg_size;
3106 rxq_init->sge_buf_sz = sge_sz;
3107 rxq_init->max_sges_pkt = max_sge;
3108 rxq_init->rss_engine_id = BP_FUNC(bp);
3109 rxq_init->mcast_engine_id = BP_FUNC(bp);
3111 /* Maximum number or simultaneous TPA aggregation for this Queue.
3113 * For PF Clients it should be the maximum available number.
3114 * VF driver(s) may want to define it to a smaller value.
3116 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3118 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3119 rxq_init->fw_sb_id = fp->fw_sb_id;
3122 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3124 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3125 /* configure silent vlan removal
3126 * if multi function mode is afex, then mask default vlan
3128 if (IS_MF_AFEX(bp)) {
3129 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3130 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3134 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3135 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3138 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3139 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3140 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3141 txq_init->fw_sb_id = fp->fw_sb_id;
3144 * set the tss leading client id for TX classification ==
3145 * leading RSS client id
3147 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3149 if (IS_FCOE_FP(fp)) {
3150 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3151 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3155 static void bnx2x_pf_init(struct bnx2x *bp)
3157 struct bnx2x_func_init_params func_init = {0};
3158 struct event_ring_data eq_data = { {0} };
3161 if (!CHIP_IS_E1x(bp)) {
3162 /* reset IGU PF statistics: MSIX + ATTN */
3164 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3165 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3166 (CHIP_MODE_IS_4_PORT(bp) ?
3167 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3169 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3170 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3171 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3172 (CHIP_MODE_IS_4_PORT(bp) ?
3173 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3176 /* function setup flags */
3177 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3179 /* This flag is relevant for E1x only.
3180 * E2 doesn't have a TPA configuration in a function level.
3182 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3184 func_init.func_flgs = flags;
3185 func_init.pf_id = BP_FUNC(bp);
3186 func_init.func_id = BP_FUNC(bp);
3187 func_init.spq_map = bp->spq_mapping;
3188 func_init.spq_prod = bp->spq_prod_idx;
3190 bnx2x_func_init(bp, &func_init);
3192 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3195 * Congestion management values depend on the link rate
3196 * There is no active link so initial link rate is set to 10 Gbps.
3197 * When the link comes up The congestion management values are
3198 * re-calculated according to the actual link rate.
3200 bp->link_vars.line_speed = SPEED_10000;
3201 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3203 /* Only the PMF sets the HW */
3205 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3207 /* init Event Queue - PCI bus guarantees correct endianity*/
3208 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3209 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3210 eq_data.producer = bp->eq_prod;
3211 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3212 eq_data.sb_id = DEF_SB_ID;
3213 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3216 static void bnx2x_e1h_disable(struct bnx2x *bp)
3218 int port = BP_PORT(bp);
3220 bnx2x_tx_disable(bp);
3222 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3225 static void bnx2x_e1h_enable(struct bnx2x *bp)
3227 int port = BP_PORT(bp);
3229 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3231 /* Tx queue should be only re-enabled */
3232 netif_tx_wake_all_queues(bp->dev);
3235 * Should not call netif_carrier_on since it will be called if the link
3236 * is up when checking for link state
3240 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3242 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3244 struct eth_stats_info *ether_stat =
3245 &bp->slowpath->drv_info_to_mcp.ether_stat;
3246 struct bnx2x_vlan_mac_obj *mac_obj =
3247 &bp->sp_objs->mac_obj;
3250 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3251 ETH_STAT_INFO_VERSION_LEN);
3253 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3254 * mac_local field in ether_stat struct. The base address is offset by 2
3255 * bytes to account for the field being 8 bytes but a mac address is
3256 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3257 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3258 * allocated by the ether_stat struct, so the macs will land in their
3261 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3262 memset(ether_stat->mac_local + i, 0,
3263 sizeof(ether_stat->mac_local[0]));
3264 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3265 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3266 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3268 ether_stat->mtu_size = bp->dev->mtu;
3269 if (bp->dev->features & NETIF_F_RXCSUM)
3270 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3271 if (bp->dev->features & NETIF_F_TSO)
3272 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3273 ether_stat->feature_flags |= bp->common.boot_mode;
3275 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3277 ether_stat->txq_size = bp->tx_ring_size;
3278 ether_stat->rxq_size = bp->rx_ring_size;
3281 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3283 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3284 struct fcoe_stats_info *fcoe_stat =
3285 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3287 if (!CNIC_LOADED(bp))
3290 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3292 fcoe_stat->qos_priority =
3293 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3295 /* insert FCoE stats from ramrod response */
3297 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3298 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3299 tstorm_queue_statistics;
3301 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3302 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3303 xstorm_queue_statistics;
3305 struct fcoe_statistics_params *fw_fcoe_stat =
3306 &bp->fw_stats_data->fcoe;
3308 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3309 fcoe_stat->rx_bytes_lo,
3310 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3312 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3313 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3314 fcoe_stat->rx_bytes_lo,
3315 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3317 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3318 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3319 fcoe_stat->rx_bytes_lo,
3320 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3322 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3323 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3324 fcoe_stat->rx_bytes_lo,
3325 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3327 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3328 fcoe_stat->rx_frames_lo,
3329 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3331 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3332 fcoe_stat->rx_frames_lo,
3333 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3335 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3336 fcoe_stat->rx_frames_lo,
3337 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3339 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3340 fcoe_stat->rx_frames_lo,
3341 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3343 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3344 fcoe_stat->tx_bytes_lo,
3345 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3347 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3348 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3349 fcoe_stat->tx_bytes_lo,
3350 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3352 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3353 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3354 fcoe_stat->tx_bytes_lo,
3355 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3357 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3358 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3359 fcoe_stat->tx_bytes_lo,
3360 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3362 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3363 fcoe_stat->tx_frames_lo,
3364 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3366 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3367 fcoe_stat->tx_frames_lo,
3368 fcoe_q_xstorm_stats->ucast_pkts_sent);
3370 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3371 fcoe_stat->tx_frames_lo,
3372 fcoe_q_xstorm_stats->bcast_pkts_sent);
3374 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3375 fcoe_stat->tx_frames_lo,
3376 fcoe_q_xstorm_stats->mcast_pkts_sent);
3379 /* ask L5 driver to add data to the struct */
3380 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3383 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3385 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3386 struct iscsi_stats_info *iscsi_stat =
3387 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3389 if (!CNIC_LOADED(bp))
3392 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3395 iscsi_stat->qos_priority =
3396 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3398 /* ask L5 driver to add data to the struct */
3399 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3402 /* called due to MCP event (on pmf):
3403 * reread new bandwidth configuration
3405 * notify others function about the change
3407 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3409 if (bp->link_vars.link_up) {
3410 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3411 bnx2x_link_sync_notify(bp);
3413 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3416 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3418 bnx2x_config_mf_bw(bp);
3419 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3422 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3424 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3425 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3428 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3430 enum drv_info_opcode op_code;
3431 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3433 /* if drv_info version supported by MFW doesn't match - send NACK */
3434 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3435 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3439 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3440 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3442 memset(&bp->slowpath->drv_info_to_mcp, 0,
3443 sizeof(union drv_info_to_mcp));
3446 case ETH_STATS_OPCODE:
3447 bnx2x_drv_info_ether_stat(bp);
3449 case FCOE_STATS_OPCODE:
3450 bnx2x_drv_info_fcoe_stat(bp);
3452 case ISCSI_STATS_OPCODE:
3453 bnx2x_drv_info_iscsi_stat(bp);
3456 /* if op code isn't supported - send NACK */
3457 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3461 /* if we got drv_info attn from MFW then these fields are defined in
3464 SHMEM2_WR(bp, drv_info_host_addr_lo,
3465 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3466 SHMEM2_WR(bp, drv_info_host_addr_hi,
3467 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3469 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3472 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3474 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3476 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3479 * This is the only place besides the function initialization
3480 * where the bp->flags can change so it is done without any
3483 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3484 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3485 bp->flags |= MF_FUNC_DIS;
3487 bnx2x_e1h_disable(bp);
3489 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3490 bp->flags &= ~MF_FUNC_DIS;
3492 bnx2x_e1h_enable(bp);
3494 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3496 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3497 bnx2x_config_mf_bw(bp);
3498 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3501 /* Report results to MCP */
3503 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3505 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3508 /* must be called under the spq lock */
3509 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3511 struct eth_spe *next_spe = bp->spq_prod_bd;
3513 if (bp->spq_prod_bd == bp->spq_last_bd) {
3514 bp->spq_prod_bd = bp->spq;
3515 bp->spq_prod_idx = 0;
3516 DP(BNX2X_MSG_SP, "end of spq\n");
3524 /* must be called under the spq lock */
3525 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3527 int func = BP_FUNC(bp);
3530 * Make sure that BD data is updated before writing the producer:
3531 * BD data is written to the memory, the producer is read from the
3532 * memory, thus we need a full memory barrier to ensure the ordering.
3536 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3542 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3544 * @cmd: command to check
3545 * @cmd_type: command type
3547 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3549 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3550 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3551 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3552 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3553 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3554 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3555 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3562 * bnx2x_sp_post - place a single command on an SP ring
3564 * @bp: driver handle
3565 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3566 * @cid: SW CID the command is related to
3567 * @data_hi: command private data address (high 32 bits)
3568 * @data_lo: command private data address (low 32 bits)
3569 * @cmd_type: command type (e.g. NONE, ETH)
3571 * SP data is handled as if it's always an address pair, thus data fields are
3572 * not swapped to little endian in upper functions. Instead this function swaps
3573 * data as if it's two u32 fields.
3575 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3576 u32 data_hi, u32 data_lo, int cmd_type)
3578 struct eth_spe *spe;
3580 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3582 #ifdef BNX2X_STOP_ON_ERROR
3583 if (unlikely(bp->panic)) {
3584 BNX2X_ERR("Can't post SP when there is panic\n");
3589 spin_lock_bh(&bp->spq_lock);
3592 if (!atomic_read(&bp->eq_spq_left)) {
3593 BNX2X_ERR("BUG! EQ ring full!\n");
3594 spin_unlock_bh(&bp->spq_lock);
3598 } else if (!atomic_read(&bp->cq_spq_left)) {
3599 BNX2X_ERR("BUG! SPQ ring full!\n");
3600 spin_unlock_bh(&bp->spq_lock);
3605 spe = bnx2x_sp_get_next(bp);
3607 /* CID needs port number to be encoded int it */
3608 spe->hdr.conn_and_cmd_data =
3609 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3612 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3614 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3615 SPE_HDR_FUNCTION_ID);
3617 spe->hdr.type = cpu_to_le16(type);
3619 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3620 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3623 * It's ok if the actual decrement is issued towards the memory
3624 * somewhere between the spin_lock and spin_unlock. Thus no
3625 * more explicit memory barrier is needed.
3628 atomic_dec(&bp->eq_spq_left);
3630 atomic_dec(&bp->cq_spq_left);
3633 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3634 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3635 (u32)(U64_LO(bp->spq_mapping) +
3636 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3637 HW_CID(bp, cid), data_hi, data_lo, type,
3638 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3640 bnx2x_sp_prod_update(bp);
3641 spin_unlock_bh(&bp->spq_lock);
3645 /* acquire split MCP access lock register */
3646 static int bnx2x_acquire_alr(struct bnx2x *bp)
3652 for (j = 0; j < 1000; j++) {
3653 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3654 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3655 if (val & MCPR_ACCESS_LOCK_LOCK)
3658 usleep_range(5000, 10000);
3660 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3661 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3668 /* release split MCP access lock register */
3669 static void bnx2x_release_alr(struct bnx2x *bp)
3671 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3674 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3675 #define BNX2X_DEF_SB_IDX 0x0002
3677 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3679 struct host_sp_status_block *def_sb = bp->def_status_blk;
3682 barrier(); /* status block is written to by the chip */
3683 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3684 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3685 rc |= BNX2X_DEF_SB_ATT_IDX;
3688 if (bp->def_idx != def_sb->sp_sb.running_index) {
3689 bp->def_idx = def_sb->sp_sb.running_index;
3690 rc |= BNX2X_DEF_SB_IDX;
3693 /* Do not reorder: indices reading should complete before handling */
3699 * slow path service functions
3702 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3704 int port = BP_PORT(bp);
3705 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3706 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3707 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3708 NIG_REG_MASK_INTERRUPT_PORT0;
3713 if (bp->attn_state & asserted)
3714 BNX2X_ERR("IGU ERROR\n");
3716 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3717 aeu_mask = REG_RD(bp, aeu_addr);
3719 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3720 aeu_mask, asserted);
3721 aeu_mask &= ~(asserted & 0x3ff);
3722 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3724 REG_WR(bp, aeu_addr, aeu_mask);
3725 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3727 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3728 bp->attn_state |= asserted;
3729 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3731 if (asserted & ATTN_HARD_WIRED_MASK) {
3732 if (asserted & ATTN_NIG_FOR_FUNC) {
3734 bnx2x_acquire_phy_lock(bp);
3736 /* save nig interrupt mask */
3737 nig_mask = REG_RD(bp, nig_int_mask_addr);
3739 /* If nig_mask is not set, no need to call the update
3743 REG_WR(bp, nig_int_mask_addr, 0);
3745 bnx2x_link_attn(bp);
3748 /* handle unicore attn? */
3750 if (asserted & ATTN_SW_TIMER_4_FUNC)
3751 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3753 if (asserted & GPIO_2_FUNC)
3754 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3756 if (asserted & GPIO_3_FUNC)
3757 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3759 if (asserted & GPIO_4_FUNC)
3760 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3763 if (asserted & ATTN_GENERAL_ATTN_1) {
3764 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3765 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3767 if (asserted & ATTN_GENERAL_ATTN_2) {
3768 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3769 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3771 if (asserted & ATTN_GENERAL_ATTN_3) {
3772 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3773 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3776 if (asserted & ATTN_GENERAL_ATTN_4) {
3777 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3778 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3780 if (asserted & ATTN_GENERAL_ATTN_5) {
3781 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3782 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3784 if (asserted & ATTN_GENERAL_ATTN_6) {
3785 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3786 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3790 } /* if hardwired */
3792 if (bp->common.int_block == INT_BLOCK_HC)
3793 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3794 COMMAND_REG_ATTN_BITS_SET);
3796 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3798 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3799 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3800 REG_WR(bp, reg_addr, asserted);
3802 /* now set back the mask */
3803 if (asserted & ATTN_NIG_FOR_FUNC) {
3804 /* Verify that IGU ack through BAR was written before restoring
3805 * NIG mask. This loop should exit after 2-3 iterations max.
3807 if (bp->common.int_block != INT_BLOCK_HC) {
3808 u32 cnt = 0, igu_acked;
3810 igu_acked = REG_RD(bp,
3811 IGU_REG_ATTENTION_ACK_BITS);
3812 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3813 (++cnt < MAX_IGU_ATTN_ACK_TO));
3816 "Failed to verify IGU ack on time\n");
3819 REG_WR(bp, nig_int_mask_addr, nig_mask);
3820 bnx2x_release_phy_lock(bp);
3824 static void bnx2x_fan_failure(struct bnx2x *bp)
3826 int port = BP_PORT(bp);
3828 /* mark the failure */
3831 dev_info.port_hw_config[port].external_phy_config);
3833 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3834 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3835 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3838 /* log the failure */
3839 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3840 "Please contact OEM Support for assistance\n");
3842 /* Schedule device reset (unload)
3843 * This is due to some boards consuming sufficient power when driver is
3844 * up to overheat if fan fails.
3846 smp_mb__before_clear_bit();
3847 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3848 smp_mb__after_clear_bit();
3849 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3852 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3854 int port = BP_PORT(bp);
3858 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3859 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3861 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3863 val = REG_RD(bp, reg_offset);
3864 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3865 REG_WR(bp, reg_offset, val);
3867 BNX2X_ERR("SPIO5 hw attention\n");
3869 /* Fan failure attention */
3870 bnx2x_hw_reset_phy(&bp->link_params);
3871 bnx2x_fan_failure(bp);
3874 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3875 bnx2x_acquire_phy_lock(bp);
3876 bnx2x_handle_module_detect_int(&bp->link_params);
3877 bnx2x_release_phy_lock(bp);
3880 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3882 val = REG_RD(bp, reg_offset);
3883 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3884 REG_WR(bp, reg_offset, val);
3886 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3887 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3892 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3896 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3898 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3899 BNX2X_ERR("DB hw attention 0x%x\n", val);
3900 /* DORQ discard attention */
3902 BNX2X_ERR("FATAL error from DORQ\n");
3905 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3907 int port = BP_PORT(bp);
3910 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3911 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3913 val = REG_RD(bp, reg_offset);
3914 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3915 REG_WR(bp, reg_offset, val);
3917 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3918 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3923 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3927 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3929 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3930 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3931 /* CFC error attention */
3933 BNX2X_ERR("FATAL error from CFC\n");
3936 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3937 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3938 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3939 /* RQ_USDMDP_FIFO_OVERFLOW */
3941 BNX2X_ERR("FATAL error from PXP\n");
3943 if (!CHIP_IS_E1x(bp)) {
3944 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3945 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3949 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3951 int port = BP_PORT(bp);
3954 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3955 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3957 val = REG_RD(bp, reg_offset);
3958 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3959 REG_WR(bp, reg_offset, val);
3961 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3962 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3967 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3971 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3973 if (attn & BNX2X_PMF_LINK_ASSERT) {
3974 int func = BP_FUNC(bp);
3976 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3977 bnx2x_read_mf_cfg(bp);
3978 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3979 func_mf_config[BP_ABS_FUNC(bp)].config);
3981 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3982 if (val & DRV_STATUS_DCC_EVENT_MASK)
3984 (val & DRV_STATUS_DCC_EVENT_MASK));
3986 if (val & DRV_STATUS_SET_MF_BW)
3987 bnx2x_set_mf_bw(bp);
3989 if (val & DRV_STATUS_DRV_INFO_REQ)
3990 bnx2x_handle_drv_info_req(bp);
3992 if (val & DRV_STATUS_VF_DISABLED)
3993 bnx2x_vf_handle_flr_event(bp);
3995 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3996 bnx2x_pmf_update(bp);
3999 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4000 bp->dcbx_enabled > 0)
4001 /* start dcbx state machine */
4002 bnx2x_dcbx_set_params(bp,
4003 BNX2X_DCBX_STATE_NEG_RECEIVED);
4004 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4005 bnx2x_handle_afex_cmd(bp,
4006 val & DRV_STATUS_AFEX_EVENT_MASK);
4007 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4008 bnx2x_handle_eee_event(bp);
4009 if (bp->link_vars.periodic_flags &
4010 PERIODIC_FLAGS_LINK_EVENT) {
4011 /* sync with link */
4012 bnx2x_acquire_phy_lock(bp);
4013 bp->link_vars.periodic_flags &=
4014 ~PERIODIC_FLAGS_LINK_EVENT;
4015 bnx2x_release_phy_lock(bp);
4017 bnx2x_link_sync_notify(bp);
4018 bnx2x_link_report(bp);
4020 /* Always call it here: bnx2x_link_report() will
4021 * prevent the link indication duplication.
4023 bnx2x__link_status_update(bp);
4024 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4026 BNX2X_ERR("MC assert!\n");
4027 bnx2x_mc_assert(bp);
4028 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4029 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4030 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4031 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4034 } else if (attn & BNX2X_MCP_ASSERT) {
4036 BNX2X_ERR("MCP assert!\n");
4037 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4041 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4044 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4045 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4046 if (attn & BNX2X_GRC_TIMEOUT) {
4047 val = CHIP_IS_E1(bp) ? 0 :
4048 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4049 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4051 if (attn & BNX2X_GRC_RSV) {
4052 val = CHIP_IS_E1(bp) ? 0 :
4053 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4054 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4056 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4062 * 0-7 - Engine0 load counter.
4063 * 8-15 - Engine1 load counter.
4064 * 16 - Engine0 RESET_IN_PROGRESS bit.
4065 * 17 - Engine1 RESET_IN_PROGRESS bit.
4066 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4068 * 19 - Engine1 ONE_IS_LOADED.
4069 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4070 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4071 * just the one belonging to its engine).
4074 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4076 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4077 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4078 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4079 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4080 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4081 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4082 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4085 * Set the GLOBAL_RESET bit.
4087 * Should be run under rtnl lock
4089 void bnx2x_set_reset_global(struct bnx2x *bp)
4092 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4093 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4094 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4095 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4099 * Clear the GLOBAL_RESET bit.
4101 * Should be run under rtnl lock
4103 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4106 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4107 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4108 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4109 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4113 * Checks the GLOBAL_RESET bit.
4115 * should be run under rtnl lock
4117 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4119 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4121 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4122 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4126 * Clear RESET_IN_PROGRESS bit for the current engine.
4128 * Should be run under rtnl lock
4130 static void bnx2x_set_reset_done(struct bnx2x *bp)
4133 u32 bit = BP_PATH(bp) ?
4134 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4135 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4136 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4140 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4142 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4146 * Set RESET_IN_PROGRESS for the current engine.
4148 * should be run under rtnl lock
4150 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4153 u32 bit = BP_PATH(bp) ?
4154 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4155 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4156 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4160 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4161 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4165 * Checks the RESET_IN_PROGRESS bit for the given engine.
4166 * should be run under rtnl lock
4168 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4170 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4172 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4174 /* return false if bit is set */
4175 return (val & bit) ? false : true;
4179 * set pf load for the current pf.
4181 * should be run under rtnl lock
4183 void bnx2x_set_pf_load(struct bnx2x *bp)
4186 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4187 BNX2X_PATH0_LOAD_CNT_MASK;
4188 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4189 BNX2X_PATH0_LOAD_CNT_SHIFT;
4191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4192 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4194 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4196 /* get the current counter value */
4197 val1 = (val & mask) >> shift;
4199 /* set bit of that PF */
4200 val1 |= (1 << bp->pf_num);
4202 /* clear the old value */
4205 /* set the new one */
4206 val |= ((val1 << shift) & mask);
4208 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4209 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4213 * bnx2x_clear_pf_load - clear pf load mark
4215 * @bp: driver handle
4217 * Should be run under rtnl lock.
4218 * Decrements the load counter for the current engine. Returns
4219 * whether other functions are still loaded
4221 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4224 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4225 BNX2X_PATH0_LOAD_CNT_MASK;
4226 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4227 BNX2X_PATH0_LOAD_CNT_SHIFT;
4229 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4230 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4231 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4233 /* get the current counter value */
4234 val1 = (val & mask) >> shift;
4236 /* clear bit of that PF */
4237 val1 &= ~(1 << bp->pf_num);
4239 /* clear the old value */
4242 /* set the new one */
4243 val |= ((val1 << shift) & mask);
4245 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4246 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4251 * Read the load status for the current engine.
4253 * should be run under rtnl lock
4255 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4257 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4258 BNX2X_PATH0_LOAD_CNT_MASK);
4259 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4260 BNX2X_PATH0_LOAD_CNT_SHIFT);
4261 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4263 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4265 val = (val & mask) >> shift;
4267 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4273 static void _print_parity(struct bnx2x *bp, u32 reg)
4275 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4278 static void _print_next_block(int idx, const char *blk)
4280 pr_cont("%s%s", idx ? ", " : "", blk);
4283 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4284 int par_num, bool print)
4288 for (i = 0; sig; i++) {
4289 cur_bit = ((u32)0x1 << i);
4290 if (sig & cur_bit) {
4292 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4294 _print_next_block(par_num++, "BRB");
4296 BRB1_REG_BRB1_PRTY_STS);
4299 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4301 _print_next_block(par_num++, "PARSER");
4302 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4305 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4307 _print_next_block(par_num++, "TSDM");
4309 TSDM_REG_TSDM_PRTY_STS);
4312 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4314 _print_next_block(par_num++,
4316 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4319 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4321 _print_next_block(par_num++, "TCM");
4323 TCM_REG_TCM_PRTY_STS);
4326 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4328 _print_next_block(par_num++, "TSEMI");
4330 TSEM_REG_TSEM_PRTY_STS_0);
4332 TSEM_REG_TSEM_PRTY_STS_1);
4335 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4337 _print_next_block(par_num++, "XPB");
4338 _print_parity(bp, GRCBASE_XPB +
4339 PB_REG_PB_PRTY_STS);
4352 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4353 int par_num, bool *global,
4358 for (i = 0; sig; i++) {
4359 cur_bit = ((u32)0x1 << i);
4360 if (sig & cur_bit) {
4362 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4364 _print_next_block(par_num++, "PBF");
4365 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4368 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4370 _print_next_block(par_num++, "QM");
4371 _print_parity(bp, QM_REG_QM_PRTY_STS);
4374 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4376 _print_next_block(par_num++, "TM");
4377 _print_parity(bp, TM_REG_TM_PRTY_STS);
4380 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4382 _print_next_block(par_num++, "XSDM");
4384 XSDM_REG_XSDM_PRTY_STS);
4387 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4389 _print_next_block(par_num++, "XCM");
4390 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4393 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4395 _print_next_block(par_num++, "XSEMI");
4397 XSEM_REG_XSEM_PRTY_STS_0);
4399 XSEM_REG_XSEM_PRTY_STS_1);
4402 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4404 _print_next_block(par_num++,
4407 DORQ_REG_DORQ_PRTY_STS);
4410 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4412 _print_next_block(par_num++, "NIG");
4413 if (CHIP_IS_E1x(bp)) {
4415 NIG_REG_NIG_PRTY_STS);
4418 NIG_REG_NIG_PRTY_STS_0);
4420 NIG_REG_NIG_PRTY_STS_1);
4424 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4426 _print_next_block(par_num++,
4430 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4432 _print_next_block(par_num++, "DEBUG");
4433 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4436 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4438 _print_next_block(par_num++, "USDM");
4440 USDM_REG_USDM_PRTY_STS);
4443 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4445 _print_next_block(par_num++, "UCM");
4446 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4449 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4451 _print_next_block(par_num++, "USEMI");
4453 USEM_REG_USEM_PRTY_STS_0);
4455 USEM_REG_USEM_PRTY_STS_1);
4458 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4460 _print_next_block(par_num++, "UPB");
4461 _print_parity(bp, GRCBASE_UPB +
4462 PB_REG_PB_PRTY_STS);
4465 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4467 _print_next_block(par_num++, "CSDM");
4469 CSDM_REG_CSDM_PRTY_STS);
4472 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4474 _print_next_block(par_num++, "CCM");
4475 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4488 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4489 int par_num, bool print)
4493 for (i = 0; sig; i++) {
4494 cur_bit = ((u32)0x1 << i);
4495 if (sig & cur_bit) {
4497 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4499 _print_next_block(par_num++, "CSEMI");
4501 CSEM_REG_CSEM_PRTY_STS_0);
4503 CSEM_REG_CSEM_PRTY_STS_1);
4506 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4508 _print_next_block(par_num++, "PXP");
4509 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4511 PXP2_REG_PXP2_PRTY_STS_0);
4513 PXP2_REG_PXP2_PRTY_STS_1);
4516 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4518 _print_next_block(par_num++,
4519 "PXPPCICLOCKCLIENT");
4521 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4523 _print_next_block(par_num++, "CFC");
4525 CFC_REG_CFC_PRTY_STS);
4528 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4530 _print_next_block(par_num++, "CDU");
4531 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4534 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4536 _print_next_block(par_num++, "DMAE");
4538 DMAE_REG_DMAE_PRTY_STS);
4541 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4543 _print_next_block(par_num++, "IGU");
4544 if (CHIP_IS_E1x(bp))
4546 HC_REG_HC_PRTY_STS);
4549 IGU_REG_IGU_PRTY_STS);
4552 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4554 _print_next_block(par_num++, "MISC");
4556 MISC_REG_MISC_PRTY_STS);
4569 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4570 bool *global, bool print)
4574 for (i = 0; sig; i++) {
4575 cur_bit = ((u32)0x1 << i);
4576 if (sig & cur_bit) {
4578 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4580 _print_next_block(par_num++, "MCP ROM");
4583 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4585 _print_next_block(par_num++,
4589 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4591 _print_next_block(par_num++,
4595 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4597 _print_next_block(par_num++,
4611 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4612 int par_num, bool print)
4616 for (i = 0; sig; i++) {
4617 cur_bit = ((u32)0x1 << i);
4618 if (sig & cur_bit) {
4620 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4622 _print_next_block(par_num++, "PGLUE_B");
4624 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4627 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4629 _print_next_block(par_num++, "ATC");
4631 ATC_REG_ATC_PRTY_STS);
4644 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4647 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4648 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4649 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4650 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4651 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4653 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4654 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4655 sig[0] & HW_PRTY_ASSERT_SET_0,
4656 sig[1] & HW_PRTY_ASSERT_SET_1,
4657 sig[2] & HW_PRTY_ASSERT_SET_2,
4658 sig[3] & HW_PRTY_ASSERT_SET_3,
4659 sig[4] & HW_PRTY_ASSERT_SET_4);
4662 "Parity errors detected in blocks: ");
4663 par_num = bnx2x_check_blocks_with_parity0(bp,
4664 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4665 par_num = bnx2x_check_blocks_with_parity1(bp,
4666 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4667 par_num = bnx2x_check_blocks_with_parity2(bp,
4668 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4669 par_num = bnx2x_check_blocks_with_parity3(
4670 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4671 par_num = bnx2x_check_blocks_with_parity4(bp,
4672 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4683 * bnx2x_chk_parity_attn - checks for parity attentions.
4685 * @bp: driver handle
4686 * @global: true if there was a global attention
4687 * @print: show parity attention in syslog
4689 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4691 struct attn_route attn = { {0} };
4692 int port = BP_PORT(bp);
4694 attn.sig[0] = REG_RD(bp,
4695 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4697 attn.sig[1] = REG_RD(bp,
4698 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4700 attn.sig[2] = REG_RD(bp,
4701 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4703 attn.sig[3] = REG_RD(bp,
4704 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4707 if (!CHIP_IS_E1x(bp))
4708 attn.sig[4] = REG_RD(bp,
4709 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4712 return bnx2x_parity_attn(bp, global, print, attn.sig);
4715 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4718 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4720 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4721 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4722 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4723 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4724 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4725 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4726 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4727 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4728 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4729 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4731 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4732 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4734 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4735 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4736 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4737 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4738 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4739 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4740 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4741 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4743 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4744 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4745 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4746 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4747 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4748 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4749 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4750 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4751 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4752 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4753 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4754 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4755 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4756 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4757 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4760 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4761 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4762 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4763 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4764 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4768 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4770 struct attn_route attn, *group_mask;
4771 int port = BP_PORT(bp);
4776 bool global = false;
4778 /* need to take HW lock because MCP or other port might also
4779 try to handle this event */
4780 bnx2x_acquire_alr(bp);
4782 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4783 #ifndef BNX2X_STOP_ON_ERROR
4784 bp->recovery_state = BNX2X_RECOVERY_INIT;
4785 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4786 /* Disable HW interrupts */
4787 bnx2x_int_disable(bp);
4788 /* In case of parity errors don't handle attentions so that
4789 * other function would "see" parity errors.
4794 bnx2x_release_alr(bp);
4798 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4799 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4800 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4801 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4802 if (!CHIP_IS_E1x(bp))
4804 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4808 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4809 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4811 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4812 if (deasserted & (1 << index)) {
4813 group_mask = &bp->attn_group[index];
4815 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4817 group_mask->sig[0], group_mask->sig[1],
4818 group_mask->sig[2], group_mask->sig[3],
4819 group_mask->sig[4]);
4821 bnx2x_attn_int_deasserted4(bp,
4822 attn.sig[4] & group_mask->sig[4]);
4823 bnx2x_attn_int_deasserted3(bp,
4824 attn.sig[3] & group_mask->sig[3]);
4825 bnx2x_attn_int_deasserted1(bp,
4826 attn.sig[1] & group_mask->sig[1]);
4827 bnx2x_attn_int_deasserted2(bp,
4828 attn.sig[2] & group_mask->sig[2]);
4829 bnx2x_attn_int_deasserted0(bp,
4830 attn.sig[0] & group_mask->sig[0]);
4834 bnx2x_release_alr(bp);
4836 if (bp->common.int_block == INT_BLOCK_HC)
4837 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4838 COMMAND_REG_ATTN_BITS_CLR);
4840 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4843 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4844 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4845 REG_WR(bp, reg_addr, val);
4847 if (~bp->attn_state & deasserted)
4848 BNX2X_ERR("IGU ERROR\n");
4850 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4851 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4853 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4854 aeu_mask = REG_RD(bp, reg_addr);
4856 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4857 aeu_mask, deasserted);
4858 aeu_mask |= (deasserted & 0x3ff);
4859 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4861 REG_WR(bp, reg_addr, aeu_mask);
4862 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4864 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4865 bp->attn_state &= ~deasserted;
4866 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4869 static void bnx2x_attn_int(struct bnx2x *bp)
4871 /* read local copy of bits */
4872 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4874 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4876 u32 attn_state = bp->attn_state;
4878 /* look for changed bits */
4879 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4880 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4883 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4884 attn_bits, attn_ack, asserted, deasserted);
4886 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4887 BNX2X_ERR("BAD attention state\n");
4889 /* handle bits that were raised */
4891 bnx2x_attn_int_asserted(bp, asserted);
4894 bnx2x_attn_int_deasserted(bp, deasserted);
4897 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4898 u16 index, u8 op, u8 update)
4900 u32 igu_addr = bp->igu_base_addr;
4901 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4902 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4906 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4908 /* No memory barriers */
4909 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4910 mmiowb(); /* keep prod updates ordered */
4913 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4914 union event_ring_elem *elem)
4916 u8 err = elem->message.error;
4918 if (!bp->cnic_eth_dev.starting_cid ||
4919 (cid < bp->cnic_eth_dev.starting_cid &&
4920 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4923 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4925 if (unlikely(err)) {
4927 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4929 bnx2x_panic_dump(bp, false);
4931 bnx2x_cnic_cfc_comp(bp, cid, err);
4935 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4937 struct bnx2x_mcast_ramrod_params rparam;
4940 memset(&rparam, 0, sizeof(rparam));
4942 rparam.mcast_obj = &bp->mcast_obj;
4944 netif_addr_lock_bh(bp->dev);
4946 /* Clear pending state for the last command */
4947 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4949 /* If there are pending mcast commands - send them */
4950 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4951 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4953 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4957 netif_addr_unlock_bh(bp->dev);
4960 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4961 union event_ring_elem *elem)
4963 unsigned long ramrod_flags = 0;
4965 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4966 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4968 /* Always push next commands out, don't wait here */
4969 __set_bit(RAMROD_CONT, &ramrod_flags);
4971 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4972 >> BNX2X_SWCID_SHIFT) {
4973 case BNX2X_FILTER_MAC_PENDING:
4974 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4975 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4976 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4978 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4981 case BNX2X_FILTER_MCAST_PENDING:
4982 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4983 /* This is only relevant for 57710 where multicast MACs are
4984 * configured as unicast MACs using the same ramrod.
4986 bnx2x_handle_mcast_eqe(bp);
4989 BNX2X_ERR("Unsupported classification command: %d\n",
4990 elem->message.data.eth_event.echo);
4994 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4997 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4999 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5002 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5004 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5006 netif_addr_lock_bh(bp->dev);
5008 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5010 /* Send rx_mode command again if was requested */
5011 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5012 bnx2x_set_storm_rx_mode(bp);
5013 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5015 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5016 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5018 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5020 netif_addr_unlock_bh(bp->dev);
5023 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5024 union event_ring_elem *elem)
5026 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5028 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5029 elem->message.data.vif_list_event.func_bit_map);
5030 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5031 elem->message.data.vif_list_event.func_bit_map);
5032 } else if (elem->message.data.vif_list_event.echo ==
5033 VIF_LIST_RULE_SET) {
5034 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5035 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5039 /* called with rtnl_lock */
5040 static void bnx2x_after_function_update(struct bnx2x *bp)
5043 struct bnx2x_fastpath *fp;
5044 struct bnx2x_queue_state_params queue_params = {NULL};
5045 struct bnx2x_queue_update_params *q_update_params =
5046 &queue_params.params.update;
5048 /* Send Q update command with afex vlan removal values for all Qs */
5049 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5051 /* set silent vlan removal values according to vlan mode */
5052 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5053 &q_update_params->update_flags);
5054 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5055 &q_update_params->update_flags);
5056 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5058 /* in access mode mark mask and value are 0 to strip all vlans */
5059 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5060 q_update_params->silent_removal_value = 0;
5061 q_update_params->silent_removal_mask = 0;
5063 q_update_params->silent_removal_value =
5064 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5065 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5068 for_each_eth_queue(bp, q) {
5069 /* Set the appropriate Queue object */
5071 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5073 /* send the ramrod */
5074 rc = bnx2x_queue_state_change(bp, &queue_params);
5076 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5080 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5081 fp = &bp->fp[FCOE_IDX(bp)];
5082 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5084 /* clear pending completion bit */
5085 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5087 /* mark latest Q bit */
5088 smp_mb__before_clear_bit();
5089 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5090 smp_mb__after_clear_bit();
5092 /* send Q update ramrod for FCoE Q */
5093 rc = bnx2x_queue_state_change(bp, &queue_params);
5095 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5098 /* If no FCoE ring - ACK MCP now */
5099 bnx2x_link_report(bp);
5100 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5104 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5105 struct bnx2x *bp, u32 cid)
5107 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5109 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5110 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5112 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5115 static void bnx2x_eq_int(struct bnx2x *bp)
5117 u16 hw_cons, sw_cons, sw_prod;
5118 union event_ring_elem *elem;
5122 int rc, spqe_cnt = 0;
5123 struct bnx2x_queue_sp_obj *q_obj;
5124 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5125 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5127 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5129 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5130 * when we get the next-page we need to adjust so the loop
5131 * condition below will be met. The next element is the size of a
5132 * regular element and hence incrementing by 1
5134 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5137 /* This function may never run in parallel with itself for a
5138 * specific bp, thus there is no need in "paired" read memory
5141 sw_cons = bp->eq_cons;
5142 sw_prod = bp->eq_prod;
5144 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5145 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5147 for (; sw_cons != hw_cons;
5148 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5150 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5152 rc = bnx2x_iov_eq_sp_event(bp, elem);
5154 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5159 /* elem CID originates from FW; actually LE */
5160 cid = SW_CID((__force __le32)
5161 elem->message.data.cfc_del_event.cid);
5162 opcode = elem->message.opcode;
5164 /* handle eq element */
5166 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5167 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5168 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5171 case EVENT_RING_OPCODE_STAT_QUERY:
5172 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5173 "got statistics comp event %d\n",
5175 /* nothing to do with stats comp */
5178 case EVENT_RING_OPCODE_CFC_DEL:
5179 /* handle according to cid range */
5181 * we may want to verify here that the bp state is
5185 "got delete ramrod for MULTI[%d]\n", cid);
5187 if (CNIC_LOADED(bp) &&
5188 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5191 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5193 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5198 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5199 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5200 if (f_obj->complete_cmd(bp, f_obj,
5201 BNX2X_F_CMD_TX_STOP))
5203 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5206 case EVENT_RING_OPCODE_START_TRAFFIC:
5207 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5208 if (f_obj->complete_cmd(bp, f_obj,
5209 BNX2X_F_CMD_TX_START))
5211 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5214 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5215 echo = elem->message.data.function_update_event.echo;
5216 if (echo == SWITCH_UPDATE) {
5217 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5218 "got FUNC_SWITCH_UPDATE ramrod\n");
5219 if (f_obj->complete_cmd(
5220 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5224 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5225 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5226 f_obj->complete_cmd(bp, f_obj,
5227 BNX2X_F_CMD_AFEX_UPDATE);
5229 /* We will perform the Queues update from
5230 * sp_rtnl task as all Queue SP operations
5231 * should run under rtnl_lock.
5233 smp_mb__before_clear_bit();
5234 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5235 &bp->sp_rtnl_state);
5236 smp_mb__after_clear_bit();
5238 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5243 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5244 f_obj->complete_cmd(bp, f_obj,
5245 BNX2X_F_CMD_AFEX_VIFLISTS);
5246 bnx2x_after_afex_vif_lists(bp, elem);
5248 case EVENT_RING_OPCODE_FUNCTION_START:
5249 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5250 "got FUNC_START ramrod\n");
5251 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5256 case EVENT_RING_OPCODE_FUNCTION_STOP:
5257 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5258 "got FUNC_STOP ramrod\n");
5259 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5265 switch (opcode | bp->state) {
5266 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5268 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5269 BNX2X_STATE_OPENING_WAIT4_PORT):
5270 cid = elem->message.data.eth_event.echo &
5272 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5274 rss_raw->clear_pending(rss_raw);
5277 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5278 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5279 case (EVENT_RING_OPCODE_SET_MAC |
5280 BNX2X_STATE_CLOSING_WAIT4_HALT):
5281 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5283 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5285 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5286 BNX2X_STATE_CLOSING_WAIT4_HALT):
5287 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5288 bnx2x_handle_classification_eqe(bp, elem);
5291 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5293 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5295 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5296 BNX2X_STATE_CLOSING_WAIT4_HALT):
5297 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5298 bnx2x_handle_mcast_eqe(bp);
5301 case (EVENT_RING_OPCODE_FILTERS_RULES |
5303 case (EVENT_RING_OPCODE_FILTERS_RULES |
5305 case (EVENT_RING_OPCODE_FILTERS_RULES |
5306 BNX2X_STATE_CLOSING_WAIT4_HALT):
5307 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5308 bnx2x_handle_rx_mode_eqe(bp);
5311 /* unknown event log error and continue */
5312 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5313 elem->message.opcode, bp->state);
5319 smp_mb__before_atomic_inc();
5320 atomic_add(spqe_cnt, &bp->eq_spq_left);
5322 bp->eq_cons = sw_cons;
5323 bp->eq_prod = sw_prod;
5324 /* Make sure that above mem writes were issued towards the memory */
5327 /* update producer */
5328 bnx2x_update_eq_prod(bp, bp->eq_prod);
5331 static void bnx2x_sp_task(struct work_struct *work)
5333 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5335 DP(BNX2X_MSG_SP, "sp task invoked\n");
5337 /* make sure the atomic interrupt_occurred has been written */
5339 if (atomic_read(&bp->interrupt_occurred)) {
5341 /* what work needs to be performed? */
5342 u16 status = bnx2x_update_dsb_idx(bp);
5344 DP(BNX2X_MSG_SP, "status %x\n", status);
5345 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5346 atomic_set(&bp->interrupt_occurred, 0);
5349 if (status & BNX2X_DEF_SB_ATT_IDX) {
5351 status &= ~BNX2X_DEF_SB_ATT_IDX;
5354 /* SP events: STAT_QUERY and others */
5355 if (status & BNX2X_DEF_SB_IDX) {
5356 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5358 if (FCOE_INIT(bp) &&
5359 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5360 /* Prevent local bottom-halves from running as
5361 * we are going to change the local NAPI list.
5364 napi_schedule(&bnx2x_fcoe(bp, napi));
5368 /* Handle EQ completions */
5370 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5371 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5373 status &= ~BNX2X_DEF_SB_IDX;
5376 /* if status is non zero then perhaps something went wrong */
5377 if (unlikely(status))
5379 "got an unknown interrupt! (status 0x%x)\n", status);
5381 /* ack status block only if something was actually handled */
5382 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5383 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5386 /* must be called after the EQ processing (since eq leads to sriov
5387 * ramrod completion flows).
5388 * This flow may have been scheduled by the arrival of a ramrod
5389 * completion, or by the sriov code rescheduling itself.
5391 bnx2x_iov_sp_task(bp);
5393 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5394 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5396 bnx2x_link_report(bp);
5397 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5401 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5403 struct net_device *dev = dev_instance;
5404 struct bnx2x *bp = netdev_priv(dev);
5406 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5407 IGU_INT_DISABLE, 0);
5409 #ifdef BNX2X_STOP_ON_ERROR
5410 if (unlikely(bp->panic))
5414 if (CNIC_LOADED(bp)) {
5415 struct cnic_ops *c_ops;
5418 c_ops = rcu_dereference(bp->cnic_ops);
5420 c_ops->cnic_handler(bp->cnic_data, NULL);
5424 /* schedule sp task to perform default status block work, ack
5425 * attentions and enable interrupts.
5427 bnx2x_schedule_sp_task(bp);
5432 /* end of slow path */
5434 void bnx2x_drv_pulse(struct bnx2x *bp)
5436 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5437 bp->fw_drv_pulse_wr_seq);
5440 static void bnx2x_timer(unsigned long data)
5442 struct bnx2x *bp = (struct bnx2x *) data;
5444 if (!netif_running(bp->dev))
5449 int mb_idx = BP_FW_MB_IDX(bp);
5453 ++bp->fw_drv_pulse_wr_seq;
5454 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5455 /* TBD - add SYSTEM_TIME */
5456 drv_pulse = bp->fw_drv_pulse_wr_seq;
5457 bnx2x_drv_pulse(bp);
5459 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5460 MCP_PULSE_SEQ_MASK);
5461 /* The delta between driver pulse and mcp response
5462 * should be 1 (before mcp response) or 0 (after mcp response)
5464 if ((drv_pulse != mcp_pulse) &&
5465 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5466 /* someone lost a heartbeat... */
5467 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5468 drv_pulse, mcp_pulse);
5472 if (bp->state == BNX2X_STATE_OPEN)
5473 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5475 /* sample pf vf bulletin board for new posts from pf */
5477 bnx2x_timer_sriov(bp);
5479 mod_timer(&bp->timer, jiffies + bp->current_interval);
5482 /* end of Statistics */
5487 * nic init service functions
5490 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5493 if (!(len%4) && !(addr%4))
5494 for (i = 0; i < len; i += 4)
5495 REG_WR(bp, addr + i, fill);
5497 for (i = 0; i < len; i++)
5498 REG_WR8(bp, addr + i, fill);
5501 /* helper: writes FP SP data to FW - data_size in dwords */
5502 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5508 for (index = 0; index < data_size; index++)
5509 REG_WR(bp, BAR_CSTRORM_INTMEM +
5510 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5512 *(sb_data_p + index));
5515 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5519 struct hc_status_block_data_e2 sb_data_e2;
5520 struct hc_status_block_data_e1x sb_data_e1x;
5522 /* disable the function first */
5523 if (!CHIP_IS_E1x(bp)) {
5524 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5525 sb_data_e2.common.state = SB_DISABLED;
5526 sb_data_e2.common.p_func.vf_valid = false;
5527 sb_data_p = (u32 *)&sb_data_e2;
5528 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5530 memset(&sb_data_e1x, 0,
5531 sizeof(struct hc_status_block_data_e1x));
5532 sb_data_e1x.common.state = SB_DISABLED;
5533 sb_data_e1x.common.p_func.vf_valid = false;
5534 sb_data_p = (u32 *)&sb_data_e1x;
5535 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5537 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5539 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5540 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5541 CSTORM_STATUS_BLOCK_SIZE);
5542 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5543 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5544 CSTORM_SYNC_BLOCK_SIZE);
5547 /* helper: writes SP SB data to FW */
5548 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5549 struct hc_sp_status_block_data *sp_sb_data)
5551 int func = BP_FUNC(bp);
5553 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5554 REG_WR(bp, BAR_CSTRORM_INTMEM +
5555 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5557 *((u32 *)sp_sb_data + i));
5560 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5562 int func = BP_FUNC(bp);
5563 struct hc_sp_status_block_data sp_sb_data;
5564 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5566 sp_sb_data.state = SB_DISABLED;
5567 sp_sb_data.p_func.vf_valid = false;
5569 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5571 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5572 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5573 CSTORM_SP_STATUS_BLOCK_SIZE);
5574 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5575 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5576 CSTORM_SP_SYNC_BLOCK_SIZE);
5579 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5580 int igu_sb_id, int igu_seg_id)
5582 hc_sm->igu_sb_id = igu_sb_id;
5583 hc_sm->igu_seg_id = igu_seg_id;
5584 hc_sm->timer_value = 0xFF;
5585 hc_sm->time_to_expire = 0xFFFFFFFF;
5588 /* allocates state machine ids. */
5589 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5591 /* zero out state machine indices */
5593 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5596 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5597 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5598 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5599 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5603 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5604 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5607 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5608 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5609 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5610 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5611 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5612 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5613 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5614 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5617 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5618 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5622 struct hc_status_block_data_e2 sb_data_e2;
5623 struct hc_status_block_data_e1x sb_data_e1x;
5624 struct hc_status_block_sm *hc_sm_p;
5628 if (CHIP_INT_MODE_IS_BC(bp))
5629 igu_seg_id = HC_SEG_ACCESS_NORM;
5631 igu_seg_id = IGU_SEG_ACCESS_NORM;
5633 bnx2x_zero_fp_sb(bp, fw_sb_id);
5635 if (!CHIP_IS_E1x(bp)) {
5636 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5637 sb_data_e2.common.state = SB_ENABLED;
5638 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5639 sb_data_e2.common.p_func.vf_id = vfid;
5640 sb_data_e2.common.p_func.vf_valid = vf_valid;
5641 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5642 sb_data_e2.common.same_igu_sb_1b = true;
5643 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5644 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5645 hc_sm_p = sb_data_e2.common.state_machine;
5646 sb_data_p = (u32 *)&sb_data_e2;
5647 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5648 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5650 memset(&sb_data_e1x, 0,
5651 sizeof(struct hc_status_block_data_e1x));
5652 sb_data_e1x.common.state = SB_ENABLED;
5653 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5654 sb_data_e1x.common.p_func.vf_id = 0xff;
5655 sb_data_e1x.common.p_func.vf_valid = false;
5656 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5657 sb_data_e1x.common.same_igu_sb_1b = true;
5658 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5659 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5660 hc_sm_p = sb_data_e1x.common.state_machine;
5661 sb_data_p = (u32 *)&sb_data_e1x;
5662 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5663 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5666 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5667 igu_sb_id, igu_seg_id);
5668 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5669 igu_sb_id, igu_seg_id);
5671 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5673 /* write indices to HW - PCI guarantees endianity of regpairs */
5674 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5677 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5678 u16 tx_usec, u16 rx_usec)
5680 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5682 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5683 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5685 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5686 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5688 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5689 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5693 static void bnx2x_init_def_sb(struct bnx2x *bp)
5695 struct host_sp_status_block *def_sb = bp->def_status_blk;
5696 dma_addr_t mapping = bp->def_status_blk_mapping;
5697 int igu_sp_sb_index;
5699 int port = BP_PORT(bp);
5700 int func = BP_FUNC(bp);
5701 int reg_offset, reg_offset_en5;
5704 struct hc_sp_status_block_data sp_sb_data;
5705 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5707 if (CHIP_INT_MODE_IS_BC(bp)) {
5708 igu_sp_sb_index = DEF_SB_IGU_ID;
5709 igu_seg_id = HC_SEG_ACCESS_DEF;
5711 igu_sp_sb_index = bp->igu_dsb_id;
5712 igu_seg_id = IGU_SEG_ACCESS_DEF;
5716 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5717 atten_status_block);
5718 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5722 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5723 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5724 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5725 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5726 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5728 /* take care of sig[0]..sig[4] */
5729 for (sindex = 0; sindex < 4; sindex++)
5730 bp->attn_group[index].sig[sindex] =
5731 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5733 if (!CHIP_IS_E1x(bp))
5735 * enable5 is separate from the rest of the registers,
5736 * and therefore the address skip is 4
5737 * and not 16 between the different groups
5739 bp->attn_group[index].sig[4] = REG_RD(bp,
5740 reg_offset_en5 + 0x4*index);
5742 bp->attn_group[index].sig[4] = 0;
5745 if (bp->common.int_block == INT_BLOCK_HC) {
5746 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5747 HC_REG_ATTN_MSG0_ADDR_L);
5749 REG_WR(bp, reg_offset, U64_LO(section));
5750 REG_WR(bp, reg_offset + 4, U64_HI(section));
5751 } else if (!CHIP_IS_E1x(bp)) {
5752 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5753 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5756 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5759 bnx2x_zero_sp_sb(bp);
5761 /* PCI guarantees endianity of regpairs */
5762 sp_sb_data.state = SB_ENABLED;
5763 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5764 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5765 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5766 sp_sb_data.igu_seg_id = igu_seg_id;
5767 sp_sb_data.p_func.pf_id = func;
5768 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5769 sp_sb_data.p_func.vf_id = 0xff;
5771 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5773 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5776 void bnx2x_update_coalesce(struct bnx2x *bp)
5780 for_each_eth_queue(bp, i)
5781 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5782 bp->tx_ticks, bp->rx_ticks);
5785 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5787 spin_lock_init(&bp->spq_lock);
5788 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5790 bp->spq_prod_idx = 0;
5791 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5792 bp->spq_prod_bd = bp->spq;
5793 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5796 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5799 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5800 union event_ring_elem *elem =
5801 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5803 elem->next_page.addr.hi =
5804 cpu_to_le32(U64_HI(bp->eq_mapping +
5805 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5806 elem->next_page.addr.lo =
5807 cpu_to_le32(U64_LO(bp->eq_mapping +
5808 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5811 bp->eq_prod = NUM_EQ_DESC;
5812 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5813 /* we want a warning message before it gets wrought... */
5814 atomic_set(&bp->eq_spq_left,
5815 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5818 /* called with netif_addr_lock_bh() */
5819 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5820 unsigned long rx_mode_flags,
5821 unsigned long rx_accept_flags,
5822 unsigned long tx_accept_flags,
5823 unsigned long ramrod_flags)
5825 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5828 memset(&ramrod_param, 0, sizeof(ramrod_param));
5830 /* Prepare ramrod parameters */
5831 ramrod_param.cid = 0;
5832 ramrod_param.cl_id = cl_id;
5833 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5834 ramrod_param.func_id = BP_FUNC(bp);
5836 ramrod_param.pstate = &bp->sp_state;
5837 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5839 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5840 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5842 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5844 ramrod_param.ramrod_flags = ramrod_flags;
5845 ramrod_param.rx_mode_flags = rx_mode_flags;
5847 ramrod_param.rx_accept_flags = rx_accept_flags;
5848 ramrod_param.tx_accept_flags = tx_accept_flags;
5850 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5852 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5859 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5860 unsigned long *rx_accept_flags,
5861 unsigned long *tx_accept_flags)
5863 /* Clear the flags first */
5864 *rx_accept_flags = 0;
5865 *tx_accept_flags = 0;
5868 case BNX2X_RX_MODE_NONE:
5870 * 'drop all' supersedes any accept flags that may have been
5871 * passed to the function.
5874 case BNX2X_RX_MODE_NORMAL:
5875 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5876 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5877 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5879 /* internal switching mode */
5880 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5881 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5882 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5885 case BNX2X_RX_MODE_ALLMULTI:
5886 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5887 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5888 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5890 /* internal switching mode */
5891 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5892 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5893 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5896 case BNX2X_RX_MODE_PROMISC:
5897 /* According to definition of SI mode, iface in promisc mode
5898 * should receive matched and unmatched (in resolution of port)
5901 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5902 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5903 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5904 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5906 /* internal switching mode */
5907 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5908 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5911 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5913 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5917 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5921 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5922 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5923 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5924 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5930 /* called with netif_addr_lock_bh() */
5931 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5933 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5934 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5938 /* Configure rx_mode of FCoE Queue */
5939 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5941 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5946 __set_bit(RAMROD_RX, &ramrod_flags);
5947 __set_bit(RAMROD_TX, &ramrod_flags);
5949 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5950 rx_accept_flags, tx_accept_flags,
5954 static void bnx2x_init_internal_common(struct bnx2x *bp)
5960 * In switch independent mode, the TSTORM needs to accept
5961 * packets that failed classification, since approximate match
5962 * mac addresses aren't written to NIG LLH
5964 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5965 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5966 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5967 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5968 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5970 /* Zero this manually as its initialization is
5971 currently missing in the initTool */
5972 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5973 REG_WR(bp, BAR_USTRORM_INTMEM +
5974 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5975 if (!CHIP_IS_E1x(bp)) {
5976 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5977 CHIP_INT_MODE_IS_BC(bp) ?
5978 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5982 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5984 switch (load_code) {
5985 case FW_MSG_CODE_DRV_LOAD_COMMON:
5986 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5987 bnx2x_init_internal_common(bp);
5990 case FW_MSG_CODE_DRV_LOAD_PORT:
5994 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5995 /* internal memory per function is
5996 initialized inside bnx2x_pf_init */
6000 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6005 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6007 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6010 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6012 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6015 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6017 if (CHIP_IS_E1x(fp->bp))
6018 return BP_L_ID(fp->bp) + fp->index;
6019 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6020 return bnx2x_fp_igu_sb_id(fp);
6023 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6025 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6027 unsigned long q_type = 0;
6028 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6029 fp->rx_queue = fp_idx;
6031 fp->cl_id = bnx2x_fp_cl_id(fp);
6032 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6033 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6034 /* qZone id equals to FW (per path) client id */
6035 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6038 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6040 /* Setup SB indices */
6041 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6043 /* Configure Queue State object */
6044 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6045 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6047 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6050 for_each_cos_in_tx_queue(fp, cos) {
6051 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6052 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6053 FP_COS_TO_TXQ(fp, cos, bp),
6054 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6055 cids[cos] = fp->txdata_ptr[cos]->cid;
6058 /* nothing more for vf to do here */
6062 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6063 fp->fw_sb_id, fp->igu_sb_id);
6064 bnx2x_update_fpsb_idx(fp);
6065 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6066 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6067 bnx2x_sp_mapping(bp, q_rdata), q_type);
6070 * Configure classification DBs: Always enable Tx switching
6072 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6075 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6076 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6080 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6084 for (i = 1; i <= NUM_TX_RINGS; i++) {
6085 struct eth_tx_next_bd *tx_next_bd =
6086 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6088 tx_next_bd->addr_hi =
6089 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6090 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6091 tx_next_bd->addr_lo =
6092 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6093 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6096 *txdata->tx_cons_sb = cpu_to_le16(0);
6098 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6099 txdata->tx_db.data.zero_fill1 = 0;
6100 txdata->tx_db.data.prod = 0;
6102 txdata->tx_pkt_prod = 0;
6103 txdata->tx_pkt_cons = 0;
6104 txdata->tx_bd_prod = 0;
6105 txdata->tx_bd_cons = 0;
6109 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6113 for_each_tx_queue_cnic(bp, i)
6114 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6117 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6122 for_each_eth_queue(bp, i)
6123 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6124 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6127 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6130 bnx2x_init_fcoe_fp(bp);
6132 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6133 BNX2X_VF_ID_INVALID, false,
6134 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6136 /* ensure status block indices were read */
6138 bnx2x_init_rx_rings_cnic(bp);
6139 bnx2x_init_tx_rings_cnic(bp);
6146 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6150 /* Setup NIC internals and enable interrupts */
6151 for_each_eth_queue(bp, i)
6152 bnx2x_init_eth_fp(bp, i);
6154 /* ensure status block indices were read */
6156 bnx2x_init_rx_rings(bp);
6157 bnx2x_init_tx_rings(bp);
6160 /* Initialize MOD_ABS interrupts */
6161 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6162 bp->common.shmem_base,
6163 bp->common.shmem2_base, BP_PORT(bp));
6165 /* initialize the default status block and sp ring */
6166 bnx2x_init_def_sb(bp);
6167 bnx2x_update_dsb_idx(bp);
6168 bnx2x_init_sp_ring(bp);
6170 bnx2x_memset_stats(bp);
6174 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6176 bnx2x_init_eq_ring(bp);
6177 bnx2x_init_internal(bp, load_code);
6179 bnx2x_stats_init(bp);
6181 /* flush all before enabling interrupts */
6185 bnx2x_int_enable(bp);
6187 /* Check for SPIO5 */
6188 bnx2x_attn_int_deasserted0(bp,
6189 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6190 AEU_INPUTS_ATTN_BITS_SPIO5);
6193 /* gzip service functions */
6194 static int bnx2x_gunzip_init(struct bnx2x *bp)
6196 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6197 &bp->gunzip_mapping, GFP_KERNEL);
6198 if (bp->gunzip_buf == NULL)
6201 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6202 if (bp->strm == NULL)
6205 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6206 if (bp->strm->workspace == NULL)
6216 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6217 bp->gunzip_mapping);
6218 bp->gunzip_buf = NULL;
6221 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6225 static void bnx2x_gunzip_end(struct bnx2x *bp)
6228 vfree(bp->strm->workspace);
6233 if (bp->gunzip_buf) {
6234 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6235 bp->gunzip_mapping);
6236 bp->gunzip_buf = NULL;
6240 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6244 /* check gzip header */
6245 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6246 BNX2X_ERR("Bad gzip header\n");
6254 if (zbuf[3] & FNAME)
6255 while ((zbuf[n++] != 0) && (n < len));
6257 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6258 bp->strm->avail_in = len - n;
6259 bp->strm->next_out = bp->gunzip_buf;
6260 bp->strm->avail_out = FW_BUF_SIZE;
6262 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6266 rc = zlib_inflate(bp->strm, Z_FINISH);
6267 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6268 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6271 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6272 if (bp->gunzip_outlen & 0x3)
6274 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6276 bp->gunzip_outlen >>= 2;
6278 zlib_inflateEnd(bp->strm);
6280 if (rc == Z_STREAM_END)
6286 /* nic load/unload */
6289 * General service functions
6292 /* send a NIG loopback debug packet */
6293 static void bnx2x_lb_pckt(struct bnx2x *bp)
6297 /* Ethernet source and destination addresses */
6298 wb_write[0] = 0x55555555;
6299 wb_write[1] = 0x55555555;
6300 wb_write[2] = 0x20; /* SOP */
6301 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6303 /* NON-IP protocol */
6304 wb_write[0] = 0x09000000;
6305 wb_write[1] = 0x55555555;
6306 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6307 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6310 /* some of the internal memories
6311 * are not directly readable from the driver
6312 * to test them we send debug packets
6314 static int bnx2x_int_mem_test(struct bnx2x *bp)
6320 if (CHIP_REV_IS_FPGA(bp))
6322 else if (CHIP_REV_IS_EMUL(bp))
6327 /* Disable inputs of parser neighbor blocks */
6328 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6329 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6330 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6331 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6333 /* Write 0 to parser credits for CFC search request */
6334 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6336 /* send Ethernet packet */
6339 /* TODO do i reset NIG statistic? */
6340 /* Wait until NIG register shows 1 packet of size 0x10 */
6341 count = 1000 * factor;
6344 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6345 val = *bnx2x_sp(bp, wb_data[0]);
6349 usleep_range(10000, 20000);
6353 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6357 /* Wait until PRS register shows 1 packet */
6358 count = 1000 * factor;
6360 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6364 usleep_range(10000, 20000);
6368 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6372 /* Reset and init BRB, PRS */
6373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6377 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6378 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6380 DP(NETIF_MSG_HW, "part2\n");
6382 /* Disable inputs of parser neighbor blocks */
6383 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6384 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6385 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6386 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6388 /* Write 0 to parser credits for CFC search request */
6389 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6391 /* send 10 Ethernet packets */
6392 for (i = 0; i < 10; i++)
6395 /* Wait until NIG register shows 10 + 1
6396 packets of size 11*0x10 = 0xb0 */
6397 count = 1000 * factor;
6400 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6401 val = *bnx2x_sp(bp, wb_data[0]);
6405 usleep_range(10000, 20000);
6409 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6413 /* Wait until PRS register shows 2 packets */
6414 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6416 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6418 /* Write 1 to parser credits for CFC search request */
6419 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6421 /* Wait until PRS register shows 3 packets */
6422 msleep(10 * factor);
6423 /* Wait until NIG register shows 1 packet of size 0x10 */
6424 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6426 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6428 /* clear NIG EOP FIFO */
6429 for (i = 0; i < 11; i++)
6430 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6431 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6433 BNX2X_ERR("clear of NIG failed\n");
6437 /* Reset and init BRB, PRS, NIG */
6438 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6440 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6442 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6443 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6444 if (!CNIC_SUPPORT(bp))
6446 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6448 /* Enable inputs of parser neighbor blocks */
6449 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6450 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6451 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6452 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6454 DP(NETIF_MSG_HW, "done\n");
6459 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6463 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6464 if (!CHIP_IS_E1x(bp))
6465 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6467 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6468 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6469 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6471 * mask read length error interrupts in brb for parser
6472 * (parsing unit and 'checksum and crc' unit)
6473 * these errors are legal (PU reads fixed length and CAC can cause
6474 * read length error on truncated packets)
6476 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6477 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6478 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6479 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6480 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6481 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6482 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6483 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6484 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6485 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6486 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6487 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6488 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6489 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6490 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6491 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6492 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6493 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6494 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6496 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6497 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6498 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6499 if (!CHIP_IS_E1x(bp))
6500 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6501 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6502 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6504 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6505 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6506 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6507 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6509 if (!CHIP_IS_E1x(bp))
6510 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6511 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6513 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6514 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6515 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6516 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6519 static void bnx2x_reset_common(struct bnx2x *bp)
6524 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6527 if (CHIP_IS_E3(bp)) {
6528 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6529 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6532 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6535 static void bnx2x_setup_dmae(struct bnx2x *bp)
6538 spin_lock_init(&bp->dmae_lock);
6541 static void bnx2x_init_pxp(struct bnx2x *bp)
6544 int r_order, w_order;
6546 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6547 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6548 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6550 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6552 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6556 bnx2x_init_pxp_arb(bp, r_order, w_order);
6559 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6569 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6570 SHARED_HW_CFG_FAN_FAILURE_MASK;
6572 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6576 * The fan failure mechanism is usually related to the PHY type since
6577 * the power consumption of the board is affected by the PHY. Currently,
6578 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6580 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6581 for (port = PORT_0; port < PORT_MAX; port++) {
6583 bnx2x_fan_failure_det_req(
6585 bp->common.shmem_base,
6586 bp->common.shmem2_base,
6590 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6592 if (is_required == 0)
6595 /* Fan failure is indicated by SPIO 5 */
6596 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6598 /* set to active low mode */
6599 val = REG_RD(bp, MISC_REG_SPIO_INT);
6600 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6601 REG_WR(bp, MISC_REG_SPIO_INT, val);
6603 /* enable interrupt to signal the IGU */
6604 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6605 val |= MISC_SPIO_SPIO5;
6606 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6609 void bnx2x_pf_disable(struct bnx2x *bp)
6611 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6612 val &= ~IGU_PF_CONF_FUNC_EN;
6614 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6615 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6616 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6619 static void bnx2x__common_init_phy(struct bnx2x *bp)
6621 u32 shmem_base[2], shmem2_base[2];
6622 /* Avoid common init in case MFW supports LFA */
6623 if (SHMEM2_RD(bp, size) >
6624 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6626 shmem_base[0] = bp->common.shmem_base;
6627 shmem2_base[0] = bp->common.shmem2_base;
6628 if (!CHIP_IS_E1x(bp)) {
6630 SHMEM2_RD(bp, other_shmem_base_addr);
6632 SHMEM2_RD(bp, other_shmem2_base_addr);
6634 bnx2x_acquire_phy_lock(bp);
6635 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6636 bp->common.chip_id);
6637 bnx2x_release_phy_lock(bp);
6641 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6643 * @bp: driver handle
6645 static int bnx2x_init_hw_common(struct bnx2x *bp)
6649 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6652 * take the RESET lock to protect undi_unload flow from accessing
6653 * registers while we're resetting the chip
6655 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6657 bnx2x_reset_common(bp);
6658 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6661 if (CHIP_IS_E3(bp)) {
6662 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6663 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6665 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6667 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6669 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6671 if (!CHIP_IS_E1x(bp)) {
6675 * 4-port mode or 2-port mode we need to turn of master-enable
6676 * for everyone, after that, turn it back on for self.
6677 * so, we disregard multi-function or not, and always disable
6678 * for all functions on the given path, this means 0,2,4,6 for
6679 * path 0 and 1,3,5,7 for path 1
6681 for (abs_func_id = BP_PATH(bp);
6682 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6683 if (abs_func_id == BP_ABS_FUNC(bp)) {
6685 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6690 bnx2x_pretend_func(bp, abs_func_id);
6691 /* clear pf enable */
6692 bnx2x_pf_disable(bp);
6693 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6697 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6698 if (CHIP_IS_E1(bp)) {
6699 /* enable HW interrupt from PXP on USDM overflow
6700 bit 16 on INT_MASK_0 */
6701 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6704 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6708 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6709 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6710 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6711 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6712 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6713 /* make sure this value is 0 */
6714 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6716 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6717 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6718 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6719 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6720 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6723 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6725 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6726 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6728 /* let the HW do it's magic ... */
6730 /* finish PXP init */
6731 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6733 BNX2X_ERR("PXP2 CFG failed\n");
6736 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6738 BNX2X_ERR("PXP2 RD_INIT failed\n");
6742 /* Timers bug workaround E2 only. We need to set the entire ILT to
6743 * have entries with value "0" and valid bit on.
6744 * This needs to be done by the first PF that is loaded in a path
6745 * (i.e. common phase)
6747 if (!CHIP_IS_E1x(bp)) {
6748 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6749 * (i.e. vnic3) to start even if it is marked as "scan-off".
6750 * This occurs when a different function (func2,3) is being marked
6751 * as "scan-off". Real-life scenario for example: if a driver is being
6752 * load-unloaded while func6,7 are down. This will cause the timer to access
6753 * the ilt, translate to a logical address and send a request to read/write.
6754 * Since the ilt for the function that is down is not valid, this will cause
6755 * a translation error which is unrecoverable.
6756 * The Workaround is intended to make sure that when this happens nothing fatal
6757 * will occur. The workaround:
6758 * 1. First PF driver which loads on a path will:
6759 * a. After taking the chip out of reset, by using pretend,
6760 * it will write "0" to the following registers of
6762 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6763 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6764 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6765 * And for itself it will write '1' to
6766 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6767 * dmae-operations (writing to pram for example.)
6768 * note: can be done for only function 6,7 but cleaner this
6770 * b. Write zero+valid to the entire ILT.
6771 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6772 * VNIC3 (of that port). The range allocated will be the
6773 * entire ILT. This is needed to prevent ILT range error.
6774 * 2. Any PF driver load flow:
6775 * a. ILT update with the physical addresses of the allocated
6777 * b. Wait 20msec. - note that this timeout is needed to make
6778 * sure there are no requests in one of the PXP internal
6779 * queues with "old" ILT addresses.
6780 * c. PF enable in the PGLC.
6781 * d. Clear the was_error of the PF in the PGLC. (could have
6782 * occurred while driver was down)
6783 * e. PF enable in the CFC (WEAK + STRONG)
6784 * f. Timers scan enable
6785 * 3. PF driver unload flow:
6786 * a. Clear the Timers scan_en.
6787 * b. Polling for scan_on=0 for that PF.
6788 * c. Clear the PF enable bit in the PXP.
6789 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6790 * e. Write zero+valid to all ILT entries (The valid bit must
6792 * f. If this is VNIC 3 of a port then also init
6793 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6794 * to the last entry in the ILT.
6797 * Currently the PF error in the PGLC is non recoverable.
6798 * In the future the there will be a recovery routine for this error.
6799 * Currently attention is masked.
6800 * Having an MCP lock on the load/unload process does not guarantee that
6801 * there is no Timer disable during Func6/7 enable. This is because the
6802 * Timers scan is currently being cleared by the MCP on FLR.
6803 * Step 2.d can be done only for PF6/7 and the driver can also check if
6804 * there is error before clearing it. But the flow above is simpler and
6806 * All ILT entries are written by zero+valid and not just PF6/7
6807 * ILT entries since in the future the ILT entries allocation for
6808 * PF-s might be dynamic.
6810 struct ilt_client_info ilt_cli;
6811 struct bnx2x_ilt ilt;
6812 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6813 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6815 /* initialize dummy TM client */
6817 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6818 ilt_cli.client_num = ILT_CLIENT_TM;
6820 /* Step 1: set zeroes to all ilt page entries with valid bit on
6821 * Step 2: set the timers first/last ilt entry to point
6822 * to the entire range to prevent ILT range error for 3rd/4th
6823 * vnic (this code assumes existence of the vnic)
6825 * both steps performed by call to bnx2x_ilt_client_init_op()
6826 * with dummy TM client
6828 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6829 * and his brother are split registers
6831 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6832 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6833 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6835 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6836 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6837 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6840 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6841 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6843 if (!CHIP_IS_E1x(bp)) {
6844 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6845 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6846 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6848 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6850 /* let the HW do it's magic ... */
6853 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6854 } while (factor-- && (val != 1));
6857 BNX2X_ERR("ATC_INIT failed\n");
6862 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6864 bnx2x_iov_init_dmae(bp);
6866 /* clean the DMAE memory */
6868 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6870 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6872 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6874 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6876 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6878 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6879 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6880 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6881 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6883 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6885 /* QM queues pointers table */
6886 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6888 /* soft reset pulse */
6889 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6890 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6892 if (CNIC_SUPPORT(bp))
6893 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6895 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6897 if (!CHIP_REV_IS_SLOW(bp))
6898 /* enable hw interrupt from doorbell Q */
6899 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6901 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6903 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6904 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6906 if (!CHIP_IS_E1(bp))
6907 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6909 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6910 if (IS_MF_AFEX(bp)) {
6911 /* configure that VNTag and VLAN headers must be
6912 * received in afex mode
6914 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6915 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6916 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6917 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6918 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6920 /* Bit-map indicating which L2 hdrs may appear
6921 * after the basic Ethernet header
6923 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6924 bp->path_has_ovlan ? 7 : 6);
6928 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6929 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6930 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6931 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6933 if (!CHIP_IS_E1x(bp)) {
6934 /* reset VFC memories */
6935 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6936 VFC_MEMORIES_RST_REG_CAM_RST |
6937 VFC_MEMORIES_RST_REG_RAM_RST);
6938 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6939 VFC_MEMORIES_RST_REG_CAM_RST |
6940 VFC_MEMORIES_RST_REG_RAM_RST);
6945 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6946 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6947 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6948 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6951 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6953 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6956 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6957 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6958 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6960 if (!CHIP_IS_E1x(bp)) {
6961 if (IS_MF_AFEX(bp)) {
6962 /* configure that VNTag and VLAN headers must be
6965 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6966 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6967 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6968 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6969 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6971 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6972 bp->path_has_ovlan ? 7 : 6);
6976 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6978 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6980 if (CNIC_SUPPORT(bp)) {
6981 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6982 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6983 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6984 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6985 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6986 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6987 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6988 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6989 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6990 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6992 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6994 if (sizeof(union cdu_context) != 1024)
6995 /* we currently assume that a context is 1024 bytes */
6996 dev_alert(&bp->pdev->dev,
6997 "please adjust the size of cdu_context(%ld)\n",
6998 (long)sizeof(union cdu_context));
7000 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7001 val = (4 << 24) + (0 << 12) + 1024;
7002 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7004 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7005 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7006 /* enable context validation interrupt from CFC */
7007 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7009 /* set the thresholds to prevent CFC/CDU race */
7010 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7012 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7014 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7015 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7017 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7018 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7020 /* Reset PCIE errors for debug */
7021 REG_WR(bp, 0x2814, 0xffffffff);
7022 REG_WR(bp, 0x3820, 0xffffffff);
7024 if (!CHIP_IS_E1x(bp)) {
7025 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7026 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7027 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7028 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7029 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7030 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7031 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7032 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7033 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7034 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7035 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7038 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7039 if (!CHIP_IS_E1(bp)) {
7040 /* in E3 this done in per-port section */
7041 if (!CHIP_IS_E3(bp))
7042 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7044 if (CHIP_IS_E1H(bp))
7045 /* not applicable for E2 (and above ...) */
7046 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7048 if (CHIP_REV_IS_SLOW(bp))
7051 /* finish CFC init */
7052 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7054 BNX2X_ERR("CFC LL_INIT failed\n");
7057 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7059 BNX2X_ERR("CFC AC_INIT failed\n");
7062 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7064 BNX2X_ERR("CFC CAM_INIT failed\n");
7067 REG_WR(bp, CFC_REG_DEBUG0, 0);
7069 if (CHIP_IS_E1(bp)) {
7070 /* read NIG statistic
7071 to see if this is our first up since powerup */
7072 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7073 val = *bnx2x_sp(bp, wb_data[0]);
7075 /* do internal memory self test */
7076 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7077 BNX2X_ERR("internal mem self test failed\n");
7082 bnx2x_setup_fan_failure_detection(bp);
7084 /* clear PXP2 attentions */
7085 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7087 bnx2x_enable_blocks_attention(bp);
7088 bnx2x_enable_blocks_parity(bp);
7090 if (!BP_NOMCP(bp)) {
7091 if (CHIP_IS_E1x(bp))
7092 bnx2x__common_init_phy(bp);
7094 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7100 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7102 * @bp: driver handle
7104 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7106 int rc = bnx2x_init_hw_common(bp);
7111 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7113 bnx2x__common_init_phy(bp);
7118 static int bnx2x_init_hw_port(struct bnx2x *bp)
7120 int port = BP_PORT(bp);
7121 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7125 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7127 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7129 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7130 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7131 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7133 /* Timers bug workaround: disables the pf_master bit in pglue at
7134 * common phase, we need to enable it here before any dmae access are
7135 * attempted. Therefore we manually added the enable-master to the
7136 * port phase (it also happens in the function phase)
7138 if (!CHIP_IS_E1x(bp))
7139 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7141 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7142 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7143 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7144 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7146 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7147 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7148 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7149 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7151 /* QM cid (connection) count */
7152 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7154 if (CNIC_SUPPORT(bp)) {
7155 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7156 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7157 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7160 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7162 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7164 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7167 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7168 else if (bp->dev->mtu > 4096) {
7169 if (bp->flags & ONE_PORT_FLAG)
7173 /* (24*1024 + val*4)/256 */
7174 low = 96 + (val/64) +
7175 ((val % 64) ? 1 : 0);
7178 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7179 high = low + 56; /* 14*1024/256 */
7180 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7181 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7184 if (CHIP_MODE_IS_4_PORT(bp))
7185 REG_WR(bp, (BP_PORT(bp) ?
7186 BRB1_REG_MAC_GUARANTIED_1 :
7187 BRB1_REG_MAC_GUARANTIED_0), 40);
7189 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7190 if (CHIP_IS_E3B0(bp)) {
7191 if (IS_MF_AFEX(bp)) {
7192 /* configure headers for AFEX mode */
7193 REG_WR(bp, BP_PORT(bp) ?
7194 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7195 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7196 REG_WR(bp, BP_PORT(bp) ?
7197 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7198 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7199 REG_WR(bp, BP_PORT(bp) ?
7200 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7201 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7203 /* Ovlan exists only if we are in multi-function +
7204 * switch-dependent mode, in switch-independent there
7205 * is no ovlan headers
7207 REG_WR(bp, BP_PORT(bp) ?
7208 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7209 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7210 (bp->path_has_ovlan ? 7 : 6));
7214 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7215 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7216 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7217 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7219 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7220 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7221 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7222 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7224 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7225 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7227 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7229 if (CHIP_IS_E1x(bp)) {
7230 /* configure PBF to work without PAUSE mtu 9000 */
7231 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7233 /* update threshold */
7234 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7235 /* update init credit */
7236 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7239 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7241 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7244 if (CNIC_SUPPORT(bp))
7245 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7247 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7248 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7250 if (CHIP_IS_E1(bp)) {
7251 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7252 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7254 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7256 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7258 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7259 /* init aeu_mask_attn_func_0/1:
7260 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7261 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7262 * bits 4-7 are used for "per vn group attention" */
7263 val = IS_MF(bp) ? 0xF7 : 0x7;
7264 /* Enable DCBX attention for all but E1 */
7265 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7266 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7268 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7270 if (!CHIP_IS_E1x(bp)) {
7271 /* Bit-map indicating which L2 hdrs may appear after the
7272 * basic Ethernet header
7275 REG_WR(bp, BP_PORT(bp) ?
7276 NIG_REG_P1_HDRS_AFTER_BASIC :
7277 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7279 REG_WR(bp, BP_PORT(bp) ?
7280 NIG_REG_P1_HDRS_AFTER_BASIC :
7281 NIG_REG_P0_HDRS_AFTER_BASIC,
7282 IS_MF_SD(bp) ? 7 : 6);
7285 REG_WR(bp, BP_PORT(bp) ?
7286 NIG_REG_LLH1_MF_MODE :
7287 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7289 if (!CHIP_IS_E3(bp))
7290 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7292 if (!CHIP_IS_E1(bp)) {
7293 /* 0x2 disable mf_ov, 0x1 enable */
7294 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7295 (IS_MF_SD(bp) ? 0x1 : 0x2));
7297 if (!CHIP_IS_E1x(bp)) {
7299 switch (bp->mf_mode) {
7300 case MULTI_FUNCTION_SD:
7303 case MULTI_FUNCTION_SI:
7304 case MULTI_FUNCTION_AFEX:
7309 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7310 NIG_REG_LLH0_CLS_TYPE), val);
7313 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7314 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7315 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7319 /* If SPIO5 is set to generate interrupts, enable it for this port */
7320 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7321 if (val & MISC_SPIO_SPIO5) {
7322 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7323 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7324 val = REG_RD(bp, reg_addr);
7325 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7326 REG_WR(bp, reg_addr, val);
7332 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7338 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7340 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7342 wb_write[0] = ONCHIP_ADDR1(addr);
7343 wb_write[1] = ONCHIP_ADDR2(addr);
7344 REG_WR_DMAE(bp, reg, wb_write, 2);
7347 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7349 u32 data, ctl, cnt = 100;
7350 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7351 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7352 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7353 u32 sb_bit = 1 << (idu_sb_id%32);
7354 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7355 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7357 /* Not supported in BC mode */
7358 if (CHIP_INT_MODE_IS_BC(bp))
7361 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7362 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7363 IGU_REGULAR_CLEANUP_SET |
7364 IGU_REGULAR_BCLEANUP;
7366 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7367 func_encode << IGU_CTRL_REG_FID_SHIFT |
7368 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7370 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7371 data, igu_addr_data);
7372 REG_WR(bp, igu_addr_data, data);
7375 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7377 REG_WR(bp, igu_addr_ctl, ctl);
7381 /* wait for clean up to finish */
7382 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7385 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7387 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7388 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7392 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7394 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7397 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7399 u32 i, base = FUNC_ILT_BASE(func);
7400 for (i = base; i < base + ILT_PER_FUNC; i++)
7401 bnx2x_ilt_wr(bp, i, 0);
7404 static void bnx2x_init_searcher(struct bnx2x *bp)
7406 int port = BP_PORT(bp);
7407 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7408 /* T1 hash bits value determines the T1 number of entries */
7409 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7412 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7415 struct bnx2x_func_state_params func_params = {NULL};
7416 struct bnx2x_func_switch_update_params *switch_update_params =
7417 &func_params.params.switch_update;
7419 /* Prepare parameters for function state transitions */
7420 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7421 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7423 func_params.f_obj = &bp->func_obj;
7424 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7426 /* Function parameters */
7427 switch_update_params->suspend = suspend;
7429 rc = bnx2x_func_state_change(bp, &func_params);
7434 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7436 int rc, i, port = BP_PORT(bp);
7437 int vlan_en = 0, mac_en[NUM_MACS];
7439 /* Close input from network */
7440 if (bp->mf_mode == SINGLE_FUNCTION) {
7441 bnx2x_set_rx_filter(&bp->link_params, 0);
7443 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7444 NIG_REG_LLH0_FUNC_EN);
7445 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7446 NIG_REG_LLH0_FUNC_EN, 0);
7447 for (i = 0; i < NUM_MACS; i++) {
7448 mac_en[i] = REG_RD(bp, port ?
7449 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7451 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7453 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7455 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7459 /* Close BMC to host */
7460 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7461 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7463 /* Suspend Tx switching to the PF. Completion of this ramrod
7464 * further guarantees that all the packets of that PF / child
7465 * VFs in BRB were processed by the Parser, so it is safe to
7466 * change the NIC_MODE register.
7468 rc = bnx2x_func_switch_update(bp, 1);
7470 BNX2X_ERR("Can't suspend tx-switching!\n");
7474 /* Change NIC_MODE register */
7475 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7477 /* Open input from network */
7478 if (bp->mf_mode == SINGLE_FUNCTION) {
7479 bnx2x_set_rx_filter(&bp->link_params, 1);
7481 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7482 NIG_REG_LLH0_FUNC_EN, vlan_en);
7483 for (i = 0; i < NUM_MACS; i++) {
7484 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7486 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7491 /* Enable BMC to host */
7492 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7493 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7495 /* Resume Tx switching to the PF */
7496 rc = bnx2x_func_switch_update(bp, 0);
7498 BNX2X_ERR("Can't resume tx-switching!\n");
7502 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7506 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7510 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7512 if (CONFIGURE_NIC_MODE(bp)) {
7513 /* Configure searcher as part of function hw init */
7514 bnx2x_init_searcher(bp);
7516 /* Reset NIC mode */
7517 rc = bnx2x_reset_nic_mode(bp);
7519 BNX2X_ERR("Can't change NIC mode!\n");
7526 static int bnx2x_init_hw_func(struct bnx2x *bp)
7528 int port = BP_PORT(bp);
7529 int func = BP_FUNC(bp);
7530 int init_phase = PHASE_PF0 + func;
7531 struct bnx2x_ilt *ilt = BP_ILT(bp);
7534 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7535 int i, main_mem_width, rc;
7537 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7539 /* FLR cleanup - hmmm */
7540 if (!CHIP_IS_E1x(bp)) {
7541 rc = bnx2x_pf_flr_clnup(bp);
7548 /* set MSI reconfigure capability */
7549 if (bp->common.int_block == INT_BLOCK_HC) {
7550 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7551 val = REG_RD(bp, addr);
7552 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7553 REG_WR(bp, addr, val);
7556 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7557 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7560 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7563 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7564 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7566 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7567 * those of the VFs, so start line should be reset
7569 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7570 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7571 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7572 ilt->lines[cdu_ilt_start + i].page_mapping =
7573 bp->context[i].cxt_mapping;
7574 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7577 bnx2x_ilt_init_op(bp, INITOP_SET);
7579 if (!CONFIGURE_NIC_MODE(bp)) {
7580 bnx2x_init_searcher(bp);
7581 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7582 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7585 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7586 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7589 if (!CHIP_IS_E1x(bp)) {
7590 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7592 /* Turn on a single ISR mode in IGU if driver is going to use
7595 if (!(bp->flags & USING_MSIX_FLAG))
7596 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7598 * Timers workaround bug: function init part.
7599 * Need to wait 20msec after initializing ILT,
7600 * needed to make sure there are no requests in
7601 * one of the PXP internal queues with "old" ILT addresses
7605 * Master enable - Due to WB DMAE writes performed before this
7606 * register is re-initialized as part of the regular function
7609 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7610 /* Enable the function in IGU */
7611 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7616 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7618 if (!CHIP_IS_E1x(bp))
7619 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7621 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7622 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7623 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7624 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7625 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7626 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7627 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7628 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7629 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7630 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7631 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7632 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7633 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7635 if (!CHIP_IS_E1x(bp))
7636 REG_WR(bp, QM_REG_PF_EN, 1);
7638 if (!CHIP_IS_E1x(bp)) {
7639 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7640 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7641 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7642 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7644 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7646 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7647 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7649 bnx2x_iov_init_dq(bp);
7651 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7652 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7653 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7654 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7655 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7656 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7657 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7658 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7659 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7660 if (!CHIP_IS_E1x(bp))
7661 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7663 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7665 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7667 if (!CHIP_IS_E1x(bp))
7668 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7671 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7672 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7675 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7677 /* HC init per function */
7678 if (bp->common.int_block == INT_BLOCK_HC) {
7679 if (CHIP_IS_E1H(bp)) {
7680 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7682 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7683 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7685 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7688 int num_segs, sb_idx, prod_offset;
7690 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7692 if (!CHIP_IS_E1x(bp)) {
7693 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7694 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7697 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7699 if (!CHIP_IS_E1x(bp)) {
7703 * E2 mode: address 0-135 match to the mapping memory;
7704 * 136 - PF0 default prod; 137 - PF1 default prod;
7705 * 138 - PF2 default prod; 139 - PF3 default prod;
7706 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7707 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7710 * E1.5 mode - In backward compatible mode;
7711 * for non default SB; each even line in the memory
7712 * holds the U producer and each odd line hold
7713 * the C producer. The first 128 producers are for
7714 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7715 * producers are for the DSB for each PF.
7716 * Each PF has five segments: (the order inside each
7717 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7718 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7719 * 144-147 attn prods;
7721 /* non-default-status-blocks */
7722 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7723 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7724 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7725 prod_offset = (bp->igu_base_sb + sb_idx) *
7728 for (i = 0; i < num_segs; i++) {
7729 addr = IGU_REG_PROD_CONS_MEMORY +
7730 (prod_offset + i) * 4;
7731 REG_WR(bp, addr, 0);
7733 /* send consumer update with value 0 */
7734 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7735 USTORM_ID, 0, IGU_INT_NOP, 1);
7736 bnx2x_igu_clear_sb(bp,
7737 bp->igu_base_sb + sb_idx);
7740 /* default-status-blocks */
7741 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7742 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7744 if (CHIP_MODE_IS_4_PORT(bp))
7745 dsb_idx = BP_FUNC(bp);
7747 dsb_idx = BP_VN(bp);
7749 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7750 IGU_BC_BASE_DSB_PROD + dsb_idx :
7751 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7754 * igu prods come in chunks of E1HVN_MAX (4) -
7755 * does not matters what is the current chip mode
7757 for (i = 0; i < (num_segs * E1HVN_MAX);
7759 addr = IGU_REG_PROD_CONS_MEMORY +
7760 (prod_offset + i)*4;
7761 REG_WR(bp, addr, 0);
7763 /* send consumer update with 0 */
7764 if (CHIP_INT_MODE_IS_BC(bp)) {
7765 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7766 USTORM_ID, 0, IGU_INT_NOP, 1);
7767 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7768 CSTORM_ID, 0, IGU_INT_NOP, 1);
7769 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7770 XSTORM_ID, 0, IGU_INT_NOP, 1);
7771 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7772 TSTORM_ID, 0, IGU_INT_NOP, 1);
7773 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7774 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7776 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7777 USTORM_ID, 0, IGU_INT_NOP, 1);
7778 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7779 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7781 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7783 /* !!! These should become driver const once
7784 rf-tool supports split-68 const */
7785 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7786 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7787 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7788 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7789 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7790 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7794 /* Reset PCIE errors for debug */
7795 REG_WR(bp, 0x2114, 0xffffffff);
7796 REG_WR(bp, 0x2120, 0xffffffff);
7798 if (CHIP_IS_E1x(bp)) {
7799 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7800 main_mem_base = HC_REG_MAIN_MEMORY +
7801 BP_PORT(bp) * (main_mem_size * 4);
7802 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7805 val = REG_RD(bp, main_mem_prty_clr);
7808 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7811 /* Clear "false" parity errors in MSI-X table */
7812 for (i = main_mem_base;
7813 i < main_mem_base + main_mem_size * 4;
7814 i += main_mem_width) {
7815 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7816 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7817 i, main_mem_width / 4);
7819 /* Clear HC parity attention */
7820 REG_RD(bp, main_mem_prty_clr);
7823 #ifdef BNX2X_STOP_ON_ERROR
7824 /* Enable STORMs SP logging */
7825 REG_WR8(bp, BAR_USTRORM_INTMEM +
7826 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7827 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7828 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7829 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7830 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7831 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7832 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7835 bnx2x_phy_probe(&bp->link_params);
7840 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7842 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7844 if (!CHIP_IS_E1x(bp))
7845 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7846 sizeof(struct host_hc_status_block_e2));
7848 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7849 sizeof(struct host_hc_status_block_e1x));
7851 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7854 void bnx2x_free_mem(struct bnx2x *bp)
7858 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7859 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7864 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7865 sizeof(struct host_sp_status_block));
7867 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7868 sizeof(struct bnx2x_slowpath));
7870 for (i = 0; i < L2_ILT_LINES(bp); i++)
7871 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7872 bp->context[i].size);
7873 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7875 BNX2X_FREE(bp->ilt->lines);
7877 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7879 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7880 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7882 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7884 bnx2x_iov_free_mem(bp);
7887 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7889 if (!CHIP_IS_E1x(bp))
7890 /* size = the status block + ramrod buffers */
7891 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7892 sizeof(struct host_hc_status_block_e2));
7894 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7895 &bp->cnic_sb_mapping,
7897 host_hc_status_block_e1x));
7899 if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7900 /* allocate searcher T2 table, as it wasn't allocated before */
7901 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7903 /* write address to which L5 should insert its values */
7904 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7905 &bp->slowpath->drv_info_to_mcp;
7907 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7913 bnx2x_free_mem_cnic(bp);
7914 BNX2X_ERR("Can't allocate memory\n");
7918 int bnx2x_alloc_mem(struct bnx2x *bp)
7920 int i, allocated, context_size;
7922 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7923 /* allocate searcher T2 table */
7924 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7926 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7927 sizeof(struct host_sp_status_block));
7929 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7930 sizeof(struct bnx2x_slowpath));
7932 /* Allocate memory for CDU context:
7933 * This memory is allocated separately and not in the generic ILT
7934 * functions because CDU differs in few aspects:
7935 * 1. There are multiple entities allocating memory for context -
7936 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7937 * its own ILT lines.
7938 * 2. Since CDU page-size is not a single 4KB page (which is the case
7939 * for the other ILT clients), to be efficient we want to support
7940 * allocation of sub-page-size in the last entry.
7941 * 3. Context pointers are used by the driver to pass to FW / update
7942 * the context (for the other ILT clients the pointers are used just to
7943 * free the memory during unload).
7945 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7947 for (i = 0, allocated = 0; allocated < context_size; i++) {
7948 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7949 (context_size - allocated));
7950 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7951 &bp->context[i].cxt_mapping,
7952 bp->context[i].size);
7953 allocated += bp->context[i].size;
7955 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7957 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7960 if (bnx2x_iov_alloc_mem(bp))
7963 /* Slow path ring */
7964 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7967 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7968 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7974 BNX2X_ERR("Can't allocate memory\n");
7979 * Init service functions
7982 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7983 struct bnx2x_vlan_mac_obj *obj, bool set,
7984 int mac_type, unsigned long *ramrod_flags)
7987 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7989 memset(&ramrod_param, 0, sizeof(ramrod_param));
7991 /* Fill general parameters */
7992 ramrod_param.vlan_mac_obj = obj;
7993 ramrod_param.ramrod_flags = *ramrod_flags;
7995 /* Fill a user request section if needed */
7996 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7997 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7999 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8001 /* Set the command: ADD or DEL */
8003 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8005 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8008 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8010 if (rc == -EEXIST) {
8011 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8012 /* do not treat adding same MAC as error */
8015 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8020 int bnx2x_del_all_macs(struct bnx2x *bp,
8021 struct bnx2x_vlan_mac_obj *mac_obj,
8022 int mac_type, bool wait_for_comp)
8025 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8027 /* Wait for completion of requested */
8029 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8031 /* Set the mac type of addresses we want to clear */
8032 __set_bit(mac_type, &vlan_mac_flags);
8034 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8036 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8041 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8043 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8044 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8045 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8046 "Ignoring Zero MAC for STORAGE SD mode\n");
8051 unsigned long ramrod_flags = 0;
8053 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8054 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8055 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8056 &bp->sp_objs->mac_obj, set,
8057 BNX2X_ETH_MAC, &ramrod_flags);
8059 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8060 bp->fp->index, true);
8064 int bnx2x_setup_leading(struct bnx2x *bp)
8067 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8069 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8073 * bnx2x_set_int_mode - configure interrupt mode
8075 * @bp: driver handle
8077 * In case of MSI-X it will also try to enable MSI-X.
8079 int bnx2x_set_int_mode(struct bnx2x *bp)
8083 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8084 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8089 case BNX2X_INT_MODE_MSIX:
8090 /* attempt to enable msix */
8091 rc = bnx2x_enable_msix(bp);
8097 /* vfs use only msix */
8098 if (rc && IS_VF(bp))
8101 /* failed to enable multiple MSI-X */
8102 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8104 1 + bp->num_cnic_queues);
8106 /* falling through... */
8107 case BNX2X_INT_MODE_MSI:
8108 bnx2x_enable_msi(bp);
8110 /* falling through... */
8111 case BNX2X_INT_MODE_INTX:
8112 bp->num_ethernet_queues = 1;
8113 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8114 BNX2X_DEV_INFO("set number of queues to 1\n");
8117 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8123 /* must be called prior to any HW initializations */
8124 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8127 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8128 return L2_ILT_LINES(bp);
8131 void bnx2x_ilt_set_info(struct bnx2x *bp)
8133 struct ilt_client_info *ilt_client;
8134 struct bnx2x_ilt *ilt = BP_ILT(bp);
8137 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8138 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8141 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8142 ilt_client->client_num = ILT_CLIENT_CDU;
8143 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8144 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8145 ilt_client->start = line;
8146 line += bnx2x_cid_ilt_lines(bp);
8148 if (CNIC_SUPPORT(bp))
8149 line += CNIC_ILT_LINES;
8150 ilt_client->end = line - 1;
8152 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8155 ilt_client->page_size,
8157 ilog2(ilt_client->page_size >> 12));
8160 if (QM_INIT(bp->qm_cid_count)) {
8161 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8162 ilt_client->client_num = ILT_CLIENT_QM;
8163 ilt_client->page_size = QM_ILT_PAGE_SZ;
8164 ilt_client->flags = 0;
8165 ilt_client->start = line;
8167 /* 4 bytes for each cid */
8168 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8171 ilt_client->end = line - 1;
8174 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8177 ilt_client->page_size,
8179 ilog2(ilt_client->page_size >> 12));
8182 if (CNIC_SUPPORT(bp)) {
8184 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8185 ilt_client->client_num = ILT_CLIENT_SRC;
8186 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8187 ilt_client->flags = 0;
8188 ilt_client->start = line;
8189 line += SRC_ILT_LINES;
8190 ilt_client->end = line - 1;
8193 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8196 ilt_client->page_size,
8198 ilog2(ilt_client->page_size >> 12));
8201 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8202 ilt_client->client_num = ILT_CLIENT_TM;
8203 ilt_client->page_size = TM_ILT_PAGE_SZ;
8204 ilt_client->flags = 0;
8205 ilt_client->start = line;
8206 line += TM_ILT_LINES;
8207 ilt_client->end = line - 1;
8210 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8213 ilt_client->page_size,
8215 ilog2(ilt_client->page_size >> 12));
8218 BUG_ON(line > ILT_MAX_LINES);
8222 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8224 * @bp: driver handle
8225 * @fp: pointer to fastpath
8226 * @init_params: pointer to parameters structure
8228 * parameters configured:
8229 * - HC configuration
8230 * - Queue's CDU context
8232 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8233 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8236 int cxt_index, cxt_offset;
8238 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8239 if (!IS_FCOE_FP(fp)) {
8240 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8241 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8243 /* If HC is supported, enable host coalescing in the transition
8246 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8247 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8250 init_params->rx.hc_rate = bp->rx_ticks ?
8251 (1000000 / bp->rx_ticks) : 0;
8252 init_params->tx.hc_rate = bp->tx_ticks ?
8253 (1000000 / bp->tx_ticks) : 0;
8256 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8260 * CQ index among the SB indices: FCoE clients uses the default
8261 * SB, therefore it's different.
8263 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8264 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8267 /* set maximum number of COSs supported by this queue */
8268 init_params->max_cos = fp->max_cos;
8270 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8271 fp->index, init_params->max_cos);
8273 /* set the context pointers queue object */
8274 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8275 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8276 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8278 init_params->cxts[cos] =
8279 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8283 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8284 struct bnx2x_queue_state_params *q_params,
8285 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8286 int tx_index, bool leading)
8288 memset(tx_only_params, 0, sizeof(*tx_only_params));
8290 /* Set the command */
8291 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8293 /* Set tx-only QUEUE flags: don't zero statistics */
8294 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8296 /* choose the index of the cid to send the slow path on */
8297 tx_only_params->cid_index = tx_index;
8299 /* Set general TX_ONLY_SETUP parameters */
8300 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8302 /* Set Tx TX_ONLY_SETUP parameters */
8303 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8306 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8307 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8308 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8309 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8311 /* send the ramrod */
8312 return bnx2x_queue_state_change(bp, q_params);
8316 * bnx2x_setup_queue - setup queue
8318 * @bp: driver handle
8319 * @fp: pointer to fastpath
8320 * @leading: is leading
8322 * This function performs 2 steps in a Queue state machine
8323 * actually: 1) RESET->INIT 2) INIT->SETUP
8326 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8329 struct bnx2x_queue_state_params q_params = {NULL};
8330 struct bnx2x_queue_setup_params *setup_params =
8331 &q_params.params.setup;
8332 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8333 &q_params.params.tx_only;
8337 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8339 /* reset IGU state skip FCoE L2 queue */
8340 if (!IS_FCOE_FP(fp))
8341 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8344 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8345 /* We want to wait for completion in this context */
8346 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8348 /* Prepare the INIT parameters */
8349 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8351 /* Set the command */
8352 q_params.cmd = BNX2X_Q_CMD_INIT;
8354 /* Change the state to INIT */
8355 rc = bnx2x_queue_state_change(bp, &q_params);
8357 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8361 DP(NETIF_MSG_IFUP, "init complete\n");
8363 /* Now move the Queue to the SETUP state... */
8364 memset(setup_params, 0, sizeof(*setup_params));
8366 /* Set QUEUE flags */
8367 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8369 /* Set general SETUP parameters */
8370 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8371 FIRST_TX_COS_INDEX);
8373 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8374 &setup_params->rxq_params);
8376 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8377 FIRST_TX_COS_INDEX);
8379 /* Set the command */
8380 q_params.cmd = BNX2X_Q_CMD_SETUP;
8383 bp->fcoe_init = true;
8385 /* Change the state to SETUP */
8386 rc = bnx2x_queue_state_change(bp, &q_params);
8388 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8392 /* loop through the relevant tx-only indices */
8393 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8394 tx_index < fp->max_cos;
8397 /* prepare and send tx-only ramrod*/
8398 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8399 tx_only_params, tx_index, leading);
8401 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8402 fp->index, tx_index);
8410 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8412 struct bnx2x_fastpath *fp = &bp->fp[index];
8413 struct bnx2x_fp_txdata *txdata;
8414 struct bnx2x_queue_state_params q_params = {NULL};
8417 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8419 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8420 /* We want to wait for completion in this context */
8421 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8423 /* close tx-only connections */
8424 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8425 tx_index < fp->max_cos;
8428 /* ascertain this is a normal queue*/
8429 txdata = fp->txdata_ptr[tx_index];
8431 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8434 /* send halt terminate on tx-only connection */
8435 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8436 memset(&q_params.params.terminate, 0,
8437 sizeof(q_params.params.terminate));
8438 q_params.params.terminate.cid_index = tx_index;
8440 rc = bnx2x_queue_state_change(bp, &q_params);
8444 /* send halt terminate on tx-only connection */
8445 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8446 memset(&q_params.params.cfc_del, 0,
8447 sizeof(q_params.params.cfc_del));
8448 q_params.params.cfc_del.cid_index = tx_index;
8449 rc = bnx2x_queue_state_change(bp, &q_params);
8453 /* Stop the primary connection: */
8454 /* ...halt the connection */
8455 q_params.cmd = BNX2X_Q_CMD_HALT;
8456 rc = bnx2x_queue_state_change(bp, &q_params);
8460 /* ...terminate the connection */
8461 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8462 memset(&q_params.params.terminate, 0,
8463 sizeof(q_params.params.terminate));
8464 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8465 rc = bnx2x_queue_state_change(bp, &q_params);
8468 /* ...delete cfc entry */
8469 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8470 memset(&q_params.params.cfc_del, 0,
8471 sizeof(q_params.params.cfc_del));
8472 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8473 return bnx2x_queue_state_change(bp, &q_params);
8476 static void bnx2x_reset_func(struct bnx2x *bp)
8478 int port = BP_PORT(bp);
8479 int func = BP_FUNC(bp);
8482 /* Disable the function in the FW */
8483 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8484 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8485 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8486 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8489 for_each_eth_queue(bp, i) {
8490 struct bnx2x_fastpath *fp = &bp->fp[i];
8491 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8492 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8496 if (CNIC_LOADED(bp))
8498 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8499 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8500 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8503 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8504 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8507 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8508 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8512 if (bp->common.int_block == INT_BLOCK_HC) {
8513 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8514 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8516 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8517 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8520 if (CNIC_LOADED(bp)) {
8521 /* Disable Timer scan */
8522 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8524 * Wait for at least 10ms and up to 2 second for the timers
8527 for (i = 0; i < 200; i++) {
8528 usleep_range(10000, 20000);
8529 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8534 bnx2x_clear_func_ilt(bp, func);
8536 /* Timers workaround bug for E2: if this is vnic-3,
8537 * we need to set the entire ilt range for this timers.
8539 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8540 struct ilt_client_info ilt_cli;
8541 /* use dummy TM client */
8542 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8544 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8545 ilt_cli.client_num = ILT_CLIENT_TM;
8547 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8550 /* this assumes that reset_port() called before reset_func()*/
8551 if (!CHIP_IS_E1x(bp))
8552 bnx2x_pf_disable(bp);
8557 static void bnx2x_reset_port(struct bnx2x *bp)
8559 int port = BP_PORT(bp);
8562 /* Reset physical Link */
8563 bnx2x__link_reset(bp);
8565 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8567 /* Do not rcv packets to BRB */
8568 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8569 /* Do not direct rcv packets that are not for MCP to the BRB */
8570 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8571 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8574 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8577 /* Check for BRB port occupancy */
8578 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8580 DP(NETIF_MSG_IFDOWN,
8581 "BRB1 is not empty %d blocks are occupied\n", val);
8583 /* TODO: Close Doorbell port? */
8586 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8588 struct bnx2x_func_state_params func_params = {NULL};
8590 /* Prepare parameters for function state transitions */
8591 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8593 func_params.f_obj = &bp->func_obj;
8594 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8596 func_params.params.hw_init.load_phase = load_code;
8598 return bnx2x_func_state_change(bp, &func_params);
8601 static int bnx2x_func_stop(struct bnx2x *bp)
8603 struct bnx2x_func_state_params func_params = {NULL};
8606 /* Prepare parameters for function state transitions */
8607 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8608 func_params.f_obj = &bp->func_obj;
8609 func_params.cmd = BNX2X_F_CMD_STOP;
8612 * Try to stop the function the 'good way'. If fails (in case
8613 * of a parity error during bnx2x_chip_cleanup()) and we are
8614 * not in a debug mode, perform a state transaction in order to
8615 * enable further HW_RESET transaction.
8617 rc = bnx2x_func_state_change(bp, &func_params);
8619 #ifdef BNX2X_STOP_ON_ERROR
8622 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8623 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8624 return bnx2x_func_state_change(bp, &func_params);
8632 * bnx2x_send_unload_req - request unload mode from the MCP.
8634 * @bp: driver handle
8635 * @unload_mode: requested function's unload mode
8637 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8639 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8642 int port = BP_PORT(bp);
8644 /* Select the UNLOAD request mode */
8645 if (unload_mode == UNLOAD_NORMAL)
8646 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8648 else if (bp->flags & NO_WOL_FLAG)
8649 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8652 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8653 u8 *mac_addr = bp->dev->dev_addr;
8657 /* The mac address is written to entries 1-4 to
8658 * preserve entry 0 which is used by the PMF
8660 u8 entry = (BP_VN(bp) + 1)*8;
8662 val = (mac_addr[0] << 8) | mac_addr[1];
8663 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8665 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8666 (mac_addr[4] << 8) | mac_addr[5];
8667 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8669 /* Enable the PME and clear the status */
8670 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8671 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8672 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8674 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8677 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8679 /* Send the request to the MCP */
8681 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8683 int path = BP_PATH(bp);
8685 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8686 path, load_count[path][0], load_count[path][1],
8687 load_count[path][2]);
8688 load_count[path][0]--;
8689 load_count[path][1 + port]--;
8690 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8691 path, load_count[path][0], load_count[path][1],
8692 load_count[path][2]);
8693 if (load_count[path][0] == 0)
8694 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8695 else if (load_count[path][1 + port] == 0)
8696 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8698 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8705 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8707 * @bp: driver handle
8708 * @keep_link: true iff link should be kept up
8710 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8712 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8714 /* Report UNLOAD_DONE to MCP */
8716 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8719 static int bnx2x_func_wait_started(struct bnx2x *bp)
8722 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8728 * (assumption: No Attention from MCP at this stage)
8729 * PMF probably in the middle of TX disable/enable transaction
8730 * 1. Sync IRS for default SB
8731 * 2. Sync SP queue - this guarantees us that attention handling started
8732 * 3. Wait, that TX disable/enable transaction completes
8734 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8735 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8736 * received completion for the transaction the state is TX_STOPPED.
8737 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8741 /* make sure default SB ISR is done */
8743 synchronize_irq(bp->msix_table[0].vector);
8745 synchronize_irq(bp->pdev->irq);
8747 flush_workqueue(bnx2x_wq);
8749 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8750 BNX2X_F_STATE_STARTED && tout--)
8753 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8754 BNX2X_F_STATE_STARTED) {
8755 #ifdef BNX2X_STOP_ON_ERROR
8756 BNX2X_ERR("Wrong function state\n");
8760 * Failed to complete the transaction in a "good way"
8761 * Force both transactions with CLR bit
8763 struct bnx2x_func_state_params func_params = {NULL};
8765 DP(NETIF_MSG_IFDOWN,
8766 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8768 func_params.f_obj = &bp->func_obj;
8769 __set_bit(RAMROD_DRV_CLR_ONLY,
8770 &func_params.ramrod_flags);
8772 /* STARTED-->TX_ST0PPED */
8773 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8774 bnx2x_func_state_change(bp, &func_params);
8776 /* TX_ST0PPED-->STARTED */
8777 func_params.cmd = BNX2X_F_CMD_TX_START;
8778 return bnx2x_func_state_change(bp, &func_params);
8785 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8787 int port = BP_PORT(bp);
8790 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8793 /* Wait until tx fastpath tasks complete */
8794 for_each_tx_queue(bp, i) {
8795 struct bnx2x_fastpath *fp = &bp->fp[i];
8797 for_each_cos_in_tx_queue(fp, cos)
8798 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8799 #ifdef BNX2X_STOP_ON_ERROR
8805 /* Give HW time to discard old tx messages */
8806 usleep_range(1000, 2000);
8808 /* Clean all ETH MACs */
8809 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8812 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8814 /* Clean up UC list */
8815 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8818 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8822 if (!CHIP_IS_E1(bp))
8823 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8825 /* Set "drop all" (stop Rx).
8826 * We need to take a netif_addr_lock() here in order to prevent
8827 * a race between the completion code and this code.
8829 netif_addr_lock_bh(bp->dev);
8830 /* Schedule the rx_mode command */
8831 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8832 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8834 bnx2x_set_storm_rx_mode(bp);
8836 /* Cleanup multicast configuration */
8837 rparam.mcast_obj = &bp->mcast_obj;
8838 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8840 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8842 netif_addr_unlock_bh(bp->dev);
8844 bnx2x_iov_chip_cleanup(bp);
8847 * Send the UNLOAD_REQUEST to the MCP. This will return if
8848 * this function should perform FUNC, PORT or COMMON HW
8851 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8854 * (assumption: No Attention from MCP at this stage)
8855 * PMF probably in the middle of TX disable/enable transaction
8857 rc = bnx2x_func_wait_started(bp);
8859 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8860 #ifdef BNX2X_STOP_ON_ERROR
8865 /* Close multi and leading connections
8866 * Completions for ramrods are collected in a synchronous way
8868 for_each_eth_queue(bp, i)
8869 if (bnx2x_stop_queue(bp, i))
8870 #ifdef BNX2X_STOP_ON_ERROR
8876 if (CNIC_LOADED(bp)) {
8877 for_each_cnic_queue(bp, i)
8878 if (bnx2x_stop_queue(bp, i))
8879 #ifdef BNX2X_STOP_ON_ERROR
8886 /* If SP settings didn't get completed so far - something
8887 * very wrong has happen.
8889 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8890 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8892 #ifndef BNX2X_STOP_ON_ERROR
8895 rc = bnx2x_func_stop(bp);
8897 BNX2X_ERR("Function stop failed!\n");
8898 #ifdef BNX2X_STOP_ON_ERROR
8903 /* Disable HW interrupts, NAPI */
8904 bnx2x_netif_stop(bp, 1);
8905 /* Delete all NAPI objects */
8906 bnx2x_del_all_napi(bp);
8907 if (CNIC_LOADED(bp))
8908 bnx2x_del_all_napi_cnic(bp);
8913 /* Reset the chip */
8914 rc = bnx2x_reset_hw(bp, reset_code);
8916 BNX2X_ERR("HW_RESET failed\n");
8918 /* Report UNLOAD_DONE to MCP */
8919 bnx2x_send_unload_done(bp, keep_link);
8922 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8926 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8928 if (CHIP_IS_E1(bp)) {
8929 int port = BP_PORT(bp);
8930 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8931 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8933 val = REG_RD(bp, addr);
8935 REG_WR(bp, addr, val);
8937 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8938 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8939 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8940 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8944 /* Close gates #2, #3 and #4: */
8945 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8949 /* Gates #2 and #4a are closed/opened for "not E1" only */
8950 if (!CHIP_IS_E1(bp)) {
8952 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8954 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8958 if (CHIP_IS_E1x(bp)) {
8959 /* Prevent interrupts from HC on both ports */
8960 val = REG_RD(bp, HC_REG_CONFIG_1);
8961 REG_WR(bp, HC_REG_CONFIG_1,
8962 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8963 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8965 val = REG_RD(bp, HC_REG_CONFIG_0);
8966 REG_WR(bp, HC_REG_CONFIG_0,
8967 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8968 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8970 /* Prevent incoming interrupts in IGU */
8971 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8973 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8975 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8976 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8979 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8980 close ? "closing" : "opening");
8984 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8986 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8988 /* Do some magic... */
8989 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8990 *magic_val = val & SHARED_MF_CLP_MAGIC;
8991 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8995 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8997 * @bp: driver handle
8998 * @magic_val: old value of the `magic' bit.
9000 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9002 /* Restore the `magic' bit value... */
9003 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9004 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9005 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9009 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9011 * @bp: driver handle
9012 * @magic_val: old value of 'magic' bit.
9014 * Takes care of CLP configurations.
9016 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9019 u32 validity_offset;
9021 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9023 /* Set `magic' bit in order to save MF config */
9024 if (!CHIP_IS_E1(bp))
9025 bnx2x_clp_reset_prep(bp, magic_val);
9027 /* Get shmem offset */
9028 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9030 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9032 /* Clear validity map flags */
9034 REG_WR(bp, shmem + validity_offset, 0);
9037 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9038 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9041 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9043 * @bp: driver handle
9045 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9047 /* special handling for emulation and FPGA,
9048 wait 10 times longer */
9049 if (CHIP_REV_IS_SLOW(bp))
9050 msleep(MCP_ONE_TIMEOUT*10);
9052 msleep(MCP_ONE_TIMEOUT);
9056 * initializes bp->common.shmem_base and waits for validity signature to appear
9058 static int bnx2x_init_shmem(struct bnx2x *bp)
9064 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9065 if (bp->common.shmem_base) {
9066 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9067 if (val & SHR_MEM_VALIDITY_MB)
9071 bnx2x_mcp_wait_one(bp);
9073 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9075 BNX2X_ERR("BAD MCP validity signature\n");
9080 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9082 int rc = bnx2x_init_shmem(bp);
9084 /* Restore the `magic' bit value */
9085 if (!CHIP_IS_E1(bp))
9086 bnx2x_clp_reset_done(bp, magic_val);
9091 static void bnx2x_pxp_prep(struct bnx2x *bp)
9093 if (!CHIP_IS_E1(bp)) {
9094 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9095 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9101 * Reset the whole chip except for:
9103 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9106 * - MISC (including AEU)
9110 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9112 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9113 u32 global_bits2, stay_reset2;
9116 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9117 * (per chip) blocks.
9120 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9121 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9123 /* Don't reset the following blocks.
9124 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9125 * reset, as in 4 port device they might still be owned
9126 * by the MCP (there is only one leader per path).
9129 MISC_REGISTERS_RESET_REG_1_RST_HC |
9130 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9131 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9134 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9135 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9136 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9137 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9138 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9139 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9140 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9141 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9142 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9143 MISC_REGISTERS_RESET_REG_2_PGLC |
9144 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9145 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9146 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9147 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9148 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9149 MISC_REGISTERS_RESET_REG_2_UMAC1;
9152 * Keep the following blocks in reset:
9153 * - all xxMACs are handled by the bnx2x_link code.
9156 MISC_REGISTERS_RESET_REG_2_XMAC |
9157 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9159 /* Full reset masks according to the chip */
9160 reset_mask1 = 0xffffffff;
9163 reset_mask2 = 0xffff;
9164 else if (CHIP_IS_E1H(bp))
9165 reset_mask2 = 0x1ffff;
9166 else if (CHIP_IS_E2(bp))
9167 reset_mask2 = 0xfffff;
9168 else /* CHIP_IS_E3 */
9169 reset_mask2 = 0x3ffffff;
9171 /* Don't reset global blocks unless we need to */
9173 reset_mask2 &= ~global_bits2;
9176 * In case of attention in the QM, we need to reset PXP
9177 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9178 * because otherwise QM reset would release 'close the gates' shortly
9179 * before resetting the PXP, then the PSWRQ would send a write
9180 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9181 * read the payload data from PSWWR, but PSWWR would not
9182 * respond. The write queue in PGLUE would stuck, dmae commands
9183 * would not return. Therefore it's important to reset the second
9184 * reset register (containing the
9185 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9186 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9189 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9190 reset_mask2 & (~not_reset_mask2));
9192 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9193 reset_mask1 & (~not_reset_mask1));
9198 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9199 reset_mask2 & (~stay_reset2));
9204 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9209 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9210 * It should get cleared in no more than 1s.
9212 * @bp: driver handle
9214 * It should get cleared in no more than 1s. Returns 0 if
9215 * pending writes bit gets cleared.
9217 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9223 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9228 usleep_range(1000, 2000);
9229 } while (cnt-- > 0);
9232 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9240 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9244 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9247 /* Empty the Tetris buffer, wait for 1s */
9249 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9250 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9251 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9252 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9253 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9255 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9257 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9258 ((port_is_idle_0 & 0x1) == 0x1) &&
9259 ((port_is_idle_1 & 0x1) == 0x1) &&
9260 (pgl_exp_rom2 == 0xffffffff) &&
9261 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9263 usleep_range(1000, 2000);
9264 } while (cnt-- > 0);
9267 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9268 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9269 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9276 /* Close gates #2, #3 and #4 */
9277 bnx2x_set_234_gates(bp, true);
9279 /* Poll for IGU VQs for 57712 and newer chips */
9280 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9283 /* TBD: Indicate that "process kill" is in progress to MCP */
9285 /* Clear "unprepared" bit */
9286 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9289 /* Make sure all is written to the chip before the reset */
9292 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9293 * PSWHST, GRC and PSWRD Tetris buffer.
9295 usleep_range(1000, 2000);
9297 /* Prepare to chip reset: */
9300 bnx2x_reset_mcp_prep(bp, &val);
9306 /* reset the chip */
9307 bnx2x_process_kill_chip_reset(bp, global);
9310 /* Recover after reset: */
9312 if (global && bnx2x_reset_mcp_comp(bp, val))
9315 /* TBD: Add resetting the NO_MCP mode DB here */
9317 /* Open the gates #2, #3 and #4 */
9318 bnx2x_set_234_gates(bp, false);
9320 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9321 * reset state, re-enable attentions. */
9326 static int bnx2x_leader_reset(struct bnx2x *bp)
9329 bool global = bnx2x_reset_is_global(bp);
9332 /* if not going to reset MCP - load "fake" driver to reset HW while
9333 * driver is owner of the HW
9335 if (!global && !BP_NOMCP(bp)) {
9336 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9337 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9339 BNX2X_ERR("MCP response failure, aborting\n");
9341 goto exit_leader_reset;
9343 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9344 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9345 BNX2X_ERR("MCP unexpected resp, aborting\n");
9347 goto exit_leader_reset2;
9349 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9351 BNX2X_ERR("MCP response failure, aborting\n");
9353 goto exit_leader_reset2;
9357 /* Try to recover after the failure */
9358 if (bnx2x_process_kill(bp, global)) {
9359 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9362 goto exit_leader_reset2;
9366 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9369 bnx2x_set_reset_done(bp);
9371 bnx2x_clear_reset_global(bp);
9374 /* unload "fake driver" if it was loaded */
9375 if (!global && !BP_NOMCP(bp)) {
9376 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9377 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9381 bnx2x_release_leader_lock(bp);
9386 static void bnx2x_recovery_failed(struct bnx2x *bp)
9388 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9390 /* Disconnect this device */
9391 netif_device_detach(bp->dev);
9394 * Block ifup for all function on this engine until "process kill"
9397 bnx2x_set_reset_in_progress(bp);
9399 /* Shut down the power */
9400 bnx2x_set_power_state(bp, PCI_D3hot);
9402 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9408 * Assumption: runs under rtnl lock. This together with the fact
9409 * that it's called only from bnx2x_sp_rtnl() ensure that it
9410 * will never be called when netif_running(bp->dev) is false.
9412 static void bnx2x_parity_recover(struct bnx2x *bp)
9414 bool global = false;
9415 u32 error_recovered, error_unrecovered;
9418 DP(NETIF_MSG_HW, "Handling parity\n");
9420 switch (bp->recovery_state) {
9421 case BNX2X_RECOVERY_INIT:
9422 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9423 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9424 WARN_ON(!is_parity);
9426 /* Try to get a LEADER_LOCK HW lock */
9427 if (bnx2x_trylock_leader_lock(bp)) {
9428 bnx2x_set_reset_in_progress(bp);
9430 * Check if there is a global attention and if
9431 * there was a global attention, set the global
9436 bnx2x_set_reset_global(bp);
9441 /* Stop the driver */
9442 /* If interface has been removed - break */
9443 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9446 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9448 /* Ensure "is_leader", MCP command sequence and
9449 * "recovery_state" update values are seen on other
9455 case BNX2X_RECOVERY_WAIT:
9456 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9457 if (bp->is_leader) {
9458 int other_engine = BP_PATH(bp) ? 0 : 1;
9459 bool other_load_status =
9460 bnx2x_get_load_status(bp, other_engine);
9462 bnx2x_get_load_status(bp, BP_PATH(bp));
9463 global = bnx2x_reset_is_global(bp);
9466 * In case of a parity in a global block, let
9467 * the first leader that performs a
9468 * leader_reset() reset the global blocks in
9469 * order to clear global attentions. Otherwise
9470 * the gates will remain closed for that
9474 (global && other_load_status)) {
9475 /* Wait until all other functions get
9478 schedule_delayed_work(&bp->sp_rtnl_task,
9482 /* If all other functions got down -
9483 * try to bring the chip back to
9484 * normal. In any case it's an exit
9485 * point for a leader.
9487 if (bnx2x_leader_reset(bp)) {
9488 bnx2x_recovery_failed(bp);
9492 /* If we are here, means that the
9493 * leader has succeeded and doesn't
9494 * want to be a leader any more. Try
9495 * to continue as a none-leader.
9499 } else { /* non-leader */
9500 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9501 /* Try to get a LEADER_LOCK HW lock as
9502 * long as a former leader may have
9503 * been unloaded by the user or
9504 * released a leadership by another
9507 if (bnx2x_trylock_leader_lock(bp)) {
9508 /* I'm a leader now! Restart a
9515 schedule_delayed_work(&bp->sp_rtnl_task,
9521 * If there was a global attention, wait
9522 * for it to be cleared.
9524 if (bnx2x_reset_is_global(bp)) {
9525 schedule_delayed_work(
9532 bp->eth_stats.recoverable_error;
9534 bp->eth_stats.unrecoverable_error;
9535 bp->recovery_state =
9536 BNX2X_RECOVERY_NIC_LOADING;
9537 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9538 error_unrecovered++;
9540 "Recovery failed. Power cycle needed\n");
9541 /* Disconnect this device */
9542 netif_device_detach(bp->dev);
9543 /* Shut down the power */
9544 bnx2x_set_power_state(
9548 bp->recovery_state =
9549 BNX2X_RECOVERY_DONE;
9553 bp->eth_stats.recoverable_error =
9555 bp->eth_stats.unrecoverable_error =
9567 static int bnx2x_close(struct net_device *dev);
9569 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9570 * scheduled on a general queue in order to prevent a dead lock.
9572 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9574 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9578 if (!netif_running(bp->dev)) {
9583 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9584 #ifdef BNX2X_STOP_ON_ERROR
9585 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9586 "you will need to reboot when done\n");
9587 goto sp_rtnl_not_reset;
9590 * Clear all pending SP commands as we are going to reset the
9593 bp->sp_rtnl_state = 0;
9596 bnx2x_parity_recover(bp);
9602 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9603 #ifdef BNX2X_STOP_ON_ERROR
9604 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9605 "you will need to reboot when done\n");
9606 goto sp_rtnl_not_reset;
9610 * Clear all pending SP commands as we are going to reset the
9613 bp->sp_rtnl_state = 0;
9616 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9617 bnx2x_nic_load(bp, LOAD_NORMAL);
9622 #ifdef BNX2X_STOP_ON_ERROR
9625 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9626 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9627 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9628 bnx2x_after_function_update(bp);
9630 * in case of fan failure we need to reset id if the "stop on error"
9631 * debug flag is set, since we trying to prevent permanent overheating
9634 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9635 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9636 netif_device_detach(bp->dev);
9637 bnx2x_close(bp->dev);
9642 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9644 "sending set mcast vf pf channel message from rtnl sp-task\n");
9645 bnx2x_vfpf_set_mcast(bp->dev);
9647 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9648 &bp->sp_rtnl_state)){
9649 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9650 bnx2x_tx_disable(bp);
9651 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9655 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9656 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9657 bnx2x_set_rx_mode_inner(bp);
9660 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9661 &bp->sp_rtnl_state))
9662 bnx2x_pf_set_vfs_vlan(bp);
9664 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))
9665 bnx2x_dcbx_stop_hw_tx(bp);
9667 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))
9668 bnx2x_dcbx_resume_hw_tx(bp);
9670 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9671 * can be called from other contexts as well)
9675 /* enable SR-IOV if applicable */
9676 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9677 &bp->sp_rtnl_state)) {
9678 bnx2x_disable_sriov(bp);
9679 bnx2x_enable_sriov(bp);
9683 static void bnx2x_period_task(struct work_struct *work)
9685 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9687 if (!netif_running(bp->dev))
9688 goto period_task_exit;
9690 if (CHIP_REV_IS_SLOW(bp)) {
9691 BNX2X_ERR("period task called on emulation, ignoring\n");
9692 goto period_task_exit;
9695 bnx2x_acquire_phy_lock(bp);
9697 * The barrier is needed to ensure the ordering between the writing to
9698 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9703 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9705 /* Re-queue task in 1 sec */
9706 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9709 bnx2x_release_phy_lock(bp);
9715 * Init service functions
9718 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9720 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9721 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9722 return base + (BP_ABS_FUNC(bp)) * stride;
9725 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9726 struct bnx2x_mac_vals *vals)
9728 u32 val, base_addr, offset, mask, reset_reg;
9729 bool mac_stopped = false;
9730 u8 port = BP_PORT(bp);
9732 /* reset addresses as they also mark which values were changed */
9733 vals->bmac_addr = 0;
9734 vals->umac_addr = 0;
9735 vals->xmac_addr = 0;
9736 vals->emac_addr = 0;
9738 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9740 if (!CHIP_IS_E3(bp)) {
9741 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9742 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9743 if ((mask & reset_reg) && val) {
9745 BNX2X_DEV_INFO("Disable bmac Rx\n");
9746 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9747 : NIG_REG_INGRESS_BMAC0_MEM;
9748 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9749 : BIGMAC_REGISTER_BMAC_CONTROL;
9752 * use rd/wr since we cannot use dmae. This is safe
9753 * since MCP won't access the bus due to the request
9754 * to unload, and no function on the path can be
9755 * loaded at this time.
9757 wb_data[0] = REG_RD(bp, base_addr + offset);
9758 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9759 vals->bmac_addr = base_addr + offset;
9760 vals->bmac_val[0] = wb_data[0];
9761 vals->bmac_val[1] = wb_data[1];
9762 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9763 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9764 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9766 BNX2X_DEV_INFO("Disable emac Rx\n");
9767 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9768 vals->emac_val = REG_RD(bp, vals->emac_addr);
9769 REG_WR(bp, vals->emac_addr, 0);
9772 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9773 BNX2X_DEV_INFO("Disable xmac Rx\n");
9774 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9775 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9776 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9778 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9780 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9781 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9782 REG_WR(bp, vals->xmac_addr, 0);
9785 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9786 if (mask & reset_reg) {
9787 BNX2X_DEV_INFO("Disable umac Rx\n");
9788 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9789 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9790 vals->umac_val = REG_RD(bp, vals->umac_addr);
9791 REG_WR(bp, vals->umac_addr, 0);
9800 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9801 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9802 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9803 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9805 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9808 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9810 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9811 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9813 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9814 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9816 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9820 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9822 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9823 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9825 BNX2X_ERR("MCP response failure, aborting\n");
9832 static struct bnx2x_prev_path_list *
9833 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9835 struct bnx2x_prev_path_list *tmp_list;
9837 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9838 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9839 bp->pdev->bus->number == tmp_list->bus &&
9840 BP_PATH(bp) == tmp_list->path)
9846 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9848 struct bnx2x_prev_path_list *tmp_list;
9851 rc = down_interruptible(&bnx2x_prev_sem);
9853 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9857 tmp_list = bnx2x_prev_path_get_entry(bp);
9862 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9866 up(&bnx2x_prev_sem);
9871 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9873 struct bnx2x_prev_path_list *tmp_list;
9876 if (down_trylock(&bnx2x_prev_sem))
9879 tmp_list = bnx2x_prev_path_get_entry(bp);
9881 if (tmp_list->aer) {
9882 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9886 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9891 up(&bnx2x_prev_sem);
9896 bool bnx2x_port_after_undi(struct bnx2x *bp)
9898 struct bnx2x_prev_path_list *entry;
9901 down(&bnx2x_prev_sem);
9903 entry = bnx2x_prev_path_get_entry(bp);
9904 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9906 up(&bnx2x_prev_sem);
9911 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9913 struct bnx2x_prev_path_list *tmp_list;
9916 rc = down_interruptible(&bnx2x_prev_sem);
9918 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9922 /* Check whether the entry for this path already exists */
9923 tmp_list = bnx2x_prev_path_get_entry(bp);
9925 if (!tmp_list->aer) {
9926 BNX2X_ERR("Re-Marking the path.\n");
9928 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9932 up(&bnx2x_prev_sem);
9935 up(&bnx2x_prev_sem);
9937 /* Create an entry for this path and add it */
9938 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9940 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9944 tmp_list->bus = bp->pdev->bus->number;
9945 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9946 tmp_list->path = BP_PATH(bp);
9948 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9950 rc = down_interruptible(&bnx2x_prev_sem);
9952 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9955 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9957 list_add(&tmp_list->list, &bnx2x_prev_list);
9958 up(&bnx2x_prev_sem);
9964 static int bnx2x_do_flr(struct bnx2x *bp)
9968 struct pci_dev *dev = bp->pdev;
9970 if (CHIP_IS_E1x(bp)) {
9971 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9975 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9976 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9977 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9982 /* Wait for Transaction Pending bit clean */
9983 for (i = 0; i < 4; i++) {
9985 msleep((1 << (i - 1)) * 100);
9987 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9988 if (!(status & PCI_EXP_DEVSTA_TRPND))
9993 "transaction is not cleared; proceeding with reset anyway\n");
9997 BNX2X_DEV_INFO("Initiating FLR\n");
9998 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10003 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10007 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10009 /* Test if previous unload process was already finished for this path */
10010 if (bnx2x_prev_is_path_marked(bp))
10011 return bnx2x_prev_mcp_done(bp);
10013 BNX2X_DEV_INFO("Path is unmarked\n");
10015 /* If function has FLR capabilities, and existing FW version matches
10016 * the one required, then FLR will be sufficient to clean any residue
10017 * left by previous driver
10019 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10022 /* fw version is good */
10023 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10024 rc = bnx2x_do_flr(bp);
10028 /* FLR was performed */
10029 BNX2X_DEV_INFO("FLR successful\n");
10033 BNX2X_DEV_INFO("Could not FLR\n");
10035 /* Close the MCP request, return failure*/
10036 rc = bnx2x_prev_mcp_done(bp);
10038 rc = BNX2X_PREV_WAIT_NEEDED;
10043 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10045 u32 reset_reg, tmp_reg = 0, rc;
10046 bool prev_undi = false;
10047 struct bnx2x_mac_vals mac_vals;
10049 /* It is possible a previous function received 'common' answer,
10050 * but hasn't loaded yet, therefore creating a scenario of
10051 * multiple functions receiving 'common' on the same path.
10053 BNX2X_DEV_INFO("Common unload Flow\n");
10055 memset(&mac_vals, 0, sizeof(mac_vals));
10057 if (bnx2x_prev_is_path_marked(bp))
10058 return bnx2x_prev_mcp_done(bp);
10060 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10062 /* Reset should be performed after BRB is emptied */
10063 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10064 u32 timer_count = 1000;
10066 /* Close the MAC Rx to prevent BRB from filling up */
10067 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10069 /* close LLH filters towards the BRB */
10070 bnx2x_set_rx_filter(&bp->link_params, 0);
10072 /* Check if the UNDI driver was previously loaded
10073 * UNDI driver initializes CID offset for normal bell to 0x7
10075 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10076 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10077 if (tmp_reg == 0x7) {
10078 BNX2X_DEV_INFO("UNDI previously loaded\n");
10080 /* clear the UNDI indication */
10081 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10082 /* clear possible idle check errors */
10083 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10086 if (!CHIP_IS_E1x(bp))
10087 /* block FW from writing to host */
10088 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10090 /* wait until BRB is empty */
10091 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10092 while (timer_count) {
10093 u32 prev_brb = tmp_reg;
10095 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10099 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10101 /* reset timer as long as BRB actually gets emptied */
10102 if (prev_brb > tmp_reg)
10103 timer_count = 1000;
10107 /* If UNDI resides in memory, manually increment it */
10109 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10115 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10118 /* No packets are in the pipeline, path is ready for reset */
10119 bnx2x_reset_common(bp);
10121 if (mac_vals.xmac_addr)
10122 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10123 if (mac_vals.umac_addr)
10124 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10125 if (mac_vals.emac_addr)
10126 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10127 if (mac_vals.bmac_addr) {
10128 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10129 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10132 rc = bnx2x_prev_mark_path(bp, prev_undi);
10134 bnx2x_prev_mcp_done(bp);
10138 return bnx2x_prev_mcp_done(bp);
10141 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10142 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10143 * the addresses of the transaction, resulting in was-error bit set in the pci
10144 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10145 * to clear the interrupt which detected this from the pglueb and the was done
10148 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10150 if (!CHIP_IS_E1x(bp)) {
10151 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10152 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10154 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10155 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10161 static int bnx2x_prev_unload(struct bnx2x *bp)
10163 int time_counter = 10;
10164 u32 rc, fw, hw_lock_reg, hw_lock_val;
10165 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10167 /* clear hw from errors which may have resulted from an interrupted
10168 * dmae transaction.
10170 bnx2x_prev_interrupted_dmae(bp);
10172 /* Release previously held locks */
10173 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10174 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10175 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10177 hw_lock_val = REG_RD(bp, hw_lock_reg);
10179 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10180 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10181 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10182 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10185 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10186 REG_WR(bp, hw_lock_reg, 0xffffffff);
10188 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10190 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10191 BNX2X_DEV_INFO("Release previously held alr\n");
10192 bnx2x_release_alr(bp);
10197 /* Lock MCP using an unload request */
10198 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10200 BNX2X_ERR("MCP response failure, aborting\n");
10205 rc = down_interruptible(&bnx2x_prev_sem);
10207 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10210 /* If Path is marked by EEH, ignore unload status */
10211 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10212 bnx2x_prev_path_get_entry(bp)->aer);
10213 up(&bnx2x_prev_sem);
10216 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10217 rc = bnx2x_prev_unload_common(bp);
10221 /* non-common reply from MCP might require looping */
10222 rc = bnx2x_prev_unload_uncommon(bp);
10223 if (rc != BNX2X_PREV_WAIT_NEEDED)
10227 } while (--time_counter);
10229 if (!time_counter || rc) {
10230 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10234 /* Mark function if its port was used to boot from SAN */
10235 if (bnx2x_port_after_undi(bp))
10236 bp->link_params.feature_config_flags |=
10237 FEATURE_CONFIG_BOOT_FROM_SAN;
10239 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10244 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10246 u32 val, val2, val3, val4, id, boot_mode;
10249 /* Get the chip revision id and number. */
10250 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10251 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10252 id = ((val & 0xffff) << 16);
10253 val = REG_RD(bp, MISC_REG_CHIP_REV);
10254 id |= ((val & 0xf) << 12);
10256 /* Metal is read from PCI regs, but we can't access >=0x400 from
10257 * the configuration space (so we need to reg_rd)
10259 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10260 id |= (((val >> 24) & 0xf) << 4);
10261 val = REG_RD(bp, MISC_REG_BOND_ID);
10263 bp->common.chip_id = id;
10265 /* force 57811 according to MISC register */
10266 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10267 if (CHIP_IS_57810(bp))
10268 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10269 (bp->common.chip_id & 0x0000FFFF);
10270 else if (CHIP_IS_57810_MF(bp))
10271 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10272 (bp->common.chip_id & 0x0000FFFF);
10273 bp->common.chip_id |= 0x1;
10276 /* Set doorbell size */
10277 bp->db_size = (1 << BNX2X_DB_SHIFT);
10279 if (!CHIP_IS_E1x(bp)) {
10280 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10281 if ((val & 1) == 0)
10282 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10284 val = (val >> 1) & 1;
10285 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10287 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10290 if (CHIP_MODE_IS_4_PORT(bp))
10291 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10293 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10295 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10296 bp->pfid = bp->pf_num; /* 0..7 */
10299 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10301 bp->link_params.chip_id = bp->common.chip_id;
10302 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10304 val = (REG_RD(bp, 0x2874) & 0x55);
10305 if ((bp->common.chip_id & 0x1) ||
10306 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10307 bp->flags |= ONE_PORT_FLAG;
10308 BNX2X_DEV_INFO("single port device\n");
10311 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10312 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10313 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10314 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10315 bp->common.flash_size, bp->common.flash_size);
10317 bnx2x_init_shmem(bp);
10319 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10320 MISC_REG_GENERIC_CR_1 :
10321 MISC_REG_GENERIC_CR_0));
10323 bp->link_params.shmem_base = bp->common.shmem_base;
10324 bp->link_params.shmem2_base = bp->common.shmem2_base;
10325 if (SHMEM2_RD(bp, size) >
10326 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10327 bp->link_params.lfa_base =
10328 REG_RD(bp, bp->common.shmem2_base +
10329 (u32)offsetof(struct shmem2_region,
10330 lfa_host_addr[BP_PORT(bp)]));
10332 bp->link_params.lfa_base = 0;
10333 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10334 bp->common.shmem_base, bp->common.shmem2_base);
10336 if (!bp->common.shmem_base) {
10337 BNX2X_DEV_INFO("MCP not active\n");
10338 bp->flags |= NO_MCP_FLAG;
10342 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10343 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10345 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10346 SHARED_HW_CFG_LED_MODE_MASK) >>
10347 SHARED_HW_CFG_LED_MODE_SHIFT);
10349 bp->link_params.feature_config_flags = 0;
10350 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10351 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10352 bp->link_params.feature_config_flags |=
10353 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10355 bp->link_params.feature_config_flags &=
10356 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10358 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10359 bp->common.bc_ver = val;
10360 BNX2X_DEV_INFO("bc_ver %X\n", val);
10361 if (val < BNX2X_BC_VER) {
10362 /* for now only warn
10363 * later we might need to enforce this */
10364 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10365 BNX2X_BC_VER, val);
10367 bp->link_params.feature_config_flags |=
10368 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10369 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10371 bp->link_params.feature_config_flags |=
10372 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10373 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10374 bp->link_params.feature_config_flags |=
10375 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10376 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10377 bp->link_params.feature_config_flags |=
10378 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10379 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10381 bp->link_params.feature_config_flags |=
10382 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10383 FEATURE_CONFIG_MT_SUPPORT : 0;
10385 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10386 BC_SUPPORTS_PFC_STATS : 0;
10388 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10389 BC_SUPPORTS_FCOE_FEATURES : 0;
10391 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10392 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10394 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10395 BC_SUPPORTS_RMMOD_CMD : 0;
10397 boot_mode = SHMEM_RD(bp,
10398 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10399 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10400 switch (boot_mode) {
10401 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10402 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10404 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10405 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10407 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10408 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10410 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10411 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10415 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10416 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10418 BNX2X_DEV_INFO("%sWoL capable\n",
10419 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10421 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10422 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10423 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10424 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10426 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10427 val, val2, val3, val4);
10430 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10431 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10433 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10435 int pfid = BP_FUNC(bp);
10438 u8 fid, igu_sb_cnt = 0;
10440 bp->igu_base_sb = 0xff;
10441 if (CHIP_INT_MODE_IS_BC(bp)) {
10442 int vn = BP_VN(bp);
10443 igu_sb_cnt = bp->igu_sb_cnt;
10444 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10447 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10448 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10453 /* IGU in normal mode - read CAM */
10454 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10456 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10457 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10459 fid = IGU_FID(val);
10460 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10461 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10463 if (IGU_VEC(val) == 0)
10464 /* default status block */
10465 bp->igu_dsb_id = igu_sb_id;
10467 if (bp->igu_base_sb == 0xff)
10468 bp->igu_base_sb = igu_sb_id;
10474 #ifdef CONFIG_PCI_MSI
10475 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10476 * optional that number of CAM entries will not be equal to the value
10477 * advertised in PCI.
10478 * Driver should use the minimal value of both as the actual status
10481 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10484 if (igu_sb_cnt == 0) {
10485 BNX2X_ERR("CAM configuration error\n");
10492 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10494 int cfg_size = 0, idx, port = BP_PORT(bp);
10496 /* Aggregation of supported attributes of all external phys */
10497 bp->port.supported[0] = 0;
10498 bp->port.supported[1] = 0;
10499 switch (bp->link_params.num_phys) {
10501 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10505 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10509 if (bp->link_params.multi_phy_config &
10510 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10511 bp->port.supported[1] =
10512 bp->link_params.phy[EXT_PHY1].supported;
10513 bp->port.supported[0] =
10514 bp->link_params.phy[EXT_PHY2].supported;
10516 bp->port.supported[0] =
10517 bp->link_params.phy[EXT_PHY1].supported;
10518 bp->port.supported[1] =
10519 bp->link_params.phy[EXT_PHY2].supported;
10525 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10526 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10528 dev_info.port_hw_config[port].external_phy_config),
10530 dev_info.port_hw_config[port].external_phy_config2));
10534 if (CHIP_IS_E3(bp))
10535 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10537 switch (switch_cfg) {
10538 case SWITCH_CFG_1G:
10539 bp->port.phy_addr = REG_RD(
10540 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10542 case SWITCH_CFG_10G:
10543 bp->port.phy_addr = REG_RD(
10544 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10547 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10548 bp->port.link_config[0]);
10552 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10553 /* mask what we support according to speed_cap_mask per configuration */
10554 for (idx = 0; idx < cfg_size; idx++) {
10555 if (!(bp->link_params.speed_cap_mask[idx] &
10556 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10557 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10559 if (!(bp->link_params.speed_cap_mask[idx] &
10560 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10561 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10563 if (!(bp->link_params.speed_cap_mask[idx] &
10564 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10565 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10567 if (!(bp->link_params.speed_cap_mask[idx] &
10568 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10569 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10571 if (!(bp->link_params.speed_cap_mask[idx] &
10572 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10573 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10574 SUPPORTED_1000baseT_Full);
10576 if (!(bp->link_params.speed_cap_mask[idx] &
10577 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10578 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10580 if (!(bp->link_params.speed_cap_mask[idx] &
10581 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10582 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10584 if (!(bp->link_params.speed_cap_mask[idx] &
10585 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10586 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10589 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10590 bp->port.supported[1]);
10593 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10595 u32 link_config, idx, cfg_size = 0;
10596 bp->port.advertising[0] = 0;
10597 bp->port.advertising[1] = 0;
10598 switch (bp->link_params.num_phys) {
10607 for (idx = 0; idx < cfg_size; idx++) {
10608 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10609 link_config = bp->port.link_config[idx];
10610 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10611 case PORT_FEATURE_LINK_SPEED_AUTO:
10612 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10613 bp->link_params.req_line_speed[idx] =
10615 bp->port.advertising[idx] |=
10616 bp->port.supported[idx];
10617 if (bp->link_params.phy[EXT_PHY1].type ==
10618 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10619 bp->port.advertising[idx] |=
10620 (SUPPORTED_100baseT_Half |
10621 SUPPORTED_100baseT_Full);
10623 /* force 10G, no AN */
10624 bp->link_params.req_line_speed[idx] =
10626 bp->port.advertising[idx] |=
10627 (ADVERTISED_10000baseT_Full |
10633 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10634 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10635 bp->link_params.req_line_speed[idx] =
10637 bp->port.advertising[idx] |=
10638 (ADVERTISED_10baseT_Full |
10641 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10643 bp->link_params.speed_cap_mask[idx]);
10648 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10649 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10650 bp->link_params.req_line_speed[idx] =
10652 bp->link_params.req_duplex[idx] =
10654 bp->port.advertising[idx] |=
10655 (ADVERTISED_10baseT_Half |
10658 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10660 bp->link_params.speed_cap_mask[idx]);
10665 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10666 if (bp->port.supported[idx] &
10667 SUPPORTED_100baseT_Full) {
10668 bp->link_params.req_line_speed[idx] =
10670 bp->port.advertising[idx] |=
10671 (ADVERTISED_100baseT_Full |
10674 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10676 bp->link_params.speed_cap_mask[idx]);
10681 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10682 if (bp->port.supported[idx] &
10683 SUPPORTED_100baseT_Half) {
10684 bp->link_params.req_line_speed[idx] =
10686 bp->link_params.req_duplex[idx] =
10688 bp->port.advertising[idx] |=
10689 (ADVERTISED_100baseT_Half |
10692 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10694 bp->link_params.speed_cap_mask[idx]);
10699 case PORT_FEATURE_LINK_SPEED_1G:
10700 if (bp->port.supported[idx] &
10701 SUPPORTED_1000baseT_Full) {
10702 bp->link_params.req_line_speed[idx] =
10704 bp->port.advertising[idx] |=
10705 (ADVERTISED_1000baseT_Full |
10708 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10710 bp->link_params.speed_cap_mask[idx]);
10715 case PORT_FEATURE_LINK_SPEED_2_5G:
10716 if (bp->port.supported[idx] &
10717 SUPPORTED_2500baseX_Full) {
10718 bp->link_params.req_line_speed[idx] =
10720 bp->port.advertising[idx] |=
10721 (ADVERTISED_2500baseX_Full |
10724 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10726 bp->link_params.speed_cap_mask[idx]);
10731 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10732 if (bp->port.supported[idx] &
10733 SUPPORTED_10000baseT_Full) {
10734 bp->link_params.req_line_speed[idx] =
10736 bp->port.advertising[idx] |=
10737 (ADVERTISED_10000baseT_Full |
10740 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10742 bp->link_params.speed_cap_mask[idx]);
10746 case PORT_FEATURE_LINK_SPEED_20G:
10747 bp->link_params.req_line_speed[idx] = SPEED_20000;
10751 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10753 bp->link_params.req_line_speed[idx] =
10755 bp->port.advertising[idx] =
10756 bp->port.supported[idx];
10760 bp->link_params.req_flow_ctrl[idx] = (link_config &
10761 PORT_FEATURE_FLOW_CONTROL_MASK);
10762 if (bp->link_params.req_flow_ctrl[idx] ==
10763 BNX2X_FLOW_CTRL_AUTO) {
10764 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10765 bp->link_params.req_flow_ctrl[idx] =
10766 BNX2X_FLOW_CTRL_NONE;
10768 bnx2x_set_requested_fc(bp);
10771 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10772 bp->link_params.req_line_speed[idx],
10773 bp->link_params.req_duplex[idx],
10774 bp->link_params.req_flow_ctrl[idx],
10775 bp->port.advertising[idx]);
10779 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10781 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10782 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10783 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10784 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10787 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10789 int port = BP_PORT(bp);
10791 u32 ext_phy_type, ext_phy_config, eee_mode;
10793 bp->link_params.bp = bp;
10794 bp->link_params.port = port;
10796 bp->link_params.lane_config =
10797 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10799 bp->link_params.speed_cap_mask[0] =
10801 dev_info.port_hw_config[port].speed_capability_mask) &
10802 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10803 bp->link_params.speed_cap_mask[1] =
10805 dev_info.port_hw_config[port].speed_capability_mask2) &
10806 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10807 bp->port.link_config[0] =
10808 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10810 bp->port.link_config[1] =
10811 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10813 bp->link_params.multi_phy_config =
10814 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10815 /* If the device is capable of WoL, set the default state according
10818 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10819 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10820 (config & PORT_FEATURE_WOL_ENABLED));
10822 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10823 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10824 bp->flags |= NO_ISCSI_FLAG;
10825 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10826 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10827 bp->flags |= NO_FCOE_FLAG;
10829 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10830 bp->link_params.lane_config,
10831 bp->link_params.speed_cap_mask[0],
10832 bp->port.link_config[0]);
10834 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10835 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10836 bnx2x_phy_probe(&bp->link_params);
10837 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10839 bnx2x_link_settings_requested(bp);
10842 * If connected directly, work with the internal PHY, otherwise, work
10843 * with the external PHY
10847 dev_info.port_hw_config[port].external_phy_config);
10848 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10849 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10850 bp->mdio.prtad = bp->port.phy_addr;
10852 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10853 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10855 XGXS_EXT_PHY_ADDR(ext_phy_config);
10857 /* Configure link feature according to nvram value */
10858 eee_mode = (((SHMEM_RD(bp, dev_info.
10859 port_feature_config[port].eee_power_mode)) &
10860 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10861 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10862 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10863 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10864 EEE_MODE_ENABLE_LPI |
10865 EEE_MODE_OUTPUT_TIME;
10867 bp->link_params.eee_mode = 0;
10871 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10873 u32 no_flags = NO_ISCSI_FLAG;
10874 int port = BP_PORT(bp);
10875 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10876 drv_lic_key[port].max_iscsi_conn);
10878 if (!CNIC_SUPPORT(bp)) {
10879 bp->flags |= no_flags;
10883 /* Get the number of maximum allowed iSCSI connections */
10884 bp->cnic_eth_dev.max_iscsi_conn =
10885 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10886 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10888 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10889 bp->cnic_eth_dev.max_iscsi_conn);
10892 * If maximum allowed number of connections is zero -
10893 * disable the feature.
10895 if (!bp->cnic_eth_dev.max_iscsi_conn)
10896 bp->flags |= no_flags;
10899 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10902 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10903 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10904 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10905 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10908 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10909 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10910 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10911 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10914 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10921 /* iterate over absolute function ids for this path: */
10922 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10923 if (IS_MF_SD(bp)) {
10924 u32 cfg = MF_CFG_RD(bp,
10925 func_mf_config[fid].config);
10927 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10928 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10929 FUNC_MF_CFG_PROTOCOL_FCOE))
10932 u32 cfg = MF_CFG_RD(bp,
10933 func_ext_config[fid].
10936 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10937 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10942 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10944 for (port = 0; port < port_cnt; port++) {
10945 u32 lic = SHMEM_RD(bp,
10946 drv_lic_key[port].max_fcoe_conn) ^
10947 FW_ENCODE_32BIT_PATTERN;
10956 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10958 int port = BP_PORT(bp);
10959 int func = BP_ABS_FUNC(bp);
10960 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10961 drv_lic_key[port].max_fcoe_conn);
10962 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10964 if (!CNIC_SUPPORT(bp)) {
10965 bp->flags |= NO_FCOE_FLAG;
10969 /* Get the number of maximum allowed FCoE connections */
10970 bp->cnic_eth_dev.max_fcoe_conn =
10971 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10972 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10974 /* Calculate the number of maximum allowed FCoE tasks */
10975 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
10977 /* check if FCoE resources must be shared between different functions */
10979 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
10981 /* Read the WWN: */
10984 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10986 dev_info.port_hw_config[port].
10987 fcoe_wwn_port_name_upper);
10988 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10990 dev_info.port_hw_config[port].
10991 fcoe_wwn_port_name_lower);
10994 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10996 dev_info.port_hw_config[port].
10997 fcoe_wwn_node_name_upper);
10998 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11000 dev_info.port_hw_config[port].
11001 fcoe_wwn_node_name_lower);
11002 } else if (!IS_MF_SD(bp)) {
11004 * Read the WWN info only if the FCoE feature is enabled for
11007 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11008 bnx2x_get_ext_wwn_info(bp, func);
11010 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11011 bnx2x_get_ext_wwn_info(bp, func);
11014 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11017 * If maximum allowed number of connections is zero -
11018 * disable the feature.
11020 if (!bp->cnic_eth_dev.max_fcoe_conn)
11021 bp->flags |= NO_FCOE_FLAG;
11024 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11027 * iSCSI may be dynamically disabled but reading
11028 * info here we will decrease memory usage by driver
11029 * if the feature is disabled for good
11031 bnx2x_get_iscsi_info(bp);
11032 bnx2x_get_fcoe_info(bp);
11035 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11038 int func = BP_ABS_FUNC(bp);
11039 int port = BP_PORT(bp);
11040 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11041 u8 *fip_mac = bp->fip_mac;
11044 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11045 * FCoE MAC then the appropriate feature should be disabled.
11046 * In non SD mode features configuration comes from struct
11049 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11050 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11051 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11052 val2 = MF_CFG_RD(bp, func_ext_config[func].
11053 iscsi_mac_addr_upper);
11054 val = MF_CFG_RD(bp, func_ext_config[func].
11055 iscsi_mac_addr_lower);
11056 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11058 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11060 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11063 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11064 val2 = MF_CFG_RD(bp, func_ext_config[func].
11065 fcoe_mac_addr_upper);
11066 val = MF_CFG_RD(bp, func_ext_config[func].
11067 fcoe_mac_addr_lower);
11068 bnx2x_set_mac_buf(fip_mac, val, val2);
11070 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11072 bp->flags |= NO_FCOE_FLAG;
11075 bp->mf_ext_config = cfg;
11077 } else { /* SD MODE */
11078 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11079 /* use primary mac as iscsi mac */
11080 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11082 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11084 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11085 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11086 /* use primary mac as fip mac */
11087 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11088 BNX2X_DEV_INFO("SD FCoE MODE\n");
11090 ("Read FIP MAC: %pM\n", fip_mac);
11094 /* If this is a storage-only interface, use SAN mac as
11095 * primary MAC. Notice that for SD this is already the case,
11096 * as the SAN mac was copied from the primary MAC.
11098 if (IS_MF_FCOE_AFEX(bp))
11099 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11101 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11103 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11105 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11107 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11108 fcoe_fip_mac_upper);
11109 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11110 fcoe_fip_mac_lower);
11111 bnx2x_set_mac_buf(fip_mac, val, val2);
11114 /* Disable iSCSI OOO if MAC configuration is invalid. */
11115 if (!is_valid_ether_addr(iscsi_mac)) {
11116 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11117 memset(iscsi_mac, 0, ETH_ALEN);
11120 /* Disable FCoE if MAC configuration is invalid. */
11121 if (!is_valid_ether_addr(fip_mac)) {
11122 bp->flags |= NO_FCOE_FLAG;
11123 memset(bp->fip_mac, 0, ETH_ALEN);
11127 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11130 int func = BP_ABS_FUNC(bp);
11131 int port = BP_PORT(bp);
11133 /* Zero primary MAC configuration */
11134 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11136 if (BP_NOMCP(bp)) {
11137 BNX2X_ERROR("warning: random MAC workaround active\n");
11138 eth_hw_addr_random(bp->dev);
11139 } else if (IS_MF(bp)) {
11140 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11141 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11142 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11143 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11144 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11146 if (CNIC_SUPPORT(bp))
11147 bnx2x_get_cnic_mac_hwinfo(bp);
11149 /* in SF read MACs from port configuration */
11150 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11151 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11152 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11154 if (CNIC_SUPPORT(bp))
11155 bnx2x_get_cnic_mac_hwinfo(bp);
11158 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11160 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11161 dev_err(&bp->pdev->dev,
11162 "bad Ethernet MAC address configuration: %pM\n"
11163 "change it manually before bringing up the appropriate network interface\n",
11164 bp->dev->dev_addr);
11167 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11175 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11176 /* Take function: tmp = func */
11177 tmp = BP_ABS_FUNC(bp);
11178 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11179 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11181 /* Take port: tmp = port */
11184 dev_info.port_hw_config[tmp].generic_features);
11185 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11190 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11192 int /*abs*/func = BP_ABS_FUNC(bp);
11197 bnx2x_get_common_hwinfo(bp);
11200 * initialize IGU parameters
11202 if (CHIP_IS_E1x(bp)) {
11203 bp->common.int_block = INT_BLOCK_HC;
11205 bp->igu_dsb_id = DEF_SB_IGU_ID;
11206 bp->igu_base_sb = 0;
11208 bp->common.int_block = INT_BLOCK_IGU;
11210 /* do not allow device reset during IGU info processing */
11211 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11213 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11215 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11218 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11220 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11221 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11222 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11224 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11226 usleep_range(1000, 2000);
11229 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11230 dev_err(&bp->pdev->dev,
11231 "FORCING Normal Mode failed!!!\n");
11232 bnx2x_release_hw_lock(bp,
11233 HW_LOCK_RESOURCE_RESET);
11238 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11239 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11240 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11242 BNX2X_DEV_INFO("IGU Normal Mode\n");
11244 rc = bnx2x_get_igu_cam_info(bp);
11245 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11251 * set base FW non-default (fast path) status block id, this value is
11252 * used to initialize the fw_sb_id saved on the fp/queue structure to
11253 * determine the id used by the FW.
11255 if (CHIP_IS_E1x(bp))
11256 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11258 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11259 * the same queue are indicated on the same IGU SB). So we prefer
11260 * FW and IGU SBs to be the same value.
11262 bp->base_fw_ndsb = bp->igu_base_sb;
11264 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11265 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11266 bp->igu_sb_cnt, bp->base_fw_ndsb);
11269 * Initialize MF configuration
11276 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11277 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11278 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11279 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11281 if (SHMEM2_HAS(bp, mf_cfg_addr))
11282 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11284 bp->common.mf_cfg_base = bp->common.shmem_base +
11285 offsetof(struct shmem_region, func_mb) +
11286 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11288 * get mf configuration:
11289 * 1. Existence of MF configuration
11290 * 2. MAC address must be legal (check only upper bytes)
11291 * for Switch-Independent mode;
11292 * OVLAN must be legal for Switch-Dependent mode
11293 * 3. SF_MODE configures specific MF mode
11295 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11296 /* get mf configuration */
11298 dev_info.shared_feature_config.config);
11299 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11302 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11303 val = MF_CFG_RD(bp, func_mf_config[func].
11305 /* check for legal mac (upper bytes)*/
11306 if (val != 0xffff) {
11307 bp->mf_mode = MULTI_FUNCTION_SI;
11308 bp->mf_config[vn] = MF_CFG_RD(bp,
11309 func_mf_config[func].config);
11311 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11313 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11314 if ((!CHIP_IS_E1x(bp)) &&
11315 (MF_CFG_RD(bp, func_mf_config[func].
11316 mac_upper) != 0xffff) &&
11318 afex_driver_support))) {
11319 bp->mf_mode = MULTI_FUNCTION_AFEX;
11320 bp->mf_config[vn] = MF_CFG_RD(bp,
11321 func_mf_config[func].config);
11323 BNX2X_DEV_INFO("can not configure afex mode\n");
11326 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11327 /* get OV configuration */
11328 val = MF_CFG_RD(bp,
11329 func_mf_config[FUNC_0].e1hov_tag);
11330 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11332 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11333 bp->mf_mode = MULTI_FUNCTION_SD;
11334 bp->mf_config[vn] = MF_CFG_RD(bp,
11335 func_mf_config[func].config);
11337 BNX2X_DEV_INFO("illegal OV for SD\n");
11339 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11340 bp->mf_config[vn] = 0;
11343 /* Unknown configuration: reset mf_config */
11344 bp->mf_config[vn] = 0;
11345 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11349 BNX2X_DEV_INFO("%s function mode\n",
11350 IS_MF(bp) ? "multi" : "single");
11352 switch (bp->mf_mode) {
11353 case MULTI_FUNCTION_SD:
11354 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11355 FUNC_MF_CFG_E1HOV_TAG_MASK;
11356 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11358 bp->path_has_ovlan = true;
11360 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11361 func, bp->mf_ov, bp->mf_ov);
11363 dev_err(&bp->pdev->dev,
11364 "No valid MF OV for func %d, aborting\n",
11369 case MULTI_FUNCTION_AFEX:
11370 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11372 case MULTI_FUNCTION_SI:
11373 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11378 dev_err(&bp->pdev->dev,
11379 "VN %d is in a single function mode, aborting\n",
11386 /* check if other port on the path needs ovlan:
11387 * Since MF configuration is shared between ports
11388 * Possible mixed modes are only
11389 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11391 if (CHIP_MODE_IS_4_PORT(bp) &&
11392 !bp->path_has_ovlan &&
11394 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11395 u8 other_port = !BP_PORT(bp);
11396 u8 other_func = BP_PATH(bp) + 2*other_port;
11397 val = MF_CFG_RD(bp,
11398 func_mf_config[other_func].e1hov_tag);
11399 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11400 bp->path_has_ovlan = true;
11404 /* adjust igu_sb_cnt to MF for E1x */
11405 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11406 bp->igu_sb_cnt /= E1HVN_MAX;
11409 bnx2x_get_port_hwinfo(bp);
11411 /* Get MAC addresses */
11412 bnx2x_get_mac_hwinfo(bp);
11414 bnx2x_get_cnic_info(bp);
11419 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11421 int cnt, i, block_end, rodi;
11422 char vpd_start[BNX2X_VPD_LEN+1];
11423 char str_id_reg[VENDOR_ID_LEN+1];
11424 char str_id_cap[VENDOR_ID_LEN+1];
11426 char *vpd_extended_data = NULL;
11429 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11430 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11432 if (cnt < BNX2X_VPD_LEN)
11433 goto out_not_found;
11435 /* VPD RO tag should be first tag after identifier string, hence
11436 * we should be able to find it in first BNX2X_VPD_LEN chars
11438 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11439 PCI_VPD_LRDT_RO_DATA);
11441 goto out_not_found;
11443 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11444 pci_vpd_lrdt_size(&vpd_start[i]);
11446 i += PCI_VPD_LRDT_TAG_SIZE;
11448 if (block_end > BNX2X_VPD_LEN) {
11449 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11450 if (vpd_extended_data == NULL)
11451 goto out_not_found;
11453 /* read rest of vpd image into vpd_extended_data */
11454 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11455 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11456 block_end - BNX2X_VPD_LEN,
11457 vpd_extended_data + BNX2X_VPD_LEN);
11458 if (cnt < (block_end - BNX2X_VPD_LEN))
11459 goto out_not_found;
11460 vpd_data = vpd_extended_data;
11462 vpd_data = vpd_start;
11464 /* now vpd_data holds full vpd content in both cases */
11466 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11467 PCI_VPD_RO_KEYWORD_MFR_ID);
11469 goto out_not_found;
11471 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11473 if (len != VENDOR_ID_LEN)
11474 goto out_not_found;
11476 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11478 /* vendor specific info */
11479 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11480 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11481 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11482 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11484 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11485 PCI_VPD_RO_KEYWORD_VENDOR0);
11487 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11489 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11491 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11492 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11493 bp->fw_ver[len] = ' ';
11496 kfree(vpd_extended_data);
11500 kfree(vpd_extended_data);
11504 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11508 if (CHIP_REV_IS_FPGA(bp))
11509 SET_FLAGS(flags, MODE_FPGA);
11510 else if (CHIP_REV_IS_EMUL(bp))
11511 SET_FLAGS(flags, MODE_EMUL);
11513 SET_FLAGS(flags, MODE_ASIC);
11515 if (CHIP_MODE_IS_4_PORT(bp))
11516 SET_FLAGS(flags, MODE_PORT4);
11518 SET_FLAGS(flags, MODE_PORT2);
11520 if (CHIP_IS_E2(bp))
11521 SET_FLAGS(flags, MODE_E2);
11522 else if (CHIP_IS_E3(bp)) {
11523 SET_FLAGS(flags, MODE_E3);
11524 if (CHIP_REV(bp) == CHIP_REV_Ax)
11525 SET_FLAGS(flags, MODE_E3_A0);
11526 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11527 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11531 SET_FLAGS(flags, MODE_MF);
11532 switch (bp->mf_mode) {
11533 case MULTI_FUNCTION_SD:
11534 SET_FLAGS(flags, MODE_MF_SD);
11536 case MULTI_FUNCTION_SI:
11537 SET_FLAGS(flags, MODE_MF_SI);
11539 case MULTI_FUNCTION_AFEX:
11540 SET_FLAGS(flags, MODE_MF_AFEX);
11544 SET_FLAGS(flags, MODE_SF);
11546 #if defined(__LITTLE_ENDIAN)
11547 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11548 #else /*(__BIG_ENDIAN)*/
11549 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11551 INIT_MODE_FLAGS(bp) = flags;
11554 static int bnx2x_init_bp(struct bnx2x *bp)
11559 mutex_init(&bp->port.phy_mutex);
11560 mutex_init(&bp->fw_mb_mutex);
11561 spin_lock_init(&bp->stats_lock);
11562 sema_init(&bp->stats_sema, 1);
11564 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11565 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11566 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11568 rc = bnx2x_get_hwinfo(bp);
11572 eth_zero_addr(bp->dev->dev_addr);
11575 bnx2x_set_modes_bitmap(bp);
11577 rc = bnx2x_alloc_mem_bp(bp);
11581 bnx2x_read_fwinfo(bp);
11583 func = BP_FUNC(bp);
11585 /* need to reset chip if undi was active */
11586 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11589 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11590 DRV_MSG_SEQ_NUMBER_MASK;
11591 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11593 bnx2x_prev_unload(bp);
11596 if (CHIP_REV_IS_FPGA(bp))
11597 dev_err(&bp->pdev->dev, "FPGA detected\n");
11599 if (BP_NOMCP(bp) && (func == 0))
11600 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11602 bp->disable_tpa = disable_tpa;
11603 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11605 /* Set TPA flags */
11606 if (bp->disable_tpa) {
11607 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11608 bp->dev->features &= ~NETIF_F_LRO;
11610 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11611 bp->dev->features |= NETIF_F_LRO;
11614 if (CHIP_IS_E1(bp))
11615 bp->dropless_fc = 0;
11617 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11621 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11623 bp->rx_ring_size = MAX_RX_AVAIL;
11625 /* make sure that the numbers are in the right granularity */
11626 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11627 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11629 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11631 init_timer(&bp->timer);
11632 bp->timer.expires = jiffies + bp->current_interval;
11633 bp->timer.data = (unsigned long) bp;
11634 bp->timer.function = bnx2x_timer;
11636 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11637 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11638 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11639 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11640 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11641 bnx2x_dcbx_init_params(bp);
11643 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11646 if (CHIP_IS_E1x(bp))
11647 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11649 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11651 /* multiple tx priority */
11654 else if (CHIP_IS_E1x(bp))
11655 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11656 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11657 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11658 else if (CHIP_IS_E3B0(bp))
11659 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11661 BNX2X_ERR("unknown chip %x revision %x\n",
11662 CHIP_NUM(bp), CHIP_REV(bp));
11663 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11665 /* We need at least one default status block for slow-path events,
11666 * second status block for the L2 queue, and a third status block for
11667 * CNIC if supported.
11670 bp->min_msix_vec_cnt = 1;
11671 else if (CNIC_SUPPORT(bp))
11672 bp->min_msix_vec_cnt = 3;
11673 else /* PF w/o cnic */
11674 bp->min_msix_vec_cnt = 2;
11675 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11677 bp->dump_preset_idx = 1;
11682 /****************************************************************************
11683 * General service functions
11684 ****************************************************************************/
11687 * net_device service functions
11690 /* called with rtnl_lock */
11691 static int bnx2x_open(struct net_device *dev)
11693 struct bnx2x *bp = netdev_priv(dev);
11694 bool global = false;
11695 int other_engine = BP_PATH(bp) ? 0 : 1;
11696 bool other_load_status, load_status;
11699 bp->stats_init = true;
11701 netif_carrier_off(dev);
11703 bnx2x_set_power_state(bp, PCI_D0);
11705 /* If parity had happen during the unload, then attentions
11706 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11707 * want the first function loaded on the current engine to
11708 * complete the recovery.
11709 * Parity recovery is only relevant for PF driver.
11712 other_load_status = bnx2x_get_load_status(bp, other_engine);
11713 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11714 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11715 bnx2x_chk_parity_attn(bp, &global, true)) {
11717 /* If there are attentions and they are in a
11718 * global blocks, set the GLOBAL_RESET bit
11719 * regardless whether it will be this function
11720 * that will complete the recovery or not.
11723 bnx2x_set_reset_global(bp);
11725 /* Only the first function on the current
11726 * engine should try to recover in open. In case
11727 * of attentions in global blocks only the first
11728 * in the chip should try to recover.
11730 if ((!load_status &&
11731 (!global || !other_load_status)) &&
11732 bnx2x_trylock_leader_lock(bp) &&
11733 !bnx2x_leader_reset(bp)) {
11734 netdev_info(bp->dev,
11735 "Recovered in open\n");
11739 /* recovery has failed... */
11740 bnx2x_set_power_state(bp, PCI_D3hot);
11741 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11743 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11744 "If you still see this message after a few retries then power cycle is required.\n");
11751 bp->recovery_state = BNX2X_RECOVERY_DONE;
11752 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11755 return bnx2x_open_epilog(bp);
11758 /* called with rtnl_lock */
11759 static int bnx2x_close(struct net_device *dev)
11761 struct bnx2x *bp = netdev_priv(dev);
11763 /* Unload the driver, release IRQs */
11764 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11769 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11770 struct bnx2x_mcast_ramrod_params *p)
11772 int mc_count = netdev_mc_count(bp->dev);
11773 struct bnx2x_mcast_list_elem *mc_mac =
11774 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11775 struct netdev_hw_addr *ha;
11780 INIT_LIST_HEAD(&p->mcast_list);
11782 netdev_for_each_mc_addr(ha, bp->dev) {
11783 mc_mac->mac = bnx2x_mc_addr(ha);
11784 list_add_tail(&mc_mac->link, &p->mcast_list);
11788 p->mcast_list_len = mc_count;
11793 static void bnx2x_free_mcast_macs_list(
11794 struct bnx2x_mcast_ramrod_params *p)
11796 struct bnx2x_mcast_list_elem *mc_mac =
11797 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11805 * bnx2x_set_uc_list - configure a new unicast MACs list.
11807 * @bp: driver handle
11809 * We will use zero (0) as a MAC type for these MACs.
11811 static int bnx2x_set_uc_list(struct bnx2x *bp)
11814 struct net_device *dev = bp->dev;
11815 struct netdev_hw_addr *ha;
11816 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11817 unsigned long ramrod_flags = 0;
11819 /* First schedule a cleanup up of old configuration */
11820 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11822 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11826 netdev_for_each_uc_addr(ha, dev) {
11827 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11828 BNX2X_UC_LIST_MAC, &ramrod_flags);
11829 if (rc == -EEXIST) {
11831 "Failed to schedule ADD operations: %d\n", rc);
11832 /* do not treat adding same MAC as error */
11835 } else if (rc < 0) {
11837 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11843 /* Execute the pending commands */
11844 __set_bit(RAMROD_CONT, &ramrod_flags);
11845 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11846 BNX2X_UC_LIST_MAC, &ramrod_flags);
11849 static int bnx2x_set_mc_list(struct bnx2x *bp)
11851 struct net_device *dev = bp->dev;
11852 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11855 rparam.mcast_obj = &bp->mcast_obj;
11857 /* first, clear all configured multicast MACs */
11858 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11860 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11864 /* then, configure a new MACs list */
11865 if (netdev_mc_count(dev)) {
11866 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11868 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11873 /* Now add the new MACs */
11874 rc = bnx2x_config_mcast(bp, &rparam,
11875 BNX2X_MCAST_CMD_ADD);
11877 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11880 bnx2x_free_mcast_macs_list(&rparam);
11886 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11887 void bnx2x_set_rx_mode(struct net_device *dev)
11889 struct bnx2x *bp = netdev_priv(dev);
11891 if (bp->state != BNX2X_STATE_OPEN) {
11892 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11895 /* Schedule an SP task to handle rest of change */
11896 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
11897 smp_mb__before_clear_bit();
11898 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
11899 smp_mb__after_clear_bit();
11900 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11904 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
11906 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11908 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11910 netif_addr_lock_bh(bp->dev);
11912 if (bp->dev->flags & IFF_PROMISC) {
11913 rx_mode = BNX2X_RX_MODE_PROMISC;
11914 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
11915 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
11917 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11920 /* some multicasts */
11921 if (bnx2x_set_mc_list(bp) < 0)
11922 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11924 /* release bh lock, as bnx2x_set_uc_list might sleep */
11925 netif_addr_unlock_bh(bp->dev);
11926 if (bnx2x_set_uc_list(bp) < 0)
11927 rx_mode = BNX2X_RX_MODE_PROMISC;
11928 netif_addr_lock_bh(bp->dev);
11930 /* configuring mcast to a vf involves sleeping (when we
11931 * wait for the pf's response).
11933 smp_mb__before_clear_bit();
11934 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11935 &bp->sp_rtnl_state);
11936 smp_mb__after_clear_bit();
11937 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11941 bp->rx_mode = rx_mode;
11942 /* handle ISCSI SD mode */
11943 if (IS_MF_ISCSI_SD(bp))
11944 bp->rx_mode = BNX2X_RX_MODE_NONE;
11946 /* Schedule the rx_mode command */
11947 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11948 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11949 netif_addr_unlock_bh(bp->dev);
11954 bnx2x_set_storm_rx_mode(bp);
11955 netif_addr_unlock_bh(bp->dev);
11957 /* VF will need to request the PF to make this change, and so
11958 * the VF needs to release the bottom-half lock prior to the
11959 * request (as it will likely require sleep on the VF side)
11961 netif_addr_unlock_bh(bp->dev);
11962 bnx2x_vfpf_storm_rx_mode(bp);
11966 /* called with rtnl_lock */
11967 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11968 int devad, u16 addr)
11970 struct bnx2x *bp = netdev_priv(netdev);
11974 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11975 prtad, devad, addr);
11977 /* The HW expects different devad if CL22 is used */
11978 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11980 bnx2x_acquire_phy_lock(bp);
11981 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11982 bnx2x_release_phy_lock(bp);
11983 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11990 /* called with rtnl_lock */
11991 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11992 u16 addr, u16 value)
11994 struct bnx2x *bp = netdev_priv(netdev);
11998 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11999 prtad, devad, addr, value);
12001 /* The HW expects different devad if CL22 is used */
12002 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12004 bnx2x_acquire_phy_lock(bp);
12005 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12006 bnx2x_release_phy_lock(bp);
12010 /* called with rtnl_lock */
12011 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12013 struct bnx2x *bp = netdev_priv(dev);
12014 struct mii_ioctl_data *mdio = if_mii(ifr);
12016 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12017 mdio->phy_id, mdio->reg_num, mdio->val_in);
12019 if (!netif_running(dev))
12022 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12025 #ifdef CONFIG_NET_POLL_CONTROLLER
12026 static void poll_bnx2x(struct net_device *dev)
12028 struct bnx2x *bp = netdev_priv(dev);
12031 for_each_eth_queue(bp, i) {
12032 struct bnx2x_fastpath *fp = &bp->fp[i];
12033 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12038 static int bnx2x_validate_addr(struct net_device *dev)
12040 struct bnx2x *bp = netdev_priv(dev);
12042 /* query the bulletin board for mac address configured by the PF */
12044 bnx2x_sample_bulletin(bp);
12046 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12047 BNX2X_ERR("Non-valid Ethernet address\n");
12048 return -EADDRNOTAVAIL;
12053 static const struct net_device_ops bnx2x_netdev_ops = {
12054 .ndo_open = bnx2x_open,
12055 .ndo_stop = bnx2x_close,
12056 .ndo_start_xmit = bnx2x_start_xmit,
12057 .ndo_select_queue = bnx2x_select_queue,
12058 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12059 .ndo_set_mac_address = bnx2x_change_mac_addr,
12060 .ndo_validate_addr = bnx2x_validate_addr,
12061 .ndo_do_ioctl = bnx2x_ioctl,
12062 .ndo_change_mtu = bnx2x_change_mtu,
12063 .ndo_fix_features = bnx2x_fix_features,
12064 .ndo_set_features = bnx2x_set_features,
12065 .ndo_tx_timeout = bnx2x_tx_timeout,
12066 #ifdef CONFIG_NET_POLL_CONTROLLER
12067 .ndo_poll_controller = poll_bnx2x,
12069 .ndo_setup_tc = bnx2x_setup_tc,
12070 #ifdef CONFIG_BNX2X_SRIOV
12071 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12072 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12073 .ndo_get_vf_config = bnx2x_get_vf_config,
12075 #ifdef NETDEV_FCOE_WWNN
12076 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12079 #ifdef CONFIG_NET_RX_BUSY_POLL
12080 .ndo_busy_poll = bnx2x_low_latency_recv,
12084 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12086 struct device *dev = &bp->pdev->dev;
12088 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12089 bp->flags |= USING_DAC_FLAG;
12090 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12091 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12094 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12095 dev_err(dev, "System does not support DMA, aborting\n");
12102 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12103 struct net_device *dev, unsigned long board_type)
12107 bool chip_is_e1x = (board_type == BCM57710 ||
12108 board_type == BCM57711 ||
12109 board_type == BCM57711E);
12111 SET_NETDEV_DEV(dev, &pdev->dev);
12116 rc = pci_enable_device(pdev);
12118 dev_err(&bp->pdev->dev,
12119 "Cannot enable PCI device, aborting\n");
12123 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12124 dev_err(&bp->pdev->dev,
12125 "Cannot find PCI device base address, aborting\n");
12127 goto err_out_disable;
12130 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12131 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12133 goto err_out_disable;
12136 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12137 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12138 PCICFG_REVESION_ID_ERROR_VAL) {
12139 pr_err("PCI device error, probably due to fan failure, aborting\n");
12141 goto err_out_disable;
12144 if (atomic_read(&pdev->enable_cnt) == 1) {
12145 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12147 dev_err(&bp->pdev->dev,
12148 "Cannot obtain PCI resources, aborting\n");
12149 goto err_out_disable;
12152 pci_set_master(pdev);
12153 pci_save_state(pdev);
12157 bp->pm_cap = pdev->pm_cap;
12158 if (bp->pm_cap == 0) {
12159 dev_err(&bp->pdev->dev,
12160 "Cannot find power management capability, aborting\n");
12162 goto err_out_release;
12166 if (!pci_is_pcie(pdev)) {
12167 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12169 goto err_out_release;
12172 rc = bnx2x_set_coherency_mask(bp);
12174 goto err_out_release;
12176 dev->mem_start = pci_resource_start(pdev, 0);
12177 dev->base_addr = dev->mem_start;
12178 dev->mem_end = pci_resource_end(pdev, 0);
12180 dev->irq = pdev->irq;
12182 bp->regview = pci_ioremap_bar(pdev, 0);
12183 if (!bp->regview) {
12184 dev_err(&bp->pdev->dev,
12185 "Cannot map register space, aborting\n");
12187 goto err_out_release;
12190 /* In E1/E1H use pci device function given by kernel.
12191 * In E2/E3 read physical function from ME register since these chips
12192 * support Physical Device Assignment where kernel BDF maybe arbitrary
12193 * (depending on hypervisor).
12196 bp->pf_num = PCI_FUNC(pdev->devfn);
12199 pci_read_config_dword(bp->pdev,
12200 PCICFG_ME_REGISTER, &pci_cfg_dword);
12201 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12202 ME_REG_ABS_PF_NUM_SHIFT);
12204 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12206 /* clean indirect addresses */
12207 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12208 PCICFG_VENDOR_ID_OFFSET);
12210 * Clean the following indirect addresses for all functions since it
12211 * is not used by the driver.
12214 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12215 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12216 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12217 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12220 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12221 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12222 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12223 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12226 /* Enable internal target-read (in case we are probed after PF
12227 * FLR). Must be done prior to any BAR read access. Only for
12232 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12235 dev->watchdog_timeo = TX_TIMEOUT;
12237 dev->netdev_ops = &bnx2x_netdev_ops;
12238 bnx2x_set_ethtool_ops(bp, dev);
12240 dev->priv_flags |= IFF_UNICAST_FLT;
12242 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12243 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12244 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12245 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12246 if (!CHIP_IS_E1x(bp)) {
12247 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12248 dev->hw_enc_features =
12249 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12250 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12251 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12254 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12255 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12257 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12258 if (bp->flags & USING_DAC_FLAG)
12259 dev->features |= NETIF_F_HIGHDMA;
12261 /* Add Loopback capability to the device */
12262 dev->hw_features |= NETIF_F_LOOPBACK;
12265 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12268 /* get_port_hwinfo() will set prtad and mmds properly */
12269 bp->mdio.prtad = MDIO_PRTAD_NONE;
12271 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12272 bp->mdio.dev = dev;
12273 bp->mdio.mdio_read = bnx2x_mdio_read;
12274 bp->mdio.mdio_write = bnx2x_mdio_write;
12279 if (atomic_read(&pdev->enable_cnt) == 1)
12280 pci_release_regions(pdev);
12283 pci_disable_device(pdev);
12284 pci_set_drvdata(pdev, NULL);
12290 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12291 enum bnx2x_pci_bus_speed *speed)
12293 u32 link_speed, val = 0;
12295 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12296 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12298 link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12300 switch (link_speed) {
12302 *speed = BNX2X_PCI_LINK_SPEED_8000;
12305 *speed = BNX2X_PCI_LINK_SPEED_5000;
12308 *speed = BNX2X_PCI_LINK_SPEED_2500;
12312 static int bnx2x_check_firmware(struct bnx2x *bp)
12314 const struct firmware *firmware = bp->firmware;
12315 struct bnx2x_fw_file_hdr *fw_hdr;
12316 struct bnx2x_fw_file_section *sections;
12317 u32 offset, len, num_ops;
12318 __be16 *ops_offsets;
12322 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12323 BNX2X_ERR("Wrong FW size\n");
12327 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12328 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12330 /* Make sure none of the offsets and sizes make us read beyond
12331 * the end of the firmware data */
12332 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12333 offset = be32_to_cpu(sections[i].offset);
12334 len = be32_to_cpu(sections[i].len);
12335 if (offset + len > firmware->size) {
12336 BNX2X_ERR("Section %d length is out of bounds\n", i);
12341 /* Likewise for the init_ops offsets */
12342 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12343 ops_offsets = (__force __be16 *)(firmware->data + offset);
12344 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12346 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12347 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12348 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12353 /* Check FW version */
12354 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12355 fw_ver = firmware->data + offset;
12356 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12357 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12358 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12359 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12360 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12361 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12362 BCM_5710_FW_MAJOR_VERSION,
12363 BCM_5710_FW_MINOR_VERSION,
12364 BCM_5710_FW_REVISION_VERSION,
12365 BCM_5710_FW_ENGINEERING_VERSION);
12372 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12374 const __be32 *source = (const __be32 *)_source;
12375 u32 *target = (u32 *)_target;
12378 for (i = 0; i < n/4; i++)
12379 target[i] = be32_to_cpu(source[i]);
12383 Ops array is stored in the following format:
12384 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12386 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12388 const __be32 *source = (const __be32 *)_source;
12389 struct raw_op *target = (struct raw_op *)_target;
12392 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12393 tmp = be32_to_cpu(source[j]);
12394 target[i].op = (tmp >> 24) & 0xff;
12395 target[i].offset = tmp & 0xffffff;
12396 target[i].raw_data = be32_to_cpu(source[j + 1]);
12400 /* IRO array is stored in the following format:
12401 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12403 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12405 const __be32 *source = (const __be32 *)_source;
12406 struct iro *target = (struct iro *)_target;
12409 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12410 target[i].base = be32_to_cpu(source[j]);
12412 tmp = be32_to_cpu(source[j]);
12413 target[i].m1 = (tmp >> 16) & 0xffff;
12414 target[i].m2 = tmp & 0xffff;
12416 tmp = be32_to_cpu(source[j]);
12417 target[i].m3 = (tmp >> 16) & 0xffff;
12418 target[i].size = tmp & 0xffff;
12423 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12425 const __be16 *source = (const __be16 *)_source;
12426 u16 *target = (u16 *)_target;
12429 for (i = 0; i < n/2; i++)
12430 target[i] = be16_to_cpu(source[i]);
12433 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12435 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12436 bp->arr = kmalloc(len, GFP_KERNEL); \
12439 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12440 (u8 *)bp->arr, len); \
12443 static int bnx2x_init_firmware(struct bnx2x *bp)
12445 const char *fw_file_name;
12446 struct bnx2x_fw_file_hdr *fw_hdr;
12452 if (CHIP_IS_E1(bp))
12453 fw_file_name = FW_FILE_NAME_E1;
12454 else if (CHIP_IS_E1H(bp))
12455 fw_file_name = FW_FILE_NAME_E1H;
12456 else if (!CHIP_IS_E1x(bp))
12457 fw_file_name = FW_FILE_NAME_E2;
12459 BNX2X_ERR("Unsupported chip revision\n");
12462 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12464 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12466 BNX2X_ERR("Can't load firmware file %s\n",
12468 goto request_firmware_exit;
12471 rc = bnx2x_check_firmware(bp);
12473 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12474 goto request_firmware_exit;
12477 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12479 /* Initialize the pointers to the init arrays */
12481 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12484 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12487 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12490 /* STORMs firmware */
12491 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12492 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12493 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12494 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12495 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12496 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12497 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12498 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12499 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12500 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12501 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12502 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12503 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12504 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12505 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12506 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12508 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12513 kfree(bp->init_ops_offsets);
12514 init_offsets_alloc_err:
12515 kfree(bp->init_ops);
12516 init_ops_alloc_err:
12517 kfree(bp->init_data);
12518 request_firmware_exit:
12519 release_firmware(bp->firmware);
12520 bp->firmware = NULL;
12525 static void bnx2x_release_firmware(struct bnx2x *bp)
12527 kfree(bp->init_ops_offsets);
12528 kfree(bp->init_ops);
12529 kfree(bp->init_data);
12530 release_firmware(bp->firmware);
12531 bp->firmware = NULL;
12534 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12535 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12536 .init_hw_cmn = bnx2x_init_hw_common,
12537 .init_hw_port = bnx2x_init_hw_port,
12538 .init_hw_func = bnx2x_init_hw_func,
12540 .reset_hw_cmn = bnx2x_reset_common,
12541 .reset_hw_port = bnx2x_reset_port,
12542 .reset_hw_func = bnx2x_reset_func,
12544 .gunzip_init = bnx2x_gunzip_init,
12545 .gunzip_end = bnx2x_gunzip_end,
12547 .init_fw = bnx2x_init_firmware,
12548 .release_fw = bnx2x_release_firmware,
12551 void bnx2x__init_func_obj(struct bnx2x *bp)
12553 /* Prepare DMAE related driver resources */
12554 bnx2x_setup_dmae(bp);
12556 bnx2x_init_func_obj(bp, &bp->func_obj,
12557 bnx2x_sp(bp, func_rdata),
12558 bnx2x_sp_mapping(bp, func_rdata),
12559 bnx2x_sp(bp, func_afex_rdata),
12560 bnx2x_sp_mapping(bp, func_afex_rdata),
12561 &bnx2x_func_sp_drv);
12564 /* must be called after sriov-enable */
12565 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12567 int cid_count = BNX2X_L2_MAX_CID(bp);
12570 cid_count += BNX2X_VF_CIDS;
12572 if (CNIC_SUPPORT(bp))
12573 cid_count += CNIC_CID_MAX;
12575 return roundup(cid_count, QM_CID_ROUND);
12579 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12584 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12590 * If MSI-X is not supported - return number of SBs needed to support
12591 * one fast path queue: one FP queue + SB for CNIC
12593 if (!pdev->msix_cap) {
12594 dev_info(&pdev->dev, "no msix capability found\n");
12595 return 1 + cnic_cnt;
12597 dev_info(&pdev->dev, "msix capability found\n");
12600 * The value in the PCI configuration space is the index of the last
12601 * entry, namely one less than the actual size of the table, which is
12602 * exactly what we want to return from this function: number of all SBs
12603 * without the default SB.
12604 * For VFs there is no default SB, then we return (index+1).
12606 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12608 index = control & PCI_MSIX_FLAGS_QSIZE;
12613 static int set_max_cos_est(int chip_id)
12619 return BNX2X_MULTI_TX_COS_E1X;
12623 return BNX2X_MULTI_TX_COS_E2_E3A0;
12629 case BCM57840_4_10:
12630 case BCM57840_2_20:
12639 return BNX2X_MULTI_TX_COS_E3B0;
12642 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12647 static int set_is_vf(int chip_id)
12661 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12663 static int bnx2x_init_one(struct pci_dev *pdev,
12664 const struct pci_device_id *ent)
12666 struct net_device *dev = NULL;
12669 enum bnx2x_pci_bus_speed pcie_speed;
12670 int rc, max_non_def_sbs;
12671 int rx_count, tx_count, rss_count, doorbell_size;
12676 /* An estimated maximum supported CoS number according to the chip
12678 * We will try to roughly estimate the maximum number of CoSes this chip
12679 * may support in order to minimize the memory allocated for Tx
12680 * netdev_queue's. This number will be accurately calculated during the
12681 * initialization of bp->max_cos based on the chip versions AND chip
12682 * revision in the bnx2x_init_bp().
12684 max_cos_est = set_max_cos_est(ent->driver_data);
12685 if (max_cos_est < 0)
12686 return max_cos_est;
12687 is_vf = set_is_vf(ent->driver_data);
12688 cnic_cnt = is_vf ? 0 : 1;
12690 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12692 /* add another SB for VF as it has no default SB */
12693 max_non_def_sbs += is_vf ? 1 : 0;
12695 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12696 rss_count = max_non_def_sbs - cnic_cnt;
12701 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12702 rx_count = rss_count + cnic_cnt;
12704 /* Maximum number of netdev Tx queues:
12705 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12707 tx_count = rss_count * max_cos_est + cnic_cnt;
12709 /* dev zeroed in init_etherdev */
12710 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12714 bp = netdev_priv(dev);
12718 bp->flags |= IS_VF_FLAG;
12720 bp->igu_sb_cnt = max_non_def_sbs;
12721 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12722 bp->msg_enable = debug;
12723 bp->cnic_support = cnic_cnt;
12724 bp->cnic_probe = bnx2x_cnic_probe;
12726 pci_set_drvdata(pdev, dev);
12728 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12734 BNX2X_DEV_INFO("This is a %s function\n",
12735 IS_PF(bp) ? "physical" : "virtual");
12736 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12737 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12738 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12739 tx_count, rx_count);
12741 rc = bnx2x_init_bp(bp);
12743 goto init_one_exit;
12745 /* Map doorbells here as we need the real value of bp->max_cos which
12746 * is initialized in bnx2x_init_bp() to determine the number of
12750 bp->doorbells = bnx2x_vf_doorbells(bp);
12751 rc = bnx2x_vf_pci_alloc(bp);
12753 goto init_one_exit;
12755 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12756 if (doorbell_size > pci_resource_len(pdev, 2)) {
12757 dev_err(&bp->pdev->dev,
12758 "Cannot map doorbells, bar size too small, aborting\n");
12760 goto init_one_exit;
12762 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12765 if (!bp->doorbells) {
12766 dev_err(&bp->pdev->dev,
12767 "Cannot map doorbell space, aborting\n");
12769 goto init_one_exit;
12773 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12775 goto init_one_exit;
12778 /* Enable SRIOV if capability found in configuration space */
12779 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12781 goto init_one_exit;
12783 /* calc qm_cid_count */
12784 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12785 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12787 /* disable FCOE L2 queue for E1x*/
12788 if (CHIP_IS_E1x(bp))
12789 bp->flags |= NO_FCOE_FLAG;
12791 /* Set bp->num_queues for MSI-X mode*/
12792 bnx2x_set_num_queues(bp);
12794 /* Configure interrupt mode: try to enable MSI-X/MSI if
12797 rc = bnx2x_set_int_mode(bp);
12799 dev_err(&pdev->dev, "Cannot set interrupts\n");
12800 goto init_one_exit;
12802 BNX2X_DEV_INFO("set interrupts successfully\n");
12804 /* register the net device */
12805 rc = register_netdev(dev);
12807 dev_err(&pdev->dev, "Cannot register net device\n");
12808 goto init_one_exit;
12810 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12812 if (!NO_FCOE(bp)) {
12813 /* Add storage MAC address */
12815 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12819 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12820 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12821 pcie_width, pcie_speed);
12823 BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12824 board_info[ent->driver_data].name,
12825 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12827 pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12828 pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12829 pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12831 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12837 iounmap(bp->regview);
12839 if (IS_PF(bp) && bp->doorbells)
12840 iounmap(bp->doorbells);
12844 if (atomic_read(&pdev->enable_cnt) == 1)
12845 pci_release_regions(pdev);
12847 pci_disable_device(pdev);
12848 pci_set_drvdata(pdev, NULL);
12853 static void __bnx2x_remove(struct pci_dev *pdev,
12854 struct net_device *dev,
12856 bool remove_netdev)
12858 /* Delete storage MAC address */
12859 if (!NO_FCOE(bp)) {
12861 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12866 /* Delete app tlvs from dcbnl */
12867 bnx2x_dcbnl_update_applist(bp, true);
12872 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12873 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12875 /* Close the interface - either directly or implicitly */
12876 if (remove_netdev) {
12877 unregister_netdev(dev);
12884 bnx2x_iov_remove_one(bp);
12886 /* Power on: we can't let PCI layer write to us while we are in D3 */
12888 bnx2x_set_power_state(bp, PCI_D0);
12890 /* Disable MSI/MSI-X */
12891 bnx2x_disable_msi(bp);
12895 bnx2x_set_power_state(bp, PCI_D3hot);
12897 /* Make sure RESET task is not scheduled before continuing */
12898 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12900 /* send message via vfpf channel to release the resources of this vf */
12902 bnx2x_vfpf_release(bp);
12904 /* Assumes no further PCIe PM changes will occur */
12905 if (system_state == SYSTEM_POWER_OFF) {
12906 pci_wake_from_d3(pdev, bp->wol);
12907 pci_set_power_state(pdev, PCI_D3hot);
12911 iounmap(bp->regview);
12913 /* for vf doorbells are part of the regview and were unmapped along with
12914 * it. FW is only loaded by PF.
12918 iounmap(bp->doorbells);
12920 bnx2x_release_firmware(bp);
12922 bnx2x_free_mem_bp(bp);
12927 if (atomic_read(&pdev->enable_cnt) == 1)
12928 pci_release_regions(pdev);
12930 pci_disable_device(pdev);
12931 pci_set_drvdata(pdev, NULL);
12934 static void bnx2x_remove_one(struct pci_dev *pdev)
12936 struct net_device *dev = pci_get_drvdata(pdev);
12940 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12943 bp = netdev_priv(dev);
12945 __bnx2x_remove(pdev, dev, bp, true);
12948 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12950 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12952 bp->rx_mode = BNX2X_RX_MODE_NONE;
12954 if (CNIC_LOADED(bp))
12955 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12958 bnx2x_tx_disable(bp);
12959 /* Delete all NAPI objects */
12960 bnx2x_del_all_napi(bp);
12961 if (CNIC_LOADED(bp))
12962 bnx2x_del_all_napi_cnic(bp);
12963 netdev_reset_tc(bp->dev);
12965 del_timer_sync(&bp->timer);
12966 cancel_delayed_work(&bp->sp_task);
12967 cancel_delayed_work(&bp->period_task);
12969 spin_lock_bh(&bp->stats_lock);
12970 bp->stats_state = STATS_STATE_DISABLED;
12971 spin_unlock_bh(&bp->stats_lock);
12973 bnx2x_save_statistics(bp);
12975 netif_carrier_off(bp->dev);
12981 * bnx2x_io_error_detected - called when PCI error is detected
12982 * @pdev: Pointer to PCI device
12983 * @state: The current pci connection state
12985 * This function is called after a PCI bus error affecting
12986 * this device has been detected.
12988 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12989 pci_channel_state_t state)
12991 struct net_device *dev = pci_get_drvdata(pdev);
12992 struct bnx2x *bp = netdev_priv(dev);
12996 BNX2X_ERR("IO error detected\n");
12998 netif_device_detach(dev);
13000 if (state == pci_channel_io_perm_failure) {
13002 return PCI_ERS_RESULT_DISCONNECT;
13005 if (netif_running(dev))
13006 bnx2x_eeh_nic_unload(bp);
13008 bnx2x_prev_path_mark_eeh(bp);
13010 pci_disable_device(pdev);
13014 /* Request a slot reset */
13015 return PCI_ERS_RESULT_NEED_RESET;
13019 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13020 * @pdev: Pointer to PCI device
13022 * Restart the card from scratch, as if from a cold-boot.
13024 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13026 struct net_device *dev = pci_get_drvdata(pdev);
13027 struct bnx2x *bp = netdev_priv(dev);
13031 BNX2X_ERR("IO slot reset initializing...\n");
13032 if (pci_enable_device(pdev)) {
13033 dev_err(&pdev->dev,
13034 "Cannot re-enable PCI device after reset\n");
13036 return PCI_ERS_RESULT_DISCONNECT;
13039 pci_set_master(pdev);
13040 pci_restore_state(pdev);
13041 pci_save_state(pdev);
13043 if (netif_running(dev))
13044 bnx2x_set_power_state(bp, PCI_D0);
13046 if (netif_running(dev)) {
13047 BNX2X_ERR("IO slot reset --> driver unload\n");
13049 /* MCP should have been reset; Need to wait for validity */
13050 bnx2x_init_shmem(bp);
13052 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13056 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13057 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13058 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13060 bnx2x_drain_tx_queues(bp);
13061 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13062 bnx2x_netif_stop(bp, 1);
13063 bnx2x_free_irq(bp);
13065 /* Report UNLOAD_DONE to MCP */
13066 bnx2x_send_unload_done(bp, true);
13071 bnx2x_prev_unload(bp);
13073 /* We should have reseted the engine, so It's fair to
13074 * assume the FW will no longer write to the bnx2x driver.
13076 bnx2x_squeeze_objects(bp);
13077 bnx2x_free_skbs(bp);
13078 for_each_rx_queue(bp, i)
13079 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13080 bnx2x_free_fp_mem(bp);
13081 bnx2x_free_mem(bp);
13083 bp->state = BNX2X_STATE_CLOSED;
13088 return PCI_ERS_RESULT_RECOVERED;
13092 * bnx2x_io_resume - called when traffic can start flowing again
13093 * @pdev: Pointer to PCI device
13095 * This callback is called when the error recovery driver tells us that
13096 * its OK to resume normal operation.
13098 static void bnx2x_io_resume(struct pci_dev *pdev)
13100 struct net_device *dev = pci_get_drvdata(pdev);
13101 struct bnx2x *bp = netdev_priv(dev);
13103 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13104 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13110 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13111 DRV_MSG_SEQ_NUMBER_MASK;
13113 if (netif_running(dev))
13114 bnx2x_nic_load(bp, LOAD_NORMAL);
13116 netif_device_attach(dev);
13121 static const struct pci_error_handlers bnx2x_err_handler = {
13122 .error_detected = bnx2x_io_error_detected,
13123 .slot_reset = bnx2x_io_slot_reset,
13124 .resume = bnx2x_io_resume,
13127 static void bnx2x_shutdown(struct pci_dev *pdev)
13129 struct net_device *dev = pci_get_drvdata(pdev);
13135 bp = netdev_priv(dev);
13140 netif_device_detach(dev);
13143 /* Don't remove the netdevice, as there are scenarios which will cause
13144 * the kernel to hang, e.g., when trying to remove bnx2i while the
13145 * rootfs is mounted from SAN.
13147 __bnx2x_remove(pdev, dev, bp, false);
13150 static struct pci_driver bnx2x_pci_driver = {
13151 .name = DRV_MODULE_NAME,
13152 .id_table = bnx2x_pci_tbl,
13153 .probe = bnx2x_init_one,
13154 .remove = bnx2x_remove_one,
13155 .suspend = bnx2x_suspend,
13156 .resume = bnx2x_resume,
13157 .err_handler = &bnx2x_err_handler,
13158 #ifdef CONFIG_BNX2X_SRIOV
13159 .sriov_configure = bnx2x_sriov_configure,
13161 .shutdown = bnx2x_shutdown,
13164 static int __init bnx2x_init(void)
13168 pr_info("%s", version);
13170 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13171 if (bnx2x_wq == NULL) {
13172 pr_err("Cannot create workqueue\n");
13176 ret = pci_register_driver(&bnx2x_pci_driver);
13178 pr_err("Cannot register driver\n");
13179 destroy_workqueue(bnx2x_wq);
13184 static void __exit bnx2x_cleanup(void)
13186 struct list_head *pos, *q;
13188 pci_unregister_driver(&bnx2x_pci_driver);
13190 destroy_workqueue(bnx2x_wq);
13192 /* Free globally allocated resources */
13193 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13194 struct bnx2x_prev_path_list *tmp =
13195 list_entry(pos, struct bnx2x_prev_path_list, list);
13201 void bnx2x_notify_link_changed(struct bnx2x *bp)
13203 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13206 module_init(bnx2x_init);
13207 module_exit(bnx2x_cleanup);
13210 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13212 * @bp: driver handle
13213 * @set: set or clear the CAM entry
13215 * This function will wait until the ramrod completion returns.
13216 * Return 0 if success, -ENODEV if ramrod doesn't return.
13218 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13220 unsigned long ramrod_flags = 0;
13222 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13223 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13224 &bp->iscsi_l2_mac_obj, true,
13225 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13228 /* count denotes the number of new completions we have seen */
13229 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13231 struct eth_spe *spe;
13232 int cxt_index, cxt_offset;
13234 #ifdef BNX2X_STOP_ON_ERROR
13235 if (unlikely(bp->panic))
13239 spin_lock_bh(&bp->spq_lock);
13240 BUG_ON(bp->cnic_spq_pending < count);
13241 bp->cnic_spq_pending -= count;
13243 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13244 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13245 & SPE_HDR_CONN_TYPE) >>
13246 SPE_HDR_CONN_TYPE_SHIFT;
13247 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13248 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13250 /* Set validation for iSCSI L2 client before sending SETUP
13253 if (type == ETH_CONNECTION_TYPE) {
13254 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13255 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13257 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13258 (cxt_index * ILT_PAGE_CIDS);
13259 bnx2x_set_ctx_validation(bp,
13260 &bp->context[cxt_index].
13261 vcxt[cxt_offset].eth,
13262 BNX2X_ISCSI_ETH_CID(bp));
13267 * There may be not more than 8 L2, not more than 8 L5 SPEs
13268 * and in the air. We also check that number of outstanding
13269 * COMMON ramrods is not more than the EQ and SPQ can
13272 if (type == ETH_CONNECTION_TYPE) {
13273 if (!atomic_read(&bp->cq_spq_left))
13276 atomic_dec(&bp->cq_spq_left);
13277 } else if (type == NONE_CONNECTION_TYPE) {
13278 if (!atomic_read(&bp->eq_spq_left))
13281 atomic_dec(&bp->eq_spq_left);
13282 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13283 (type == FCOE_CONNECTION_TYPE)) {
13284 if (bp->cnic_spq_pending >=
13285 bp->cnic_eth_dev.max_kwqe_pending)
13288 bp->cnic_spq_pending++;
13290 BNX2X_ERR("Unknown SPE type: %d\n", type);
13295 spe = bnx2x_sp_get_next(bp);
13296 *spe = *bp->cnic_kwq_cons;
13298 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13299 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13301 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13302 bp->cnic_kwq_cons = bp->cnic_kwq;
13304 bp->cnic_kwq_cons++;
13306 bnx2x_sp_prod_update(bp);
13307 spin_unlock_bh(&bp->spq_lock);
13310 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13311 struct kwqe_16 *kwqes[], u32 count)
13313 struct bnx2x *bp = netdev_priv(dev);
13316 #ifdef BNX2X_STOP_ON_ERROR
13317 if (unlikely(bp->panic)) {
13318 BNX2X_ERR("Can't post to SP queue while panic\n");
13323 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13324 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13325 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13329 spin_lock_bh(&bp->spq_lock);
13331 for (i = 0; i < count; i++) {
13332 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13334 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13337 *bp->cnic_kwq_prod = *spe;
13339 bp->cnic_kwq_pending++;
13341 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13342 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13343 spe->data.update_data_addr.hi,
13344 spe->data.update_data_addr.lo,
13345 bp->cnic_kwq_pending);
13347 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13348 bp->cnic_kwq_prod = bp->cnic_kwq;
13350 bp->cnic_kwq_prod++;
13353 spin_unlock_bh(&bp->spq_lock);
13355 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13356 bnx2x_cnic_sp_post(bp, 0);
13361 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13363 struct cnic_ops *c_ops;
13366 mutex_lock(&bp->cnic_mutex);
13367 c_ops = rcu_dereference_protected(bp->cnic_ops,
13368 lockdep_is_held(&bp->cnic_mutex));
13370 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13371 mutex_unlock(&bp->cnic_mutex);
13376 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13378 struct cnic_ops *c_ops;
13382 c_ops = rcu_dereference(bp->cnic_ops);
13384 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13391 * for commands that have no data
13393 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13395 struct cnic_ctl_info ctl = {0};
13399 return bnx2x_cnic_ctl_send(bp, &ctl);
13402 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13404 struct cnic_ctl_info ctl = {0};
13406 /* first we tell CNIC and only then we count this as a completion */
13407 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13408 ctl.data.comp.cid = cid;
13409 ctl.data.comp.error = err;
13411 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13412 bnx2x_cnic_sp_post(bp, 0);
13415 /* Called with netif_addr_lock_bh() taken.
13416 * Sets an rx_mode config for an iSCSI ETH client.
13418 * Completion should be checked outside.
13420 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13422 unsigned long accept_flags = 0, ramrod_flags = 0;
13423 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13424 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13427 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13428 * because it's the only way for UIO Queue to accept
13429 * multicasts (in non-promiscuous mode only one Queue per
13430 * function will receive multicast packets (leading in our
13433 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13434 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13435 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13436 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13438 /* Clear STOP_PENDING bit if START is requested */
13439 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13441 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13443 /* Clear START_PENDING bit if STOP is requested */
13444 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13446 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13447 set_bit(sched_state, &bp->sp_state);
13449 __set_bit(RAMROD_RX, &ramrod_flags);
13450 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13455 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13457 struct bnx2x *bp = netdev_priv(dev);
13460 switch (ctl->cmd) {
13461 case DRV_CTL_CTXTBL_WR_CMD: {
13462 u32 index = ctl->data.io.offset;
13463 dma_addr_t addr = ctl->data.io.dma_addr;
13465 bnx2x_ilt_wr(bp, index, addr);
13469 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13470 int count = ctl->data.credit.credit_count;
13472 bnx2x_cnic_sp_post(bp, count);
13476 /* rtnl_lock is held. */
13477 case DRV_CTL_START_L2_CMD: {
13478 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13479 unsigned long sp_bits = 0;
13481 /* Configure the iSCSI classification object */
13482 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13483 cp->iscsi_l2_client_id,
13484 cp->iscsi_l2_cid, BP_FUNC(bp),
13485 bnx2x_sp(bp, mac_rdata),
13486 bnx2x_sp_mapping(bp, mac_rdata),
13487 BNX2X_FILTER_MAC_PENDING,
13488 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13491 /* Set iSCSI MAC address */
13492 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13499 /* Start accepting on iSCSI L2 ring */
13501 netif_addr_lock_bh(dev);
13502 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13503 netif_addr_unlock_bh(dev);
13505 /* bits to wait on */
13506 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13507 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13509 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13510 BNX2X_ERR("rx_mode completion timed out!\n");
13515 /* rtnl_lock is held. */
13516 case DRV_CTL_STOP_L2_CMD: {
13517 unsigned long sp_bits = 0;
13519 /* Stop accepting on iSCSI L2 ring */
13520 netif_addr_lock_bh(dev);
13521 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13522 netif_addr_unlock_bh(dev);
13524 /* bits to wait on */
13525 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13526 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13528 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13529 BNX2X_ERR("rx_mode completion timed out!\n");
13534 /* Unset iSCSI L2 MAC */
13535 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13536 BNX2X_ISCSI_ETH_MAC, true);
13539 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13540 int count = ctl->data.credit.credit_count;
13542 smp_mb__before_atomic_inc();
13543 atomic_add(count, &bp->cq_spq_left);
13544 smp_mb__after_atomic_inc();
13547 case DRV_CTL_ULP_REGISTER_CMD: {
13548 int ulp_type = ctl->data.register_data.ulp_type;
13550 if (CHIP_IS_E3(bp)) {
13551 int idx = BP_FW_MB_IDX(bp);
13552 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13553 int path = BP_PATH(bp);
13554 int port = BP_PORT(bp);
13556 u32 scratch_offset;
13559 /* first write capability to shmem2 */
13560 if (ulp_type == CNIC_ULP_ISCSI)
13561 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13562 else if (ulp_type == CNIC_ULP_FCOE)
13563 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13564 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13566 if ((ulp_type != CNIC_ULP_FCOE) ||
13567 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13568 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13571 /* if reached here - should write fcoe capabilities */
13572 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13573 if (!scratch_offset)
13575 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13576 fcoe_features[path][port]);
13577 host_addr = (u32 *) &(ctl->data.register_data.
13579 for (i = 0; i < sizeof(struct fcoe_capabilities);
13581 REG_WR(bp, scratch_offset + i,
13582 *(host_addr + i/4));
13587 case DRV_CTL_ULP_UNREGISTER_CMD: {
13588 int ulp_type = ctl->data.ulp_type;
13590 if (CHIP_IS_E3(bp)) {
13591 int idx = BP_FW_MB_IDX(bp);
13594 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13595 if (ulp_type == CNIC_ULP_ISCSI)
13596 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13597 else if (ulp_type == CNIC_ULP_FCOE)
13598 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13599 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13605 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13612 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13614 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13616 if (bp->flags & USING_MSIX_FLAG) {
13617 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13618 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13619 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13621 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13622 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13624 if (!CHIP_IS_E1x(bp))
13625 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13627 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13629 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13630 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13631 cp->irq_arr[1].status_blk = bp->def_status_blk;
13632 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13633 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13638 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13640 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13642 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13643 bnx2x_cid_ilt_lines(bp);
13644 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13645 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13646 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13648 if (NO_ISCSI_OOO(bp))
13649 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13652 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13655 struct bnx2x *bp = netdev_priv(dev);
13656 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13659 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13662 BNX2X_ERR("NULL ops received\n");
13666 if (!CNIC_SUPPORT(bp)) {
13667 BNX2X_ERR("Can't register CNIC when not supported\n");
13668 return -EOPNOTSUPP;
13671 if (!CNIC_LOADED(bp)) {
13672 rc = bnx2x_load_cnic(bp);
13674 BNX2X_ERR("CNIC-related load failed\n");
13679 bp->cnic_enabled = true;
13681 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13685 bp->cnic_kwq_cons = bp->cnic_kwq;
13686 bp->cnic_kwq_prod = bp->cnic_kwq;
13687 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13689 bp->cnic_spq_pending = 0;
13690 bp->cnic_kwq_pending = 0;
13692 bp->cnic_data = data;
13695 cp->drv_state |= CNIC_DRV_STATE_REGD;
13696 cp->iro_arr = bp->iro_arr;
13698 bnx2x_setup_cnic_irq_info(bp);
13700 rcu_assign_pointer(bp->cnic_ops, ops);
13705 static int bnx2x_unregister_cnic(struct net_device *dev)
13707 struct bnx2x *bp = netdev_priv(dev);
13708 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13710 mutex_lock(&bp->cnic_mutex);
13712 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13713 mutex_unlock(&bp->cnic_mutex);
13715 bp->cnic_enabled = false;
13716 kfree(bp->cnic_kwq);
13717 bp->cnic_kwq = NULL;
13722 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13724 struct bnx2x *bp = netdev_priv(dev);
13725 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13727 /* If both iSCSI and FCoE are disabled - return NULL in
13728 * order to indicate CNIC that it should not try to work
13729 * with this device.
13731 if (NO_ISCSI(bp) && NO_FCOE(bp))
13734 cp->drv_owner = THIS_MODULE;
13735 cp->chip_id = CHIP_ID(bp);
13736 cp->pdev = bp->pdev;
13737 cp->io_base = bp->regview;
13738 cp->io_base2 = bp->doorbells;
13739 cp->max_kwqe_pending = 8;
13740 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13741 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13742 bnx2x_cid_ilt_lines(bp);
13743 cp->ctx_tbl_len = CNIC_ILT_LINES;
13744 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13745 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13746 cp->drv_ctl = bnx2x_drv_ctl;
13747 cp->drv_register_cnic = bnx2x_register_cnic;
13748 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13749 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13750 cp->iscsi_l2_client_id =
13751 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13752 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13754 if (NO_ISCSI_OOO(bp))
13755 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13758 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13761 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13764 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13766 cp->ctx_tbl_offset,
13772 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13774 struct bnx2x *bp = fp->bp;
13775 u32 offset = BAR_USTRORM_INTMEM;
13778 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13779 else if (!CHIP_IS_E1x(bp))
13780 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13782 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13787 /* called only on E1H or E2.
13788 * When pretending to be PF, the pretend value is the function number 0...7
13789 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13792 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13796 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13799 /* get my own pretend register */
13800 pretend_reg = bnx2x_get_pretend_reg(bp);
13801 REG_WR(bp, pretend_reg, pretend_func_val);
13802 REG_RD(bp, pretend_reg);