1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
81 static char version[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 module_param(int_mode, int, 0);
107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 static int dropless_fc;
111 module_param(dropless_fc, int, 0);
112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 static int mrrs = -1;
115 module_param(mrrs, int, 0);
116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 module_param(debug, int, 0);
120 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 struct workqueue_struct *bnx2x_wq;
124 struct bnx2x_mac_vals {
135 enum bnx2x_board_type {
159 /* indexed by board_type, above */
163 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
164 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
165 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
166 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
167 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
168 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
169 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
170 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
171 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
172 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
173 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
174 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
175 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
176 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
177 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
178 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
179 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
180 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
181 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
182 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 #ifndef PCI_DEVICE_ID_NX2_57710
187 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189 #ifndef PCI_DEVICE_ID_NX2_57711
190 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192 #ifndef PCI_DEVICE_ID_NX2_57711E
193 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195 #ifndef PCI_DEVICE_ID_NX2_57712
196 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
199 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
202 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204 #ifndef PCI_DEVICE_ID_NX2_57800
205 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
208 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
211 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213 #ifndef PCI_DEVICE_ID_NX2_57810
214 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
217 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219 #ifndef PCI_DEVICE_ID_NX2_57840_O
220 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
223 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
226 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
229 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
232 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
235 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
238 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240 #ifndef PCI_DEVICE_ID_NX2_57811
241 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
244 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
247 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277 /* Global resources for unloading a previously loaded device */
278 #define BNX2X_PREV_WAIT_NEEDED 1
279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
280 static LIST_HEAD(bnx2x_prev_list);
281 /****************************************************************************
282 * General service functions
283 ****************************************************************************/
285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
286 u32 addr, dma_addr_t mapping)
288 REG_WR(bp, addr, U64_LO(mapping));
289 REG_WR(bp, addr + 4, U64_HI(mapping));
292 static void storm_memset_spq_addr(struct bnx2x *bp,
293 dma_addr_t mapping, u16 abs_fid)
295 u32 addr = XSEM_REG_FAST_MEMORY +
296 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
298 __storm_memset_dma_mapping(bp, addr, mapping);
301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
304 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
306 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
308 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
310 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
327 static void storm_memset_eq_data(struct bnx2x *bp,
328 struct event_ring_data *eq_data,
331 size_t size = sizeof(struct event_ring_data);
333 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
335 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
342 REG_WR16(bp, addr, eq_prod);
346 * locking is done by mcp
348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
350 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
351 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
353 PCICFG_VENDOR_ID_OFFSET);
356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
368 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
369 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
370 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
371 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
372 #define DMAE_DP_DST_NONE "dst_addr [none]"
374 static void bnx2x_dp_dmae(struct bnx2x *bp,
375 struct dmae_command *dmae, int msglvl)
377 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
380 switch (dmae->opcode & DMAE_COMMAND_DST) {
381 case DMAE_CMD_DST_PCI:
382 if (src_type == DMAE_CMD_SRC_PCI)
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
387 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
391 DP(msglvl, "DMAE: opcode 0x%08x\n"
392 "src [%08x], len [%d*4], dst [%x:%08x]\n"
393 "comp_addr [%x:%08x], comp_val 0x%08x\n",
394 dmae->opcode, dmae->src_addr_lo >> 2,
395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 case DMAE_CMD_DST_GRC:
400 if (src_type == DMAE_CMD_SRC_PCI)
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
405 dmae->len, dmae->dst_addr_lo >> 2,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_lo >> 2,
413 dmae->len, dmae->dst_addr_lo >> 2,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
418 if (src_type == DMAE_CMD_SRC_PCI)
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
421 "comp_addr [%x:%08x] comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
423 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_lo >> 2,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
435 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
436 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
437 i, *(((u32 *)dmae) + i));
440 /* copy command into DMAE command memory and set DMAE command go */
441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
446 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
448 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 REG_WR(bp, dmae_reg_go_c[idx], 1);
453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 return opcode & ~DMAE_CMD_SRC_RESET;
464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
465 bool with_comp, u8 comp_type)
469 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
470 (dst_type << DMAE_COMMAND_DST_SHIFT));
472 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
475 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
476 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
477 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
480 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
485 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
490 struct dmae_command *dmae,
491 u8 src_type, u8 dst_type)
493 memset(dmae, 0, sizeof(struct dmae_command));
496 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
497 true, DMAE_COMP_PCI);
499 /* fill in the completion parameters */
500 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
501 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_val = DMAE_COMP_VAL;
505 /* issue a dmae command over the init-channel and wait for completion */
506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
508 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
512 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
514 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
518 spin_lock_bh(&bp->dmae_lock);
520 /* reset completion */
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
526 /* wait for completion */
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
546 spin_unlock_bh(&bp->dmae_lock);
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
554 struct dmae_command dmae;
556 if (!bp->dmae_ready) {
557 u32 *data = bnx2x_sp(bp, wb_data[0]);
560 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
562 bnx2x_init_str_wr(bp, dst_addr, data, len32);
566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
569 /* fill in addresses and len */
570 dmae.src_addr_lo = U64_LO(dma_addr);
571 dmae.src_addr_hi = U64_HI(dma_addr);
572 dmae.dst_addr_lo = dst_addr >> 2;
573 dmae.dst_addr_hi = 0;
576 /* issue the command and wait for completion */
577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
579 BNX2X_ERR("DMAE returned failure %d\n", rc);
584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
587 struct dmae_command dmae;
589 if (!bp->dmae_ready) {
590 u32 *data = bnx2x_sp(bp, wb_data[0]);
594 for (i = 0; i < len32; i++)
595 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
597 for (i = 0; i < len32; i++)
598 data[i] = REG_RD(bp, src_addr + i*4);
603 /* set opcode and fixed command fields */
604 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
606 /* fill in addresses and len */
607 dmae.src_addr_lo = src_addr >> 2;
608 dmae.src_addr_hi = 0;
609 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
610 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
613 /* issue the command and wait for completion */
614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
616 BNX2X_ERR("DMAE returned failure %d\n", rc);
621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
624 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
627 while (len > dmae_wr_max) {
628 bnx2x_write_dmae(bp, phys_addr + offset,
629 addr + offset, dmae_wr_max);
630 offset += dmae_wr_max * 4;
634 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
637 static int bnx2x_mc_assert(struct bnx2x *bp)
641 u32 row0, row1, row2, row3;
644 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_INDEX_OFFSET);
647 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
649 /* print the asserts */
650 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
652 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
653 XSTORM_ASSERT_LIST_OFFSET(i));
654 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
655 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
656 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
657 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
658 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
659 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
661 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
662 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
663 i, row3, row2, row1, row0);
671 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_INDEX_OFFSET);
674 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
676 /* print the asserts */
677 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
679 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
680 TSTORM_ASSERT_LIST_OFFSET(i));
681 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
682 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
683 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
684 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
685 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
686 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
688 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
689 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
690 i, row3, row2, row1, row0);
698 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_INDEX_OFFSET);
701 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
703 /* print the asserts */
704 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
706 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
707 CSTORM_ASSERT_LIST_OFFSET(i));
708 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
709 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
710 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
711 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
712 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
713 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
715 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
716 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
717 i, row3, row2, row1, row0);
725 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_INDEX_OFFSET);
728 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
730 /* print the asserts */
731 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
733 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
734 USTORM_ASSERT_LIST_OFFSET(i));
735 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
736 USTORM_ASSERT_LIST_OFFSET(i) + 4);
737 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
738 USTORM_ASSERT_LIST_OFFSET(i) + 8);
739 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
740 USTORM_ASSERT_LIST_OFFSET(i) + 12);
742 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
743 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
744 i, row3, row2, row1, row0);
754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
760 u32 trace_shmem_base;
762 BNX2X_ERR("NO MCP - can not dump\n");
765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766 (bp->common.bc_ver & 0xff0000) >> 16,
767 (bp->common.bc_ver & 0xff00) >> 8,
768 (bp->common.bc_ver & 0xff));
770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
774 if (BP_PATH(bp) == 0)
775 trace_shmem_base = bp->common.shmem_base;
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778 addr = trace_shmem_base - 0x800;
780 /* validate TRCB signature */
781 mark = REG_RD(bp, addr);
782 if (mark != MFW_TRACE_SIGNATURE) {
783 BNX2X_ERR("Trace buffer signature is missing.");
787 /* read cyclic buffer pointer */
789 mark = REG_RD(bp, addr);
790 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
791 + ((mark + 0x3) & ~0x3) - 0x08000000;
792 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
796 /* dump buffer after the mark */
797 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
798 for (word = 0; word < 8; word++)
799 data[word] = htonl(REG_RD(bp, offset + 4*word));
801 pr_cont("%s", (char *)data);
804 /* dump buffer before the mark */
805 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
806 for (word = 0; word < 8; word++)
807 data[word] = htonl(REG_RD(bp, offset + 4*word));
809 pr_cont("%s", (char *)data);
811 printk("%s" "end of fw dump\n", lvl);
814 static void bnx2x_fw_dump(struct bnx2x *bp)
816 bnx2x_fw_dump_lvl(bp, KERN_ERR);
819 static void bnx2x_hc_int_disable(struct bnx2x *bp)
821 int port = BP_PORT(bp);
822 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
823 u32 val = REG_RD(bp, addr);
825 /* in E1 we must use only PCI configuration space to disable
826 * MSI/MSIX capability
827 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
829 if (CHIP_IS_E1(bp)) {
830 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
831 * Use mask register to prevent from HC sending interrupts
832 * after we exit the function
834 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
836 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
837 HC_CONFIG_0_REG_INT_LINE_EN_0 |
838 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
840 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
841 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
842 HC_CONFIG_0_REG_INT_LINE_EN_0 |
843 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
846 "write %x to HC %d (addr 0x%x)\n",
849 /* flush all outstanding writes */
852 REG_WR(bp, addr, val);
853 if (REG_RD(bp, addr) != val)
854 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
857 static void bnx2x_igu_int_disable(struct bnx2x *bp)
859 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
861 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
862 IGU_PF_CONF_INT_LINE_EN |
863 IGU_PF_CONF_ATTN_BIT_EN);
865 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
867 /* flush all outstanding writes */
870 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
871 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
872 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
875 static void bnx2x_int_disable(struct bnx2x *bp)
877 if (bp->common.int_block == INT_BLOCK_HC)
878 bnx2x_hc_int_disable(bp);
880 bnx2x_igu_int_disable(bp);
883 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
887 struct hc_sp_status_block_data sp_sb_data;
888 int func = BP_FUNC(bp);
889 #ifdef BNX2X_STOP_ON_ERROR
890 u16 start = 0, end = 0;
894 bnx2x_int_disable(bp);
896 bp->stats_state = STATS_STATE_DISABLED;
897 bp->eth_stats.unrecoverable_error++;
898 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
900 BNX2X_ERR("begin crash dump -----------------\n");
904 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
905 bp->def_idx, bp->def_att_idx, bp->attn_state,
906 bp->spq_prod_idx, bp->stats_counter);
907 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
908 bp->def_status_blk->atten_status_block.attn_bits,
909 bp->def_status_blk->atten_status_block.attn_bits_ack,
910 bp->def_status_blk->atten_status_block.status_block_id,
911 bp->def_status_blk->atten_status_block.attn_bits_index);
913 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
915 bp->def_status_blk->sp_sb.index_values[i],
916 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
918 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
919 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
920 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
923 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
924 sp_sb_data.igu_sb_id,
925 sp_sb_data.igu_seg_id,
926 sp_sb_data.p_func.pf_id,
927 sp_sb_data.p_func.vnic_id,
928 sp_sb_data.p_func.vf_id,
929 sp_sb_data.p_func.vf_valid,
932 for_each_eth_queue(bp, i) {
933 struct bnx2x_fastpath *fp = &bp->fp[i];
935 struct hc_status_block_data_e2 sb_data_e2;
936 struct hc_status_block_data_e1x sb_data_e1x;
937 struct hc_status_block_sm *hc_sm_p =
939 sb_data_e1x.common.state_machine :
940 sb_data_e2.common.state_machine;
941 struct hc_index_data *hc_index_p =
943 sb_data_e1x.index_data :
944 sb_data_e2.index_data;
947 struct bnx2x_fp_txdata txdata;
950 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
951 i, fp->rx_bd_prod, fp->rx_bd_cons,
953 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
954 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
955 fp->rx_sge_prod, fp->last_max_sge,
956 le16_to_cpu(fp->fp_hc_idx));
959 for_each_cos_in_tx_queue(fp, cos)
961 txdata = *fp->txdata_ptr[cos];
962 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
963 i, txdata.tx_pkt_prod,
964 txdata.tx_pkt_cons, txdata.tx_bd_prod,
966 le16_to_cpu(*txdata.tx_cons_sb));
969 loop = CHIP_IS_E1x(bp) ?
970 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
977 BNX2X_ERR(" run indexes (");
978 for (j = 0; j < HC_SB_MAX_SM; j++)
980 fp->sb_running_index[j],
981 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
983 BNX2X_ERR(" indexes (");
984 for (j = 0; j < loop; j++)
986 fp->sb_index_values[j],
987 (j == loop - 1) ? ")" : " ");
989 data_size = CHIP_IS_E1x(bp) ?
990 sizeof(struct hc_status_block_data_e1x) :
991 sizeof(struct hc_status_block_data_e2);
992 data_size /= sizeof(u32);
993 sb_data_p = CHIP_IS_E1x(bp) ?
994 (u32 *)&sb_data_e1x :
996 /* copy sb data in here */
997 for (j = 0; j < data_size; j++)
998 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
999 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1002 if (!CHIP_IS_E1x(bp)) {
1003 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1004 sb_data_e2.common.p_func.pf_id,
1005 sb_data_e2.common.p_func.vf_id,
1006 sb_data_e2.common.p_func.vf_valid,
1007 sb_data_e2.common.p_func.vnic_id,
1008 sb_data_e2.common.same_igu_sb_1b,
1009 sb_data_e2.common.state);
1011 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1012 sb_data_e1x.common.p_func.pf_id,
1013 sb_data_e1x.common.p_func.vf_id,
1014 sb_data_e1x.common.p_func.vf_valid,
1015 sb_data_e1x.common.p_func.vnic_id,
1016 sb_data_e1x.common.same_igu_sb_1b,
1017 sb_data_e1x.common.state);
1021 for (j = 0; j < HC_SB_MAX_SM; j++) {
1022 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1023 j, hc_sm_p[j].__flags,
1024 hc_sm_p[j].igu_sb_id,
1025 hc_sm_p[j].igu_seg_id,
1026 hc_sm_p[j].time_to_expire,
1027 hc_sm_p[j].timer_value);
1031 for (j = 0; j < loop; j++) {
1032 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1038 #ifdef BNX2X_STOP_ON_ERROR
1041 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1042 for (i = 0; i < NUM_EQ_DESC; i++) {
1043 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1045 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1046 i, bp->eq_ring[i].message.opcode,
1047 bp->eq_ring[i].message.error);
1048 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1053 for_each_valid_rx_queue(bp, i) {
1054 struct bnx2x_fastpath *fp = &bp->fp[i];
1056 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1057 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1058 for (j = start; j != end; j = RX_BD(j + 1)) {
1059 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1060 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1062 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1063 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1066 start = RX_SGE(fp->rx_sge_prod);
1067 end = RX_SGE(fp->last_max_sge);
1068 for (j = start; j != end; j = RX_SGE(j + 1)) {
1069 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1070 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1072 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1073 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1076 start = RCQ_BD(fp->rx_comp_cons - 10);
1077 end = RCQ_BD(fp->rx_comp_cons + 503);
1078 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1079 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1081 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1082 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1087 for_each_valid_tx_queue(bp, i) {
1088 struct bnx2x_fastpath *fp = &bp->fp[i];
1089 for_each_cos_in_tx_queue(fp, cos) {
1090 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1092 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1093 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1094 for (j = start; j != end; j = TX_BD(j + 1)) {
1095 struct sw_tx_bd *sw_bd =
1096 &txdata->tx_buf_ring[j];
1098 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1099 i, cos, j, sw_bd->skb,
1103 start = TX_BD(txdata->tx_bd_cons - 10);
1104 end = TX_BD(txdata->tx_bd_cons + 254);
1105 for (j = start; j != end; j = TX_BD(j + 1)) {
1106 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1108 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1109 i, cos, j, tx_bd[0], tx_bd[1],
1110 tx_bd[2], tx_bd[3]);
1116 bnx2x_mc_assert(bp);
1117 BNX2X_ERR("end crash dump -----------------\n");
1121 * FLR Support for E2
1123 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1126 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1127 #define FLR_WAIT_INTERVAL 50 /* usec */
1128 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1130 struct pbf_pN_buf_regs {
1137 struct pbf_pN_cmd_regs {
1143 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1144 struct pbf_pN_buf_regs *regs,
1147 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1148 u32 cur_cnt = poll_count;
1150 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1151 crd = crd_start = REG_RD(bp, regs->crd);
1152 init_crd = REG_RD(bp, regs->init_crd);
1154 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1155 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1156 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1158 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1159 (init_crd - crd_start))) {
1161 udelay(FLR_WAIT_INTERVAL);
1162 crd = REG_RD(bp, regs->crd);
1163 crd_freed = REG_RD(bp, regs->crd_freed);
1165 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1167 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1169 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1170 regs->pN, crd_freed);
1174 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1175 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1178 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1179 struct pbf_pN_cmd_regs *regs,
1182 u32 occup, to_free, freed, freed_start;
1183 u32 cur_cnt = poll_count;
1185 occup = to_free = REG_RD(bp, regs->lines_occup);
1186 freed = freed_start = REG_RD(bp, regs->lines_freed);
1188 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1189 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1191 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1193 udelay(FLR_WAIT_INTERVAL);
1194 occup = REG_RD(bp, regs->lines_occup);
1195 freed = REG_RD(bp, regs->lines_freed);
1197 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1199 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1201 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1206 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1207 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1210 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1211 u32 expected, u32 poll_count)
1213 u32 cur_cnt = poll_count;
1216 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1217 udelay(FLR_WAIT_INTERVAL);
1222 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1223 char *msg, u32 poll_cnt)
1225 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1227 BNX2X_ERR("%s usage count=%d\n", msg, val);
1233 /* Common routines with VF FLR cleanup */
1234 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1236 /* adjust polling timeout */
1237 if (CHIP_REV_IS_EMUL(bp))
1238 return FLR_POLL_CNT * 2000;
1240 if (CHIP_REV_IS_FPGA(bp))
1241 return FLR_POLL_CNT * 120;
1243 return FLR_POLL_CNT;
1246 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1248 struct pbf_pN_cmd_regs cmd_regs[] = {
1249 {0, (CHIP_IS_E3B0(bp)) ?
1250 PBF_REG_TQ_OCCUPANCY_Q0 :
1251 PBF_REG_P0_TQ_OCCUPANCY,
1252 (CHIP_IS_E3B0(bp)) ?
1253 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1254 PBF_REG_P0_TQ_LINES_FREED_CNT},
1255 {1, (CHIP_IS_E3B0(bp)) ?
1256 PBF_REG_TQ_OCCUPANCY_Q1 :
1257 PBF_REG_P1_TQ_OCCUPANCY,
1258 (CHIP_IS_E3B0(bp)) ?
1259 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1260 PBF_REG_P1_TQ_LINES_FREED_CNT},
1261 {4, (CHIP_IS_E3B0(bp)) ?
1262 PBF_REG_TQ_OCCUPANCY_LB_Q :
1263 PBF_REG_P4_TQ_OCCUPANCY,
1264 (CHIP_IS_E3B0(bp)) ?
1265 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1266 PBF_REG_P4_TQ_LINES_FREED_CNT}
1269 struct pbf_pN_buf_regs buf_regs[] = {
1270 {0, (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_INIT_CRD_Q0 :
1272 PBF_REG_P0_INIT_CRD ,
1273 (CHIP_IS_E3B0(bp)) ?
1276 (CHIP_IS_E3B0(bp)) ?
1277 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1278 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1279 {1, (CHIP_IS_E3B0(bp)) ?
1280 PBF_REG_INIT_CRD_Q1 :
1281 PBF_REG_P1_INIT_CRD,
1282 (CHIP_IS_E3B0(bp)) ?
1285 (CHIP_IS_E3B0(bp)) ?
1286 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1287 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1288 {4, (CHIP_IS_E3B0(bp)) ?
1289 PBF_REG_INIT_CRD_LB_Q :
1290 PBF_REG_P4_INIT_CRD,
1291 (CHIP_IS_E3B0(bp)) ?
1292 PBF_REG_CREDIT_LB_Q :
1294 (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1296 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1301 /* Verify the command queues are flushed P0, P1, P4 */
1302 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1303 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1305 /* Verify the transmission buffers are flushed P0, P1, P4 */
1306 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1307 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1310 #define OP_GEN_PARAM(param) \
1311 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1313 #define OP_GEN_TYPE(type) \
1314 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1316 #define OP_GEN_AGG_VECT(index) \
1317 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1319 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1321 u32 op_gen_command = 0;
1322 u32 comp_addr = BAR_CSTRORM_INTMEM +
1323 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1326 if (REG_RD(bp, comp_addr)) {
1327 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1331 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1332 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1333 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1334 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1336 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1337 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1339 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1340 BNX2X_ERR("FW final cleanup did not succeed\n");
1341 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1342 (REG_RD(bp, comp_addr)));
1346 /* Zero completion for next FLR */
1347 REG_WR(bp, comp_addr, 0);
1352 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1356 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1357 return status & PCI_EXP_DEVSTA_TRPND;
1360 /* PF FLR specific routines
1362 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1364 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1365 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366 CFC_REG_NUM_LCIDS_INSIDE_PF,
1367 "CFC PF usage counter timed out",
1371 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1372 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373 DORQ_REG_PF_USAGE_CNT,
1374 "DQ PF usage counter timed out",
1378 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1379 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1381 "QM PF usage counter timed out",
1385 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1386 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1388 "Timers VNIC usage counter timed out",
1391 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1393 "Timers NUM_SCANS usage counter timed out",
1397 /* Wait DMAE PF usage counter to zero */
1398 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1399 dmae_reg_go_c[INIT_DMAE_C(bp)],
1400 "DMAE command register timed out",
1407 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1411 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1412 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1414 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1415 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1417 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1418 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1420 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1421 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1423 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1424 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1426 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1427 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1429 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1430 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1432 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1433 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1437 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1439 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1441 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1443 /* Re-enable PF target read access */
1444 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1446 /* Poll HW usage counters */
1447 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1448 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1451 /* Zero the igu 'trailing edge' and 'leading edge' */
1453 /* Send the FW cleanup command */
1454 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1459 /* Verify TX hw is flushed */
1460 bnx2x_tx_hw_flushed(bp, poll_cnt);
1462 /* Wait 100ms (not adjusted according to platform) */
1465 /* Verify no pending pci transactions */
1466 if (bnx2x_is_pcie_pending(bp->pdev))
1467 BNX2X_ERR("PCIE Transactions still pending\n");
1470 bnx2x_hw_enable_status(bp);
1473 * Master enable - Due to WB DMAE writes performed before this
1474 * register is re-initialized as part of the regular function init
1476 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1481 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1483 int port = BP_PORT(bp);
1484 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1485 u32 val = REG_RD(bp, addr);
1486 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1487 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1488 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1491 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1492 HC_CONFIG_0_REG_INT_LINE_EN_0);
1493 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1496 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1498 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1499 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1500 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1503 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1504 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1505 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1506 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1508 if (!CHIP_IS_E1(bp)) {
1510 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1512 REG_WR(bp, addr, val);
1514 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1519 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1522 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1523 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1525 REG_WR(bp, addr, val);
1527 * Ensure that HC_CONFIG is written before leading/trailing edge config
1532 if (!CHIP_IS_E1(bp)) {
1533 /* init leading/trailing edge */
1535 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1537 /* enable nig and gpio3 attention */
1542 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1543 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1546 /* Make sure that interrupts are indeed enabled from here on */
1550 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1553 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1554 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1555 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1557 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1560 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1561 IGU_PF_CONF_SINGLE_ISR_EN);
1562 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563 IGU_PF_CONF_ATTN_BIT_EN);
1566 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1568 val &= ~IGU_PF_CONF_INT_LINE_EN;
1569 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1570 IGU_PF_CONF_ATTN_BIT_EN |
1571 IGU_PF_CONF_SINGLE_ISR_EN);
1573 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1574 val |= (IGU_PF_CONF_INT_LINE_EN |
1575 IGU_PF_CONF_ATTN_BIT_EN |
1576 IGU_PF_CONF_SINGLE_ISR_EN);
1579 /* Clean previous status - need to configure igu prior to ack*/
1580 if ((!msix) || single_msix) {
1581 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1585 val |= IGU_PF_CONF_FUNC_EN;
1587 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1588 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1590 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1592 if (val & IGU_PF_CONF_INT_LINE_EN)
1593 pci_intx(bp->pdev, true);
1597 /* init leading/trailing edge */
1599 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1601 /* enable nig and gpio3 attention */
1606 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1607 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1609 /* Make sure that interrupts are indeed enabled from here on */
1613 void bnx2x_int_enable(struct bnx2x *bp)
1615 if (bp->common.int_block == INT_BLOCK_HC)
1616 bnx2x_hc_int_enable(bp);
1618 bnx2x_igu_int_enable(bp);
1621 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1623 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1627 /* prevent the HW from sending interrupts */
1628 bnx2x_int_disable(bp);
1630 /* make sure all ISRs are done */
1632 synchronize_irq(bp->msix_table[0].vector);
1634 if (CNIC_SUPPORT(bp))
1636 for_each_eth_queue(bp, i)
1637 synchronize_irq(bp->msix_table[offset++].vector);
1639 synchronize_irq(bp->pdev->irq);
1641 /* make sure sp_task is not running */
1642 cancel_delayed_work(&bp->sp_task);
1643 cancel_delayed_work(&bp->period_task);
1644 flush_workqueue(bnx2x_wq);
1650 * General service functions
1653 /* Return true if succeeded to acquire the lock */
1654 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1657 u32 resource_bit = (1 << resource);
1658 int func = BP_FUNC(bp);
1659 u32 hw_lock_control_reg;
1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1662 "Trying to take a lock on resource %d\n", resource);
1664 /* Validating that the resource is within range */
1665 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1666 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1667 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1668 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1673 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1675 hw_lock_control_reg =
1676 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1678 /* Try to acquire the lock */
1679 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1680 lock_status = REG_RD(bp, hw_lock_control_reg);
1681 if (lock_status & resource_bit)
1684 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1685 "Failed to get a lock on resource %d\n", resource);
1690 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1692 * @bp: driver handle
1694 * Returns the recovery leader resource id according to the engine this function
1695 * belongs to. Currently only only 2 engines is supported.
1697 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1700 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1702 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1706 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1708 * @bp: driver handle
1710 * Tries to acquire a leader lock for current engine.
1712 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1714 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1717 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1719 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1720 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1722 /* Set the interrupt occurred bit for the sp-task to recognize it
1723 * must ack the interrupt and transition according to the IGU
1726 atomic_set(&bp->interrupt_occurred, 1);
1728 /* The sp_task must execute only after this bit
1729 * is set, otherwise we will get out of sync and miss all
1730 * further interrupts. Hence, the barrier.
1734 /* schedule sp_task to workqueue */
1735 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1738 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1740 struct bnx2x *bp = fp->bp;
1741 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1742 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1743 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1744 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1747 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1748 fp->index, cid, command, bp->state,
1749 rr_cqe->ramrod_cqe.ramrod_type);
1751 /* If cid is within VF range, replace the slowpath object with the
1752 * one corresponding to this VF
1754 if (cid >= BNX2X_FIRST_VF_CID &&
1755 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1756 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1759 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1760 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1761 drv_cmd = BNX2X_Q_CMD_UPDATE;
1764 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1765 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1766 drv_cmd = BNX2X_Q_CMD_SETUP;
1769 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1770 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1771 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1774 case (RAMROD_CMD_ID_ETH_HALT):
1775 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1776 drv_cmd = BNX2X_Q_CMD_HALT;
1779 case (RAMROD_CMD_ID_ETH_TERMINATE):
1780 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1781 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1784 case (RAMROD_CMD_ID_ETH_EMPTY):
1785 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1786 drv_cmd = BNX2X_Q_CMD_EMPTY;
1790 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1791 command, fp->index);
1795 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1796 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1797 /* q_obj->complete_cmd() failure means that this was
1798 * an unexpected completion.
1800 * In this case we don't want to increase the bp->spq_left
1801 * because apparently we haven't sent this command the first
1804 #ifdef BNX2X_STOP_ON_ERROR
1809 /* SRIOV: reschedule any 'in_progress' operations */
1810 bnx2x_iov_sp_event(bp, cid, true);
1812 smp_mb__before_atomic_inc();
1813 atomic_inc(&bp->cq_spq_left);
1814 /* push the change in bp->spq_left and towards the memory */
1815 smp_mb__after_atomic_inc();
1817 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1819 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1820 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1821 /* if Q update ramrod is completed for last Q in AFEX vif set
1822 * flow, then ACK MCP at the end
1824 * mark pending ACK to MCP bit.
1825 * prevent case that both bits are cleared.
1826 * At the end of load/unload driver checks that
1827 * sp_state is cleared, and this order prevents
1830 smp_mb__before_clear_bit();
1831 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1833 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1834 smp_mb__after_clear_bit();
1836 /* schedule the sp task as mcp ack is required */
1837 bnx2x_schedule_sp_task(bp);
1843 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1845 struct bnx2x *bp = netdev_priv(dev_instance);
1846 u16 status = bnx2x_ack_int(bp);
1851 /* Return here if interrupt is shared and it's not for us */
1852 if (unlikely(status == 0)) {
1853 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1856 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1858 #ifdef BNX2X_STOP_ON_ERROR
1859 if (unlikely(bp->panic))
1863 for_each_eth_queue(bp, i) {
1864 struct bnx2x_fastpath *fp = &bp->fp[i];
1866 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1867 if (status & mask) {
1868 /* Handle Rx or Tx according to SB id */
1869 for_each_cos_in_tx_queue(fp, cos)
1870 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1871 prefetch(&fp->sb_running_index[SM_RX_ID]);
1872 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1877 if (CNIC_SUPPORT(bp)) {
1879 if (status & (mask | 0x1)) {
1880 struct cnic_ops *c_ops = NULL;
1883 c_ops = rcu_dereference(bp->cnic_ops);
1884 if (c_ops && (bp->cnic_eth_dev.drv_state &
1885 CNIC_DRV_STATE_HANDLES_IRQ))
1886 c_ops->cnic_handler(bp->cnic_data, NULL);
1893 if (unlikely(status & 0x1)) {
1895 /* schedule sp task to perform default status block work, ack
1896 * attentions and enable interrupts.
1898 bnx2x_schedule_sp_task(bp);
1905 if (unlikely(status))
1906 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1915 * General service functions
1918 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1921 u32 resource_bit = (1 << resource);
1922 int func = BP_FUNC(bp);
1923 u32 hw_lock_control_reg;
1926 /* Validating that the resource is within range */
1927 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1928 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1929 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1934 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1936 hw_lock_control_reg =
1937 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1940 /* Validating that the resource is not already taken */
1941 lock_status = REG_RD(bp, hw_lock_control_reg);
1942 if (lock_status & resource_bit) {
1943 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1944 lock_status, resource_bit);
1948 /* Try for 5 second every 5ms */
1949 for (cnt = 0; cnt < 1000; cnt++) {
1950 /* Try to acquire the lock */
1951 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1952 lock_status = REG_RD(bp, hw_lock_control_reg);
1953 if (lock_status & resource_bit)
1956 usleep_range(5000, 10000);
1958 BNX2X_ERR("Timeout\n");
1962 int bnx2x_release_leader_lock(struct bnx2x *bp)
1964 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1967 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1970 u32 resource_bit = (1 << resource);
1971 int func = BP_FUNC(bp);
1972 u32 hw_lock_control_reg;
1974 /* Validating that the resource is within range */
1975 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1976 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1977 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1982 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984 hw_lock_control_reg =
1985 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 /* Validating that the resource is currently taken */
1989 lock_status = REG_RD(bp, hw_lock_control_reg);
1990 if (!(lock_status & resource_bit)) {
1991 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
1992 lock_status, resource_bit);
1996 REG_WR(bp, hw_lock_control_reg, resource_bit);
2000 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2002 /* The GPIO should be swapped if swap register is set and active */
2003 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2004 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2005 int gpio_shift = gpio_num +
2006 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2007 u32 gpio_mask = (1 << gpio_shift);
2011 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2012 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2016 /* read GPIO value */
2017 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2019 /* get the requested pin value */
2020 if ((gpio_reg & gpio_mask) == gpio_mask)
2025 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2030 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO and mask except the float bits */
2047 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2050 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2052 "Set GPIO %d (shift %d) -> output low\n",
2053 gpio_num, gpio_shift);
2054 /* clear FLOAT and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2059 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2061 "Set GPIO %d (shift %d) -> output high\n",
2062 gpio_num, gpio_shift);
2063 /* clear FLOAT and set SET */
2064 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2065 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2068 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2070 "Set GPIO %d (shift %d) -> input\n",
2071 gpio_num, gpio_shift);
2073 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2080 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2081 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2091 /* Any port swapping should be handled by caller. */
2093 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2094 /* read GPIO and mask except the float bits */
2095 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2096 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2097 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2098 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2101 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2102 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2104 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2107 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2108 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2110 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2113 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2114 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2116 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2120 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2126 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2133 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2135 /* The GPIO should be swapped if swap register is set and active */
2136 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2137 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2138 int gpio_shift = gpio_num +
2139 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2140 u32 gpio_mask = (1 << gpio_shift);
2143 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2144 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2148 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2150 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2153 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2155 "Clear GPIO INT %d (shift %d) -> output low\n",
2156 gpio_num, gpio_shift);
2157 /* clear SET and set CLR */
2158 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2159 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2162 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2164 "Set GPIO INT %d (shift %d) -> output high\n",
2165 gpio_num, gpio_shift);
2166 /* clear CLR and set SET */
2167 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2168 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2175 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2176 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2181 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2185 /* Only 2 SPIOs are configurable */
2186 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2187 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2192 /* read SPIO and mask except the float bits */
2193 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2196 case MISC_SPIO_OUTPUT_LOW:
2197 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2198 /* clear FLOAT and set CLR */
2199 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2200 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2203 case MISC_SPIO_OUTPUT_HIGH:
2204 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2205 /* clear FLOAT and set SET */
2206 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2207 spio_reg |= (spio << MISC_SPIO_SET_POS);
2210 case MISC_SPIO_INPUT_HI_Z:
2211 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2213 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2220 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2226 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2228 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2229 switch (bp->link_vars.ieee_fc &
2230 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2232 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2237 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2241 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2242 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2246 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2252 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2254 /* Initialize link parameters structure variables
2255 * It is recommended to turn off RX FC for jumbo frames
2256 * for better performance
2258 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2259 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2261 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2264 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2266 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2267 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2269 if (!BP_NOMCP(bp)) {
2270 bnx2x_set_requested_fc(bp);
2271 bnx2x_acquire_phy_lock(bp);
2273 if (load_mode == LOAD_DIAG) {
2274 struct link_params *lp = &bp->link_params;
2275 lp->loopback_mode = LOOPBACK_XGXS;
2276 /* do PHY loopback at 10G speed, if possible */
2277 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2278 if (lp->speed_cap_mask[cfx_idx] &
2279 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2280 lp->req_line_speed[cfx_idx] =
2283 lp->req_line_speed[cfx_idx] =
2288 if (load_mode == LOAD_LOOPBACK_EXT) {
2289 struct link_params *lp = &bp->link_params;
2290 lp->loopback_mode = LOOPBACK_EXT;
2293 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2295 bnx2x_release_phy_lock(bp);
2297 bnx2x_calc_fc_adv(bp);
2299 if (bp->link_vars.link_up) {
2300 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2301 bnx2x_link_report(bp);
2303 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2304 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2307 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2311 void bnx2x_link_set(struct bnx2x *bp)
2313 if (!BP_NOMCP(bp)) {
2314 bnx2x_acquire_phy_lock(bp);
2315 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2316 bnx2x_release_phy_lock(bp);
2318 bnx2x_calc_fc_adv(bp);
2320 BNX2X_ERR("Bootcode is missing - can not set link\n");
2323 static void bnx2x__link_reset(struct bnx2x *bp)
2325 if (!BP_NOMCP(bp)) {
2326 bnx2x_acquire_phy_lock(bp);
2327 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2328 bnx2x_release_phy_lock(bp);
2330 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2333 void bnx2x_force_link_reset(struct bnx2x *bp)
2335 bnx2x_acquire_phy_lock(bp);
2336 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2337 bnx2x_release_phy_lock(bp);
2340 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2344 if (!BP_NOMCP(bp)) {
2345 bnx2x_acquire_phy_lock(bp);
2346 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2348 bnx2x_release_phy_lock(bp);
2350 BNX2X_ERR("Bootcode is missing - can not test link\n");
2355 /* Calculates the sum of vn_min_rates.
2356 It's needed for further normalizing of the min_rates.
2358 sum of vn_min_rates.
2360 0 - if all the min_rates are 0.
2361 In the later case fairness algorithm should be deactivated.
2362 If not all min_rates are zero then those that are zeroes will be set to 1.
2364 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2365 struct cmng_init_input *input)
2370 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2371 u32 vn_cfg = bp->mf_config[vn];
2372 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2373 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2375 /* Skip hidden vns */
2376 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2378 /* If min rate is zero - set it to 1 */
2379 else if (!vn_min_rate)
2380 vn_min_rate = DEF_MIN_RATE;
2384 input->vnic_min_rate[vn] = vn_min_rate;
2387 /* if ETS or all min rates are zeros - disable fairness */
2388 if (BNX2X_IS_ETS_ENABLED(bp)) {
2389 input->flags.cmng_enables &=
2390 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2392 } else if (all_zero) {
2393 input->flags.cmng_enables &=
2394 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 "All MIN values are zeroes fairness will be disabled\n");
2398 input->flags.cmng_enables |=
2399 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2402 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2403 struct cmng_init_input *input)
2406 u32 vn_cfg = bp->mf_config[vn];
2408 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2411 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2414 /* maxCfg in percents of linkspeed */
2415 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2416 } else /* SD modes */
2417 /* maxCfg is absolute in 100Mb units */
2418 vn_max_rate = maxCfg * 100;
2421 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2423 input->vnic_max_rate[vn] = vn_max_rate;
2426 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2428 if (CHIP_REV_IS_SLOW(bp))
2429 return CMNG_FNS_NONE;
2431 return CMNG_FNS_MINMAX;
2433 return CMNG_FNS_NONE;
2436 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2438 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2441 return; /* what should be the default value in this case */
2443 /* For 2 port configuration the absolute function number formula
2445 * abs_func = 2 * vn + BP_PORT + BP_PATH
2447 * and there are 4 functions per port
2449 * For 4 port configuration it is
2450 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2452 * and there are 2 functions per port
2454 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2457 if (func >= E1H_FUNC_MAX)
2461 MF_CFG_RD(bp, func_mf_config[func].config);
2463 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2464 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2465 bp->flags |= MF_FUNC_DIS;
2467 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2468 bp->flags &= ~MF_FUNC_DIS;
2472 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2474 struct cmng_init_input input;
2475 memset(&input, 0, sizeof(struct cmng_init_input));
2477 input.port_rate = bp->link_vars.line_speed;
2479 if (cmng_type == CMNG_FNS_MINMAX) {
2482 /* read mf conf from shmem */
2484 bnx2x_read_mf_cfg(bp);
2486 /* vn_weight_sum and enable fairness if not 0 */
2487 bnx2x_calc_vn_min(bp, &input);
2489 /* calculate and set min-max rate for each vn */
2491 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2492 bnx2x_calc_vn_max(bp, vn, &input);
2494 /* always enable rate shaping and fairness */
2495 input.flags.cmng_enables |=
2496 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2498 bnx2x_init_cmng(&input, &bp->cmng);
2502 /* rate shaping and fairness are disabled */
2504 "rate shaping and fairness are disabled\n");
2507 static void storm_memset_cmng(struct bnx2x *bp,
2508 struct cmng_init *cmng,
2512 size_t size = sizeof(struct cmng_struct_per_port);
2514 u32 addr = BAR_XSTRORM_INTMEM +
2515 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2517 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2519 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2520 int func = func_by_vn(bp, vn);
2522 addr = BAR_XSTRORM_INTMEM +
2523 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2524 size = sizeof(struct rate_shaping_vars_per_vn);
2525 __storm_memset_struct(bp, addr, size,
2526 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2528 addr = BAR_XSTRORM_INTMEM +
2529 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2530 size = sizeof(struct fairness_vars_per_vn);
2531 __storm_memset_struct(bp, addr, size,
2532 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2536 /* This function is called upon link interrupt */
2537 static void bnx2x_link_attn(struct bnx2x *bp)
2539 /* Make sure that we are synced with the current statistics */
2540 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2542 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2544 if (bp->link_vars.link_up) {
2546 /* dropless flow control */
2547 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2548 int port = BP_PORT(bp);
2549 u32 pause_enabled = 0;
2551 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2554 REG_WR(bp, BAR_USTRORM_INTMEM +
2555 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2559 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2560 struct host_port_stats *pstats;
2562 pstats = bnx2x_sp(bp, port_stats);
2563 /* reset old mac stats */
2564 memset(&(pstats->mac_stx[0]), 0,
2565 sizeof(struct mac_stx));
2567 if (bp->state == BNX2X_STATE_OPEN)
2568 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2571 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2572 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2574 if (cmng_fns != CMNG_FNS_NONE) {
2575 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2576 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2578 /* rate shaping and fairness are disabled */
2580 "single function mode without fairness\n");
2583 __bnx2x_link_report(bp);
2586 bnx2x_link_sync_notify(bp);
2589 void bnx2x__link_status_update(struct bnx2x *bp)
2591 if (bp->state != BNX2X_STATE_OPEN)
2594 /* read updated dcb configuration */
2596 bnx2x_dcbx_pmf_update(bp);
2597 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2598 if (bp->link_vars.link_up)
2599 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2601 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2602 /* indicate link status */
2603 bnx2x_link_report(bp);
2606 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2607 SUPPORTED_10baseT_Full |
2608 SUPPORTED_100baseT_Half |
2609 SUPPORTED_100baseT_Full |
2610 SUPPORTED_1000baseT_Full |
2611 SUPPORTED_2500baseX_Full |
2612 SUPPORTED_10000baseT_Full |
2617 SUPPORTED_Asym_Pause);
2618 bp->port.advertising[0] = bp->port.supported[0];
2620 bp->link_params.bp = bp;
2621 bp->link_params.port = BP_PORT(bp);
2622 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2623 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2624 bp->link_params.req_line_speed[0] = SPEED_10000;
2625 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2626 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2627 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2628 bp->link_vars.line_speed = SPEED_10000;
2629 bp->link_vars.link_status =
2630 (LINK_STATUS_LINK_UP |
2631 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2632 bp->link_vars.link_up = 1;
2633 bp->link_vars.duplex = DUPLEX_FULL;
2634 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2635 __bnx2x_link_report(bp);
2636 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2640 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2641 u16 vlan_val, u8 allowed_prio)
2643 struct bnx2x_func_state_params func_params = {NULL};
2644 struct bnx2x_func_afex_update_params *f_update_params =
2645 &func_params.params.afex_update;
2647 func_params.f_obj = &bp->func_obj;
2648 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2650 /* no need to wait for RAMROD completion, so don't
2651 * set RAMROD_COMP_WAIT flag
2654 f_update_params->vif_id = vifid;
2655 f_update_params->afex_default_vlan = vlan_val;
2656 f_update_params->allowed_priorities = allowed_prio;
2658 /* if ramrod can not be sent, response to MCP immediately */
2659 if (bnx2x_func_state_change(bp, &func_params) < 0)
2660 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2665 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2666 u16 vif_index, u8 func_bit_map)
2668 struct bnx2x_func_state_params func_params = {NULL};
2669 struct bnx2x_func_afex_viflists_params *update_params =
2670 &func_params.params.afex_viflists;
2674 /* validate only LIST_SET and LIST_GET are received from switch */
2675 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2676 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2679 func_params.f_obj = &bp->func_obj;
2680 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2682 /* set parameters according to cmd_type */
2683 update_params->afex_vif_list_command = cmd_type;
2684 update_params->vif_list_index = vif_index;
2685 update_params->func_bit_map =
2686 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2687 update_params->func_to_clear = 0;
2689 (cmd_type == VIF_LIST_RULE_GET) ?
2690 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2691 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2693 /* if ramrod can not be sent, respond to MCP immediately for
2694 * SET and GET requests (other are not triggered from MCP)
2696 rc = bnx2x_func_state_change(bp, &func_params);
2698 bnx2x_fw_command(bp, drv_msg_code, 0);
2703 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2705 struct afex_stats afex_stats;
2706 u32 func = BP_ABS_FUNC(bp);
2713 u32 addr_to_write, vifid, addrs, stats_type, i;
2715 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2716 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2718 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2719 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2722 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2723 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2724 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2726 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2728 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2732 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2733 addr_to_write = SHMEM2_RD(bp,
2734 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2735 stats_type = SHMEM2_RD(bp,
2736 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2739 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2742 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2744 /* write response to scratchpad, for MCP */
2745 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2746 REG_WR(bp, addr_to_write + i*sizeof(u32),
2747 *(((u32 *)(&afex_stats))+i));
2749 /* send ack message to MCP */
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2753 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2754 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2755 bp->mf_config[BP_VN(bp)] = mf_config;
2757 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2760 /* if VIF_SET is "enabled" */
2761 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2762 /* set rate limit directly to internal RAM */
2763 struct cmng_init_input cmng_input;
2764 struct rate_shaping_vars_per_vn m_rs_vn;
2765 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2766 u32 addr = BAR_XSTRORM_INTMEM +
2767 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2769 bp->mf_config[BP_VN(bp)] = mf_config;
2771 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2772 m_rs_vn.vn_counter.rate =
2773 cmng_input.vnic_max_rate[BP_VN(bp)];
2774 m_rs_vn.vn_counter.quota =
2775 (m_rs_vn.vn_counter.rate *
2776 RS_PERIODIC_TIMEOUT_USEC) / 8;
2778 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2780 /* read relevant values from mf_cfg struct in shmem */
2782 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2783 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2784 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2786 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2787 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2788 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2789 vlan_prio = (mf_config &
2790 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2791 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2792 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2795 func_mf_config[func].afex_config) &
2796 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2797 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2800 func_mf_config[func].afex_config) &
2801 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2802 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2804 /* send ramrod to FW, return in case of failure */
2805 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2809 bp->afex_def_vlan_tag = vlan_val;
2810 bp->afex_vlan_mode = vlan_mode;
2812 /* notify link down because BP->flags is disabled */
2813 bnx2x_link_report(bp);
2815 /* send INVALID VIF ramrod to FW */
2816 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2818 /* Reset the default afex VLAN */
2819 bp->afex_def_vlan_tag = -1;
2824 static void bnx2x_pmf_update(struct bnx2x *bp)
2826 int port = BP_PORT(bp);
2830 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2833 * We need the mb() to ensure the ordering between the writing to
2834 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2838 /* queue a periodic task */
2839 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2841 bnx2x_dcbx_pmf_update(bp);
2843 /* enable nig attention */
2844 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2845 if (bp->common.int_block == INT_BLOCK_HC) {
2846 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2847 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2848 } else if (!CHIP_IS_E1x(bp)) {
2849 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2850 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2853 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2861 * General service functions
2864 /* send the MCP a request, block until there is a reply */
2865 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2867 int mb_idx = BP_FW_MB_IDX(bp);
2871 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2873 mutex_lock(&bp->fw_mb_mutex);
2875 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2876 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2878 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2879 (command | seq), param);
2882 /* let the FW do it's magic ... */
2885 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2887 /* Give the FW up to 5 second (500*10ms) */
2888 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2890 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2891 cnt*delay, rc, seq);
2893 /* is this a reply to our command? */
2894 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2895 rc &= FW_MSG_CODE_MASK;
2898 BNX2X_ERR("FW failed to respond!\n");
2902 mutex_unlock(&bp->fw_mb_mutex);
2907 static void storm_memset_func_cfg(struct bnx2x *bp,
2908 struct tstorm_eth_function_common_config *tcfg,
2911 size_t size = sizeof(struct tstorm_eth_function_common_config);
2913 u32 addr = BAR_TSTRORM_INTMEM +
2914 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2916 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2919 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2921 if (CHIP_IS_E1x(bp)) {
2922 struct tstorm_eth_function_common_config tcfg = {0};
2924 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2927 /* Enable the function in the FW */
2928 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2929 storm_memset_func_en(bp, p->func_id, 1);
2932 if (p->func_flgs & FUNC_FLG_SPQ) {
2933 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2934 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2935 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2940 * bnx2x_get_common_flags - Return common flags
2944 * @zero_stats TRUE if statistics zeroing is needed
2946 * Return the flags that are common for the Tx-only and not normal connections.
2948 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2949 struct bnx2x_fastpath *fp,
2952 unsigned long flags = 0;
2954 /* PF driver will always initialize the Queue to an ACTIVE state */
2955 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2957 /* tx only connections collect statistics (on the same index as the
2958 * parent connection). The statistics are zeroed when the parent
2959 * connection is initialized.
2962 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2964 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2966 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2967 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2969 #ifdef BNX2X_STOP_ON_ERROR
2970 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2976 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2977 struct bnx2x_fastpath *fp,
2980 unsigned long flags = 0;
2982 /* calculate other queue flags */
2984 __set_bit(BNX2X_Q_FLG_OV, &flags);
2986 if (IS_FCOE_FP(fp)) {
2987 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2988 /* For FCoE - force usage of default priority (for afex) */
2989 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2992 if (!fp->disable_tpa) {
2993 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2994 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2995 if (fp->mode == TPA_MODE_GRO)
2996 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3000 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3001 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3004 /* Always set HW VLAN stripping */
3005 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3007 /* configure silent vlan removal */
3009 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3011 return flags | bnx2x_get_common_flags(bp, fp, true);
3014 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3015 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3018 gen_init->stat_id = bnx2x_stats_id(fp);
3019 gen_init->spcl_id = fp->cl_id;
3021 /* Always use mini-jumbo MTU for FCoE L2 ring */
3023 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3025 gen_init->mtu = bp->dev->mtu;
3027 gen_init->cos = cos;
3030 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3031 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3032 struct bnx2x_rxq_setup_params *rxq_init)
3036 u16 tpa_agg_size = 0;
3038 if (!fp->disable_tpa) {
3039 pause->sge_th_lo = SGE_TH_LO(bp);
3040 pause->sge_th_hi = SGE_TH_HI(bp);
3042 /* validate SGE ring has enough to cross high threshold */
3043 WARN_ON(bp->dropless_fc &&
3044 pause->sge_th_hi + FW_PREFETCH_CNT >
3045 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3047 tpa_agg_size = TPA_AGG_SIZE;
3048 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3050 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3051 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3052 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3055 /* pause - not for e1 */
3056 if (!CHIP_IS_E1(bp)) {
3057 pause->bd_th_lo = BD_TH_LO(bp);
3058 pause->bd_th_hi = BD_TH_HI(bp);
3060 pause->rcq_th_lo = RCQ_TH_LO(bp);
3061 pause->rcq_th_hi = RCQ_TH_HI(bp);
3063 * validate that rings have enough entries to cross
3066 WARN_ON(bp->dropless_fc &&
3067 pause->bd_th_hi + FW_PREFETCH_CNT >
3069 WARN_ON(bp->dropless_fc &&
3070 pause->rcq_th_hi + FW_PREFETCH_CNT >
3071 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3077 rxq_init->dscr_map = fp->rx_desc_mapping;
3078 rxq_init->sge_map = fp->rx_sge_mapping;
3079 rxq_init->rcq_map = fp->rx_comp_mapping;
3080 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3082 /* This should be a maximum number of data bytes that may be
3083 * placed on the BD (not including paddings).
3085 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3086 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3088 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3089 rxq_init->tpa_agg_sz = tpa_agg_size;
3090 rxq_init->sge_buf_sz = sge_sz;
3091 rxq_init->max_sges_pkt = max_sge;
3092 rxq_init->rss_engine_id = BP_FUNC(bp);
3093 rxq_init->mcast_engine_id = BP_FUNC(bp);
3095 /* Maximum number or simultaneous TPA aggregation for this Queue.
3097 * For PF Clients it should be the maximum available number.
3098 * VF driver(s) may want to define it to a smaller value.
3100 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3102 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3103 rxq_init->fw_sb_id = fp->fw_sb_id;
3106 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3108 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3109 /* configure silent vlan removal
3110 * if multi function mode is afex, then mask default vlan
3112 if (IS_MF_AFEX(bp)) {
3113 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3114 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3118 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3119 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3122 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3123 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3124 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3125 txq_init->fw_sb_id = fp->fw_sb_id;
3128 * set the tss leading client id for TX classification ==
3129 * leading RSS client id
3131 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3133 if (IS_FCOE_FP(fp)) {
3134 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3135 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3139 static void bnx2x_pf_init(struct bnx2x *bp)
3141 struct bnx2x_func_init_params func_init = {0};
3142 struct event_ring_data eq_data = { {0} };
3145 if (!CHIP_IS_E1x(bp)) {
3146 /* reset IGU PF statistics: MSIX + ATTN */
3148 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3149 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3150 (CHIP_MODE_IS_4_PORT(bp) ?
3151 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3153 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3154 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3155 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3156 (CHIP_MODE_IS_4_PORT(bp) ?
3157 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3160 /* function setup flags */
3161 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3163 /* This flag is relevant for E1x only.
3164 * E2 doesn't have a TPA configuration in a function level.
3166 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3168 func_init.func_flgs = flags;
3169 func_init.pf_id = BP_FUNC(bp);
3170 func_init.func_id = BP_FUNC(bp);
3171 func_init.spq_map = bp->spq_mapping;
3172 func_init.spq_prod = bp->spq_prod_idx;
3174 bnx2x_func_init(bp, &func_init);
3176 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3179 * Congestion management values depend on the link rate
3180 * There is no active link so initial link rate is set to 10 Gbps.
3181 * When the link comes up The congestion management values are
3182 * re-calculated according to the actual link rate.
3184 bp->link_vars.line_speed = SPEED_10000;
3185 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3187 /* Only the PMF sets the HW */
3189 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3191 /* init Event Queue - PCI bus guarantees correct endianity*/
3192 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3193 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3194 eq_data.producer = bp->eq_prod;
3195 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3196 eq_data.sb_id = DEF_SB_ID;
3197 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3200 static void bnx2x_e1h_disable(struct bnx2x *bp)
3202 int port = BP_PORT(bp);
3204 bnx2x_tx_disable(bp);
3206 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3209 static void bnx2x_e1h_enable(struct bnx2x *bp)
3211 int port = BP_PORT(bp);
3213 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3215 /* Tx queue should be only re-enabled */
3216 netif_tx_wake_all_queues(bp->dev);
3219 * Should not call netif_carrier_on since it will be called if the link
3220 * is up when checking for link state
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3228 struct eth_stats_info *ether_stat =
3229 &bp->slowpath->drv_info_to_mcp.ether_stat;
3230 struct bnx2x_vlan_mac_obj *mac_obj =
3231 &bp->sp_objs->mac_obj;
3234 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3235 ETH_STAT_INFO_VERSION_LEN);
3237 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3238 * mac_local field in ether_stat struct. The base address is offset by 2
3239 * bytes to account for the field being 8 bytes but a mac address is
3240 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3241 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3242 * allocated by the ether_stat struct, so the macs will land in their
3245 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3246 memset(ether_stat->mac_local + i, 0,
3247 sizeof(ether_stat->mac_local[0]));
3248 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3249 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3250 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3252 ether_stat->mtu_size = bp->dev->mtu;
3253 if (bp->dev->features & NETIF_F_RXCSUM)
3254 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3255 if (bp->dev->features & NETIF_F_TSO)
3256 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3257 ether_stat->feature_flags |= bp->common.boot_mode;
3259 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3261 ether_stat->txq_size = bp->tx_ring_size;
3262 ether_stat->rxq_size = bp->rx_ring_size;
3265 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3267 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3268 struct fcoe_stats_info *fcoe_stat =
3269 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3271 if (!CNIC_LOADED(bp))
3274 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3276 fcoe_stat->qos_priority =
3277 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3279 /* insert FCoE stats from ramrod response */
3281 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3282 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3283 tstorm_queue_statistics;
3285 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3286 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3287 xstorm_queue_statistics;
3289 struct fcoe_statistics_params *fw_fcoe_stat =
3290 &bp->fw_stats_data->fcoe;
3292 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3293 fcoe_stat->rx_bytes_lo,
3294 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3296 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3297 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3298 fcoe_stat->rx_bytes_lo,
3299 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3301 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3302 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3303 fcoe_stat->rx_bytes_lo,
3304 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3306 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3307 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3308 fcoe_stat->rx_bytes_lo,
3309 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3311 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3312 fcoe_stat->rx_frames_lo,
3313 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3315 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3316 fcoe_stat->rx_frames_lo,
3317 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3319 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3320 fcoe_stat->rx_frames_lo,
3321 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3323 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3324 fcoe_stat->rx_frames_lo,
3325 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3327 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3328 fcoe_stat->tx_bytes_lo,
3329 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3331 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3332 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3333 fcoe_stat->tx_bytes_lo,
3334 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3336 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3337 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3338 fcoe_stat->tx_bytes_lo,
3339 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3341 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3342 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3343 fcoe_stat->tx_bytes_lo,
3344 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3346 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3347 fcoe_stat->tx_frames_lo,
3348 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3350 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3351 fcoe_stat->tx_frames_lo,
3352 fcoe_q_xstorm_stats->ucast_pkts_sent);
3354 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3355 fcoe_stat->tx_frames_lo,
3356 fcoe_q_xstorm_stats->bcast_pkts_sent);
3358 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3359 fcoe_stat->tx_frames_lo,
3360 fcoe_q_xstorm_stats->mcast_pkts_sent);
3363 /* ask L5 driver to add data to the struct */
3364 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3367 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3369 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3370 struct iscsi_stats_info *iscsi_stat =
3371 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3373 if (!CNIC_LOADED(bp))
3376 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3379 iscsi_stat->qos_priority =
3380 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3382 /* ask L5 driver to add data to the struct */
3383 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3386 /* called due to MCP event (on pmf):
3387 * reread new bandwidth configuration
3389 * notify others function about the change
3391 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3393 if (bp->link_vars.link_up) {
3394 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3395 bnx2x_link_sync_notify(bp);
3397 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3400 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3402 bnx2x_config_mf_bw(bp);
3403 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3406 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3408 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3409 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3412 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3414 enum drv_info_opcode op_code;
3415 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3417 /* if drv_info version supported by MFW doesn't match - send NACK */
3418 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3419 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3423 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3424 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3426 memset(&bp->slowpath->drv_info_to_mcp, 0,
3427 sizeof(union drv_info_to_mcp));
3430 case ETH_STATS_OPCODE:
3431 bnx2x_drv_info_ether_stat(bp);
3433 case FCOE_STATS_OPCODE:
3434 bnx2x_drv_info_fcoe_stat(bp);
3436 case ISCSI_STATS_OPCODE:
3437 bnx2x_drv_info_iscsi_stat(bp);
3440 /* if op code isn't supported - send NACK */
3441 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3445 /* if we got drv_info attn from MFW then these fields are defined in
3448 SHMEM2_WR(bp, drv_info_host_addr_lo,
3449 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3450 SHMEM2_WR(bp, drv_info_host_addr_hi,
3451 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3453 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3456 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3458 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3460 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3463 * This is the only place besides the function initialization
3464 * where the bp->flags can change so it is done without any
3467 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3468 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3469 bp->flags |= MF_FUNC_DIS;
3471 bnx2x_e1h_disable(bp);
3473 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3474 bp->flags &= ~MF_FUNC_DIS;
3476 bnx2x_e1h_enable(bp);
3478 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3480 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3481 bnx2x_config_mf_bw(bp);
3482 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3485 /* Report results to MCP */
3487 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3489 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3492 /* must be called under the spq lock */
3493 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3495 struct eth_spe *next_spe = bp->spq_prod_bd;
3497 if (bp->spq_prod_bd == bp->spq_last_bd) {
3498 bp->spq_prod_bd = bp->spq;
3499 bp->spq_prod_idx = 0;
3500 DP(BNX2X_MSG_SP, "end of spq\n");
3508 /* must be called under the spq lock */
3509 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3511 int func = BP_FUNC(bp);
3514 * Make sure that BD data is updated before writing the producer:
3515 * BD data is written to the memory, the producer is read from the
3516 * memory, thus we need a full memory barrier to ensure the ordering.
3520 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3526 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3528 * @cmd: command to check
3529 * @cmd_type: command type
3531 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3533 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3534 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3535 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3536 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3537 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3538 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3539 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3546 * bnx2x_sp_post - place a single command on an SP ring
3548 * @bp: driver handle
3549 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3550 * @cid: SW CID the command is related to
3551 * @data_hi: command private data address (high 32 bits)
3552 * @data_lo: command private data address (low 32 bits)
3553 * @cmd_type: command type (e.g. NONE, ETH)
3555 * SP data is handled as if it's always an address pair, thus data fields are
3556 * not swapped to little endian in upper functions. Instead this function swaps
3557 * data as if it's two u32 fields.
3559 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3560 u32 data_hi, u32 data_lo, int cmd_type)
3562 struct eth_spe *spe;
3564 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3566 #ifdef BNX2X_STOP_ON_ERROR
3567 if (unlikely(bp->panic)) {
3568 BNX2X_ERR("Can't post SP when there is panic\n");
3573 spin_lock_bh(&bp->spq_lock);
3576 if (!atomic_read(&bp->eq_spq_left)) {
3577 BNX2X_ERR("BUG! EQ ring full!\n");
3578 spin_unlock_bh(&bp->spq_lock);
3582 } else if (!atomic_read(&bp->cq_spq_left)) {
3583 BNX2X_ERR("BUG! SPQ ring full!\n");
3584 spin_unlock_bh(&bp->spq_lock);
3589 spe = bnx2x_sp_get_next(bp);
3591 /* CID needs port number to be encoded int it */
3592 spe->hdr.conn_and_cmd_data =
3593 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3596 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3598 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3599 SPE_HDR_FUNCTION_ID);
3601 spe->hdr.type = cpu_to_le16(type);
3603 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3604 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3607 * It's ok if the actual decrement is issued towards the memory
3608 * somewhere between the spin_lock and spin_unlock. Thus no
3609 * more explicit memory barrier is needed.
3612 atomic_dec(&bp->eq_spq_left);
3614 atomic_dec(&bp->cq_spq_left);
3617 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3618 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3619 (u32)(U64_LO(bp->spq_mapping) +
3620 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3621 HW_CID(bp, cid), data_hi, data_lo, type,
3622 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3624 bnx2x_sp_prod_update(bp);
3625 spin_unlock_bh(&bp->spq_lock);
3629 /* acquire split MCP access lock register */
3630 static int bnx2x_acquire_alr(struct bnx2x *bp)
3636 for (j = 0; j < 1000; j++) {
3637 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3638 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3639 if (val & MCPR_ACCESS_LOCK_LOCK)
3642 usleep_range(5000, 10000);
3644 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3645 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3652 /* release split MCP access lock register */
3653 static void bnx2x_release_alr(struct bnx2x *bp)
3655 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3658 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3659 #define BNX2X_DEF_SB_IDX 0x0002
3661 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3663 struct host_sp_status_block *def_sb = bp->def_status_blk;
3666 barrier(); /* status block is written to by the chip */
3667 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3668 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3669 rc |= BNX2X_DEF_SB_ATT_IDX;
3672 if (bp->def_idx != def_sb->sp_sb.running_index) {
3673 bp->def_idx = def_sb->sp_sb.running_index;
3674 rc |= BNX2X_DEF_SB_IDX;
3677 /* Do not reorder: indices reading should complete before handling */
3683 * slow path service functions
3686 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3688 int port = BP_PORT(bp);
3689 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3690 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3691 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3692 NIG_REG_MASK_INTERRUPT_PORT0;
3697 if (bp->attn_state & asserted)
3698 BNX2X_ERR("IGU ERROR\n");
3700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3701 aeu_mask = REG_RD(bp, aeu_addr);
3703 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3704 aeu_mask, asserted);
3705 aeu_mask &= ~(asserted & 0x3ff);
3706 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3708 REG_WR(bp, aeu_addr, aeu_mask);
3709 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3711 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3712 bp->attn_state |= asserted;
3713 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3715 if (asserted & ATTN_HARD_WIRED_MASK) {
3716 if (asserted & ATTN_NIG_FOR_FUNC) {
3718 bnx2x_acquire_phy_lock(bp);
3720 /* save nig interrupt mask */
3721 nig_mask = REG_RD(bp, nig_int_mask_addr);
3723 /* If nig_mask is not set, no need to call the update
3727 REG_WR(bp, nig_int_mask_addr, 0);
3729 bnx2x_link_attn(bp);
3732 /* handle unicore attn? */
3734 if (asserted & ATTN_SW_TIMER_4_FUNC)
3735 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3737 if (asserted & GPIO_2_FUNC)
3738 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3740 if (asserted & GPIO_3_FUNC)
3741 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3743 if (asserted & GPIO_4_FUNC)
3744 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3747 if (asserted & ATTN_GENERAL_ATTN_1) {
3748 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3749 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3751 if (asserted & ATTN_GENERAL_ATTN_2) {
3752 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3753 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3755 if (asserted & ATTN_GENERAL_ATTN_3) {
3756 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3757 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3760 if (asserted & ATTN_GENERAL_ATTN_4) {
3761 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3762 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3764 if (asserted & ATTN_GENERAL_ATTN_5) {
3765 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3766 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3768 if (asserted & ATTN_GENERAL_ATTN_6) {
3769 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3770 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3774 } /* if hardwired */
3776 if (bp->common.int_block == INT_BLOCK_HC)
3777 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3778 COMMAND_REG_ATTN_BITS_SET);
3780 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3782 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3783 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3784 REG_WR(bp, reg_addr, asserted);
3786 /* now set back the mask */
3787 if (asserted & ATTN_NIG_FOR_FUNC) {
3788 /* Verify that IGU ack through BAR was written before restoring
3789 * NIG mask. This loop should exit after 2-3 iterations max.
3791 if (bp->common.int_block != INT_BLOCK_HC) {
3792 u32 cnt = 0, igu_acked;
3794 igu_acked = REG_RD(bp,
3795 IGU_REG_ATTENTION_ACK_BITS);
3796 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3797 (++cnt < MAX_IGU_ATTN_ACK_TO));
3800 "Failed to verify IGU ack on time\n");
3803 REG_WR(bp, nig_int_mask_addr, nig_mask);
3804 bnx2x_release_phy_lock(bp);
3808 static void bnx2x_fan_failure(struct bnx2x *bp)
3810 int port = BP_PORT(bp);
3812 /* mark the failure */
3815 dev_info.port_hw_config[port].external_phy_config);
3817 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3818 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3819 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3822 /* log the failure */
3823 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3824 "Please contact OEM Support for assistance\n");
3826 /* Schedule device reset (unload)
3827 * This is due to some boards consuming sufficient power when driver is
3828 * up to overheat if fan fails.
3830 smp_mb__before_clear_bit();
3831 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3832 smp_mb__after_clear_bit();
3833 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3836 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3838 int port = BP_PORT(bp);
3842 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3843 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3845 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3847 val = REG_RD(bp, reg_offset);
3848 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3849 REG_WR(bp, reg_offset, val);
3851 BNX2X_ERR("SPIO5 hw attention\n");
3853 /* Fan failure attention */
3854 bnx2x_hw_reset_phy(&bp->link_params);
3855 bnx2x_fan_failure(bp);
3858 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3859 bnx2x_acquire_phy_lock(bp);
3860 bnx2x_handle_module_detect_int(&bp->link_params);
3861 bnx2x_release_phy_lock(bp);
3864 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3866 val = REG_RD(bp, reg_offset);
3867 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3868 REG_WR(bp, reg_offset, val);
3870 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3871 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3876 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3880 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3882 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3883 BNX2X_ERR("DB hw attention 0x%x\n", val);
3884 /* DORQ discard attention */
3886 BNX2X_ERR("FATAL error from DORQ\n");
3889 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3891 int port = BP_PORT(bp);
3894 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3895 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3897 val = REG_RD(bp, reg_offset);
3898 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3899 REG_WR(bp, reg_offset, val);
3901 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3902 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3907 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3911 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3913 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3914 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3915 /* CFC error attention */
3917 BNX2X_ERR("FATAL error from CFC\n");
3920 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3921 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3922 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3923 /* RQ_USDMDP_FIFO_OVERFLOW */
3925 BNX2X_ERR("FATAL error from PXP\n");
3927 if (!CHIP_IS_E1x(bp)) {
3928 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3929 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3933 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3935 int port = BP_PORT(bp);
3938 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3939 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3941 val = REG_RD(bp, reg_offset);
3942 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3943 REG_WR(bp, reg_offset, val);
3945 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3946 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3951 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3955 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3957 if (attn & BNX2X_PMF_LINK_ASSERT) {
3958 int func = BP_FUNC(bp);
3960 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3961 bnx2x_read_mf_cfg(bp);
3962 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3963 func_mf_config[BP_ABS_FUNC(bp)].config);
3965 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3966 if (val & DRV_STATUS_DCC_EVENT_MASK)
3968 (val & DRV_STATUS_DCC_EVENT_MASK));
3970 if (val & DRV_STATUS_SET_MF_BW)
3971 bnx2x_set_mf_bw(bp);
3973 if (val & DRV_STATUS_DRV_INFO_REQ)
3974 bnx2x_handle_drv_info_req(bp);
3976 if (val & DRV_STATUS_VF_DISABLED)
3977 bnx2x_vf_handle_flr_event(bp);
3979 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3980 bnx2x_pmf_update(bp);
3983 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3984 bp->dcbx_enabled > 0)
3985 /* start dcbx state machine */
3986 bnx2x_dcbx_set_params(bp,
3987 BNX2X_DCBX_STATE_NEG_RECEIVED);
3988 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3989 bnx2x_handle_afex_cmd(bp,
3990 val & DRV_STATUS_AFEX_EVENT_MASK);
3991 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3992 bnx2x_handle_eee_event(bp);
3993 if (bp->link_vars.periodic_flags &
3994 PERIODIC_FLAGS_LINK_EVENT) {
3995 /* sync with link */
3996 bnx2x_acquire_phy_lock(bp);
3997 bp->link_vars.periodic_flags &=
3998 ~PERIODIC_FLAGS_LINK_EVENT;
3999 bnx2x_release_phy_lock(bp);
4001 bnx2x_link_sync_notify(bp);
4002 bnx2x_link_report(bp);
4004 /* Always call it here: bnx2x_link_report() will
4005 * prevent the link indication duplication.
4007 bnx2x__link_status_update(bp);
4008 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4010 BNX2X_ERR("MC assert!\n");
4011 bnx2x_mc_assert(bp);
4012 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4013 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4014 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4015 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4018 } else if (attn & BNX2X_MCP_ASSERT) {
4020 BNX2X_ERR("MCP assert!\n");
4021 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4025 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4028 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4029 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4030 if (attn & BNX2X_GRC_TIMEOUT) {
4031 val = CHIP_IS_E1(bp) ? 0 :
4032 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4033 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4035 if (attn & BNX2X_GRC_RSV) {
4036 val = CHIP_IS_E1(bp) ? 0 :
4037 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4038 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4040 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4046 * 0-7 - Engine0 load counter.
4047 * 8-15 - Engine1 load counter.
4048 * 16 - Engine0 RESET_IN_PROGRESS bit.
4049 * 17 - Engine1 RESET_IN_PROGRESS bit.
4050 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4052 * 19 - Engine1 ONE_IS_LOADED.
4053 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4054 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4055 * just the one belonging to its engine).
4058 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4060 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4061 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4062 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4063 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4064 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4065 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4066 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4069 * Set the GLOBAL_RESET bit.
4071 * Should be run under rtnl lock
4073 void bnx2x_set_reset_global(struct bnx2x *bp)
4076 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4077 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4078 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4079 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4083 * Clear the GLOBAL_RESET bit.
4085 * Should be run under rtnl lock
4087 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4091 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4092 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4093 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4097 * Checks the GLOBAL_RESET bit.
4099 * should be run under rtnl lock
4101 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4103 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4105 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4106 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4110 * Clear RESET_IN_PROGRESS bit for the current engine.
4112 * Should be run under rtnl lock
4114 static void bnx2x_set_reset_done(struct bnx2x *bp)
4117 u32 bit = BP_PATH(bp) ?
4118 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4119 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4120 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4124 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4126 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4130 * Set RESET_IN_PROGRESS for the current engine.
4132 * should be run under rtnl lock
4134 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4137 u32 bit = BP_PATH(bp) ?
4138 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4139 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4140 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4144 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4145 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4149 * Checks the RESET_IN_PROGRESS bit for the given engine.
4150 * should be run under rtnl lock
4152 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4154 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4156 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4158 /* return false if bit is set */
4159 return (val & bit) ? false : true;
4163 * set pf load for the current pf.
4165 * should be run under rtnl lock
4167 void bnx2x_set_pf_load(struct bnx2x *bp)
4170 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4171 BNX2X_PATH0_LOAD_CNT_MASK;
4172 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4173 BNX2X_PATH0_LOAD_CNT_SHIFT;
4175 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4176 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4178 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4180 /* get the current counter value */
4181 val1 = (val & mask) >> shift;
4183 /* set bit of that PF */
4184 val1 |= (1 << bp->pf_num);
4186 /* clear the old value */
4189 /* set the new one */
4190 val |= ((val1 << shift) & mask);
4192 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4193 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4197 * bnx2x_clear_pf_load - clear pf load mark
4199 * @bp: driver handle
4201 * Should be run under rtnl lock.
4202 * Decrements the load counter for the current engine. Returns
4203 * whether other functions are still loaded
4205 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4208 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4209 BNX2X_PATH0_LOAD_CNT_MASK;
4210 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4211 BNX2X_PATH0_LOAD_CNT_SHIFT;
4213 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4214 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4215 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4217 /* get the current counter value */
4218 val1 = (val & mask) >> shift;
4220 /* clear bit of that PF */
4221 val1 &= ~(1 << bp->pf_num);
4223 /* clear the old value */
4226 /* set the new one */
4227 val |= ((val1 << shift) & mask);
4229 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4230 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4235 * Read the load status for the current engine.
4237 * should be run under rtnl lock
4239 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4241 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4242 BNX2X_PATH0_LOAD_CNT_MASK);
4243 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4244 BNX2X_PATH0_LOAD_CNT_SHIFT);
4245 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4247 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4249 val = (val & mask) >> shift;
4251 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4257 static void _print_parity(struct bnx2x *bp, u32 reg)
4259 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4262 static void _print_next_block(int idx, const char *blk)
4264 pr_cont("%s%s", idx ? ", " : "", blk);
4267 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4268 int par_num, bool print)
4272 for (i = 0; sig; i++) {
4273 cur_bit = ((u32)0x1 << i);
4274 if (sig & cur_bit) {
4276 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4278 _print_next_block(par_num++, "BRB");
4280 BRB1_REG_BRB1_PRTY_STS);
4283 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4285 _print_next_block(par_num++, "PARSER");
4286 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4289 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4291 _print_next_block(par_num++, "TSDM");
4293 TSDM_REG_TSDM_PRTY_STS);
4296 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4298 _print_next_block(par_num++,
4300 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4303 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4305 _print_next_block(par_num++, "TCM");
4307 TCM_REG_TCM_PRTY_STS);
4310 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4312 _print_next_block(par_num++, "TSEMI");
4314 TSEM_REG_TSEM_PRTY_STS_0);
4316 TSEM_REG_TSEM_PRTY_STS_1);
4319 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4321 _print_next_block(par_num++, "XPB");
4322 _print_parity(bp, GRCBASE_XPB +
4323 PB_REG_PB_PRTY_STS);
4336 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4337 int par_num, bool *global,
4342 for (i = 0; sig; i++) {
4343 cur_bit = ((u32)0x1 << i);
4344 if (sig & cur_bit) {
4346 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4348 _print_next_block(par_num++, "PBF");
4349 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4352 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4354 _print_next_block(par_num++, "QM");
4355 _print_parity(bp, QM_REG_QM_PRTY_STS);
4358 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4360 _print_next_block(par_num++, "TM");
4361 _print_parity(bp, TM_REG_TM_PRTY_STS);
4364 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4366 _print_next_block(par_num++, "XSDM");
4368 XSDM_REG_XSDM_PRTY_STS);
4371 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4373 _print_next_block(par_num++, "XCM");
4374 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4377 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4379 _print_next_block(par_num++, "XSEMI");
4381 XSEM_REG_XSEM_PRTY_STS_0);
4383 XSEM_REG_XSEM_PRTY_STS_1);
4386 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4388 _print_next_block(par_num++,
4391 DORQ_REG_DORQ_PRTY_STS);
4394 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4396 _print_next_block(par_num++, "NIG");
4397 if (CHIP_IS_E1x(bp)) {
4399 NIG_REG_NIG_PRTY_STS);
4402 NIG_REG_NIG_PRTY_STS_0);
4404 NIG_REG_NIG_PRTY_STS_1);
4408 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4410 _print_next_block(par_num++,
4414 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4416 _print_next_block(par_num++, "DEBUG");
4417 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4420 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4422 _print_next_block(par_num++, "USDM");
4424 USDM_REG_USDM_PRTY_STS);
4427 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4429 _print_next_block(par_num++, "UCM");
4430 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4433 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4435 _print_next_block(par_num++, "USEMI");
4437 USEM_REG_USEM_PRTY_STS_0);
4439 USEM_REG_USEM_PRTY_STS_1);
4442 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4444 _print_next_block(par_num++, "UPB");
4445 _print_parity(bp, GRCBASE_UPB +
4446 PB_REG_PB_PRTY_STS);
4449 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4451 _print_next_block(par_num++, "CSDM");
4453 CSDM_REG_CSDM_PRTY_STS);
4456 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4458 _print_next_block(par_num++, "CCM");
4459 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4472 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4473 int par_num, bool print)
4477 for (i = 0; sig; i++) {
4478 cur_bit = ((u32)0x1 << i);
4479 if (sig & cur_bit) {
4481 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4483 _print_next_block(par_num++, "CSEMI");
4485 CSEM_REG_CSEM_PRTY_STS_0);
4487 CSEM_REG_CSEM_PRTY_STS_1);
4490 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4492 _print_next_block(par_num++, "PXP");
4493 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4495 PXP2_REG_PXP2_PRTY_STS_0);
4497 PXP2_REG_PXP2_PRTY_STS_1);
4500 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4502 _print_next_block(par_num++,
4503 "PXPPCICLOCKCLIENT");
4505 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4507 _print_next_block(par_num++, "CFC");
4509 CFC_REG_CFC_PRTY_STS);
4512 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4514 _print_next_block(par_num++, "CDU");
4515 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4518 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4520 _print_next_block(par_num++, "DMAE");
4522 DMAE_REG_DMAE_PRTY_STS);
4525 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4527 _print_next_block(par_num++, "IGU");
4528 if (CHIP_IS_E1x(bp))
4530 HC_REG_HC_PRTY_STS);
4533 IGU_REG_IGU_PRTY_STS);
4536 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4538 _print_next_block(par_num++, "MISC");
4540 MISC_REG_MISC_PRTY_STS);
4553 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4554 bool *global, bool print)
4558 for (i = 0; sig; i++) {
4559 cur_bit = ((u32)0x1 << i);
4560 if (sig & cur_bit) {
4562 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4564 _print_next_block(par_num++, "MCP ROM");
4567 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4569 _print_next_block(par_num++,
4573 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4575 _print_next_block(par_num++,
4579 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4581 _print_next_block(par_num++,
4595 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4596 int par_num, bool print)
4600 for (i = 0; sig; i++) {
4601 cur_bit = ((u32)0x1 << i);
4602 if (sig & cur_bit) {
4604 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4606 _print_next_block(par_num++, "PGLUE_B");
4608 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4611 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4613 _print_next_block(par_num++, "ATC");
4615 ATC_REG_ATC_PRTY_STS);
4628 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4631 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4632 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4633 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4634 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4635 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4637 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4638 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4639 sig[0] & HW_PRTY_ASSERT_SET_0,
4640 sig[1] & HW_PRTY_ASSERT_SET_1,
4641 sig[2] & HW_PRTY_ASSERT_SET_2,
4642 sig[3] & HW_PRTY_ASSERT_SET_3,
4643 sig[4] & HW_PRTY_ASSERT_SET_4);
4646 "Parity errors detected in blocks: ");
4647 par_num = bnx2x_check_blocks_with_parity0(bp,
4648 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4649 par_num = bnx2x_check_blocks_with_parity1(bp,
4650 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4651 par_num = bnx2x_check_blocks_with_parity2(bp,
4652 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4653 par_num = bnx2x_check_blocks_with_parity3(
4654 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4655 par_num = bnx2x_check_blocks_with_parity4(bp,
4656 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4667 * bnx2x_chk_parity_attn - checks for parity attentions.
4669 * @bp: driver handle
4670 * @global: true if there was a global attention
4671 * @print: show parity attention in syslog
4673 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4675 struct attn_route attn = { {0} };
4676 int port = BP_PORT(bp);
4678 attn.sig[0] = REG_RD(bp,
4679 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4681 attn.sig[1] = REG_RD(bp,
4682 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4684 attn.sig[2] = REG_RD(bp,
4685 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4687 attn.sig[3] = REG_RD(bp,
4688 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4691 if (!CHIP_IS_E1x(bp))
4692 attn.sig[4] = REG_RD(bp,
4693 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4696 return bnx2x_parity_attn(bp, global, print, attn.sig);
4699 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4702 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4704 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4705 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4706 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4707 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4708 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4709 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4710 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4711 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4712 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4713 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4715 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4716 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4718 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4719 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4720 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4721 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4722 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4723 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4724 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4725 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4727 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4728 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4729 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4730 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4731 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4732 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4733 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4734 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4735 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4736 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4737 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4738 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4739 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4740 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4741 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4744 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4745 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4746 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4747 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4748 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4752 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4754 struct attn_route attn, *group_mask;
4755 int port = BP_PORT(bp);
4760 bool global = false;
4762 /* need to take HW lock because MCP or other port might also
4763 try to handle this event */
4764 bnx2x_acquire_alr(bp);
4766 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4767 #ifndef BNX2X_STOP_ON_ERROR
4768 bp->recovery_state = BNX2X_RECOVERY_INIT;
4769 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4770 /* Disable HW interrupts */
4771 bnx2x_int_disable(bp);
4772 /* In case of parity errors don't handle attentions so that
4773 * other function would "see" parity errors.
4778 bnx2x_release_alr(bp);
4782 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4783 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4784 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4785 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4786 if (!CHIP_IS_E1x(bp))
4788 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4792 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4793 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4795 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4796 if (deasserted & (1 << index)) {
4797 group_mask = &bp->attn_group[index];
4799 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4801 group_mask->sig[0], group_mask->sig[1],
4802 group_mask->sig[2], group_mask->sig[3],
4803 group_mask->sig[4]);
4805 bnx2x_attn_int_deasserted4(bp,
4806 attn.sig[4] & group_mask->sig[4]);
4807 bnx2x_attn_int_deasserted3(bp,
4808 attn.sig[3] & group_mask->sig[3]);
4809 bnx2x_attn_int_deasserted1(bp,
4810 attn.sig[1] & group_mask->sig[1]);
4811 bnx2x_attn_int_deasserted2(bp,
4812 attn.sig[2] & group_mask->sig[2]);
4813 bnx2x_attn_int_deasserted0(bp,
4814 attn.sig[0] & group_mask->sig[0]);
4818 bnx2x_release_alr(bp);
4820 if (bp->common.int_block == INT_BLOCK_HC)
4821 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4822 COMMAND_REG_ATTN_BITS_CLR);
4824 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4827 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4828 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4829 REG_WR(bp, reg_addr, val);
4831 if (~bp->attn_state & deasserted)
4832 BNX2X_ERR("IGU ERROR\n");
4834 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4835 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4837 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4838 aeu_mask = REG_RD(bp, reg_addr);
4840 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4841 aeu_mask, deasserted);
4842 aeu_mask |= (deasserted & 0x3ff);
4843 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4845 REG_WR(bp, reg_addr, aeu_mask);
4846 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4848 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4849 bp->attn_state &= ~deasserted;
4850 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4853 static void bnx2x_attn_int(struct bnx2x *bp)
4855 /* read local copy of bits */
4856 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4858 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4860 u32 attn_state = bp->attn_state;
4862 /* look for changed bits */
4863 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4864 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4867 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4868 attn_bits, attn_ack, asserted, deasserted);
4870 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4871 BNX2X_ERR("BAD attention state\n");
4873 /* handle bits that were raised */
4875 bnx2x_attn_int_asserted(bp, asserted);
4878 bnx2x_attn_int_deasserted(bp, deasserted);
4881 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4882 u16 index, u8 op, u8 update)
4884 u32 igu_addr = bp->igu_base_addr;
4885 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4886 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4890 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4892 /* No memory barriers */
4893 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4894 mmiowb(); /* keep prod updates ordered */
4897 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4898 union event_ring_elem *elem)
4900 u8 err = elem->message.error;
4902 if (!bp->cnic_eth_dev.starting_cid ||
4903 (cid < bp->cnic_eth_dev.starting_cid &&
4904 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4907 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4909 if (unlikely(err)) {
4911 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4913 bnx2x_panic_dump(bp, false);
4915 bnx2x_cnic_cfc_comp(bp, cid, err);
4919 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4921 struct bnx2x_mcast_ramrod_params rparam;
4924 memset(&rparam, 0, sizeof(rparam));
4926 rparam.mcast_obj = &bp->mcast_obj;
4928 netif_addr_lock_bh(bp->dev);
4930 /* Clear pending state for the last command */
4931 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4933 /* If there are pending mcast commands - send them */
4934 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4935 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4937 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4941 netif_addr_unlock_bh(bp->dev);
4944 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4945 union event_ring_elem *elem)
4947 unsigned long ramrod_flags = 0;
4949 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4950 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4952 /* Always push next commands out, don't wait here */
4953 __set_bit(RAMROD_CONT, &ramrod_flags);
4955 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4956 >> BNX2X_SWCID_SHIFT) {
4957 case BNX2X_FILTER_MAC_PENDING:
4958 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4959 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4960 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4962 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4965 case BNX2X_FILTER_MCAST_PENDING:
4966 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4967 /* This is only relevant for 57710 where multicast MACs are
4968 * configured as unicast MACs using the same ramrod.
4970 bnx2x_handle_mcast_eqe(bp);
4973 BNX2X_ERR("Unsupported classification command: %d\n",
4974 elem->message.data.eth_event.echo);
4978 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4981 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4983 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4986 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4988 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4990 netif_addr_lock_bh(bp->dev);
4992 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4994 /* Send rx_mode command again if was requested */
4995 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4996 bnx2x_set_storm_rx_mode(bp);
4997 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4999 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5000 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5002 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5004 netif_addr_unlock_bh(bp->dev);
5007 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5008 union event_ring_elem *elem)
5010 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5012 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5013 elem->message.data.vif_list_event.func_bit_map);
5014 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5015 elem->message.data.vif_list_event.func_bit_map);
5016 } else if (elem->message.data.vif_list_event.echo ==
5017 VIF_LIST_RULE_SET) {
5018 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5019 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5023 /* called with rtnl_lock */
5024 static void bnx2x_after_function_update(struct bnx2x *bp)
5027 struct bnx2x_fastpath *fp;
5028 struct bnx2x_queue_state_params queue_params = {NULL};
5029 struct bnx2x_queue_update_params *q_update_params =
5030 &queue_params.params.update;
5032 /* Send Q update command with afex vlan removal values for all Qs */
5033 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5035 /* set silent vlan removal values according to vlan mode */
5036 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5037 &q_update_params->update_flags);
5038 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5039 &q_update_params->update_flags);
5040 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5042 /* in access mode mark mask and value are 0 to strip all vlans */
5043 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5044 q_update_params->silent_removal_value = 0;
5045 q_update_params->silent_removal_mask = 0;
5047 q_update_params->silent_removal_value =
5048 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5049 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5052 for_each_eth_queue(bp, q) {
5053 /* Set the appropriate Queue object */
5055 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5057 /* send the ramrod */
5058 rc = bnx2x_queue_state_change(bp, &queue_params);
5060 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5064 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5065 fp = &bp->fp[FCOE_IDX(bp)];
5066 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5068 /* clear pending completion bit */
5069 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5071 /* mark latest Q bit */
5072 smp_mb__before_clear_bit();
5073 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5074 smp_mb__after_clear_bit();
5076 /* send Q update ramrod for FCoE Q */
5077 rc = bnx2x_queue_state_change(bp, &queue_params);
5079 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5082 /* If no FCoE ring - ACK MCP now */
5083 bnx2x_link_report(bp);
5084 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5088 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5089 struct bnx2x *bp, u32 cid)
5091 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5093 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5094 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5096 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5099 static void bnx2x_eq_int(struct bnx2x *bp)
5101 u16 hw_cons, sw_cons, sw_prod;
5102 union event_ring_elem *elem;
5106 int rc, spqe_cnt = 0;
5107 struct bnx2x_queue_sp_obj *q_obj;
5108 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5109 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5111 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5113 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5114 * when we get the next-page we need to adjust so the loop
5115 * condition below will be met. The next element is the size of a
5116 * regular element and hence incrementing by 1
5118 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5121 /* This function may never run in parallel with itself for a
5122 * specific bp, thus there is no need in "paired" read memory
5125 sw_cons = bp->eq_cons;
5126 sw_prod = bp->eq_prod;
5128 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5129 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5131 for (; sw_cons != hw_cons;
5132 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5134 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5136 rc = bnx2x_iov_eq_sp_event(bp, elem);
5138 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5143 /* elem CID originates from FW; actually LE */
5144 cid = SW_CID((__force __le32)
5145 elem->message.data.cfc_del_event.cid);
5146 opcode = elem->message.opcode;
5148 /* handle eq element */
5150 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5151 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5152 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5155 case EVENT_RING_OPCODE_STAT_QUERY:
5156 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5157 "got statistics comp event %d\n",
5159 /* nothing to do with stats comp */
5162 case EVENT_RING_OPCODE_CFC_DEL:
5163 /* handle according to cid range */
5165 * we may want to verify here that the bp state is
5169 "got delete ramrod for MULTI[%d]\n", cid);
5171 if (CNIC_LOADED(bp) &&
5172 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5175 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5177 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5182 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5183 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5184 if (f_obj->complete_cmd(bp, f_obj,
5185 BNX2X_F_CMD_TX_STOP))
5187 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5190 case EVENT_RING_OPCODE_START_TRAFFIC:
5191 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5192 if (f_obj->complete_cmd(bp, f_obj,
5193 BNX2X_F_CMD_TX_START))
5195 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5198 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5199 echo = elem->message.data.function_update_event.echo;
5200 if (echo == SWITCH_UPDATE) {
5201 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5202 "got FUNC_SWITCH_UPDATE ramrod\n");
5203 if (f_obj->complete_cmd(
5204 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5208 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5209 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5210 f_obj->complete_cmd(bp, f_obj,
5211 BNX2X_F_CMD_AFEX_UPDATE);
5213 /* We will perform the Queues update from
5214 * sp_rtnl task as all Queue SP operations
5215 * should run under rtnl_lock.
5217 smp_mb__before_clear_bit();
5218 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5219 &bp->sp_rtnl_state);
5220 smp_mb__after_clear_bit();
5222 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5227 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5228 f_obj->complete_cmd(bp, f_obj,
5229 BNX2X_F_CMD_AFEX_VIFLISTS);
5230 bnx2x_after_afex_vif_lists(bp, elem);
5232 case EVENT_RING_OPCODE_FUNCTION_START:
5233 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5234 "got FUNC_START ramrod\n");
5235 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5240 case EVENT_RING_OPCODE_FUNCTION_STOP:
5241 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5242 "got FUNC_STOP ramrod\n");
5243 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5249 switch (opcode | bp->state) {
5250 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5252 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5253 BNX2X_STATE_OPENING_WAIT4_PORT):
5254 cid = elem->message.data.eth_event.echo &
5256 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5258 rss_raw->clear_pending(rss_raw);
5261 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5262 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5263 case (EVENT_RING_OPCODE_SET_MAC |
5264 BNX2X_STATE_CLOSING_WAIT4_HALT):
5265 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5267 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5269 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5270 BNX2X_STATE_CLOSING_WAIT4_HALT):
5271 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5272 bnx2x_handle_classification_eqe(bp, elem);
5275 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5277 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5279 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5280 BNX2X_STATE_CLOSING_WAIT4_HALT):
5281 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5282 bnx2x_handle_mcast_eqe(bp);
5285 case (EVENT_RING_OPCODE_FILTERS_RULES |
5287 case (EVENT_RING_OPCODE_FILTERS_RULES |
5289 case (EVENT_RING_OPCODE_FILTERS_RULES |
5290 BNX2X_STATE_CLOSING_WAIT4_HALT):
5291 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5292 bnx2x_handle_rx_mode_eqe(bp);
5295 /* unknown event log error and continue */
5296 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5297 elem->message.opcode, bp->state);
5303 smp_mb__before_atomic_inc();
5304 atomic_add(spqe_cnt, &bp->eq_spq_left);
5306 bp->eq_cons = sw_cons;
5307 bp->eq_prod = sw_prod;
5308 /* Make sure that above mem writes were issued towards the memory */
5311 /* update producer */
5312 bnx2x_update_eq_prod(bp, bp->eq_prod);
5315 static void bnx2x_sp_task(struct work_struct *work)
5317 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5319 DP(BNX2X_MSG_SP, "sp task invoked\n");
5321 /* make sure the atomic interrupt_occurred has been written */
5323 if (atomic_read(&bp->interrupt_occurred)) {
5325 /* what work needs to be performed? */
5326 u16 status = bnx2x_update_dsb_idx(bp);
5328 DP(BNX2X_MSG_SP, "status %x\n", status);
5329 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5330 atomic_set(&bp->interrupt_occurred, 0);
5333 if (status & BNX2X_DEF_SB_ATT_IDX) {
5335 status &= ~BNX2X_DEF_SB_ATT_IDX;
5338 /* SP events: STAT_QUERY and others */
5339 if (status & BNX2X_DEF_SB_IDX) {
5340 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5342 if (FCOE_INIT(bp) &&
5343 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5344 /* Prevent local bottom-halves from running as
5345 * we are going to change the local NAPI list.
5348 napi_schedule(&bnx2x_fcoe(bp, napi));
5352 /* Handle EQ completions */
5354 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5355 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5357 status &= ~BNX2X_DEF_SB_IDX;
5360 /* if status is non zero then perhaps something went wrong */
5361 if (unlikely(status))
5363 "got an unknown interrupt! (status 0x%x)\n", status);
5365 /* ack status block only if something was actually handled */
5366 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5367 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5370 /* must be called after the EQ processing (since eq leads to sriov
5371 * ramrod completion flows).
5372 * This flow may have been scheduled by the arrival of a ramrod
5373 * completion, or by the sriov code rescheduling itself.
5375 bnx2x_iov_sp_task(bp);
5377 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5378 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5380 bnx2x_link_report(bp);
5381 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5385 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5387 struct net_device *dev = dev_instance;
5388 struct bnx2x *bp = netdev_priv(dev);
5390 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5391 IGU_INT_DISABLE, 0);
5393 #ifdef BNX2X_STOP_ON_ERROR
5394 if (unlikely(bp->panic))
5398 if (CNIC_LOADED(bp)) {
5399 struct cnic_ops *c_ops;
5402 c_ops = rcu_dereference(bp->cnic_ops);
5404 c_ops->cnic_handler(bp->cnic_data, NULL);
5408 /* schedule sp task to perform default status block work, ack
5409 * attentions and enable interrupts.
5411 bnx2x_schedule_sp_task(bp);
5416 /* end of slow path */
5418 void bnx2x_drv_pulse(struct bnx2x *bp)
5420 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5421 bp->fw_drv_pulse_wr_seq);
5424 static void bnx2x_timer(unsigned long data)
5426 struct bnx2x *bp = (struct bnx2x *) data;
5428 if (!netif_running(bp->dev))
5433 int mb_idx = BP_FW_MB_IDX(bp);
5437 ++bp->fw_drv_pulse_wr_seq;
5438 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5439 /* TBD - add SYSTEM_TIME */
5440 drv_pulse = bp->fw_drv_pulse_wr_seq;
5441 bnx2x_drv_pulse(bp);
5443 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5444 MCP_PULSE_SEQ_MASK);
5445 /* The delta between driver pulse and mcp response
5446 * should be 1 (before mcp response) or 0 (after mcp response)
5448 if ((drv_pulse != mcp_pulse) &&
5449 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5450 /* someone lost a heartbeat... */
5451 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5452 drv_pulse, mcp_pulse);
5456 if (bp->state == BNX2X_STATE_OPEN)
5457 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5459 /* sample pf vf bulletin board for new posts from pf */
5461 bnx2x_timer_sriov(bp);
5463 mod_timer(&bp->timer, jiffies + bp->current_interval);
5466 /* end of Statistics */
5471 * nic init service functions
5474 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5477 if (!(len%4) && !(addr%4))
5478 for (i = 0; i < len; i += 4)
5479 REG_WR(bp, addr + i, fill);
5481 for (i = 0; i < len; i++)
5482 REG_WR8(bp, addr + i, fill);
5485 /* helper: writes FP SP data to FW - data_size in dwords */
5486 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5492 for (index = 0; index < data_size; index++)
5493 REG_WR(bp, BAR_CSTRORM_INTMEM +
5494 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5496 *(sb_data_p + index));
5499 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5503 struct hc_status_block_data_e2 sb_data_e2;
5504 struct hc_status_block_data_e1x sb_data_e1x;
5506 /* disable the function first */
5507 if (!CHIP_IS_E1x(bp)) {
5508 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5509 sb_data_e2.common.state = SB_DISABLED;
5510 sb_data_e2.common.p_func.vf_valid = false;
5511 sb_data_p = (u32 *)&sb_data_e2;
5512 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5514 memset(&sb_data_e1x, 0,
5515 sizeof(struct hc_status_block_data_e1x));
5516 sb_data_e1x.common.state = SB_DISABLED;
5517 sb_data_e1x.common.p_func.vf_valid = false;
5518 sb_data_p = (u32 *)&sb_data_e1x;
5519 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5521 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5523 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5524 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5525 CSTORM_STATUS_BLOCK_SIZE);
5526 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5527 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5528 CSTORM_SYNC_BLOCK_SIZE);
5531 /* helper: writes SP SB data to FW */
5532 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5533 struct hc_sp_status_block_data *sp_sb_data)
5535 int func = BP_FUNC(bp);
5537 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5538 REG_WR(bp, BAR_CSTRORM_INTMEM +
5539 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5541 *((u32 *)sp_sb_data + i));
5544 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5546 int func = BP_FUNC(bp);
5547 struct hc_sp_status_block_data sp_sb_data;
5548 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5550 sp_sb_data.state = SB_DISABLED;
5551 sp_sb_data.p_func.vf_valid = false;
5553 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5555 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5556 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5557 CSTORM_SP_STATUS_BLOCK_SIZE);
5558 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5559 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5560 CSTORM_SP_SYNC_BLOCK_SIZE);
5563 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5564 int igu_sb_id, int igu_seg_id)
5566 hc_sm->igu_sb_id = igu_sb_id;
5567 hc_sm->igu_seg_id = igu_seg_id;
5568 hc_sm->timer_value = 0xFF;
5569 hc_sm->time_to_expire = 0xFFFFFFFF;
5572 /* allocates state machine ids. */
5573 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5575 /* zero out state machine indices */
5577 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5580 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5581 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5582 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5583 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5587 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5588 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5591 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5592 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5593 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5594 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5595 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5596 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5597 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5598 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5601 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5602 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5606 struct hc_status_block_data_e2 sb_data_e2;
5607 struct hc_status_block_data_e1x sb_data_e1x;
5608 struct hc_status_block_sm *hc_sm_p;
5612 if (CHIP_INT_MODE_IS_BC(bp))
5613 igu_seg_id = HC_SEG_ACCESS_NORM;
5615 igu_seg_id = IGU_SEG_ACCESS_NORM;
5617 bnx2x_zero_fp_sb(bp, fw_sb_id);
5619 if (!CHIP_IS_E1x(bp)) {
5620 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5621 sb_data_e2.common.state = SB_ENABLED;
5622 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5623 sb_data_e2.common.p_func.vf_id = vfid;
5624 sb_data_e2.common.p_func.vf_valid = vf_valid;
5625 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5626 sb_data_e2.common.same_igu_sb_1b = true;
5627 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5628 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5629 hc_sm_p = sb_data_e2.common.state_machine;
5630 sb_data_p = (u32 *)&sb_data_e2;
5631 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5632 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5634 memset(&sb_data_e1x, 0,
5635 sizeof(struct hc_status_block_data_e1x));
5636 sb_data_e1x.common.state = SB_ENABLED;
5637 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5638 sb_data_e1x.common.p_func.vf_id = 0xff;
5639 sb_data_e1x.common.p_func.vf_valid = false;
5640 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5641 sb_data_e1x.common.same_igu_sb_1b = true;
5642 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5643 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5644 hc_sm_p = sb_data_e1x.common.state_machine;
5645 sb_data_p = (u32 *)&sb_data_e1x;
5646 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5647 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5650 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5651 igu_sb_id, igu_seg_id);
5652 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5653 igu_sb_id, igu_seg_id);
5655 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5657 /* write indices to HW - PCI guarantees endianity of regpairs */
5658 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5661 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5662 u16 tx_usec, u16 rx_usec)
5664 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5666 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5667 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5669 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5670 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5672 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5673 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5677 static void bnx2x_init_def_sb(struct bnx2x *bp)
5679 struct host_sp_status_block *def_sb = bp->def_status_blk;
5680 dma_addr_t mapping = bp->def_status_blk_mapping;
5681 int igu_sp_sb_index;
5683 int port = BP_PORT(bp);
5684 int func = BP_FUNC(bp);
5685 int reg_offset, reg_offset_en5;
5688 struct hc_sp_status_block_data sp_sb_data;
5689 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5691 if (CHIP_INT_MODE_IS_BC(bp)) {
5692 igu_sp_sb_index = DEF_SB_IGU_ID;
5693 igu_seg_id = HC_SEG_ACCESS_DEF;
5695 igu_sp_sb_index = bp->igu_dsb_id;
5696 igu_seg_id = IGU_SEG_ACCESS_DEF;
5700 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5701 atten_status_block);
5702 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5706 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5707 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5708 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5709 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5710 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5712 /* take care of sig[0]..sig[4] */
5713 for (sindex = 0; sindex < 4; sindex++)
5714 bp->attn_group[index].sig[sindex] =
5715 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5717 if (!CHIP_IS_E1x(bp))
5719 * enable5 is separate from the rest of the registers,
5720 * and therefore the address skip is 4
5721 * and not 16 between the different groups
5723 bp->attn_group[index].sig[4] = REG_RD(bp,
5724 reg_offset_en5 + 0x4*index);
5726 bp->attn_group[index].sig[4] = 0;
5729 if (bp->common.int_block == INT_BLOCK_HC) {
5730 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5731 HC_REG_ATTN_MSG0_ADDR_L);
5733 REG_WR(bp, reg_offset, U64_LO(section));
5734 REG_WR(bp, reg_offset + 4, U64_HI(section));
5735 } else if (!CHIP_IS_E1x(bp)) {
5736 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5737 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5740 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5743 bnx2x_zero_sp_sb(bp);
5745 /* PCI guarantees endianity of regpairs */
5746 sp_sb_data.state = SB_ENABLED;
5747 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5748 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5749 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5750 sp_sb_data.igu_seg_id = igu_seg_id;
5751 sp_sb_data.p_func.pf_id = func;
5752 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5753 sp_sb_data.p_func.vf_id = 0xff;
5755 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5757 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5760 void bnx2x_update_coalesce(struct bnx2x *bp)
5764 for_each_eth_queue(bp, i)
5765 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5766 bp->tx_ticks, bp->rx_ticks);
5769 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5771 spin_lock_init(&bp->spq_lock);
5772 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5774 bp->spq_prod_idx = 0;
5775 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5776 bp->spq_prod_bd = bp->spq;
5777 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5780 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5783 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5784 union event_ring_elem *elem =
5785 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5787 elem->next_page.addr.hi =
5788 cpu_to_le32(U64_HI(bp->eq_mapping +
5789 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5790 elem->next_page.addr.lo =
5791 cpu_to_le32(U64_LO(bp->eq_mapping +
5792 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5795 bp->eq_prod = NUM_EQ_DESC;
5796 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5797 /* we want a warning message before it gets wrought... */
5798 atomic_set(&bp->eq_spq_left,
5799 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5802 /* called with netif_addr_lock_bh() */
5803 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5804 unsigned long rx_mode_flags,
5805 unsigned long rx_accept_flags,
5806 unsigned long tx_accept_flags,
5807 unsigned long ramrod_flags)
5809 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5812 memset(&ramrod_param, 0, sizeof(ramrod_param));
5814 /* Prepare ramrod parameters */
5815 ramrod_param.cid = 0;
5816 ramrod_param.cl_id = cl_id;
5817 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5818 ramrod_param.func_id = BP_FUNC(bp);
5820 ramrod_param.pstate = &bp->sp_state;
5821 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5823 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5824 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5826 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5828 ramrod_param.ramrod_flags = ramrod_flags;
5829 ramrod_param.rx_mode_flags = rx_mode_flags;
5831 ramrod_param.rx_accept_flags = rx_accept_flags;
5832 ramrod_param.tx_accept_flags = tx_accept_flags;
5834 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5836 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5843 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5844 unsigned long *rx_accept_flags,
5845 unsigned long *tx_accept_flags)
5847 /* Clear the flags first */
5848 *rx_accept_flags = 0;
5849 *tx_accept_flags = 0;
5852 case BNX2X_RX_MODE_NONE:
5854 * 'drop all' supersedes any accept flags that may have been
5855 * passed to the function.
5858 case BNX2X_RX_MODE_NORMAL:
5859 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5860 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5861 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5863 /* internal switching mode */
5864 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5865 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5866 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5869 case BNX2X_RX_MODE_ALLMULTI:
5870 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5871 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5872 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5874 /* internal switching mode */
5875 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5876 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5877 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5880 case BNX2X_RX_MODE_PROMISC:
5881 /* According to definition of SI mode, iface in promisc mode
5882 * should receive matched and unmatched (in resolution of port)
5885 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5886 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5887 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5888 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5890 /* internal switching mode */
5891 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5892 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5895 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5897 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5901 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5905 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5906 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5907 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5908 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5914 /* called with netif_addr_lock_bh() */
5915 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5917 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5918 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5922 /* Configure rx_mode of FCoE Queue */
5923 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5925 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5930 __set_bit(RAMROD_RX, &ramrod_flags);
5931 __set_bit(RAMROD_TX, &ramrod_flags);
5933 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5934 rx_accept_flags, tx_accept_flags,
5938 static void bnx2x_init_internal_common(struct bnx2x *bp)
5944 * In switch independent mode, the TSTORM needs to accept
5945 * packets that failed classification, since approximate match
5946 * mac addresses aren't written to NIG LLH
5948 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5949 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5950 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5951 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5952 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5954 /* Zero this manually as its initialization is
5955 currently missing in the initTool */
5956 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5957 REG_WR(bp, BAR_USTRORM_INTMEM +
5958 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5959 if (!CHIP_IS_E1x(bp)) {
5960 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5961 CHIP_INT_MODE_IS_BC(bp) ?
5962 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5966 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5968 switch (load_code) {
5969 case FW_MSG_CODE_DRV_LOAD_COMMON:
5970 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5971 bnx2x_init_internal_common(bp);
5974 case FW_MSG_CODE_DRV_LOAD_PORT:
5978 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5979 /* internal memory per function is
5980 initialized inside bnx2x_pf_init */
5984 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5989 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5991 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5994 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5996 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5999 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6001 if (CHIP_IS_E1x(fp->bp))
6002 return BP_L_ID(fp->bp) + fp->index;
6003 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6004 return bnx2x_fp_igu_sb_id(fp);
6007 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6009 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6011 unsigned long q_type = 0;
6012 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6013 fp->rx_queue = fp_idx;
6015 fp->cl_id = bnx2x_fp_cl_id(fp);
6016 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6017 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6018 /* qZone id equals to FW (per path) client id */
6019 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6022 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6024 /* Setup SB indices */
6025 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6027 /* Configure Queue State object */
6028 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6029 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6031 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6034 for_each_cos_in_tx_queue(fp, cos) {
6035 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6036 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6037 FP_COS_TO_TXQ(fp, cos, bp),
6038 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6039 cids[cos] = fp->txdata_ptr[cos]->cid;
6042 /* nothing more for vf to do here */
6046 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6047 fp->fw_sb_id, fp->igu_sb_id);
6048 bnx2x_update_fpsb_idx(fp);
6049 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6050 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6051 bnx2x_sp_mapping(bp, q_rdata), q_type);
6054 * Configure classification DBs: Always enable Tx switching
6056 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6059 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6060 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6064 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6068 for (i = 1; i <= NUM_TX_RINGS; i++) {
6069 struct eth_tx_next_bd *tx_next_bd =
6070 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6072 tx_next_bd->addr_hi =
6073 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6074 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6075 tx_next_bd->addr_lo =
6076 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6077 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6080 *txdata->tx_cons_sb = cpu_to_le16(0);
6082 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6083 txdata->tx_db.data.zero_fill1 = 0;
6084 txdata->tx_db.data.prod = 0;
6086 txdata->tx_pkt_prod = 0;
6087 txdata->tx_pkt_cons = 0;
6088 txdata->tx_bd_prod = 0;
6089 txdata->tx_bd_cons = 0;
6093 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6097 for_each_tx_queue_cnic(bp, i)
6098 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6101 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6106 for_each_eth_queue(bp, i)
6107 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6108 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6111 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6114 bnx2x_init_fcoe_fp(bp);
6116 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6117 BNX2X_VF_ID_INVALID, false,
6118 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6120 /* ensure status block indices were read */
6122 bnx2x_init_rx_rings_cnic(bp);
6123 bnx2x_init_tx_rings_cnic(bp);
6130 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6134 /* Setup NIC internals and enable interrupts */
6135 for_each_eth_queue(bp, i)
6136 bnx2x_init_eth_fp(bp, i);
6138 /* ensure status block indices were read */
6140 bnx2x_init_rx_rings(bp);
6141 bnx2x_init_tx_rings(bp);
6144 /* Initialize MOD_ABS interrupts */
6145 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6146 bp->common.shmem_base,
6147 bp->common.shmem2_base, BP_PORT(bp));
6149 /* initialize the default status block and sp ring */
6150 bnx2x_init_def_sb(bp);
6151 bnx2x_update_dsb_idx(bp);
6152 bnx2x_init_sp_ring(bp);
6154 bnx2x_memset_stats(bp);
6158 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6160 bnx2x_init_eq_ring(bp);
6161 bnx2x_init_internal(bp, load_code);
6163 bnx2x_stats_init(bp);
6165 /* flush all before enabling interrupts */
6169 bnx2x_int_enable(bp);
6171 /* Check for SPIO5 */
6172 bnx2x_attn_int_deasserted0(bp,
6173 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6174 AEU_INPUTS_ATTN_BITS_SPIO5);
6177 /* gzip service functions */
6178 static int bnx2x_gunzip_init(struct bnx2x *bp)
6180 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6181 &bp->gunzip_mapping, GFP_KERNEL);
6182 if (bp->gunzip_buf == NULL)
6185 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6186 if (bp->strm == NULL)
6189 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6190 if (bp->strm->workspace == NULL)
6200 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6201 bp->gunzip_mapping);
6202 bp->gunzip_buf = NULL;
6205 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6209 static void bnx2x_gunzip_end(struct bnx2x *bp)
6212 vfree(bp->strm->workspace);
6217 if (bp->gunzip_buf) {
6218 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6219 bp->gunzip_mapping);
6220 bp->gunzip_buf = NULL;
6224 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6228 /* check gzip header */
6229 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6230 BNX2X_ERR("Bad gzip header\n");
6238 if (zbuf[3] & FNAME)
6239 while ((zbuf[n++] != 0) && (n < len));
6241 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6242 bp->strm->avail_in = len - n;
6243 bp->strm->next_out = bp->gunzip_buf;
6244 bp->strm->avail_out = FW_BUF_SIZE;
6246 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6250 rc = zlib_inflate(bp->strm, Z_FINISH);
6251 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6252 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6255 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6256 if (bp->gunzip_outlen & 0x3)
6258 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6260 bp->gunzip_outlen >>= 2;
6262 zlib_inflateEnd(bp->strm);
6264 if (rc == Z_STREAM_END)
6270 /* nic load/unload */
6273 * General service functions
6276 /* send a NIG loopback debug packet */
6277 static void bnx2x_lb_pckt(struct bnx2x *bp)
6281 /* Ethernet source and destination addresses */
6282 wb_write[0] = 0x55555555;
6283 wb_write[1] = 0x55555555;
6284 wb_write[2] = 0x20; /* SOP */
6285 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6287 /* NON-IP protocol */
6288 wb_write[0] = 0x09000000;
6289 wb_write[1] = 0x55555555;
6290 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6291 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6294 /* some of the internal memories
6295 * are not directly readable from the driver
6296 * to test them we send debug packets
6298 static int bnx2x_int_mem_test(struct bnx2x *bp)
6304 if (CHIP_REV_IS_FPGA(bp))
6306 else if (CHIP_REV_IS_EMUL(bp))
6311 /* Disable inputs of parser neighbor blocks */
6312 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6313 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6314 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6315 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6317 /* Write 0 to parser credits for CFC search request */
6318 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6320 /* send Ethernet packet */
6323 /* TODO do i reset NIG statistic? */
6324 /* Wait until NIG register shows 1 packet of size 0x10 */
6325 count = 1000 * factor;
6328 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6329 val = *bnx2x_sp(bp, wb_data[0]);
6333 usleep_range(10000, 20000);
6337 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6341 /* Wait until PRS register shows 1 packet */
6342 count = 1000 * factor;
6344 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6348 usleep_range(10000, 20000);
6352 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6356 /* Reset and init BRB, PRS */
6357 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6359 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6361 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6362 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6364 DP(NETIF_MSG_HW, "part2\n");
6366 /* Disable inputs of parser neighbor blocks */
6367 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6368 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6369 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6370 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6372 /* Write 0 to parser credits for CFC search request */
6373 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6375 /* send 10 Ethernet packets */
6376 for (i = 0; i < 10; i++)
6379 /* Wait until NIG register shows 10 + 1
6380 packets of size 11*0x10 = 0xb0 */
6381 count = 1000 * factor;
6384 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6385 val = *bnx2x_sp(bp, wb_data[0]);
6389 usleep_range(10000, 20000);
6393 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6397 /* Wait until PRS register shows 2 packets */
6398 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6400 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6402 /* Write 1 to parser credits for CFC search request */
6403 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6405 /* Wait until PRS register shows 3 packets */
6406 msleep(10 * factor);
6407 /* Wait until NIG register shows 1 packet of size 0x10 */
6408 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6410 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6412 /* clear NIG EOP FIFO */
6413 for (i = 0; i < 11; i++)
6414 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6415 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6417 BNX2X_ERR("clear of NIG failed\n");
6421 /* Reset and init BRB, PRS, NIG */
6422 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6424 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6426 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6427 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6428 if (!CNIC_SUPPORT(bp))
6430 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6432 /* Enable inputs of parser neighbor blocks */
6433 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6434 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6435 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6436 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6438 DP(NETIF_MSG_HW, "done\n");
6443 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6447 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6448 if (!CHIP_IS_E1x(bp))
6449 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6451 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6452 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6453 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6455 * mask read length error interrupts in brb for parser
6456 * (parsing unit and 'checksum and crc' unit)
6457 * these errors are legal (PU reads fixed length and CAC can cause
6458 * read length error on truncated packets)
6460 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6461 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6462 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6463 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6464 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6465 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6466 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6467 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6468 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6469 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6470 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6471 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6472 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6473 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6474 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6475 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6476 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6477 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6478 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6480 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6481 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6482 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6483 if (!CHIP_IS_E1x(bp))
6484 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6485 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6486 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6488 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6489 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6490 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6491 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6493 if (!CHIP_IS_E1x(bp))
6494 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6495 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6497 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6498 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6499 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6500 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6503 static void bnx2x_reset_common(struct bnx2x *bp)
6508 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6511 if (CHIP_IS_E3(bp)) {
6512 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6513 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6516 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6519 static void bnx2x_setup_dmae(struct bnx2x *bp)
6522 spin_lock_init(&bp->dmae_lock);
6525 static void bnx2x_init_pxp(struct bnx2x *bp)
6528 int r_order, w_order;
6530 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6531 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6532 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6534 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6536 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6540 bnx2x_init_pxp_arb(bp, r_order, w_order);
6543 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6553 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6554 SHARED_HW_CFG_FAN_FAILURE_MASK;
6556 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6560 * The fan failure mechanism is usually related to the PHY type since
6561 * the power consumption of the board is affected by the PHY. Currently,
6562 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6564 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6565 for (port = PORT_0; port < PORT_MAX; port++) {
6567 bnx2x_fan_failure_det_req(
6569 bp->common.shmem_base,
6570 bp->common.shmem2_base,
6574 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6576 if (is_required == 0)
6579 /* Fan failure is indicated by SPIO 5 */
6580 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6582 /* set to active low mode */
6583 val = REG_RD(bp, MISC_REG_SPIO_INT);
6584 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6585 REG_WR(bp, MISC_REG_SPIO_INT, val);
6587 /* enable interrupt to signal the IGU */
6588 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6589 val |= MISC_SPIO_SPIO5;
6590 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6593 void bnx2x_pf_disable(struct bnx2x *bp)
6595 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6596 val &= ~IGU_PF_CONF_FUNC_EN;
6598 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6599 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6600 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6603 static void bnx2x__common_init_phy(struct bnx2x *bp)
6605 u32 shmem_base[2], shmem2_base[2];
6606 /* Avoid common init in case MFW supports LFA */
6607 if (SHMEM2_RD(bp, size) >
6608 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6610 shmem_base[0] = bp->common.shmem_base;
6611 shmem2_base[0] = bp->common.shmem2_base;
6612 if (!CHIP_IS_E1x(bp)) {
6614 SHMEM2_RD(bp, other_shmem_base_addr);
6616 SHMEM2_RD(bp, other_shmem2_base_addr);
6618 bnx2x_acquire_phy_lock(bp);
6619 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6620 bp->common.chip_id);
6621 bnx2x_release_phy_lock(bp);
6625 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6627 * @bp: driver handle
6629 static int bnx2x_init_hw_common(struct bnx2x *bp)
6633 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6636 * take the RESET lock to protect undi_unload flow from accessing
6637 * registers while we're resetting the chip
6639 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6641 bnx2x_reset_common(bp);
6642 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6645 if (CHIP_IS_E3(bp)) {
6646 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6647 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6649 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6651 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6653 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6655 if (!CHIP_IS_E1x(bp)) {
6659 * 4-port mode or 2-port mode we need to turn of master-enable
6660 * for everyone, after that, turn it back on for self.
6661 * so, we disregard multi-function or not, and always disable
6662 * for all functions on the given path, this means 0,2,4,6 for
6663 * path 0 and 1,3,5,7 for path 1
6665 for (abs_func_id = BP_PATH(bp);
6666 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6667 if (abs_func_id == BP_ABS_FUNC(bp)) {
6669 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6674 bnx2x_pretend_func(bp, abs_func_id);
6675 /* clear pf enable */
6676 bnx2x_pf_disable(bp);
6677 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6681 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6682 if (CHIP_IS_E1(bp)) {
6683 /* enable HW interrupt from PXP on USDM overflow
6684 bit 16 on INT_MASK_0 */
6685 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6688 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6692 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6693 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6694 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6695 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6696 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6697 /* make sure this value is 0 */
6698 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6700 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6701 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6702 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6703 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6704 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6707 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6709 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6710 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6712 /* let the HW do it's magic ... */
6714 /* finish PXP init */
6715 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6717 BNX2X_ERR("PXP2 CFG failed\n");
6720 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6722 BNX2X_ERR("PXP2 RD_INIT failed\n");
6726 /* Timers bug workaround E2 only. We need to set the entire ILT to
6727 * have entries with value "0" and valid bit on.
6728 * This needs to be done by the first PF that is loaded in a path
6729 * (i.e. common phase)
6731 if (!CHIP_IS_E1x(bp)) {
6732 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6733 * (i.e. vnic3) to start even if it is marked as "scan-off".
6734 * This occurs when a different function (func2,3) is being marked
6735 * as "scan-off". Real-life scenario for example: if a driver is being
6736 * load-unloaded while func6,7 are down. This will cause the timer to access
6737 * the ilt, translate to a logical address and send a request to read/write.
6738 * Since the ilt for the function that is down is not valid, this will cause
6739 * a translation error which is unrecoverable.
6740 * The Workaround is intended to make sure that when this happens nothing fatal
6741 * will occur. The workaround:
6742 * 1. First PF driver which loads on a path will:
6743 * a. After taking the chip out of reset, by using pretend,
6744 * it will write "0" to the following registers of
6746 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6747 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6748 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6749 * And for itself it will write '1' to
6750 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6751 * dmae-operations (writing to pram for example.)
6752 * note: can be done for only function 6,7 but cleaner this
6754 * b. Write zero+valid to the entire ILT.
6755 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6756 * VNIC3 (of that port). The range allocated will be the
6757 * entire ILT. This is needed to prevent ILT range error.
6758 * 2. Any PF driver load flow:
6759 * a. ILT update with the physical addresses of the allocated
6761 * b. Wait 20msec. - note that this timeout is needed to make
6762 * sure there are no requests in one of the PXP internal
6763 * queues with "old" ILT addresses.
6764 * c. PF enable in the PGLC.
6765 * d. Clear the was_error of the PF in the PGLC. (could have
6766 * occurred while driver was down)
6767 * e. PF enable in the CFC (WEAK + STRONG)
6768 * f. Timers scan enable
6769 * 3. PF driver unload flow:
6770 * a. Clear the Timers scan_en.
6771 * b. Polling for scan_on=0 for that PF.
6772 * c. Clear the PF enable bit in the PXP.
6773 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6774 * e. Write zero+valid to all ILT entries (The valid bit must
6776 * f. If this is VNIC 3 of a port then also init
6777 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6778 * to the last entry in the ILT.
6781 * Currently the PF error in the PGLC is non recoverable.
6782 * In the future the there will be a recovery routine for this error.
6783 * Currently attention is masked.
6784 * Having an MCP lock on the load/unload process does not guarantee that
6785 * there is no Timer disable during Func6/7 enable. This is because the
6786 * Timers scan is currently being cleared by the MCP on FLR.
6787 * Step 2.d can be done only for PF6/7 and the driver can also check if
6788 * there is error before clearing it. But the flow above is simpler and
6790 * All ILT entries are written by zero+valid and not just PF6/7
6791 * ILT entries since in the future the ILT entries allocation for
6792 * PF-s might be dynamic.
6794 struct ilt_client_info ilt_cli;
6795 struct bnx2x_ilt ilt;
6796 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6797 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6799 /* initialize dummy TM client */
6801 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6802 ilt_cli.client_num = ILT_CLIENT_TM;
6804 /* Step 1: set zeroes to all ilt page entries with valid bit on
6805 * Step 2: set the timers first/last ilt entry to point
6806 * to the entire range to prevent ILT range error for 3rd/4th
6807 * vnic (this code assumes existence of the vnic)
6809 * both steps performed by call to bnx2x_ilt_client_init_op()
6810 * with dummy TM client
6812 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6813 * and his brother are split registers
6815 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6816 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6817 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6819 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6820 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6821 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6824 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6825 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6827 if (!CHIP_IS_E1x(bp)) {
6828 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6829 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6830 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6832 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6834 /* let the HW do it's magic ... */
6837 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6838 } while (factor-- && (val != 1));
6841 BNX2X_ERR("ATC_INIT failed\n");
6846 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6848 bnx2x_iov_init_dmae(bp);
6850 /* clean the DMAE memory */
6852 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6854 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6856 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6858 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6860 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6862 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6863 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6864 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6865 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6867 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6869 /* QM queues pointers table */
6870 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6872 /* soft reset pulse */
6873 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6874 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6876 if (CNIC_SUPPORT(bp))
6877 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6879 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6880 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6881 if (!CHIP_REV_IS_SLOW(bp))
6882 /* enable hw interrupt from doorbell Q */
6883 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6885 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6887 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6888 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6890 if (!CHIP_IS_E1(bp))
6891 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6893 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6894 if (IS_MF_AFEX(bp)) {
6895 /* configure that VNTag and VLAN headers must be
6896 * received in afex mode
6898 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6899 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6900 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6901 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6902 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6904 /* Bit-map indicating which L2 hdrs may appear
6905 * after the basic Ethernet header
6907 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6908 bp->path_has_ovlan ? 7 : 6);
6912 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6913 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6914 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6915 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6917 if (!CHIP_IS_E1x(bp)) {
6918 /* reset VFC memories */
6919 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6920 VFC_MEMORIES_RST_REG_CAM_RST |
6921 VFC_MEMORIES_RST_REG_RAM_RST);
6922 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6923 VFC_MEMORIES_RST_REG_CAM_RST |
6924 VFC_MEMORIES_RST_REG_RAM_RST);
6929 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6930 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6931 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6932 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6935 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6937 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6940 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6941 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6942 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6944 if (!CHIP_IS_E1x(bp)) {
6945 if (IS_MF_AFEX(bp)) {
6946 /* configure that VNTag and VLAN headers must be
6949 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6950 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6951 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6952 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6953 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6955 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6956 bp->path_has_ovlan ? 7 : 6);
6960 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6962 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6964 if (CNIC_SUPPORT(bp)) {
6965 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6966 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6967 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6968 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6969 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6970 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6971 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6972 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6973 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6974 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6976 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6978 if (sizeof(union cdu_context) != 1024)
6979 /* we currently assume that a context is 1024 bytes */
6980 dev_alert(&bp->pdev->dev,
6981 "please adjust the size of cdu_context(%ld)\n",
6982 (long)sizeof(union cdu_context));
6984 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6985 val = (4 << 24) + (0 << 12) + 1024;
6986 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6988 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6989 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6990 /* enable context validation interrupt from CFC */
6991 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6993 /* set the thresholds to prevent CFC/CDU race */
6994 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6996 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6998 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6999 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7001 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7002 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7004 /* Reset PCIE errors for debug */
7005 REG_WR(bp, 0x2814, 0xffffffff);
7006 REG_WR(bp, 0x3820, 0xffffffff);
7008 if (!CHIP_IS_E1x(bp)) {
7009 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7010 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7011 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7012 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7013 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7014 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7015 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7016 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7017 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7018 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7019 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7022 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7023 if (!CHIP_IS_E1(bp)) {
7024 /* in E3 this done in per-port section */
7025 if (!CHIP_IS_E3(bp))
7026 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7028 if (CHIP_IS_E1H(bp))
7029 /* not applicable for E2 (and above ...) */
7030 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7032 if (CHIP_REV_IS_SLOW(bp))
7035 /* finish CFC init */
7036 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7038 BNX2X_ERR("CFC LL_INIT failed\n");
7041 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7043 BNX2X_ERR("CFC AC_INIT failed\n");
7046 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7048 BNX2X_ERR("CFC CAM_INIT failed\n");
7051 REG_WR(bp, CFC_REG_DEBUG0, 0);
7053 if (CHIP_IS_E1(bp)) {
7054 /* read NIG statistic
7055 to see if this is our first up since powerup */
7056 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7057 val = *bnx2x_sp(bp, wb_data[0]);
7059 /* do internal memory self test */
7060 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7061 BNX2X_ERR("internal mem self test failed\n");
7066 bnx2x_setup_fan_failure_detection(bp);
7068 /* clear PXP2 attentions */
7069 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7071 bnx2x_enable_blocks_attention(bp);
7072 bnx2x_enable_blocks_parity(bp);
7074 if (!BP_NOMCP(bp)) {
7075 if (CHIP_IS_E1x(bp))
7076 bnx2x__common_init_phy(bp);
7078 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7084 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7086 * @bp: driver handle
7088 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7090 int rc = bnx2x_init_hw_common(bp);
7095 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7097 bnx2x__common_init_phy(bp);
7102 static int bnx2x_init_hw_port(struct bnx2x *bp)
7104 int port = BP_PORT(bp);
7105 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7109 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7111 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7113 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7114 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7115 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7117 /* Timers bug workaround: disables the pf_master bit in pglue at
7118 * common phase, we need to enable it here before any dmae access are
7119 * attempted. Therefore we manually added the enable-master to the
7120 * port phase (it also happens in the function phase)
7122 if (!CHIP_IS_E1x(bp))
7123 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7125 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7126 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7127 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7128 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7130 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7131 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7132 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7133 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7135 /* QM cid (connection) count */
7136 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7138 if (CNIC_SUPPORT(bp)) {
7139 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7140 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7141 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7144 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7146 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7148 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7151 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7152 else if (bp->dev->mtu > 4096) {
7153 if (bp->flags & ONE_PORT_FLAG)
7157 /* (24*1024 + val*4)/256 */
7158 low = 96 + (val/64) +
7159 ((val % 64) ? 1 : 0);
7162 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7163 high = low + 56; /* 14*1024/256 */
7164 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7165 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7168 if (CHIP_MODE_IS_4_PORT(bp))
7169 REG_WR(bp, (BP_PORT(bp) ?
7170 BRB1_REG_MAC_GUARANTIED_1 :
7171 BRB1_REG_MAC_GUARANTIED_0), 40);
7173 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7174 if (CHIP_IS_E3B0(bp)) {
7175 if (IS_MF_AFEX(bp)) {
7176 /* configure headers for AFEX mode */
7177 REG_WR(bp, BP_PORT(bp) ?
7178 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7179 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7180 REG_WR(bp, BP_PORT(bp) ?
7181 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7182 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7183 REG_WR(bp, BP_PORT(bp) ?
7184 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7185 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7187 /* Ovlan exists only if we are in multi-function +
7188 * switch-dependent mode, in switch-independent there
7189 * is no ovlan headers
7191 REG_WR(bp, BP_PORT(bp) ?
7192 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7193 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7194 (bp->path_has_ovlan ? 7 : 6));
7198 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7199 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7200 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7201 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7203 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7204 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7205 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7206 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7208 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7209 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7211 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7213 if (CHIP_IS_E1x(bp)) {
7214 /* configure PBF to work without PAUSE mtu 9000 */
7215 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7217 /* update threshold */
7218 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7219 /* update init credit */
7220 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7223 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7225 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7228 if (CNIC_SUPPORT(bp))
7229 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7231 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7232 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7234 if (CHIP_IS_E1(bp)) {
7235 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7236 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7238 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7240 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7242 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7243 /* init aeu_mask_attn_func_0/1:
7244 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7245 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7246 * bits 4-7 are used for "per vn group attention" */
7247 val = IS_MF(bp) ? 0xF7 : 0x7;
7248 /* Enable DCBX attention for all but E1 */
7249 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7250 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7252 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7254 if (!CHIP_IS_E1x(bp)) {
7255 /* Bit-map indicating which L2 hdrs may appear after the
7256 * basic Ethernet header
7259 REG_WR(bp, BP_PORT(bp) ?
7260 NIG_REG_P1_HDRS_AFTER_BASIC :
7261 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7263 REG_WR(bp, BP_PORT(bp) ?
7264 NIG_REG_P1_HDRS_AFTER_BASIC :
7265 NIG_REG_P0_HDRS_AFTER_BASIC,
7266 IS_MF_SD(bp) ? 7 : 6);
7269 REG_WR(bp, BP_PORT(bp) ?
7270 NIG_REG_LLH1_MF_MODE :
7271 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7273 if (!CHIP_IS_E3(bp))
7274 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7276 if (!CHIP_IS_E1(bp)) {
7277 /* 0x2 disable mf_ov, 0x1 enable */
7278 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7279 (IS_MF_SD(bp) ? 0x1 : 0x2));
7281 if (!CHIP_IS_E1x(bp)) {
7283 switch (bp->mf_mode) {
7284 case MULTI_FUNCTION_SD:
7287 case MULTI_FUNCTION_SI:
7288 case MULTI_FUNCTION_AFEX:
7293 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7294 NIG_REG_LLH0_CLS_TYPE), val);
7297 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7298 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7299 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7303 /* If SPIO5 is set to generate interrupts, enable it for this port */
7304 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7305 if (val & MISC_SPIO_SPIO5) {
7306 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7307 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7308 val = REG_RD(bp, reg_addr);
7309 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7310 REG_WR(bp, reg_addr, val);
7316 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7322 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7324 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7326 wb_write[0] = ONCHIP_ADDR1(addr);
7327 wb_write[1] = ONCHIP_ADDR2(addr);
7328 REG_WR_DMAE(bp, reg, wb_write, 2);
7331 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7333 u32 data, ctl, cnt = 100;
7334 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7335 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7336 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7337 u32 sb_bit = 1 << (idu_sb_id%32);
7338 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7339 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7341 /* Not supported in BC mode */
7342 if (CHIP_INT_MODE_IS_BC(bp))
7345 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7346 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7347 IGU_REGULAR_CLEANUP_SET |
7348 IGU_REGULAR_BCLEANUP;
7350 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7351 func_encode << IGU_CTRL_REG_FID_SHIFT |
7352 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7354 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7355 data, igu_addr_data);
7356 REG_WR(bp, igu_addr_data, data);
7359 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7361 REG_WR(bp, igu_addr_ctl, ctl);
7365 /* wait for clean up to finish */
7366 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7369 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7371 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7372 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7376 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7378 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7381 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7383 u32 i, base = FUNC_ILT_BASE(func);
7384 for (i = base; i < base + ILT_PER_FUNC; i++)
7385 bnx2x_ilt_wr(bp, i, 0);
7388 static void bnx2x_init_searcher(struct bnx2x *bp)
7390 int port = BP_PORT(bp);
7391 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7392 /* T1 hash bits value determines the T1 number of entries */
7393 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7396 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7399 struct bnx2x_func_state_params func_params = {NULL};
7400 struct bnx2x_func_switch_update_params *switch_update_params =
7401 &func_params.params.switch_update;
7403 /* Prepare parameters for function state transitions */
7404 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7405 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7407 func_params.f_obj = &bp->func_obj;
7408 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7410 /* Function parameters */
7411 switch_update_params->suspend = suspend;
7413 rc = bnx2x_func_state_change(bp, &func_params);
7418 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7420 int rc, i, port = BP_PORT(bp);
7421 int vlan_en = 0, mac_en[NUM_MACS];
7423 /* Close input from network */
7424 if (bp->mf_mode == SINGLE_FUNCTION) {
7425 bnx2x_set_rx_filter(&bp->link_params, 0);
7427 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7428 NIG_REG_LLH0_FUNC_EN);
7429 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7430 NIG_REG_LLH0_FUNC_EN, 0);
7431 for (i = 0; i < NUM_MACS; i++) {
7432 mac_en[i] = REG_RD(bp, port ?
7433 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7435 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7437 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7439 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7443 /* Close BMC to host */
7444 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7445 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7447 /* Suspend Tx switching to the PF. Completion of this ramrod
7448 * further guarantees that all the packets of that PF / child
7449 * VFs in BRB were processed by the Parser, so it is safe to
7450 * change the NIC_MODE register.
7452 rc = bnx2x_func_switch_update(bp, 1);
7454 BNX2X_ERR("Can't suspend tx-switching!\n");
7458 /* Change NIC_MODE register */
7459 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7461 /* Open input from network */
7462 if (bp->mf_mode == SINGLE_FUNCTION) {
7463 bnx2x_set_rx_filter(&bp->link_params, 1);
7465 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7466 NIG_REG_LLH0_FUNC_EN, vlan_en);
7467 for (i = 0; i < NUM_MACS; i++) {
7468 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7470 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7475 /* Enable BMC to host */
7476 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7477 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7479 /* Resume Tx switching to the PF */
7480 rc = bnx2x_func_switch_update(bp, 0);
7482 BNX2X_ERR("Can't resume tx-switching!\n");
7486 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7490 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7494 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7496 if (CONFIGURE_NIC_MODE(bp)) {
7497 /* Configure searcher as part of function hw init */
7498 bnx2x_init_searcher(bp);
7500 /* Reset NIC mode */
7501 rc = bnx2x_reset_nic_mode(bp);
7503 BNX2X_ERR("Can't change NIC mode!\n");
7510 static int bnx2x_init_hw_func(struct bnx2x *bp)
7512 int port = BP_PORT(bp);
7513 int func = BP_FUNC(bp);
7514 int init_phase = PHASE_PF0 + func;
7515 struct bnx2x_ilt *ilt = BP_ILT(bp);
7518 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7519 int i, main_mem_width, rc;
7521 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7523 /* FLR cleanup - hmmm */
7524 if (!CHIP_IS_E1x(bp)) {
7525 rc = bnx2x_pf_flr_clnup(bp);
7532 /* set MSI reconfigure capability */
7533 if (bp->common.int_block == INT_BLOCK_HC) {
7534 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7535 val = REG_RD(bp, addr);
7536 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7537 REG_WR(bp, addr, val);
7540 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7541 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7544 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7547 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7548 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7550 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7551 * those of the VFs, so start line should be reset
7553 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7554 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7555 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7556 ilt->lines[cdu_ilt_start + i].page_mapping =
7557 bp->context[i].cxt_mapping;
7558 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7561 bnx2x_ilt_init_op(bp, INITOP_SET);
7563 if (!CONFIGURE_NIC_MODE(bp)) {
7564 bnx2x_init_searcher(bp);
7565 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7566 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7569 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7570 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7573 if (!CHIP_IS_E1x(bp)) {
7574 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7576 /* Turn on a single ISR mode in IGU if driver is going to use
7579 if (!(bp->flags & USING_MSIX_FLAG))
7580 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7582 * Timers workaround bug: function init part.
7583 * Need to wait 20msec after initializing ILT,
7584 * needed to make sure there are no requests in
7585 * one of the PXP internal queues with "old" ILT addresses
7589 * Master enable - Due to WB DMAE writes performed before this
7590 * register is re-initialized as part of the regular function
7593 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7594 /* Enable the function in IGU */
7595 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7600 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7602 if (!CHIP_IS_E1x(bp))
7603 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7605 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7606 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7607 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7608 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7609 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7610 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7611 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7612 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7613 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7614 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7615 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7616 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7617 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7619 if (!CHIP_IS_E1x(bp))
7620 REG_WR(bp, QM_REG_PF_EN, 1);
7622 if (!CHIP_IS_E1x(bp)) {
7623 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7624 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7625 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7626 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7628 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7630 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7631 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7633 bnx2x_iov_init_dq(bp);
7635 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7636 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7637 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7638 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7639 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7640 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7641 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7642 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7643 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7644 if (!CHIP_IS_E1x(bp))
7645 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7647 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7649 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7651 if (!CHIP_IS_E1x(bp))
7652 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7655 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7656 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7659 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7661 /* HC init per function */
7662 if (bp->common.int_block == INT_BLOCK_HC) {
7663 if (CHIP_IS_E1H(bp)) {
7664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7666 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7667 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7669 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7672 int num_segs, sb_idx, prod_offset;
7674 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7676 if (!CHIP_IS_E1x(bp)) {
7677 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7678 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7681 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7683 if (!CHIP_IS_E1x(bp)) {
7687 * E2 mode: address 0-135 match to the mapping memory;
7688 * 136 - PF0 default prod; 137 - PF1 default prod;
7689 * 138 - PF2 default prod; 139 - PF3 default prod;
7690 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7691 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7694 * E1.5 mode - In backward compatible mode;
7695 * for non default SB; each even line in the memory
7696 * holds the U producer and each odd line hold
7697 * the C producer. The first 128 producers are for
7698 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7699 * producers are for the DSB for each PF.
7700 * Each PF has five segments: (the order inside each
7701 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7702 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7703 * 144-147 attn prods;
7705 /* non-default-status-blocks */
7706 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7707 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7708 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7709 prod_offset = (bp->igu_base_sb + sb_idx) *
7712 for (i = 0; i < num_segs; i++) {
7713 addr = IGU_REG_PROD_CONS_MEMORY +
7714 (prod_offset + i) * 4;
7715 REG_WR(bp, addr, 0);
7717 /* send consumer update with value 0 */
7718 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7719 USTORM_ID, 0, IGU_INT_NOP, 1);
7720 bnx2x_igu_clear_sb(bp,
7721 bp->igu_base_sb + sb_idx);
7724 /* default-status-blocks */
7725 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7726 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7728 if (CHIP_MODE_IS_4_PORT(bp))
7729 dsb_idx = BP_FUNC(bp);
7731 dsb_idx = BP_VN(bp);
7733 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7734 IGU_BC_BASE_DSB_PROD + dsb_idx :
7735 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7738 * igu prods come in chunks of E1HVN_MAX (4) -
7739 * does not matters what is the current chip mode
7741 for (i = 0; i < (num_segs * E1HVN_MAX);
7743 addr = IGU_REG_PROD_CONS_MEMORY +
7744 (prod_offset + i)*4;
7745 REG_WR(bp, addr, 0);
7747 /* send consumer update with 0 */
7748 if (CHIP_INT_MODE_IS_BC(bp)) {
7749 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7750 USTORM_ID, 0, IGU_INT_NOP, 1);
7751 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7752 CSTORM_ID, 0, IGU_INT_NOP, 1);
7753 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7754 XSTORM_ID, 0, IGU_INT_NOP, 1);
7755 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7756 TSTORM_ID, 0, IGU_INT_NOP, 1);
7757 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7758 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7760 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7761 USTORM_ID, 0, IGU_INT_NOP, 1);
7762 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7763 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7765 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7767 /* !!! These should become driver const once
7768 rf-tool supports split-68 const */
7769 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7770 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7771 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7772 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7773 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7774 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7778 /* Reset PCIE errors for debug */
7779 REG_WR(bp, 0x2114, 0xffffffff);
7780 REG_WR(bp, 0x2120, 0xffffffff);
7782 if (CHIP_IS_E1x(bp)) {
7783 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7784 main_mem_base = HC_REG_MAIN_MEMORY +
7785 BP_PORT(bp) * (main_mem_size * 4);
7786 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7789 val = REG_RD(bp, main_mem_prty_clr);
7792 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7795 /* Clear "false" parity errors in MSI-X table */
7796 for (i = main_mem_base;
7797 i < main_mem_base + main_mem_size * 4;
7798 i += main_mem_width) {
7799 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7800 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7801 i, main_mem_width / 4);
7803 /* Clear HC parity attention */
7804 REG_RD(bp, main_mem_prty_clr);
7807 #ifdef BNX2X_STOP_ON_ERROR
7808 /* Enable STORMs SP logging */
7809 REG_WR8(bp, BAR_USTRORM_INTMEM +
7810 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7811 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7812 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7813 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7814 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7815 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7816 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7819 bnx2x_phy_probe(&bp->link_params);
7824 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7826 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7828 if (!CHIP_IS_E1x(bp))
7829 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7830 sizeof(struct host_hc_status_block_e2));
7832 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7833 sizeof(struct host_hc_status_block_e1x));
7835 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7838 void bnx2x_free_mem(struct bnx2x *bp)
7842 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7843 sizeof(struct host_sp_status_block));
7845 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7846 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7848 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7849 sizeof(struct bnx2x_slowpath));
7851 for (i = 0; i < L2_ILT_LINES(bp); i++)
7852 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7853 bp->context[i].size);
7854 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7856 BNX2X_FREE(bp->ilt->lines);
7858 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7860 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7861 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7863 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7865 bnx2x_iov_free_mem(bp);
7868 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7870 if (!CHIP_IS_E1x(bp))
7871 /* size = the status block + ramrod buffers */
7872 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7873 sizeof(struct host_hc_status_block_e2));
7875 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7876 &bp->cnic_sb_mapping,
7878 host_hc_status_block_e1x));
7880 if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7881 /* allocate searcher T2 table, as it wasn't allocated before */
7882 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7884 /* write address to which L5 should insert its values */
7885 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7886 &bp->slowpath->drv_info_to_mcp;
7888 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7894 bnx2x_free_mem_cnic(bp);
7895 BNX2X_ERR("Can't allocate memory\n");
7899 int bnx2x_alloc_mem(struct bnx2x *bp)
7901 int i, allocated, context_size;
7903 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7904 /* allocate searcher T2 table */
7905 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7907 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7908 sizeof(struct host_sp_status_block));
7910 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7911 sizeof(struct bnx2x_slowpath));
7913 /* Allocate memory for CDU context:
7914 * This memory is allocated separately and not in the generic ILT
7915 * functions because CDU differs in few aspects:
7916 * 1. There are multiple entities allocating memory for context -
7917 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7918 * its own ILT lines.
7919 * 2. Since CDU page-size is not a single 4KB page (which is the case
7920 * for the other ILT clients), to be efficient we want to support
7921 * allocation of sub-page-size in the last entry.
7922 * 3. Context pointers are used by the driver to pass to FW / update
7923 * the context (for the other ILT clients the pointers are used just to
7924 * free the memory during unload).
7926 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7928 for (i = 0, allocated = 0; allocated < context_size; i++) {
7929 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7930 (context_size - allocated));
7931 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7932 &bp->context[i].cxt_mapping,
7933 bp->context[i].size);
7934 allocated += bp->context[i].size;
7936 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7938 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7941 if (bnx2x_iov_alloc_mem(bp))
7944 /* Slow path ring */
7945 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7948 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7949 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7955 BNX2X_ERR("Can't allocate memory\n");
7960 * Init service functions
7963 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7964 struct bnx2x_vlan_mac_obj *obj, bool set,
7965 int mac_type, unsigned long *ramrod_flags)
7968 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7970 memset(&ramrod_param, 0, sizeof(ramrod_param));
7972 /* Fill general parameters */
7973 ramrod_param.vlan_mac_obj = obj;
7974 ramrod_param.ramrod_flags = *ramrod_flags;
7976 /* Fill a user request section if needed */
7977 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7978 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7980 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7982 /* Set the command: ADD or DEL */
7984 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7986 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7989 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7991 if (rc == -EEXIST) {
7992 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7993 /* do not treat adding same MAC as error */
7996 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8001 int bnx2x_del_all_macs(struct bnx2x *bp,
8002 struct bnx2x_vlan_mac_obj *mac_obj,
8003 int mac_type, bool wait_for_comp)
8006 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8008 /* Wait for completion of requested */
8010 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8012 /* Set the mac type of addresses we want to clear */
8013 __set_bit(mac_type, &vlan_mac_flags);
8015 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8017 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8022 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8024 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8025 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8026 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8027 "Ignoring Zero MAC for STORAGE SD mode\n");
8032 unsigned long ramrod_flags = 0;
8034 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8035 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8036 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8037 &bp->sp_objs->mac_obj, set,
8038 BNX2X_ETH_MAC, &ramrod_flags);
8040 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8041 bp->fp->index, true);
8045 int bnx2x_setup_leading(struct bnx2x *bp)
8047 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
8051 * bnx2x_set_int_mode - configure interrupt mode
8053 * @bp: driver handle
8055 * In case of MSI-X it will also try to enable MSI-X.
8057 int bnx2x_set_int_mode(struct bnx2x *bp)
8061 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
8065 case BNX2X_INT_MODE_MSIX:
8066 /* attempt to enable msix */
8067 rc = bnx2x_enable_msix(bp);
8073 /* vfs use only msix */
8074 if (rc && IS_VF(bp))
8077 /* failed to enable multiple MSI-X */
8078 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8080 1 + bp->num_cnic_queues);
8082 /* falling through... */
8083 case BNX2X_INT_MODE_MSI:
8084 bnx2x_enable_msi(bp);
8086 /* falling through... */
8087 case BNX2X_INT_MODE_INTX:
8088 bp->num_ethernet_queues = 1;
8089 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8090 BNX2X_DEV_INFO("set number of queues to 1\n");
8093 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8099 /* must be called prior to any HW initializations */
8100 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8103 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8104 return L2_ILT_LINES(bp);
8107 void bnx2x_ilt_set_info(struct bnx2x *bp)
8109 struct ilt_client_info *ilt_client;
8110 struct bnx2x_ilt *ilt = BP_ILT(bp);
8113 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8114 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8117 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8118 ilt_client->client_num = ILT_CLIENT_CDU;
8119 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8120 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8121 ilt_client->start = line;
8122 line += bnx2x_cid_ilt_lines(bp);
8124 if (CNIC_SUPPORT(bp))
8125 line += CNIC_ILT_LINES;
8126 ilt_client->end = line - 1;
8128 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8131 ilt_client->page_size,
8133 ilog2(ilt_client->page_size >> 12));
8136 if (QM_INIT(bp->qm_cid_count)) {
8137 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8138 ilt_client->client_num = ILT_CLIENT_QM;
8139 ilt_client->page_size = QM_ILT_PAGE_SZ;
8140 ilt_client->flags = 0;
8141 ilt_client->start = line;
8143 /* 4 bytes for each cid */
8144 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8147 ilt_client->end = line - 1;
8150 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8153 ilt_client->page_size,
8155 ilog2(ilt_client->page_size >> 12));
8158 if (CNIC_SUPPORT(bp)) {
8160 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8161 ilt_client->client_num = ILT_CLIENT_SRC;
8162 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8163 ilt_client->flags = 0;
8164 ilt_client->start = line;
8165 line += SRC_ILT_LINES;
8166 ilt_client->end = line - 1;
8169 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8172 ilt_client->page_size,
8174 ilog2(ilt_client->page_size >> 12));
8177 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8178 ilt_client->client_num = ILT_CLIENT_TM;
8179 ilt_client->page_size = TM_ILT_PAGE_SZ;
8180 ilt_client->flags = 0;
8181 ilt_client->start = line;
8182 line += TM_ILT_LINES;
8183 ilt_client->end = line - 1;
8186 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8189 ilt_client->page_size,
8191 ilog2(ilt_client->page_size >> 12));
8194 BUG_ON(line > ILT_MAX_LINES);
8198 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8200 * @bp: driver handle
8201 * @fp: pointer to fastpath
8202 * @init_params: pointer to parameters structure
8204 * parameters configured:
8205 * - HC configuration
8206 * - Queue's CDU context
8208 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8209 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8212 int cxt_index, cxt_offset;
8214 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8215 if (!IS_FCOE_FP(fp)) {
8216 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8217 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8219 /* If HC is supported, enable host coalescing in the transition
8222 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8223 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8226 init_params->rx.hc_rate = bp->rx_ticks ?
8227 (1000000 / bp->rx_ticks) : 0;
8228 init_params->tx.hc_rate = bp->tx_ticks ?
8229 (1000000 / bp->tx_ticks) : 0;
8232 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8236 * CQ index among the SB indices: FCoE clients uses the default
8237 * SB, therefore it's different.
8239 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8240 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8243 /* set maximum number of COSs supported by this queue */
8244 init_params->max_cos = fp->max_cos;
8246 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8247 fp->index, init_params->max_cos);
8249 /* set the context pointers queue object */
8250 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8251 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8252 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8254 init_params->cxts[cos] =
8255 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8259 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8260 struct bnx2x_queue_state_params *q_params,
8261 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8262 int tx_index, bool leading)
8264 memset(tx_only_params, 0, sizeof(*tx_only_params));
8266 /* Set the command */
8267 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8269 /* Set tx-only QUEUE flags: don't zero statistics */
8270 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8272 /* choose the index of the cid to send the slow path on */
8273 tx_only_params->cid_index = tx_index;
8275 /* Set general TX_ONLY_SETUP parameters */
8276 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8278 /* Set Tx TX_ONLY_SETUP parameters */
8279 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8282 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8283 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8284 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8285 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8287 /* send the ramrod */
8288 return bnx2x_queue_state_change(bp, q_params);
8292 * bnx2x_setup_queue - setup queue
8294 * @bp: driver handle
8295 * @fp: pointer to fastpath
8296 * @leading: is leading
8298 * This function performs 2 steps in a Queue state machine
8299 * actually: 1) RESET->INIT 2) INIT->SETUP
8302 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8305 struct bnx2x_queue_state_params q_params = {NULL};
8306 struct bnx2x_queue_setup_params *setup_params =
8307 &q_params.params.setup;
8308 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8309 &q_params.params.tx_only;
8313 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8315 /* reset IGU state skip FCoE L2 queue */
8316 if (!IS_FCOE_FP(fp))
8317 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8320 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8321 /* We want to wait for completion in this context */
8322 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8324 /* Prepare the INIT parameters */
8325 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8327 /* Set the command */
8328 q_params.cmd = BNX2X_Q_CMD_INIT;
8330 /* Change the state to INIT */
8331 rc = bnx2x_queue_state_change(bp, &q_params);
8333 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8337 DP(NETIF_MSG_IFUP, "init complete\n");
8339 /* Now move the Queue to the SETUP state... */
8340 memset(setup_params, 0, sizeof(*setup_params));
8342 /* Set QUEUE flags */
8343 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8345 /* Set general SETUP parameters */
8346 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8347 FIRST_TX_COS_INDEX);
8349 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8350 &setup_params->rxq_params);
8352 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8353 FIRST_TX_COS_INDEX);
8355 /* Set the command */
8356 q_params.cmd = BNX2X_Q_CMD_SETUP;
8359 bp->fcoe_init = true;
8361 /* Change the state to SETUP */
8362 rc = bnx2x_queue_state_change(bp, &q_params);
8364 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8368 /* loop through the relevant tx-only indices */
8369 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8370 tx_index < fp->max_cos;
8373 /* prepare and send tx-only ramrod*/
8374 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8375 tx_only_params, tx_index, leading);
8377 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8378 fp->index, tx_index);
8386 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8388 struct bnx2x_fastpath *fp = &bp->fp[index];
8389 struct bnx2x_fp_txdata *txdata;
8390 struct bnx2x_queue_state_params q_params = {NULL};
8393 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8395 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8396 /* We want to wait for completion in this context */
8397 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8399 /* close tx-only connections */
8400 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8401 tx_index < fp->max_cos;
8404 /* ascertain this is a normal queue*/
8405 txdata = fp->txdata_ptr[tx_index];
8407 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8410 /* send halt terminate on tx-only connection */
8411 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8412 memset(&q_params.params.terminate, 0,
8413 sizeof(q_params.params.terminate));
8414 q_params.params.terminate.cid_index = tx_index;
8416 rc = bnx2x_queue_state_change(bp, &q_params);
8420 /* send halt terminate on tx-only connection */
8421 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8422 memset(&q_params.params.cfc_del, 0,
8423 sizeof(q_params.params.cfc_del));
8424 q_params.params.cfc_del.cid_index = tx_index;
8425 rc = bnx2x_queue_state_change(bp, &q_params);
8429 /* Stop the primary connection: */
8430 /* ...halt the connection */
8431 q_params.cmd = BNX2X_Q_CMD_HALT;
8432 rc = bnx2x_queue_state_change(bp, &q_params);
8436 /* ...terminate the connection */
8437 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8438 memset(&q_params.params.terminate, 0,
8439 sizeof(q_params.params.terminate));
8440 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8441 rc = bnx2x_queue_state_change(bp, &q_params);
8444 /* ...delete cfc entry */
8445 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8446 memset(&q_params.params.cfc_del, 0,
8447 sizeof(q_params.params.cfc_del));
8448 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8449 return bnx2x_queue_state_change(bp, &q_params);
8452 static void bnx2x_reset_func(struct bnx2x *bp)
8454 int port = BP_PORT(bp);
8455 int func = BP_FUNC(bp);
8458 /* Disable the function in the FW */
8459 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8460 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8461 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8462 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8465 for_each_eth_queue(bp, i) {
8466 struct bnx2x_fastpath *fp = &bp->fp[i];
8467 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8468 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8472 if (CNIC_LOADED(bp))
8474 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8475 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8476 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8479 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8480 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8483 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8484 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8488 if (bp->common.int_block == INT_BLOCK_HC) {
8489 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8490 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8492 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8493 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8496 if (CNIC_LOADED(bp)) {
8497 /* Disable Timer scan */
8498 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8500 * Wait for at least 10ms and up to 2 second for the timers
8503 for (i = 0; i < 200; i++) {
8504 usleep_range(10000, 20000);
8505 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8510 bnx2x_clear_func_ilt(bp, func);
8512 /* Timers workaround bug for E2: if this is vnic-3,
8513 * we need to set the entire ilt range for this timers.
8515 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8516 struct ilt_client_info ilt_cli;
8517 /* use dummy TM client */
8518 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8520 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8521 ilt_cli.client_num = ILT_CLIENT_TM;
8523 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8526 /* this assumes that reset_port() called before reset_func()*/
8527 if (!CHIP_IS_E1x(bp))
8528 bnx2x_pf_disable(bp);
8533 static void bnx2x_reset_port(struct bnx2x *bp)
8535 int port = BP_PORT(bp);
8538 /* Reset physical Link */
8539 bnx2x__link_reset(bp);
8541 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8543 /* Do not rcv packets to BRB */
8544 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8545 /* Do not direct rcv packets that are not for MCP to the BRB */
8546 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8547 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8550 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8553 /* Check for BRB port occupancy */
8554 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8556 DP(NETIF_MSG_IFDOWN,
8557 "BRB1 is not empty %d blocks are occupied\n", val);
8559 /* TODO: Close Doorbell port? */
8562 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8564 struct bnx2x_func_state_params func_params = {NULL};
8566 /* Prepare parameters for function state transitions */
8567 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8569 func_params.f_obj = &bp->func_obj;
8570 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8572 func_params.params.hw_init.load_phase = load_code;
8574 return bnx2x_func_state_change(bp, &func_params);
8577 static int bnx2x_func_stop(struct bnx2x *bp)
8579 struct bnx2x_func_state_params func_params = {NULL};
8582 /* Prepare parameters for function state transitions */
8583 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8584 func_params.f_obj = &bp->func_obj;
8585 func_params.cmd = BNX2X_F_CMD_STOP;
8588 * Try to stop the function the 'good way'. If fails (in case
8589 * of a parity error during bnx2x_chip_cleanup()) and we are
8590 * not in a debug mode, perform a state transaction in order to
8591 * enable further HW_RESET transaction.
8593 rc = bnx2x_func_state_change(bp, &func_params);
8595 #ifdef BNX2X_STOP_ON_ERROR
8598 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8599 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8600 return bnx2x_func_state_change(bp, &func_params);
8608 * bnx2x_send_unload_req - request unload mode from the MCP.
8610 * @bp: driver handle
8611 * @unload_mode: requested function's unload mode
8613 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8615 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8618 int port = BP_PORT(bp);
8620 /* Select the UNLOAD request mode */
8621 if (unload_mode == UNLOAD_NORMAL)
8622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8624 else if (bp->flags & NO_WOL_FLAG)
8625 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8628 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8629 u8 *mac_addr = bp->dev->dev_addr;
8633 /* The mac address is written to entries 1-4 to
8634 * preserve entry 0 which is used by the PMF
8636 u8 entry = (BP_VN(bp) + 1)*8;
8638 val = (mac_addr[0] << 8) | mac_addr[1];
8639 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8641 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8642 (mac_addr[4] << 8) | mac_addr[5];
8643 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8645 /* Enable the PME and clear the status */
8646 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8647 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8648 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8650 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8653 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8655 /* Send the request to the MCP */
8657 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8659 int path = BP_PATH(bp);
8661 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8662 path, load_count[path][0], load_count[path][1],
8663 load_count[path][2]);
8664 load_count[path][0]--;
8665 load_count[path][1 + port]--;
8666 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8667 path, load_count[path][0], load_count[path][1],
8668 load_count[path][2]);
8669 if (load_count[path][0] == 0)
8670 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8671 else if (load_count[path][1 + port] == 0)
8672 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8674 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8681 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8683 * @bp: driver handle
8684 * @keep_link: true iff link should be kept up
8686 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8688 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8690 /* Report UNLOAD_DONE to MCP */
8692 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8695 static int bnx2x_func_wait_started(struct bnx2x *bp)
8698 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8704 * (assumption: No Attention from MCP at this stage)
8705 * PMF probably in the middle of TX disable/enable transaction
8706 * 1. Sync IRS for default SB
8707 * 2. Sync SP queue - this guarantees us that attention handling started
8708 * 3. Wait, that TX disable/enable transaction completes
8710 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8711 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8712 * received completion for the transaction the state is TX_STOPPED.
8713 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8717 /* make sure default SB ISR is done */
8719 synchronize_irq(bp->msix_table[0].vector);
8721 synchronize_irq(bp->pdev->irq);
8723 flush_workqueue(bnx2x_wq);
8725 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8726 BNX2X_F_STATE_STARTED && tout--)
8729 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8730 BNX2X_F_STATE_STARTED) {
8731 #ifdef BNX2X_STOP_ON_ERROR
8732 BNX2X_ERR("Wrong function state\n");
8736 * Failed to complete the transaction in a "good way"
8737 * Force both transactions with CLR bit
8739 struct bnx2x_func_state_params func_params = {NULL};
8741 DP(NETIF_MSG_IFDOWN,
8742 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8744 func_params.f_obj = &bp->func_obj;
8745 __set_bit(RAMROD_DRV_CLR_ONLY,
8746 &func_params.ramrod_flags);
8748 /* STARTED-->TX_ST0PPED */
8749 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8750 bnx2x_func_state_change(bp, &func_params);
8752 /* TX_ST0PPED-->STARTED */
8753 func_params.cmd = BNX2X_F_CMD_TX_START;
8754 return bnx2x_func_state_change(bp, &func_params);
8761 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8763 int port = BP_PORT(bp);
8766 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8769 /* Wait until tx fastpath tasks complete */
8770 for_each_tx_queue(bp, i) {
8771 struct bnx2x_fastpath *fp = &bp->fp[i];
8773 for_each_cos_in_tx_queue(fp, cos)
8774 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8775 #ifdef BNX2X_STOP_ON_ERROR
8781 /* Give HW time to discard old tx messages */
8782 usleep_range(1000, 2000);
8784 /* Clean all ETH MACs */
8785 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8788 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8790 /* Clean up UC list */
8791 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8794 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8798 if (!CHIP_IS_E1(bp))
8799 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8801 /* Set "drop all" (stop Rx).
8802 * We need to take a netif_addr_lock() here in order to prevent
8803 * a race between the completion code and this code.
8805 netif_addr_lock_bh(bp->dev);
8806 /* Schedule the rx_mode command */
8807 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8808 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8810 bnx2x_set_storm_rx_mode(bp);
8812 /* Cleanup multicast configuration */
8813 rparam.mcast_obj = &bp->mcast_obj;
8814 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8816 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8818 netif_addr_unlock_bh(bp->dev);
8820 bnx2x_iov_chip_cleanup(bp);
8823 * Send the UNLOAD_REQUEST to the MCP. This will return if
8824 * this function should perform FUNC, PORT or COMMON HW
8827 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8830 * (assumption: No Attention from MCP at this stage)
8831 * PMF probably in the middle of TX disable/enable transaction
8833 rc = bnx2x_func_wait_started(bp);
8835 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8836 #ifdef BNX2X_STOP_ON_ERROR
8841 /* Close multi and leading connections
8842 * Completions for ramrods are collected in a synchronous way
8844 for_each_eth_queue(bp, i)
8845 if (bnx2x_stop_queue(bp, i))
8846 #ifdef BNX2X_STOP_ON_ERROR
8852 if (CNIC_LOADED(bp)) {
8853 for_each_cnic_queue(bp, i)
8854 if (bnx2x_stop_queue(bp, i))
8855 #ifdef BNX2X_STOP_ON_ERROR
8862 /* If SP settings didn't get completed so far - something
8863 * very wrong has happen.
8865 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8866 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8868 #ifndef BNX2X_STOP_ON_ERROR
8871 rc = bnx2x_func_stop(bp);
8873 BNX2X_ERR("Function stop failed!\n");
8874 #ifdef BNX2X_STOP_ON_ERROR
8879 /* Disable HW interrupts, NAPI */
8880 bnx2x_netif_stop(bp, 1);
8881 /* Delete all NAPI objects */
8882 bnx2x_del_all_napi(bp);
8883 if (CNIC_LOADED(bp))
8884 bnx2x_del_all_napi_cnic(bp);
8889 /* Reset the chip */
8890 rc = bnx2x_reset_hw(bp, reset_code);
8892 BNX2X_ERR("HW_RESET failed\n");
8894 /* Report UNLOAD_DONE to MCP */
8895 bnx2x_send_unload_done(bp, keep_link);
8898 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8902 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8904 if (CHIP_IS_E1(bp)) {
8905 int port = BP_PORT(bp);
8906 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8907 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8909 val = REG_RD(bp, addr);
8911 REG_WR(bp, addr, val);
8913 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8914 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8915 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8916 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8920 /* Close gates #2, #3 and #4: */
8921 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8925 /* Gates #2 and #4a are closed/opened for "not E1" only */
8926 if (!CHIP_IS_E1(bp)) {
8928 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8930 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8934 if (CHIP_IS_E1x(bp)) {
8935 /* Prevent interrupts from HC on both ports */
8936 val = REG_RD(bp, HC_REG_CONFIG_1);
8937 REG_WR(bp, HC_REG_CONFIG_1,
8938 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8939 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8941 val = REG_RD(bp, HC_REG_CONFIG_0);
8942 REG_WR(bp, HC_REG_CONFIG_0,
8943 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8944 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8946 /* Prevent incoming interrupts in IGU */
8947 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8949 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8951 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8952 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8955 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8956 close ? "closing" : "opening");
8960 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8962 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8964 /* Do some magic... */
8965 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8966 *magic_val = val & SHARED_MF_CLP_MAGIC;
8967 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8971 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8973 * @bp: driver handle
8974 * @magic_val: old value of the `magic' bit.
8976 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8978 /* Restore the `magic' bit value... */
8979 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8980 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8981 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8985 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8987 * @bp: driver handle
8988 * @magic_val: old value of 'magic' bit.
8990 * Takes care of CLP configurations.
8992 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8995 u32 validity_offset;
8997 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8999 /* Set `magic' bit in order to save MF config */
9000 if (!CHIP_IS_E1(bp))
9001 bnx2x_clp_reset_prep(bp, magic_val);
9003 /* Get shmem offset */
9004 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9006 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9008 /* Clear validity map flags */
9010 REG_WR(bp, shmem + validity_offset, 0);
9013 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9014 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9017 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9019 * @bp: driver handle
9021 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9023 /* special handling for emulation and FPGA,
9024 wait 10 times longer */
9025 if (CHIP_REV_IS_SLOW(bp))
9026 msleep(MCP_ONE_TIMEOUT*10);
9028 msleep(MCP_ONE_TIMEOUT);
9032 * initializes bp->common.shmem_base and waits for validity signature to appear
9034 static int bnx2x_init_shmem(struct bnx2x *bp)
9040 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9041 if (bp->common.shmem_base) {
9042 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9043 if (val & SHR_MEM_VALIDITY_MB)
9047 bnx2x_mcp_wait_one(bp);
9049 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9051 BNX2X_ERR("BAD MCP validity signature\n");
9056 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9058 int rc = bnx2x_init_shmem(bp);
9060 /* Restore the `magic' bit value */
9061 if (!CHIP_IS_E1(bp))
9062 bnx2x_clp_reset_done(bp, magic_val);
9067 static void bnx2x_pxp_prep(struct bnx2x *bp)
9069 if (!CHIP_IS_E1(bp)) {
9070 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9071 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9077 * Reset the whole chip except for:
9079 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9082 * - MISC (including AEU)
9086 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9088 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9089 u32 global_bits2, stay_reset2;
9092 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9093 * (per chip) blocks.
9096 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9097 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9099 /* Don't reset the following blocks.
9100 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9101 * reset, as in 4 port device they might still be owned
9102 * by the MCP (there is only one leader per path).
9105 MISC_REGISTERS_RESET_REG_1_RST_HC |
9106 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9107 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9110 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9111 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9112 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9113 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9114 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9115 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9116 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9117 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9118 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9119 MISC_REGISTERS_RESET_REG_2_PGLC |
9120 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9121 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9122 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9123 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9124 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9125 MISC_REGISTERS_RESET_REG_2_UMAC1;
9128 * Keep the following blocks in reset:
9129 * - all xxMACs are handled by the bnx2x_link code.
9132 MISC_REGISTERS_RESET_REG_2_XMAC |
9133 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9135 /* Full reset masks according to the chip */
9136 reset_mask1 = 0xffffffff;
9139 reset_mask2 = 0xffff;
9140 else if (CHIP_IS_E1H(bp))
9141 reset_mask2 = 0x1ffff;
9142 else if (CHIP_IS_E2(bp))
9143 reset_mask2 = 0xfffff;
9144 else /* CHIP_IS_E3 */
9145 reset_mask2 = 0x3ffffff;
9147 /* Don't reset global blocks unless we need to */
9149 reset_mask2 &= ~global_bits2;
9152 * In case of attention in the QM, we need to reset PXP
9153 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9154 * because otherwise QM reset would release 'close the gates' shortly
9155 * before resetting the PXP, then the PSWRQ would send a write
9156 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9157 * read the payload data from PSWWR, but PSWWR would not
9158 * respond. The write queue in PGLUE would stuck, dmae commands
9159 * would not return. Therefore it's important to reset the second
9160 * reset register (containing the
9161 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9162 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9165 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9166 reset_mask2 & (~not_reset_mask2));
9168 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9169 reset_mask1 & (~not_reset_mask1));
9174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9175 reset_mask2 & (~stay_reset2));
9180 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9185 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9186 * It should get cleared in no more than 1s.
9188 * @bp: driver handle
9190 * It should get cleared in no more than 1s. Returns 0 if
9191 * pending writes bit gets cleared.
9193 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9199 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9204 usleep_range(1000, 2000);
9205 } while (cnt-- > 0);
9208 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9216 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9220 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9223 /* Empty the Tetris buffer, wait for 1s */
9225 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9226 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9227 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9228 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9229 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9231 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9233 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9234 ((port_is_idle_0 & 0x1) == 0x1) &&
9235 ((port_is_idle_1 & 0x1) == 0x1) &&
9236 (pgl_exp_rom2 == 0xffffffff) &&
9237 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9239 usleep_range(1000, 2000);
9240 } while (cnt-- > 0);
9243 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9244 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9245 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9252 /* Close gates #2, #3 and #4 */
9253 bnx2x_set_234_gates(bp, true);
9255 /* Poll for IGU VQs for 57712 and newer chips */
9256 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9259 /* TBD: Indicate that "process kill" is in progress to MCP */
9261 /* Clear "unprepared" bit */
9262 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9265 /* Make sure all is written to the chip before the reset */
9268 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9269 * PSWHST, GRC and PSWRD Tetris buffer.
9271 usleep_range(1000, 2000);
9273 /* Prepare to chip reset: */
9276 bnx2x_reset_mcp_prep(bp, &val);
9282 /* reset the chip */
9283 bnx2x_process_kill_chip_reset(bp, global);
9286 /* Recover after reset: */
9288 if (global && bnx2x_reset_mcp_comp(bp, val))
9291 /* TBD: Add resetting the NO_MCP mode DB here */
9293 /* Open the gates #2, #3 and #4 */
9294 bnx2x_set_234_gates(bp, false);
9296 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9297 * reset state, re-enable attentions. */
9302 static int bnx2x_leader_reset(struct bnx2x *bp)
9305 bool global = bnx2x_reset_is_global(bp);
9308 /* if not going to reset MCP - load "fake" driver to reset HW while
9309 * driver is owner of the HW
9311 if (!global && !BP_NOMCP(bp)) {
9312 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9313 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9315 BNX2X_ERR("MCP response failure, aborting\n");
9317 goto exit_leader_reset;
9319 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9320 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9321 BNX2X_ERR("MCP unexpected resp, aborting\n");
9323 goto exit_leader_reset2;
9325 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9327 BNX2X_ERR("MCP response failure, aborting\n");
9329 goto exit_leader_reset2;
9333 /* Try to recover after the failure */
9334 if (bnx2x_process_kill(bp, global)) {
9335 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9338 goto exit_leader_reset2;
9342 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9345 bnx2x_set_reset_done(bp);
9347 bnx2x_clear_reset_global(bp);
9350 /* unload "fake driver" if it was loaded */
9351 if (!global && !BP_NOMCP(bp)) {
9352 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9353 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9357 bnx2x_release_leader_lock(bp);
9362 static void bnx2x_recovery_failed(struct bnx2x *bp)
9364 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9366 /* Disconnect this device */
9367 netif_device_detach(bp->dev);
9370 * Block ifup for all function on this engine until "process kill"
9373 bnx2x_set_reset_in_progress(bp);
9375 /* Shut down the power */
9376 bnx2x_set_power_state(bp, PCI_D3hot);
9378 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9384 * Assumption: runs under rtnl lock. This together with the fact
9385 * that it's called only from bnx2x_sp_rtnl() ensure that it
9386 * will never be called when netif_running(bp->dev) is false.
9388 static void bnx2x_parity_recover(struct bnx2x *bp)
9390 bool global = false;
9391 u32 error_recovered, error_unrecovered;
9394 DP(NETIF_MSG_HW, "Handling parity\n");
9396 switch (bp->recovery_state) {
9397 case BNX2X_RECOVERY_INIT:
9398 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9399 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9400 WARN_ON(!is_parity);
9402 /* Try to get a LEADER_LOCK HW lock */
9403 if (bnx2x_trylock_leader_lock(bp)) {
9404 bnx2x_set_reset_in_progress(bp);
9406 * Check if there is a global attention and if
9407 * there was a global attention, set the global
9412 bnx2x_set_reset_global(bp);
9417 /* Stop the driver */
9418 /* If interface has been removed - break */
9419 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9422 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9424 /* Ensure "is_leader", MCP command sequence and
9425 * "recovery_state" update values are seen on other
9431 case BNX2X_RECOVERY_WAIT:
9432 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9433 if (bp->is_leader) {
9434 int other_engine = BP_PATH(bp) ? 0 : 1;
9435 bool other_load_status =
9436 bnx2x_get_load_status(bp, other_engine);
9438 bnx2x_get_load_status(bp, BP_PATH(bp));
9439 global = bnx2x_reset_is_global(bp);
9442 * In case of a parity in a global block, let
9443 * the first leader that performs a
9444 * leader_reset() reset the global blocks in
9445 * order to clear global attentions. Otherwise
9446 * the gates will remain closed for that
9450 (global && other_load_status)) {
9451 /* Wait until all other functions get
9454 schedule_delayed_work(&bp->sp_rtnl_task,
9458 /* If all other functions got down -
9459 * try to bring the chip back to
9460 * normal. In any case it's an exit
9461 * point for a leader.
9463 if (bnx2x_leader_reset(bp)) {
9464 bnx2x_recovery_failed(bp);
9468 /* If we are here, means that the
9469 * leader has succeeded and doesn't
9470 * want to be a leader any more. Try
9471 * to continue as a none-leader.
9475 } else { /* non-leader */
9476 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9477 /* Try to get a LEADER_LOCK HW lock as
9478 * long as a former leader may have
9479 * been unloaded by the user or
9480 * released a leadership by another
9483 if (bnx2x_trylock_leader_lock(bp)) {
9484 /* I'm a leader now! Restart a
9491 schedule_delayed_work(&bp->sp_rtnl_task,
9497 * If there was a global attention, wait
9498 * for it to be cleared.
9500 if (bnx2x_reset_is_global(bp)) {
9501 schedule_delayed_work(
9508 bp->eth_stats.recoverable_error;
9510 bp->eth_stats.unrecoverable_error;
9511 bp->recovery_state =
9512 BNX2X_RECOVERY_NIC_LOADING;
9513 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9514 error_unrecovered++;
9516 "Recovery failed. Power cycle needed\n");
9517 /* Disconnect this device */
9518 netif_device_detach(bp->dev);
9519 /* Shut down the power */
9520 bnx2x_set_power_state(
9524 bp->recovery_state =
9525 BNX2X_RECOVERY_DONE;
9529 bp->eth_stats.recoverable_error =
9531 bp->eth_stats.unrecoverable_error =
9543 static int bnx2x_close(struct net_device *dev);
9545 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9546 * scheduled on a general queue in order to prevent a dead lock.
9548 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9550 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9554 if (!netif_running(bp->dev)) {
9559 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9560 #ifdef BNX2X_STOP_ON_ERROR
9561 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9562 "you will need to reboot when done\n");
9563 goto sp_rtnl_not_reset;
9566 * Clear all pending SP commands as we are going to reset the
9569 bp->sp_rtnl_state = 0;
9572 bnx2x_parity_recover(bp);
9578 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9579 #ifdef BNX2X_STOP_ON_ERROR
9580 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9581 "you will need to reboot when done\n");
9582 goto sp_rtnl_not_reset;
9586 * Clear all pending SP commands as we are going to reset the
9589 bp->sp_rtnl_state = 0;
9592 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9593 bnx2x_nic_load(bp, LOAD_NORMAL);
9598 #ifdef BNX2X_STOP_ON_ERROR
9601 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9602 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9603 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9604 bnx2x_after_function_update(bp);
9606 * in case of fan failure we need to reset id if the "stop on error"
9607 * debug flag is set, since we trying to prevent permanent overheating
9610 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9611 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9612 netif_device_detach(bp->dev);
9613 bnx2x_close(bp->dev);
9618 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9620 "sending set mcast vf pf channel message from rtnl sp-task\n");
9621 bnx2x_vfpf_set_mcast(bp->dev);
9623 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9624 &bp->sp_rtnl_state)){
9625 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9626 bnx2x_tx_disable(bp);
9627 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9631 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9632 &bp->sp_rtnl_state)) {
9634 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9635 bnx2x_vfpf_storm_rx_mode(bp);
9638 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9639 &bp->sp_rtnl_state))
9640 bnx2x_pf_set_vfs_vlan(bp);
9642 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9643 * can be called from other contexts as well)
9647 /* enable SR-IOV if applicable */
9648 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9649 &bp->sp_rtnl_state)) {
9650 bnx2x_disable_sriov(bp);
9651 bnx2x_enable_sriov(bp);
9655 static void bnx2x_period_task(struct work_struct *work)
9657 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9659 if (!netif_running(bp->dev))
9660 goto period_task_exit;
9662 if (CHIP_REV_IS_SLOW(bp)) {
9663 BNX2X_ERR("period task called on emulation, ignoring\n");
9664 goto period_task_exit;
9667 bnx2x_acquire_phy_lock(bp);
9669 * The barrier is needed to ensure the ordering between the writing to
9670 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9675 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9677 /* Re-queue task in 1 sec */
9678 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9681 bnx2x_release_phy_lock(bp);
9687 * Init service functions
9690 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9692 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9693 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9694 return base + (BP_ABS_FUNC(bp)) * stride;
9697 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9698 struct bnx2x_mac_vals *vals)
9700 u32 val, base_addr, offset, mask, reset_reg;
9701 bool mac_stopped = false;
9702 u8 port = BP_PORT(bp);
9704 /* reset addresses as they also mark which values were changed */
9705 vals->bmac_addr = 0;
9706 vals->umac_addr = 0;
9707 vals->xmac_addr = 0;
9708 vals->emac_addr = 0;
9710 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9712 if (!CHIP_IS_E3(bp)) {
9713 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9714 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9715 if ((mask & reset_reg) && val) {
9717 BNX2X_DEV_INFO("Disable bmac Rx\n");
9718 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9719 : NIG_REG_INGRESS_BMAC0_MEM;
9720 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9721 : BIGMAC_REGISTER_BMAC_CONTROL;
9724 * use rd/wr since we cannot use dmae. This is safe
9725 * since MCP won't access the bus due to the request
9726 * to unload, and no function on the path can be
9727 * loaded at this time.
9729 wb_data[0] = REG_RD(bp, base_addr + offset);
9730 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9731 vals->bmac_addr = base_addr + offset;
9732 vals->bmac_val[0] = wb_data[0];
9733 vals->bmac_val[1] = wb_data[1];
9734 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9735 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9736 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9738 BNX2X_DEV_INFO("Disable emac Rx\n");
9739 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9740 vals->emac_val = REG_RD(bp, vals->emac_addr);
9741 REG_WR(bp, vals->emac_addr, 0);
9744 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9745 BNX2X_DEV_INFO("Disable xmac Rx\n");
9746 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9747 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9748 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9750 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9752 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9753 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9754 REG_WR(bp, vals->xmac_addr, 0);
9757 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9758 if (mask & reset_reg) {
9759 BNX2X_DEV_INFO("Disable umac Rx\n");
9760 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9761 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9762 vals->umac_val = REG_RD(bp, vals->umac_addr);
9763 REG_WR(bp, vals->umac_addr, 0);
9772 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9773 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9774 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9775 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9777 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9780 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9782 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9783 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9785 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9786 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9788 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9792 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9794 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9795 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9797 BNX2X_ERR("MCP response failure, aborting\n");
9804 static struct bnx2x_prev_path_list *
9805 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9807 struct bnx2x_prev_path_list *tmp_list;
9809 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9810 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9811 bp->pdev->bus->number == tmp_list->bus &&
9812 BP_PATH(bp) == tmp_list->path)
9818 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9820 struct bnx2x_prev_path_list *tmp_list;
9823 rc = down_interruptible(&bnx2x_prev_sem);
9825 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9829 tmp_list = bnx2x_prev_path_get_entry(bp);
9834 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9838 up(&bnx2x_prev_sem);
9843 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9845 struct bnx2x_prev_path_list *tmp_list;
9848 if (down_trylock(&bnx2x_prev_sem))
9851 tmp_list = bnx2x_prev_path_get_entry(bp);
9853 if (tmp_list->aer) {
9854 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9858 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9863 up(&bnx2x_prev_sem);
9868 bool bnx2x_port_after_undi(struct bnx2x *bp)
9870 struct bnx2x_prev_path_list *entry;
9873 down(&bnx2x_prev_sem);
9875 entry = bnx2x_prev_path_get_entry(bp);
9876 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9878 up(&bnx2x_prev_sem);
9883 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9885 struct bnx2x_prev_path_list *tmp_list;
9888 rc = down_interruptible(&bnx2x_prev_sem);
9890 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9894 /* Check whether the entry for this path already exists */
9895 tmp_list = bnx2x_prev_path_get_entry(bp);
9897 if (!tmp_list->aer) {
9898 BNX2X_ERR("Re-Marking the path.\n");
9900 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9904 up(&bnx2x_prev_sem);
9907 up(&bnx2x_prev_sem);
9909 /* Create an entry for this path and add it */
9910 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9912 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9916 tmp_list->bus = bp->pdev->bus->number;
9917 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9918 tmp_list->path = BP_PATH(bp);
9920 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9922 rc = down_interruptible(&bnx2x_prev_sem);
9924 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9927 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9929 list_add(&tmp_list->list, &bnx2x_prev_list);
9930 up(&bnx2x_prev_sem);
9936 static int bnx2x_do_flr(struct bnx2x *bp)
9940 struct pci_dev *dev = bp->pdev;
9942 if (CHIP_IS_E1x(bp)) {
9943 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9947 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9948 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9949 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9954 /* Wait for Transaction Pending bit clean */
9955 for (i = 0; i < 4; i++) {
9957 msleep((1 << (i - 1)) * 100);
9959 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9960 if (!(status & PCI_EXP_DEVSTA_TRPND))
9965 "transaction is not cleared; proceeding with reset anyway\n");
9969 BNX2X_DEV_INFO("Initiating FLR\n");
9970 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9975 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9979 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9981 /* Test if previous unload process was already finished for this path */
9982 if (bnx2x_prev_is_path_marked(bp))
9983 return bnx2x_prev_mcp_done(bp);
9985 BNX2X_DEV_INFO("Path is unmarked\n");
9987 /* If function has FLR capabilities, and existing FW version matches
9988 * the one required, then FLR will be sufficient to clean any residue
9989 * left by previous driver
9991 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9994 /* fw version is good */
9995 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9996 rc = bnx2x_do_flr(bp);
10000 /* FLR was performed */
10001 BNX2X_DEV_INFO("FLR successful\n");
10005 BNX2X_DEV_INFO("Could not FLR\n");
10007 /* Close the MCP request, return failure*/
10008 rc = bnx2x_prev_mcp_done(bp);
10010 rc = BNX2X_PREV_WAIT_NEEDED;
10015 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10017 u32 reset_reg, tmp_reg = 0, rc;
10018 bool prev_undi = false;
10019 struct bnx2x_mac_vals mac_vals;
10021 /* It is possible a previous function received 'common' answer,
10022 * but hasn't loaded yet, therefore creating a scenario of
10023 * multiple functions receiving 'common' on the same path.
10025 BNX2X_DEV_INFO("Common unload Flow\n");
10027 memset(&mac_vals, 0, sizeof(mac_vals));
10029 if (bnx2x_prev_is_path_marked(bp))
10030 return bnx2x_prev_mcp_done(bp);
10032 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10034 /* Reset should be performed after BRB is emptied */
10035 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10036 u32 timer_count = 1000;
10038 /* Close the MAC Rx to prevent BRB from filling up */
10039 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10041 /* close LLH filters towards the BRB */
10042 bnx2x_set_rx_filter(&bp->link_params, 0);
10044 /* Check if the UNDI driver was previously loaded
10045 * UNDI driver initializes CID offset for normal bell to 0x7
10047 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10048 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10049 if (tmp_reg == 0x7) {
10050 BNX2X_DEV_INFO("UNDI previously loaded\n");
10052 /* clear the UNDI indication */
10053 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10054 /* clear possible idle check errors */
10055 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10058 if (!CHIP_IS_E1x(bp))
10059 /* block FW from writing to host */
10060 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10062 /* wait until BRB is empty */
10063 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10064 while (timer_count) {
10065 u32 prev_brb = tmp_reg;
10067 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10071 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10073 /* reset timer as long as BRB actually gets emptied */
10074 if (prev_brb > tmp_reg)
10075 timer_count = 1000;
10079 /* If UNDI resides in memory, manually increment it */
10081 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10087 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10090 /* No packets are in the pipeline, path is ready for reset */
10091 bnx2x_reset_common(bp);
10093 if (mac_vals.xmac_addr)
10094 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10095 if (mac_vals.umac_addr)
10096 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10097 if (mac_vals.emac_addr)
10098 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10099 if (mac_vals.bmac_addr) {
10100 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10101 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10104 rc = bnx2x_prev_mark_path(bp, prev_undi);
10106 bnx2x_prev_mcp_done(bp);
10110 return bnx2x_prev_mcp_done(bp);
10113 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10114 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10115 * the addresses of the transaction, resulting in was-error bit set in the pci
10116 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10117 * to clear the interrupt which detected this from the pglueb and the was done
10120 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10122 if (!CHIP_IS_E1x(bp)) {
10123 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10124 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10126 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10127 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10133 static int bnx2x_prev_unload(struct bnx2x *bp)
10135 int time_counter = 10;
10136 u32 rc, fw, hw_lock_reg, hw_lock_val;
10137 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10139 /* clear hw from errors which may have resulted from an interrupted
10140 * dmae transaction.
10142 bnx2x_prev_interrupted_dmae(bp);
10144 /* Release previously held locks */
10145 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10146 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10147 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10149 hw_lock_val = REG_RD(bp, hw_lock_reg);
10151 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10152 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10153 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10154 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10157 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10158 REG_WR(bp, hw_lock_reg, 0xffffffff);
10160 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10162 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10163 BNX2X_DEV_INFO("Release previously held alr\n");
10164 bnx2x_release_alr(bp);
10169 /* Lock MCP using an unload request */
10170 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10172 BNX2X_ERR("MCP response failure, aborting\n");
10177 rc = down_interruptible(&bnx2x_prev_sem);
10179 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10182 /* If Path is marked by EEH, ignore unload status */
10183 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10184 bnx2x_prev_path_get_entry(bp)->aer);
10185 up(&bnx2x_prev_sem);
10188 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10189 rc = bnx2x_prev_unload_common(bp);
10193 /* non-common reply from MCP might require looping */
10194 rc = bnx2x_prev_unload_uncommon(bp);
10195 if (rc != BNX2X_PREV_WAIT_NEEDED)
10199 } while (--time_counter);
10201 if (!time_counter || rc) {
10202 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10206 /* Mark function if its port was used to boot from SAN */
10207 if (bnx2x_port_after_undi(bp))
10208 bp->link_params.feature_config_flags |=
10209 FEATURE_CONFIG_BOOT_FROM_SAN;
10211 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10216 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10218 u32 val, val2, val3, val4, id, boot_mode;
10221 /* Get the chip revision id and number. */
10222 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10223 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10224 id = ((val & 0xffff) << 16);
10225 val = REG_RD(bp, MISC_REG_CHIP_REV);
10226 id |= ((val & 0xf) << 12);
10228 /* Metal is read from PCI regs, but we can't access >=0x400 from
10229 * the configuration space (so we need to reg_rd)
10231 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10232 id |= (((val >> 24) & 0xf) << 4);
10233 val = REG_RD(bp, MISC_REG_BOND_ID);
10235 bp->common.chip_id = id;
10237 /* force 57811 according to MISC register */
10238 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10239 if (CHIP_IS_57810(bp))
10240 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10241 (bp->common.chip_id & 0x0000FFFF);
10242 else if (CHIP_IS_57810_MF(bp))
10243 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10244 (bp->common.chip_id & 0x0000FFFF);
10245 bp->common.chip_id |= 0x1;
10248 /* Set doorbell size */
10249 bp->db_size = (1 << BNX2X_DB_SHIFT);
10251 if (!CHIP_IS_E1x(bp)) {
10252 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10253 if ((val & 1) == 0)
10254 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10256 val = (val >> 1) & 1;
10257 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10259 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10262 if (CHIP_MODE_IS_4_PORT(bp))
10263 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10265 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10267 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10268 bp->pfid = bp->pf_num; /* 0..7 */
10271 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10273 bp->link_params.chip_id = bp->common.chip_id;
10274 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10276 val = (REG_RD(bp, 0x2874) & 0x55);
10277 if ((bp->common.chip_id & 0x1) ||
10278 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10279 bp->flags |= ONE_PORT_FLAG;
10280 BNX2X_DEV_INFO("single port device\n");
10283 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10284 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10285 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10286 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10287 bp->common.flash_size, bp->common.flash_size);
10289 bnx2x_init_shmem(bp);
10291 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10292 MISC_REG_GENERIC_CR_1 :
10293 MISC_REG_GENERIC_CR_0));
10295 bp->link_params.shmem_base = bp->common.shmem_base;
10296 bp->link_params.shmem2_base = bp->common.shmem2_base;
10297 if (SHMEM2_RD(bp, size) >
10298 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10299 bp->link_params.lfa_base =
10300 REG_RD(bp, bp->common.shmem2_base +
10301 (u32)offsetof(struct shmem2_region,
10302 lfa_host_addr[BP_PORT(bp)]));
10304 bp->link_params.lfa_base = 0;
10305 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10306 bp->common.shmem_base, bp->common.shmem2_base);
10308 if (!bp->common.shmem_base) {
10309 BNX2X_DEV_INFO("MCP not active\n");
10310 bp->flags |= NO_MCP_FLAG;
10314 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10315 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10317 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10318 SHARED_HW_CFG_LED_MODE_MASK) >>
10319 SHARED_HW_CFG_LED_MODE_SHIFT);
10321 bp->link_params.feature_config_flags = 0;
10322 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10323 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10324 bp->link_params.feature_config_flags |=
10325 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10327 bp->link_params.feature_config_flags &=
10328 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10330 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10331 bp->common.bc_ver = val;
10332 BNX2X_DEV_INFO("bc_ver %X\n", val);
10333 if (val < BNX2X_BC_VER) {
10334 /* for now only warn
10335 * later we might need to enforce this */
10336 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10337 BNX2X_BC_VER, val);
10339 bp->link_params.feature_config_flags |=
10340 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10341 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10343 bp->link_params.feature_config_flags |=
10344 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10345 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10346 bp->link_params.feature_config_flags |=
10347 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10348 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10349 bp->link_params.feature_config_flags |=
10350 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10351 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10353 bp->link_params.feature_config_flags |=
10354 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10355 FEATURE_CONFIG_MT_SUPPORT : 0;
10357 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10358 BC_SUPPORTS_PFC_STATS : 0;
10360 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10361 BC_SUPPORTS_FCOE_FEATURES : 0;
10363 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10364 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10365 boot_mode = SHMEM_RD(bp,
10366 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10367 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10368 switch (boot_mode) {
10369 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10370 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10372 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10373 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10375 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10376 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10378 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10379 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10383 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10384 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10386 BNX2X_DEV_INFO("%sWoL capable\n",
10387 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10389 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10390 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10391 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10392 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10394 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10395 val, val2, val3, val4);
10398 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10399 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10401 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10403 int pfid = BP_FUNC(bp);
10406 u8 fid, igu_sb_cnt = 0;
10408 bp->igu_base_sb = 0xff;
10409 if (CHIP_INT_MODE_IS_BC(bp)) {
10410 int vn = BP_VN(bp);
10411 igu_sb_cnt = bp->igu_sb_cnt;
10412 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10415 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10416 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10421 /* IGU in normal mode - read CAM */
10422 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10424 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10425 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10427 fid = IGU_FID(val);
10428 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10429 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10431 if (IGU_VEC(val) == 0)
10432 /* default status block */
10433 bp->igu_dsb_id = igu_sb_id;
10435 if (bp->igu_base_sb == 0xff)
10436 bp->igu_base_sb = igu_sb_id;
10442 #ifdef CONFIG_PCI_MSI
10443 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10444 * optional that number of CAM entries will not be equal to the value
10445 * advertised in PCI.
10446 * Driver should use the minimal value of both as the actual status
10449 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10452 if (igu_sb_cnt == 0) {
10453 BNX2X_ERR("CAM configuration error\n");
10460 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10462 int cfg_size = 0, idx, port = BP_PORT(bp);
10464 /* Aggregation of supported attributes of all external phys */
10465 bp->port.supported[0] = 0;
10466 bp->port.supported[1] = 0;
10467 switch (bp->link_params.num_phys) {
10469 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10473 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10477 if (bp->link_params.multi_phy_config &
10478 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10479 bp->port.supported[1] =
10480 bp->link_params.phy[EXT_PHY1].supported;
10481 bp->port.supported[0] =
10482 bp->link_params.phy[EXT_PHY2].supported;
10484 bp->port.supported[0] =
10485 bp->link_params.phy[EXT_PHY1].supported;
10486 bp->port.supported[1] =
10487 bp->link_params.phy[EXT_PHY2].supported;
10493 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10494 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10496 dev_info.port_hw_config[port].external_phy_config),
10498 dev_info.port_hw_config[port].external_phy_config2));
10502 if (CHIP_IS_E3(bp))
10503 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10505 switch (switch_cfg) {
10506 case SWITCH_CFG_1G:
10507 bp->port.phy_addr = REG_RD(
10508 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10510 case SWITCH_CFG_10G:
10511 bp->port.phy_addr = REG_RD(
10512 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10515 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10516 bp->port.link_config[0]);
10520 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10521 /* mask what we support according to speed_cap_mask per configuration */
10522 for (idx = 0; idx < cfg_size; idx++) {
10523 if (!(bp->link_params.speed_cap_mask[idx] &
10524 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10525 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10527 if (!(bp->link_params.speed_cap_mask[idx] &
10528 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10529 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10531 if (!(bp->link_params.speed_cap_mask[idx] &
10532 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10533 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10535 if (!(bp->link_params.speed_cap_mask[idx] &
10536 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10537 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10539 if (!(bp->link_params.speed_cap_mask[idx] &
10540 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10541 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10542 SUPPORTED_1000baseT_Full);
10544 if (!(bp->link_params.speed_cap_mask[idx] &
10545 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10546 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10548 if (!(bp->link_params.speed_cap_mask[idx] &
10549 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10550 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10552 if (!(bp->link_params.speed_cap_mask[idx] &
10553 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10554 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10557 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10558 bp->port.supported[1]);
10561 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10563 u32 link_config, idx, cfg_size = 0;
10564 bp->port.advertising[0] = 0;
10565 bp->port.advertising[1] = 0;
10566 switch (bp->link_params.num_phys) {
10575 for (idx = 0; idx < cfg_size; idx++) {
10576 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10577 link_config = bp->port.link_config[idx];
10578 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10579 case PORT_FEATURE_LINK_SPEED_AUTO:
10580 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10581 bp->link_params.req_line_speed[idx] =
10583 bp->port.advertising[idx] |=
10584 bp->port.supported[idx];
10585 if (bp->link_params.phy[EXT_PHY1].type ==
10586 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10587 bp->port.advertising[idx] |=
10588 (SUPPORTED_100baseT_Half |
10589 SUPPORTED_100baseT_Full);
10591 /* force 10G, no AN */
10592 bp->link_params.req_line_speed[idx] =
10594 bp->port.advertising[idx] |=
10595 (ADVERTISED_10000baseT_Full |
10601 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10602 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10603 bp->link_params.req_line_speed[idx] =
10605 bp->port.advertising[idx] |=
10606 (ADVERTISED_10baseT_Full |
10609 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10611 bp->link_params.speed_cap_mask[idx]);
10616 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10617 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10618 bp->link_params.req_line_speed[idx] =
10620 bp->link_params.req_duplex[idx] =
10622 bp->port.advertising[idx] |=
10623 (ADVERTISED_10baseT_Half |
10626 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10628 bp->link_params.speed_cap_mask[idx]);
10633 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10634 if (bp->port.supported[idx] &
10635 SUPPORTED_100baseT_Full) {
10636 bp->link_params.req_line_speed[idx] =
10638 bp->port.advertising[idx] |=
10639 (ADVERTISED_100baseT_Full |
10642 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10644 bp->link_params.speed_cap_mask[idx]);
10649 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10650 if (bp->port.supported[idx] &
10651 SUPPORTED_100baseT_Half) {
10652 bp->link_params.req_line_speed[idx] =
10654 bp->link_params.req_duplex[idx] =
10656 bp->port.advertising[idx] |=
10657 (ADVERTISED_100baseT_Half |
10660 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10662 bp->link_params.speed_cap_mask[idx]);
10667 case PORT_FEATURE_LINK_SPEED_1G:
10668 if (bp->port.supported[idx] &
10669 SUPPORTED_1000baseT_Full) {
10670 bp->link_params.req_line_speed[idx] =
10672 bp->port.advertising[idx] |=
10673 (ADVERTISED_1000baseT_Full |
10676 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10678 bp->link_params.speed_cap_mask[idx]);
10683 case PORT_FEATURE_LINK_SPEED_2_5G:
10684 if (bp->port.supported[idx] &
10685 SUPPORTED_2500baseX_Full) {
10686 bp->link_params.req_line_speed[idx] =
10688 bp->port.advertising[idx] |=
10689 (ADVERTISED_2500baseX_Full |
10692 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10694 bp->link_params.speed_cap_mask[idx]);
10699 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10700 if (bp->port.supported[idx] &
10701 SUPPORTED_10000baseT_Full) {
10702 bp->link_params.req_line_speed[idx] =
10704 bp->port.advertising[idx] |=
10705 (ADVERTISED_10000baseT_Full |
10708 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10710 bp->link_params.speed_cap_mask[idx]);
10714 case PORT_FEATURE_LINK_SPEED_20G:
10715 bp->link_params.req_line_speed[idx] = SPEED_20000;
10719 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10721 bp->link_params.req_line_speed[idx] =
10723 bp->port.advertising[idx] =
10724 bp->port.supported[idx];
10728 bp->link_params.req_flow_ctrl[idx] = (link_config &
10729 PORT_FEATURE_FLOW_CONTROL_MASK);
10730 if (bp->link_params.req_flow_ctrl[idx] ==
10731 BNX2X_FLOW_CTRL_AUTO) {
10732 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10733 bp->link_params.req_flow_ctrl[idx] =
10734 BNX2X_FLOW_CTRL_NONE;
10736 bnx2x_set_requested_fc(bp);
10739 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10740 bp->link_params.req_line_speed[idx],
10741 bp->link_params.req_duplex[idx],
10742 bp->link_params.req_flow_ctrl[idx],
10743 bp->port.advertising[idx]);
10747 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10749 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10750 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10751 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10752 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10755 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10757 int port = BP_PORT(bp);
10759 u32 ext_phy_type, ext_phy_config, eee_mode;
10761 bp->link_params.bp = bp;
10762 bp->link_params.port = port;
10764 bp->link_params.lane_config =
10765 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10767 bp->link_params.speed_cap_mask[0] =
10769 dev_info.port_hw_config[port].speed_capability_mask) &
10770 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10771 bp->link_params.speed_cap_mask[1] =
10773 dev_info.port_hw_config[port].speed_capability_mask2) &
10774 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10775 bp->port.link_config[0] =
10776 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10778 bp->port.link_config[1] =
10779 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10781 bp->link_params.multi_phy_config =
10782 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10783 /* If the device is capable of WoL, set the default state according
10786 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10787 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10788 (config & PORT_FEATURE_WOL_ENABLED));
10790 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10791 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10792 bp->flags |= NO_ISCSI_FLAG;
10793 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10794 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10795 bp->flags |= NO_FCOE_FLAG;
10797 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10798 bp->link_params.lane_config,
10799 bp->link_params.speed_cap_mask[0],
10800 bp->port.link_config[0]);
10802 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10803 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10804 bnx2x_phy_probe(&bp->link_params);
10805 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10807 bnx2x_link_settings_requested(bp);
10810 * If connected directly, work with the internal PHY, otherwise, work
10811 * with the external PHY
10815 dev_info.port_hw_config[port].external_phy_config);
10816 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10817 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10818 bp->mdio.prtad = bp->port.phy_addr;
10820 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10821 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10823 XGXS_EXT_PHY_ADDR(ext_phy_config);
10825 /* Configure link feature according to nvram value */
10826 eee_mode = (((SHMEM_RD(bp, dev_info.
10827 port_feature_config[port].eee_power_mode)) &
10828 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10829 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10830 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10831 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10832 EEE_MODE_ENABLE_LPI |
10833 EEE_MODE_OUTPUT_TIME;
10835 bp->link_params.eee_mode = 0;
10839 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10841 u32 no_flags = NO_ISCSI_FLAG;
10842 int port = BP_PORT(bp);
10843 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10844 drv_lic_key[port].max_iscsi_conn);
10846 if (!CNIC_SUPPORT(bp)) {
10847 bp->flags |= no_flags;
10851 /* Get the number of maximum allowed iSCSI connections */
10852 bp->cnic_eth_dev.max_iscsi_conn =
10853 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10854 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10856 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10857 bp->cnic_eth_dev.max_iscsi_conn);
10860 * If maximum allowed number of connections is zero -
10861 * disable the feature.
10863 if (!bp->cnic_eth_dev.max_iscsi_conn)
10864 bp->flags |= no_flags;
10867 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10870 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10871 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10872 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10873 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10876 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10877 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10878 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10879 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10882 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10889 /* iterate over absolute function ids for this path: */
10890 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10891 if (IS_MF_SD(bp)) {
10892 u32 cfg = MF_CFG_RD(bp,
10893 func_mf_config[fid].config);
10895 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10896 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10897 FUNC_MF_CFG_PROTOCOL_FCOE))
10900 u32 cfg = MF_CFG_RD(bp,
10901 func_ext_config[fid].
10904 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10905 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10910 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10912 for (port = 0; port < port_cnt; port++) {
10913 u32 lic = SHMEM_RD(bp,
10914 drv_lic_key[port].max_fcoe_conn) ^
10915 FW_ENCODE_32BIT_PATTERN;
10924 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10926 int port = BP_PORT(bp);
10927 int func = BP_ABS_FUNC(bp);
10928 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10929 drv_lic_key[port].max_fcoe_conn);
10930 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10932 if (!CNIC_SUPPORT(bp)) {
10933 bp->flags |= NO_FCOE_FLAG;
10937 /* Get the number of maximum allowed FCoE connections */
10938 bp->cnic_eth_dev.max_fcoe_conn =
10939 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10940 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10942 /* Calculate the number of maximum allowed FCoE tasks */
10943 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
10945 /* check if FCoE resources must be shared between different functions */
10947 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
10949 /* Read the WWN: */
10952 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10954 dev_info.port_hw_config[port].
10955 fcoe_wwn_port_name_upper);
10956 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10958 dev_info.port_hw_config[port].
10959 fcoe_wwn_port_name_lower);
10962 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10964 dev_info.port_hw_config[port].
10965 fcoe_wwn_node_name_upper);
10966 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10968 dev_info.port_hw_config[port].
10969 fcoe_wwn_node_name_lower);
10970 } else if (!IS_MF_SD(bp)) {
10972 * Read the WWN info only if the FCoE feature is enabled for
10975 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10976 bnx2x_get_ext_wwn_info(bp, func);
10978 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10979 bnx2x_get_ext_wwn_info(bp, func);
10982 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10985 * If maximum allowed number of connections is zero -
10986 * disable the feature.
10988 if (!bp->cnic_eth_dev.max_fcoe_conn)
10989 bp->flags |= NO_FCOE_FLAG;
10992 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10995 * iSCSI may be dynamically disabled but reading
10996 * info here we will decrease memory usage by driver
10997 * if the feature is disabled for good
10999 bnx2x_get_iscsi_info(bp);
11000 bnx2x_get_fcoe_info(bp);
11003 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11006 int func = BP_ABS_FUNC(bp);
11007 int port = BP_PORT(bp);
11008 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11009 u8 *fip_mac = bp->fip_mac;
11012 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11013 * FCoE MAC then the appropriate feature should be disabled.
11014 * In non SD mode features configuration comes from struct
11017 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11018 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11019 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11020 val2 = MF_CFG_RD(bp, func_ext_config[func].
11021 iscsi_mac_addr_upper);
11022 val = MF_CFG_RD(bp, func_ext_config[func].
11023 iscsi_mac_addr_lower);
11024 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11026 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11028 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11031 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11032 val2 = MF_CFG_RD(bp, func_ext_config[func].
11033 fcoe_mac_addr_upper);
11034 val = MF_CFG_RD(bp, func_ext_config[func].
11035 fcoe_mac_addr_lower);
11036 bnx2x_set_mac_buf(fip_mac, val, val2);
11038 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11040 bp->flags |= NO_FCOE_FLAG;
11043 bp->mf_ext_config = cfg;
11045 } else { /* SD MODE */
11046 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11047 /* use primary mac as iscsi mac */
11048 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11050 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11052 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11053 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11054 /* use primary mac as fip mac */
11055 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11056 BNX2X_DEV_INFO("SD FCoE MODE\n");
11058 ("Read FIP MAC: %pM\n", fip_mac);
11062 /* If this is a storage-only interface, use SAN mac as
11063 * primary MAC. Notice that for SD this is already the case,
11064 * as the SAN mac was copied from the primary MAC.
11066 if (IS_MF_FCOE_AFEX(bp))
11067 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11069 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11071 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11073 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11075 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11076 fcoe_fip_mac_upper);
11077 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11078 fcoe_fip_mac_lower);
11079 bnx2x_set_mac_buf(fip_mac, val, val2);
11082 /* Disable iSCSI OOO if MAC configuration is invalid. */
11083 if (!is_valid_ether_addr(iscsi_mac)) {
11084 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11085 memset(iscsi_mac, 0, ETH_ALEN);
11088 /* Disable FCoE if MAC configuration is invalid. */
11089 if (!is_valid_ether_addr(fip_mac)) {
11090 bp->flags |= NO_FCOE_FLAG;
11091 memset(bp->fip_mac, 0, ETH_ALEN);
11095 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11098 int func = BP_ABS_FUNC(bp);
11099 int port = BP_PORT(bp);
11101 /* Zero primary MAC configuration */
11102 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11104 if (BP_NOMCP(bp)) {
11105 BNX2X_ERROR("warning: random MAC workaround active\n");
11106 eth_hw_addr_random(bp->dev);
11107 } else if (IS_MF(bp)) {
11108 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11109 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11110 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11111 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11112 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11114 if (CNIC_SUPPORT(bp))
11115 bnx2x_get_cnic_mac_hwinfo(bp);
11117 /* in SF read MACs from port configuration */
11118 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11119 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11120 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11122 if (CNIC_SUPPORT(bp))
11123 bnx2x_get_cnic_mac_hwinfo(bp);
11126 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11128 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11129 dev_err(&bp->pdev->dev,
11130 "bad Ethernet MAC address configuration: %pM\n"
11131 "change it manually before bringing up the appropriate network interface\n",
11132 bp->dev->dev_addr);
11135 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11140 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11141 /* Take function: tmp = func */
11142 tmp = BP_ABS_FUNC(bp);
11143 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11144 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11146 /* Take port: tmp = port */
11149 dev_info.port_hw_config[tmp].generic_features);
11150 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11155 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11157 int /*abs*/func = BP_ABS_FUNC(bp);
11162 bnx2x_get_common_hwinfo(bp);
11165 * initialize IGU parameters
11167 if (CHIP_IS_E1x(bp)) {
11168 bp->common.int_block = INT_BLOCK_HC;
11170 bp->igu_dsb_id = DEF_SB_IGU_ID;
11171 bp->igu_base_sb = 0;
11173 bp->common.int_block = INT_BLOCK_IGU;
11175 /* do not allow device reset during IGU info processing */
11176 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11178 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11180 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11183 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11185 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11186 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11187 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11189 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11191 usleep_range(1000, 2000);
11194 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11195 dev_err(&bp->pdev->dev,
11196 "FORCING Normal Mode failed!!!\n");
11197 bnx2x_release_hw_lock(bp,
11198 HW_LOCK_RESOURCE_RESET);
11203 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11204 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11205 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11207 BNX2X_DEV_INFO("IGU Normal Mode\n");
11209 rc = bnx2x_get_igu_cam_info(bp);
11210 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11216 * set base FW non-default (fast path) status block id, this value is
11217 * used to initialize the fw_sb_id saved on the fp/queue structure to
11218 * determine the id used by the FW.
11220 if (CHIP_IS_E1x(bp))
11221 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11223 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11224 * the same queue are indicated on the same IGU SB). So we prefer
11225 * FW and IGU SBs to be the same value.
11227 bp->base_fw_ndsb = bp->igu_base_sb;
11229 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11230 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11231 bp->igu_sb_cnt, bp->base_fw_ndsb);
11234 * Initialize MF configuration
11241 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11242 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11243 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11244 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11246 if (SHMEM2_HAS(bp, mf_cfg_addr))
11247 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11249 bp->common.mf_cfg_base = bp->common.shmem_base +
11250 offsetof(struct shmem_region, func_mb) +
11251 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11253 * get mf configuration:
11254 * 1. Existence of MF configuration
11255 * 2. MAC address must be legal (check only upper bytes)
11256 * for Switch-Independent mode;
11257 * OVLAN must be legal for Switch-Dependent mode
11258 * 3. SF_MODE configures specific MF mode
11260 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11261 /* get mf configuration */
11263 dev_info.shared_feature_config.config);
11264 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11267 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11268 val = MF_CFG_RD(bp, func_mf_config[func].
11270 /* check for legal mac (upper bytes)*/
11271 if (val != 0xffff) {
11272 bp->mf_mode = MULTI_FUNCTION_SI;
11273 bp->mf_config[vn] = MF_CFG_RD(bp,
11274 func_mf_config[func].config);
11276 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11278 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11279 if ((!CHIP_IS_E1x(bp)) &&
11280 (MF_CFG_RD(bp, func_mf_config[func].
11281 mac_upper) != 0xffff) &&
11283 afex_driver_support))) {
11284 bp->mf_mode = MULTI_FUNCTION_AFEX;
11285 bp->mf_config[vn] = MF_CFG_RD(bp,
11286 func_mf_config[func].config);
11288 BNX2X_DEV_INFO("can not configure afex mode\n");
11291 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11292 /* get OV configuration */
11293 val = MF_CFG_RD(bp,
11294 func_mf_config[FUNC_0].e1hov_tag);
11295 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11297 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11298 bp->mf_mode = MULTI_FUNCTION_SD;
11299 bp->mf_config[vn] = MF_CFG_RD(bp,
11300 func_mf_config[func].config);
11302 BNX2X_DEV_INFO("illegal OV for SD\n");
11304 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11305 bp->mf_config[vn] = 0;
11308 /* Unknown configuration: reset mf_config */
11309 bp->mf_config[vn] = 0;
11310 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11314 BNX2X_DEV_INFO("%s function mode\n",
11315 IS_MF(bp) ? "multi" : "single");
11317 switch (bp->mf_mode) {
11318 case MULTI_FUNCTION_SD:
11319 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11320 FUNC_MF_CFG_E1HOV_TAG_MASK;
11321 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11323 bp->path_has_ovlan = true;
11325 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11326 func, bp->mf_ov, bp->mf_ov);
11328 dev_err(&bp->pdev->dev,
11329 "No valid MF OV for func %d, aborting\n",
11334 case MULTI_FUNCTION_AFEX:
11335 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11337 case MULTI_FUNCTION_SI:
11338 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11343 dev_err(&bp->pdev->dev,
11344 "VN %d is in a single function mode, aborting\n",
11351 /* check if other port on the path needs ovlan:
11352 * Since MF configuration is shared between ports
11353 * Possible mixed modes are only
11354 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11356 if (CHIP_MODE_IS_4_PORT(bp) &&
11357 !bp->path_has_ovlan &&
11359 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11360 u8 other_port = !BP_PORT(bp);
11361 u8 other_func = BP_PATH(bp) + 2*other_port;
11362 val = MF_CFG_RD(bp,
11363 func_mf_config[other_func].e1hov_tag);
11364 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11365 bp->path_has_ovlan = true;
11369 /* adjust igu_sb_cnt to MF for E1x */
11370 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11371 bp->igu_sb_cnt /= E1HVN_MAX;
11374 bnx2x_get_port_hwinfo(bp);
11376 /* Get MAC addresses */
11377 bnx2x_get_mac_hwinfo(bp);
11379 bnx2x_get_cnic_info(bp);
11384 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11386 int cnt, i, block_end, rodi;
11387 char vpd_start[BNX2X_VPD_LEN+1];
11388 char str_id_reg[VENDOR_ID_LEN+1];
11389 char str_id_cap[VENDOR_ID_LEN+1];
11391 char *vpd_extended_data = NULL;
11394 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11395 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11397 if (cnt < BNX2X_VPD_LEN)
11398 goto out_not_found;
11400 /* VPD RO tag should be first tag after identifier string, hence
11401 * we should be able to find it in first BNX2X_VPD_LEN chars
11403 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11404 PCI_VPD_LRDT_RO_DATA);
11406 goto out_not_found;
11408 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11409 pci_vpd_lrdt_size(&vpd_start[i]);
11411 i += PCI_VPD_LRDT_TAG_SIZE;
11413 if (block_end > BNX2X_VPD_LEN) {
11414 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11415 if (vpd_extended_data == NULL)
11416 goto out_not_found;
11418 /* read rest of vpd image into vpd_extended_data */
11419 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11420 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11421 block_end - BNX2X_VPD_LEN,
11422 vpd_extended_data + BNX2X_VPD_LEN);
11423 if (cnt < (block_end - BNX2X_VPD_LEN))
11424 goto out_not_found;
11425 vpd_data = vpd_extended_data;
11427 vpd_data = vpd_start;
11429 /* now vpd_data holds full vpd content in both cases */
11431 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11432 PCI_VPD_RO_KEYWORD_MFR_ID);
11434 goto out_not_found;
11436 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11438 if (len != VENDOR_ID_LEN)
11439 goto out_not_found;
11441 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11443 /* vendor specific info */
11444 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11445 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11446 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11447 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11449 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11450 PCI_VPD_RO_KEYWORD_VENDOR0);
11452 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11454 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11456 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11457 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11458 bp->fw_ver[len] = ' ';
11461 kfree(vpd_extended_data);
11465 kfree(vpd_extended_data);
11469 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11473 if (CHIP_REV_IS_FPGA(bp))
11474 SET_FLAGS(flags, MODE_FPGA);
11475 else if (CHIP_REV_IS_EMUL(bp))
11476 SET_FLAGS(flags, MODE_EMUL);
11478 SET_FLAGS(flags, MODE_ASIC);
11480 if (CHIP_MODE_IS_4_PORT(bp))
11481 SET_FLAGS(flags, MODE_PORT4);
11483 SET_FLAGS(flags, MODE_PORT2);
11485 if (CHIP_IS_E2(bp))
11486 SET_FLAGS(flags, MODE_E2);
11487 else if (CHIP_IS_E3(bp)) {
11488 SET_FLAGS(flags, MODE_E3);
11489 if (CHIP_REV(bp) == CHIP_REV_Ax)
11490 SET_FLAGS(flags, MODE_E3_A0);
11491 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11492 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11496 SET_FLAGS(flags, MODE_MF);
11497 switch (bp->mf_mode) {
11498 case MULTI_FUNCTION_SD:
11499 SET_FLAGS(flags, MODE_MF_SD);
11501 case MULTI_FUNCTION_SI:
11502 SET_FLAGS(flags, MODE_MF_SI);
11504 case MULTI_FUNCTION_AFEX:
11505 SET_FLAGS(flags, MODE_MF_AFEX);
11509 SET_FLAGS(flags, MODE_SF);
11511 #if defined(__LITTLE_ENDIAN)
11512 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11513 #else /*(__BIG_ENDIAN)*/
11514 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11516 INIT_MODE_FLAGS(bp) = flags;
11519 static int bnx2x_init_bp(struct bnx2x *bp)
11524 mutex_init(&bp->port.phy_mutex);
11525 mutex_init(&bp->fw_mb_mutex);
11526 spin_lock_init(&bp->stats_lock);
11528 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11529 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11530 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11532 rc = bnx2x_get_hwinfo(bp);
11536 eth_zero_addr(bp->dev->dev_addr);
11539 bnx2x_set_modes_bitmap(bp);
11541 rc = bnx2x_alloc_mem_bp(bp);
11545 bnx2x_read_fwinfo(bp);
11547 func = BP_FUNC(bp);
11549 /* need to reset chip if undi was active */
11550 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11553 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11554 DRV_MSG_SEQ_NUMBER_MASK;
11555 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11557 bnx2x_prev_unload(bp);
11560 if (CHIP_REV_IS_FPGA(bp))
11561 dev_err(&bp->pdev->dev, "FPGA detected\n");
11563 if (BP_NOMCP(bp) && (func == 0))
11564 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11566 bp->disable_tpa = disable_tpa;
11567 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11569 /* Set TPA flags */
11570 if (bp->disable_tpa) {
11571 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11572 bp->dev->features &= ~NETIF_F_LRO;
11574 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11575 bp->dev->features |= NETIF_F_LRO;
11578 if (CHIP_IS_E1(bp))
11579 bp->dropless_fc = 0;
11581 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11585 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11587 bp->rx_ring_size = MAX_RX_AVAIL;
11589 /* make sure that the numbers are in the right granularity */
11590 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11591 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11593 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11595 init_timer(&bp->timer);
11596 bp->timer.expires = jiffies + bp->current_interval;
11597 bp->timer.data = (unsigned long) bp;
11598 bp->timer.function = bnx2x_timer;
11600 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11601 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11602 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11603 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11604 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11605 bnx2x_dcbx_init_params(bp);
11607 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11610 if (CHIP_IS_E1x(bp))
11611 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11613 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11615 /* multiple tx priority */
11618 else if (CHIP_IS_E1x(bp))
11619 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11620 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11621 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11622 else if (CHIP_IS_E3B0(bp))
11623 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11625 BNX2X_ERR("unknown chip %x revision %x\n",
11626 CHIP_NUM(bp), CHIP_REV(bp));
11627 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11629 /* We need at least one default status block for slow-path events,
11630 * second status block for the L2 queue, and a third status block for
11631 * CNIC if supported.
11633 if (CNIC_SUPPORT(bp))
11634 bp->min_msix_vec_cnt = 3;
11636 bp->min_msix_vec_cnt = 2;
11637 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11639 bp->dump_preset_idx = 1;
11644 /****************************************************************************
11645 * General service functions
11646 ****************************************************************************/
11649 * net_device service functions
11652 /* called with rtnl_lock */
11653 static int bnx2x_open(struct net_device *dev)
11655 struct bnx2x *bp = netdev_priv(dev);
11656 bool global = false;
11657 int other_engine = BP_PATH(bp) ? 0 : 1;
11658 bool other_load_status, load_status;
11661 bp->stats_init = true;
11663 netif_carrier_off(dev);
11665 bnx2x_set_power_state(bp, PCI_D0);
11667 /* If parity had happen during the unload, then attentions
11668 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11669 * want the first function loaded on the current engine to
11670 * complete the recovery.
11671 * Parity recovery is only relevant for PF driver.
11674 other_load_status = bnx2x_get_load_status(bp, other_engine);
11675 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11676 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11677 bnx2x_chk_parity_attn(bp, &global, true)) {
11679 /* If there are attentions and they are in a
11680 * global blocks, set the GLOBAL_RESET bit
11681 * regardless whether it will be this function
11682 * that will complete the recovery or not.
11685 bnx2x_set_reset_global(bp);
11687 /* Only the first function on the current
11688 * engine should try to recover in open. In case
11689 * of attentions in global blocks only the first
11690 * in the chip should try to recover.
11692 if ((!load_status &&
11693 (!global || !other_load_status)) &&
11694 bnx2x_trylock_leader_lock(bp) &&
11695 !bnx2x_leader_reset(bp)) {
11696 netdev_info(bp->dev,
11697 "Recovered in open\n");
11701 /* recovery has failed... */
11702 bnx2x_set_power_state(bp, PCI_D3hot);
11703 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11705 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11706 "If you still see this message after a few retries then power cycle is required.\n");
11713 bp->recovery_state = BNX2X_RECOVERY_DONE;
11714 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11717 return bnx2x_open_epilog(bp);
11720 /* called with rtnl_lock */
11721 static int bnx2x_close(struct net_device *dev)
11723 struct bnx2x *bp = netdev_priv(dev);
11725 /* Unload the driver, release IRQs */
11726 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11731 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11732 struct bnx2x_mcast_ramrod_params *p)
11734 int mc_count = netdev_mc_count(bp->dev);
11735 struct bnx2x_mcast_list_elem *mc_mac =
11736 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11737 struct netdev_hw_addr *ha;
11742 INIT_LIST_HEAD(&p->mcast_list);
11744 netdev_for_each_mc_addr(ha, bp->dev) {
11745 mc_mac->mac = bnx2x_mc_addr(ha);
11746 list_add_tail(&mc_mac->link, &p->mcast_list);
11750 p->mcast_list_len = mc_count;
11755 static void bnx2x_free_mcast_macs_list(
11756 struct bnx2x_mcast_ramrod_params *p)
11758 struct bnx2x_mcast_list_elem *mc_mac =
11759 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11767 * bnx2x_set_uc_list - configure a new unicast MACs list.
11769 * @bp: driver handle
11771 * We will use zero (0) as a MAC type for these MACs.
11773 static int bnx2x_set_uc_list(struct bnx2x *bp)
11776 struct net_device *dev = bp->dev;
11777 struct netdev_hw_addr *ha;
11778 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11779 unsigned long ramrod_flags = 0;
11781 /* First schedule a cleanup up of old configuration */
11782 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11784 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11788 netdev_for_each_uc_addr(ha, dev) {
11789 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11790 BNX2X_UC_LIST_MAC, &ramrod_flags);
11791 if (rc == -EEXIST) {
11793 "Failed to schedule ADD operations: %d\n", rc);
11794 /* do not treat adding same MAC as error */
11797 } else if (rc < 0) {
11799 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11805 /* Execute the pending commands */
11806 __set_bit(RAMROD_CONT, &ramrod_flags);
11807 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11808 BNX2X_UC_LIST_MAC, &ramrod_flags);
11811 static int bnx2x_set_mc_list(struct bnx2x *bp)
11813 struct net_device *dev = bp->dev;
11814 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11817 rparam.mcast_obj = &bp->mcast_obj;
11819 /* first, clear all configured multicast MACs */
11820 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11822 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11826 /* then, configure a new MACs list */
11827 if (netdev_mc_count(dev)) {
11828 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11830 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11835 /* Now add the new MACs */
11836 rc = bnx2x_config_mcast(bp, &rparam,
11837 BNX2X_MCAST_CMD_ADD);
11839 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11842 bnx2x_free_mcast_macs_list(&rparam);
11848 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11849 void bnx2x_set_rx_mode(struct net_device *dev)
11851 struct bnx2x *bp = netdev_priv(dev);
11852 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11854 if (bp->state != BNX2X_STATE_OPEN) {
11855 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11859 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11861 if (dev->flags & IFF_PROMISC)
11862 rx_mode = BNX2X_RX_MODE_PROMISC;
11863 else if ((dev->flags & IFF_ALLMULTI) ||
11864 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11866 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11869 /* some multicasts */
11870 if (bnx2x_set_mc_list(bp) < 0)
11871 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11873 if (bnx2x_set_uc_list(bp) < 0)
11874 rx_mode = BNX2X_RX_MODE_PROMISC;
11876 /* configuring mcast to a vf involves sleeping (when we
11877 * wait for the pf's response). Since this function is
11878 * called from non sleepable context we must schedule
11879 * a work item for this purpose
11881 smp_mb__before_clear_bit();
11882 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11883 &bp->sp_rtnl_state);
11884 smp_mb__after_clear_bit();
11885 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11889 bp->rx_mode = rx_mode;
11890 /* handle ISCSI SD mode */
11891 if (IS_MF_ISCSI_SD(bp))
11892 bp->rx_mode = BNX2X_RX_MODE_NONE;
11894 /* Schedule the rx_mode command */
11895 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11896 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11901 bnx2x_set_storm_rx_mode(bp);
11903 /* configuring rx mode to storms in a vf involves sleeping (when
11904 * we wait for the pf's response). Since this function is
11905 * called from non sleepable context we must schedule
11906 * a work item for this purpose
11908 smp_mb__before_clear_bit();
11909 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11910 &bp->sp_rtnl_state);
11911 smp_mb__after_clear_bit();
11912 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11916 /* called with rtnl_lock */
11917 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11918 int devad, u16 addr)
11920 struct bnx2x *bp = netdev_priv(netdev);
11924 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11925 prtad, devad, addr);
11927 /* The HW expects different devad if CL22 is used */
11928 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11930 bnx2x_acquire_phy_lock(bp);
11931 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11932 bnx2x_release_phy_lock(bp);
11933 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11940 /* called with rtnl_lock */
11941 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11942 u16 addr, u16 value)
11944 struct bnx2x *bp = netdev_priv(netdev);
11948 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11949 prtad, devad, addr, value);
11951 /* The HW expects different devad if CL22 is used */
11952 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11954 bnx2x_acquire_phy_lock(bp);
11955 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11956 bnx2x_release_phy_lock(bp);
11960 /* called with rtnl_lock */
11961 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11963 struct bnx2x *bp = netdev_priv(dev);
11964 struct mii_ioctl_data *mdio = if_mii(ifr);
11966 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11967 mdio->phy_id, mdio->reg_num, mdio->val_in);
11969 if (!netif_running(dev))
11972 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11975 #ifdef CONFIG_NET_POLL_CONTROLLER
11976 static void poll_bnx2x(struct net_device *dev)
11978 struct bnx2x *bp = netdev_priv(dev);
11981 for_each_eth_queue(bp, i) {
11982 struct bnx2x_fastpath *fp = &bp->fp[i];
11983 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11988 static int bnx2x_validate_addr(struct net_device *dev)
11990 struct bnx2x *bp = netdev_priv(dev);
11992 /* query the bulletin board for mac address configured by the PF */
11994 bnx2x_sample_bulletin(bp);
11996 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11997 BNX2X_ERR("Non-valid Ethernet address\n");
11998 return -EADDRNOTAVAIL;
12003 static const struct net_device_ops bnx2x_netdev_ops = {
12004 .ndo_open = bnx2x_open,
12005 .ndo_stop = bnx2x_close,
12006 .ndo_start_xmit = bnx2x_start_xmit,
12007 .ndo_select_queue = bnx2x_select_queue,
12008 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12009 .ndo_set_mac_address = bnx2x_change_mac_addr,
12010 .ndo_validate_addr = bnx2x_validate_addr,
12011 .ndo_do_ioctl = bnx2x_ioctl,
12012 .ndo_change_mtu = bnx2x_change_mtu,
12013 .ndo_fix_features = bnx2x_fix_features,
12014 .ndo_set_features = bnx2x_set_features,
12015 .ndo_tx_timeout = bnx2x_tx_timeout,
12016 #ifdef CONFIG_NET_POLL_CONTROLLER
12017 .ndo_poll_controller = poll_bnx2x,
12019 .ndo_setup_tc = bnx2x_setup_tc,
12020 #ifdef CONFIG_BNX2X_SRIOV
12021 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12022 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12023 .ndo_get_vf_config = bnx2x_get_vf_config,
12025 #ifdef NETDEV_FCOE_WWNN
12026 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12029 #ifdef CONFIG_NET_RX_BUSY_POLL
12030 .ndo_busy_poll = bnx2x_low_latency_recv,
12034 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12036 struct device *dev = &bp->pdev->dev;
12038 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12039 bp->flags |= USING_DAC_FLAG;
12040 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12041 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12044 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12045 dev_err(dev, "System does not support DMA, aborting\n");
12052 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12053 struct net_device *dev, unsigned long board_type)
12057 bool chip_is_e1x = (board_type == BCM57710 ||
12058 board_type == BCM57711 ||
12059 board_type == BCM57711E);
12061 SET_NETDEV_DEV(dev, &pdev->dev);
12066 rc = pci_enable_device(pdev);
12068 dev_err(&bp->pdev->dev,
12069 "Cannot enable PCI device, aborting\n");
12073 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12074 dev_err(&bp->pdev->dev,
12075 "Cannot find PCI device base address, aborting\n");
12077 goto err_out_disable;
12080 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12081 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12083 goto err_out_disable;
12086 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12087 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12088 PCICFG_REVESION_ID_ERROR_VAL) {
12089 pr_err("PCI device error, probably due to fan failure, aborting\n");
12091 goto err_out_disable;
12094 if (atomic_read(&pdev->enable_cnt) == 1) {
12095 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12097 dev_err(&bp->pdev->dev,
12098 "Cannot obtain PCI resources, aborting\n");
12099 goto err_out_disable;
12102 pci_set_master(pdev);
12103 pci_save_state(pdev);
12107 bp->pm_cap = pdev->pm_cap;
12108 if (bp->pm_cap == 0) {
12109 dev_err(&bp->pdev->dev,
12110 "Cannot find power management capability, aborting\n");
12112 goto err_out_release;
12116 if (!pci_is_pcie(pdev)) {
12117 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12119 goto err_out_release;
12122 rc = bnx2x_set_coherency_mask(bp);
12124 goto err_out_release;
12126 dev->mem_start = pci_resource_start(pdev, 0);
12127 dev->base_addr = dev->mem_start;
12128 dev->mem_end = pci_resource_end(pdev, 0);
12130 dev->irq = pdev->irq;
12132 bp->regview = pci_ioremap_bar(pdev, 0);
12133 if (!bp->regview) {
12134 dev_err(&bp->pdev->dev,
12135 "Cannot map register space, aborting\n");
12137 goto err_out_release;
12140 /* In E1/E1H use pci device function given by kernel.
12141 * In E2/E3 read physical function from ME register since these chips
12142 * support Physical Device Assignment where kernel BDF maybe arbitrary
12143 * (depending on hypervisor).
12146 bp->pf_num = PCI_FUNC(pdev->devfn);
12149 pci_read_config_dword(bp->pdev,
12150 PCICFG_ME_REGISTER, &pci_cfg_dword);
12151 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12152 ME_REG_ABS_PF_NUM_SHIFT);
12154 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12156 /* clean indirect addresses */
12157 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12158 PCICFG_VENDOR_ID_OFFSET);
12160 * Clean the following indirect addresses for all functions since it
12161 * is not used by the driver.
12164 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12165 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12166 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12167 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12170 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12171 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12172 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12173 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12176 /* Enable internal target-read (in case we are probed after PF
12177 * FLR). Must be done prior to any BAR read access. Only for
12182 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12185 dev->watchdog_timeo = TX_TIMEOUT;
12187 dev->netdev_ops = &bnx2x_netdev_ops;
12188 bnx2x_set_ethtool_ops(bp, dev);
12190 dev->priv_flags |= IFF_UNICAST_FLT;
12192 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12193 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12194 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12195 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12196 if (!CHIP_IS_E1x(bp)) {
12197 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12198 dev->hw_enc_features =
12199 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12200 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12201 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12204 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12205 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12207 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12208 if (bp->flags & USING_DAC_FLAG)
12209 dev->features |= NETIF_F_HIGHDMA;
12211 /* Add Loopback capability to the device */
12212 dev->hw_features |= NETIF_F_LOOPBACK;
12215 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12218 /* get_port_hwinfo() will set prtad and mmds properly */
12219 bp->mdio.prtad = MDIO_PRTAD_NONE;
12221 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12222 bp->mdio.dev = dev;
12223 bp->mdio.mdio_read = bnx2x_mdio_read;
12224 bp->mdio.mdio_write = bnx2x_mdio_write;
12229 if (atomic_read(&pdev->enable_cnt) == 1)
12230 pci_release_regions(pdev);
12233 pci_disable_device(pdev);
12234 pci_set_drvdata(pdev, NULL);
12240 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12241 enum bnx2x_pci_bus_speed *speed)
12243 u32 link_speed, val = 0;
12245 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12246 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12248 link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12250 switch (link_speed) {
12252 *speed = BNX2X_PCI_LINK_SPEED_8000;
12255 *speed = BNX2X_PCI_LINK_SPEED_5000;
12258 *speed = BNX2X_PCI_LINK_SPEED_2500;
12262 static int bnx2x_check_firmware(struct bnx2x *bp)
12264 const struct firmware *firmware = bp->firmware;
12265 struct bnx2x_fw_file_hdr *fw_hdr;
12266 struct bnx2x_fw_file_section *sections;
12267 u32 offset, len, num_ops;
12268 __be16 *ops_offsets;
12272 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12273 BNX2X_ERR("Wrong FW size\n");
12277 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12278 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12280 /* Make sure none of the offsets and sizes make us read beyond
12281 * the end of the firmware data */
12282 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12283 offset = be32_to_cpu(sections[i].offset);
12284 len = be32_to_cpu(sections[i].len);
12285 if (offset + len > firmware->size) {
12286 BNX2X_ERR("Section %d length is out of bounds\n", i);
12291 /* Likewise for the init_ops offsets */
12292 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12293 ops_offsets = (__force __be16 *)(firmware->data + offset);
12294 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12296 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12297 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12298 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12303 /* Check FW version */
12304 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12305 fw_ver = firmware->data + offset;
12306 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12307 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12308 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12309 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12310 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12311 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12312 BCM_5710_FW_MAJOR_VERSION,
12313 BCM_5710_FW_MINOR_VERSION,
12314 BCM_5710_FW_REVISION_VERSION,
12315 BCM_5710_FW_ENGINEERING_VERSION);
12322 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12324 const __be32 *source = (const __be32 *)_source;
12325 u32 *target = (u32 *)_target;
12328 for (i = 0; i < n/4; i++)
12329 target[i] = be32_to_cpu(source[i]);
12333 Ops array is stored in the following format:
12334 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12336 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12338 const __be32 *source = (const __be32 *)_source;
12339 struct raw_op *target = (struct raw_op *)_target;
12342 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12343 tmp = be32_to_cpu(source[j]);
12344 target[i].op = (tmp >> 24) & 0xff;
12345 target[i].offset = tmp & 0xffffff;
12346 target[i].raw_data = be32_to_cpu(source[j + 1]);
12350 /* IRO array is stored in the following format:
12351 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12353 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12355 const __be32 *source = (const __be32 *)_source;
12356 struct iro *target = (struct iro *)_target;
12359 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12360 target[i].base = be32_to_cpu(source[j]);
12362 tmp = be32_to_cpu(source[j]);
12363 target[i].m1 = (tmp >> 16) & 0xffff;
12364 target[i].m2 = tmp & 0xffff;
12366 tmp = be32_to_cpu(source[j]);
12367 target[i].m3 = (tmp >> 16) & 0xffff;
12368 target[i].size = tmp & 0xffff;
12373 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12375 const __be16 *source = (const __be16 *)_source;
12376 u16 *target = (u16 *)_target;
12379 for (i = 0; i < n/2; i++)
12380 target[i] = be16_to_cpu(source[i]);
12383 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12385 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12386 bp->arr = kmalloc(len, GFP_KERNEL); \
12389 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12390 (u8 *)bp->arr, len); \
12393 static int bnx2x_init_firmware(struct bnx2x *bp)
12395 const char *fw_file_name;
12396 struct bnx2x_fw_file_hdr *fw_hdr;
12402 if (CHIP_IS_E1(bp))
12403 fw_file_name = FW_FILE_NAME_E1;
12404 else if (CHIP_IS_E1H(bp))
12405 fw_file_name = FW_FILE_NAME_E1H;
12406 else if (!CHIP_IS_E1x(bp))
12407 fw_file_name = FW_FILE_NAME_E2;
12409 BNX2X_ERR("Unsupported chip revision\n");
12412 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12414 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12416 BNX2X_ERR("Can't load firmware file %s\n",
12418 goto request_firmware_exit;
12421 rc = bnx2x_check_firmware(bp);
12423 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12424 goto request_firmware_exit;
12427 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12429 /* Initialize the pointers to the init arrays */
12431 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12434 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12437 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12440 /* STORMs firmware */
12441 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12442 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12443 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12444 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12445 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12446 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12447 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12448 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12449 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12450 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12451 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12452 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12453 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12454 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12455 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12456 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12458 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12463 kfree(bp->init_ops_offsets);
12464 init_offsets_alloc_err:
12465 kfree(bp->init_ops);
12466 init_ops_alloc_err:
12467 kfree(bp->init_data);
12468 request_firmware_exit:
12469 release_firmware(bp->firmware);
12470 bp->firmware = NULL;
12475 static void bnx2x_release_firmware(struct bnx2x *bp)
12477 kfree(bp->init_ops_offsets);
12478 kfree(bp->init_ops);
12479 kfree(bp->init_data);
12480 release_firmware(bp->firmware);
12481 bp->firmware = NULL;
12484 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12485 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12486 .init_hw_cmn = bnx2x_init_hw_common,
12487 .init_hw_port = bnx2x_init_hw_port,
12488 .init_hw_func = bnx2x_init_hw_func,
12490 .reset_hw_cmn = bnx2x_reset_common,
12491 .reset_hw_port = bnx2x_reset_port,
12492 .reset_hw_func = bnx2x_reset_func,
12494 .gunzip_init = bnx2x_gunzip_init,
12495 .gunzip_end = bnx2x_gunzip_end,
12497 .init_fw = bnx2x_init_firmware,
12498 .release_fw = bnx2x_release_firmware,
12501 void bnx2x__init_func_obj(struct bnx2x *bp)
12503 /* Prepare DMAE related driver resources */
12504 bnx2x_setup_dmae(bp);
12506 bnx2x_init_func_obj(bp, &bp->func_obj,
12507 bnx2x_sp(bp, func_rdata),
12508 bnx2x_sp_mapping(bp, func_rdata),
12509 bnx2x_sp(bp, func_afex_rdata),
12510 bnx2x_sp_mapping(bp, func_afex_rdata),
12511 &bnx2x_func_sp_drv);
12514 /* must be called after sriov-enable */
12515 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12517 int cid_count = BNX2X_L2_MAX_CID(bp);
12520 cid_count += BNX2X_VF_CIDS;
12522 if (CNIC_SUPPORT(bp))
12523 cid_count += CNIC_CID_MAX;
12525 return roundup(cid_count, QM_CID_ROUND);
12529 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12534 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12535 int cnic_cnt, bool is_vf)
12540 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12543 * If MSI-X is not supported - return number of SBs needed to support
12544 * one fast path queue: one FP queue + SB for CNIC
12547 dev_info(&pdev->dev, "no msix capability found\n");
12548 return 1 + cnic_cnt;
12550 dev_info(&pdev->dev, "msix capability found\n");
12553 * The value in the PCI configuration space is the index of the last
12554 * entry, namely one less than the actual size of the table, which is
12555 * exactly what we want to return from this function: number of all SBs
12556 * without the default SB.
12557 * For VFs there is no default SB, then we return (index+1).
12559 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12561 index = control & PCI_MSIX_FLAGS_QSIZE;
12563 return is_vf ? index + 1 : index;
12566 static int set_max_cos_est(int chip_id)
12572 return BNX2X_MULTI_TX_COS_E1X;
12576 return BNX2X_MULTI_TX_COS_E2_E3A0;
12582 case BCM57840_4_10:
12583 case BCM57840_2_20:
12592 return BNX2X_MULTI_TX_COS_E3B0;
12595 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12600 static int set_is_vf(int chip_id)
12614 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12616 static int bnx2x_init_one(struct pci_dev *pdev,
12617 const struct pci_device_id *ent)
12619 struct net_device *dev = NULL;
12622 enum bnx2x_pci_bus_speed pcie_speed;
12623 int rc, max_non_def_sbs;
12624 int rx_count, tx_count, rss_count, doorbell_size;
12629 /* An estimated maximum supported CoS number according to the chip
12631 * We will try to roughly estimate the maximum number of CoSes this chip
12632 * may support in order to minimize the memory allocated for Tx
12633 * netdev_queue's. This number will be accurately calculated during the
12634 * initialization of bp->max_cos based on the chip versions AND chip
12635 * revision in the bnx2x_init_bp().
12637 max_cos_est = set_max_cos_est(ent->driver_data);
12638 if (max_cos_est < 0)
12639 return max_cos_est;
12640 is_vf = set_is_vf(ent->driver_data);
12641 cnic_cnt = is_vf ? 0 : 1;
12643 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12645 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12646 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12651 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12652 rx_count = rss_count + cnic_cnt;
12654 /* Maximum number of netdev Tx queues:
12655 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12657 tx_count = rss_count * max_cos_est + cnic_cnt;
12659 /* dev zeroed in init_etherdev */
12660 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12664 bp = netdev_priv(dev);
12668 bp->flags |= IS_VF_FLAG;
12670 bp->igu_sb_cnt = max_non_def_sbs;
12671 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12672 bp->msg_enable = debug;
12673 bp->cnic_support = cnic_cnt;
12674 bp->cnic_probe = bnx2x_cnic_probe;
12676 pci_set_drvdata(pdev, dev);
12678 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12684 BNX2X_DEV_INFO("This is a %s function\n",
12685 IS_PF(bp) ? "physical" : "virtual");
12686 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12687 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12688 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12689 tx_count, rx_count);
12691 rc = bnx2x_init_bp(bp);
12693 goto init_one_exit;
12695 /* Map doorbells here as we need the real value of bp->max_cos which
12696 * is initialized in bnx2x_init_bp() to determine the number of
12700 bp->doorbells = bnx2x_vf_doorbells(bp);
12701 rc = bnx2x_vf_pci_alloc(bp);
12703 goto init_one_exit;
12705 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12706 if (doorbell_size > pci_resource_len(pdev, 2)) {
12707 dev_err(&bp->pdev->dev,
12708 "Cannot map doorbells, bar size too small, aborting\n");
12710 goto init_one_exit;
12712 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12715 if (!bp->doorbells) {
12716 dev_err(&bp->pdev->dev,
12717 "Cannot map doorbell space, aborting\n");
12719 goto init_one_exit;
12723 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12725 goto init_one_exit;
12728 /* Enable SRIOV if capability found in configuration space */
12729 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12731 goto init_one_exit;
12733 /* calc qm_cid_count */
12734 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12735 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12737 /* disable FCOE L2 queue for E1x*/
12738 if (CHIP_IS_E1x(bp))
12739 bp->flags |= NO_FCOE_FLAG;
12741 /* Set bp->num_queues for MSI-X mode*/
12742 bnx2x_set_num_queues(bp);
12744 /* Configure interrupt mode: try to enable MSI-X/MSI if
12747 rc = bnx2x_set_int_mode(bp);
12749 dev_err(&pdev->dev, "Cannot set interrupts\n");
12750 goto init_one_exit;
12752 BNX2X_DEV_INFO("set interrupts successfully\n");
12754 /* register the net device */
12755 rc = register_netdev(dev);
12757 dev_err(&pdev->dev, "Cannot register net device\n");
12758 goto init_one_exit;
12760 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12762 if (!NO_FCOE(bp)) {
12763 /* Add storage MAC address */
12765 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12769 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12770 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12771 pcie_width, pcie_speed);
12773 BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12774 board_info[ent->driver_data].name,
12775 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12777 pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12778 pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12779 pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12781 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12787 iounmap(bp->regview);
12789 if (IS_PF(bp) && bp->doorbells)
12790 iounmap(bp->doorbells);
12794 if (atomic_read(&pdev->enable_cnt) == 1)
12795 pci_release_regions(pdev);
12797 pci_disable_device(pdev);
12798 pci_set_drvdata(pdev, NULL);
12803 static void __bnx2x_remove(struct pci_dev *pdev,
12804 struct net_device *dev,
12806 bool remove_netdev)
12808 /* Delete storage MAC address */
12809 if (!NO_FCOE(bp)) {
12811 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12816 /* Delete app tlvs from dcbnl */
12817 bnx2x_dcbnl_update_applist(bp, true);
12820 /* Close the interface - either directly or implicitly */
12821 if (remove_netdev) {
12822 unregister_netdev(dev);
12825 if (netif_running(dev))
12830 bnx2x_iov_remove_one(bp);
12832 /* Power on: we can't let PCI layer write to us while we are in D3 */
12834 bnx2x_set_power_state(bp, PCI_D0);
12836 /* Disable MSI/MSI-X */
12837 bnx2x_disable_msi(bp);
12841 bnx2x_set_power_state(bp, PCI_D3hot);
12843 /* Make sure RESET task is not scheduled before continuing */
12844 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12846 /* send message via vfpf channel to release the resources of this vf */
12848 bnx2x_vfpf_release(bp);
12850 /* Assumes no further PCIe PM changes will occur */
12851 if (system_state == SYSTEM_POWER_OFF) {
12852 pci_wake_from_d3(pdev, bp->wol);
12853 pci_set_power_state(pdev, PCI_D3hot);
12857 iounmap(bp->regview);
12859 /* for vf doorbells are part of the regview and were unmapped along with
12860 * it. FW is only loaded by PF.
12864 iounmap(bp->doorbells);
12866 bnx2x_release_firmware(bp);
12868 bnx2x_free_mem_bp(bp);
12873 if (atomic_read(&pdev->enable_cnt) == 1)
12874 pci_release_regions(pdev);
12876 pci_disable_device(pdev);
12877 pci_set_drvdata(pdev, NULL);
12880 static void bnx2x_remove_one(struct pci_dev *pdev)
12882 struct net_device *dev = pci_get_drvdata(pdev);
12886 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12889 bp = netdev_priv(dev);
12891 __bnx2x_remove(pdev, dev, bp, true);
12894 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12896 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12898 bp->rx_mode = BNX2X_RX_MODE_NONE;
12900 if (CNIC_LOADED(bp))
12901 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12904 bnx2x_tx_disable(bp);
12905 /* Delete all NAPI objects */
12906 bnx2x_del_all_napi(bp);
12907 if (CNIC_LOADED(bp))
12908 bnx2x_del_all_napi_cnic(bp);
12909 netdev_reset_tc(bp->dev);
12911 del_timer_sync(&bp->timer);
12912 cancel_delayed_work(&bp->sp_task);
12913 cancel_delayed_work(&bp->period_task);
12915 spin_lock_bh(&bp->stats_lock);
12916 bp->stats_state = STATS_STATE_DISABLED;
12917 spin_unlock_bh(&bp->stats_lock);
12919 bnx2x_save_statistics(bp);
12921 netif_carrier_off(bp->dev);
12927 * bnx2x_io_error_detected - called when PCI error is detected
12928 * @pdev: Pointer to PCI device
12929 * @state: The current pci connection state
12931 * This function is called after a PCI bus error affecting
12932 * this device has been detected.
12934 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12935 pci_channel_state_t state)
12937 struct net_device *dev = pci_get_drvdata(pdev);
12938 struct bnx2x *bp = netdev_priv(dev);
12942 BNX2X_ERR("IO error detected\n");
12944 netif_device_detach(dev);
12946 if (state == pci_channel_io_perm_failure) {
12948 return PCI_ERS_RESULT_DISCONNECT;
12951 if (netif_running(dev))
12952 bnx2x_eeh_nic_unload(bp);
12954 bnx2x_prev_path_mark_eeh(bp);
12956 pci_disable_device(pdev);
12960 /* Request a slot reset */
12961 return PCI_ERS_RESULT_NEED_RESET;
12965 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12966 * @pdev: Pointer to PCI device
12968 * Restart the card from scratch, as if from a cold-boot.
12970 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12972 struct net_device *dev = pci_get_drvdata(pdev);
12973 struct bnx2x *bp = netdev_priv(dev);
12977 BNX2X_ERR("IO slot reset initializing...\n");
12978 if (pci_enable_device(pdev)) {
12979 dev_err(&pdev->dev,
12980 "Cannot re-enable PCI device after reset\n");
12982 return PCI_ERS_RESULT_DISCONNECT;
12985 pci_set_master(pdev);
12986 pci_restore_state(pdev);
12987 pci_save_state(pdev);
12989 if (netif_running(dev))
12990 bnx2x_set_power_state(bp, PCI_D0);
12992 if (netif_running(dev)) {
12993 BNX2X_ERR("IO slot reset --> driver unload\n");
12995 /* MCP should have been reset; Need to wait for validity */
12996 bnx2x_init_shmem(bp);
12998 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13002 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13003 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13004 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13006 bnx2x_drain_tx_queues(bp);
13007 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13008 bnx2x_netif_stop(bp, 1);
13009 bnx2x_free_irq(bp);
13011 /* Report UNLOAD_DONE to MCP */
13012 bnx2x_send_unload_done(bp, true);
13017 bnx2x_prev_unload(bp);
13019 /* We should have reseted the engine, so It's fair to
13020 * assume the FW will no longer write to the bnx2x driver.
13022 bnx2x_squeeze_objects(bp);
13023 bnx2x_free_skbs(bp);
13024 for_each_rx_queue(bp, i)
13025 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13026 bnx2x_free_fp_mem(bp);
13027 bnx2x_free_mem(bp);
13029 bp->state = BNX2X_STATE_CLOSED;
13034 return PCI_ERS_RESULT_RECOVERED;
13038 * bnx2x_io_resume - called when traffic can start flowing again
13039 * @pdev: Pointer to PCI device
13041 * This callback is called when the error recovery driver tells us that
13042 * its OK to resume normal operation.
13044 static void bnx2x_io_resume(struct pci_dev *pdev)
13046 struct net_device *dev = pci_get_drvdata(pdev);
13047 struct bnx2x *bp = netdev_priv(dev);
13049 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13050 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13056 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13057 DRV_MSG_SEQ_NUMBER_MASK;
13059 if (netif_running(dev))
13060 bnx2x_nic_load(bp, LOAD_NORMAL);
13062 netif_device_attach(dev);
13067 static const struct pci_error_handlers bnx2x_err_handler = {
13068 .error_detected = bnx2x_io_error_detected,
13069 .slot_reset = bnx2x_io_slot_reset,
13070 .resume = bnx2x_io_resume,
13073 static void bnx2x_shutdown(struct pci_dev *pdev)
13075 struct net_device *dev = pci_get_drvdata(pdev);
13081 bp = netdev_priv(dev);
13086 netif_device_detach(dev);
13089 /* Don't remove the netdevice, as there are scenarios which will cause
13090 * the kernel to hang, e.g., when trying to remove bnx2i while the
13091 * rootfs is mounted from SAN.
13093 __bnx2x_remove(pdev, dev, bp, false);
13096 static struct pci_driver bnx2x_pci_driver = {
13097 .name = DRV_MODULE_NAME,
13098 .id_table = bnx2x_pci_tbl,
13099 .probe = bnx2x_init_one,
13100 .remove = bnx2x_remove_one,
13101 .suspend = bnx2x_suspend,
13102 .resume = bnx2x_resume,
13103 .err_handler = &bnx2x_err_handler,
13104 #ifdef CONFIG_BNX2X_SRIOV
13105 .sriov_configure = bnx2x_sriov_configure,
13107 .shutdown = bnx2x_shutdown,
13110 static int __init bnx2x_init(void)
13114 pr_info("%s", version);
13116 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13117 if (bnx2x_wq == NULL) {
13118 pr_err("Cannot create workqueue\n");
13122 ret = pci_register_driver(&bnx2x_pci_driver);
13124 pr_err("Cannot register driver\n");
13125 destroy_workqueue(bnx2x_wq);
13130 static void __exit bnx2x_cleanup(void)
13132 struct list_head *pos, *q;
13134 pci_unregister_driver(&bnx2x_pci_driver);
13136 destroy_workqueue(bnx2x_wq);
13138 /* Free globally allocated resources */
13139 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13140 struct bnx2x_prev_path_list *tmp =
13141 list_entry(pos, struct bnx2x_prev_path_list, list);
13147 void bnx2x_notify_link_changed(struct bnx2x *bp)
13149 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13152 module_init(bnx2x_init);
13153 module_exit(bnx2x_cleanup);
13156 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13158 * @bp: driver handle
13159 * @set: set or clear the CAM entry
13161 * This function will wait until the ramrod completion returns.
13162 * Return 0 if success, -ENODEV if ramrod doesn't return.
13164 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13166 unsigned long ramrod_flags = 0;
13168 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13169 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13170 &bp->iscsi_l2_mac_obj, true,
13171 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13174 /* count denotes the number of new completions we have seen */
13175 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13177 struct eth_spe *spe;
13178 int cxt_index, cxt_offset;
13180 #ifdef BNX2X_STOP_ON_ERROR
13181 if (unlikely(bp->panic))
13185 spin_lock_bh(&bp->spq_lock);
13186 BUG_ON(bp->cnic_spq_pending < count);
13187 bp->cnic_spq_pending -= count;
13189 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13190 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13191 & SPE_HDR_CONN_TYPE) >>
13192 SPE_HDR_CONN_TYPE_SHIFT;
13193 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13194 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13196 /* Set validation for iSCSI L2 client before sending SETUP
13199 if (type == ETH_CONNECTION_TYPE) {
13200 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13201 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13203 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13204 (cxt_index * ILT_PAGE_CIDS);
13205 bnx2x_set_ctx_validation(bp,
13206 &bp->context[cxt_index].
13207 vcxt[cxt_offset].eth,
13208 BNX2X_ISCSI_ETH_CID(bp));
13213 * There may be not more than 8 L2, not more than 8 L5 SPEs
13214 * and in the air. We also check that number of outstanding
13215 * COMMON ramrods is not more than the EQ and SPQ can
13218 if (type == ETH_CONNECTION_TYPE) {
13219 if (!atomic_read(&bp->cq_spq_left))
13222 atomic_dec(&bp->cq_spq_left);
13223 } else if (type == NONE_CONNECTION_TYPE) {
13224 if (!atomic_read(&bp->eq_spq_left))
13227 atomic_dec(&bp->eq_spq_left);
13228 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13229 (type == FCOE_CONNECTION_TYPE)) {
13230 if (bp->cnic_spq_pending >=
13231 bp->cnic_eth_dev.max_kwqe_pending)
13234 bp->cnic_spq_pending++;
13236 BNX2X_ERR("Unknown SPE type: %d\n", type);
13241 spe = bnx2x_sp_get_next(bp);
13242 *spe = *bp->cnic_kwq_cons;
13244 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13245 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13247 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13248 bp->cnic_kwq_cons = bp->cnic_kwq;
13250 bp->cnic_kwq_cons++;
13252 bnx2x_sp_prod_update(bp);
13253 spin_unlock_bh(&bp->spq_lock);
13256 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13257 struct kwqe_16 *kwqes[], u32 count)
13259 struct bnx2x *bp = netdev_priv(dev);
13262 #ifdef BNX2X_STOP_ON_ERROR
13263 if (unlikely(bp->panic)) {
13264 BNX2X_ERR("Can't post to SP queue while panic\n");
13269 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13270 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13271 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13275 spin_lock_bh(&bp->spq_lock);
13277 for (i = 0; i < count; i++) {
13278 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13280 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13283 *bp->cnic_kwq_prod = *spe;
13285 bp->cnic_kwq_pending++;
13287 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13288 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13289 spe->data.update_data_addr.hi,
13290 spe->data.update_data_addr.lo,
13291 bp->cnic_kwq_pending);
13293 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13294 bp->cnic_kwq_prod = bp->cnic_kwq;
13296 bp->cnic_kwq_prod++;
13299 spin_unlock_bh(&bp->spq_lock);
13301 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13302 bnx2x_cnic_sp_post(bp, 0);
13307 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13309 struct cnic_ops *c_ops;
13312 mutex_lock(&bp->cnic_mutex);
13313 c_ops = rcu_dereference_protected(bp->cnic_ops,
13314 lockdep_is_held(&bp->cnic_mutex));
13316 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13317 mutex_unlock(&bp->cnic_mutex);
13322 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13324 struct cnic_ops *c_ops;
13328 c_ops = rcu_dereference(bp->cnic_ops);
13330 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13337 * for commands that have no data
13339 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13341 struct cnic_ctl_info ctl = {0};
13345 return bnx2x_cnic_ctl_send(bp, &ctl);
13348 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13350 struct cnic_ctl_info ctl = {0};
13352 /* first we tell CNIC and only then we count this as a completion */
13353 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13354 ctl.data.comp.cid = cid;
13355 ctl.data.comp.error = err;
13357 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13358 bnx2x_cnic_sp_post(bp, 0);
13361 /* Called with netif_addr_lock_bh() taken.
13362 * Sets an rx_mode config for an iSCSI ETH client.
13364 * Completion should be checked outside.
13366 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13368 unsigned long accept_flags = 0, ramrod_flags = 0;
13369 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13370 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13373 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13374 * because it's the only way for UIO Queue to accept
13375 * multicasts (in non-promiscuous mode only one Queue per
13376 * function will receive multicast packets (leading in our
13379 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13380 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13381 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13382 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13384 /* Clear STOP_PENDING bit if START is requested */
13385 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13387 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13389 /* Clear START_PENDING bit if STOP is requested */
13390 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13392 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13393 set_bit(sched_state, &bp->sp_state);
13395 __set_bit(RAMROD_RX, &ramrod_flags);
13396 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13401 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13403 struct bnx2x *bp = netdev_priv(dev);
13406 switch (ctl->cmd) {
13407 case DRV_CTL_CTXTBL_WR_CMD: {
13408 u32 index = ctl->data.io.offset;
13409 dma_addr_t addr = ctl->data.io.dma_addr;
13411 bnx2x_ilt_wr(bp, index, addr);
13415 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13416 int count = ctl->data.credit.credit_count;
13418 bnx2x_cnic_sp_post(bp, count);
13422 /* rtnl_lock is held. */
13423 case DRV_CTL_START_L2_CMD: {
13424 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13425 unsigned long sp_bits = 0;
13427 /* Configure the iSCSI classification object */
13428 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13429 cp->iscsi_l2_client_id,
13430 cp->iscsi_l2_cid, BP_FUNC(bp),
13431 bnx2x_sp(bp, mac_rdata),
13432 bnx2x_sp_mapping(bp, mac_rdata),
13433 BNX2X_FILTER_MAC_PENDING,
13434 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13437 /* Set iSCSI MAC address */
13438 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13445 /* Start accepting on iSCSI L2 ring */
13447 netif_addr_lock_bh(dev);
13448 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13449 netif_addr_unlock_bh(dev);
13451 /* bits to wait on */
13452 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13453 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13455 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13456 BNX2X_ERR("rx_mode completion timed out!\n");
13461 /* rtnl_lock is held. */
13462 case DRV_CTL_STOP_L2_CMD: {
13463 unsigned long sp_bits = 0;
13465 /* Stop accepting on iSCSI L2 ring */
13466 netif_addr_lock_bh(dev);
13467 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13468 netif_addr_unlock_bh(dev);
13470 /* bits to wait on */
13471 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13472 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13474 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13475 BNX2X_ERR("rx_mode completion timed out!\n");
13480 /* Unset iSCSI L2 MAC */
13481 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13482 BNX2X_ISCSI_ETH_MAC, true);
13485 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13486 int count = ctl->data.credit.credit_count;
13488 smp_mb__before_atomic_inc();
13489 atomic_add(count, &bp->cq_spq_left);
13490 smp_mb__after_atomic_inc();
13493 case DRV_CTL_ULP_REGISTER_CMD: {
13494 int ulp_type = ctl->data.register_data.ulp_type;
13496 if (CHIP_IS_E3(bp)) {
13497 int idx = BP_FW_MB_IDX(bp);
13498 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13499 int path = BP_PATH(bp);
13500 int port = BP_PORT(bp);
13502 u32 scratch_offset;
13505 /* first write capability to shmem2 */
13506 if (ulp_type == CNIC_ULP_ISCSI)
13507 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13508 else if (ulp_type == CNIC_ULP_FCOE)
13509 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13510 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13512 if ((ulp_type != CNIC_ULP_FCOE) ||
13513 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13514 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13517 /* if reached here - should write fcoe capabilities */
13518 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13519 if (!scratch_offset)
13521 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13522 fcoe_features[path][port]);
13523 host_addr = (u32 *) &(ctl->data.register_data.
13525 for (i = 0; i < sizeof(struct fcoe_capabilities);
13527 REG_WR(bp, scratch_offset + i,
13528 *(host_addr + i/4));
13533 case DRV_CTL_ULP_UNREGISTER_CMD: {
13534 int ulp_type = ctl->data.ulp_type;
13536 if (CHIP_IS_E3(bp)) {
13537 int idx = BP_FW_MB_IDX(bp);
13540 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13541 if (ulp_type == CNIC_ULP_ISCSI)
13542 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13543 else if (ulp_type == CNIC_ULP_FCOE)
13544 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13545 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13551 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13558 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13560 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13562 if (bp->flags & USING_MSIX_FLAG) {
13563 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13564 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13565 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13567 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13568 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13570 if (!CHIP_IS_E1x(bp))
13571 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13573 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13575 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13576 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13577 cp->irq_arr[1].status_blk = bp->def_status_blk;
13578 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13579 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13584 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13586 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13588 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13589 bnx2x_cid_ilt_lines(bp);
13590 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13591 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13592 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13594 if (NO_ISCSI_OOO(bp))
13595 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13598 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13601 struct bnx2x *bp = netdev_priv(dev);
13602 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13605 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13608 BNX2X_ERR("NULL ops received\n");
13612 if (!CNIC_SUPPORT(bp)) {
13613 BNX2X_ERR("Can't register CNIC when not supported\n");
13614 return -EOPNOTSUPP;
13617 if (!CNIC_LOADED(bp)) {
13618 rc = bnx2x_load_cnic(bp);
13620 BNX2X_ERR("CNIC-related load failed\n");
13625 bp->cnic_enabled = true;
13627 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13631 bp->cnic_kwq_cons = bp->cnic_kwq;
13632 bp->cnic_kwq_prod = bp->cnic_kwq;
13633 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13635 bp->cnic_spq_pending = 0;
13636 bp->cnic_kwq_pending = 0;
13638 bp->cnic_data = data;
13641 cp->drv_state |= CNIC_DRV_STATE_REGD;
13642 cp->iro_arr = bp->iro_arr;
13644 bnx2x_setup_cnic_irq_info(bp);
13646 rcu_assign_pointer(bp->cnic_ops, ops);
13651 static int bnx2x_unregister_cnic(struct net_device *dev)
13653 struct bnx2x *bp = netdev_priv(dev);
13654 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13656 mutex_lock(&bp->cnic_mutex);
13658 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13659 mutex_unlock(&bp->cnic_mutex);
13661 bp->cnic_enabled = false;
13662 kfree(bp->cnic_kwq);
13663 bp->cnic_kwq = NULL;
13668 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13670 struct bnx2x *bp = netdev_priv(dev);
13671 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13673 /* If both iSCSI and FCoE are disabled - return NULL in
13674 * order to indicate CNIC that it should not try to work
13675 * with this device.
13677 if (NO_ISCSI(bp) && NO_FCOE(bp))
13680 cp->drv_owner = THIS_MODULE;
13681 cp->chip_id = CHIP_ID(bp);
13682 cp->pdev = bp->pdev;
13683 cp->io_base = bp->regview;
13684 cp->io_base2 = bp->doorbells;
13685 cp->max_kwqe_pending = 8;
13686 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13687 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13688 bnx2x_cid_ilt_lines(bp);
13689 cp->ctx_tbl_len = CNIC_ILT_LINES;
13690 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13691 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13692 cp->drv_ctl = bnx2x_drv_ctl;
13693 cp->drv_register_cnic = bnx2x_register_cnic;
13694 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13695 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13696 cp->iscsi_l2_client_id =
13697 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13698 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13700 if (NO_ISCSI_OOO(bp))
13701 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13704 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13707 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13710 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13712 cp->ctx_tbl_offset,
13718 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13720 struct bnx2x *bp = fp->bp;
13721 u32 offset = BAR_USTRORM_INTMEM;
13724 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13725 else if (!CHIP_IS_E1x(bp))
13726 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13728 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13733 /* called only on E1H or E2.
13734 * When pretending to be PF, the pretend value is the function number 0...7
13735 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13738 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13742 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13745 /* get my own pretend register */
13746 pretend_reg = bnx2x_get_pretend_reg(bp);
13747 REG_WR(bp, pretend_reg, pretend_func_val);
13748 REG_RD(bp, pretend_reg);