drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96 int num_queues;
  97 module_param(num_queues, int, 0);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, 0);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 int int_mode;
 106 module_param(int_mode, int, 0);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, 0);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, 0);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, 0);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 struct workqueue_struct *bnx2x_wq;
 123
 124 struct bnx2x_mac_vals {
 125         u32 xmac_addr;
 126         u32 xmac_val;
 127         u32 emac_addr;
 128         u32 emac_val;
 129         u32 umac_addr;
 130         u32 umac_val;
 131         u32 bmac_addr;
 132         u32 bmac_val[2];
 133 };
 134
 135 enum bnx2x_board_type {
 136         BCM57710 = 0,
 137         BCM57711,
 138         BCM57711E,
 139         BCM57712,
 140         BCM57712_MF,
 141         BCM57712_VF,
 142         BCM57800,
 143         BCM57800_MF,
 144         BCM57800_VF,
 145         BCM57810,
 146         BCM57810_MF,
 147         BCM57810_VF,
 148         BCM57840_4_10,
 149         BCM57840_2_20,
 150         BCM57840_MF,
 151         BCM57840_VF,
 152         BCM57811,
 153         BCM57811_MF,
 154         BCM57840_O,
 155         BCM57840_MFO,
 156         BCM57811_VF
 157 };
 158
 159 /* indexed by board_type, above */
 160 static struct {
 161         char *name;
 162 } board_info[] = {
 163         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 164         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 165         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 166         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 167         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 168         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 170         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 171         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 173         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 174         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 176         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 177         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 178         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 179         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 180         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 181         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 182         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 184 };
 185
 186 #ifndef PCI_DEVICE_ID_NX2_57710
 187 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711
 190 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711E
 193 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712
 196 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 199 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 202 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800
 205 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 208 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 211 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810
 214 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 217 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57840_O
 220 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 223 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 226 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 229 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 232 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 235 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 238 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811
 241 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 244 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 247 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 248 #endif
 249
 250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 272         { 0 }
 273 };
 274
 275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 276
 277 /* Global resources for unloading a previously loaded device */
 278 #define BNX2X_PREV_WAIT_NEEDED 1
 279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 280 static LIST_HEAD(bnx2x_prev_list);
 281 /****************************************************************************
 282 * General service functions
 283 ****************************************************************************/
 284
 285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 286                                        u32 addr, dma_addr_t mapping)
 287 {
 288         REG_WR(bp,  addr, U64_LO(mapping));
 289         REG_WR(bp,  addr + 4, U64_HI(mapping));
 290 }
 291
 292 static void storm_memset_spq_addr(struct bnx2x *bp,
 293                                   dma_addr_t mapping, u16 abs_fid)
 294 {
 295         u32 addr = XSEM_REG_FAST_MEMORY +
 296                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 297
 298         __storm_memset_dma_mapping(bp, addr, mapping);
 299 }
 300
 301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 302                                   u16 pf_id)
 303 {
 304         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 305                 pf_id);
 306         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 307                 pf_id);
 308         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 309                 pf_id);
 310         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 311                 pf_id);
 312 }
 313
 314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 315                                  u8 enable)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 318                 enable);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 320                 enable);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 322                 enable);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 324                 enable);
 325 }
 326
 327 static void storm_memset_eq_data(struct bnx2x *bp,
 328                                  struct event_ring_data *eq_data,
 329                                 u16 pfid)
 330 {
 331         size_t size = sizeof(struct event_ring_data);
 332
 333         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 334
 335         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 336 }
 337
 338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 339                                  u16 pfid)
 340 {
 341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 342         REG_WR16(bp, addr, eq_prod);
 343 }
 344
 345 /* used only at init
 346  * locking is done by mcp
 347  */
 348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 349 {
 350         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 351         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 352         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 353                                PCICFG_VENDOR_ID_OFFSET);
 354 }
 355
 356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 357 {
 358         u32 val;
 359
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 361         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 363                                PCICFG_VENDOR_ID_OFFSET);
 364
 365         return val;
 366 }
 367
 368 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 369 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 370 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 371 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 372 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 373
 374 static void bnx2x_dp_dmae(struct bnx2x *bp,
 375                           struct dmae_command *dmae, int msglvl)
 376 {
 377         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 378         int i;
 379
 380         switch (dmae->opcode & DMAE_COMMAND_DST) {
 381         case DMAE_CMD_DST_PCI:
 382                 if (src_type == DMAE_CMD_SRC_PCI)
 383                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 384                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 385                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 386                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 387                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 388                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 389                            dmae->comp_val);
 390                 else
 391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 392                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 394                            dmae->opcode, dmae->src_addr_lo >> 2,
 395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 397                            dmae->comp_val);
 398                 break;
 399         case DMAE_CMD_DST_GRC:
 400                 if (src_type == DMAE_CMD_SRC_PCI)
 401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 402                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 404                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 405                            dmae->len, dmae->dst_addr_lo >> 2,
 406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 407                            dmae->comp_val);
 408                 else
 409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 410                            "src [%08x], len [%d*4], dst [%08x]\n"
 411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 412                            dmae->opcode, dmae->src_addr_lo >> 2,
 413                            dmae->len, dmae->dst_addr_lo >> 2,
 414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 415                            dmae->comp_val);
 416                 break;
 417         default:
 418                 if (src_type == DMAE_CMD_SRC_PCI)
 419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 420                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 421                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 422                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 423                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 424                            dmae->comp_val);
 425                 else
 426                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 427                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 428                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 429                            dmae->opcode, dmae->src_addr_lo >> 2,
 430                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 431                            dmae->comp_val);
 432                 break;
 433         }
 434
 435         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 436                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 437                    i, *(((u32 *)dmae) + i));
 438 }
 439
 440 /* copy command into DMAE command memory and set DMAE command go */
 441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 442 {
 443         u32 cmd_offset;
 444         int i;
 445
 446         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 447         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 448                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 449         }
 450         REG_WR(bp, dmae_reg_go_c[idx], 1);
 451 }
 452
 453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 454 {
 455         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 456                            DMAE_CMD_C_ENABLE);
 457 }
 458
 459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 460 {
 461         return opcode & ~DMAE_CMD_SRC_RESET;
 462 }
 463
 464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 465                              bool with_comp, u8 comp_type)
 466 {
 467         u32 opcode = 0;
 468
 469         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 470                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 471
 472         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 473
 474         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 475         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 476                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 477         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 478
 479 #ifdef __BIG_ENDIAN
 480         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 481 #else
 482         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 483 #endif
 484         if (with_comp)
 485                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 486         return opcode;
 487 }
 488
 489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 490                                       struct dmae_command *dmae,
 491                                       u8 src_type, u8 dst_type)
 492 {
 493         memset(dmae, 0, sizeof(struct dmae_command));
 494
 495         /* set the opcode */
 496         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 497                                          true, DMAE_COMP_PCI);
 498
 499         /* fill in the completion parameters */
 500         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_val = DMAE_COMP_VAL;
 503 }
 504
 505 /* issue a dmae command over the init-channel and wait for completion */
 506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 507 {
 508         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 509         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 510         int rc = 0;
 511
 512         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 513
 514         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 515          * as long as this code is called both from syscall context and
 516          * from ndo_set_rx_mode() flow that may be called from BH.
 517          */
 518         spin_lock_bh(&bp->dmae_lock);
 519
 520         /* reset completion */
 521         *wb_comp = 0;
 522
 523         /* post the command on the channel used for initializations */
 524         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 525
 526         /* wait for completion */
 527         udelay(5);
 528         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 529
 530                 if (!cnt ||
 531                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 532                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 533                         BNX2X_ERR("DMAE timeout!\n");
 534                         rc = DMAE_TIMEOUT;
 535                         goto unlock;
 536                 }
 537                 cnt--;
 538                 udelay(50);
 539         }
 540         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 541                 BNX2X_ERR("DMAE PCI error!\n");
 542                 rc = DMAE_PCI_ERROR;
 543         }
 544
 545 unlock:
 546         spin_unlock_bh(&bp->dmae_lock);
 547         return rc;
 548 }
 549
 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 551                       u32 len32)
 552 {
 553         int rc;
 554         struct dmae_command dmae;
 555
 556         if (!bp->dmae_ready) {
 557                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 558
 559                 if (CHIP_IS_E1(bp))
 560                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 561                 else
 562                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 563                 return;
 564         }
 565
 566         /* set opcode and fixed command fields */
 567         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 568
 569         /* fill in addresses and len */
 570         dmae.src_addr_lo = U64_LO(dma_addr);
 571         dmae.src_addr_hi = U64_HI(dma_addr);
 572         dmae.dst_addr_lo = dst_addr >> 2;
 573         dmae.dst_addr_hi = 0;
 574         dmae.len = len32;
 575
 576         /* issue the command and wait for completion */
 577         rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
 578         if (rc) {
 579                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 580                 bnx2x_panic();
 581         }
 582 }
 583
 584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 585 {
 586         int rc;
 587         struct dmae_command dmae;
 588
 589         if (!bp->dmae_ready) {
 590                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 591                 int i;
 592
 593                 if (CHIP_IS_E1(bp))
 594                         for (i = 0; i < len32; i++)
 595                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 596                 else
 597                         for (i = 0; i < len32; i++)
 598                                 data[i] = REG_RD(bp, src_addr + i*4);
 599
 600                 return;
 601         }
 602
 603         /* set opcode and fixed command fields */
 604         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 605
 606         /* fill in addresses and len */
 607         dmae.src_addr_lo = src_addr >> 2;
 608         dmae.src_addr_hi = 0;
 609         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 610         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 611         dmae.len = len32;
 612
 613         /* issue the command and wait for completion */
 614         rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
 615         if (rc) {
 616                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 617                 bnx2x_panic();
 618         }
 619 }
 620
 621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 622                                       u32 addr, u32 len)
 623 {
 624         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 625         int offset = 0;
 626
 627         while (len > dmae_wr_max) {
 628                 bnx2x_write_dmae(bp, phys_addr + offset,
 629                                  addr + offset, dmae_wr_max);
 630                 offset += dmae_wr_max * 4;
 631                 len -= dmae_wr_max;
 632         }
 633
 634         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 635 }
 636
 637 static int bnx2x_mc_assert(struct bnx2x *bp)
 638 {
 639         char last_idx;
 640         int i, rc = 0;
 641         u32 row0, row1, row2, row3;
 642
 643         /* XSTORM */
 644         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 645                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 646         if (last_idx)
 647                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 648
 649         /* print the asserts */
 650         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 651
 652                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 653                               XSTORM_ASSERT_LIST_OFFSET(i));
 654                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 655                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 656                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 657                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 658                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 659                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 660
 661                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 662                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 663                                   i, row3, row2, row1, row0);
 664                         rc++;
 665                 } else {
 666                         break;
 667                 }
 668         }
 669
 670         /* TSTORM */
 671         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 672                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 673         if (last_idx)
 674                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 675
 676         /* print the asserts */
 677         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 678
 679                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 680                               TSTORM_ASSERT_LIST_OFFSET(i));
 681                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 682                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 683                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 684                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 685                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 686                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 687
 688                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 689                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 690                                   i, row3, row2, row1, row0);
 691                         rc++;
 692                 } else {
 693                         break;
 694                 }
 695         }
 696
 697         /* CSTORM */
 698         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 699                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 700         if (last_idx)
 701                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 702
 703         /* print the asserts */
 704         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 705
 706                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 707                               CSTORM_ASSERT_LIST_OFFSET(i));
 708                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 709                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 710                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 711                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 712                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 713                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 714
 715                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 716                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 717                                   i, row3, row2, row1, row0);
 718                         rc++;
 719                 } else {
 720                         break;
 721                 }
 722         }
 723
 724         /* USTORM */
 725         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 726                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 727         if (last_idx)
 728                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 729
 730         /* print the asserts */
 731         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 732
 733                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 734                               USTORM_ASSERT_LIST_OFFSET(i));
 735                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 736                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 737                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 738                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 739                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 740                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 741
 742                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 743                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 744                                   i, row3, row2, row1, row0);
 745                         rc++;
 746                 } else {
 747                         break;
 748                 }
 749         }
 750
 751         return rc;
 752 }
 753
 754 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 755 #define SCRATCH_BUFFER_SIZE(bp) \
 756         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 757
 758 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 759 {
 760         u32 addr, val;
 761         u32 mark, offset;
 762         __be32 data[9];
 763         int word;
 764         u32 trace_shmem_base;
 765         if (BP_NOMCP(bp)) {
 766                 BNX2X_ERR("NO MCP - can not dump\n");
 767                 return;
 768         }
 769         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 770                 (bp->common.bc_ver & 0xff0000) >> 16,
 771                 (bp->common.bc_ver & 0xff00) >> 8,
 772                 (bp->common.bc_ver & 0xff));
 773
 774         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 775         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 776                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 777
 778         if (BP_PATH(bp) == 0)
 779                 trace_shmem_base = bp->common.shmem_base;
 780         else
 781                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 782
 783         /* sanity */
 784         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 785             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 786                                 SCRATCH_BUFFER_SIZE(bp)) {
 787                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 788                           trace_shmem_base);
 789                 return;
 790         }
 791
 792         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 793
 794         /* validate TRCB signature */
 795         mark = REG_RD(bp, addr);
 796         if (mark != MFW_TRACE_SIGNATURE) {
 797                 BNX2X_ERR("Trace buffer signature is missing.");
 798                 return ;
 799         }
 800
 801         /* read cyclic buffer pointer */
 802         addr += 4;
 803         mark = REG_RD(bp, addr);
 804         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 805         if (mark >= trace_shmem_base || mark < addr + 4) {
 806                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 807                 return;
 808         }
 809         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 810
 811         printk("%s", lvl);
 812
 813         /* dump buffer after the mark */
 814         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 815                 for (word = 0; word < 8; word++)
 816                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 817                 data[8] = 0x0;
 818                 pr_cont("%s", (char *)data);
 819         }
 820
 821         /* dump buffer before the mark */
 822         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 823                 for (word = 0; word < 8; word++)
 824                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 825                 data[8] = 0x0;
 826                 pr_cont("%s", (char *)data);
 827         }
 828         printk("%s" "end of fw dump\n", lvl);
 829 }
 830
 831 static void bnx2x_fw_dump(struct bnx2x *bp)
 832 {
 833         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 834 }
 835
 836 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 837 {
 838         int port = BP_PORT(bp);
 839         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 840         u32 val = REG_RD(bp, addr);
 841
 842         /* in E1 we must use only PCI configuration space to disable
 843          * MSI/MSIX capability
 844          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 845          */
 846         if (CHIP_IS_E1(bp)) {
 847                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 848                  * Use mask register to prevent from HC sending interrupts
 849                  * after we exit the function
 850                  */
 851                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 852
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 855                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 856         } else
 857                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 858                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861
 862         DP(NETIF_MSG_IFDOWN,
 863            "write %x to HC %d (addr 0x%x)\n",
 864            val, port, addr);
 865
 866         /* flush all outstanding writes */
 867         mmiowb();
 868
 869         REG_WR(bp, addr, val);
 870         if (REG_RD(bp, addr) != val)
 871                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 872 }
 873
 874 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 875 {
 876         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 877
 878         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 879                  IGU_PF_CONF_INT_LINE_EN |
 880                  IGU_PF_CONF_ATTN_BIT_EN);
 881
 882         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 883
 884         /* flush all outstanding writes */
 885         mmiowb();
 886
 887         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 888         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 889                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 890 }
 891
 892 static void bnx2x_int_disable(struct bnx2x *bp)
 893 {
 894         if (bp->common.int_block == INT_BLOCK_HC)
 895                 bnx2x_hc_int_disable(bp);
 896         else
 897                 bnx2x_igu_int_disable(bp);
 898 }
 899
 900 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 901 {
 902         int i;
 903         u16 j;
 904         struct hc_sp_status_block_data sp_sb_data;
 905         int func = BP_FUNC(bp);
 906 #ifdef BNX2X_STOP_ON_ERROR
 907         u16 start = 0, end = 0;
 908         u8 cos;
 909 #endif
 910         if (disable_int)
 911                 bnx2x_int_disable(bp);
 912
 913         bp->stats_state = STATS_STATE_DISABLED;
 914         bp->eth_stats.unrecoverable_error++;
 915         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 916
 917         BNX2X_ERR("begin crash dump -----------------\n");
 918
 919         /* Indices */
 920         /* Common */
 921         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                   bp->spq_prod_idx, bp->stats_counter);
 924         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                   bp->def_status_blk->atten_status_block.attn_bits,
 926                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 927                   bp->def_status_blk->atten_status_block.status_block_id,
 928                   bp->def_status_blk->atten_status_block.attn_bits_index);
 929         BNX2X_ERR("     def (");
 930         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                 pr_cont("0x%x%s",
 932                         bp->def_status_blk->sp_sb.index_values[i],
 933                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 936                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 937                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 938                         i*sizeof(u32));
 939
 940         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 941                sp_sb_data.igu_sb_id,
 942                sp_sb_data.igu_seg_id,
 943                sp_sb_data.p_func.pf_id,
 944                sp_sb_data.p_func.vnic_id,
 945                sp_sb_data.p_func.vf_id,
 946                sp_sb_data.p_func.vf_valid,
 947                sp_sb_data.state);
 948
 949         for_each_eth_queue(bp, i) {
 950                 struct bnx2x_fastpath *fp = &bp->fp[i];
 951                 int loop;
 952                 struct hc_status_block_data_e2 sb_data_e2;
 953                 struct hc_status_block_data_e1x sb_data_e1x;
 954                 struct hc_status_block_sm  *hc_sm_p =
 955                         CHIP_IS_E1x(bp) ?
 956                         sb_data_e1x.common.state_machine :
 957                         sb_data_e2.common.state_machine;
 958                 struct hc_index_data *hc_index_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.index_data :
 961                         sb_data_e2.index_data;
 962                 u8 data_size, cos;
 963                 u32 *sb_data_p;
 964                 struct bnx2x_fp_txdata txdata;
 965
 966                 /* Rx */
 967                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 968                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 969                           fp->rx_comp_prod,
 970                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 971                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 972                           fp->rx_sge_prod, fp->last_max_sge,
 973                           le16_to_cpu(fp->fp_hc_idx));
 974
 975                 /* Tx */
 976                 for_each_cos_in_tx_queue(fp, cos)
 977                 {
 978                         txdata = *fp->txdata_ptr[cos];
 979                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 980                                   i, txdata.tx_pkt_prod,
 981                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 982                                   txdata.tx_bd_cons,
 983                                   le16_to_cpu(*txdata.tx_cons_sb));
 984                 }
 985
 986                 loop = CHIP_IS_E1x(bp) ?
 987                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 988
 989                 /* host sb data */
 990
 991                 if (IS_FCOE_FP(fp))
 992                         continue;
 993
 994                 BNX2X_ERR("     run indexes (");
 995                 for (j = 0; j < HC_SB_MAX_SM; j++)
 996                         pr_cont("0x%x%s",
 997                                fp->sb_running_index[j],
 998                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 999
1000                 BNX2X_ERR("     indexes (");
1001                 for (j = 0; j < loop; j++)
1002                         pr_cont("0x%x%s",
1003                                fp->sb_index_values[j],
1004                                (j == loop - 1) ? ")" : " ");
1005                 /* fw sb data */
1006                 data_size = CHIP_IS_E1x(bp) ?
1007                         sizeof(struct hc_status_block_data_e1x) :
1008                         sizeof(struct hc_status_block_data_e2);
1009                 data_size /= sizeof(u32);
1010                 sb_data_p = CHIP_IS_E1x(bp) ?
1011                         (u32 *)&sb_data_e1x :
1012                         (u32 *)&sb_data_e2;
1013                 /* copy sb data in here */
1014                 for (j = 0; j < data_size; j++)
1015                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1016                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1017                                 j * sizeof(u32));
1018
1019                 if (!CHIP_IS_E1x(bp)) {
1020                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1021                                 sb_data_e2.common.p_func.pf_id,
1022                                 sb_data_e2.common.p_func.vf_id,
1023                                 sb_data_e2.common.p_func.vf_valid,
1024                                 sb_data_e2.common.p_func.vnic_id,
1025                                 sb_data_e2.common.same_igu_sb_1b,
1026                                 sb_data_e2.common.state);
1027                 } else {
1028                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1029                                 sb_data_e1x.common.p_func.pf_id,
1030                                 sb_data_e1x.common.p_func.vf_id,
1031                                 sb_data_e1x.common.p_func.vf_valid,
1032                                 sb_data_e1x.common.p_func.vnic_id,
1033                                 sb_data_e1x.common.same_igu_sb_1b,
1034                                 sb_data_e1x.common.state);
1035                 }
1036
1037                 /* SB_SMs data */
1038                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1039                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1040                                 j, hc_sm_p[j].__flags,
1041                                 hc_sm_p[j].igu_sb_id,
1042                                 hc_sm_p[j].igu_seg_id,
1043                                 hc_sm_p[j].time_to_expire,
1044                                 hc_sm_p[j].timer_value);
1045                 }
1046
1047                 /* Indices data */
1048                 for (j = 0; j < loop; j++) {
1049                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1050                                hc_index_p[j].flags,
1051                                hc_index_p[j].timeout);
1052                 }
1053         }
1054
1055 #ifdef BNX2X_STOP_ON_ERROR
1056
1057         /* event queue */
1058         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1059         for (i = 0; i < NUM_EQ_DESC; i++) {
1060                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1061
1062                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1063                           i, bp->eq_ring[i].message.opcode,
1064                           bp->eq_ring[i].message.error);
1065                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1066         }
1067
1068         /* Rings */
1069         /* Rx */
1070         for_each_valid_rx_queue(bp, i) {
1071                 struct bnx2x_fastpath *fp = &bp->fp[i];
1072
1073                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1074                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1075                 for (j = start; j != end; j = RX_BD(j + 1)) {
1076                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1077                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1078
1079                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1080                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1081                 }
1082
1083                 start = RX_SGE(fp->rx_sge_prod);
1084                 end = RX_SGE(fp->last_max_sge);
1085                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1086                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1087                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1088
1089                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1090                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1091                 }
1092
1093                 start = RCQ_BD(fp->rx_comp_cons - 10);
1094                 end = RCQ_BD(fp->rx_comp_cons + 503);
1095                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1096                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1097
1098                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1099                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1100                 }
1101         }
1102
1103         /* Tx */
1104         for_each_valid_tx_queue(bp, i) {
1105                 struct bnx2x_fastpath *fp = &bp->fp[i];
1106                 for_each_cos_in_tx_queue(fp, cos) {
1107                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1108
1109                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1110                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1111                         for (j = start; j != end; j = TX_BD(j + 1)) {
1112                                 struct sw_tx_bd *sw_bd =
1113                                         &txdata->tx_buf_ring[j];
1114
1115                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1116                                           i, cos, j, sw_bd->skb,
1117                                           sw_bd->first_bd);
1118                         }
1119
1120                         start = TX_BD(txdata->tx_bd_cons - 10);
1121                         end = TX_BD(txdata->tx_bd_cons + 254);
1122                         for (j = start; j != end; j = TX_BD(j + 1)) {
1123                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1124
1125                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1126                                           i, cos, j, tx_bd[0], tx_bd[1],
1127                                           tx_bd[2], tx_bd[3]);
1128                         }
1129                 }
1130         }
1131 #endif
1132         bnx2x_fw_dump(bp);
1133         bnx2x_mc_assert(bp);
1134         BNX2X_ERR("end crash dump -----------------\n");
1135 }
1136
1137 /*
1138  * FLR Support for E2
1139  *
1140  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1141  * initialization.
1142  */
1143 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1144 #define FLR_WAIT_INTERVAL       50      /* usec */
1145 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1146
1147 struct pbf_pN_buf_regs {
1148         int pN;
1149         u32 init_crd;
1150         u32 crd;
1151         u32 crd_freed;
1152 };
1153
1154 struct pbf_pN_cmd_regs {
1155         int pN;
1156         u32 lines_occup;
1157         u32 lines_freed;
1158 };
1159
1160 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1161                                      struct pbf_pN_buf_regs *regs,
1162                                      u32 poll_count)
1163 {
1164         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1165         u32 cur_cnt = poll_count;
1166
1167         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1168         crd = crd_start = REG_RD(bp, regs->crd);
1169         init_crd = REG_RD(bp, regs->init_crd);
1170
1171         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1172         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1173         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1174
1175         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1176                (init_crd - crd_start))) {
1177                 if (cur_cnt--) {
1178                         udelay(FLR_WAIT_INTERVAL);
1179                         crd = REG_RD(bp, regs->crd);
1180                         crd_freed = REG_RD(bp, regs->crd_freed);
1181                 } else {
1182                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1183                            regs->pN);
1184                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1185                            regs->pN, crd);
1186                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1187                            regs->pN, crd_freed);
1188                         break;
1189                 }
1190         }
1191         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1192            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1193 }
1194
1195 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1196                                      struct pbf_pN_cmd_regs *regs,
1197                                      u32 poll_count)
1198 {
1199         u32 occup, to_free, freed, freed_start;
1200         u32 cur_cnt = poll_count;
1201
1202         occup = to_free = REG_RD(bp, regs->lines_occup);
1203         freed = freed_start = REG_RD(bp, regs->lines_freed);
1204
1205         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1206         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1207
1208         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1209                 if (cur_cnt--) {
1210                         udelay(FLR_WAIT_INTERVAL);
1211                         occup = REG_RD(bp, regs->lines_occup);
1212                         freed = REG_RD(bp, regs->lines_freed);
1213                 } else {
1214                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1215                            regs->pN);
1216                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1217                            regs->pN, occup);
1218                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1219                            regs->pN, freed);
1220                         break;
1221                 }
1222         }
1223         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1224            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1225 }
1226
1227 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1228                                     u32 expected, u32 poll_count)
1229 {
1230         u32 cur_cnt = poll_count;
1231         u32 val;
1232
1233         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1234                 udelay(FLR_WAIT_INTERVAL);
1235
1236         return val;
1237 }
1238
1239 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1240                                     char *msg, u32 poll_cnt)
1241 {
1242         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1243         if (val != 0) {
1244                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1245                 return 1;
1246         }
1247         return 0;
1248 }
1249
1250 /* Common routines with VF FLR cleanup */
1251 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1252 {
1253         /* adjust polling timeout */
1254         if (CHIP_REV_IS_EMUL(bp))
1255                 return FLR_POLL_CNT * 2000;
1256
1257         if (CHIP_REV_IS_FPGA(bp))
1258                 return FLR_POLL_CNT * 120;
1259
1260         return FLR_POLL_CNT;
1261 }
1262
1263 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1264 {
1265         struct pbf_pN_cmd_regs cmd_regs[] = {
1266                 {0, (CHIP_IS_E3B0(bp)) ?
1267                         PBF_REG_TQ_OCCUPANCY_Q0 :
1268                         PBF_REG_P0_TQ_OCCUPANCY,
1269                     (CHIP_IS_E3B0(bp)) ?
1270                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1271                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1272                 {1, (CHIP_IS_E3B0(bp)) ?
1273                         PBF_REG_TQ_OCCUPANCY_Q1 :
1274                         PBF_REG_P1_TQ_OCCUPANCY,
1275                     (CHIP_IS_E3B0(bp)) ?
1276                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1277                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1278                 {4, (CHIP_IS_E3B0(bp)) ?
1279                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1280                         PBF_REG_P4_TQ_OCCUPANCY,
1281                     (CHIP_IS_E3B0(bp)) ?
1282                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1283                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1284         };
1285
1286         struct pbf_pN_buf_regs buf_regs[] = {
1287                 {0, (CHIP_IS_E3B0(bp)) ?
1288                         PBF_REG_INIT_CRD_Q0 :
1289                         PBF_REG_P0_INIT_CRD ,
1290                     (CHIP_IS_E3B0(bp)) ?
1291                         PBF_REG_CREDIT_Q0 :
1292                         PBF_REG_P0_CREDIT,
1293                     (CHIP_IS_E3B0(bp)) ?
1294                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1295                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1296                 {1, (CHIP_IS_E3B0(bp)) ?
1297                         PBF_REG_INIT_CRD_Q1 :
1298                         PBF_REG_P1_INIT_CRD,
1299                     (CHIP_IS_E3B0(bp)) ?
1300                         PBF_REG_CREDIT_Q1 :
1301                         PBF_REG_P1_CREDIT,
1302                     (CHIP_IS_E3B0(bp)) ?
1303                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1304                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1305                 {4, (CHIP_IS_E3B0(bp)) ?
1306                         PBF_REG_INIT_CRD_LB_Q :
1307                         PBF_REG_P4_INIT_CRD,
1308                     (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_CREDIT_LB_Q :
1310                         PBF_REG_P4_CREDIT,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1313                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1314         };
1315
1316         int i;
1317
1318         /* Verify the command queues are flushed P0, P1, P4 */
1319         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1320                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1321
1322         /* Verify the transmission buffers are flushed P0, P1, P4 */
1323         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1324                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1325 }
1326
1327 #define OP_GEN_PARAM(param) \
1328         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1329
1330 #define OP_GEN_TYPE(type) \
1331         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1332
1333 #define OP_GEN_AGG_VECT(index) \
1334         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1335
1336 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1337 {
1338         u32 op_gen_command = 0;
1339         u32 comp_addr = BAR_CSTRORM_INTMEM +
1340                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1341         int ret = 0;
1342
1343         if (REG_RD(bp, comp_addr)) {
1344                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1345                 return 1;
1346         }
1347
1348         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1349         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1350         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1351         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1352
1353         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1354         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1355
1356         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1357                 BNX2X_ERR("FW final cleanup did not succeed\n");
1358                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1359                    (REG_RD(bp, comp_addr)));
1360                 bnx2x_panic();
1361                 return 1;
1362         }
1363         /* Zero completion for next FLR */
1364         REG_WR(bp, comp_addr, 0);
1365
1366         return ret;
1367 }
1368
1369 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1370 {
1371         u16 status;
1372
1373         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1374         return status & PCI_EXP_DEVSTA_TRPND;
1375 }
1376
1377 /* PF FLR specific routines
1378 */
1379 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1380 {
1381         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1382         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1383                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1384                         "CFC PF usage counter timed out",
1385                         poll_cnt))
1386                 return 1;
1387
1388         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1389         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1390                         DORQ_REG_PF_USAGE_CNT,
1391                         "DQ PF usage counter timed out",
1392                         poll_cnt))
1393                 return 1;
1394
1395         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1396         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1397                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1398                         "QM PF usage counter timed out",
1399                         poll_cnt))
1400                 return 1;
1401
1402         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1403         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1404                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1405                         "Timers VNIC usage counter timed out",
1406                         poll_cnt))
1407                 return 1;
1408         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1409                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1410                         "Timers NUM_SCANS usage counter timed out",
1411                         poll_cnt))
1412                 return 1;
1413
1414         /* Wait DMAE PF usage counter to zero */
1415         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1416                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1417                         "DMAE command register timed out",
1418                         poll_cnt))
1419                 return 1;
1420
1421         return 0;
1422 }
1423
1424 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1425 {
1426         u32 val;
1427
1428         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1429         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1430
1431         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1432         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1433
1434         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1435         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1436
1437         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1438         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1439
1440         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1441         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1442
1443         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1444         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1445
1446         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1447         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1448
1449         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1450         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1451            val);
1452 }
1453
1454 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1455 {
1456         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1457
1458         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1459
1460         /* Re-enable PF target read access */
1461         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1462
1463         /* Poll HW usage counters */
1464         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1465         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1466                 return -EBUSY;
1467
1468         /* Zero the igu 'trailing edge' and 'leading edge' */
1469
1470         /* Send the FW cleanup command */
1471         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1472                 return -EBUSY;
1473
1474         /* ATC cleanup */
1475
1476         /* Verify TX hw is flushed */
1477         bnx2x_tx_hw_flushed(bp, poll_cnt);
1478
1479         /* Wait 100ms (not adjusted according to platform) */
1480         msleep(100);
1481
1482         /* Verify no pending pci transactions */
1483         if (bnx2x_is_pcie_pending(bp->pdev))
1484                 BNX2X_ERR("PCIE Transactions still pending\n");
1485
1486         /* Debug */
1487         bnx2x_hw_enable_status(bp);
1488
1489         /*
1490          * Master enable - Due to WB DMAE writes performed before this
1491          * register is re-initialized as part of the regular function init
1492          */
1493         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1494
1495         return 0;
1496 }
1497
1498 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1499 {
1500         int port = BP_PORT(bp);
1501         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1502         u32 val = REG_RD(bp, addr);
1503         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1504         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1505         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1506
1507         if (msix) {
1508                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1509                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1510                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1511                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1512                 if (single_msix)
1513                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1514         } else if (msi) {
1515                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1516                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1519         } else {
1520                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1521                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1522                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1523                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1524
1525                 if (!CHIP_IS_E1(bp)) {
1526                         DP(NETIF_MSG_IFUP,
1527                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1528
1529                         REG_WR(bp, addr, val);
1530
1531                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1532                 }
1533         }
1534
1535         if (CHIP_IS_E1(bp))
1536                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1537
1538         DP(NETIF_MSG_IFUP,
1539            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1540            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1541
1542         REG_WR(bp, addr, val);
1543         /*
1544          * Ensure that HC_CONFIG is written before leading/trailing edge config
1545          */
1546         mmiowb();
1547         barrier();
1548
1549         if (!CHIP_IS_E1(bp)) {
1550                 /* init leading/trailing edge */
1551                 if (IS_MF(bp)) {
1552                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1553                         if (bp->port.pmf)
1554                                 /* enable nig and gpio3 attention */
1555                                 val |= 0x1100;
1556                 } else
1557                         val = 0xffff;
1558
1559                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1560                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1561         }
1562
1563         /* Make sure that interrupts are indeed enabled from here on */
1564         mmiowb();
1565 }
1566
1567 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1568 {
1569         u32 val;
1570         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1571         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1572         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1573
1574         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1575
1576         if (msix) {
1577                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1578                          IGU_PF_CONF_SINGLE_ISR_EN);
1579                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1580                         IGU_PF_CONF_ATTN_BIT_EN);
1581
1582                 if (single_msix)
1583                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1584         } else if (msi) {
1585                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1586                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1587                         IGU_PF_CONF_ATTN_BIT_EN |
1588                         IGU_PF_CONF_SINGLE_ISR_EN);
1589         } else {
1590                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1591                 val |= (IGU_PF_CONF_INT_LINE_EN |
1592                         IGU_PF_CONF_ATTN_BIT_EN |
1593                         IGU_PF_CONF_SINGLE_ISR_EN);
1594         }
1595
1596         /* Clean previous status - need to configure igu prior to ack*/
1597         if ((!msix) || single_msix) {
1598                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1599                 bnx2x_ack_int(bp);
1600         }
1601
1602         val |= IGU_PF_CONF_FUNC_EN;
1603
1604         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1605            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1606
1607         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1608
1609         if (val & IGU_PF_CONF_INT_LINE_EN)
1610                 pci_intx(bp->pdev, true);
1611
1612         barrier();
1613
1614         /* init leading/trailing edge */
1615         if (IS_MF(bp)) {
1616                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1617                 if (bp->port.pmf)
1618                         /* enable nig and gpio3 attention */
1619                         val |= 0x1100;
1620         } else
1621                 val = 0xffff;
1622
1623         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1624         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1625
1626         /* Make sure that interrupts are indeed enabled from here on */
1627         mmiowb();
1628 }
1629
1630 void bnx2x_int_enable(struct bnx2x *bp)
1631 {
1632         if (bp->common.int_block == INT_BLOCK_HC)
1633                 bnx2x_hc_int_enable(bp);
1634         else
1635                 bnx2x_igu_int_enable(bp);
1636 }
1637
1638 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1639 {
1640         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1641         int i, offset;
1642
1643         if (disable_hw)
1644                 /* prevent the HW from sending interrupts */
1645                 bnx2x_int_disable(bp);
1646
1647         /* make sure all ISRs are done */
1648         if (msix) {
1649                 synchronize_irq(bp->msix_table[0].vector);
1650                 offset = 1;
1651                 if (CNIC_SUPPORT(bp))
1652                         offset++;
1653                 for_each_eth_queue(bp, i)
1654                         synchronize_irq(bp->msix_table[offset++].vector);
1655         } else
1656                 synchronize_irq(bp->pdev->irq);
1657
1658         /* make sure sp_task is not running */
1659         cancel_delayed_work(&bp->sp_task);
1660         cancel_delayed_work(&bp->period_task);
1661         flush_workqueue(bnx2x_wq);
1662 }
1663
1664 /* fast path */
1665
1666 /*
1667  * General service functions
1668  */
1669
1670 /* Return true if succeeded to acquire the lock */
1671 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1672 {
1673         u32 lock_status;
1674         u32 resource_bit = (1 << resource);
1675         int func = BP_FUNC(bp);
1676         u32 hw_lock_control_reg;
1677
1678         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1679            "Trying to take a lock on resource %d\n", resource);
1680
1681         /* Validating that the resource is within range */
1682         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1683                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1684                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1685                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1686                 return false;
1687         }
1688
1689         if (func <= 5)
1690                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1691         else
1692                 hw_lock_control_reg =
1693                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1694
1695         /* Try to acquire the lock */
1696         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1697         lock_status = REG_RD(bp, hw_lock_control_reg);
1698         if (lock_status & resource_bit)
1699                 return true;
1700
1701         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1702            "Failed to get a lock on resource %d\n", resource);
1703         return false;
1704 }
1705
1706 /**
1707  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1708  *
1709  * @bp: driver handle
1710  *
1711  * Returns the recovery leader resource id according to the engine this function
1712  * belongs to. Currently only only 2 engines is supported.
1713  */
1714 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1715 {
1716         if (BP_PATH(bp))
1717                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1718         else
1719                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1720 }
1721
1722 /**
1723  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1724  *
1725  * @bp: driver handle
1726  *
1727  * Tries to acquire a leader lock for current engine.
1728  */
1729 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1730 {
1731         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1732 }
1733
1734 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1735
1736 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1737 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1738 {
1739         /* Set the interrupt occurred bit for the sp-task to recognize it
1740          * must ack the interrupt and transition according to the IGU
1741          * state machine.
1742          */
1743         atomic_set(&bp->interrupt_occurred, 1);
1744
1745         /* The sp_task must execute only after this bit
1746          * is set, otherwise we will get out of sync and miss all
1747          * further interrupts. Hence, the barrier.
1748          */
1749         smp_wmb();
1750
1751         /* schedule sp_task to workqueue */
1752         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1753 }
1754
1755 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1756 {
1757         struct bnx2x *bp = fp->bp;
1758         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1759         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1760         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1761         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1762
1763         DP(BNX2X_MSG_SP,
1764            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1765            fp->index, cid, command, bp->state,
1766            rr_cqe->ramrod_cqe.ramrod_type);
1767
1768         /* If cid is within VF range, replace the slowpath object with the
1769          * one corresponding to this VF
1770          */
1771         if (cid >= BNX2X_FIRST_VF_CID  &&
1772             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1773                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1774
1775         switch (command) {
1776         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1777                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1778                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1779                 break;
1780
1781         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1782                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1783                 drv_cmd = BNX2X_Q_CMD_SETUP;
1784                 break;
1785
1786         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1787                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1788                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1789                 break;
1790
1791         case (RAMROD_CMD_ID_ETH_HALT):
1792                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1793                 drv_cmd = BNX2X_Q_CMD_HALT;
1794                 break;
1795
1796         case (RAMROD_CMD_ID_ETH_TERMINATE):
1797                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1798                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1799                 break;
1800
1801         case (RAMROD_CMD_ID_ETH_EMPTY):
1802                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1803                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1804                 break;
1805
1806         default:
1807                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1808                           command, fp->index);
1809                 return;
1810         }
1811
1812         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1813             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1814                 /* q_obj->complete_cmd() failure means that this was
1815                  * an unexpected completion.
1816                  *
1817                  * In this case we don't want to increase the bp->spq_left
1818                  * because apparently we haven't sent this command the first
1819                  * place.
1820                  */
1821 #ifdef BNX2X_STOP_ON_ERROR
1822                 bnx2x_panic();
1823 #else
1824                 return;
1825 #endif
1826         /* SRIOV: reschedule any 'in_progress' operations */
1827         bnx2x_iov_sp_event(bp, cid, true);
1828
1829         smp_mb__before_atomic_inc();
1830         atomic_inc(&bp->cq_spq_left);
1831         /* push the change in bp->spq_left and towards the memory */
1832         smp_mb__after_atomic_inc();
1833
1834         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1835
1836         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1837             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1838                 /* if Q update ramrod is completed for last Q in AFEX vif set
1839                  * flow, then ACK MCP at the end
1840                  *
1841                  * mark pending ACK to MCP bit.
1842                  * prevent case that both bits are cleared.
1843                  * At the end of load/unload driver checks that
1844                  * sp_state is cleared, and this order prevents
1845                  * races
1846                  */
1847                 smp_mb__before_clear_bit();
1848                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1849                 wmb();
1850                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1851                 smp_mb__after_clear_bit();
1852
1853                 /* schedule the sp task as mcp ack is required */
1854                 bnx2x_schedule_sp_task(bp);
1855         }
1856
1857         return;
1858 }
1859
1860 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1861 {
1862         struct bnx2x *bp = netdev_priv(dev_instance);
1863         u16 status = bnx2x_ack_int(bp);
1864         u16 mask;
1865         int i;
1866         u8 cos;
1867
1868         /* Return here if interrupt is shared and it's not for us */
1869         if (unlikely(status == 0)) {
1870                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1871                 return IRQ_NONE;
1872         }
1873         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1874
1875 #ifdef BNX2X_STOP_ON_ERROR
1876         if (unlikely(bp->panic))
1877                 return IRQ_HANDLED;
1878 #endif
1879
1880         for_each_eth_queue(bp, i) {
1881                 struct bnx2x_fastpath *fp = &bp->fp[i];
1882
1883                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1884                 if (status & mask) {
1885                         /* Handle Rx or Tx according to SB id */
1886                         for_each_cos_in_tx_queue(fp, cos)
1887                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1888                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1889                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1890                         status &= ~mask;
1891                 }
1892         }
1893
1894         if (CNIC_SUPPORT(bp)) {
1895                 mask = 0x2;
1896                 if (status & (mask | 0x1)) {
1897                         struct cnic_ops *c_ops = NULL;
1898
1899                         rcu_read_lock();
1900                         c_ops = rcu_dereference(bp->cnic_ops);
1901                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1902                                       CNIC_DRV_STATE_HANDLES_IRQ))
1903                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1904                         rcu_read_unlock();
1905
1906                         status &= ~mask;
1907                 }
1908         }
1909
1910         if (unlikely(status & 0x1)) {
1911
1912                 /* schedule sp task to perform default status block work, ack
1913                  * attentions and enable interrupts.
1914                  */
1915                 bnx2x_schedule_sp_task(bp);
1916
1917                 status &= ~0x1;
1918                 if (!status)
1919                         return IRQ_HANDLED;
1920         }
1921
1922         if (unlikely(status))
1923                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1924                    status);
1925
1926         return IRQ_HANDLED;
1927 }
1928
1929 /* Link */
1930
1931 /*
1932  * General service functions
1933  */
1934
1935 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1936 {
1937         u32 lock_status;
1938         u32 resource_bit = (1 << resource);
1939         int func = BP_FUNC(bp);
1940         u32 hw_lock_control_reg;
1941         int cnt;
1942
1943         /* Validating that the resource is within range */
1944         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1945                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1946                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1947                 return -EINVAL;
1948         }
1949
1950         if (func <= 5) {
1951                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1952         } else {
1953                 hw_lock_control_reg =
1954                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1955         }
1956
1957         /* Validating that the resource is not already taken */
1958         lock_status = REG_RD(bp, hw_lock_control_reg);
1959         if (lock_status & resource_bit) {
1960                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1961                    lock_status, resource_bit);
1962                 return -EEXIST;
1963         }
1964
1965         /* Try for 5 second every 5ms */
1966         for (cnt = 0; cnt < 1000; cnt++) {
1967                 /* Try to acquire the lock */
1968                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1969                 lock_status = REG_RD(bp, hw_lock_control_reg);
1970                 if (lock_status & resource_bit)
1971                         return 0;
1972
1973                 usleep_range(5000, 10000);
1974         }
1975         BNX2X_ERR("Timeout\n");
1976         return -EAGAIN;
1977 }
1978
1979 int bnx2x_release_leader_lock(struct bnx2x *bp)
1980 {
1981         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1982 }
1983
1984 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1985 {
1986         u32 lock_status;
1987         u32 resource_bit = (1 << resource);
1988         int func = BP_FUNC(bp);
1989         u32 hw_lock_control_reg;
1990
1991         /* Validating that the resource is within range */
1992         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1993                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1994                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1995                 return -EINVAL;
1996         }
1997
1998         if (func <= 5) {
1999                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2000         } else {
2001                 hw_lock_control_reg =
2002                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2003         }
2004
2005         /* Validating that the resource is currently taken */
2006         lock_status = REG_RD(bp, hw_lock_control_reg);
2007         if (!(lock_status & resource_bit)) {
2008                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2009                           lock_status, resource_bit);
2010                 return -EFAULT;
2011         }
2012
2013         REG_WR(bp, hw_lock_control_reg, resource_bit);
2014         return 0;
2015 }
2016
2017 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2018 {
2019         /* The GPIO should be swapped if swap register is set and active */
2020         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2021                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2022         int gpio_shift = gpio_num +
2023                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2024         u32 gpio_mask = (1 << gpio_shift);
2025         u32 gpio_reg;
2026         int value;
2027
2028         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2029                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2030                 return -EINVAL;
2031         }
2032
2033         /* read GPIO value */
2034         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2035
2036         /* get the requested pin value */
2037         if ((gpio_reg & gpio_mask) == gpio_mask)
2038                 value = 1;
2039         else
2040                 value = 0;
2041
2042         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2043
2044         return value;
2045 }
2046
2047 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2048 {
2049         /* The GPIO should be swapped if swap register is set and active */
2050         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2051                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2052         int gpio_shift = gpio_num +
2053                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2054         u32 gpio_mask = (1 << gpio_shift);
2055         u32 gpio_reg;
2056
2057         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2058                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2059                 return -EINVAL;
2060         }
2061
2062         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2063         /* read GPIO and mask except the float bits */
2064         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2065
2066         switch (mode) {
2067         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2068                 DP(NETIF_MSG_LINK,
2069                    "Set GPIO %d (shift %d) -> output low\n",
2070                    gpio_num, gpio_shift);
2071                 /* clear FLOAT and set CLR */
2072                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2073                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2074                 break;
2075
2076         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2077                 DP(NETIF_MSG_LINK,
2078                    "Set GPIO %d (shift %d) -> output high\n",
2079                    gpio_num, gpio_shift);
2080                 /* clear FLOAT and set SET */
2081                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2082                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2083                 break;
2084
2085         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2086                 DP(NETIF_MSG_LINK,
2087                    "Set GPIO %d (shift %d) -> input\n",
2088                    gpio_num, gpio_shift);
2089                 /* set FLOAT */
2090                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2091                 break;
2092
2093         default:
2094                 break;
2095         }
2096
2097         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2098         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2099
2100         return 0;
2101 }
2102
2103 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2104 {
2105         u32 gpio_reg = 0;
2106         int rc = 0;
2107
2108         /* Any port swapping should be handled by caller. */
2109
2110         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2111         /* read GPIO and mask except the float bits */
2112         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2113         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2114         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2115         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2116
2117         switch (mode) {
2118         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2119                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2120                 /* set CLR */
2121                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2122                 break;
2123
2124         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2125                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2126                 /* set SET */
2127                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2128                 break;
2129
2130         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2131                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2132                 /* set FLOAT */
2133                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2138                 rc = -EINVAL;
2139                 break;
2140         }
2141
2142         if (rc == 0)
2143                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2144
2145         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2146
2147         return rc;
2148 }
2149
2150 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2151 {
2152         /* The GPIO should be swapped if swap register is set and active */
2153         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2154                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2155         int gpio_shift = gpio_num +
2156                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2157         u32 gpio_mask = (1 << gpio_shift);
2158         u32 gpio_reg;
2159
2160         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2161                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2162                 return -EINVAL;
2163         }
2164
2165         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2166         /* read GPIO int */
2167         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2168
2169         switch (mode) {
2170         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2171                 DP(NETIF_MSG_LINK,
2172                    "Clear GPIO INT %d (shift %d) -> output low\n",
2173                    gpio_num, gpio_shift);
2174                 /* clear SET and set CLR */
2175                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2176                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2177                 break;
2178
2179         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2180                 DP(NETIF_MSG_LINK,
2181                    "Set GPIO INT %d (shift %d) -> output high\n",
2182                    gpio_num, gpio_shift);
2183                 /* clear CLR and set SET */
2184                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2185                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2186                 break;
2187
2188         default:
2189                 break;
2190         }
2191
2192         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2193         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2194
2195         return 0;
2196 }
2197
2198 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2199 {
2200         u32 spio_reg;
2201
2202         /* Only 2 SPIOs are configurable */
2203         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2204                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2209         /* read SPIO and mask except the float bits */
2210         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2211
2212         switch (mode) {
2213         case MISC_SPIO_OUTPUT_LOW:
2214                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2215                 /* clear FLOAT and set CLR */
2216                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2217                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2218                 break;
2219
2220         case MISC_SPIO_OUTPUT_HIGH:
2221                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2222                 /* clear FLOAT and set SET */
2223                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2224                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2225                 break;
2226
2227         case MISC_SPIO_INPUT_HI_Z:
2228                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2229                 /* set FLOAT */
2230                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2231                 break;
2232
2233         default:
2234                 break;
2235         }
2236
2237         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2238         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2239
2240         return 0;
2241 }
2242
2243 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2244 {
2245         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2246         switch (bp->link_vars.ieee_fc &
2247                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2248         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2249                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2250                                                    ADVERTISED_Pause);
2251                 break;
2252
2253         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2254                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2255                                                   ADVERTISED_Pause);
2256                 break;
2257
2258         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2259                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2260                 break;
2261
2262         default:
2263                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2264                                                    ADVERTISED_Pause);
2265                 break;
2266         }
2267 }
2268
2269 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2270 {
2271         /* Initialize link parameters structure variables
2272          * It is recommended to turn off RX FC for jumbo frames
2273          *  for better performance
2274          */
2275         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2276                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2277         else
2278                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2279 }
2280
2281 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2282 {
2283         u32 pause_enabled = 0;
2284
2285         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2286                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2287                         pause_enabled = 1;
2288
2289                 REG_WR(bp, BAR_USTRORM_INTMEM +
2290                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2291                        pause_enabled);
2292         }
2293
2294         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2295            pause_enabled ? "enabled" : "disabled");
2296 }
2297
2298 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2299 {
2300         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2301         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2302
2303         if (!BP_NOMCP(bp)) {
2304                 bnx2x_set_requested_fc(bp);
2305                 bnx2x_acquire_phy_lock(bp);
2306
2307                 if (load_mode == LOAD_DIAG) {
2308                         struct link_params *lp = &bp->link_params;
2309                         lp->loopback_mode = LOOPBACK_XGXS;
2310                         /* do PHY loopback at 10G speed, if possible */
2311                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2312                                 if (lp->speed_cap_mask[cfx_idx] &
2313                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2314                                         lp->req_line_speed[cfx_idx] =
2315                                         SPEED_10000;
2316                                 else
2317                                         lp->req_line_speed[cfx_idx] =
2318                                         SPEED_1000;
2319                         }
2320                 }
2321
2322                 if (load_mode == LOAD_LOOPBACK_EXT) {
2323                         struct link_params *lp = &bp->link_params;
2324                         lp->loopback_mode = LOOPBACK_EXT;
2325                 }
2326
2327                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2328
2329                 bnx2x_release_phy_lock(bp);
2330
2331                 bnx2x_init_dropless_fc(bp);
2332
2333                 bnx2x_calc_fc_adv(bp);
2334
2335                 if (bp->link_vars.link_up) {
2336                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2337                         bnx2x_link_report(bp);
2338                 }
2339                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2340                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2341                 return rc;
2342         }
2343         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2344         return -EINVAL;
2345 }
2346
2347 void bnx2x_link_set(struct bnx2x *bp)
2348 {
2349         if (!BP_NOMCP(bp)) {
2350                 bnx2x_acquire_phy_lock(bp);
2351                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2352                 bnx2x_release_phy_lock(bp);
2353
2354                 bnx2x_init_dropless_fc(bp);
2355
2356                 bnx2x_calc_fc_adv(bp);
2357         } else
2358                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2359 }
2360
2361 static void bnx2x__link_reset(struct bnx2x *bp)
2362 {
2363         if (!BP_NOMCP(bp)) {
2364                 bnx2x_acquire_phy_lock(bp);
2365                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2366                 bnx2x_release_phy_lock(bp);
2367         } else
2368                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2369 }
2370
2371 void bnx2x_force_link_reset(struct bnx2x *bp)
2372 {
2373         bnx2x_acquire_phy_lock(bp);
2374         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2375         bnx2x_release_phy_lock(bp);
2376 }
2377
2378 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2379 {
2380         u8 rc = 0;
2381
2382         if (!BP_NOMCP(bp)) {
2383                 bnx2x_acquire_phy_lock(bp);
2384                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2385                                      is_serdes);
2386                 bnx2x_release_phy_lock(bp);
2387         } else
2388                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2389
2390         return rc;
2391 }
2392
2393 /* Calculates the sum of vn_min_rates.
2394    It's needed for further normalizing of the min_rates.
2395    Returns:
2396      sum of vn_min_rates.
2397        or
2398      0 - if all the min_rates are 0.
2399      In the later case fairness algorithm should be deactivated.
2400      If not all min_rates are zero then those that are zeroes will be set to 1.
2401  */
2402 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2403                                       struct cmng_init_input *input)
2404 {
2405         int all_zero = 1;
2406         int vn;
2407
2408         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2409                 u32 vn_cfg = bp->mf_config[vn];
2410                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2411                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2412
2413                 /* Skip hidden vns */
2414                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2415                         vn_min_rate = 0;
2416                 /* If min rate is zero - set it to 1 */
2417                 else if (!vn_min_rate)
2418                         vn_min_rate = DEF_MIN_RATE;
2419                 else
2420                         all_zero = 0;
2421
2422                 input->vnic_min_rate[vn] = vn_min_rate;
2423         }
2424
2425         /* if ETS or all min rates are zeros - disable fairness */
2426         if (BNX2X_IS_ETS_ENABLED(bp)) {
2427                 input->flags.cmng_enables &=
2428                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2429                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2430         } else if (all_zero) {
2431                 input->flags.cmng_enables &=
2432                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2433                 DP(NETIF_MSG_IFUP,
2434                    "All MIN values are zeroes fairness will be disabled\n");
2435         } else
2436                 input->flags.cmng_enables |=
2437                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2438 }
2439
2440 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2441                                     struct cmng_init_input *input)
2442 {
2443         u16 vn_max_rate;
2444         u32 vn_cfg = bp->mf_config[vn];
2445
2446         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2447                 vn_max_rate = 0;
2448         else {
2449                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2450
2451                 if (IS_MF_SI(bp)) {
2452                         /* maxCfg in percents of linkspeed */
2453                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2454                 } else /* SD modes */
2455                         /* maxCfg is absolute in 100Mb units */
2456                         vn_max_rate = maxCfg * 100;
2457         }
2458
2459         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2460
2461         input->vnic_max_rate[vn] = vn_max_rate;
2462 }
2463
2464 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2465 {
2466         if (CHIP_REV_IS_SLOW(bp))
2467                 return CMNG_FNS_NONE;
2468         if (IS_MF(bp))
2469                 return CMNG_FNS_MINMAX;
2470
2471         return CMNG_FNS_NONE;
2472 }
2473
2474 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2475 {
2476         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2477
2478         if (BP_NOMCP(bp))
2479                 return; /* what should be the default value in this case */
2480
2481         /* For 2 port configuration the absolute function number formula
2482          * is:
2483          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2484          *
2485          *      and there are 4 functions per port
2486          *
2487          * For 4 port configuration it is
2488          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2489          *
2490          *      and there are 2 functions per port
2491          */
2492         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2493                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2494
2495                 if (func >= E1H_FUNC_MAX)
2496                         break;
2497
2498                 bp->mf_config[vn] =
2499                         MF_CFG_RD(bp, func_mf_config[func].config);
2500         }
2501         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2502                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2503                 bp->flags |= MF_FUNC_DIS;
2504         } else {
2505                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2506                 bp->flags &= ~MF_FUNC_DIS;
2507         }
2508 }
2509
2510 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2511 {
2512         struct cmng_init_input input;
2513         memset(&input, 0, sizeof(struct cmng_init_input));
2514
2515         input.port_rate = bp->link_vars.line_speed;
2516
2517         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2518                 int vn;
2519
2520                 /* read mf conf from shmem */
2521                 if (read_cfg)
2522                         bnx2x_read_mf_cfg(bp);
2523
2524                 /* vn_weight_sum and enable fairness if not 0 */
2525                 bnx2x_calc_vn_min(bp, &input);
2526
2527                 /* calculate and set min-max rate for each vn */
2528                 if (bp->port.pmf)
2529                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2530                                 bnx2x_calc_vn_max(bp, vn, &input);
2531
2532                 /* always enable rate shaping and fairness */
2533                 input.flags.cmng_enables |=
2534                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2535
2536                 bnx2x_init_cmng(&input, &bp->cmng);
2537                 return;
2538         }
2539
2540         /* rate shaping and fairness are disabled */
2541         DP(NETIF_MSG_IFUP,
2542            "rate shaping and fairness are disabled\n");
2543 }
2544
2545 static void storm_memset_cmng(struct bnx2x *bp,
2546                               struct cmng_init *cmng,
2547                               u8 port)
2548 {
2549         int vn;
2550         size_t size = sizeof(struct cmng_struct_per_port);
2551
2552         u32 addr = BAR_XSTRORM_INTMEM +
2553                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2554
2555         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2556
2557         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2558                 int func = func_by_vn(bp, vn);
2559
2560                 addr = BAR_XSTRORM_INTMEM +
2561                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2562                 size = sizeof(struct rate_shaping_vars_per_vn);
2563                 __storm_memset_struct(bp, addr, size,
2564                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2565
2566                 addr = BAR_XSTRORM_INTMEM +
2567                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2568                 size = sizeof(struct fairness_vars_per_vn);
2569                 __storm_memset_struct(bp, addr, size,
2570                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2571         }
2572 }
2573
2574 /* init cmng mode in HW according to local configuration */
2575 void bnx2x_set_local_cmng(struct bnx2x *bp)
2576 {
2577         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2578
2579         if (cmng_fns != CMNG_FNS_NONE) {
2580                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2581                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2582         } else {
2583                 /* rate shaping and fairness are disabled */
2584                 DP(NETIF_MSG_IFUP,
2585                    "single function mode without fairness\n");
2586         }
2587 }
2588
2589 /* This function is called upon link interrupt */
2590 static void bnx2x_link_attn(struct bnx2x *bp)
2591 {
2592         /* Make sure that we are synced with the current statistics */
2593         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2594
2595         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2596
2597         bnx2x_init_dropless_fc(bp);
2598
2599         if (bp->link_vars.link_up) {
2600
2601                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2602                         struct host_port_stats *pstats;
2603
2604                         pstats = bnx2x_sp(bp, port_stats);
2605                         /* reset old mac stats */
2606                         memset(&(pstats->mac_stx[0]), 0,
2607                                sizeof(struct mac_stx));
2608                 }
2609                 if (bp->state == BNX2X_STATE_OPEN)
2610                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2611         }
2612
2613         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2614                 bnx2x_set_local_cmng(bp);
2615
2616         __bnx2x_link_report(bp);
2617
2618         if (IS_MF(bp))
2619                 bnx2x_link_sync_notify(bp);
2620 }
2621
2622 void bnx2x__link_status_update(struct bnx2x *bp)
2623 {
2624         if (bp->state != BNX2X_STATE_OPEN)
2625                 return;
2626
2627         /* read updated dcb configuration */
2628         if (IS_PF(bp)) {
2629                 bnx2x_dcbx_pmf_update(bp);
2630                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2631                 if (bp->link_vars.link_up)
2632                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2633                 else
2634                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2635                         /* indicate link status */
2636                 bnx2x_link_report(bp);
2637
2638         } else { /* VF */
2639                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2640                                           SUPPORTED_10baseT_Full |
2641                                           SUPPORTED_100baseT_Half |
2642                                           SUPPORTED_100baseT_Full |
2643                                           SUPPORTED_1000baseT_Full |
2644                                           SUPPORTED_2500baseX_Full |
2645                                           SUPPORTED_10000baseT_Full |
2646                                           SUPPORTED_TP |
2647                                           SUPPORTED_FIBRE |
2648                                           SUPPORTED_Autoneg |
2649                                           SUPPORTED_Pause |
2650                                           SUPPORTED_Asym_Pause);
2651                 bp->port.advertising[0] = bp->port.supported[0];
2652
2653                 bp->link_params.bp = bp;
2654                 bp->link_params.port = BP_PORT(bp);
2655                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2656                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2657                 bp->link_params.req_line_speed[0] = SPEED_10000;
2658                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2659                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2660                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2661                 bp->link_vars.line_speed = SPEED_10000;
2662                 bp->link_vars.link_status =
2663                         (LINK_STATUS_LINK_UP |
2664                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2665                 bp->link_vars.link_up = 1;
2666                 bp->link_vars.duplex = DUPLEX_FULL;
2667                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2668                 __bnx2x_link_report(bp);
2669                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2670         }
2671 }
2672
2673 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2674                                   u16 vlan_val, u8 allowed_prio)
2675 {
2676         struct bnx2x_func_state_params func_params = {NULL};
2677         struct bnx2x_func_afex_update_params *f_update_params =
2678                 &func_params.params.afex_update;
2679
2680         func_params.f_obj = &bp->func_obj;
2681         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2682
2683         /* no need to wait for RAMROD completion, so don't
2684          * set RAMROD_COMP_WAIT flag
2685          */
2686
2687         f_update_params->vif_id = vifid;
2688         f_update_params->afex_default_vlan = vlan_val;
2689         f_update_params->allowed_priorities = allowed_prio;
2690
2691         /* if ramrod can not be sent, response to MCP immediately */
2692         if (bnx2x_func_state_change(bp, &func_params) < 0)
2693                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2694
2695         return 0;
2696 }
2697
2698 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2699                                           u16 vif_index, u8 func_bit_map)
2700 {
2701         struct bnx2x_func_state_params func_params = {NULL};
2702         struct bnx2x_func_afex_viflists_params *update_params =
2703                 &func_params.params.afex_viflists;
2704         int rc;
2705         u32 drv_msg_code;
2706
2707         /* validate only LIST_SET and LIST_GET are received from switch */
2708         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2709                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2710                           cmd_type);
2711
2712         func_params.f_obj = &bp->func_obj;
2713         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2714
2715         /* set parameters according to cmd_type */
2716         update_params->afex_vif_list_command = cmd_type;
2717         update_params->vif_list_index = vif_index;
2718         update_params->func_bit_map =
2719                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2720         update_params->func_to_clear = 0;
2721         drv_msg_code =
2722                 (cmd_type == VIF_LIST_RULE_GET) ?
2723                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2724                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2725
2726         /* if ramrod can not be sent, respond to MCP immediately for
2727          * SET and GET requests (other are not triggered from MCP)
2728          */
2729         rc = bnx2x_func_state_change(bp, &func_params);
2730         if (rc < 0)
2731                 bnx2x_fw_command(bp, drv_msg_code, 0);
2732
2733         return 0;
2734 }
2735
2736 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2737 {
2738         struct afex_stats afex_stats;
2739         u32 func = BP_ABS_FUNC(bp);
2740         u32 mf_config;
2741         u16 vlan_val;
2742         u32 vlan_prio;
2743         u16 vif_id;
2744         u8 allowed_prio;
2745         u8 vlan_mode;
2746         u32 addr_to_write, vifid, addrs, stats_type, i;
2747
2748         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2749                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2750                 DP(BNX2X_MSG_MCP,
2751                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2752                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2753         }
2754
2755         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2756                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2757                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2758                 DP(BNX2X_MSG_MCP,
2759                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2760                    vifid, addrs);
2761                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2762                                                addrs);
2763         }
2764
2765         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2766                 addr_to_write = SHMEM2_RD(bp,
2767                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2768                 stats_type = SHMEM2_RD(bp,
2769                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2770
2771                 DP(BNX2X_MSG_MCP,
2772                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2773                    addr_to_write);
2774
2775                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2776
2777                 /* write response to scratchpad, for MCP */
2778                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2779                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2780                                *(((u32 *)(&afex_stats))+i));
2781
2782                 /* send ack message to MCP */
2783                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2784         }
2785
2786         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2787                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2788                 bp->mf_config[BP_VN(bp)] = mf_config;
2789                 DP(BNX2X_MSG_MCP,
2790                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2791                    mf_config);
2792
2793                 /* if VIF_SET is "enabled" */
2794                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2795                         /* set rate limit directly to internal RAM */
2796                         struct cmng_init_input cmng_input;
2797                         struct rate_shaping_vars_per_vn m_rs_vn;
2798                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2799                         u32 addr = BAR_XSTRORM_INTMEM +
2800                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2801
2802                         bp->mf_config[BP_VN(bp)] = mf_config;
2803
2804                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2805                         m_rs_vn.vn_counter.rate =
2806                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2807                         m_rs_vn.vn_counter.quota =
2808                                 (m_rs_vn.vn_counter.rate *
2809                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2810
2811                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2812
2813                         /* read relevant values from mf_cfg struct in shmem */
2814                         vif_id =
2815                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2816                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2817                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2818                         vlan_val =
2819                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2820                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2821                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2822                         vlan_prio = (mf_config &
2823                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2824                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2825                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2826                         vlan_mode =
2827                                 (MF_CFG_RD(bp,
2828                                            func_mf_config[func].afex_config) &
2829                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2830                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2831                         allowed_prio =
2832                                 (MF_CFG_RD(bp,
2833                                            func_mf_config[func].afex_config) &
2834                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2835                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2836
2837                         /* send ramrod to FW, return in case of failure */
2838                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2839                                                    allowed_prio))
2840                                 return;
2841
2842                         bp->afex_def_vlan_tag = vlan_val;
2843                         bp->afex_vlan_mode = vlan_mode;
2844                 } else {
2845                         /* notify link down because BP->flags is disabled */
2846                         bnx2x_link_report(bp);
2847
2848                         /* send INVALID VIF ramrod to FW */
2849                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2850
2851                         /* Reset the default afex VLAN */
2852                         bp->afex_def_vlan_tag = -1;
2853                 }
2854         }
2855 }
2856
2857 static void bnx2x_pmf_update(struct bnx2x *bp)
2858 {
2859         int port = BP_PORT(bp);
2860         u32 val;
2861
2862         bp->port.pmf = 1;
2863         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2864
2865         /*
2866          * We need the mb() to ensure the ordering between the writing to
2867          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2868          */
2869         smp_mb();
2870
2871         /* queue a periodic task */
2872         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2873
2874         bnx2x_dcbx_pmf_update(bp);
2875
2876         /* enable nig attention */
2877         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2878         if (bp->common.int_block == INT_BLOCK_HC) {
2879                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2880                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2881         } else if (!CHIP_IS_E1x(bp)) {
2882                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2883                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2884         }
2885
2886         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2887 }
2888
2889 /* end of Link */
2890
2891 /* slow path */
2892
2893 /*
2894  * General service functions
2895  */
2896
2897 /* send the MCP a request, block until there is a reply */
2898 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2899 {
2900         int mb_idx = BP_FW_MB_IDX(bp);
2901         u32 seq;
2902         u32 rc = 0;
2903         u32 cnt = 1;
2904         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2905
2906         mutex_lock(&bp->fw_mb_mutex);
2907         seq = ++bp->fw_seq;
2908         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2909         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2910
2911         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2912                         (command | seq), param);
2913
2914         do {
2915                 /* let the FW do it's magic ... */
2916                 msleep(delay);
2917
2918                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2919
2920                 /* Give the FW up to 5 second (500*10ms) */
2921         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2922
2923         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2924            cnt*delay, rc, seq);
2925
2926         /* is this a reply to our command? */
2927         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2928                 rc &= FW_MSG_CODE_MASK;
2929         else {
2930                 /* FW BUG! */
2931                 BNX2X_ERR("FW failed to respond!\n");
2932                 bnx2x_fw_dump(bp);
2933                 rc = 0;
2934         }
2935         mutex_unlock(&bp->fw_mb_mutex);
2936
2937         return rc;
2938 }
2939
2940 static void storm_memset_func_cfg(struct bnx2x *bp,
2941                                  struct tstorm_eth_function_common_config *tcfg,
2942                                  u16 abs_fid)
2943 {
2944         size_t size = sizeof(struct tstorm_eth_function_common_config);
2945
2946         u32 addr = BAR_TSTRORM_INTMEM +
2947                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2948
2949         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2950 }
2951
2952 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2953 {
2954         if (CHIP_IS_E1x(bp)) {
2955                 struct tstorm_eth_function_common_config tcfg = {0};
2956
2957                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2958         }
2959
2960         /* Enable the function in the FW */
2961         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2962         storm_memset_func_en(bp, p->func_id, 1);
2963
2964         /* spq */
2965         if (p->func_flgs & FUNC_FLG_SPQ) {
2966                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2967                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2968                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2969         }
2970 }
2971
2972 /**
2973  * bnx2x_get_common_flags - Return common flags
2974  *
2975  * @bp          device handle
2976  * @fp          queue handle
2977  * @zero_stats  TRUE if statistics zeroing is needed
2978  *
2979  * Return the flags that are common for the Tx-only and not normal connections.
2980  */
2981 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2982                                             struct bnx2x_fastpath *fp,
2983                                             bool zero_stats)
2984 {
2985         unsigned long flags = 0;
2986
2987         /* PF driver will always initialize the Queue to an ACTIVE state */
2988         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2989
2990         /* tx only connections collect statistics (on the same index as the
2991          * parent connection). The statistics are zeroed when the parent
2992          * connection is initialized.
2993          */
2994
2995         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2996         if (zero_stats)
2997                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2998
2999         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3000         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3001
3002 #ifdef BNX2X_STOP_ON_ERROR
3003         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3004 #endif
3005
3006         return flags;
3007 }
3008
3009 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3010                                        struct bnx2x_fastpath *fp,
3011                                        bool leading)
3012 {
3013         unsigned long flags = 0;
3014
3015         /* calculate other queue flags */
3016         if (IS_MF_SD(bp))
3017                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3018
3019         if (IS_FCOE_FP(fp)) {
3020                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3021                 /* For FCoE - force usage of default priority (for afex) */
3022                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3023         }
3024
3025         if (!fp->disable_tpa) {
3026                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3027                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3028                 if (fp->mode == TPA_MODE_GRO)
3029                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3030         }
3031
3032         if (leading) {
3033                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3034                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3035         }
3036
3037         /* Always set HW VLAN stripping */
3038         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3039
3040         /* configure silent vlan removal */
3041         if (IS_MF_AFEX(bp))
3042                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3043
3044         return flags | bnx2x_get_common_flags(bp, fp, true);
3045 }
3046
3047 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3048         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3049         u8 cos)
3050 {
3051         gen_init->stat_id = bnx2x_stats_id(fp);
3052         gen_init->spcl_id = fp->cl_id;
3053
3054         /* Always use mini-jumbo MTU for FCoE L2 ring */
3055         if (IS_FCOE_FP(fp))
3056                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3057         else
3058                 gen_init->mtu = bp->dev->mtu;
3059
3060         gen_init->cos = cos;
3061 }
3062
3063 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3064         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3065         struct bnx2x_rxq_setup_params *rxq_init)
3066 {
3067         u8 max_sge = 0;
3068         u16 sge_sz = 0;
3069         u16 tpa_agg_size = 0;
3070
3071         if (!fp->disable_tpa) {
3072                 pause->sge_th_lo = SGE_TH_LO(bp);
3073                 pause->sge_th_hi = SGE_TH_HI(bp);
3074
3075                 /* validate SGE ring has enough to cross high threshold */
3076                 WARN_ON(bp->dropless_fc &&
3077                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3078                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3079
3080                 tpa_agg_size = TPA_AGG_SIZE;
3081                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3082                         SGE_PAGE_SHIFT;
3083                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3084                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3085                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3086         }
3087
3088         /* pause - not for e1 */
3089         if (!CHIP_IS_E1(bp)) {
3090                 pause->bd_th_lo = BD_TH_LO(bp);
3091                 pause->bd_th_hi = BD_TH_HI(bp);
3092
3093                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3094                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3095                 /*
3096                  * validate that rings have enough entries to cross
3097                  * high thresholds
3098                  */
3099                 WARN_ON(bp->dropless_fc &&
3100                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3101                                 bp->rx_ring_size);
3102                 WARN_ON(bp->dropless_fc &&
3103                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3104                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3105
3106                 pause->pri_map = 1;
3107         }
3108
3109         /* rxq setup */
3110         rxq_init->dscr_map = fp->rx_desc_mapping;
3111         rxq_init->sge_map = fp->rx_sge_mapping;
3112         rxq_init->rcq_map = fp->rx_comp_mapping;
3113         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3114
3115         /* This should be a maximum number of data bytes that may be
3116          * placed on the BD (not including paddings).
3117          */
3118         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3119                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3120
3121         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3122         rxq_init->tpa_agg_sz = tpa_agg_size;
3123         rxq_init->sge_buf_sz = sge_sz;
3124         rxq_init->max_sges_pkt = max_sge;
3125         rxq_init->rss_engine_id = BP_FUNC(bp);
3126         rxq_init->mcast_engine_id = BP_FUNC(bp);
3127
3128         /* Maximum number or simultaneous TPA aggregation for this Queue.
3129          *
3130          * For PF Clients it should be the maximum available number.
3131          * VF driver(s) may want to define it to a smaller value.
3132          */
3133         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3134
3135         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3136         rxq_init->fw_sb_id = fp->fw_sb_id;
3137
3138         if (IS_FCOE_FP(fp))
3139                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3140         else
3141                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3142         /* configure silent vlan removal
3143          * if multi function mode is afex, then mask default vlan
3144          */
3145         if (IS_MF_AFEX(bp)) {
3146                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3147                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3148         }
3149 }
3150
3151 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3152         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3153         u8 cos)
3154 {
3155         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3156         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3157         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3158         txq_init->fw_sb_id = fp->fw_sb_id;
3159
3160         /*
3161          * set the tss leading client id for TX classification ==
3162          * leading RSS client id
3163          */
3164         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3165
3166         if (IS_FCOE_FP(fp)) {
3167                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3168                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3169         }
3170 }
3171
3172 static void bnx2x_pf_init(struct bnx2x *bp)
3173 {
3174         struct bnx2x_func_init_params func_init = {0};
3175         struct event_ring_data eq_data = { {0} };
3176         u16 flags;
3177
3178         if (!CHIP_IS_E1x(bp)) {
3179                 /* reset IGU PF statistics: MSIX + ATTN */
3180                 /* PF */
3181                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3182                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3183                            (CHIP_MODE_IS_4_PORT(bp) ?
3184                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3185                 /* ATTN */
3186                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3187                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3188                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3189                            (CHIP_MODE_IS_4_PORT(bp) ?
3190                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3191         }
3192
3193         /* function setup flags */
3194         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3195
3196         /* This flag is relevant for E1x only.
3197          * E2 doesn't have a TPA configuration in a function level.
3198          */
3199         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3200
3201         func_init.func_flgs = flags;
3202         func_init.pf_id = BP_FUNC(bp);
3203         func_init.func_id = BP_FUNC(bp);
3204         func_init.spq_map = bp->spq_mapping;
3205         func_init.spq_prod = bp->spq_prod_idx;
3206
3207         bnx2x_func_init(bp, &func_init);
3208
3209         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3210
3211         /*
3212          * Congestion management values depend on the link rate
3213          * There is no active link so initial link rate is set to 10 Gbps.
3214          * When the link comes up The congestion management values are
3215          * re-calculated according to the actual link rate.
3216          */
3217         bp->link_vars.line_speed = SPEED_10000;
3218         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3219
3220         /* Only the PMF sets the HW */
3221         if (bp->port.pmf)
3222                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3223
3224         /* init Event Queue - PCI bus guarantees correct endianity*/
3225         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3226         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3227         eq_data.producer = bp->eq_prod;
3228         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3229         eq_data.sb_id = DEF_SB_ID;
3230         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3231 }
3232
3233 static void bnx2x_e1h_disable(struct bnx2x *bp)
3234 {
3235         int port = BP_PORT(bp);
3236
3237         bnx2x_tx_disable(bp);
3238
3239         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3240 }
3241
3242 static void bnx2x_e1h_enable(struct bnx2x *bp)
3243 {
3244         int port = BP_PORT(bp);
3245
3246         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3247
3248         /* Tx queue should be only re-enabled */
3249         netif_tx_wake_all_queues(bp->dev);
3250
3251         /*
3252          * Should not call netif_carrier_on since it will be called if the link
3253          * is up when checking for link state
3254          */
3255 }
3256
3257 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3258
3259 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3260 {
3261         struct eth_stats_info *ether_stat =
3262                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3263         struct bnx2x_vlan_mac_obj *mac_obj =
3264                 &bp->sp_objs->mac_obj;
3265         int i;
3266
3267         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3268                 ETH_STAT_INFO_VERSION_LEN);
3269
3270         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3271          * mac_local field in ether_stat struct. The base address is offset by 2
3272          * bytes to account for the field being 8 bytes but a mac address is
3273          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3274          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3275          * allocated by the ether_stat struct, so the macs will land in their
3276          * proper positions.
3277          */
3278         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3279                 memset(ether_stat->mac_local + i, 0,
3280                        sizeof(ether_stat->mac_local[0]));
3281         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3282                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3283                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3284                                 ETH_ALEN);
3285         ether_stat->mtu_size = bp->dev->mtu;
3286         if (bp->dev->features & NETIF_F_RXCSUM)
3287                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3288         if (bp->dev->features & NETIF_F_TSO)
3289                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3290         ether_stat->feature_flags |= bp->common.boot_mode;
3291
3292         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3293
3294         ether_stat->txq_size = bp->tx_ring_size;
3295         ether_stat->rxq_size = bp->rx_ring_size;
3296 }
3297
3298 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3299 {
3300         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3301         struct fcoe_stats_info *fcoe_stat =
3302                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3303
3304         if (!CNIC_LOADED(bp))
3305                 return;
3306
3307         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3308
3309         fcoe_stat->qos_priority =
3310                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3311
3312         /* insert FCoE stats from ramrod response */
3313         if (!NO_FCOE(bp)) {
3314                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3315                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3316                         tstorm_queue_statistics;
3317
3318                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3319                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3320                         xstorm_queue_statistics;
3321
3322                 struct fcoe_statistics_params *fw_fcoe_stat =
3323                         &bp->fw_stats_data->fcoe;
3324
3325                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3326                           fcoe_stat->rx_bytes_lo,
3327                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3328
3329                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3330                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3331                           fcoe_stat->rx_bytes_lo,
3332                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3333
3334                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3335                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3336                           fcoe_stat->rx_bytes_lo,
3337                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3338
3339                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3340                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3341                           fcoe_stat->rx_bytes_lo,
3342                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3343
3344                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3345                           fcoe_stat->rx_frames_lo,
3346                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3347
3348                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3349                           fcoe_stat->rx_frames_lo,
3350                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3351
3352                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3353                           fcoe_stat->rx_frames_lo,
3354                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3355
3356                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3357                           fcoe_stat->rx_frames_lo,
3358                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3359
3360                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3361                           fcoe_stat->tx_bytes_lo,
3362                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3363
3364                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3365                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3366                           fcoe_stat->tx_bytes_lo,
3367                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3368
3369                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3370                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3371                           fcoe_stat->tx_bytes_lo,
3372                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3373
3374                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3375                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3376                           fcoe_stat->tx_bytes_lo,
3377                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3378
3379                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3380                           fcoe_stat->tx_frames_lo,
3381                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3382
3383                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3384                           fcoe_stat->tx_frames_lo,
3385                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3386
3387                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3388                           fcoe_stat->tx_frames_lo,
3389                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3390
3391                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3392                           fcoe_stat->tx_frames_lo,
3393                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3394         }
3395
3396         /* ask L5 driver to add data to the struct */
3397         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3398 }
3399
3400 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3401 {
3402         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3403         struct iscsi_stats_info *iscsi_stat =
3404                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3405
3406         if (!CNIC_LOADED(bp))
3407                 return;
3408
3409         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3410                ETH_ALEN);
3411
3412         iscsi_stat->qos_priority =
3413                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3414
3415         /* ask L5 driver to add data to the struct */
3416         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3417 }
3418
3419 /* called due to MCP event (on pmf):
3420  *      reread new bandwidth configuration
3421  *      configure FW
3422  *      notify others function about the change
3423  */
3424 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3425 {
3426         if (bp->link_vars.link_up) {
3427                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3428                 bnx2x_link_sync_notify(bp);
3429         }
3430         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3431 }
3432
3433 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3434 {
3435         bnx2x_config_mf_bw(bp);
3436         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3437 }
3438
3439 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3440 {
3441         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3442         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3443 }
3444
3445 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3446 {
3447         enum drv_info_opcode op_code;
3448         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3449
3450         /* if drv_info version supported by MFW doesn't match - send NACK */
3451         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3452                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3453                 return;
3454         }
3455
3456         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3457                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3458
3459         memset(&bp->slowpath->drv_info_to_mcp, 0,
3460                sizeof(union drv_info_to_mcp));
3461
3462         switch (op_code) {
3463         case ETH_STATS_OPCODE:
3464                 bnx2x_drv_info_ether_stat(bp);
3465                 break;
3466         case FCOE_STATS_OPCODE:
3467                 bnx2x_drv_info_fcoe_stat(bp);
3468                 break;
3469         case ISCSI_STATS_OPCODE:
3470                 bnx2x_drv_info_iscsi_stat(bp);
3471                 break;
3472         default:
3473                 /* if op code isn't supported - send NACK */
3474                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3475                 return;
3476         }
3477
3478         /* if we got drv_info attn from MFW then these fields are defined in
3479          * shmem2 for sure
3480          */
3481         SHMEM2_WR(bp, drv_info_host_addr_lo,
3482                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3483         SHMEM2_WR(bp, drv_info_host_addr_hi,
3484                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3485
3486         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3487 }
3488
3489 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3490 {
3491         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3492
3493         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3494
3495                 /*
3496                  * This is the only place besides the function initialization
3497                  * where the bp->flags can change so it is done without any
3498                  * locks
3499                  */
3500                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3501                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3502                         bp->flags |= MF_FUNC_DIS;
3503
3504                         bnx2x_e1h_disable(bp);
3505                 } else {
3506                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3507                         bp->flags &= ~MF_FUNC_DIS;
3508
3509                         bnx2x_e1h_enable(bp);
3510                 }
3511                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3512         }
3513         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3514                 bnx2x_config_mf_bw(bp);
3515                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3516         }
3517
3518         /* Report results to MCP */
3519         if (dcc_event)
3520                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3521         else
3522                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3523 }
3524
3525 /* must be called under the spq lock */
3526 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3527 {
3528         struct eth_spe *next_spe = bp->spq_prod_bd;
3529
3530         if (bp->spq_prod_bd == bp->spq_last_bd) {
3531                 bp->spq_prod_bd = bp->spq;
3532                 bp->spq_prod_idx = 0;
3533                 DP(BNX2X_MSG_SP, "end of spq\n");
3534         } else {
3535                 bp->spq_prod_bd++;
3536                 bp->spq_prod_idx++;
3537         }
3538         return next_spe;
3539 }
3540
3541 /* must be called under the spq lock */
3542 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3543 {
3544         int func = BP_FUNC(bp);
3545
3546         /*
3547          * Make sure that BD data is updated before writing the producer:
3548          * BD data is written to the memory, the producer is read from the
3549          * memory, thus we need a full memory barrier to ensure the ordering.
3550          */
3551         mb();
3552
3553         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3554                  bp->spq_prod_idx);
3555         mmiowb();
3556 }
3557
3558 /**
3559  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3560  *
3561  * @cmd:        command to check
3562  * @cmd_type:   command type
3563  */
3564 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3565 {
3566         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3567             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3568             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3569             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3570             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3571             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3572             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3573                 return true;
3574         else
3575                 return false;
3576 }
3577
3578 /**
3579  * bnx2x_sp_post - place a single command on an SP ring
3580  *
3581  * @bp:         driver handle
3582  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3583  * @cid:        SW CID the command is related to
3584  * @data_hi:    command private data address (high 32 bits)
3585  * @data_lo:    command private data address (low 32 bits)
3586  * @cmd_type:   command type (e.g. NONE, ETH)
3587  *
3588  * SP data is handled as if it's always an address pair, thus data fields are
3589  * not swapped to little endian in upper functions. Instead this function swaps
3590  * data as if it's two u32 fields.
3591  */
3592 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3593                   u32 data_hi, u32 data_lo, int cmd_type)
3594 {
3595         struct eth_spe *spe;
3596         u16 type;
3597         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3598
3599 #ifdef BNX2X_STOP_ON_ERROR
3600         if (unlikely(bp->panic)) {
3601                 BNX2X_ERR("Can't post SP when there is panic\n");
3602                 return -EIO;
3603         }
3604 #endif
3605
3606         spin_lock_bh(&bp->spq_lock);
3607
3608         if (common) {
3609                 if (!atomic_read(&bp->eq_spq_left)) {
3610                         BNX2X_ERR("BUG! EQ ring full!\n");
3611                         spin_unlock_bh(&bp->spq_lock);
3612                         bnx2x_panic();
3613                         return -EBUSY;
3614                 }
3615         } else if (!atomic_read(&bp->cq_spq_left)) {
3616                         BNX2X_ERR("BUG! SPQ ring full!\n");
3617                         spin_unlock_bh(&bp->spq_lock);
3618                         bnx2x_panic();
3619                         return -EBUSY;
3620         }
3621
3622         spe = bnx2x_sp_get_next(bp);
3623
3624         /* CID needs port number to be encoded int it */
3625         spe->hdr.conn_and_cmd_data =
3626                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3627                                     HW_CID(bp, cid));
3628
3629         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3630
3631         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3632                  SPE_HDR_FUNCTION_ID);
3633
3634         spe->hdr.type = cpu_to_le16(type);
3635
3636         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3637         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3638
3639         /*
3640          * It's ok if the actual decrement is issued towards the memory
3641          * somewhere between the spin_lock and spin_unlock. Thus no
3642          * more explicit memory barrier is needed.
3643          */
3644         if (common)
3645                 atomic_dec(&bp->eq_spq_left);
3646         else
3647                 atomic_dec(&bp->cq_spq_left);
3648
3649         DP(BNX2X_MSG_SP,
3650            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3651            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3652            (u32)(U64_LO(bp->spq_mapping) +
3653            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3654            HW_CID(bp, cid), data_hi, data_lo, type,
3655            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3656
3657         bnx2x_sp_prod_update(bp);
3658         spin_unlock_bh(&bp->spq_lock);
3659         return 0;
3660 }
3661
3662 /* acquire split MCP access lock register */
3663 static int bnx2x_acquire_alr(struct bnx2x *bp)
3664 {
3665         u32 j, val;
3666         int rc = 0;
3667
3668         might_sleep();
3669         for (j = 0; j < 1000; j++) {
3670                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3671                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3672                 if (val & MCPR_ACCESS_LOCK_LOCK)
3673                         break;
3674
3675                 usleep_range(5000, 10000);
3676         }
3677         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3678                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3679                 rc = -EBUSY;
3680         }
3681
3682         return rc;
3683 }
3684
3685 /* release split MCP access lock register */
3686 static void bnx2x_release_alr(struct bnx2x *bp)
3687 {
3688         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3689 }
3690
3691 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3692 #define BNX2X_DEF_SB_IDX        0x0002
3693
3694 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3695 {
3696         struct host_sp_status_block *def_sb = bp->def_status_blk;
3697         u16 rc = 0;
3698
3699         barrier(); /* status block is written to by the chip */
3700         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3701                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3702                 rc |= BNX2X_DEF_SB_ATT_IDX;
3703         }
3704
3705         if (bp->def_idx != def_sb->sp_sb.running_index) {
3706                 bp->def_idx = def_sb->sp_sb.running_index;
3707                 rc |= BNX2X_DEF_SB_IDX;
3708         }
3709
3710         /* Do not reorder: indices reading should complete before handling */
3711         barrier();
3712         return rc;
3713 }
3714
3715 /*
3716  * slow path service functions
3717  */
3718
3719 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3720 {
3721         int port = BP_PORT(bp);
3722         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3723                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3724         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3725                                        NIG_REG_MASK_INTERRUPT_PORT0;
3726         u32 aeu_mask;
3727         u32 nig_mask = 0;
3728         u32 reg_addr;
3729
3730         if (bp->attn_state & asserted)
3731                 BNX2X_ERR("IGU ERROR\n");
3732
3733         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3734         aeu_mask = REG_RD(bp, aeu_addr);
3735
3736         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3737            aeu_mask, asserted);
3738         aeu_mask &= ~(asserted & 0x3ff);
3739         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3740
3741         REG_WR(bp, aeu_addr, aeu_mask);
3742         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3743
3744         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3745         bp->attn_state |= asserted;
3746         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3747
3748         if (asserted & ATTN_HARD_WIRED_MASK) {
3749                 if (asserted & ATTN_NIG_FOR_FUNC) {
3750
3751                         bnx2x_acquire_phy_lock(bp);
3752
3753                         /* save nig interrupt mask */
3754                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3755
3756                         /* If nig_mask is not set, no need to call the update
3757                          * function.
3758                          */
3759                         if (nig_mask) {
3760                                 REG_WR(bp, nig_int_mask_addr, 0);
3761
3762                                 bnx2x_link_attn(bp);
3763                         }
3764
3765                         /* handle unicore attn? */
3766                 }
3767                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3768                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3769
3770                 if (asserted & GPIO_2_FUNC)
3771                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3772
3773                 if (asserted & GPIO_3_FUNC)
3774                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3775
3776                 if (asserted & GPIO_4_FUNC)
3777                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3778
3779                 if (port == 0) {
3780                         if (asserted & ATTN_GENERAL_ATTN_1) {
3781                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3782                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3783                         }
3784                         if (asserted & ATTN_GENERAL_ATTN_2) {
3785                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3786                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3787                         }
3788                         if (asserted & ATTN_GENERAL_ATTN_3) {
3789                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3790                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3791                         }
3792                 } else {
3793                         if (asserted & ATTN_GENERAL_ATTN_4) {
3794                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3795                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3796                         }
3797                         if (asserted & ATTN_GENERAL_ATTN_5) {
3798                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3799                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3800                         }
3801                         if (asserted & ATTN_GENERAL_ATTN_6) {
3802                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3803                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3804                         }
3805                 }
3806
3807         } /* if hardwired */
3808
3809         if (bp->common.int_block == INT_BLOCK_HC)
3810                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3811                             COMMAND_REG_ATTN_BITS_SET);
3812         else
3813                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3814
3815         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3816            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3817         REG_WR(bp, reg_addr, asserted);
3818
3819         /* now set back the mask */
3820         if (asserted & ATTN_NIG_FOR_FUNC) {
3821                 /* Verify that IGU ack through BAR was written before restoring
3822                  * NIG mask. This loop should exit after 2-3 iterations max.
3823                  */
3824                 if (bp->common.int_block != INT_BLOCK_HC) {
3825                         u32 cnt = 0, igu_acked;
3826                         do {
3827                                 igu_acked = REG_RD(bp,
3828                                                    IGU_REG_ATTENTION_ACK_BITS);
3829                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3830                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3831                         if (!igu_acked)
3832                                 DP(NETIF_MSG_HW,
3833                                    "Failed to verify IGU ack on time\n");
3834                         barrier();
3835                 }
3836                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3837                 bnx2x_release_phy_lock(bp);
3838         }
3839 }
3840
3841 static void bnx2x_fan_failure(struct bnx2x *bp)
3842 {
3843         int port = BP_PORT(bp);
3844         u32 ext_phy_config;
3845         /* mark the failure */
3846         ext_phy_config =
3847                 SHMEM_RD(bp,
3848                          dev_info.port_hw_config[port].external_phy_config);
3849
3850         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3851         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3852         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3853                  ext_phy_config);
3854
3855         /* log the failure */
3856         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3857                             "Please contact OEM Support for assistance\n");
3858
3859         /* Schedule device reset (unload)
3860          * This is due to some boards consuming sufficient power when driver is
3861          * up to overheat if fan fails.
3862          */
3863         smp_mb__before_clear_bit();
3864         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3865         smp_mb__after_clear_bit();
3866         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3867 }
3868
3869 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3870 {
3871         int port = BP_PORT(bp);
3872         int reg_offset;
3873         u32 val;
3874
3875         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3876                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3877
3878         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3879
3880                 val = REG_RD(bp, reg_offset);
3881                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3882                 REG_WR(bp, reg_offset, val);
3883
3884                 BNX2X_ERR("SPIO5 hw attention\n");
3885
3886                 /* Fan failure attention */
3887                 bnx2x_hw_reset_phy(&bp->link_params);
3888                 bnx2x_fan_failure(bp);
3889         }
3890
3891         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3892                 bnx2x_acquire_phy_lock(bp);
3893                 bnx2x_handle_module_detect_int(&bp->link_params);
3894                 bnx2x_release_phy_lock(bp);
3895         }
3896
3897         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3898
3899                 val = REG_RD(bp, reg_offset);
3900                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3901                 REG_WR(bp, reg_offset, val);
3902
3903                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3904                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3905                 bnx2x_panic();
3906         }
3907 }
3908
3909 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3910 {
3911         u32 val;
3912
3913         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3914
3915                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3916                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3917                 /* DORQ discard attention */
3918                 if (val & 0x2)
3919                         BNX2X_ERR("FATAL error from DORQ\n");
3920         }
3921
3922         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3923
3924                 int port = BP_PORT(bp);
3925                 int reg_offset;
3926
3927                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3928                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3929
3930                 val = REG_RD(bp, reg_offset);
3931                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3932                 REG_WR(bp, reg_offset, val);
3933
3934                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3935                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3936                 bnx2x_panic();
3937         }
3938 }
3939
3940 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3941 {
3942         u32 val;
3943
3944         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3945
3946                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3947                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3948                 /* CFC error attention */
3949                 if (val & 0x2)
3950                         BNX2X_ERR("FATAL error from CFC\n");
3951         }
3952
3953         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3954                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3955                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3956                 /* RQ_USDMDP_FIFO_OVERFLOW */
3957                 if (val & 0x18000)
3958                         BNX2X_ERR("FATAL error from PXP\n");
3959
3960                 if (!CHIP_IS_E1x(bp)) {
3961                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3962                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3963                 }
3964         }
3965
3966         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3967
3968                 int port = BP_PORT(bp);
3969                 int reg_offset;
3970
3971                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3972                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3973
3974                 val = REG_RD(bp, reg_offset);
3975                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3976                 REG_WR(bp, reg_offset, val);
3977
3978                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3979                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3980                 bnx2x_panic();
3981         }
3982 }
3983
3984 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3985 {
3986         u32 val;
3987
3988         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3989
3990                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3991                         int func = BP_FUNC(bp);
3992
3993                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3994                         bnx2x_read_mf_cfg(bp);
3995                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3996                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3997                         val = SHMEM_RD(bp,
3998                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3999                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4000                                 bnx2x_dcc_event(bp,
4001                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4002
4003                         if (val & DRV_STATUS_SET_MF_BW)
4004                                 bnx2x_set_mf_bw(bp);
4005
4006                         if (val & DRV_STATUS_DRV_INFO_REQ)
4007                                 bnx2x_handle_drv_info_req(bp);
4008
4009                         if (val & DRV_STATUS_VF_DISABLED)
4010                                 bnx2x_vf_handle_flr_event(bp);
4011
4012                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4013                                 bnx2x_pmf_update(bp);
4014
4015                         if (bp->port.pmf &&
4016                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4017                                 bp->dcbx_enabled > 0)
4018                                 /* start dcbx state machine */
4019                                 bnx2x_dcbx_set_params(bp,
4020                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4021                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4022                                 bnx2x_handle_afex_cmd(bp,
4023                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4024                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4025                                 bnx2x_handle_eee_event(bp);
4026                         if (bp->link_vars.periodic_flags &
4027                             PERIODIC_FLAGS_LINK_EVENT) {
4028                                 /*  sync with link */
4029                                 bnx2x_acquire_phy_lock(bp);
4030                                 bp->link_vars.periodic_flags &=
4031                                         ~PERIODIC_FLAGS_LINK_EVENT;
4032                                 bnx2x_release_phy_lock(bp);
4033                                 if (IS_MF(bp))
4034                                         bnx2x_link_sync_notify(bp);
4035                                 bnx2x_link_report(bp);
4036                         }
4037                         /* Always call it here: bnx2x_link_report() will
4038                          * prevent the link indication duplication.
4039                          */
4040                         bnx2x__link_status_update(bp);
4041                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4042
4043                         BNX2X_ERR("MC assert!\n");
4044                         bnx2x_mc_assert(bp);
4045                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4046                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4047                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4048                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4049                         bnx2x_panic();
4050
4051                 } else if (attn & BNX2X_MCP_ASSERT) {
4052
4053                         BNX2X_ERR("MCP assert!\n");
4054                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4055                         bnx2x_fw_dump(bp);
4056
4057                 } else
4058                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4059         }
4060
4061         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4062                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4063                 if (attn & BNX2X_GRC_TIMEOUT) {
4064                         val = CHIP_IS_E1(bp) ? 0 :
4065                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4066                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4067                 }
4068                 if (attn & BNX2X_GRC_RSV) {
4069                         val = CHIP_IS_E1(bp) ? 0 :
4070                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4071                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4072                 }
4073                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4074         }
4075 }
4076
4077 /*
4078  * Bits map:
4079  * 0-7   - Engine0 load counter.
4080  * 8-15  - Engine1 load counter.
4081  * 16    - Engine0 RESET_IN_PROGRESS bit.
4082  * 17    - Engine1 RESET_IN_PROGRESS bit.
4083  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4084  *         on the engine
4085  * 19    - Engine1 ONE_IS_LOADED.
4086  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4087  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4088  *         just the one belonging to its engine).
4089  *
4090  */
4091 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4092
4093 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4094 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4095 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4096 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4097 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4098 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4099 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4100
4101 /*
4102  * Set the GLOBAL_RESET bit.
4103  *
4104  * Should be run under rtnl lock
4105  */
4106 void bnx2x_set_reset_global(struct bnx2x *bp)
4107 {
4108         u32 val;
4109         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4110         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4111         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4112         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4113 }
4114
4115 /*
4116  * Clear the GLOBAL_RESET bit.
4117  *
4118  * Should be run under rtnl lock
4119  */
4120 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4121 {
4122         u32 val;
4123         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4124         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4125         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4126         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4127 }
4128
4129 /*
4130  * Checks the GLOBAL_RESET bit.
4131  *
4132  * should be run under rtnl lock
4133  */
4134 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4135 {
4136         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4137
4138         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4139         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4140 }
4141
4142 /*
4143  * Clear RESET_IN_PROGRESS bit for the current engine.
4144  *
4145  * Should be run under rtnl lock
4146  */
4147 static void bnx2x_set_reset_done(struct bnx2x *bp)
4148 {
4149         u32 val;
4150         u32 bit = BP_PATH(bp) ?
4151                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4152         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4153         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4154
4155         /* Clear the bit */
4156         val &= ~bit;
4157         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4158
4159         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4160 }
4161
4162 /*
4163  * Set RESET_IN_PROGRESS for the current engine.
4164  *
4165  * should be run under rtnl lock
4166  */
4167 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4168 {
4169         u32 val;
4170         u32 bit = BP_PATH(bp) ?
4171                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4172         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4173         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4174
4175         /* Set the bit */
4176         val |= bit;
4177         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4178         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4179 }
4180
4181 /*
4182  * Checks the RESET_IN_PROGRESS bit for the given engine.
4183  * should be run under rtnl lock
4184  */
4185 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4186 {
4187         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4188         u32 bit = engine ?
4189                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4190
4191         /* return false if bit is set */
4192         return (val & bit) ? false : true;
4193 }
4194
4195 /*
4196  * set pf load for the current pf.
4197  *
4198  * should be run under rtnl lock
4199  */
4200 void bnx2x_set_pf_load(struct bnx2x *bp)
4201 {
4202         u32 val1, val;
4203         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4204                              BNX2X_PATH0_LOAD_CNT_MASK;
4205         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4206                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4207
4208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4209         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4210
4211         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4212
4213         /* get the current counter value */
4214         val1 = (val & mask) >> shift;
4215
4216         /* set bit of that PF */
4217         val1 |= (1 << bp->pf_num);
4218
4219         /* clear the old value */
4220         val &= ~mask;
4221
4222         /* set the new one */
4223         val |= ((val1 << shift) & mask);
4224
4225         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4226         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4227 }
4228
4229 /**
4230  * bnx2x_clear_pf_load - clear pf load mark
4231  *
4232  * @bp:         driver handle
4233  *
4234  * Should be run under rtnl lock.
4235  * Decrements the load counter for the current engine. Returns
4236  * whether other functions are still loaded
4237  */
4238 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4239 {
4240         u32 val1, val;
4241         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4242                              BNX2X_PATH0_LOAD_CNT_MASK;
4243         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4244                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4245
4246         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4247         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4248         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4249
4250         /* get the current counter value */
4251         val1 = (val & mask) >> shift;
4252
4253         /* clear bit of that PF */
4254         val1 &= ~(1 << bp->pf_num);
4255
4256         /* clear the old value */
4257         val &= ~mask;
4258
4259         /* set the new one */
4260         val |= ((val1 << shift) & mask);
4261
4262         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4263         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4264         return val1 != 0;
4265 }
4266
4267 /*
4268  * Read the load status for the current engine.
4269  *
4270  * should be run under rtnl lock
4271  */
4272 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4273 {
4274         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4275                              BNX2X_PATH0_LOAD_CNT_MASK);
4276         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4277                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4278         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4279
4280         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4281
4282         val = (val & mask) >> shift;
4283
4284         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4285            engine, val);
4286
4287         return val != 0;
4288 }
4289
4290 static void _print_parity(struct bnx2x *bp, u32 reg)
4291 {
4292         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4293 }
4294
4295 static void _print_next_block(int idx, const char *blk)
4296 {
4297         pr_cont("%s%s", idx ? ", " : "", blk);
4298 }
4299
4300 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4301                                             int par_num, bool print)
4302 {
4303         int i = 0;
4304         u32 cur_bit = 0;
4305         for (i = 0; sig; i++) {
4306                 cur_bit = ((u32)0x1 << i);
4307                 if (sig & cur_bit) {
4308                         switch (cur_bit) {
4309                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4310                                 if (print) {
4311                                         _print_next_block(par_num++, "BRB");
4312                                         _print_parity(bp,
4313                                                       BRB1_REG_BRB1_PRTY_STS);
4314                                 }
4315                                 break;
4316                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4317                                 if (print) {
4318                                         _print_next_block(par_num++, "PARSER");
4319                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4320                                 }
4321                                 break;
4322                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4323                                 if (print) {
4324                                         _print_next_block(par_num++, "TSDM");
4325                                         _print_parity(bp,
4326                                                       TSDM_REG_TSDM_PRTY_STS);
4327                                 }
4328                                 break;
4329                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4330                                 if (print) {
4331                                         _print_next_block(par_num++,
4332                                                           "SEARCHER");
4333                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4334                                 }
4335                                 break;
4336                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4337                                 if (print) {
4338                                         _print_next_block(par_num++, "TCM");
4339                                         _print_parity(bp,
4340                                                       TCM_REG_TCM_PRTY_STS);
4341                                 }
4342                                 break;
4343                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4344                                 if (print) {
4345                                         _print_next_block(par_num++, "TSEMI");
4346                                         _print_parity(bp,
4347                                                       TSEM_REG_TSEM_PRTY_STS_0);
4348                                         _print_parity(bp,
4349                                                       TSEM_REG_TSEM_PRTY_STS_1);
4350                                 }
4351                                 break;
4352                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4353                                 if (print) {
4354                                         _print_next_block(par_num++, "XPB");
4355                                         _print_parity(bp, GRCBASE_XPB +
4356                                                           PB_REG_PB_PRTY_STS);
4357                                 }
4358                                 break;
4359                         }
4360
4361                         /* Clear the bit */
4362                         sig &= ~cur_bit;
4363                 }
4364         }
4365
4366         return par_num;
4367 }
4368
4369 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4370                                             int par_num, bool *global,
4371                                             bool print)
4372 {
4373         int i = 0;
4374         u32 cur_bit = 0;
4375         for (i = 0; sig; i++) {
4376                 cur_bit = ((u32)0x1 << i);
4377                 if (sig & cur_bit) {
4378                         switch (cur_bit) {
4379                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4380                                 if (print) {
4381                                         _print_next_block(par_num++, "PBF");
4382                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4383                                 }
4384                                 break;
4385                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4386                                 if (print) {
4387                                         _print_next_block(par_num++, "QM");
4388                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4389                                 }
4390                                 break;
4391                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4392                                 if (print) {
4393                                         _print_next_block(par_num++, "TM");
4394                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4395                                 }
4396                                 break;
4397                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4398                                 if (print) {
4399                                         _print_next_block(par_num++, "XSDM");
4400                                         _print_parity(bp,
4401                                                       XSDM_REG_XSDM_PRTY_STS);
4402                                 }
4403                                 break;
4404                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4405                                 if (print) {
4406                                         _print_next_block(par_num++, "XCM");
4407                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4408                                 }
4409                                 break;
4410                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4411                                 if (print) {
4412                                         _print_next_block(par_num++, "XSEMI");
4413                                         _print_parity(bp,
4414                                                       XSEM_REG_XSEM_PRTY_STS_0);
4415                                         _print_parity(bp,
4416                                                       XSEM_REG_XSEM_PRTY_STS_1);
4417                                 }
4418                                 break;
4419                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4420                                 if (print) {
4421                                         _print_next_block(par_num++,
4422                                                           "DOORBELLQ");
4423                                         _print_parity(bp,
4424                                                       DORQ_REG_DORQ_PRTY_STS);
4425                                 }
4426                                 break;
4427                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4428                                 if (print) {
4429                                         _print_next_block(par_num++, "NIG");
4430                                         if (CHIP_IS_E1x(bp)) {
4431                                                 _print_parity(bp,
4432                                                         NIG_REG_NIG_PRTY_STS);
4433                                         } else {
4434                                                 _print_parity(bp,
4435                                                         NIG_REG_NIG_PRTY_STS_0);
4436                                                 _print_parity(bp,
4437                                                         NIG_REG_NIG_PRTY_STS_1);
4438                                         }
4439                                 }
4440                                 break;
4441                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4442                                 if (print)
4443                                         _print_next_block(par_num++,
4444                                                           "VAUX PCI CORE");
4445                                 *global = true;
4446                                 break;
4447                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4448                                 if (print) {
4449                                         _print_next_block(par_num++, "DEBUG");
4450                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4451                                 }
4452                                 break;
4453                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4454                                 if (print) {
4455                                         _print_next_block(par_num++, "USDM");
4456                                         _print_parity(bp,
4457                                                       USDM_REG_USDM_PRTY_STS);
4458                                 }
4459                                 break;
4460                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4461                                 if (print) {
4462                                         _print_next_block(par_num++, "UCM");
4463                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4464                                 }
4465                                 break;
4466                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4467                                 if (print) {
4468                                         _print_next_block(par_num++, "USEMI");
4469                                         _print_parity(bp,
4470                                                       USEM_REG_USEM_PRTY_STS_0);
4471                                         _print_parity(bp,
4472                                                       USEM_REG_USEM_PRTY_STS_1);
4473                                 }
4474                                 break;
4475                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4476                                 if (print) {
4477                                         _print_next_block(par_num++, "UPB");
4478                                         _print_parity(bp, GRCBASE_UPB +
4479                                                           PB_REG_PB_PRTY_STS);
4480                                 }
4481                                 break;
4482                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4483                                 if (print) {
4484                                         _print_next_block(par_num++, "CSDM");
4485                                         _print_parity(bp,
4486                                                       CSDM_REG_CSDM_PRTY_STS);
4487                                 }
4488                                 break;
4489                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4490                                 if (print) {
4491                                         _print_next_block(par_num++, "CCM");
4492                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4493                                 }
4494                                 break;
4495                         }
4496
4497                         /* Clear the bit */
4498                         sig &= ~cur_bit;
4499                 }
4500         }
4501
4502         return par_num;
4503 }
4504
4505 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4506                                             int par_num, bool print)
4507 {
4508         int i = 0;
4509         u32 cur_bit = 0;
4510         for (i = 0; sig; i++) {
4511                 cur_bit = ((u32)0x1 << i);
4512                 if (sig & cur_bit) {
4513                         switch (cur_bit) {
4514                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4515                                 if (print) {
4516                                         _print_next_block(par_num++, "CSEMI");
4517                                         _print_parity(bp,
4518                                                       CSEM_REG_CSEM_PRTY_STS_0);
4519                                         _print_parity(bp,
4520                                                       CSEM_REG_CSEM_PRTY_STS_1);
4521                                 }
4522                                 break;
4523                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4524                                 if (print) {
4525                                         _print_next_block(par_num++, "PXP");
4526                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4527                                         _print_parity(bp,
4528                                                       PXP2_REG_PXP2_PRTY_STS_0);
4529                                         _print_parity(bp,
4530                                                       PXP2_REG_PXP2_PRTY_STS_1);
4531                                 }
4532                                 break;
4533                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4534                                 if (print)
4535                                         _print_next_block(par_num++,
4536                                         "PXPPCICLOCKCLIENT");
4537                                 break;
4538                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4539                                 if (print) {
4540                                         _print_next_block(par_num++, "CFC");
4541                                         _print_parity(bp,
4542                                                       CFC_REG_CFC_PRTY_STS);
4543                                 }
4544                                 break;
4545                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4546                                 if (print) {
4547                                         _print_next_block(par_num++, "CDU");
4548                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4549                                 }
4550                                 break;
4551                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4552                                 if (print) {
4553                                         _print_next_block(par_num++, "DMAE");
4554                                         _print_parity(bp,
4555                                                       DMAE_REG_DMAE_PRTY_STS);
4556                                 }
4557                                 break;
4558                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4559                                 if (print) {
4560                                         _print_next_block(par_num++, "IGU");
4561                                         if (CHIP_IS_E1x(bp))
4562                                                 _print_parity(bp,
4563                                                         HC_REG_HC_PRTY_STS);
4564                                         else
4565                                                 _print_parity(bp,
4566                                                         IGU_REG_IGU_PRTY_STS);
4567                                 }
4568                                 break;
4569                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4570                                 if (print) {
4571                                         _print_next_block(par_num++, "MISC");
4572                                         _print_parity(bp,
4573                                                       MISC_REG_MISC_PRTY_STS);
4574                                 }
4575                                 break;
4576                         }
4577
4578                         /* Clear the bit */
4579                         sig &= ~cur_bit;
4580                 }
4581         }
4582
4583         return par_num;
4584 }
4585
4586 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4587                                            bool *global, bool print)
4588 {
4589         int i = 0;
4590         u32 cur_bit = 0;
4591         for (i = 0; sig; i++) {
4592                 cur_bit = ((u32)0x1 << i);
4593                 if (sig & cur_bit) {
4594                         switch (cur_bit) {
4595                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4596                                 if (print)
4597                                         _print_next_block(par_num++, "MCP ROM");
4598                                 *global = true;
4599                                 break;
4600                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4601                                 if (print)
4602                                         _print_next_block(par_num++,
4603                                                           "MCP UMP RX");
4604                                 *global = true;
4605                                 break;
4606                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4607                                 if (print)
4608                                         _print_next_block(par_num++,
4609                                                           "MCP UMP TX");
4610                                 *global = true;
4611                                 break;
4612                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4613                                 if (print)
4614                                         _print_next_block(par_num++,
4615                                                           "MCP SCPAD");
4616                                 *global = true;
4617                                 break;
4618                         }
4619
4620                         /* Clear the bit */
4621                         sig &= ~cur_bit;
4622                 }
4623         }
4624
4625         return par_num;
4626 }
4627
4628 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4629                                             int par_num, bool print)
4630 {
4631         int i = 0;
4632         u32 cur_bit = 0;
4633         for (i = 0; sig; i++) {
4634                 cur_bit = ((u32)0x1 << i);
4635                 if (sig & cur_bit) {
4636                         switch (cur_bit) {
4637                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4638                                 if (print) {
4639                                         _print_next_block(par_num++, "PGLUE_B");
4640                                         _print_parity(bp,
4641                                                 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4642                                 }
4643                                 break;
4644                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4645                                 if (print) {
4646                                         _print_next_block(par_num++, "ATC");
4647                                         _print_parity(bp,
4648                                                       ATC_REG_ATC_PRTY_STS);
4649                                 }
4650                                 break;
4651                         }
4652
4653                         /* Clear the bit */
4654                         sig &= ~cur_bit;
4655                 }
4656         }
4657
4658         return par_num;
4659 }
4660
4661 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4662                               u32 *sig)
4663 {
4664         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4665             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4666             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4667             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4668             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4669                 int par_num = 0;
4670                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4671                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4672                           sig[0] & HW_PRTY_ASSERT_SET_0,
4673                           sig[1] & HW_PRTY_ASSERT_SET_1,
4674                           sig[2] & HW_PRTY_ASSERT_SET_2,
4675                           sig[3] & HW_PRTY_ASSERT_SET_3,
4676                           sig[4] & HW_PRTY_ASSERT_SET_4);
4677                 if (print)
4678                         netdev_err(bp->dev,
4679                                    "Parity errors detected in blocks: ");
4680                 par_num = bnx2x_check_blocks_with_parity0(bp,
4681                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4682                 par_num = bnx2x_check_blocks_with_parity1(bp,
4683                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4684                 par_num = bnx2x_check_blocks_with_parity2(bp,
4685                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4686                 par_num = bnx2x_check_blocks_with_parity3(
4687                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4688                 par_num = bnx2x_check_blocks_with_parity4(bp,
4689                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4690
4691                 if (print)
4692                         pr_cont("\n");
4693
4694                 return true;
4695         } else
4696                 return false;
4697 }
4698
4699 /**
4700  * bnx2x_chk_parity_attn - checks for parity attentions.
4701  *
4702  * @bp:         driver handle
4703  * @global:     true if there was a global attention
4704  * @print:      show parity attention in syslog
4705  */
4706 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4707 {
4708         struct attn_route attn = { {0} };
4709         int port = BP_PORT(bp);
4710
4711         attn.sig[0] = REG_RD(bp,
4712                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4713                              port*4);
4714         attn.sig[1] = REG_RD(bp,
4715                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4716                              port*4);
4717         attn.sig[2] = REG_RD(bp,
4718                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4719                              port*4);
4720         attn.sig[3] = REG_RD(bp,
4721                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4722                              port*4);
4723         /* Since MCP attentions can't be disabled inside the block, we need to
4724          * read AEU registers to see whether they're currently disabled
4725          */
4726         attn.sig[3] &= ((REG_RD(bp,
4727                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4728                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4729                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4730                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4731
4732         if (!CHIP_IS_E1x(bp))
4733                 attn.sig[4] = REG_RD(bp,
4734                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4735                                      port*4);
4736
4737         return bnx2x_parity_attn(bp, global, print, attn.sig);
4738 }
4739
4740 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4741 {
4742         u32 val;
4743         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4744
4745                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4746                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4747                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4748                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4749                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4750                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4751                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4752                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4753                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4754                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4755                 if (val &
4756                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4757                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4758                 if (val &
4759                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4760                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4761                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4762                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4763                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4764                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4765                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4766                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4767         }
4768         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4769                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4770                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4771                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4772                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4773                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4774                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4775                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4776                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4777                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4778                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4779                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4780                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4781                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4782                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4783         }
4784
4785         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4786                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4787                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4788                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4789                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4790         }
4791 }
4792
4793 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4794 {
4795         struct attn_route attn, *group_mask;
4796         int port = BP_PORT(bp);
4797         int index;
4798         u32 reg_addr;
4799         u32 val;
4800         u32 aeu_mask;
4801         bool global = false;
4802
4803         /* need to take HW lock because MCP or other port might also
4804            try to handle this event */
4805         bnx2x_acquire_alr(bp);
4806
4807         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4808 #ifndef BNX2X_STOP_ON_ERROR
4809                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4810                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4811                 /* Disable HW interrupts */
4812                 bnx2x_int_disable(bp);
4813                 /* In case of parity errors don't handle attentions so that
4814                  * other function would "see" parity errors.
4815                  */
4816 #else
4817                 bnx2x_panic();
4818 #endif
4819                 bnx2x_release_alr(bp);
4820                 return;
4821         }
4822
4823         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4824         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4825         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4826         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4827         if (!CHIP_IS_E1x(bp))
4828                 attn.sig[4] =
4829                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4830         else
4831                 attn.sig[4] = 0;
4832
4833         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4834            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4835
4836         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4837                 if (deasserted & (1 << index)) {
4838                         group_mask = &bp->attn_group[index];
4839
4840                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4841                            index,
4842                            group_mask->sig[0], group_mask->sig[1],
4843                            group_mask->sig[2], group_mask->sig[3],
4844                            group_mask->sig[4]);
4845
4846                         bnx2x_attn_int_deasserted4(bp,
4847                                         attn.sig[4] & group_mask->sig[4]);
4848                         bnx2x_attn_int_deasserted3(bp,
4849                                         attn.sig[3] & group_mask->sig[3]);
4850                         bnx2x_attn_int_deasserted1(bp,
4851                                         attn.sig[1] & group_mask->sig[1]);
4852                         bnx2x_attn_int_deasserted2(bp,
4853                                         attn.sig[2] & group_mask->sig[2]);
4854                         bnx2x_attn_int_deasserted0(bp,
4855                                         attn.sig[0] & group_mask->sig[0]);
4856                 }
4857         }
4858
4859         bnx2x_release_alr(bp);
4860
4861         if (bp->common.int_block == INT_BLOCK_HC)
4862                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4863                             COMMAND_REG_ATTN_BITS_CLR);
4864         else
4865                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4866
4867         val = ~deasserted;
4868         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4869            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4870         REG_WR(bp, reg_addr, val);
4871
4872         if (~bp->attn_state & deasserted)
4873                 BNX2X_ERR("IGU ERROR\n");
4874
4875         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4876                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4877
4878         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4879         aeu_mask = REG_RD(bp, reg_addr);
4880
4881         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4882            aeu_mask, deasserted);
4883         aeu_mask |= (deasserted & 0x3ff);
4884         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4885
4886         REG_WR(bp, reg_addr, aeu_mask);
4887         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4888
4889         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4890         bp->attn_state &= ~deasserted;
4891         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4892 }
4893
4894 static void bnx2x_attn_int(struct bnx2x *bp)
4895 {
4896         /* read local copy of bits */
4897         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4898                                                                 attn_bits);
4899         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4900                                                                 attn_bits_ack);
4901         u32 attn_state = bp->attn_state;
4902
4903         /* look for changed bits */
4904         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4905         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4906
4907         DP(NETIF_MSG_HW,
4908            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4909            attn_bits, attn_ack, asserted, deasserted);
4910
4911         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4912                 BNX2X_ERR("BAD attention state\n");
4913
4914         /* handle bits that were raised */
4915         if (asserted)
4916                 bnx2x_attn_int_asserted(bp, asserted);
4917
4918         if (deasserted)
4919                 bnx2x_attn_int_deasserted(bp, deasserted);
4920 }
4921
4922 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4923                       u16 index, u8 op, u8 update)
4924 {
4925         u32 igu_addr = bp->igu_base_addr;
4926         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4927         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4928                              igu_addr);
4929 }
4930
4931 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4932 {
4933         /* No memory barriers */
4934         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4935         mmiowb(); /* keep prod updates ordered */
4936 }
4937
4938 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4939                                       union event_ring_elem *elem)
4940 {
4941         u8 err = elem->message.error;
4942
4943         if (!bp->cnic_eth_dev.starting_cid  ||
4944             (cid < bp->cnic_eth_dev.starting_cid &&
4945             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4946                 return 1;
4947
4948         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4949
4950         if (unlikely(err)) {
4951
4952                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4953                           cid);
4954                 bnx2x_panic_dump(bp, false);
4955         }
4956         bnx2x_cnic_cfc_comp(bp, cid, err);
4957         return 0;
4958 }
4959
4960 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4961 {
4962         struct bnx2x_mcast_ramrod_params rparam;
4963         int rc;
4964
4965         memset(&rparam, 0, sizeof(rparam));
4966
4967         rparam.mcast_obj = &bp->mcast_obj;
4968
4969         netif_addr_lock_bh(bp->dev);
4970
4971         /* Clear pending state for the last command */
4972         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4973
4974         /* If there are pending mcast commands - send them */
4975         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4976                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4977                 if (rc < 0)
4978                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4979                                   rc);
4980         }
4981
4982         netif_addr_unlock_bh(bp->dev);
4983 }
4984
4985 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4986                                             union event_ring_elem *elem)
4987 {
4988         unsigned long ramrod_flags = 0;
4989         int rc = 0;
4990         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4991         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4992
4993         /* Always push next commands out, don't wait here */
4994         __set_bit(RAMROD_CONT, &ramrod_flags);
4995
4996         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4997                             >> BNX2X_SWCID_SHIFT) {
4998         case BNX2X_FILTER_MAC_PENDING:
4999                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5000                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5001                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5002                 else
5003                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5004
5005                 break;
5006         case BNX2X_FILTER_MCAST_PENDING:
5007                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5008                 /* This is only relevant for 57710 where multicast MACs are
5009                  * configured as unicast MACs using the same ramrod.
5010                  */
5011                 bnx2x_handle_mcast_eqe(bp);
5012                 return;
5013         default:
5014                 BNX2X_ERR("Unsupported classification command: %d\n",
5015                           elem->message.data.eth_event.echo);
5016                 return;
5017         }
5018
5019         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5020
5021         if (rc < 0)
5022                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5023         else if (rc > 0)
5024                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5025 }
5026
5027 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5028
5029 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5030 {
5031         netif_addr_lock_bh(bp->dev);
5032
5033         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5034
5035         /* Send rx_mode command again if was requested */
5036         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5037                 bnx2x_set_storm_rx_mode(bp);
5038         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5039                                     &bp->sp_state))
5040                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5041         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5042                                     &bp->sp_state))
5043                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5044
5045         netif_addr_unlock_bh(bp->dev);
5046 }
5047
5048 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5049                                               union event_ring_elem *elem)
5050 {
5051         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5052                 DP(BNX2X_MSG_SP,
5053                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5054                    elem->message.data.vif_list_event.func_bit_map);
5055                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5056                         elem->message.data.vif_list_event.func_bit_map);
5057         } else if (elem->message.data.vif_list_event.echo ==
5058                    VIF_LIST_RULE_SET) {
5059                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5060                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5061         }
5062 }
5063
5064 /* called with rtnl_lock */
5065 static void bnx2x_after_function_update(struct bnx2x *bp)
5066 {
5067         int q, rc;
5068         struct bnx2x_fastpath *fp;
5069         struct bnx2x_queue_state_params queue_params = {NULL};
5070         struct bnx2x_queue_update_params *q_update_params =
5071                 &queue_params.params.update;
5072
5073         /* Send Q update command with afex vlan removal values for all Qs */
5074         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5075
5076         /* set silent vlan removal values according to vlan mode */
5077         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5078                   &q_update_params->update_flags);
5079         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5080                   &q_update_params->update_flags);
5081         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5082
5083         /* in access mode mark mask and value are 0 to strip all vlans */
5084         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5085                 q_update_params->silent_removal_value = 0;
5086                 q_update_params->silent_removal_mask = 0;
5087         } else {
5088                 q_update_params->silent_removal_value =
5089                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5090                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5091         }
5092
5093         for_each_eth_queue(bp, q) {
5094                 /* Set the appropriate Queue object */
5095                 fp = &bp->fp[q];
5096                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5097
5098                 /* send the ramrod */
5099                 rc = bnx2x_queue_state_change(bp, &queue_params);
5100                 if (rc < 0)
5101                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5102                                   q);
5103         }
5104
5105         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5106                 fp = &bp->fp[FCOE_IDX(bp)];
5107                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5108
5109                 /* clear pending completion bit */
5110                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5111
5112                 /* mark latest Q bit */
5113                 smp_mb__before_clear_bit();
5114                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5115                 smp_mb__after_clear_bit();
5116
5117                 /* send Q update ramrod for FCoE Q */
5118                 rc = bnx2x_queue_state_change(bp, &queue_params);
5119                 if (rc < 0)
5120                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5121                                   q);
5122         } else {
5123                 /* If no FCoE ring - ACK MCP now */
5124                 bnx2x_link_report(bp);
5125                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5126         }
5127 }
5128
5129 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5130         struct bnx2x *bp, u32 cid)
5131 {
5132         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5133
5134         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5135                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5136         else
5137                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5138 }
5139
5140 static void bnx2x_eq_int(struct bnx2x *bp)
5141 {
5142         u16 hw_cons, sw_cons, sw_prod;
5143         union event_ring_elem *elem;
5144         u8 echo;
5145         u32 cid;
5146         u8 opcode;
5147         int rc, spqe_cnt = 0;
5148         struct bnx2x_queue_sp_obj *q_obj;
5149         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5150         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5151
5152         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5153
5154         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5155          * when we get the next-page we need to adjust so the loop
5156          * condition below will be met. The next element is the size of a
5157          * regular element and hence incrementing by 1
5158          */
5159         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5160                 hw_cons++;
5161
5162         /* This function may never run in parallel with itself for a
5163          * specific bp, thus there is no need in "paired" read memory
5164          * barrier here.
5165          */
5166         sw_cons = bp->eq_cons;
5167         sw_prod = bp->eq_prod;
5168
5169         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5170                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5171
5172         for (; sw_cons != hw_cons;
5173               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5174
5175                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5176
5177                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5178                 if (!rc) {
5179                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5180                            rc);
5181                         goto next_spqe;
5182                 }
5183
5184                 /* elem CID originates from FW; actually LE */
5185                 cid = SW_CID((__force __le32)
5186                              elem->message.data.cfc_del_event.cid);
5187                 opcode = elem->message.opcode;
5188
5189                 /* handle eq element */
5190                 switch (opcode) {
5191                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5192                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5193                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5194                         continue;
5195
5196                 case EVENT_RING_OPCODE_STAT_QUERY:
5197                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5198                            "got statistics comp event %d\n",
5199                            bp->stats_comp++);
5200                         /* nothing to do with stats comp */
5201                         goto next_spqe;
5202
5203                 case EVENT_RING_OPCODE_CFC_DEL:
5204                         /* handle according to cid range */
5205                         /*
5206                          * we may want to verify here that the bp state is
5207                          * HALTING
5208                          */
5209                         DP(BNX2X_MSG_SP,
5210                            "got delete ramrod for MULTI[%d]\n", cid);
5211
5212                         if (CNIC_LOADED(bp) &&
5213                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5214                                 goto next_spqe;
5215
5216                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5217
5218                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5219                                 break;
5220
5221                         goto next_spqe;
5222
5223                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5224                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5225                         if (f_obj->complete_cmd(bp, f_obj,
5226                                                 BNX2X_F_CMD_TX_STOP))
5227                                 break;
5228                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5229                         goto next_spqe;
5230
5231                 case EVENT_RING_OPCODE_START_TRAFFIC:
5232                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5233                         if (f_obj->complete_cmd(bp, f_obj,
5234                                                 BNX2X_F_CMD_TX_START))
5235                                 break;
5236                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5237                         goto next_spqe;
5238
5239                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5240                         echo = elem->message.data.function_update_event.echo;
5241                         if (echo == SWITCH_UPDATE) {
5242                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5243                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5244                                 if (f_obj->complete_cmd(
5245                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5246                                         break;
5247
5248                         } else {
5249                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5250                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5251                                 f_obj->complete_cmd(bp, f_obj,
5252                                                     BNX2X_F_CMD_AFEX_UPDATE);
5253
5254                                 /* We will perform the Queues update from
5255                                  * sp_rtnl task as all Queue SP operations
5256                                  * should run under rtnl_lock.
5257                                  */
5258                                 smp_mb__before_clear_bit();
5259                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5260                                         &bp->sp_rtnl_state);
5261                                 smp_mb__after_clear_bit();
5262
5263                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5264                         }
5265
5266                         goto next_spqe;
5267
5268                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5269                         f_obj->complete_cmd(bp, f_obj,
5270                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5271                         bnx2x_after_afex_vif_lists(bp, elem);
5272                         goto next_spqe;
5273                 case EVENT_RING_OPCODE_FUNCTION_START:
5274                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5275                            "got FUNC_START ramrod\n");
5276                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5277                                 break;
5278
5279                         goto next_spqe;
5280
5281                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5282                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5283                            "got FUNC_STOP ramrod\n");
5284                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5285                                 break;
5286
5287                         goto next_spqe;
5288                 }
5289
5290                 switch (opcode | bp->state) {
5291                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5292                       BNX2X_STATE_OPEN):
5293                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5294                       BNX2X_STATE_OPENING_WAIT4_PORT):
5295                         cid = elem->message.data.eth_event.echo &
5296                                 BNX2X_SWCID_MASK;
5297                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5298                            cid);
5299                         rss_raw->clear_pending(rss_raw);
5300                         break;
5301
5302                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5303                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5304                 case (EVENT_RING_OPCODE_SET_MAC |
5305                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5306                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5307                       BNX2X_STATE_OPEN):
5308                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5309                       BNX2X_STATE_DIAG):
5310                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5311                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5312                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5313                         bnx2x_handle_classification_eqe(bp, elem);
5314                         break;
5315
5316                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5317                       BNX2X_STATE_OPEN):
5318                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5319                       BNX2X_STATE_DIAG):
5320                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5321                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5322                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5323                         bnx2x_handle_mcast_eqe(bp);
5324                         break;
5325
5326                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5327                       BNX2X_STATE_OPEN):
5328                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5329                       BNX2X_STATE_DIAG):
5330                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5331                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5332                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5333                         bnx2x_handle_rx_mode_eqe(bp);
5334                         break;
5335                 default:
5336                         /* unknown event log error and continue */
5337                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5338                                   elem->message.opcode, bp->state);
5339                 }
5340 next_spqe:
5341                 spqe_cnt++;
5342         } /* for */
5343
5344         smp_mb__before_atomic_inc();
5345         atomic_add(spqe_cnt, &bp->eq_spq_left);
5346
5347         bp->eq_cons = sw_cons;
5348         bp->eq_prod = sw_prod;
5349         /* Make sure that above mem writes were issued towards the memory */
5350         smp_wmb();
5351
5352         /* update producer */
5353         bnx2x_update_eq_prod(bp, bp->eq_prod);
5354 }
5355
5356 static void bnx2x_sp_task(struct work_struct *work)
5357 {
5358         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5359
5360         DP(BNX2X_MSG_SP, "sp task invoked\n");
5361
5362         /* make sure the atomic interrupt_occurred has been written */
5363         smp_rmb();
5364         if (atomic_read(&bp->interrupt_occurred)) {
5365
5366                 /* what work needs to be performed? */
5367                 u16 status = bnx2x_update_dsb_idx(bp);
5368
5369                 DP(BNX2X_MSG_SP, "status %x\n", status);
5370                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5371                 atomic_set(&bp->interrupt_occurred, 0);
5372
5373                 /* HW attentions */
5374                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5375                         bnx2x_attn_int(bp);
5376                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5377                 }
5378
5379                 /* SP events: STAT_QUERY and others */
5380                 if (status & BNX2X_DEF_SB_IDX) {
5381                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5382
5383                 if (FCOE_INIT(bp) &&
5384                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5385                                 /* Prevent local bottom-halves from running as
5386                                  * we are going to change the local NAPI list.
5387                                  */
5388                                 local_bh_disable();
5389                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5390                                 local_bh_enable();
5391                         }
5392
5393                         /* Handle EQ completions */
5394                         bnx2x_eq_int(bp);
5395                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5396                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5397
5398                         status &= ~BNX2X_DEF_SB_IDX;
5399                 }
5400
5401                 /* if status is non zero then perhaps something went wrong */
5402                 if (unlikely(status))
5403                         DP(BNX2X_MSG_SP,
5404                            "got an unknown interrupt! (status 0x%x)\n", status);
5405
5406                 /* ack status block only if something was actually handled */
5407                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5408                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5409         }
5410
5411         /* must be called after the EQ processing (since eq leads to sriov
5412          * ramrod completion flows).
5413          * This flow may have been scheduled by the arrival of a ramrod
5414          * completion, or by the sriov code rescheduling itself.
5415          */
5416         bnx2x_iov_sp_task(bp);
5417
5418         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5419         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5420                                &bp->sp_state)) {
5421                 bnx2x_link_report(bp);
5422                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5423         }
5424 }
5425
5426 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5427 {
5428         struct net_device *dev = dev_instance;
5429         struct bnx2x *bp = netdev_priv(dev);
5430
5431         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5432                      IGU_INT_DISABLE, 0);
5433
5434 #ifdef BNX2X_STOP_ON_ERROR
5435         if (unlikely(bp->panic))
5436                 return IRQ_HANDLED;
5437 #endif
5438
5439         if (CNIC_LOADED(bp)) {
5440                 struct cnic_ops *c_ops;
5441
5442                 rcu_read_lock();
5443                 c_ops = rcu_dereference(bp->cnic_ops);
5444                 if (c_ops)
5445                         c_ops->cnic_handler(bp->cnic_data, NULL);
5446                 rcu_read_unlock();
5447         }
5448
5449         /* schedule sp task to perform default status block work, ack
5450          * attentions and enable interrupts.
5451          */
5452         bnx2x_schedule_sp_task(bp);
5453
5454         return IRQ_HANDLED;
5455 }
5456
5457 /* end of slow path */
5458
5459 void bnx2x_drv_pulse(struct bnx2x *bp)
5460 {
5461         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5462                  bp->fw_drv_pulse_wr_seq);
5463 }
5464
5465 static void bnx2x_timer(unsigned long data)
5466 {
5467         struct bnx2x *bp = (struct bnx2x *) data;
5468
5469         if (!netif_running(bp->dev))
5470                 return;
5471
5472         if (IS_PF(bp) &&
5473             !BP_NOMCP(bp)) {
5474                 int mb_idx = BP_FW_MB_IDX(bp);
5475                 u16 drv_pulse;
5476                 u16 mcp_pulse;
5477
5478                 ++bp->fw_drv_pulse_wr_seq;
5479                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5480                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5481                 bnx2x_drv_pulse(bp);
5482
5483                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5484                              MCP_PULSE_SEQ_MASK);
5485                 /* The delta between driver pulse and mcp response
5486                  * should not get too big. If the MFW is more than 5 pulses
5487                  * behind, we should worry about it enough to generate an error
5488                  * log.
5489                  */
5490                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5491                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5492                                   drv_pulse, mcp_pulse);
5493         }
5494
5495         if (bp->state == BNX2X_STATE_OPEN)
5496                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5497
5498         /* sample pf vf bulletin board for new posts from pf */
5499         if (IS_VF(bp))
5500                 bnx2x_timer_sriov(bp);
5501
5502         mod_timer(&bp->timer, jiffies + bp->current_interval);
5503 }
5504
5505 /* end of Statistics */
5506
5507 /* nic init */
5508
5509 /*
5510  * nic init service functions
5511  */
5512
5513 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5514 {
5515         u32 i;
5516         if (!(len%4) && !(addr%4))
5517                 for (i = 0; i < len; i += 4)
5518                         REG_WR(bp, addr + i, fill);
5519         else
5520                 for (i = 0; i < len; i++)
5521                         REG_WR8(bp, addr + i, fill);
5522 }
5523
5524 /* helper: writes FP SP data to FW - data_size in dwords */
5525 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5526                                 int fw_sb_id,
5527                                 u32 *sb_data_p,
5528                                 u32 data_size)
5529 {
5530         int index;
5531         for (index = 0; index < data_size; index++)
5532                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5533                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5534                         sizeof(u32)*index,
5535                         *(sb_data_p + index));
5536 }
5537
5538 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5539 {
5540         u32 *sb_data_p;
5541         u32 data_size = 0;
5542         struct hc_status_block_data_e2 sb_data_e2;
5543         struct hc_status_block_data_e1x sb_data_e1x;
5544
5545         /* disable the function first */
5546         if (!CHIP_IS_E1x(bp)) {
5547                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5548                 sb_data_e2.common.state = SB_DISABLED;
5549                 sb_data_e2.common.p_func.vf_valid = false;
5550                 sb_data_p = (u32 *)&sb_data_e2;
5551                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5552         } else {
5553                 memset(&sb_data_e1x, 0,
5554                        sizeof(struct hc_status_block_data_e1x));
5555                 sb_data_e1x.common.state = SB_DISABLED;
5556                 sb_data_e1x.common.p_func.vf_valid = false;
5557                 sb_data_p = (u32 *)&sb_data_e1x;
5558                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5559         }
5560         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5561
5562         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5563                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5564                         CSTORM_STATUS_BLOCK_SIZE);
5565         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5566                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5567                         CSTORM_SYNC_BLOCK_SIZE);
5568 }
5569
5570 /* helper:  writes SP SB data to FW */
5571 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5572                 struct hc_sp_status_block_data *sp_sb_data)
5573 {
5574         int func = BP_FUNC(bp);
5575         int i;
5576         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5577                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5578                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5579                         i*sizeof(u32),
5580                         *((u32 *)sp_sb_data + i));
5581 }
5582
5583 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5584 {
5585         int func = BP_FUNC(bp);
5586         struct hc_sp_status_block_data sp_sb_data;
5587         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5588
5589         sp_sb_data.state = SB_DISABLED;
5590         sp_sb_data.p_func.vf_valid = false;
5591
5592         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5593
5594         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5595                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5596                         CSTORM_SP_STATUS_BLOCK_SIZE);
5597         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5598                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5599                         CSTORM_SP_SYNC_BLOCK_SIZE);
5600 }
5601
5602 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5603                                            int igu_sb_id, int igu_seg_id)
5604 {
5605         hc_sm->igu_sb_id = igu_sb_id;
5606         hc_sm->igu_seg_id = igu_seg_id;
5607         hc_sm->timer_value = 0xFF;
5608         hc_sm->time_to_expire = 0xFFFFFFFF;
5609 }
5610
5611 /* allocates state machine ids. */
5612 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5613 {
5614         /* zero out state machine indices */
5615         /* rx indices */
5616         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5617
5618         /* tx indices */
5619         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5620         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5621         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5622         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5623
5624         /* map indices */
5625         /* rx indices */
5626         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5627                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5628
5629         /* tx indices */
5630         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5631                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5632         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5633                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5634         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5635                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5636         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5637                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5638 }
5639
5640 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5641                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5642 {
5643         int igu_seg_id;
5644
5645         struct hc_status_block_data_e2 sb_data_e2;
5646         struct hc_status_block_data_e1x sb_data_e1x;
5647         struct hc_status_block_sm  *hc_sm_p;
5648         int data_size;
5649         u32 *sb_data_p;
5650
5651         if (CHIP_INT_MODE_IS_BC(bp))
5652                 igu_seg_id = HC_SEG_ACCESS_NORM;
5653         else
5654                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5655
5656         bnx2x_zero_fp_sb(bp, fw_sb_id);
5657
5658         if (!CHIP_IS_E1x(bp)) {
5659                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5660                 sb_data_e2.common.state = SB_ENABLED;
5661                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5662                 sb_data_e2.common.p_func.vf_id = vfid;
5663                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5664                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5665                 sb_data_e2.common.same_igu_sb_1b = true;
5666                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5667                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5668                 hc_sm_p = sb_data_e2.common.state_machine;
5669                 sb_data_p = (u32 *)&sb_data_e2;
5670                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5671                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5672         } else {
5673                 memset(&sb_data_e1x, 0,
5674                        sizeof(struct hc_status_block_data_e1x));
5675                 sb_data_e1x.common.state = SB_ENABLED;
5676                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5677                 sb_data_e1x.common.p_func.vf_id = 0xff;
5678                 sb_data_e1x.common.p_func.vf_valid = false;
5679                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5680                 sb_data_e1x.common.same_igu_sb_1b = true;
5681                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5682                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5683                 hc_sm_p = sb_data_e1x.common.state_machine;
5684                 sb_data_p = (u32 *)&sb_data_e1x;
5685                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5686                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5687         }
5688
5689         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5690                                        igu_sb_id, igu_seg_id);
5691         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5692                                        igu_sb_id, igu_seg_id);
5693
5694         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5695
5696         /* write indices to HW - PCI guarantees endianity of regpairs */
5697         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5698 }
5699
5700 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5701                                      u16 tx_usec, u16 rx_usec)
5702 {
5703         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5704                                     false, rx_usec);
5705         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5706                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5707                                        tx_usec);
5708         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5709                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5710                                        tx_usec);
5711         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5712                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5713                                        tx_usec);
5714 }
5715
5716 static void bnx2x_init_def_sb(struct bnx2x *bp)
5717 {
5718         struct host_sp_status_block *def_sb = bp->def_status_blk;
5719         dma_addr_t mapping = bp->def_status_blk_mapping;
5720         int igu_sp_sb_index;
5721         int igu_seg_id;
5722         int port = BP_PORT(bp);
5723         int func = BP_FUNC(bp);
5724         int reg_offset, reg_offset_en5;
5725         u64 section;
5726         int index;
5727         struct hc_sp_status_block_data sp_sb_data;
5728         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5729
5730         if (CHIP_INT_MODE_IS_BC(bp)) {
5731                 igu_sp_sb_index = DEF_SB_IGU_ID;
5732                 igu_seg_id = HC_SEG_ACCESS_DEF;
5733         } else {
5734                 igu_sp_sb_index = bp->igu_dsb_id;
5735                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5736         }
5737
5738         /* ATTN */
5739         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5740                                             atten_status_block);
5741         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5742
5743         bp->attn_state = 0;
5744
5745         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5746                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5747         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5748                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5749         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5750                 int sindex;
5751                 /* take care of sig[0]..sig[4] */
5752                 for (sindex = 0; sindex < 4; sindex++)
5753                         bp->attn_group[index].sig[sindex] =
5754                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5755
5756                 if (!CHIP_IS_E1x(bp))
5757                         /*
5758                          * enable5 is separate from the rest of the registers,
5759                          * and therefore the address skip is 4
5760                          * and not 16 between the different groups
5761                          */
5762                         bp->attn_group[index].sig[4] = REG_RD(bp,
5763                                         reg_offset_en5 + 0x4*index);
5764                 else
5765                         bp->attn_group[index].sig[4] = 0;
5766         }
5767
5768         if (bp->common.int_block == INT_BLOCK_HC) {
5769                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5770                                      HC_REG_ATTN_MSG0_ADDR_L);
5771
5772                 REG_WR(bp, reg_offset, U64_LO(section));
5773                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5774         } else if (!CHIP_IS_E1x(bp)) {
5775                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5776                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5777         }
5778
5779         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5780                                             sp_sb);
5781
5782         bnx2x_zero_sp_sb(bp);
5783
5784         /* PCI guarantees endianity of regpairs */
5785         sp_sb_data.state                = SB_ENABLED;
5786         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5787         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5788         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5789         sp_sb_data.igu_seg_id           = igu_seg_id;
5790         sp_sb_data.p_func.pf_id         = func;
5791         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5792         sp_sb_data.p_func.vf_id         = 0xff;
5793
5794         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5795
5796         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5797 }
5798
5799 void bnx2x_update_coalesce(struct bnx2x *bp)
5800 {
5801         int i;
5802
5803         for_each_eth_queue(bp, i)
5804                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5805                                          bp->tx_ticks, bp->rx_ticks);
5806 }
5807
5808 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5809 {
5810         spin_lock_init(&bp->spq_lock);
5811         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5812
5813         bp->spq_prod_idx = 0;
5814         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5815         bp->spq_prod_bd = bp->spq;
5816         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5817 }
5818
5819 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5820 {
5821         int i;
5822         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5823                 union event_ring_elem *elem =
5824                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5825
5826                 elem->next_page.addr.hi =
5827                         cpu_to_le32(U64_HI(bp->eq_mapping +
5828                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5829                 elem->next_page.addr.lo =
5830                         cpu_to_le32(U64_LO(bp->eq_mapping +
5831                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5832         }
5833         bp->eq_cons = 0;
5834         bp->eq_prod = NUM_EQ_DESC;
5835         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5836         /* we want a warning message before it gets wrought... */
5837         atomic_set(&bp->eq_spq_left,
5838                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5839 }
5840
5841 /* called with netif_addr_lock_bh() */
5842 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5843                         unsigned long rx_mode_flags,
5844                         unsigned long rx_accept_flags,
5845                         unsigned long tx_accept_flags,
5846                         unsigned long ramrod_flags)
5847 {
5848         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5849         int rc;
5850
5851         memset(&ramrod_param, 0, sizeof(ramrod_param));
5852
5853         /* Prepare ramrod parameters */
5854         ramrod_param.cid = 0;
5855         ramrod_param.cl_id = cl_id;
5856         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5857         ramrod_param.func_id = BP_FUNC(bp);
5858
5859         ramrod_param.pstate = &bp->sp_state;
5860         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5861
5862         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5863         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5864
5865         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5866
5867         ramrod_param.ramrod_flags = ramrod_flags;
5868         ramrod_param.rx_mode_flags = rx_mode_flags;
5869
5870         ramrod_param.rx_accept_flags = rx_accept_flags;
5871         ramrod_param.tx_accept_flags = tx_accept_flags;
5872
5873         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5874         if (rc < 0) {
5875                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5876                 return rc;
5877         }
5878
5879         return 0;
5880 }
5881
5882 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5883                                    unsigned long *rx_accept_flags,
5884                                    unsigned long *tx_accept_flags)
5885 {
5886         /* Clear the flags first */
5887         *rx_accept_flags = 0;
5888         *tx_accept_flags = 0;
5889
5890         switch (rx_mode) {
5891         case BNX2X_RX_MODE_NONE:
5892                 /*
5893                  * 'drop all' supersedes any accept flags that may have been
5894                  * passed to the function.
5895                  */
5896                 break;
5897         case BNX2X_RX_MODE_NORMAL:
5898                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5899                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5900                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5901
5902                 /* internal switching mode */
5903                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5904                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5905                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5906
5907                 break;
5908         case BNX2X_RX_MODE_ALLMULTI:
5909                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5910                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5911                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5912
5913                 /* internal switching mode */
5914                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5915                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5916                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5917
5918                 break;
5919         case BNX2X_RX_MODE_PROMISC:
5920                 /* According to definition of SI mode, iface in promisc mode
5921                  * should receive matched and unmatched (in resolution of port)
5922                  * unicast packets.
5923                  */
5924                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5925                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5926                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5927                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5928
5929                 /* internal switching mode */
5930                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5931                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5932
5933                 if (IS_MF_SI(bp))
5934                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5935                 else
5936                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5937
5938                 break;
5939         default:
5940                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5941                 return -EINVAL;
5942         }
5943
5944         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5945         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5946                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5947                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5948         }
5949
5950         return 0;
5951 }
5952
5953 /* called with netif_addr_lock_bh() */
5954 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5955 {
5956         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5957         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5958         int rc;
5959
5960         if (!NO_FCOE(bp))
5961                 /* Configure rx_mode of FCoE Queue */
5962                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5963
5964         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5965                                      &tx_accept_flags);
5966         if (rc)
5967                 return rc;
5968
5969         __set_bit(RAMROD_RX, &ramrod_flags);
5970         __set_bit(RAMROD_TX, &ramrod_flags);
5971
5972         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5973                                    rx_accept_flags, tx_accept_flags,
5974                                    ramrod_flags);
5975 }
5976
5977 static void bnx2x_init_internal_common(struct bnx2x *bp)
5978 {
5979         int i;
5980
5981         if (IS_MF_SI(bp))
5982                 /*
5983                  * In switch independent mode, the TSTORM needs to accept
5984                  * packets that failed classification, since approximate match
5985                  * mac addresses aren't written to NIG LLH
5986                  */
5987                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5988                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5989         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5990                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5991                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5992
5993         /* Zero this manually as its initialization is
5994            currently missing in the initTool */
5995         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5996                 REG_WR(bp, BAR_USTRORM_INTMEM +
5997                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5998         if (!CHIP_IS_E1x(bp)) {
5999                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6000                         CHIP_INT_MODE_IS_BC(bp) ?
6001                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6002         }
6003 }
6004
6005 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6006 {
6007         switch (load_code) {
6008         case FW_MSG_CODE_DRV_LOAD_COMMON:
6009         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6010                 bnx2x_init_internal_common(bp);
6011                 /* no break */
6012
6013         case FW_MSG_CODE_DRV_LOAD_PORT:
6014                 /* nothing to do */
6015                 /* no break */
6016
6017         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6018                 /* internal memory per function is
6019                    initialized inside bnx2x_pf_init */
6020                 break;
6021
6022         default:
6023                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6024                 break;
6025         }
6026 }
6027
6028 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6029 {
6030         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6031 }
6032
6033 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6034 {
6035         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6036 }
6037
6038 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6039 {
6040         if (CHIP_IS_E1x(fp->bp))
6041                 return BP_L_ID(fp->bp) + fp->index;
6042         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6043                 return bnx2x_fp_igu_sb_id(fp);
6044 }
6045
6046 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6047 {
6048         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6049         u8 cos;
6050         unsigned long q_type = 0;
6051         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6052         fp->rx_queue = fp_idx;
6053         fp->cid = fp_idx;
6054         fp->cl_id = bnx2x_fp_cl_id(fp);
6055         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6056         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6057         /* qZone id equals to FW (per path) client id */
6058         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6059
6060         /* init shortcut */
6061         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6062
6063         /* Setup SB indices */
6064         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6065
6066         /* Configure Queue State object */
6067         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6068         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6069
6070         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6071
6072         /* init tx data */
6073         for_each_cos_in_tx_queue(fp, cos) {
6074                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6075                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6076                                   FP_COS_TO_TXQ(fp, cos, bp),
6077                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6078                 cids[cos] = fp->txdata_ptr[cos]->cid;
6079         }
6080
6081         /* nothing more for vf to do here */
6082         if (IS_VF(bp))
6083                 return;
6084
6085         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6086                       fp->fw_sb_id, fp->igu_sb_id);
6087         bnx2x_update_fpsb_idx(fp);
6088         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6089                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6090                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6091
6092         /**
6093          * Configure classification DBs: Always enable Tx switching
6094          */
6095         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6096
6097         DP(NETIF_MSG_IFUP,
6098            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6099            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6100            fp->igu_sb_id);
6101 }
6102
6103 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6104 {
6105         int i;
6106
6107         for (i = 1; i <= NUM_TX_RINGS; i++) {
6108                 struct eth_tx_next_bd *tx_next_bd =
6109                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6110
6111                 tx_next_bd->addr_hi =
6112                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6113                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6114                 tx_next_bd->addr_lo =
6115                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6116                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6117         }
6118
6119         *txdata->tx_cons_sb = cpu_to_le16(0);
6120
6121         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6122         txdata->tx_db.data.zero_fill1 = 0;
6123         txdata->tx_db.data.prod = 0;
6124
6125         txdata->tx_pkt_prod = 0;
6126         txdata->tx_pkt_cons = 0;
6127         txdata->tx_bd_prod = 0;
6128         txdata->tx_bd_cons = 0;
6129         txdata->tx_pkt = 0;
6130 }
6131
6132 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6133 {
6134         int i;
6135
6136         for_each_tx_queue_cnic(bp, i)
6137                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6138 }
6139
6140 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6141 {
6142         int i;
6143         u8 cos;
6144
6145         for_each_eth_queue(bp, i)
6146                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6147                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6148 }
6149
6150 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6151 {
6152         if (!NO_FCOE(bp))
6153                 bnx2x_init_fcoe_fp(bp);
6154
6155         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6156                       BNX2X_VF_ID_INVALID, false,
6157                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6158
6159         /* ensure status block indices were read */
6160         rmb();
6161         bnx2x_init_rx_rings_cnic(bp);
6162         bnx2x_init_tx_rings_cnic(bp);
6163
6164         /* flush all */
6165         mb();
6166         mmiowb();
6167 }
6168
6169 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6170 {
6171         int i;
6172
6173         /* Setup NIC internals and enable interrupts */
6174         for_each_eth_queue(bp, i)
6175                 bnx2x_init_eth_fp(bp, i);
6176
6177         /* ensure status block indices were read */
6178         rmb();
6179         bnx2x_init_rx_rings(bp);
6180         bnx2x_init_tx_rings(bp);
6181
6182         if (IS_PF(bp)) {
6183                 /* Initialize MOD_ABS interrupts */
6184                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6185                                        bp->common.shmem_base,
6186                                        bp->common.shmem2_base, BP_PORT(bp));
6187
6188                 /* initialize the default status block and sp ring */
6189                 bnx2x_init_def_sb(bp);
6190                 bnx2x_update_dsb_idx(bp);
6191                 bnx2x_init_sp_ring(bp);
6192         } else {
6193                 bnx2x_memset_stats(bp);
6194         }
6195 }
6196
6197 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6198 {
6199         bnx2x_init_eq_ring(bp);
6200         bnx2x_init_internal(bp, load_code);
6201         bnx2x_pf_init(bp);
6202         bnx2x_stats_init(bp);
6203
6204         /* flush all before enabling interrupts */
6205         mb();
6206         mmiowb();
6207
6208         bnx2x_int_enable(bp);
6209
6210         /* Check for SPIO5 */
6211         bnx2x_attn_int_deasserted0(bp,
6212                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6213                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6214 }
6215
6216 /* gzip service functions */
6217 static int bnx2x_gunzip_init(struct bnx2x *bp)
6218 {
6219         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6220                                             &bp->gunzip_mapping, GFP_KERNEL);
6221         if (bp->gunzip_buf  == NULL)
6222                 goto gunzip_nomem1;
6223
6224         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6225         if (bp->strm  == NULL)
6226                 goto gunzip_nomem2;
6227
6228         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6229         if (bp->strm->workspace == NULL)
6230                 goto gunzip_nomem3;
6231
6232         return 0;
6233
6234 gunzip_nomem3:
6235         kfree(bp->strm);
6236         bp->strm = NULL;
6237
6238 gunzip_nomem2:
6239         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6240                           bp->gunzip_mapping);
6241         bp->gunzip_buf = NULL;
6242
6243 gunzip_nomem1:
6244         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6245         return -ENOMEM;
6246 }
6247
6248 static void bnx2x_gunzip_end(struct bnx2x *bp)
6249 {
6250         if (bp->strm) {
6251                 vfree(bp->strm->workspace);
6252                 kfree(bp->strm);
6253                 bp->strm = NULL;
6254         }
6255
6256         if (bp->gunzip_buf) {
6257                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6258                                   bp->gunzip_mapping);
6259                 bp->gunzip_buf = NULL;
6260         }
6261 }
6262
6263 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6264 {
6265         int n, rc;
6266
6267         /* check gzip header */
6268         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6269                 BNX2X_ERR("Bad gzip header\n");
6270                 return -EINVAL;
6271         }
6272
6273         n = 10;
6274
6275 #define FNAME                           0x8
6276
6277         if (zbuf[3] & FNAME)
6278                 while ((zbuf[n++] != 0) && (n < len));
6279
6280         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6281         bp->strm->avail_in = len - n;
6282         bp->strm->next_out = bp->gunzip_buf;
6283         bp->strm->avail_out = FW_BUF_SIZE;
6284
6285         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6286         if (rc != Z_OK)
6287                 return rc;
6288
6289         rc = zlib_inflate(bp->strm, Z_FINISH);
6290         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6291                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6292                            bp->strm->msg);
6293
6294         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6295         if (bp->gunzip_outlen & 0x3)
6296                 netdev_err(bp->dev,
6297                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6298                                 bp->gunzip_outlen);
6299         bp->gunzip_outlen >>= 2;
6300
6301         zlib_inflateEnd(bp->strm);
6302
6303         if (rc == Z_STREAM_END)
6304                 return 0;
6305
6306         return rc;
6307 }
6308
6309 /* nic load/unload */
6310
6311 /*
6312  * General service functions
6313  */
6314
6315 /* send a NIG loopback debug packet */
6316 static void bnx2x_lb_pckt(struct bnx2x *bp)
6317 {
6318         u32 wb_write[3];
6319
6320         /* Ethernet source and destination addresses */
6321         wb_write[0] = 0x55555555;
6322         wb_write[1] = 0x55555555;
6323         wb_write[2] = 0x20;             /* SOP */
6324         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6325
6326         /* NON-IP protocol */
6327         wb_write[0] = 0x09000000;
6328         wb_write[1] = 0x55555555;
6329         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6330         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6331 }
6332
6333 /* some of the internal memories
6334  * are not directly readable from the driver
6335  * to test them we send debug packets
6336  */
6337 static int bnx2x_int_mem_test(struct bnx2x *bp)
6338 {
6339         int factor;
6340         int count, i;
6341         u32 val = 0;
6342
6343         if (CHIP_REV_IS_FPGA(bp))
6344                 factor = 120;
6345         else if (CHIP_REV_IS_EMUL(bp))
6346                 factor = 200;
6347         else
6348                 factor = 1;
6349
6350         /* Disable inputs of parser neighbor blocks */
6351         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6352         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6353         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6354         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6355
6356         /*  Write 0 to parser credits for CFC search request */
6357         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6358
6359         /* send Ethernet packet */
6360         bnx2x_lb_pckt(bp);
6361
6362         /* TODO do i reset NIG statistic? */
6363         /* Wait until NIG register shows 1 packet of size 0x10 */
6364         count = 1000 * factor;
6365         while (count) {
6366
6367                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6368                 val = *bnx2x_sp(bp, wb_data[0]);
6369                 if (val == 0x10)
6370                         break;
6371
6372                 usleep_range(10000, 20000);
6373                 count--;
6374         }
6375         if (val != 0x10) {
6376                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6377                 return -1;
6378         }
6379
6380         /* Wait until PRS register shows 1 packet */
6381         count = 1000 * factor;
6382         while (count) {
6383                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6384                 if (val == 1)
6385                         break;
6386
6387                 usleep_range(10000, 20000);
6388                 count--;
6389         }
6390         if (val != 0x1) {
6391                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6392                 return -2;
6393         }
6394
6395         /* Reset and init BRB, PRS */
6396         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6397         msleep(50);
6398         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6399         msleep(50);
6400         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6401         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6402
6403         DP(NETIF_MSG_HW, "part2\n");
6404
6405         /* Disable inputs of parser neighbor blocks */
6406         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6407         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6408         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6409         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6410
6411         /* Write 0 to parser credits for CFC search request */
6412         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6413
6414         /* send 10 Ethernet packets */
6415         for (i = 0; i < 10; i++)
6416                 bnx2x_lb_pckt(bp);
6417
6418         /* Wait until NIG register shows 10 + 1
6419            packets of size 11*0x10 = 0xb0 */
6420         count = 1000 * factor;
6421         while (count) {
6422
6423                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6424                 val = *bnx2x_sp(bp, wb_data[0]);
6425                 if (val == 0xb0)
6426                         break;
6427
6428                 usleep_range(10000, 20000);
6429                 count--;
6430         }
6431         if (val != 0xb0) {
6432                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6433                 return -3;
6434         }
6435
6436         /* Wait until PRS register shows 2 packets */
6437         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6438         if (val != 2)
6439                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6440
6441         /* Write 1 to parser credits for CFC search request */
6442         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6443
6444         /* Wait until PRS register shows 3 packets */
6445         msleep(10 * factor);
6446         /* Wait until NIG register shows 1 packet of size 0x10 */
6447         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6448         if (val != 3)
6449                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6450
6451         /* clear NIG EOP FIFO */
6452         for (i = 0; i < 11; i++)
6453                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6454         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6455         if (val != 1) {
6456                 BNX2X_ERR("clear of NIG failed\n");
6457                 return -4;
6458         }
6459
6460         /* Reset and init BRB, PRS, NIG */
6461         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6462         msleep(50);
6463         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6464         msleep(50);
6465         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6466         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6467         if (!CNIC_SUPPORT(bp))
6468                 /* set NIC mode */
6469                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6470
6471         /* Enable inputs of parser neighbor blocks */
6472         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6473         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6474         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6475         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6476
6477         DP(NETIF_MSG_HW, "done\n");
6478
6479         return 0; /* OK */
6480 }
6481
6482 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6483 {
6484         u32 val;
6485
6486         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6487         if (!CHIP_IS_E1x(bp))
6488                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6489         else
6490                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6491         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6492         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6493         /*
6494          * mask read length error interrupts in brb for parser
6495          * (parsing unit and 'checksum and crc' unit)
6496          * these errors are legal (PU reads fixed length and CAC can cause
6497          * read length error on truncated packets)
6498          */
6499         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6500         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6501         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6502         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6503         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6504         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6505 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6506 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6507         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6508         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6509         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6510 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6511 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6512         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6513         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6514         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6515         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6516 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6517 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6518
6519         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6520                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6521                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6522         if (!CHIP_IS_E1x(bp))
6523                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6524                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6525         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6526
6527         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6528         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6529         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6530 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6531
6532         if (!CHIP_IS_E1x(bp))
6533                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6534                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6535
6536         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6537         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6538 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6539         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6540 }
6541
6542 static void bnx2x_reset_common(struct bnx2x *bp)
6543 {
6544         u32 val = 0x1400;
6545
6546         /* reset_common */
6547         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6548                0xd3ffff7f);
6549
6550         if (CHIP_IS_E3(bp)) {
6551                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6552                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6553         }
6554
6555         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6556 }
6557
6558 static void bnx2x_setup_dmae(struct bnx2x *bp)
6559 {
6560         bp->dmae_ready = 0;
6561         spin_lock_init(&bp->dmae_lock);
6562 }
6563
6564 static void bnx2x_init_pxp(struct bnx2x *bp)
6565 {
6566         u16 devctl;
6567         int r_order, w_order;
6568
6569         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6570         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6571         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6572         if (bp->mrrs == -1)
6573                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6574         else {
6575                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6576                 r_order = bp->mrrs;
6577         }
6578
6579         bnx2x_init_pxp_arb(bp, r_order, w_order);
6580 }
6581
6582 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6583 {
6584         int is_required;
6585         u32 val;
6586         int port;
6587
6588         if (BP_NOMCP(bp))
6589                 return;
6590
6591         is_required = 0;
6592         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6593               SHARED_HW_CFG_FAN_FAILURE_MASK;
6594
6595         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6596                 is_required = 1;
6597
6598         /*
6599          * The fan failure mechanism is usually related to the PHY type since
6600          * the power consumption of the board is affected by the PHY. Currently,
6601          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6602          */
6603         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6604                 for (port = PORT_0; port < PORT_MAX; port++) {
6605                         is_required |=
6606                                 bnx2x_fan_failure_det_req(
6607                                         bp,
6608                                         bp->common.shmem_base,
6609                                         bp->common.shmem2_base,
6610                                         port);
6611                 }
6612
6613         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6614
6615         if (is_required == 0)
6616                 return;
6617
6618         /* Fan failure is indicated by SPIO 5 */
6619         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6620
6621         /* set to active low mode */
6622         val = REG_RD(bp, MISC_REG_SPIO_INT);
6623         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6624         REG_WR(bp, MISC_REG_SPIO_INT, val);
6625
6626         /* enable interrupt to signal the IGU */
6627         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6628         val |= MISC_SPIO_SPIO5;
6629         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6630 }
6631
6632 void bnx2x_pf_disable(struct bnx2x *bp)
6633 {
6634         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6635         val &= ~IGU_PF_CONF_FUNC_EN;
6636
6637         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6638         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6639         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6640 }
6641
6642 static void bnx2x__common_init_phy(struct bnx2x *bp)
6643 {
6644         u32 shmem_base[2], shmem2_base[2];
6645         /* Avoid common init in case MFW supports LFA */
6646         if (SHMEM2_RD(bp, size) >
6647             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6648                 return;
6649         shmem_base[0] =  bp->common.shmem_base;
6650         shmem2_base[0] = bp->common.shmem2_base;
6651         if (!CHIP_IS_E1x(bp)) {
6652                 shmem_base[1] =
6653                         SHMEM2_RD(bp, other_shmem_base_addr);
6654                 shmem2_base[1] =
6655                         SHMEM2_RD(bp, other_shmem2_base_addr);
6656         }
6657         bnx2x_acquire_phy_lock(bp);
6658         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6659                               bp->common.chip_id);
6660         bnx2x_release_phy_lock(bp);
6661 }
6662
6663 /**
6664  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6665  *
6666  * @bp:         driver handle
6667  */
6668 static int bnx2x_init_hw_common(struct bnx2x *bp)
6669 {
6670         u32 val;
6671
6672         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6673
6674         /*
6675          * take the RESET lock to protect undi_unload flow from accessing
6676          * registers while we're resetting the chip
6677          */
6678         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6679
6680         bnx2x_reset_common(bp);
6681         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6682
6683         val = 0xfffc;
6684         if (CHIP_IS_E3(bp)) {
6685                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6686                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6687         }
6688         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6689
6690         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6691
6692         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6693
6694         if (!CHIP_IS_E1x(bp)) {
6695                 u8 abs_func_id;
6696
6697                 /**
6698                  * 4-port mode or 2-port mode we need to turn of master-enable
6699                  * for everyone, after that, turn it back on for self.
6700                  * so, we disregard multi-function or not, and always disable
6701                  * for all functions on the given path, this means 0,2,4,6 for
6702                  * path 0 and 1,3,5,7 for path 1
6703                  */
6704                 for (abs_func_id = BP_PATH(bp);
6705                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6706                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6707                                 REG_WR(bp,
6708                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6709                                     1);
6710                                 continue;
6711                         }
6712
6713                         bnx2x_pretend_func(bp, abs_func_id);
6714                         /* clear pf enable */
6715                         bnx2x_pf_disable(bp);
6716                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6717                 }
6718         }
6719
6720         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6721         if (CHIP_IS_E1(bp)) {
6722                 /* enable HW interrupt from PXP on USDM overflow
6723                    bit 16 on INT_MASK_0 */
6724                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6725         }
6726
6727         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6728         bnx2x_init_pxp(bp);
6729
6730 #ifdef __BIG_ENDIAN
6731         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6732         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6733         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6734         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6735         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6736         /* make sure this value is 0 */
6737         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6738
6739 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6740         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6741         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6742         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6743         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6744 #endif
6745
6746         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6747
6748         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6749                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6750
6751         /* let the HW do it's magic ... */
6752         msleep(100);
6753         /* finish PXP init */
6754         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6755         if (val != 1) {
6756                 BNX2X_ERR("PXP2 CFG failed\n");
6757                 return -EBUSY;
6758         }
6759         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6760         if (val != 1) {
6761                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6762                 return -EBUSY;
6763         }
6764
6765         /* Timers bug workaround E2 only. We need to set the entire ILT to
6766          * have entries with value "0" and valid bit on.
6767          * This needs to be done by the first PF that is loaded in a path
6768          * (i.e. common phase)
6769          */
6770         if (!CHIP_IS_E1x(bp)) {
6771 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6772  * (i.e. vnic3) to start even if it is marked as "scan-off".
6773  * This occurs when a different function (func2,3) is being marked
6774  * as "scan-off". Real-life scenario for example: if a driver is being
6775  * load-unloaded while func6,7 are down. This will cause the timer to access
6776  * the ilt, translate to a logical address and send a request to read/write.
6777  * Since the ilt for the function that is down is not valid, this will cause
6778  * a translation error which is unrecoverable.
6779  * The Workaround is intended to make sure that when this happens nothing fatal
6780  * will occur. The workaround:
6781  *      1.  First PF driver which loads on a path will:
6782  *              a.  After taking the chip out of reset, by using pretend,
6783  *                  it will write "0" to the following registers of
6784  *                  the other vnics.
6785  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6786  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6787  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6788  *                  And for itself it will write '1' to
6789  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6790  *                  dmae-operations (writing to pram for example.)
6791  *                  note: can be done for only function 6,7 but cleaner this
6792  *                        way.
6793  *              b.  Write zero+valid to the entire ILT.
6794  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6795  *                  VNIC3 (of that port). The range allocated will be the
6796  *                  entire ILT. This is needed to prevent  ILT range error.
6797  *      2.  Any PF driver load flow:
6798  *              a.  ILT update with the physical addresses of the allocated
6799  *                  logical pages.
6800  *              b.  Wait 20msec. - note that this timeout is needed to make
6801  *                  sure there are no requests in one of the PXP internal
6802  *                  queues with "old" ILT addresses.
6803  *              c.  PF enable in the PGLC.
6804  *              d.  Clear the was_error of the PF in the PGLC. (could have
6805  *                  occurred while driver was down)
6806  *              e.  PF enable in the CFC (WEAK + STRONG)
6807  *              f.  Timers scan enable
6808  *      3.  PF driver unload flow:
6809  *              a.  Clear the Timers scan_en.
6810  *              b.  Polling for scan_on=0 for that PF.
6811  *              c.  Clear the PF enable bit in the PXP.
6812  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6813  *              e.  Write zero+valid to all ILT entries (The valid bit must
6814  *                  stay set)
6815  *              f.  If this is VNIC 3 of a port then also init
6816  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6817  *                  to the last entry in the ILT.
6818  *
6819  *      Notes:
6820  *      Currently the PF error in the PGLC is non recoverable.
6821  *      In the future the there will be a recovery routine for this error.
6822  *      Currently attention is masked.
6823  *      Having an MCP lock on the load/unload process does not guarantee that
6824  *      there is no Timer disable during Func6/7 enable. This is because the
6825  *      Timers scan is currently being cleared by the MCP on FLR.
6826  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6827  *      there is error before clearing it. But the flow above is simpler and
6828  *      more general.
6829  *      All ILT entries are written by zero+valid and not just PF6/7
6830  *      ILT entries since in the future the ILT entries allocation for
6831  *      PF-s might be dynamic.
6832  */
6833                 struct ilt_client_info ilt_cli;
6834                 struct bnx2x_ilt ilt;
6835                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6836                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6837
6838                 /* initialize dummy TM client */
6839                 ilt_cli.start = 0;
6840                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6841                 ilt_cli.client_num = ILT_CLIENT_TM;
6842
6843                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6844                  * Step 2: set the timers first/last ilt entry to point
6845                  * to the entire range to prevent ILT range error for 3rd/4th
6846                  * vnic (this code assumes existence of the vnic)
6847                  *
6848                  * both steps performed by call to bnx2x_ilt_client_init_op()
6849                  * with dummy TM client
6850                  *
6851                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6852                  * and his brother are split registers
6853                  */
6854                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6855                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6856                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6857
6858                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6859                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6860                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6861         }
6862
6863         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6864         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6865
6866         if (!CHIP_IS_E1x(bp)) {
6867                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6868                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6869                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6870
6871                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6872
6873                 /* let the HW do it's magic ... */
6874                 do {
6875                         msleep(200);
6876                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6877                 } while (factor-- && (val != 1));
6878
6879                 if (val != 1) {
6880                         BNX2X_ERR("ATC_INIT failed\n");
6881                         return -EBUSY;
6882                 }
6883         }
6884
6885         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6886
6887         bnx2x_iov_init_dmae(bp);
6888
6889         /* clean the DMAE memory */
6890         bp->dmae_ready = 1;
6891         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6892
6893         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6894
6895         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6896
6897         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6898
6899         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6900
6901         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6902         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6903         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6904         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6905
6906         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6907
6908         /* QM queues pointers table */
6909         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6910
6911         /* soft reset pulse */
6912         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6913         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6914
6915         if (CNIC_SUPPORT(bp))
6916                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6917
6918         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6919
6920         if (!CHIP_REV_IS_SLOW(bp))
6921                 /* enable hw interrupt from doorbell Q */
6922                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6923
6924         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6925
6926         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6927         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6928
6929         if (!CHIP_IS_E1(bp))
6930                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6931
6932         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6933                 if (IS_MF_AFEX(bp)) {
6934                         /* configure that VNTag and VLAN headers must be
6935                          * received in afex mode
6936                          */
6937                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6938                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6939                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6940                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6941                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6942                 } else {
6943                         /* Bit-map indicating which L2 hdrs may appear
6944                          * after the basic Ethernet header
6945                          */
6946                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6947                                bp->path_has_ovlan ? 7 : 6);
6948                 }
6949         }
6950
6951         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6952         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6953         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6954         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6955
6956         if (!CHIP_IS_E1x(bp)) {
6957                 /* reset VFC memories */
6958                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6959                            VFC_MEMORIES_RST_REG_CAM_RST |
6960                            VFC_MEMORIES_RST_REG_RAM_RST);
6961                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6962                            VFC_MEMORIES_RST_REG_CAM_RST |
6963                            VFC_MEMORIES_RST_REG_RAM_RST);
6964
6965                 msleep(20);
6966         }
6967
6968         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6969         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6970         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6971         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6972
6973         /* sync semi rtc */
6974         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6975                0x80000000);
6976         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6977                0x80000000);
6978
6979         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6980         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6981         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6982
6983         if (!CHIP_IS_E1x(bp)) {
6984                 if (IS_MF_AFEX(bp)) {
6985                         /* configure that VNTag and VLAN headers must be
6986                          * sent in afex mode
6987                          */
6988                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6989                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6990                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6991                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6992                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6993                 } else {
6994                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6995                                bp->path_has_ovlan ? 7 : 6);
6996                 }
6997         }
6998
6999         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7000
7001         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7002
7003         if (CNIC_SUPPORT(bp)) {
7004                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7005                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7006                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7007                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7008                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7009                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7010                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7011                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7012                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7013                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7014         }
7015         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7016
7017         if (sizeof(union cdu_context) != 1024)
7018                 /* we currently assume that a context is 1024 bytes */
7019                 dev_alert(&bp->pdev->dev,
7020                           "please adjust the size of cdu_context(%ld)\n",
7021                           (long)sizeof(union cdu_context));
7022
7023         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7024         val = (4 << 24) + (0 << 12) + 1024;
7025         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7026
7027         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7028         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7029         /* enable context validation interrupt from CFC */
7030         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7031
7032         /* set the thresholds to prevent CFC/CDU race */
7033         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7034
7035         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7036
7037         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7038                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7039
7040         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7041         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7042
7043         /* Reset PCIE errors for debug */
7044         REG_WR(bp, 0x2814, 0xffffffff);
7045         REG_WR(bp, 0x3820, 0xffffffff);
7046
7047         if (!CHIP_IS_E1x(bp)) {
7048                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7049                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7050                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7051                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7052                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7053                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7054                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7055                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7056                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7057                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7058                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7059         }
7060
7061         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7062         if (!CHIP_IS_E1(bp)) {
7063                 /* in E3 this done in per-port section */
7064                 if (!CHIP_IS_E3(bp))
7065                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7066         }
7067         if (CHIP_IS_E1H(bp))
7068                 /* not applicable for E2 (and above ...) */
7069                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7070
7071         if (CHIP_REV_IS_SLOW(bp))
7072                 msleep(200);
7073
7074         /* finish CFC init */
7075         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7076         if (val != 1) {
7077                 BNX2X_ERR("CFC LL_INIT failed\n");
7078                 return -EBUSY;
7079         }
7080         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7081         if (val != 1) {
7082                 BNX2X_ERR("CFC AC_INIT failed\n");
7083                 return -EBUSY;
7084         }
7085         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7086         if (val != 1) {
7087                 BNX2X_ERR("CFC CAM_INIT failed\n");
7088                 return -EBUSY;
7089         }
7090         REG_WR(bp, CFC_REG_DEBUG0, 0);
7091
7092         if (CHIP_IS_E1(bp)) {
7093                 /* read NIG statistic
7094                    to see if this is our first up since powerup */
7095                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7096                 val = *bnx2x_sp(bp, wb_data[0]);
7097
7098                 /* do internal memory self test */
7099                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7100                         BNX2X_ERR("internal mem self test failed\n");
7101                         return -EBUSY;
7102                 }
7103         }
7104
7105         bnx2x_setup_fan_failure_detection(bp);
7106
7107         /* clear PXP2 attentions */
7108         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7109
7110         bnx2x_enable_blocks_attention(bp);
7111         bnx2x_enable_blocks_parity(bp);
7112
7113         if (!BP_NOMCP(bp)) {
7114                 if (CHIP_IS_E1x(bp))
7115                         bnx2x__common_init_phy(bp);
7116         } else
7117                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7118
7119         return 0;
7120 }
7121
7122 /**
7123  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7124  *
7125  * @bp:         driver handle
7126  */
7127 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7128 {
7129         int rc = bnx2x_init_hw_common(bp);
7130
7131         if (rc)
7132                 return rc;
7133
7134         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7135         if (!BP_NOMCP(bp))
7136                 bnx2x__common_init_phy(bp);
7137
7138         return 0;
7139 }
7140
7141 static int bnx2x_init_hw_port(struct bnx2x *bp)
7142 {
7143         int port = BP_PORT(bp);
7144         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7145         u32 low, high;
7146         u32 val;
7147
7148         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7149
7150         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7151
7152         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7153         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7154         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7155
7156         /* Timers bug workaround: disables the pf_master bit in pglue at
7157          * common phase, we need to enable it here before any dmae access are
7158          * attempted. Therefore we manually added the enable-master to the
7159          * port phase (it also happens in the function phase)
7160          */
7161         if (!CHIP_IS_E1x(bp))
7162                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7163
7164         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7165         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7166         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7167         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7168
7169         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7170         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7171         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7172         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7173
7174         /* QM cid (connection) count */
7175         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7176
7177         if (CNIC_SUPPORT(bp)) {
7178                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7179                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7180                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7181         }
7182
7183         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7184
7185         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7186
7187         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7188
7189                 if (IS_MF(bp))
7190                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7191                 else if (bp->dev->mtu > 4096) {
7192                         if (bp->flags & ONE_PORT_FLAG)
7193                                 low = 160;
7194                         else {
7195                                 val = bp->dev->mtu;
7196                                 /* (24*1024 + val*4)/256 */
7197                                 low = 96 + (val/64) +
7198                                                 ((val % 64) ? 1 : 0);
7199                         }
7200                 } else
7201                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7202                 high = low + 56;        /* 14*1024/256 */
7203                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7204                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7205         }
7206
7207         if (CHIP_MODE_IS_4_PORT(bp))
7208                 REG_WR(bp, (BP_PORT(bp) ?
7209                             BRB1_REG_MAC_GUARANTIED_1 :
7210                             BRB1_REG_MAC_GUARANTIED_0), 40);
7211
7212         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7213         if (CHIP_IS_E3B0(bp)) {
7214                 if (IS_MF_AFEX(bp)) {
7215                         /* configure headers for AFEX mode */
7216                         REG_WR(bp, BP_PORT(bp) ?
7217                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7218                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7219                         REG_WR(bp, BP_PORT(bp) ?
7220                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7221                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7222                         REG_WR(bp, BP_PORT(bp) ?
7223                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7224                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7225                 } else {
7226                         /* Ovlan exists only if we are in multi-function +
7227                          * switch-dependent mode, in switch-independent there
7228                          * is no ovlan headers
7229                          */
7230                         REG_WR(bp, BP_PORT(bp) ?
7231                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7232                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7233                                (bp->path_has_ovlan ? 7 : 6));
7234                 }
7235         }
7236
7237         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7238         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7239         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7240         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7241
7242         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7243         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7244         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7245         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7246
7247         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7248         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7249
7250         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7251
7252         if (CHIP_IS_E1x(bp)) {
7253                 /* configure PBF to work without PAUSE mtu 9000 */
7254                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7255
7256                 /* update threshold */
7257                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7258                 /* update init credit */
7259                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7260
7261                 /* probe changes */
7262                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7263                 udelay(50);
7264                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7265         }
7266
7267         if (CNIC_SUPPORT(bp))
7268                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7269
7270         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7271         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7272
7273         if (CHIP_IS_E1(bp)) {
7274                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7275                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7276         }
7277         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7278
7279         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7280
7281         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7282         /* init aeu_mask_attn_func_0/1:
7283          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7284          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7285          *             bits 4-7 are used for "per vn group attention" */
7286         val = IS_MF(bp) ? 0xF7 : 0x7;
7287         /* Enable DCBX attention for all but E1 */
7288         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7289         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7290
7291         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7292
7293         if (!CHIP_IS_E1x(bp)) {
7294                 /* Bit-map indicating which L2 hdrs may appear after the
7295                  * basic Ethernet header
7296                  */
7297                 if (IS_MF_AFEX(bp))
7298                         REG_WR(bp, BP_PORT(bp) ?
7299                                NIG_REG_P1_HDRS_AFTER_BASIC :
7300                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7301                 else
7302                         REG_WR(bp, BP_PORT(bp) ?
7303                                NIG_REG_P1_HDRS_AFTER_BASIC :
7304                                NIG_REG_P0_HDRS_AFTER_BASIC,
7305                                IS_MF_SD(bp) ? 7 : 6);
7306
7307                 if (CHIP_IS_E3(bp))
7308                         REG_WR(bp, BP_PORT(bp) ?
7309                                    NIG_REG_LLH1_MF_MODE :
7310                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7311         }
7312         if (!CHIP_IS_E3(bp))
7313                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7314
7315         if (!CHIP_IS_E1(bp)) {
7316                 /* 0x2 disable mf_ov, 0x1 enable */
7317                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7318                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7319
7320                 if (!CHIP_IS_E1x(bp)) {
7321                         val = 0;
7322                         switch (bp->mf_mode) {
7323                         case MULTI_FUNCTION_SD:
7324                                 val = 1;
7325                                 break;
7326                         case MULTI_FUNCTION_SI:
7327                         case MULTI_FUNCTION_AFEX:
7328                                 val = 2;
7329                                 break;
7330                         }
7331
7332                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7333                                                   NIG_REG_LLH0_CLS_TYPE), val);
7334                 }
7335                 {
7336                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7337                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7338                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7339                 }
7340         }
7341
7342         /* If SPIO5 is set to generate interrupts, enable it for this port */
7343         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7344         if (val & MISC_SPIO_SPIO5) {
7345                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7346                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7347                 val = REG_RD(bp, reg_addr);
7348                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7349                 REG_WR(bp, reg_addr, val);
7350         }
7351
7352         return 0;
7353 }
7354
7355 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7356 {
7357         int reg;
7358         u32 wb_write[2];
7359
7360         if (CHIP_IS_E1(bp))
7361                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7362         else
7363                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7364
7365         wb_write[0] = ONCHIP_ADDR1(addr);
7366         wb_write[1] = ONCHIP_ADDR2(addr);
7367         REG_WR_DMAE(bp, reg, wb_write, 2);
7368 }
7369
7370 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7371 {
7372         u32 data, ctl, cnt = 100;
7373         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7374         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7375         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7376         u32 sb_bit =  1 << (idu_sb_id%32);
7377         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7378         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7379
7380         /* Not supported in BC mode */
7381         if (CHIP_INT_MODE_IS_BC(bp))
7382                 return;
7383
7384         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7385                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7386                 IGU_REGULAR_CLEANUP_SET                         |
7387                 IGU_REGULAR_BCLEANUP;
7388
7389         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7390               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7391               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7392
7393         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7394                          data, igu_addr_data);
7395         REG_WR(bp, igu_addr_data, data);
7396         mmiowb();
7397         barrier();
7398         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7399                           ctl, igu_addr_ctl);
7400         REG_WR(bp, igu_addr_ctl, ctl);
7401         mmiowb();
7402         barrier();
7403
7404         /* wait for clean up to finish */
7405         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7406                 msleep(20);
7407
7408         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7409                 DP(NETIF_MSG_HW,
7410                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7411                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7412         }
7413 }
7414
7415 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7416 {
7417         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7418 }
7419
7420 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7421 {
7422         u32 i, base = FUNC_ILT_BASE(func);
7423         for (i = base; i < base + ILT_PER_FUNC; i++)
7424                 bnx2x_ilt_wr(bp, i, 0);
7425 }
7426
7427 static void bnx2x_init_searcher(struct bnx2x *bp)
7428 {
7429         int port = BP_PORT(bp);
7430         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7431         /* T1 hash bits value determines the T1 number of entries */
7432         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7433 }
7434
7435 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7436 {
7437         int rc;
7438         struct bnx2x_func_state_params func_params = {NULL};
7439         struct bnx2x_func_switch_update_params *switch_update_params =
7440                 &func_params.params.switch_update;
7441
7442         /* Prepare parameters for function state transitions */
7443         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7444         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7445
7446         func_params.f_obj = &bp->func_obj;
7447         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7448
7449         /* Function parameters */
7450         switch_update_params->suspend = suspend;
7451
7452         rc = bnx2x_func_state_change(bp, &func_params);
7453
7454         return rc;
7455 }
7456
7457 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7458 {
7459         int rc, i, port = BP_PORT(bp);
7460         int vlan_en = 0, mac_en[NUM_MACS];
7461
7462         /* Close input from network */
7463         if (bp->mf_mode == SINGLE_FUNCTION) {
7464                 bnx2x_set_rx_filter(&bp->link_params, 0);
7465         } else {
7466                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7467                                    NIG_REG_LLH0_FUNC_EN);
7468                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7469                           NIG_REG_LLH0_FUNC_EN, 0);
7470                 for (i = 0; i < NUM_MACS; i++) {
7471                         mac_en[i] = REG_RD(bp, port ?
7472                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7473                                               4 * i) :
7474                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7475                                               4 * i));
7476                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7477                                               4 * i) :
7478                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7479                 }
7480         }
7481
7482         /* Close BMC to host */
7483         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7484                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7485
7486         /* Suspend Tx switching to the PF. Completion of this ramrod
7487          * further guarantees that all the packets of that PF / child
7488          * VFs in BRB were processed by the Parser, so it is safe to
7489          * change the NIC_MODE register.
7490          */
7491         rc = bnx2x_func_switch_update(bp, 1);
7492         if (rc) {
7493                 BNX2X_ERR("Can't suspend tx-switching!\n");
7494                 return rc;
7495         }
7496
7497         /* Change NIC_MODE register */
7498         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7499
7500         /* Open input from network */
7501         if (bp->mf_mode == SINGLE_FUNCTION) {
7502                 bnx2x_set_rx_filter(&bp->link_params, 1);
7503         } else {
7504                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7505                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7506                 for (i = 0; i < NUM_MACS; i++) {
7507                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7508                                               4 * i) :
7509                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7510                                   mac_en[i]);
7511                 }
7512         }
7513
7514         /* Enable BMC to host */
7515         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7516                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7517
7518         /* Resume Tx switching to the PF */
7519         rc = bnx2x_func_switch_update(bp, 0);
7520         if (rc) {
7521                 BNX2X_ERR("Can't resume tx-switching!\n");
7522                 return rc;
7523         }
7524
7525         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7526         return 0;
7527 }
7528
7529 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7530 {
7531         int rc;
7532
7533         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7534
7535         if (CONFIGURE_NIC_MODE(bp)) {
7536                 /* Configure searcher as part of function hw init */
7537                 bnx2x_init_searcher(bp);
7538
7539                 /* Reset NIC mode */
7540                 rc = bnx2x_reset_nic_mode(bp);
7541                 if (rc)
7542                         BNX2X_ERR("Can't change NIC mode!\n");
7543                 return rc;
7544         }
7545
7546         return 0;
7547 }
7548
7549 static int bnx2x_init_hw_func(struct bnx2x *bp)
7550 {
7551         int port = BP_PORT(bp);
7552         int func = BP_FUNC(bp);
7553         int init_phase = PHASE_PF0 + func;
7554         struct bnx2x_ilt *ilt = BP_ILT(bp);
7555         u16 cdu_ilt_start;
7556         u32 addr, val;
7557         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7558         int i, main_mem_width, rc;
7559
7560         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7561
7562         /* FLR cleanup - hmmm */
7563         if (!CHIP_IS_E1x(bp)) {
7564                 rc = bnx2x_pf_flr_clnup(bp);
7565                 if (rc) {
7566                         bnx2x_fw_dump(bp);
7567                         return rc;
7568                 }
7569         }
7570
7571         /* set MSI reconfigure capability */
7572         if (bp->common.int_block == INT_BLOCK_HC) {
7573                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7574                 val = REG_RD(bp, addr);
7575                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7576                 REG_WR(bp, addr, val);
7577         }
7578
7579         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7580         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7581
7582         ilt = BP_ILT(bp);
7583         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7584
7585         if (IS_SRIOV(bp))
7586                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7587         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7588
7589         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7590          * those of the VFs, so start line should be reset
7591          */
7592         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7593         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7594                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7595                 ilt->lines[cdu_ilt_start + i].page_mapping =
7596                         bp->context[i].cxt_mapping;
7597                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7598         }
7599
7600         bnx2x_ilt_init_op(bp, INITOP_SET);
7601
7602         if (!CONFIGURE_NIC_MODE(bp)) {
7603                 bnx2x_init_searcher(bp);
7604                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7605                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7606         } else {
7607                 /* Set NIC mode */
7608                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7609                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7610         }
7611
7612         if (!CHIP_IS_E1x(bp)) {
7613                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7614
7615                 /* Turn on a single ISR mode in IGU if driver is going to use
7616                  * INT#x or MSI
7617                  */
7618                 if (!(bp->flags & USING_MSIX_FLAG))
7619                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7620                 /*
7621                  * Timers workaround bug: function init part.
7622                  * Need to wait 20msec after initializing ILT,
7623                  * needed to make sure there are no requests in
7624                  * one of the PXP internal queues with "old" ILT addresses
7625                  */
7626                 msleep(20);
7627                 /*
7628                  * Master enable - Due to WB DMAE writes performed before this
7629                  * register is re-initialized as part of the regular function
7630                  * init
7631                  */
7632                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7633                 /* Enable the function in IGU */
7634                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7635         }
7636
7637         bp->dmae_ready = 1;
7638
7639         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7640
7641         if (!CHIP_IS_E1x(bp))
7642                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7643
7644         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7645         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7646         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7647         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7648         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7649         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7650         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7651         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7652         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7653         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7654         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7655         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7656         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7657
7658         if (!CHIP_IS_E1x(bp))
7659                 REG_WR(bp, QM_REG_PF_EN, 1);
7660
7661         if (!CHIP_IS_E1x(bp)) {
7662                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7663                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7664                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7665                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7666         }
7667         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7668
7669         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7670         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7671         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7672
7673         bnx2x_iov_init_dq(bp);
7674
7675         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7676         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7677         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7678         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7679         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7680         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7681         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7682         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7683         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7684         if (!CHIP_IS_E1x(bp))
7685                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7686
7687         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7688
7689         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7690
7691         if (!CHIP_IS_E1x(bp))
7692                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7693
7694         if (IS_MF(bp)) {
7695                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7696                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7697         }
7698
7699         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7700
7701         /* HC init per function */
7702         if (bp->common.int_block == INT_BLOCK_HC) {
7703                 if (CHIP_IS_E1H(bp)) {
7704                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7705
7706                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7707                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7708                 }
7709                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7710
7711         } else {
7712                 int num_segs, sb_idx, prod_offset;
7713
7714                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7715
7716                 if (!CHIP_IS_E1x(bp)) {
7717                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7718                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7719                 }
7720
7721                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7722
7723                 if (!CHIP_IS_E1x(bp)) {
7724                         int dsb_idx = 0;
7725                         /**
7726                          * Producer memory:
7727                          * E2 mode: address 0-135 match to the mapping memory;
7728                          * 136 - PF0 default prod; 137 - PF1 default prod;
7729                          * 138 - PF2 default prod; 139 - PF3 default prod;
7730                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7731                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7732                          * 144-147 reserved.
7733                          *
7734                          * E1.5 mode - In backward compatible mode;
7735                          * for non default SB; each even line in the memory
7736                          * holds the U producer and each odd line hold
7737                          * the C producer. The first 128 producers are for
7738                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7739                          * producers are for the DSB for each PF.
7740                          * Each PF has five segments: (the order inside each
7741                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7742                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7743                          * 144-147 attn prods;
7744                          */
7745                         /* non-default-status-blocks */
7746                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7747                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7748                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7749                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7750                                         num_segs;
7751
7752                                 for (i = 0; i < num_segs; i++) {
7753                                         addr = IGU_REG_PROD_CONS_MEMORY +
7754                                                         (prod_offset + i) * 4;
7755                                         REG_WR(bp, addr, 0);
7756                                 }
7757                                 /* send consumer update with value 0 */
7758                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7759                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7760                                 bnx2x_igu_clear_sb(bp,
7761                                                    bp->igu_base_sb + sb_idx);
7762                         }
7763
7764                         /* default-status-blocks */
7765                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7766                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7767
7768                         if (CHIP_MODE_IS_4_PORT(bp))
7769                                 dsb_idx = BP_FUNC(bp);
7770                         else
7771                                 dsb_idx = BP_VN(bp);
7772
7773                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7774                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7775                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7776
7777                         /*
7778                          * igu prods come in chunks of E1HVN_MAX (4) -
7779                          * does not matters what is the current chip mode
7780                          */
7781                         for (i = 0; i < (num_segs * E1HVN_MAX);
7782                              i += E1HVN_MAX) {
7783                                 addr = IGU_REG_PROD_CONS_MEMORY +
7784                                                         (prod_offset + i)*4;
7785                                 REG_WR(bp, addr, 0);
7786                         }
7787                         /* send consumer update with 0 */
7788                         if (CHIP_INT_MODE_IS_BC(bp)) {
7789                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7790                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7791                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7792                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7793                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7794                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7795                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7796                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7797                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7798                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7799                         } else {
7800                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7801                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7802                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7803                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7804                         }
7805                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7806
7807                         /* !!! These should become driver const once
7808                            rf-tool supports split-68 const */
7809                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7810                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7811                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7812                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7813                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7814                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7815                 }
7816         }
7817
7818         /* Reset PCIE errors for debug */
7819         REG_WR(bp, 0x2114, 0xffffffff);
7820         REG_WR(bp, 0x2120, 0xffffffff);
7821
7822         if (CHIP_IS_E1x(bp)) {
7823                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7824                 main_mem_base = HC_REG_MAIN_MEMORY +
7825                                 BP_PORT(bp) * (main_mem_size * 4);
7826                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7827                 main_mem_width = 8;
7828
7829                 val = REG_RD(bp, main_mem_prty_clr);
7830                 if (val)
7831                         DP(NETIF_MSG_HW,
7832                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7833                            val);
7834
7835                 /* Clear "false" parity errors in MSI-X table */
7836                 for (i = main_mem_base;
7837                      i < main_mem_base + main_mem_size * 4;
7838                      i += main_mem_width) {
7839                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7840                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7841                                          i, main_mem_width / 4);
7842                 }
7843                 /* Clear HC parity attention */
7844                 REG_RD(bp, main_mem_prty_clr);
7845         }
7846
7847 #ifdef BNX2X_STOP_ON_ERROR
7848         /* Enable STORMs SP logging */
7849         REG_WR8(bp, BAR_USTRORM_INTMEM +
7850                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7851         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7852                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7853         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7854                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7855         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7856                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7857 #endif
7858
7859         bnx2x_phy_probe(&bp->link_params);
7860
7861         return 0;
7862 }
7863
7864 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7865 {
7866         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7867
7868         if (!CHIP_IS_E1x(bp))
7869                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7870                                sizeof(struct host_hc_status_block_e2));
7871         else
7872                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7873                                sizeof(struct host_hc_status_block_e1x));
7874
7875         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7876 }
7877
7878 void bnx2x_free_mem(struct bnx2x *bp)
7879 {
7880         int i;
7881
7882         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7883                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7884
7885         if (IS_VF(bp))
7886                 return;
7887
7888         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7889                        sizeof(struct host_sp_status_block));
7890
7891         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7892                        sizeof(struct bnx2x_slowpath));
7893
7894         for (i = 0; i < L2_ILT_LINES(bp); i++)
7895                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7896                                bp->context[i].size);
7897         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7898
7899         BNX2X_FREE(bp->ilt->lines);
7900
7901         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7902
7903         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7904                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7905
7906         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7907
7908         bnx2x_iov_free_mem(bp);
7909 }
7910
7911 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7912 {
7913         if (!CHIP_IS_E1x(bp))
7914                 /* size = the status block + ramrod buffers */
7915                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7916                                 sizeof(struct host_hc_status_block_e2));
7917         else
7918                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7919                                 &bp->cnic_sb_mapping,
7920                                 sizeof(struct
7921                                        host_hc_status_block_e1x));
7922
7923         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7924                 /* allocate searcher T2 table, as it wasn't allocated before */
7925                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7926
7927         /* write address to which L5 should insert its values */
7928         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7929                 &bp->slowpath->drv_info_to_mcp;
7930
7931         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7932                 goto alloc_mem_err;
7933
7934         return 0;
7935
7936 alloc_mem_err:
7937         bnx2x_free_mem_cnic(bp);
7938         BNX2X_ERR("Can't allocate memory\n");
7939         return -ENOMEM;
7940 }
7941
7942 int bnx2x_alloc_mem(struct bnx2x *bp)
7943 {
7944         int i, allocated, context_size;
7945
7946         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7947                 /* allocate searcher T2 table */
7948                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7949
7950         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7951                         sizeof(struct host_sp_status_block));
7952
7953         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7954                         sizeof(struct bnx2x_slowpath));
7955
7956         /* Allocate memory for CDU context:
7957          * This memory is allocated separately and not in the generic ILT
7958          * functions because CDU differs in few aspects:
7959          * 1. There are multiple entities allocating memory for context -
7960          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7961          * its own ILT lines.
7962          * 2. Since CDU page-size is not a single 4KB page (which is the case
7963          * for the other ILT clients), to be efficient we want to support
7964          * allocation of sub-page-size in the last entry.
7965          * 3. Context pointers are used by the driver to pass to FW / update
7966          * the context (for the other ILT clients the pointers are used just to
7967          * free the memory during unload).
7968          */
7969         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7970
7971         for (i = 0, allocated = 0; allocated < context_size; i++) {
7972                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7973                                           (context_size - allocated));
7974                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7975                                 &bp->context[i].cxt_mapping,
7976                                 bp->context[i].size);
7977                 allocated += bp->context[i].size;
7978         }
7979         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7980
7981         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7982                 goto alloc_mem_err;
7983
7984         if (bnx2x_iov_alloc_mem(bp))
7985                 goto alloc_mem_err;
7986
7987         /* Slow path ring */
7988         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7989
7990         /* EQ */
7991         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7992                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7993
7994         return 0;
7995
7996 alloc_mem_err:
7997         bnx2x_free_mem(bp);
7998         BNX2X_ERR("Can't allocate memory\n");
7999         return -ENOMEM;
8000 }
8001
8002 /*
8003  * Init service functions
8004  */
8005
8006 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8007                       struct bnx2x_vlan_mac_obj *obj, bool set,
8008                       int mac_type, unsigned long *ramrod_flags)
8009 {
8010         int rc;
8011         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8012
8013         memset(&ramrod_param, 0, sizeof(ramrod_param));
8014
8015         /* Fill general parameters */
8016         ramrod_param.vlan_mac_obj = obj;
8017         ramrod_param.ramrod_flags = *ramrod_flags;
8018
8019         /* Fill a user request section if needed */
8020         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8021                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8022
8023                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8024
8025                 /* Set the command: ADD or DEL */
8026                 if (set)
8027                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8028                 else
8029                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8030         }
8031
8032         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8033
8034         if (rc == -EEXIST) {
8035                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8036                 /* do not treat adding same MAC as error */
8037                 rc = 0;
8038         } else if (rc < 0)
8039                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8040
8041         return rc;
8042 }
8043
8044 int bnx2x_del_all_macs(struct bnx2x *bp,
8045                        struct bnx2x_vlan_mac_obj *mac_obj,
8046                        int mac_type, bool wait_for_comp)
8047 {
8048         int rc;
8049         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8050
8051         /* Wait for completion of requested */
8052         if (wait_for_comp)
8053                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8054
8055         /* Set the mac type of addresses we want to clear */
8056         __set_bit(mac_type, &vlan_mac_flags);
8057
8058         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8059         if (rc < 0)
8060                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8061
8062         return rc;
8063 }
8064
8065 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8066 {
8067         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8068             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8069                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8070                    "Ignoring Zero MAC for STORAGE SD mode\n");
8071                 return 0;
8072         }
8073
8074         if (IS_PF(bp)) {
8075                 unsigned long ramrod_flags = 0;
8076
8077                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8078                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8079                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8080                                          &bp->sp_objs->mac_obj, set,
8081                                          BNX2X_ETH_MAC, &ramrod_flags);
8082         } else { /* vf */
8083                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8084                                              bp->fp->index, true);
8085         }
8086 }
8087
8088 int bnx2x_setup_leading(struct bnx2x *bp)
8089 {
8090         if (IS_PF(bp))
8091                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8092         else /* VF */
8093                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8094 }
8095
8096 /**
8097  * bnx2x_set_int_mode - configure interrupt mode
8098  *
8099  * @bp:         driver handle
8100  *
8101  * In case of MSI-X it will also try to enable MSI-X.
8102  */
8103 int bnx2x_set_int_mode(struct bnx2x *bp)
8104 {
8105         int rc = 0;
8106
8107         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8108                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8109                 return -EINVAL;
8110         }
8111
8112         switch (int_mode) {
8113         case BNX2X_INT_MODE_MSIX:
8114                 /* attempt to enable msix */
8115                 rc = bnx2x_enable_msix(bp);
8116
8117                 /* msix attained */
8118                 if (!rc)
8119                         return 0;
8120
8121                 /* vfs use only msix */
8122                 if (rc && IS_VF(bp))
8123                         return rc;
8124
8125                 /* failed to enable multiple MSI-X */
8126                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8127                                bp->num_queues,
8128                                1 + bp->num_cnic_queues);
8129
8130                 /* falling through... */
8131         case BNX2X_INT_MODE_MSI:
8132                 bnx2x_enable_msi(bp);
8133
8134                 /* falling through... */
8135         case BNX2X_INT_MODE_INTX:
8136                 bp->num_ethernet_queues = 1;
8137                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8138                 BNX2X_DEV_INFO("set number of queues to 1\n");
8139                 break;
8140         default:
8141                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8142                 return -EINVAL;
8143         }
8144         return 0;
8145 }
8146
8147 /* must be called prior to any HW initializations */
8148 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8149 {
8150         if (IS_SRIOV(bp))
8151                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8152         return L2_ILT_LINES(bp);
8153 }
8154
8155 void bnx2x_ilt_set_info(struct bnx2x *bp)
8156 {
8157         struct ilt_client_info *ilt_client;
8158         struct bnx2x_ilt *ilt = BP_ILT(bp);
8159         u16 line = 0;
8160
8161         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8162         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8163
8164         /* CDU */
8165         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8166         ilt_client->client_num = ILT_CLIENT_CDU;
8167         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8168         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8169         ilt_client->start = line;
8170         line += bnx2x_cid_ilt_lines(bp);
8171
8172         if (CNIC_SUPPORT(bp))
8173                 line += CNIC_ILT_LINES;
8174         ilt_client->end = line - 1;
8175
8176         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8177            ilt_client->start,
8178            ilt_client->end,
8179            ilt_client->page_size,
8180            ilt_client->flags,
8181            ilog2(ilt_client->page_size >> 12));
8182
8183         /* QM */
8184         if (QM_INIT(bp->qm_cid_count)) {
8185                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8186                 ilt_client->client_num = ILT_CLIENT_QM;
8187                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8188                 ilt_client->flags = 0;
8189                 ilt_client->start = line;
8190
8191                 /* 4 bytes for each cid */
8192                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8193                                                          QM_ILT_PAGE_SZ);
8194
8195                 ilt_client->end = line - 1;
8196
8197                 DP(NETIF_MSG_IFUP,
8198                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8199                    ilt_client->start,
8200                    ilt_client->end,
8201                    ilt_client->page_size,
8202                    ilt_client->flags,
8203                    ilog2(ilt_client->page_size >> 12));
8204         }
8205
8206         if (CNIC_SUPPORT(bp)) {
8207                 /* SRC */
8208                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8209                 ilt_client->client_num = ILT_CLIENT_SRC;
8210                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8211                 ilt_client->flags = 0;
8212                 ilt_client->start = line;
8213                 line += SRC_ILT_LINES;
8214                 ilt_client->end = line - 1;
8215
8216                 DP(NETIF_MSG_IFUP,
8217                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8218                    ilt_client->start,
8219                    ilt_client->end,
8220                    ilt_client->page_size,
8221                    ilt_client->flags,
8222                    ilog2(ilt_client->page_size >> 12));
8223
8224                 /* TM */
8225                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8226                 ilt_client->client_num = ILT_CLIENT_TM;
8227                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8228                 ilt_client->flags = 0;
8229                 ilt_client->start = line;
8230                 line += TM_ILT_LINES;
8231                 ilt_client->end = line - 1;
8232
8233                 DP(NETIF_MSG_IFUP,
8234                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8235                    ilt_client->start,
8236                    ilt_client->end,
8237                    ilt_client->page_size,
8238                    ilt_client->flags,
8239                    ilog2(ilt_client->page_size >> 12));
8240         }
8241
8242         BUG_ON(line > ILT_MAX_LINES);
8243 }
8244
8245 /**
8246  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8247  *
8248  * @bp:                 driver handle
8249  * @fp:                 pointer to fastpath
8250  * @init_params:        pointer to parameters structure
8251  *
8252  * parameters configured:
8253  *      - HC configuration
8254  *      - Queue's CDU context
8255  */
8256 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8257         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8258 {
8259         u8 cos;
8260         int cxt_index, cxt_offset;
8261
8262         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8263         if (!IS_FCOE_FP(fp)) {
8264                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8265                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8266
8267                 /* If HC is supported, enable host coalescing in the transition
8268                  * to INIT state.
8269                  */
8270                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8271                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8272
8273                 /* HC rate */
8274                 init_params->rx.hc_rate = bp->rx_ticks ?
8275                         (1000000 / bp->rx_ticks) : 0;
8276                 init_params->tx.hc_rate = bp->tx_ticks ?
8277                         (1000000 / bp->tx_ticks) : 0;
8278
8279                 /* FW SB ID */
8280                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8281                         fp->fw_sb_id;
8282
8283                 /*
8284                  * CQ index among the SB indices: FCoE clients uses the default
8285                  * SB, therefore it's different.
8286                  */
8287                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8288                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8289         }
8290
8291         /* set maximum number of COSs supported by this queue */
8292         init_params->max_cos = fp->max_cos;
8293
8294         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8295             fp->index, init_params->max_cos);
8296
8297         /* set the context pointers queue object */
8298         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8299                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8300                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8301                                 ILT_PAGE_CIDS);
8302                 init_params->cxts[cos] =
8303                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8304         }
8305 }
8306
8307 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8308                         struct bnx2x_queue_state_params *q_params,
8309                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8310                         int tx_index, bool leading)
8311 {
8312         memset(tx_only_params, 0, sizeof(*tx_only_params));
8313
8314         /* Set the command */
8315         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8316
8317         /* Set tx-only QUEUE flags: don't zero statistics */
8318         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8319
8320         /* choose the index of the cid to send the slow path on */
8321         tx_only_params->cid_index = tx_index;
8322
8323         /* Set general TX_ONLY_SETUP parameters */
8324         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8325
8326         /* Set Tx TX_ONLY_SETUP parameters */
8327         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8328
8329         DP(NETIF_MSG_IFUP,
8330            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8331            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8332            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8333            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8334
8335         /* send the ramrod */
8336         return bnx2x_queue_state_change(bp, q_params);
8337 }
8338
8339 /**
8340  * bnx2x_setup_queue - setup queue
8341  *
8342  * @bp:         driver handle
8343  * @fp:         pointer to fastpath
8344  * @leading:    is leading
8345  *
8346  * This function performs 2 steps in a Queue state machine
8347  *      actually: 1) RESET->INIT 2) INIT->SETUP
8348  */
8349
8350 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8351                        bool leading)
8352 {
8353         struct bnx2x_queue_state_params q_params = {NULL};
8354         struct bnx2x_queue_setup_params *setup_params =
8355                                                 &q_params.params.setup;
8356         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8357                                                 &q_params.params.tx_only;
8358         int rc;
8359         u8 tx_index;
8360
8361         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8362
8363         /* reset IGU state skip FCoE L2 queue */
8364         if (!IS_FCOE_FP(fp))
8365                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8366                              IGU_INT_ENABLE, 0);
8367
8368         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8369         /* We want to wait for completion in this context */
8370         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8371
8372         /* Prepare the INIT parameters */
8373         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8374
8375         /* Set the command */
8376         q_params.cmd = BNX2X_Q_CMD_INIT;
8377
8378         /* Change the state to INIT */
8379         rc = bnx2x_queue_state_change(bp, &q_params);
8380         if (rc) {
8381                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8382                 return rc;
8383         }
8384
8385         DP(NETIF_MSG_IFUP, "init complete\n");
8386
8387         /* Now move the Queue to the SETUP state... */
8388         memset(setup_params, 0, sizeof(*setup_params));
8389
8390         /* Set QUEUE flags */
8391         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8392
8393         /* Set general SETUP parameters */
8394         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8395                                 FIRST_TX_COS_INDEX);
8396
8397         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8398                             &setup_params->rxq_params);
8399
8400         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8401                            FIRST_TX_COS_INDEX);
8402
8403         /* Set the command */
8404         q_params.cmd = BNX2X_Q_CMD_SETUP;
8405
8406         if (IS_FCOE_FP(fp))
8407                 bp->fcoe_init = true;
8408
8409         /* Change the state to SETUP */
8410         rc = bnx2x_queue_state_change(bp, &q_params);
8411         if (rc) {
8412                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8413                 return rc;
8414         }
8415
8416         /* loop through the relevant tx-only indices */
8417         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8418               tx_index < fp->max_cos;
8419               tx_index++) {
8420
8421                 /* prepare and send tx-only ramrod*/
8422                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8423                                           tx_only_params, tx_index, leading);
8424                 if (rc) {
8425                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8426                                   fp->index, tx_index);
8427                         return rc;
8428                 }
8429         }
8430
8431         return rc;
8432 }
8433
8434 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8435 {
8436         struct bnx2x_fastpath *fp = &bp->fp[index];
8437         struct bnx2x_fp_txdata *txdata;
8438         struct bnx2x_queue_state_params q_params = {NULL};
8439         int rc, tx_index;
8440
8441         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8442
8443         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8444         /* We want to wait for completion in this context */
8445         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8446
8447         /* close tx-only connections */
8448         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8449              tx_index < fp->max_cos;
8450              tx_index++){
8451
8452                 /* ascertain this is a normal queue*/
8453                 txdata = fp->txdata_ptr[tx_index];
8454
8455                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8456                                                         txdata->txq_index);
8457
8458                 /* send halt terminate on tx-only connection */
8459                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8460                 memset(&q_params.params.terminate, 0,
8461                        sizeof(q_params.params.terminate));
8462                 q_params.params.terminate.cid_index = tx_index;
8463
8464                 rc = bnx2x_queue_state_change(bp, &q_params);
8465                 if (rc)
8466                         return rc;
8467
8468                 /* send halt terminate on tx-only connection */
8469                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8470                 memset(&q_params.params.cfc_del, 0,
8471                        sizeof(q_params.params.cfc_del));
8472                 q_params.params.cfc_del.cid_index = tx_index;
8473                 rc = bnx2x_queue_state_change(bp, &q_params);
8474                 if (rc)
8475                         return rc;
8476         }
8477         /* Stop the primary connection: */
8478         /* ...halt the connection */
8479         q_params.cmd = BNX2X_Q_CMD_HALT;
8480         rc = bnx2x_queue_state_change(bp, &q_params);
8481         if (rc)
8482                 return rc;
8483
8484         /* ...terminate the connection */
8485         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8486         memset(&q_params.params.terminate, 0,
8487                sizeof(q_params.params.terminate));
8488         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8489         rc = bnx2x_queue_state_change(bp, &q_params);
8490         if (rc)
8491                 return rc;
8492         /* ...delete cfc entry */
8493         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8494         memset(&q_params.params.cfc_del, 0,
8495                sizeof(q_params.params.cfc_del));
8496         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8497         return bnx2x_queue_state_change(bp, &q_params);
8498 }
8499
8500 static void bnx2x_reset_func(struct bnx2x *bp)
8501 {
8502         int port = BP_PORT(bp);
8503         int func = BP_FUNC(bp);
8504         int i;
8505
8506         /* Disable the function in the FW */
8507         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8508         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8509         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8510         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8511
8512         /* FP SBs */
8513         for_each_eth_queue(bp, i) {
8514                 struct bnx2x_fastpath *fp = &bp->fp[i];
8515                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8516                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8517                            SB_DISABLED);
8518         }
8519
8520         if (CNIC_LOADED(bp))
8521                 /* CNIC SB */
8522                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8523                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8524                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8525
8526         /* SP SB */
8527         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8528                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8529                 SB_DISABLED);
8530
8531         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8532                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8533                        0);
8534
8535         /* Configure IGU */
8536         if (bp->common.int_block == INT_BLOCK_HC) {
8537                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8538                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8539         } else {
8540                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8541                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8542         }
8543
8544         if (CNIC_LOADED(bp)) {
8545                 /* Disable Timer scan */
8546                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8547                 /*
8548                  * Wait for at least 10ms and up to 2 second for the timers
8549                  * scan to complete
8550                  */
8551                 for (i = 0; i < 200; i++) {
8552                         usleep_range(10000, 20000);
8553                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8554                                 break;
8555                 }
8556         }
8557         /* Clear ILT */
8558         bnx2x_clear_func_ilt(bp, func);
8559
8560         /* Timers workaround bug for E2: if this is vnic-3,
8561          * we need to set the entire ilt range for this timers.
8562          */
8563         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8564                 struct ilt_client_info ilt_cli;
8565                 /* use dummy TM client */
8566                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8567                 ilt_cli.start = 0;
8568                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8569                 ilt_cli.client_num = ILT_CLIENT_TM;
8570
8571                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8572         }
8573
8574         /* this assumes that reset_port() called before reset_func()*/
8575         if (!CHIP_IS_E1x(bp))
8576                 bnx2x_pf_disable(bp);
8577
8578         bp->dmae_ready = 0;
8579 }
8580
8581 static void bnx2x_reset_port(struct bnx2x *bp)
8582 {
8583         int port = BP_PORT(bp);
8584         u32 val;
8585
8586         /* Reset physical Link */
8587         bnx2x__link_reset(bp);
8588
8589         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8590
8591         /* Do not rcv packets to BRB */
8592         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8593         /* Do not direct rcv packets that are not for MCP to the BRB */
8594         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8595                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8596
8597         /* Configure AEU */
8598         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8599
8600         msleep(100);
8601         /* Check for BRB port occupancy */
8602         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8603         if (val)
8604                 DP(NETIF_MSG_IFDOWN,
8605                    "BRB1 is not empty  %d blocks are occupied\n", val);
8606
8607         /* TODO: Close Doorbell port? */
8608 }
8609
8610 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8611 {
8612         struct bnx2x_func_state_params func_params = {NULL};
8613
8614         /* Prepare parameters for function state transitions */
8615         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8616
8617         func_params.f_obj = &bp->func_obj;
8618         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8619
8620         func_params.params.hw_init.load_phase = load_code;
8621
8622         return bnx2x_func_state_change(bp, &func_params);
8623 }
8624
8625 static int bnx2x_func_stop(struct bnx2x *bp)
8626 {
8627         struct bnx2x_func_state_params func_params = {NULL};
8628         int rc;
8629
8630         /* Prepare parameters for function state transitions */
8631         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8632         func_params.f_obj = &bp->func_obj;
8633         func_params.cmd = BNX2X_F_CMD_STOP;
8634
8635         /*
8636          * Try to stop the function the 'good way'. If fails (in case
8637          * of a parity error during bnx2x_chip_cleanup()) and we are
8638          * not in a debug mode, perform a state transaction in order to
8639          * enable further HW_RESET transaction.
8640          */
8641         rc = bnx2x_func_state_change(bp, &func_params);
8642         if (rc) {
8643 #ifdef BNX2X_STOP_ON_ERROR
8644                 return rc;
8645 #else
8646                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8647                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8648                 return bnx2x_func_state_change(bp, &func_params);
8649 #endif
8650         }
8651
8652         return 0;
8653 }
8654
8655 /**
8656  * bnx2x_send_unload_req - request unload mode from the MCP.
8657  *
8658  * @bp:                 driver handle
8659  * @unload_mode:        requested function's unload mode
8660  *
8661  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8662  */
8663 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8664 {
8665         u32 reset_code = 0;
8666         int port = BP_PORT(bp);
8667
8668         /* Select the UNLOAD request mode */
8669         if (unload_mode == UNLOAD_NORMAL)
8670                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8671
8672         else if (bp->flags & NO_WOL_FLAG)
8673                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8674
8675         else if (bp->wol) {
8676                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8677                 u8 *mac_addr = bp->dev->dev_addr;
8678                 struct pci_dev *pdev = bp->pdev;
8679                 u32 val;
8680                 u16 pmc;
8681
8682                 /* The mac address is written to entries 1-4 to
8683                  * preserve entry 0 which is used by the PMF
8684                  */
8685                 u8 entry = (BP_VN(bp) + 1)*8;
8686
8687                 val = (mac_addr[0] << 8) | mac_addr[1];
8688                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8689
8690                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8691                       (mac_addr[4] << 8) | mac_addr[5];
8692                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8693
8694                 /* Enable the PME and clear the status */
8695                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8696                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8697                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8698
8699                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8700
8701         } else
8702                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8703
8704         /* Send the request to the MCP */
8705         if (!BP_NOMCP(bp))
8706                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8707         else {
8708                 int path = BP_PATH(bp);
8709
8710                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8711                    path, load_count[path][0], load_count[path][1],
8712                    load_count[path][2]);
8713                 load_count[path][0]--;
8714                 load_count[path][1 + port]--;
8715                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8716                    path, load_count[path][0], load_count[path][1],
8717                    load_count[path][2]);
8718                 if (load_count[path][0] == 0)
8719                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8720                 else if (load_count[path][1 + port] == 0)
8721                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8722                 else
8723                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8724         }
8725
8726         return reset_code;
8727 }
8728
8729 /**
8730  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8731  *
8732  * @bp:         driver handle
8733  * @keep_link:          true iff link should be kept up
8734  */
8735 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8736 {
8737         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8738
8739         /* Report UNLOAD_DONE to MCP */
8740         if (!BP_NOMCP(bp))
8741                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8742 }
8743
8744 static int bnx2x_func_wait_started(struct bnx2x *bp)
8745 {
8746         int tout = 50;
8747         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8748
8749         if (!bp->port.pmf)
8750                 return 0;
8751
8752         /*
8753          * (assumption: No Attention from MCP at this stage)
8754          * PMF probably in the middle of TX disable/enable transaction
8755          * 1. Sync IRS for default SB
8756          * 2. Sync SP queue - this guarantees us that attention handling started
8757          * 3. Wait, that TX disable/enable transaction completes
8758          *
8759          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8760          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8761          * received completion for the transaction the state is TX_STOPPED.
8762          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8763          * transaction.
8764          */
8765
8766         /* make sure default SB ISR is done */
8767         if (msix)
8768                 synchronize_irq(bp->msix_table[0].vector);
8769         else
8770                 synchronize_irq(bp->pdev->irq);
8771
8772         flush_workqueue(bnx2x_wq);
8773
8774         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8775                                 BNX2X_F_STATE_STARTED && tout--)
8776                 msleep(20);
8777
8778         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8779                                                 BNX2X_F_STATE_STARTED) {
8780 #ifdef BNX2X_STOP_ON_ERROR
8781                 BNX2X_ERR("Wrong function state\n");
8782                 return -EBUSY;
8783 #else
8784                 /*
8785                  * Failed to complete the transaction in a "good way"
8786                  * Force both transactions with CLR bit
8787                  */
8788                 struct bnx2x_func_state_params func_params = {NULL};
8789
8790                 DP(NETIF_MSG_IFDOWN,
8791                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8792
8793                 func_params.f_obj = &bp->func_obj;
8794                 __set_bit(RAMROD_DRV_CLR_ONLY,
8795                                         &func_params.ramrod_flags);
8796
8797                 /* STARTED-->TX_ST0PPED */
8798                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8799                 bnx2x_func_state_change(bp, &func_params);
8800
8801                 /* TX_ST0PPED-->STARTED */
8802                 func_params.cmd = BNX2X_F_CMD_TX_START;
8803                 return bnx2x_func_state_change(bp, &func_params);
8804 #endif
8805         }
8806
8807         return 0;
8808 }
8809
8810 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8811 {
8812         int port = BP_PORT(bp);
8813         int i, rc = 0;
8814         u8 cos;
8815         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8816         u32 reset_code;
8817
8818         /* Wait until tx fastpath tasks complete */
8819         for_each_tx_queue(bp, i) {
8820                 struct bnx2x_fastpath *fp = &bp->fp[i];
8821
8822                 for_each_cos_in_tx_queue(fp, cos)
8823                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8824 #ifdef BNX2X_STOP_ON_ERROR
8825                 if (rc)
8826                         return;
8827 #endif
8828         }
8829
8830         /* Give HW time to discard old tx messages */
8831         usleep_range(1000, 2000);
8832
8833         /* Clean all ETH MACs */
8834         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8835                                 false);
8836         if (rc < 0)
8837                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8838
8839         /* Clean up UC list  */
8840         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8841                                 true);
8842         if (rc < 0)
8843                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8844                           rc);
8845
8846         /* Disable LLH */
8847         if (!CHIP_IS_E1(bp))
8848                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8849
8850         /* Set "drop all" (stop Rx).
8851          * We need to take a netif_addr_lock() here in order to prevent
8852          * a race between the completion code and this code.
8853          */
8854         netif_addr_lock_bh(bp->dev);
8855         /* Schedule the rx_mode command */
8856         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8857                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8858         else
8859                 bnx2x_set_storm_rx_mode(bp);
8860
8861         /* Cleanup multicast configuration */
8862         rparam.mcast_obj = &bp->mcast_obj;
8863         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8864         if (rc < 0)
8865                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8866
8867         netif_addr_unlock_bh(bp->dev);
8868
8869         bnx2x_iov_chip_cleanup(bp);
8870
8871         /*
8872          * Send the UNLOAD_REQUEST to the MCP. This will return if
8873          * this function should perform FUNC, PORT or COMMON HW
8874          * reset.
8875          */
8876         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8877
8878         /*
8879          * (assumption: No Attention from MCP at this stage)
8880          * PMF probably in the middle of TX disable/enable transaction
8881          */
8882         rc = bnx2x_func_wait_started(bp);
8883         if (rc) {
8884                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8885 #ifdef BNX2X_STOP_ON_ERROR
8886                 return;
8887 #endif
8888         }
8889
8890         /* Close multi and leading connections
8891          * Completions for ramrods are collected in a synchronous way
8892          */
8893         for_each_eth_queue(bp, i)
8894                 if (bnx2x_stop_queue(bp, i))
8895 #ifdef BNX2X_STOP_ON_ERROR
8896                         return;
8897 #else
8898                         goto unload_error;
8899 #endif
8900
8901         if (CNIC_LOADED(bp)) {
8902                 for_each_cnic_queue(bp, i)
8903                         if (bnx2x_stop_queue(bp, i))
8904 #ifdef BNX2X_STOP_ON_ERROR
8905                                 return;
8906 #else
8907                                 goto unload_error;
8908 #endif
8909         }
8910
8911         /* If SP settings didn't get completed so far - something
8912          * very wrong has happen.
8913          */
8914         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8915                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8916
8917 #ifndef BNX2X_STOP_ON_ERROR
8918 unload_error:
8919 #endif
8920         rc = bnx2x_func_stop(bp);
8921         if (rc) {
8922                 BNX2X_ERR("Function stop failed!\n");
8923 #ifdef BNX2X_STOP_ON_ERROR
8924                 return;
8925 #endif
8926         }
8927
8928         /* Disable HW interrupts, NAPI */
8929         bnx2x_netif_stop(bp, 1);
8930         /* Delete all NAPI objects */
8931         bnx2x_del_all_napi(bp);
8932         if (CNIC_LOADED(bp))
8933                 bnx2x_del_all_napi_cnic(bp);
8934
8935         /* Release IRQs */
8936         bnx2x_free_irq(bp);
8937
8938         /* Reset the chip */
8939         rc = bnx2x_reset_hw(bp, reset_code);
8940         if (rc)
8941                 BNX2X_ERR("HW_RESET failed\n");
8942
8943         /* Report UNLOAD_DONE to MCP */
8944         bnx2x_send_unload_done(bp, keep_link);
8945 }
8946
8947 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8948 {
8949         u32 val;
8950
8951         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8952
8953         if (CHIP_IS_E1(bp)) {
8954                 int port = BP_PORT(bp);
8955                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8956                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8957
8958                 val = REG_RD(bp, addr);
8959                 val &= ~(0x300);
8960                 REG_WR(bp, addr, val);
8961         } else {
8962                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8963                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8964                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8965                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8966         }
8967 }
8968
8969 /* Close gates #2, #3 and #4: */
8970 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8971 {
8972         u32 val;
8973
8974         /* Gates #2 and #4a are closed/opened for "not E1" only */
8975         if (!CHIP_IS_E1(bp)) {
8976                 /* #4 */
8977                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8978                 /* #2 */
8979                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8980         }
8981
8982         /* #3 */
8983         if (CHIP_IS_E1x(bp)) {
8984                 /* Prevent interrupts from HC on both ports */
8985                 val = REG_RD(bp, HC_REG_CONFIG_1);
8986                 REG_WR(bp, HC_REG_CONFIG_1,
8987                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8988                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8989
8990                 val = REG_RD(bp, HC_REG_CONFIG_0);
8991                 REG_WR(bp, HC_REG_CONFIG_0,
8992                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8993                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8994         } else {
8995                 /* Prevent incoming interrupts in IGU */
8996                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8997
8998                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8999                        (!close) ?
9000                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9001                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9002         }
9003
9004         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9005                 close ? "closing" : "opening");
9006         mmiowb();
9007 }
9008
9009 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9010
9011 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9012 {
9013         /* Do some magic... */
9014         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9015         *magic_val = val & SHARED_MF_CLP_MAGIC;
9016         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9017 }
9018
9019 /**
9020  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9021  *
9022  * @bp:         driver handle
9023  * @magic_val:  old value of the `magic' bit.
9024  */
9025 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9026 {
9027         /* Restore the `magic' bit value... */
9028         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9029         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9030                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9031 }
9032
9033 /**
9034  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9035  *
9036  * @bp:         driver handle
9037  * @magic_val:  old value of 'magic' bit.
9038  *
9039  * Takes care of CLP configurations.
9040  */
9041 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9042 {
9043         u32 shmem;
9044         u32 validity_offset;
9045
9046         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9047
9048         /* Set `magic' bit in order to save MF config */
9049         if (!CHIP_IS_E1(bp))
9050                 bnx2x_clp_reset_prep(bp, magic_val);
9051
9052         /* Get shmem offset */
9053         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9054         validity_offset =
9055                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9056
9057         /* Clear validity map flags */
9058         if (shmem > 0)
9059                 REG_WR(bp, shmem + validity_offset, 0);
9060 }
9061
9062 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9063 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9064
9065 /**
9066  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9067  *
9068  * @bp: driver handle
9069  */
9070 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9071 {
9072         /* special handling for emulation and FPGA,
9073            wait 10 times longer */
9074         if (CHIP_REV_IS_SLOW(bp))
9075                 msleep(MCP_ONE_TIMEOUT*10);
9076         else
9077                 msleep(MCP_ONE_TIMEOUT);
9078 }
9079
9080 /*
9081  * initializes bp->common.shmem_base and waits for validity signature to appear
9082  */
9083 static int bnx2x_init_shmem(struct bnx2x *bp)
9084 {
9085         int cnt = 0;
9086         u32 val = 0;
9087
9088         do {
9089                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9090                 if (bp->common.shmem_base) {
9091                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9092                         if (val & SHR_MEM_VALIDITY_MB)
9093                                 return 0;
9094                 }
9095
9096                 bnx2x_mcp_wait_one(bp);
9097
9098         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9099
9100         BNX2X_ERR("BAD MCP validity signature\n");
9101
9102         return -ENODEV;
9103 }
9104
9105 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9106 {
9107         int rc = bnx2x_init_shmem(bp);
9108
9109         /* Restore the `magic' bit value */
9110         if (!CHIP_IS_E1(bp))
9111                 bnx2x_clp_reset_done(bp, magic_val);
9112
9113         return rc;
9114 }
9115
9116 static void bnx2x_pxp_prep(struct bnx2x *bp)
9117 {
9118         if (!CHIP_IS_E1(bp)) {
9119                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9120                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9121                 mmiowb();
9122         }
9123 }
9124
9125 /*
9126  * Reset the whole chip except for:
9127  *      - PCIE core
9128  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9129  *              one reset bit)
9130  *      - IGU
9131  *      - MISC (including AEU)
9132  *      - GRC
9133  *      - RBCN, RBCP
9134  */
9135 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9136 {
9137         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9138         u32 global_bits2, stay_reset2;
9139
9140         /*
9141          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9142          * (per chip) blocks.
9143          */
9144         global_bits2 =
9145                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9146                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9147
9148         /* Don't reset the following blocks.
9149          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9150          *            reset, as in 4 port device they might still be owned
9151          *            by the MCP (there is only one leader per path).
9152          */
9153         not_reset_mask1 =
9154                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9155                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9156                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9157
9158         not_reset_mask2 =
9159                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9160                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9161                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9162                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9163                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9164                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9165                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9166                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9167                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9168                 MISC_REGISTERS_RESET_REG_2_PGLC |
9169                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9170                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9171                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9172                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9173                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9174                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9175
9176         /*
9177          * Keep the following blocks in reset:
9178          *  - all xxMACs are handled by the bnx2x_link code.
9179          */
9180         stay_reset2 =
9181                 MISC_REGISTERS_RESET_REG_2_XMAC |
9182                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9183
9184         /* Full reset masks according to the chip */
9185         reset_mask1 = 0xffffffff;
9186
9187         if (CHIP_IS_E1(bp))
9188                 reset_mask2 = 0xffff;
9189         else if (CHIP_IS_E1H(bp))
9190                 reset_mask2 = 0x1ffff;
9191         else if (CHIP_IS_E2(bp))
9192                 reset_mask2 = 0xfffff;
9193         else /* CHIP_IS_E3 */
9194                 reset_mask2 = 0x3ffffff;
9195
9196         /* Don't reset global blocks unless we need to */
9197         if (!global)
9198                 reset_mask2 &= ~global_bits2;
9199
9200         /*
9201          * In case of attention in the QM, we need to reset PXP
9202          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9203          * because otherwise QM reset would release 'close the gates' shortly
9204          * before resetting the PXP, then the PSWRQ would send a write
9205          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9206          * read the payload data from PSWWR, but PSWWR would not
9207          * respond. The write queue in PGLUE would stuck, dmae commands
9208          * would not return. Therefore it's important to reset the second
9209          * reset register (containing the
9210          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9211          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9212          * bit).
9213          */
9214         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9215                reset_mask2 & (~not_reset_mask2));
9216
9217         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9218                reset_mask1 & (~not_reset_mask1));
9219
9220         barrier();
9221         mmiowb();
9222
9223         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9224                reset_mask2 & (~stay_reset2));
9225
9226         barrier();
9227         mmiowb();
9228
9229         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9230         mmiowb();
9231 }
9232
9233 /**
9234  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9235  * It should get cleared in no more than 1s.
9236  *
9237  * @bp: driver handle
9238  *
9239  * It should get cleared in no more than 1s. Returns 0 if
9240  * pending writes bit gets cleared.
9241  */
9242 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9243 {
9244         u32 cnt = 1000;
9245         u32 pend_bits = 0;
9246
9247         do {
9248                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9249
9250                 if (pend_bits == 0)
9251                         break;
9252
9253                 usleep_range(1000, 2000);
9254         } while (cnt-- > 0);
9255
9256         if (cnt <= 0) {
9257                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9258                           pend_bits);
9259                 return -EBUSY;
9260         }
9261
9262         return 0;
9263 }
9264
9265 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9266 {
9267         int cnt = 1000;
9268         u32 val = 0;
9269         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9270         u32 tags_63_32 = 0;
9271
9272         /* Empty the Tetris buffer, wait for 1s */
9273         do {
9274                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9275                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9276                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9277                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9278                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9279                 if (CHIP_IS_E3(bp))
9280                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9281
9282                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9283                     ((port_is_idle_0 & 0x1) == 0x1) &&
9284                     ((port_is_idle_1 & 0x1) == 0x1) &&
9285                     (pgl_exp_rom2 == 0xffffffff) &&
9286                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9287                         break;
9288                 usleep_range(1000, 2000);
9289         } while (cnt-- > 0);
9290
9291         if (cnt <= 0) {
9292                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9293                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9294                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9295                           pgl_exp_rom2);
9296                 return -EAGAIN;
9297         }
9298
9299         barrier();
9300
9301         /* Close gates #2, #3 and #4 */
9302         bnx2x_set_234_gates(bp, true);
9303
9304         /* Poll for IGU VQs for 57712 and newer chips */
9305         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9306                 return -EAGAIN;
9307
9308         /* TBD: Indicate that "process kill" is in progress to MCP */
9309
9310         /* Clear "unprepared" bit */
9311         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9312         barrier();
9313
9314         /* Make sure all is written to the chip before the reset */
9315         mmiowb();
9316
9317         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9318          * PSWHST, GRC and PSWRD Tetris buffer.
9319          */
9320         usleep_range(1000, 2000);
9321
9322         /* Prepare to chip reset: */
9323         /* MCP */
9324         if (global)
9325                 bnx2x_reset_mcp_prep(bp, &val);
9326
9327         /* PXP */
9328         bnx2x_pxp_prep(bp);
9329         barrier();
9330
9331         /* reset the chip */
9332         bnx2x_process_kill_chip_reset(bp, global);
9333         barrier();
9334
9335         /* Recover after reset: */
9336         /* MCP */
9337         if (global && bnx2x_reset_mcp_comp(bp, val))
9338                 return -EAGAIN;
9339
9340         /* TBD: Add resetting the NO_MCP mode DB here */
9341
9342         /* Open the gates #2, #3 and #4 */
9343         bnx2x_set_234_gates(bp, false);
9344
9345         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9346          * reset state, re-enable attentions. */
9347
9348         return 0;
9349 }
9350
9351 static int bnx2x_leader_reset(struct bnx2x *bp)
9352 {
9353         int rc = 0;
9354         bool global = bnx2x_reset_is_global(bp);
9355         u32 load_code;
9356
9357         /* if not going to reset MCP - load "fake" driver to reset HW while
9358          * driver is owner of the HW
9359          */
9360         if (!global && !BP_NOMCP(bp)) {
9361                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9362                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9363                 if (!load_code) {
9364                         BNX2X_ERR("MCP response failure, aborting\n");
9365                         rc = -EAGAIN;
9366                         goto exit_leader_reset;
9367                 }
9368                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9369                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9370                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9371                         rc = -EAGAIN;
9372                         goto exit_leader_reset2;
9373                 }
9374                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9375                 if (!load_code) {
9376                         BNX2X_ERR("MCP response failure, aborting\n");
9377                         rc = -EAGAIN;
9378                         goto exit_leader_reset2;
9379                 }
9380         }
9381
9382         /* Try to recover after the failure */
9383         if (bnx2x_process_kill(bp, global)) {
9384                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9385                           BP_PATH(bp));
9386                 rc = -EAGAIN;
9387                 goto exit_leader_reset2;
9388         }
9389
9390         /*
9391          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9392          * state.
9393          */
9394         bnx2x_set_reset_done(bp);
9395         if (global)
9396                 bnx2x_clear_reset_global(bp);
9397
9398 exit_leader_reset2:
9399         /* unload "fake driver" if it was loaded */
9400         if (!global && !BP_NOMCP(bp)) {
9401                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9402                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9403         }
9404 exit_leader_reset:
9405         bp->is_leader = 0;
9406         bnx2x_release_leader_lock(bp);
9407         smp_mb();
9408         return rc;
9409 }
9410
9411 static void bnx2x_recovery_failed(struct bnx2x *bp)
9412 {
9413         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9414
9415         /* Disconnect this device */
9416         netif_device_detach(bp->dev);
9417
9418         /*
9419          * Block ifup for all function on this engine until "process kill"
9420          * or power cycle.
9421          */
9422         bnx2x_set_reset_in_progress(bp);
9423
9424         /* Shut down the power */
9425         bnx2x_set_power_state(bp, PCI_D3hot);
9426
9427         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9428
9429         smp_mb();
9430 }
9431
9432 /*
9433  * Assumption: runs under rtnl lock. This together with the fact
9434  * that it's called only from bnx2x_sp_rtnl() ensure that it
9435  * will never be called when netif_running(bp->dev) is false.
9436  */
9437 static void bnx2x_parity_recover(struct bnx2x *bp)
9438 {
9439         bool global = false;
9440         u32 error_recovered, error_unrecovered;
9441         bool is_parity;
9442
9443         DP(NETIF_MSG_HW, "Handling parity\n");
9444         while (1) {
9445                 switch (bp->recovery_state) {
9446                 case BNX2X_RECOVERY_INIT:
9447                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9448                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9449                         WARN_ON(!is_parity);
9450
9451                         /* Try to get a LEADER_LOCK HW lock */
9452                         if (bnx2x_trylock_leader_lock(bp)) {
9453                                 bnx2x_set_reset_in_progress(bp);
9454                                 /*
9455                                  * Check if there is a global attention and if
9456                                  * there was a global attention, set the global
9457                                  * reset bit.
9458                                  */
9459
9460                                 if (global)
9461                                         bnx2x_set_reset_global(bp);
9462
9463                                 bp->is_leader = 1;
9464                         }
9465
9466                         /* Stop the driver */
9467                         /* If interface has been removed - break */
9468                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9469                                 return;
9470
9471                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9472
9473                         /* Ensure "is_leader", MCP command sequence and
9474                          * "recovery_state" update values are seen on other
9475                          * CPUs.
9476                          */
9477                         smp_mb();
9478                         break;
9479
9480                 case BNX2X_RECOVERY_WAIT:
9481                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9482                         if (bp->is_leader) {
9483                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9484                                 bool other_load_status =
9485                                         bnx2x_get_load_status(bp, other_engine);
9486                                 bool load_status =
9487                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9488                                 global = bnx2x_reset_is_global(bp);
9489
9490                                 /*
9491                                  * In case of a parity in a global block, let
9492                                  * the first leader that performs a
9493                                  * leader_reset() reset the global blocks in
9494                                  * order to clear global attentions. Otherwise
9495                                  * the gates will remain closed for that
9496                                  * engine.
9497                                  */
9498                                 if (load_status ||
9499                                     (global && other_load_status)) {
9500                                         /* Wait until all other functions get
9501                                          * down.
9502                                          */
9503                                         schedule_delayed_work(&bp->sp_rtnl_task,
9504                                                                 HZ/10);
9505                                         return;
9506                                 } else {
9507                                         /* If all other functions got down -
9508                                          * try to bring the chip back to
9509                                          * normal. In any case it's an exit
9510                                          * point for a leader.
9511                                          */
9512                                         if (bnx2x_leader_reset(bp)) {
9513                                                 bnx2x_recovery_failed(bp);
9514                                                 return;
9515                                         }
9516
9517                                         /* If we are here, means that the
9518                                          * leader has succeeded and doesn't
9519                                          * want to be a leader any more. Try
9520                                          * to continue as a none-leader.
9521                                          */
9522                                         break;
9523                                 }
9524                         } else { /* non-leader */
9525                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9526                                         /* Try to get a LEADER_LOCK HW lock as
9527                                          * long as a former leader may have
9528                                          * been unloaded by the user or
9529                                          * released a leadership by another
9530                                          * reason.
9531                                          */
9532                                         if (bnx2x_trylock_leader_lock(bp)) {
9533                                                 /* I'm a leader now! Restart a
9534                                                  * switch case.
9535                                                  */
9536                                                 bp->is_leader = 1;
9537                                                 break;
9538                                         }
9539
9540                                         schedule_delayed_work(&bp->sp_rtnl_task,
9541                                                                 HZ/10);
9542                                         return;
9543
9544                                 } else {
9545                                         /*
9546                                          * If there was a global attention, wait
9547                                          * for it to be cleared.
9548                                          */
9549                                         if (bnx2x_reset_is_global(bp)) {
9550                                                 schedule_delayed_work(
9551                                                         &bp->sp_rtnl_task,
9552                                                         HZ/10);
9553                                                 return;
9554                                         }
9555
9556                                         error_recovered =
9557                                           bp->eth_stats.recoverable_error;
9558                                         error_unrecovered =
9559                                           bp->eth_stats.unrecoverable_error;
9560                                         bp->recovery_state =
9561                                                 BNX2X_RECOVERY_NIC_LOADING;
9562                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9563                                                 error_unrecovered++;
9564                                                 netdev_err(bp->dev,
9565                                                            "Recovery failed. Power cycle needed\n");
9566                                                 /* Disconnect this device */
9567                                                 netif_device_detach(bp->dev);
9568                                                 /* Shut down the power */
9569                                                 bnx2x_set_power_state(
9570                                                         bp, PCI_D3hot);
9571                                                 smp_mb();
9572                                         } else {
9573                                                 bp->recovery_state =
9574                                                         BNX2X_RECOVERY_DONE;
9575                                                 error_recovered++;
9576                                                 smp_mb();
9577                                         }
9578                                         bp->eth_stats.recoverable_error =
9579                                                 error_recovered;
9580                                         bp->eth_stats.unrecoverable_error =
9581                                                 error_unrecovered;
9582
9583                                         return;
9584                                 }
9585                         }
9586                 default:
9587                         return;
9588                 }
9589         }
9590 }
9591
9592 static int bnx2x_close(struct net_device *dev);
9593
9594 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9595  * scheduled on a general queue in order to prevent a dead lock.
9596  */
9597 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9598 {
9599         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9600
9601         rtnl_lock();
9602
9603         if (!netif_running(bp->dev)) {
9604                 rtnl_unlock();
9605                 return;
9606         }
9607
9608         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9609 #ifdef BNX2X_STOP_ON_ERROR
9610                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9611                           "you will need to reboot when done\n");
9612                 goto sp_rtnl_not_reset;
9613 #endif
9614                 /*
9615                  * Clear all pending SP commands as we are going to reset the
9616                  * function anyway.
9617                  */
9618                 bp->sp_rtnl_state = 0;
9619                 smp_mb();
9620
9621                 bnx2x_parity_recover(bp);
9622
9623                 rtnl_unlock();
9624                 return;
9625         }
9626
9627         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9628 #ifdef BNX2X_STOP_ON_ERROR
9629                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9630                           "you will need to reboot when done\n");
9631                 goto sp_rtnl_not_reset;
9632 #endif
9633
9634                 /*
9635                  * Clear all pending SP commands as we are going to reset the
9636                  * function anyway.
9637                  */
9638                 bp->sp_rtnl_state = 0;
9639                 smp_mb();
9640
9641                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9642                 bnx2x_nic_load(bp, LOAD_NORMAL);
9643
9644                 rtnl_unlock();
9645                 return;
9646         }
9647 #ifdef BNX2X_STOP_ON_ERROR
9648 sp_rtnl_not_reset:
9649 #endif
9650         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9651                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9652         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9653                 bnx2x_after_function_update(bp);
9654         /*
9655          * in case of fan failure we need to reset id if the "stop on error"
9656          * debug flag is set, since we trying to prevent permanent overheating
9657          * damage
9658          */
9659         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9660                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9661                 netif_device_detach(bp->dev);
9662                 bnx2x_close(bp->dev);
9663                 rtnl_unlock();
9664                 return;
9665         }
9666
9667         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9668                 DP(BNX2X_MSG_SP,
9669                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9670                 bnx2x_vfpf_set_mcast(bp->dev);
9671         }
9672         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9673                                &bp->sp_rtnl_state)){
9674                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9675                         bnx2x_tx_disable(bp);
9676                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9677                 }
9678         }
9679
9680         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9681                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9682                 bnx2x_set_rx_mode_inner(bp);
9683         }
9684
9685         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9686                                &bp->sp_rtnl_state))
9687                 bnx2x_pf_set_vfs_vlan(bp);
9688
9689         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))
9690                 bnx2x_dcbx_stop_hw_tx(bp);
9691
9692         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))
9693                 bnx2x_dcbx_resume_hw_tx(bp);
9694
9695         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9696          * can be called from other contexts as well)
9697          */
9698         rtnl_unlock();
9699
9700         /* enable SR-IOV if applicable */
9701         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9702                                                &bp->sp_rtnl_state)) {
9703                 bnx2x_disable_sriov(bp);
9704                 bnx2x_enable_sriov(bp);
9705         }
9706 }
9707
9708 static void bnx2x_period_task(struct work_struct *work)
9709 {
9710         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9711
9712         if (!netif_running(bp->dev))
9713                 goto period_task_exit;
9714
9715         if (CHIP_REV_IS_SLOW(bp)) {
9716                 BNX2X_ERR("period task called on emulation, ignoring\n");
9717                 goto period_task_exit;
9718         }
9719
9720         bnx2x_acquire_phy_lock(bp);
9721         /*
9722          * The barrier is needed to ensure the ordering between the writing to
9723          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9724          * the reading here.
9725          */
9726         smp_mb();
9727         if (bp->port.pmf) {
9728                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9729
9730                 /* Re-queue task in 1 sec */
9731                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9732         }
9733
9734         bnx2x_release_phy_lock(bp);
9735 period_task_exit:
9736         return;
9737 }
9738
9739 /*
9740  * Init service functions
9741  */
9742
9743 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9744 {
9745         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9746         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9747         return base + (BP_ABS_FUNC(bp)) * stride;
9748 }
9749
9750 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9751                                         struct bnx2x_mac_vals *vals)
9752 {
9753         u32 val, base_addr, offset, mask, reset_reg;
9754         bool mac_stopped = false;
9755         u8 port = BP_PORT(bp);
9756
9757         /* reset addresses as they also mark which values were changed */
9758         vals->bmac_addr = 0;
9759         vals->umac_addr = 0;
9760         vals->xmac_addr = 0;
9761         vals->emac_addr = 0;
9762
9763         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9764
9765         if (!CHIP_IS_E3(bp)) {
9766                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9767                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9768                 if ((mask & reset_reg) && val) {
9769                         u32 wb_data[2];
9770                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9771                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9772                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9773                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9774                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9775
9776                         /*
9777                          * use rd/wr since we cannot use dmae. This is safe
9778                          * since MCP won't access the bus due to the request
9779                          * to unload, and no function on the path can be
9780                          * loaded at this time.
9781                          */
9782                         wb_data[0] = REG_RD(bp, base_addr + offset);
9783                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9784                         vals->bmac_addr = base_addr + offset;
9785                         vals->bmac_val[0] = wb_data[0];
9786                         vals->bmac_val[1] = wb_data[1];
9787                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9788                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9789                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9790                 }
9791                 BNX2X_DEV_INFO("Disable emac Rx\n");
9792                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9793                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9794                 REG_WR(bp, vals->emac_addr, 0);
9795                 mac_stopped = true;
9796         } else {
9797                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9798                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9799                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9800                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9801                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9802                                val & ~(1 << 1));
9803                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9804                                val | (1 << 1));
9805                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9806                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9807                         REG_WR(bp, vals->xmac_addr, 0);
9808                         mac_stopped = true;
9809                 }
9810                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9811                 if (mask & reset_reg) {
9812                         BNX2X_DEV_INFO("Disable umac Rx\n");
9813                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9814                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9815                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9816                         REG_WR(bp, vals->umac_addr, 0);
9817                         mac_stopped = true;
9818                 }
9819         }
9820
9821         if (mac_stopped)
9822                 msleep(20);
9823 }
9824
9825 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9826 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9827 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9828 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9829
9830 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9831 {
9832         u16 rcq, bd;
9833         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9834
9835         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9836         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9837
9838         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9839         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9840
9841         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9842                        port, bd, rcq);
9843 }
9844
9845 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9846 {
9847         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9848                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9849         if (!rc) {
9850                 BNX2X_ERR("MCP response failure, aborting\n");
9851                 return -EBUSY;
9852         }
9853
9854         return 0;
9855 }
9856
9857 static struct bnx2x_prev_path_list *
9858                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9859 {
9860         struct bnx2x_prev_path_list *tmp_list;
9861
9862         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9863                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9864                     bp->pdev->bus->number == tmp_list->bus &&
9865                     BP_PATH(bp) == tmp_list->path)
9866                         return tmp_list;
9867
9868         return NULL;
9869 }
9870
9871 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9872 {
9873         struct bnx2x_prev_path_list *tmp_list;
9874         int rc;
9875
9876         rc = down_interruptible(&bnx2x_prev_sem);
9877         if (rc) {
9878                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9879                 return rc;
9880         }
9881
9882         tmp_list = bnx2x_prev_path_get_entry(bp);
9883         if (tmp_list) {
9884                 tmp_list->aer = 1;
9885                 rc = 0;
9886         } else {
9887                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9888                           BP_PATH(bp));
9889         }
9890
9891         up(&bnx2x_prev_sem);
9892
9893         return rc;
9894 }
9895
9896 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9897 {
9898         struct bnx2x_prev_path_list *tmp_list;
9899         int rc = false;
9900
9901         if (down_trylock(&bnx2x_prev_sem))
9902                 return false;
9903
9904         tmp_list = bnx2x_prev_path_get_entry(bp);
9905         if (tmp_list) {
9906                 if (tmp_list->aer) {
9907                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9908                            BP_PATH(bp));
9909                 } else {
9910                         rc = true;
9911                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9912                                        BP_PATH(bp));
9913                 }
9914         }
9915
9916         up(&bnx2x_prev_sem);
9917
9918         return rc;
9919 }
9920
9921 bool bnx2x_port_after_undi(struct bnx2x *bp)
9922 {
9923         struct bnx2x_prev_path_list *entry;
9924         bool val;
9925
9926         down(&bnx2x_prev_sem);
9927
9928         entry = bnx2x_prev_path_get_entry(bp);
9929         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9930
9931         up(&bnx2x_prev_sem);
9932
9933         return val;
9934 }
9935
9936 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9937 {
9938         struct bnx2x_prev_path_list *tmp_list;
9939         int rc;
9940
9941         rc = down_interruptible(&bnx2x_prev_sem);
9942         if (rc) {
9943                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9944                 return rc;
9945         }
9946
9947         /* Check whether the entry for this path already exists */
9948         tmp_list = bnx2x_prev_path_get_entry(bp);
9949         if (tmp_list) {
9950                 if (!tmp_list->aer) {
9951                         BNX2X_ERR("Re-Marking the path.\n");
9952                 } else {
9953                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9954                            BP_PATH(bp));
9955                         tmp_list->aer = 0;
9956                 }
9957                 up(&bnx2x_prev_sem);
9958                 return 0;
9959         }
9960         up(&bnx2x_prev_sem);
9961
9962         /* Create an entry for this path and add it */
9963         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9964         if (!tmp_list) {
9965                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9966                 return -ENOMEM;
9967         }
9968
9969         tmp_list->bus = bp->pdev->bus->number;
9970         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9971         tmp_list->path = BP_PATH(bp);
9972         tmp_list->aer = 0;
9973         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9974
9975         rc = down_interruptible(&bnx2x_prev_sem);
9976         if (rc) {
9977                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9978                 kfree(tmp_list);
9979         } else {
9980                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9981                    BP_PATH(bp));
9982                 list_add(&tmp_list->list, &bnx2x_prev_list);
9983                 up(&bnx2x_prev_sem);
9984         }
9985
9986         return rc;
9987 }
9988
9989 static int bnx2x_do_flr(struct bnx2x *bp)
9990 {
9991         struct pci_dev *dev = bp->pdev;
9992
9993         if (CHIP_IS_E1x(bp)) {
9994                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9995                 return -EINVAL;
9996         }
9997
9998         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9999         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10000                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10001                           bp->common.bc_ver);
10002                 return -EINVAL;
10003         }
10004
10005         if (!pci_wait_for_pending_transaction(dev))
10006                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10007
10008         BNX2X_DEV_INFO("Initiating FLR\n");
10009         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10010
10011         return 0;
10012 }
10013
10014 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10015 {
10016         int rc;
10017
10018         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10019
10020         /* Test if previous unload process was already finished for this path */
10021         if (bnx2x_prev_is_path_marked(bp))
10022                 return bnx2x_prev_mcp_done(bp);
10023
10024         BNX2X_DEV_INFO("Path is unmarked\n");
10025
10026         /* If function has FLR capabilities, and existing FW version matches
10027          * the one required, then FLR will be sufficient to clean any residue
10028          * left by previous driver
10029          */
10030         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10031
10032         if (!rc) {
10033                 /* fw version is good */
10034                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10035                 rc = bnx2x_do_flr(bp);
10036         }
10037
10038         if (!rc) {
10039                 /* FLR was performed */
10040                 BNX2X_DEV_INFO("FLR successful\n");
10041                 return 0;
10042         }
10043
10044         BNX2X_DEV_INFO("Could not FLR\n");
10045
10046         /* Close the MCP request, return failure*/
10047         rc = bnx2x_prev_mcp_done(bp);
10048         if (!rc)
10049                 rc = BNX2X_PREV_WAIT_NEEDED;
10050
10051         return rc;
10052 }
10053
10054 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10055 {
10056         u32 reset_reg, tmp_reg = 0, rc;
10057         bool prev_undi = false;
10058         struct bnx2x_mac_vals mac_vals;
10059
10060         /* It is possible a previous function received 'common' answer,
10061          * but hasn't loaded yet, therefore creating a scenario of
10062          * multiple functions receiving 'common' on the same path.
10063          */
10064         BNX2X_DEV_INFO("Common unload Flow\n");
10065
10066         memset(&mac_vals, 0, sizeof(mac_vals));
10067
10068         if (bnx2x_prev_is_path_marked(bp))
10069                 return bnx2x_prev_mcp_done(bp);
10070
10071         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10072
10073         /* Reset should be performed after BRB is emptied */
10074         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10075                 u32 timer_count = 1000;
10076
10077                 /* Close the MAC Rx to prevent BRB from filling up */
10078                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10079
10080                 /* close LLH filters towards the BRB */
10081                 bnx2x_set_rx_filter(&bp->link_params, 0);
10082
10083                 /* Check if the UNDI driver was previously loaded
10084                  * UNDI driver initializes CID offset for normal bell to 0x7
10085                  */
10086                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10087                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10088                         if (tmp_reg == 0x7) {
10089                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10090                                 prev_undi = true;
10091                                 /* clear the UNDI indication */
10092                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10093                                 /* clear possible idle check errors */
10094                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10095                         }
10096                 }
10097                 if (!CHIP_IS_E1x(bp))
10098                         /* block FW from writing to host */
10099                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10100
10101                 /* wait until BRB is empty */
10102                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10103                 while (timer_count) {
10104                         u32 prev_brb = tmp_reg;
10105
10106                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10107                         if (!tmp_reg)
10108                                 break;
10109
10110                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10111
10112                         /* reset timer as long as BRB actually gets emptied */
10113                         if (prev_brb > tmp_reg)
10114                                 timer_count = 1000;
10115                         else
10116                                 timer_count--;
10117
10118                         /* If UNDI resides in memory, manually increment it */
10119                         if (prev_undi)
10120                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10121
10122                         udelay(10);
10123                 }
10124
10125                 if (!timer_count)
10126                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10127         }
10128
10129         /* No packets are in the pipeline, path is ready for reset */
10130         bnx2x_reset_common(bp);
10131
10132         if (mac_vals.xmac_addr)
10133                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10134         if (mac_vals.umac_addr)
10135                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10136         if (mac_vals.emac_addr)
10137                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10138         if (mac_vals.bmac_addr) {
10139                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10140                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10141         }
10142
10143         rc = bnx2x_prev_mark_path(bp, prev_undi);
10144         if (rc) {
10145                 bnx2x_prev_mcp_done(bp);
10146                 return rc;
10147         }
10148
10149         return bnx2x_prev_mcp_done(bp);
10150 }
10151
10152 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10153  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10154  * the addresses of the transaction, resulting in was-error bit set in the pci
10155  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10156  * to clear the interrupt which detected this from the pglueb and the was done
10157  * bit
10158  */
10159 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10160 {
10161         if (!CHIP_IS_E1x(bp)) {
10162                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10163                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10164                         DP(BNX2X_MSG_SP,
10165                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10166                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10167                                1 << BP_FUNC(bp));
10168                 }
10169         }
10170 }
10171
10172 static int bnx2x_prev_unload(struct bnx2x *bp)
10173 {
10174         int time_counter = 10;
10175         u32 rc, fw, hw_lock_reg, hw_lock_val;
10176         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10177
10178         /* clear hw from errors which may have resulted from an interrupted
10179          * dmae transaction.
10180          */
10181         bnx2x_prev_interrupted_dmae(bp);
10182
10183         /* Release previously held locks */
10184         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10185                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10186                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10187
10188         hw_lock_val = REG_RD(bp, hw_lock_reg);
10189         if (hw_lock_val) {
10190                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10191                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10192                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10193                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10194                 }
10195
10196                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10197                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10198         } else
10199                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10200
10201         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10202                 BNX2X_DEV_INFO("Release previously held alr\n");
10203                 bnx2x_release_alr(bp);
10204         }
10205
10206         do {
10207                 int aer = 0;
10208                 /* Lock MCP using an unload request */
10209                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10210                 if (!fw) {
10211                         BNX2X_ERR("MCP response failure, aborting\n");
10212                         rc = -EBUSY;
10213                         break;
10214                 }
10215
10216                 rc = down_interruptible(&bnx2x_prev_sem);
10217                 if (rc) {
10218                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10219                                   rc);
10220                 } else {
10221                         /* If Path is marked by EEH, ignore unload status */
10222                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10223                                  bnx2x_prev_path_get_entry(bp)->aer);
10224                         up(&bnx2x_prev_sem);
10225                 }
10226
10227                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10228                         rc = bnx2x_prev_unload_common(bp);
10229                         break;
10230                 }
10231
10232                 /* non-common reply from MCP might require looping */
10233                 rc = bnx2x_prev_unload_uncommon(bp);
10234                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10235                         break;
10236
10237                 msleep(20);
10238         } while (--time_counter);
10239
10240         if (!time_counter || rc) {
10241                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10242                 rc = -EBUSY;
10243         }
10244
10245         /* Mark function if its port was used to boot from SAN */
10246         if (bnx2x_port_after_undi(bp))
10247                 bp->link_params.feature_config_flags |=
10248                         FEATURE_CONFIG_BOOT_FROM_SAN;
10249
10250         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10251
10252         return rc;
10253 }
10254
10255 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10256 {
10257         u32 val, val2, val3, val4, id, boot_mode;
10258         u16 pmc;
10259
10260         /* Get the chip revision id and number. */
10261         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10262         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10263         id = ((val & 0xffff) << 16);
10264         val = REG_RD(bp, MISC_REG_CHIP_REV);
10265         id |= ((val & 0xf) << 12);
10266
10267         /* Metal is read from PCI regs, but we can't access >=0x400 from
10268          * the configuration space (so we need to reg_rd)
10269          */
10270         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10271         id |= (((val >> 24) & 0xf) << 4);
10272         val = REG_RD(bp, MISC_REG_BOND_ID);
10273         id |= (val & 0xf);
10274         bp->common.chip_id = id;
10275
10276         /* force 57811 according to MISC register */
10277         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10278                 if (CHIP_IS_57810(bp))
10279                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10280                                 (bp->common.chip_id & 0x0000FFFF);
10281                 else if (CHIP_IS_57810_MF(bp))
10282                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10283                                 (bp->common.chip_id & 0x0000FFFF);
10284                 bp->common.chip_id |= 0x1;
10285         }
10286
10287         /* Set doorbell size */
10288         bp->db_size = (1 << BNX2X_DB_SHIFT);
10289
10290         if (!CHIP_IS_E1x(bp)) {
10291                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10292                 if ((val & 1) == 0)
10293                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10294                 else
10295                         val = (val >> 1) & 1;
10296                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10297                                                        "2_PORT_MODE");
10298                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10299                                                  CHIP_2_PORT_MODE;
10300
10301                 if (CHIP_MODE_IS_4_PORT(bp))
10302                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10303                 else
10304                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10305         } else {
10306                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10307                 bp->pfid = bp->pf_num;                  /* 0..7 */
10308         }
10309
10310         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10311
10312         bp->link_params.chip_id = bp->common.chip_id;
10313         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10314
10315         val = (REG_RD(bp, 0x2874) & 0x55);
10316         if ((bp->common.chip_id & 0x1) ||
10317             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10318                 bp->flags |= ONE_PORT_FLAG;
10319                 BNX2X_DEV_INFO("single port device\n");
10320         }
10321
10322         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10323         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10324                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10325         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10326                        bp->common.flash_size, bp->common.flash_size);
10327
10328         bnx2x_init_shmem(bp);
10329
10330         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10331                                         MISC_REG_GENERIC_CR_1 :
10332                                         MISC_REG_GENERIC_CR_0));
10333
10334         bp->link_params.shmem_base = bp->common.shmem_base;
10335         bp->link_params.shmem2_base = bp->common.shmem2_base;
10336         if (SHMEM2_RD(bp, size) >
10337             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10338                 bp->link_params.lfa_base =
10339                 REG_RD(bp, bp->common.shmem2_base +
10340                        (u32)offsetof(struct shmem2_region,
10341                                      lfa_host_addr[BP_PORT(bp)]));
10342         else
10343                 bp->link_params.lfa_base = 0;
10344         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10345                        bp->common.shmem_base, bp->common.shmem2_base);
10346
10347         if (!bp->common.shmem_base) {
10348                 BNX2X_DEV_INFO("MCP not active\n");
10349                 bp->flags |= NO_MCP_FLAG;
10350                 return;
10351         }
10352
10353         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10354         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10355
10356         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10357                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10358                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10359
10360         bp->link_params.feature_config_flags = 0;
10361         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10362         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10363                 bp->link_params.feature_config_flags |=
10364                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10365         else
10366                 bp->link_params.feature_config_flags &=
10367                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10368
10369         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10370         bp->common.bc_ver = val;
10371         BNX2X_DEV_INFO("bc_ver %X\n", val);
10372         if (val < BNX2X_BC_VER) {
10373                 /* for now only warn
10374                  * later we might need to enforce this */
10375                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10376                           BNX2X_BC_VER, val);
10377         }
10378         bp->link_params.feature_config_flags |=
10379                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10380                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10381
10382         bp->link_params.feature_config_flags |=
10383                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10384                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10385         bp->link_params.feature_config_flags |=
10386                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10387                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10388         bp->link_params.feature_config_flags |=
10389                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10390                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10391
10392         bp->link_params.feature_config_flags |=
10393                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10394                 FEATURE_CONFIG_MT_SUPPORT : 0;
10395
10396         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10397                         BC_SUPPORTS_PFC_STATS : 0;
10398
10399         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10400                         BC_SUPPORTS_FCOE_FEATURES : 0;
10401
10402         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10403                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10404
10405         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10406                         BC_SUPPORTS_RMMOD_CMD : 0;
10407
10408         boot_mode = SHMEM_RD(bp,
10409                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10410                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10411         switch (boot_mode) {
10412         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10413                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10414                 break;
10415         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10416                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10417                 break;
10418         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10419                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10420                 break;
10421         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10422                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10423                 break;
10424         }
10425
10426         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10427         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10428
10429         BNX2X_DEV_INFO("%sWoL capable\n",
10430                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10431
10432         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10433         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10434         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10435         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10436
10437         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10438                  val, val2, val3, val4);
10439 }
10440
10441 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10442 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10443
10444 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10445 {
10446         int pfid = BP_FUNC(bp);
10447         int igu_sb_id;
10448         u32 val;
10449         u8 fid, igu_sb_cnt = 0;
10450
10451         bp->igu_base_sb = 0xff;
10452         if (CHIP_INT_MODE_IS_BC(bp)) {
10453                 int vn = BP_VN(bp);
10454                 igu_sb_cnt = bp->igu_sb_cnt;
10455                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10456                         FP_SB_MAX_E1x;
10457
10458                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10459                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10460
10461                 return 0;
10462         }
10463
10464         /* IGU in normal mode - read CAM */
10465         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10466              igu_sb_id++) {
10467                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10468                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10469                         continue;
10470                 fid = IGU_FID(val);
10471                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10472                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10473                                 continue;
10474                         if (IGU_VEC(val) == 0)
10475                                 /* default status block */
10476                                 bp->igu_dsb_id = igu_sb_id;
10477                         else {
10478                                 if (bp->igu_base_sb == 0xff)
10479                                         bp->igu_base_sb = igu_sb_id;
10480                                 igu_sb_cnt++;
10481                         }
10482                 }
10483         }
10484
10485 #ifdef CONFIG_PCI_MSI
10486         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10487          * optional that number of CAM entries will not be equal to the value
10488          * advertised in PCI.
10489          * Driver should use the minimal value of both as the actual status
10490          * block count
10491          */
10492         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10493 #endif
10494
10495         if (igu_sb_cnt == 0) {
10496                 BNX2X_ERR("CAM configuration error\n");
10497                 return -EINVAL;
10498         }
10499
10500         return 0;
10501 }
10502
10503 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10504 {
10505         int cfg_size = 0, idx, port = BP_PORT(bp);
10506
10507         /* Aggregation of supported attributes of all external phys */
10508         bp->port.supported[0] = 0;
10509         bp->port.supported[1] = 0;
10510         switch (bp->link_params.num_phys) {
10511         case 1:
10512                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10513                 cfg_size = 1;
10514                 break;
10515         case 2:
10516                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10517                 cfg_size = 1;
10518                 break;
10519         case 3:
10520                 if (bp->link_params.multi_phy_config &
10521                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10522                         bp->port.supported[1] =
10523                                 bp->link_params.phy[EXT_PHY1].supported;
10524                         bp->port.supported[0] =
10525                                 bp->link_params.phy[EXT_PHY2].supported;
10526                 } else {
10527                         bp->port.supported[0] =
10528                                 bp->link_params.phy[EXT_PHY1].supported;
10529                         bp->port.supported[1] =
10530                                 bp->link_params.phy[EXT_PHY2].supported;
10531                 }
10532                 cfg_size = 2;
10533                 break;
10534         }
10535
10536         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10537                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10538                            SHMEM_RD(bp,
10539                            dev_info.port_hw_config[port].external_phy_config),
10540                            SHMEM_RD(bp,
10541                            dev_info.port_hw_config[port].external_phy_config2));
10542                         return;
10543         }
10544
10545         if (CHIP_IS_E3(bp))
10546                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10547         else {
10548                 switch (switch_cfg) {
10549                 case SWITCH_CFG_1G:
10550                         bp->port.phy_addr = REG_RD(
10551                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10552                         break;
10553                 case SWITCH_CFG_10G:
10554                         bp->port.phy_addr = REG_RD(
10555                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10556                         break;
10557                 default:
10558                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10559                                   bp->port.link_config[0]);
10560                         return;
10561                 }
10562         }
10563         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10564         /* mask what we support according to speed_cap_mask per configuration */
10565         for (idx = 0; idx < cfg_size; idx++) {
10566                 if (!(bp->link_params.speed_cap_mask[idx] &
10567                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10568                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10569
10570                 if (!(bp->link_params.speed_cap_mask[idx] &
10571                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10572                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10573
10574                 if (!(bp->link_params.speed_cap_mask[idx] &
10575                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10576                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10577
10578                 if (!(bp->link_params.speed_cap_mask[idx] &
10579                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10580                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10581
10582                 if (!(bp->link_params.speed_cap_mask[idx] &
10583                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10584                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10585                                                      SUPPORTED_1000baseT_Full);
10586
10587                 if (!(bp->link_params.speed_cap_mask[idx] &
10588                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10589                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10590
10591                 if (!(bp->link_params.speed_cap_mask[idx] &
10592                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10593                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10594
10595                 if (!(bp->link_params.speed_cap_mask[idx] &
10596                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10597                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10598         }
10599
10600         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10601                        bp->port.supported[1]);
10602 }
10603
10604 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10605 {
10606         u32 link_config, idx, cfg_size = 0;
10607         bp->port.advertising[0] = 0;
10608         bp->port.advertising[1] = 0;
10609         switch (bp->link_params.num_phys) {
10610         case 1:
10611         case 2:
10612                 cfg_size = 1;
10613                 break;
10614         case 3:
10615                 cfg_size = 2;
10616                 break;
10617         }
10618         for (idx = 0; idx < cfg_size; idx++) {
10619                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10620                 link_config = bp->port.link_config[idx];
10621                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10622                 case PORT_FEATURE_LINK_SPEED_AUTO:
10623                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10624                                 bp->link_params.req_line_speed[idx] =
10625                                         SPEED_AUTO_NEG;
10626                                 bp->port.advertising[idx] |=
10627                                         bp->port.supported[idx];
10628                                 if (bp->link_params.phy[EXT_PHY1].type ==
10629                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10630                                         bp->port.advertising[idx] |=
10631                                         (SUPPORTED_100baseT_Half |
10632                                          SUPPORTED_100baseT_Full);
10633                         } else {
10634                                 /* force 10G, no AN */
10635                                 bp->link_params.req_line_speed[idx] =
10636                                         SPEED_10000;
10637                                 bp->port.advertising[idx] |=
10638                                         (ADVERTISED_10000baseT_Full |
10639                                          ADVERTISED_FIBRE);
10640                                 continue;
10641                         }
10642                         break;
10643
10644                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10645                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10646                                 bp->link_params.req_line_speed[idx] =
10647                                         SPEED_10;
10648                                 bp->port.advertising[idx] |=
10649                                         (ADVERTISED_10baseT_Full |
10650                                          ADVERTISED_TP);
10651                         } else {
10652                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10653                                             link_config,
10654                                     bp->link_params.speed_cap_mask[idx]);
10655                                 return;
10656                         }
10657                         break;
10658
10659                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10660                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10661                                 bp->link_params.req_line_speed[idx] =
10662                                         SPEED_10;
10663                                 bp->link_params.req_duplex[idx] =
10664                                         DUPLEX_HALF;
10665                                 bp->port.advertising[idx] |=
10666                                         (ADVERTISED_10baseT_Half |
10667                                          ADVERTISED_TP);
10668                         } else {
10669                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10670                                             link_config,
10671                                           bp->link_params.speed_cap_mask[idx]);
10672                                 return;
10673                         }
10674                         break;
10675
10676                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10677                         if (bp->port.supported[idx] &
10678                             SUPPORTED_100baseT_Full) {
10679                                 bp->link_params.req_line_speed[idx] =
10680                                         SPEED_100;
10681                                 bp->port.advertising[idx] |=
10682                                         (ADVERTISED_100baseT_Full |
10683                                          ADVERTISED_TP);
10684                         } else {
10685                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10686                                             link_config,
10687                                           bp->link_params.speed_cap_mask[idx]);
10688                                 return;
10689                         }
10690                         break;
10691
10692                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10693                         if (bp->port.supported[idx] &
10694                             SUPPORTED_100baseT_Half) {
10695                                 bp->link_params.req_line_speed[idx] =
10696                                                                 SPEED_100;
10697                                 bp->link_params.req_duplex[idx] =
10698                                                                 DUPLEX_HALF;
10699                                 bp->port.advertising[idx] |=
10700                                         (ADVERTISED_100baseT_Half |
10701                                          ADVERTISED_TP);
10702                         } else {
10703                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10704                                     link_config,
10705                                     bp->link_params.speed_cap_mask[idx]);
10706                                 return;
10707                         }
10708                         break;
10709
10710                 case PORT_FEATURE_LINK_SPEED_1G:
10711                         if (bp->port.supported[idx] &
10712                             SUPPORTED_1000baseT_Full) {
10713                                 bp->link_params.req_line_speed[idx] =
10714                                         SPEED_1000;
10715                                 bp->port.advertising[idx] |=
10716                                         (ADVERTISED_1000baseT_Full |
10717                                          ADVERTISED_TP);
10718                         } else {
10719                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10720                                     link_config,
10721                                     bp->link_params.speed_cap_mask[idx]);
10722                                 return;
10723                         }
10724                         break;
10725
10726                 case PORT_FEATURE_LINK_SPEED_2_5G:
10727                         if (bp->port.supported[idx] &
10728                             SUPPORTED_2500baseX_Full) {
10729                                 bp->link_params.req_line_speed[idx] =
10730                                         SPEED_2500;
10731                                 bp->port.advertising[idx] |=
10732                                         (ADVERTISED_2500baseX_Full |
10733                                                 ADVERTISED_TP);
10734                         } else {
10735                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10736                                     link_config,
10737                                     bp->link_params.speed_cap_mask[idx]);
10738                                 return;
10739                         }
10740                         break;
10741
10742                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10743                         if (bp->port.supported[idx] &
10744                             SUPPORTED_10000baseT_Full) {
10745                                 bp->link_params.req_line_speed[idx] =
10746                                         SPEED_10000;
10747                                 bp->port.advertising[idx] |=
10748                                         (ADVERTISED_10000baseT_Full |
10749                                                 ADVERTISED_FIBRE);
10750                         } else {
10751                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10752                                     link_config,
10753                                     bp->link_params.speed_cap_mask[idx]);
10754                                 return;
10755                         }
10756                         break;
10757                 case PORT_FEATURE_LINK_SPEED_20G:
10758                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10759
10760                         break;
10761                 default:
10762                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10763                                   link_config);
10764                                 bp->link_params.req_line_speed[idx] =
10765                                                         SPEED_AUTO_NEG;
10766                                 bp->port.advertising[idx] =
10767                                                 bp->port.supported[idx];
10768                         break;
10769                 }
10770
10771                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10772                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10773                 if (bp->link_params.req_flow_ctrl[idx] ==
10774                     BNX2X_FLOW_CTRL_AUTO) {
10775                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10776                                 bp->link_params.req_flow_ctrl[idx] =
10777                                                         BNX2X_FLOW_CTRL_NONE;
10778                         else
10779                                 bnx2x_set_requested_fc(bp);
10780                 }
10781
10782                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10783                                bp->link_params.req_line_speed[idx],
10784                                bp->link_params.req_duplex[idx],
10785                                bp->link_params.req_flow_ctrl[idx],
10786                                bp->port.advertising[idx]);
10787         }
10788 }
10789
10790 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10791 {
10792         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10793         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10794         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10795         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10796 }
10797
10798 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10799 {
10800         int port = BP_PORT(bp);
10801         u32 config;
10802         u32 ext_phy_type, ext_phy_config, eee_mode;
10803
10804         bp->link_params.bp = bp;
10805         bp->link_params.port = port;
10806
10807         bp->link_params.lane_config =
10808                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10809
10810         bp->link_params.speed_cap_mask[0] =
10811                 SHMEM_RD(bp,
10812                          dev_info.port_hw_config[port].speed_capability_mask) &
10813                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10814         bp->link_params.speed_cap_mask[1] =
10815                 SHMEM_RD(bp,
10816                          dev_info.port_hw_config[port].speed_capability_mask2) &
10817                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10818         bp->port.link_config[0] =
10819                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10820
10821         bp->port.link_config[1] =
10822                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10823
10824         bp->link_params.multi_phy_config =
10825                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10826         /* If the device is capable of WoL, set the default state according
10827          * to the HW
10828          */
10829         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10830         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10831                    (config & PORT_FEATURE_WOL_ENABLED));
10832
10833         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10834             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10835                 bp->flags |= NO_ISCSI_FLAG;
10836         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10837             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10838                 bp->flags |= NO_FCOE_FLAG;
10839
10840         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10841                        bp->link_params.lane_config,
10842                        bp->link_params.speed_cap_mask[0],
10843                        bp->port.link_config[0]);
10844
10845         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10846                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10847         bnx2x_phy_probe(&bp->link_params);
10848         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10849
10850         bnx2x_link_settings_requested(bp);
10851
10852         /*
10853          * If connected directly, work with the internal PHY, otherwise, work
10854          * with the external PHY
10855          */
10856         ext_phy_config =
10857                 SHMEM_RD(bp,
10858                          dev_info.port_hw_config[port].external_phy_config);
10859         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10860         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10861                 bp->mdio.prtad = bp->port.phy_addr;
10862
10863         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10864                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10865                 bp->mdio.prtad =
10866                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10867
10868         /* Configure link feature according to nvram value */
10869         eee_mode = (((SHMEM_RD(bp, dev_info.
10870                       port_feature_config[port].eee_power_mode)) &
10871                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10872                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10873         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10874                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10875                                            EEE_MODE_ENABLE_LPI |
10876                                            EEE_MODE_OUTPUT_TIME;
10877         } else {
10878                 bp->link_params.eee_mode = 0;
10879         }
10880 }
10881
10882 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10883 {
10884         u32 no_flags = NO_ISCSI_FLAG;
10885         int port = BP_PORT(bp);
10886         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10887                                 drv_lic_key[port].max_iscsi_conn);
10888
10889         if (!CNIC_SUPPORT(bp)) {
10890                 bp->flags |= no_flags;
10891                 return;
10892         }
10893
10894         /* Get the number of maximum allowed iSCSI connections */
10895         bp->cnic_eth_dev.max_iscsi_conn =
10896                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10897                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10898
10899         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10900                        bp->cnic_eth_dev.max_iscsi_conn);
10901
10902         /*
10903          * If maximum allowed number of connections is zero -
10904          * disable the feature.
10905          */
10906         if (!bp->cnic_eth_dev.max_iscsi_conn)
10907                 bp->flags |= no_flags;
10908 }
10909
10910 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10911 {
10912         /* Port info */
10913         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10914                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10915         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10916                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10917
10918         /* Node info */
10919         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10920                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10921         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10922                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10923 }
10924
10925 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10926 {
10927         u8 count = 0;
10928
10929         if (IS_MF(bp)) {
10930                 u8 fid;
10931
10932                 /* iterate over absolute function ids for this path: */
10933                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10934                         if (IS_MF_SD(bp)) {
10935                                 u32 cfg = MF_CFG_RD(bp,
10936                                                     func_mf_config[fid].config);
10937
10938                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10939                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10940                                             FUNC_MF_CFG_PROTOCOL_FCOE))
10941                                         count++;
10942                         } else {
10943                                 u32 cfg = MF_CFG_RD(bp,
10944                                                     func_ext_config[fid].
10945                                                                       func_cfg);
10946
10947                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10948                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10949                                         count++;
10950                         }
10951                 }
10952         } else { /* SF */
10953                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10954
10955                 for (port = 0; port < port_cnt; port++) {
10956                         u32 lic = SHMEM_RD(bp,
10957                                            drv_lic_key[port].max_fcoe_conn) ^
10958                                   FW_ENCODE_32BIT_PATTERN;
10959                         if (lic)
10960                                 count++;
10961                 }
10962         }
10963
10964         return count;
10965 }
10966
10967 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10968 {
10969         int port = BP_PORT(bp);
10970         int func = BP_ABS_FUNC(bp);
10971         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10972                                 drv_lic_key[port].max_fcoe_conn);
10973         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10974
10975         if (!CNIC_SUPPORT(bp)) {
10976                 bp->flags |= NO_FCOE_FLAG;
10977                 return;
10978         }
10979
10980         /* Get the number of maximum allowed FCoE connections */
10981         bp->cnic_eth_dev.max_fcoe_conn =
10982                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10983                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10984
10985         /* Calculate the number of maximum allowed FCoE tasks */
10986         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
10987
10988         /* check if FCoE resources must be shared between different functions */
10989         if (num_fcoe_func)
10990                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
10991
10992         /* Read the WWN: */
10993         if (!IS_MF(bp)) {
10994                 /* Port info */
10995                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10996                         SHMEM_RD(bp,
10997                                  dev_info.port_hw_config[port].
10998                                  fcoe_wwn_port_name_upper);
10999                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11000                         SHMEM_RD(bp,
11001                                  dev_info.port_hw_config[port].
11002                                  fcoe_wwn_port_name_lower);
11003
11004                 /* Node info */
11005                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11006                         SHMEM_RD(bp,
11007                                  dev_info.port_hw_config[port].
11008                                  fcoe_wwn_node_name_upper);
11009                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11010                         SHMEM_RD(bp,
11011                                  dev_info.port_hw_config[port].
11012                                  fcoe_wwn_node_name_lower);
11013         } else if (!IS_MF_SD(bp)) {
11014                 /*
11015                  * Read the WWN info only if the FCoE feature is enabled for
11016                  * this function.
11017                  */
11018                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11019                         bnx2x_get_ext_wwn_info(bp, func);
11020
11021         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11022                 bnx2x_get_ext_wwn_info(bp, func);
11023         }
11024
11025         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11026
11027         /*
11028          * If maximum allowed number of connections is zero -
11029          * disable the feature.
11030          */
11031         if (!bp->cnic_eth_dev.max_fcoe_conn)
11032                 bp->flags |= NO_FCOE_FLAG;
11033 }
11034
11035 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11036 {
11037         /*
11038          * iSCSI may be dynamically disabled but reading
11039          * info here we will decrease memory usage by driver
11040          * if the feature is disabled for good
11041          */
11042         bnx2x_get_iscsi_info(bp);
11043         bnx2x_get_fcoe_info(bp);
11044 }
11045
11046 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11047 {
11048         u32 val, val2;
11049         int func = BP_ABS_FUNC(bp);
11050         int port = BP_PORT(bp);
11051         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11052         u8 *fip_mac = bp->fip_mac;
11053
11054         if (IS_MF(bp)) {
11055                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11056                  * FCoE MAC then the appropriate feature should be disabled.
11057                  * In non SD mode features configuration comes from struct
11058                  * func_ext_config.
11059                  */
11060                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11061                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11062                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11063                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11064                                                  iscsi_mac_addr_upper);
11065                                 val = MF_CFG_RD(bp, func_ext_config[func].
11066                                                 iscsi_mac_addr_lower);
11067                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11068                                 BNX2X_DEV_INFO
11069                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11070                         } else {
11071                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11072                         }
11073
11074                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11075                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11076                                                  fcoe_mac_addr_upper);
11077                                 val = MF_CFG_RD(bp, func_ext_config[func].
11078                                                 fcoe_mac_addr_lower);
11079                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11080                                 BNX2X_DEV_INFO
11081                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11082                         } else {
11083                                 bp->flags |= NO_FCOE_FLAG;
11084                         }
11085
11086                         bp->mf_ext_config = cfg;
11087
11088                 } else { /* SD MODE */
11089                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11090                                 /* use primary mac as iscsi mac */
11091                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11092
11093                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11094                                 BNX2X_DEV_INFO
11095                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11096                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11097                                 /* use primary mac as fip mac */
11098                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11099                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11100                                 BNX2X_DEV_INFO
11101                                         ("Read FIP MAC: %pM\n", fip_mac);
11102                         }
11103                 }
11104
11105                 /* If this is a storage-only interface, use SAN mac as
11106                  * primary MAC. Notice that for SD this is already the case,
11107                  * as the SAN mac was copied from the primary MAC.
11108                  */
11109                 if (IS_MF_FCOE_AFEX(bp))
11110                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11111         } else {
11112                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11113                                 iscsi_mac_upper);
11114                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11115                                iscsi_mac_lower);
11116                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11117
11118                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11119                                 fcoe_fip_mac_upper);
11120                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11121                                fcoe_fip_mac_lower);
11122                 bnx2x_set_mac_buf(fip_mac, val, val2);
11123         }
11124
11125         /* Disable iSCSI OOO if MAC configuration is invalid. */
11126         if (!is_valid_ether_addr(iscsi_mac)) {
11127                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11128                 memset(iscsi_mac, 0, ETH_ALEN);
11129         }
11130
11131         /* Disable FCoE if MAC configuration is invalid. */
11132         if (!is_valid_ether_addr(fip_mac)) {
11133                 bp->flags |= NO_FCOE_FLAG;
11134                 memset(bp->fip_mac, 0, ETH_ALEN);
11135         }
11136 }
11137
11138 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11139 {
11140         u32 val, val2;
11141         int func = BP_ABS_FUNC(bp);
11142         int port = BP_PORT(bp);
11143
11144         /* Zero primary MAC configuration */
11145         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11146
11147         if (BP_NOMCP(bp)) {
11148                 BNX2X_ERROR("warning: random MAC workaround active\n");
11149                 eth_hw_addr_random(bp->dev);
11150         } else if (IS_MF(bp)) {
11151                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11152                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11153                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11154                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11155                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11156
11157                 if (CNIC_SUPPORT(bp))
11158                         bnx2x_get_cnic_mac_hwinfo(bp);
11159         } else {
11160                 /* in SF read MACs from port configuration */
11161                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11162                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11163                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11164
11165                 if (CNIC_SUPPORT(bp))
11166                         bnx2x_get_cnic_mac_hwinfo(bp);
11167         }
11168
11169         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11170
11171         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11172                 dev_err(&bp->pdev->dev,
11173                         "bad Ethernet MAC address configuration: %pM\n"
11174                         "change it manually before bringing up the appropriate network interface\n",
11175                         bp->dev->dev_addr);
11176 }
11177
11178 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11179 {
11180         int tmp;
11181         u32 cfg;
11182
11183         if (IS_VF(bp))
11184                 return 0;
11185
11186         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11187                 /* Take function: tmp = func */
11188                 tmp = BP_ABS_FUNC(bp);
11189                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11190                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11191         } else {
11192                 /* Take port: tmp = port */
11193                 tmp = BP_PORT(bp);
11194                 cfg = SHMEM_RD(bp,
11195                                dev_info.port_hw_config[tmp].generic_features);
11196                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11197         }
11198         return cfg;
11199 }
11200
11201 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11202 {
11203         int /*abs*/func = BP_ABS_FUNC(bp);
11204         int vn;
11205         u32 val = 0;
11206         int rc = 0;
11207
11208         bnx2x_get_common_hwinfo(bp);
11209
11210         /*
11211          * initialize IGU parameters
11212          */
11213         if (CHIP_IS_E1x(bp)) {
11214                 bp->common.int_block = INT_BLOCK_HC;
11215
11216                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11217                 bp->igu_base_sb = 0;
11218         } else {
11219                 bp->common.int_block = INT_BLOCK_IGU;
11220
11221                 /* do not allow device reset during IGU info processing */
11222                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11223
11224                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11225
11226                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11227                         int tout = 5000;
11228
11229                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11230
11231                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11232                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11233                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11234
11235                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11236                                 tout--;
11237                                 usleep_range(1000, 2000);
11238                         }
11239
11240                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11241                                 dev_err(&bp->pdev->dev,
11242                                         "FORCING Normal Mode failed!!!\n");
11243                                 bnx2x_release_hw_lock(bp,
11244                                                       HW_LOCK_RESOURCE_RESET);
11245                                 return -EPERM;
11246                         }
11247                 }
11248
11249                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11250                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11251                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11252                 } else
11253                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11254
11255                 rc = bnx2x_get_igu_cam_info(bp);
11256                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11257                 if (rc)
11258                         return rc;
11259         }
11260
11261         /*
11262          * set base FW non-default (fast path) status block id, this value is
11263          * used to initialize the fw_sb_id saved on the fp/queue structure to
11264          * determine the id used by the FW.
11265          */
11266         if (CHIP_IS_E1x(bp))
11267                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11268         else /*
11269               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11270               * the same queue are indicated on the same IGU SB). So we prefer
11271               * FW and IGU SBs to be the same value.
11272               */
11273                 bp->base_fw_ndsb = bp->igu_base_sb;
11274
11275         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11276                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11277                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11278
11279         /*
11280          * Initialize MF configuration
11281          */
11282
11283         bp->mf_ov = 0;
11284         bp->mf_mode = 0;
11285         vn = BP_VN(bp);
11286
11287         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11288                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11289                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11290                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11291
11292                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11293                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11294                 else
11295                         bp->common.mf_cfg_base = bp->common.shmem_base +
11296                                 offsetof(struct shmem_region, func_mb) +
11297                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11298                 /*
11299                  * get mf configuration:
11300                  * 1. Existence of MF configuration
11301                  * 2. MAC address must be legal (check only upper bytes)
11302                  *    for  Switch-Independent mode;
11303                  *    OVLAN must be legal for Switch-Dependent mode
11304                  * 3. SF_MODE configures specific MF mode
11305                  */
11306                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11307                         /* get mf configuration */
11308                         val = SHMEM_RD(bp,
11309                                        dev_info.shared_feature_config.config);
11310                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11311
11312                         switch (val) {
11313                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11314                                 val = MF_CFG_RD(bp, func_mf_config[func].
11315                                                 mac_upper);
11316                                 /* check for legal mac (upper bytes)*/
11317                                 if (val != 0xffff) {
11318                                         bp->mf_mode = MULTI_FUNCTION_SI;
11319                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11320                                                    func_mf_config[func].config);
11321                                 } else
11322                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11323                                 break;
11324                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11325                                 if ((!CHIP_IS_E1x(bp)) &&
11326                                     (MF_CFG_RD(bp, func_mf_config[func].
11327                                                mac_upper) != 0xffff) &&
11328                                     (SHMEM2_HAS(bp,
11329                                                 afex_driver_support))) {
11330                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11331                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11332                                                 func_mf_config[func].config);
11333                                 } else {
11334                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11335                                 }
11336                                 break;
11337                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11338                                 /* get OV configuration */
11339                                 val = MF_CFG_RD(bp,
11340                                         func_mf_config[FUNC_0].e1hov_tag);
11341                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11342
11343                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11344                                         bp->mf_mode = MULTI_FUNCTION_SD;
11345                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11346                                                 func_mf_config[func].config);
11347                                 } else
11348                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11349                                 break;
11350                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11351                                 bp->mf_config[vn] = 0;
11352                                 break;
11353                         default:
11354                                 /* Unknown configuration: reset mf_config */
11355                                 bp->mf_config[vn] = 0;
11356                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11357                         }
11358                 }
11359
11360                 BNX2X_DEV_INFO("%s function mode\n",
11361                                IS_MF(bp) ? "multi" : "single");
11362
11363                 switch (bp->mf_mode) {
11364                 case MULTI_FUNCTION_SD:
11365                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11366                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11367                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11368                                 bp->mf_ov = val;
11369                                 bp->path_has_ovlan = true;
11370
11371                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11372                                                func, bp->mf_ov, bp->mf_ov);
11373                         } else {
11374                                 dev_err(&bp->pdev->dev,
11375                                         "No valid MF OV for func %d, aborting\n",
11376                                         func);
11377                                 return -EPERM;
11378                         }
11379                         break;
11380                 case MULTI_FUNCTION_AFEX:
11381                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11382                         break;
11383                 case MULTI_FUNCTION_SI:
11384                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11385                                        func);
11386                         break;
11387                 default:
11388                         if (vn) {
11389                                 dev_err(&bp->pdev->dev,
11390                                         "VN %d is in a single function mode, aborting\n",
11391                                         vn);
11392                                 return -EPERM;
11393                         }
11394                         break;
11395                 }
11396
11397                 /* check if other port on the path needs ovlan:
11398                  * Since MF configuration is shared between ports
11399                  * Possible mixed modes are only
11400                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11401                  */
11402                 if (CHIP_MODE_IS_4_PORT(bp) &&
11403                     !bp->path_has_ovlan &&
11404                     !IS_MF(bp) &&
11405                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11406                         u8 other_port = !BP_PORT(bp);
11407                         u8 other_func = BP_PATH(bp) + 2*other_port;
11408                         val = MF_CFG_RD(bp,
11409                                         func_mf_config[other_func].e1hov_tag);
11410                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11411                                 bp->path_has_ovlan = true;
11412                 }
11413         }
11414
11415         /* adjust igu_sb_cnt to MF for E1x */
11416         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11417                 bp->igu_sb_cnt /= E1HVN_MAX;
11418
11419         /* port info */
11420         bnx2x_get_port_hwinfo(bp);
11421
11422         /* Get MAC addresses */
11423         bnx2x_get_mac_hwinfo(bp);
11424
11425         bnx2x_get_cnic_info(bp);
11426
11427         return rc;
11428 }
11429
11430 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11431 {
11432         int cnt, i, block_end, rodi;
11433         char vpd_start[BNX2X_VPD_LEN+1];
11434         char str_id_reg[VENDOR_ID_LEN+1];
11435         char str_id_cap[VENDOR_ID_LEN+1];
11436         char *vpd_data;
11437         char *vpd_extended_data = NULL;
11438         u8 len;
11439
11440         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11441         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11442
11443         if (cnt < BNX2X_VPD_LEN)
11444                 goto out_not_found;
11445
11446         /* VPD RO tag should be first tag after identifier string, hence
11447          * we should be able to find it in first BNX2X_VPD_LEN chars
11448          */
11449         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11450                              PCI_VPD_LRDT_RO_DATA);
11451         if (i < 0)
11452                 goto out_not_found;
11453
11454         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11455                     pci_vpd_lrdt_size(&vpd_start[i]);
11456
11457         i += PCI_VPD_LRDT_TAG_SIZE;
11458
11459         if (block_end > BNX2X_VPD_LEN) {
11460                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11461                 if (vpd_extended_data  == NULL)
11462                         goto out_not_found;
11463
11464                 /* read rest of vpd image into vpd_extended_data */
11465                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11466                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11467                                    block_end - BNX2X_VPD_LEN,
11468                                    vpd_extended_data + BNX2X_VPD_LEN);
11469                 if (cnt < (block_end - BNX2X_VPD_LEN))
11470                         goto out_not_found;
11471                 vpd_data = vpd_extended_data;
11472         } else
11473                 vpd_data = vpd_start;
11474
11475         /* now vpd_data holds full vpd content in both cases */
11476
11477         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11478                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11479         if (rodi < 0)
11480                 goto out_not_found;
11481
11482         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11483
11484         if (len != VENDOR_ID_LEN)
11485                 goto out_not_found;
11486
11487         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11488
11489         /* vendor specific info */
11490         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11491         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11492         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11493             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11494
11495                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11496                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11497                 if (rodi >= 0) {
11498                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11499
11500                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11501
11502                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11503                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11504                                 bp->fw_ver[len] = ' ';
11505                         }
11506                 }
11507                 kfree(vpd_extended_data);
11508                 return;
11509         }
11510 out_not_found:
11511         kfree(vpd_extended_data);
11512         return;
11513 }
11514
11515 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11516 {
11517         u32 flags = 0;
11518
11519         if (CHIP_REV_IS_FPGA(bp))
11520                 SET_FLAGS(flags, MODE_FPGA);
11521         else if (CHIP_REV_IS_EMUL(bp))
11522                 SET_FLAGS(flags, MODE_EMUL);
11523         else
11524                 SET_FLAGS(flags, MODE_ASIC);
11525
11526         if (CHIP_MODE_IS_4_PORT(bp))
11527                 SET_FLAGS(flags, MODE_PORT4);
11528         else
11529                 SET_FLAGS(flags, MODE_PORT2);
11530
11531         if (CHIP_IS_E2(bp))
11532                 SET_FLAGS(flags, MODE_E2);
11533         else if (CHIP_IS_E3(bp)) {
11534                 SET_FLAGS(flags, MODE_E3);
11535                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11536                         SET_FLAGS(flags, MODE_E3_A0);
11537                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11538                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11539         }
11540
11541         if (IS_MF(bp)) {
11542                 SET_FLAGS(flags, MODE_MF);
11543                 switch (bp->mf_mode) {
11544                 case MULTI_FUNCTION_SD:
11545                         SET_FLAGS(flags, MODE_MF_SD);
11546                         break;
11547                 case MULTI_FUNCTION_SI:
11548                         SET_FLAGS(flags, MODE_MF_SI);
11549                         break;
11550                 case MULTI_FUNCTION_AFEX:
11551                         SET_FLAGS(flags, MODE_MF_AFEX);
11552                         break;
11553                 }
11554         } else
11555                 SET_FLAGS(flags, MODE_SF);
11556
11557 #if defined(__LITTLE_ENDIAN)
11558         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11559 #else /*(__BIG_ENDIAN)*/
11560         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11561 #endif
11562         INIT_MODE_FLAGS(bp) = flags;
11563 }
11564
11565 static int bnx2x_init_bp(struct bnx2x *bp)
11566 {
11567         int func;
11568         int rc;
11569
11570         mutex_init(&bp->port.phy_mutex);
11571         mutex_init(&bp->fw_mb_mutex);
11572         spin_lock_init(&bp->stats_lock);
11573         sema_init(&bp->stats_sema, 1);
11574
11575         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11576         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11577         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11578         if (IS_PF(bp)) {
11579                 rc = bnx2x_get_hwinfo(bp);
11580                 if (rc)
11581                         return rc;
11582         } else {
11583                 eth_zero_addr(bp->dev->dev_addr);
11584         }
11585
11586         bnx2x_set_modes_bitmap(bp);
11587
11588         rc = bnx2x_alloc_mem_bp(bp);
11589         if (rc)
11590                 return rc;
11591
11592         bnx2x_read_fwinfo(bp);
11593
11594         func = BP_FUNC(bp);
11595
11596         /* need to reset chip if undi was active */
11597         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11598                 /* init fw_seq */
11599                 bp->fw_seq =
11600                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11601                                                         DRV_MSG_SEQ_NUMBER_MASK;
11602                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11603
11604                 bnx2x_prev_unload(bp);
11605         }
11606
11607         if (CHIP_REV_IS_FPGA(bp))
11608                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11609
11610         if (BP_NOMCP(bp) && (func == 0))
11611                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11612
11613         bp->disable_tpa = disable_tpa;
11614         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11615
11616         /* Set TPA flags */
11617         if (bp->disable_tpa) {
11618                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11619                 bp->dev->features &= ~NETIF_F_LRO;
11620         } else {
11621                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11622                 bp->dev->features |= NETIF_F_LRO;
11623         }
11624
11625         if (CHIP_IS_E1(bp))
11626                 bp->dropless_fc = 0;
11627         else
11628                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11629
11630         bp->mrrs = mrrs;
11631
11632         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11633         if (IS_VF(bp))
11634                 bp->rx_ring_size = MAX_RX_AVAIL;
11635
11636         /* make sure that the numbers are in the right granularity */
11637         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11638         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11639
11640         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11641
11642         init_timer(&bp->timer);
11643         bp->timer.expires = jiffies + bp->current_interval;
11644         bp->timer.data = (unsigned long) bp;
11645         bp->timer.function = bnx2x_timer;
11646
11647         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11648             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11649             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11650             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11651                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11652                 bnx2x_dcbx_init_params(bp);
11653         } else {
11654                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11655         }
11656
11657         if (CHIP_IS_E1x(bp))
11658                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11659         else
11660                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11661
11662         /* multiple tx priority */
11663         if (IS_VF(bp))
11664                 bp->max_cos = 1;
11665         else if (CHIP_IS_E1x(bp))
11666                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11667         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11668                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11669         else if (CHIP_IS_E3B0(bp))
11670                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11671         else
11672                 BNX2X_ERR("unknown chip %x revision %x\n",
11673                           CHIP_NUM(bp), CHIP_REV(bp));
11674         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11675
11676         /* We need at least one default status block for slow-path events,
11677          * second status block for the L2 queue, and a third status block for
11678          * CNIC if supported.
11679          */
11680         if (IS_VF(bp))
11681                 bp->min_msix_vec_cnt = 1;
11682         else if (CNIC_SUPPORT(bp))
11683                 bp->min_msix_vec_cnt = 3;
11684         else /* PF w/o cnic */
11685                 bp->min_msix_vec_cnt = 2;
11686         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11687
11688         bp->dump_preset_idx = 1;
11689
11690         return rc;
11691 }
11692
11693 /****************************************************************************
11694 * General service functions
11695 ****************************************************************************/
11696
11697 /*
11698  * net_device service functions
11699  */
11700
11701 /* called with rtnl_lock */
11702 static int bnx2x_open(struct net_device *dev)
11703 {
11704         struct bnx2x *bp = netdev_priv(dev);
11705         int rc;
11706
11707         bp->stats_init = true;
11708
11709         netif_carrier_off(dev);
11710
11711         bnx2x_set_power_state(bp, PCI_D0);
11712
11713         /* If parity had happen during the unload, then attentions
11714          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11715          * want the first function loaded on the current engine to
11716          * complete the recovery.
11717          * Parity recovery is only relevant for PF driver.
11718          */
11719         if (IS_PF(bp)) {
11720                 int other_engine = BP_PATH(bp) ? 0 : 1;
11721                 bool other_load_status, load_status;
11722                 bool global = false;
11723
11724                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11725                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11726                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11727                     bnx2x_chk_parity_attn(bp, &global, true)) {
11728                         do {
11729                                 /* If there are attentions and they are in a
11730                                  * global blocks, set the GLOBAL_RESET bit
11731                                  * regardless whether it will be this function
11732                                  * that will complete the recovery or not.
11733                                  */
11734                                 if (global)
11735                                         bnx2x_set_reset_global(bp);
11736
11737                                 /* Only the first function on the current
11738                                  * engine should try to recover in open. In case
11739                                  * of attentions in global blocks only the first
11740                                  * in the chip should try to recover.
11741                                  */
11742                                 if ((!load_status &&
11743                                      (!global || !other_load_status)) &&
11744                                       bnx2x_trylock_leader_lock(bp) &&
11745                                       !bnx2x_leader_reset(bp)) {
11746                                         netdev_info(bp->dev,
11747                                                     "Recovered in open\n");
11748                                         break;
11749                                 }
11750
11751                                 /* recovery has failed... */
11752                                 bnx2x_set_power_state(bp, PCI_D3hot);
11753                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11754
11755                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11756                                           "If you still see this message after a few retries then power cycle is required.\n");
11757
11758                                 return -EAGAIN;
11759                         } while (0);
11760                 }
11761         }
11762
11763         bp->recovery_state = BNX2X_RECOVERY_DONE;
11764         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11765         if (rc)
11766                 return rc;
11767         return bnx2x_open_epilog(bp);
11768 }
11769
11770 /* called with rtnl_lock */
11771 static int bnx2x_close(struct net_device *dev)
11772 {
11773         struct bnx2x *bp = netdev_priv(dev);
11774
11775         /* Unload the driver, release IRQs */
11776         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11777
11778         return 0;
11779 }
11780
11781 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11782                                       struct bnx2x_mcast_ramrod_params *p)
11783 {
11784         int mc_count = netdev_mc_count(bp->dev);
11785         struct bnx2x_mcast_list_elem *mc_mac =
11786                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11787         struct netdev_hw_addr *ha;
11788
11789         if (!mc_mac)
11790                 return -ENOMEM;
11791
11792         INIT_LIST_HEAD(&p->mcast_list);
11793
11794         netdev_for_each_mc_addr(ha, bp->dev) {
11795                 mc_mac->mac = bnx2x_mc_addr(ha);
11796                 list_add_tail(&mc_mac->link, &p->mcast_list);
11797                 mc_mac++;
11798         }
11799
11800         p->mcast_list_len = mc_count;
11801
11802         return 0;
11803 }
11804
11805 static void bnx2x_free_mcast_macs_list(
11806         struct bnx2x_mcast_ramrod_params *p)
11807 {
11808         struct bnx2x_mcast_list_elem *mc_mac =
11809                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11810                                  link);
11811
11812         WARN_ON(!mc_mac);
11813         kfree(mc_mac);
11814 }
11815
11816 /**
11817  * bnx2x_set_uc_list - configure a new unicast MACs list.
11818  *
11819  * @bp: driver handle
11820  *
11821  * We will use zero (0) as a MAC type for these MACs.
11822  */
11823 static int bnx2x_set_uc_list(struct bnx2x *bp)
11824 {
11825         int rc;
11826         struct net_device *dev = bp->dev;
11827         struct netdev_hw_addr *ha;
11828         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11829         unsigned long ramrod_flags = 0;
11830
11831         /* First schedule a cleanup up of old configuration */
11832         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11833         if (rc < 0) {
11834                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11835                 return rc;
11836         }
11837
11838         netdev_for_each_uc_addr(ha, dev) {
11839                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11840                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11841                 if (rc == -EEXIST) {
11842                         DP(BNX2X_MSG_SP,
11843                            "Failed to schedule ADD operations: %d\n", rc);
11844                         /* do not treat adding same MAC as error */
11845                         rc = 0;
11846
11847                 } else if (rc < 0) {
11848
11849                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11850                                   rc);
11851                         return rc;
11852                 }
11853         }
11854
11855         /* Execute the pending commands */
11856         __set_bit(RAMROD_CONT, &ramrod_flags);
11857         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11858                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11859 }
11860
11861 static int bnx2x_set_mc_list(struct bnx2x *bp)
11862 {
11863         struct net_device *dev = bp->dev;
11864         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11865         int rc = 0;
11866
11867         rparam.mcast_obj = &bp->mcast_obj;
11868
11869         /* first, clear all configured multicast MACs */
11870         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11871         if (rc < 0) {
11872                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11873                 return rc;
11874         }
11875
11876         /* then, configure a new MACs list */
11877         if (netdev_mc_count(dev)) {
11878                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11879                 if (rc) {
11880                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11881                                   rc);
11882                         return rc;
11883                 }
11884
11885                 /* Now add the new MACs */
11886                 rc = bnx2x_config_mcast(bp, &rparam,
11887                                         BNX2X_MCAST_CMD_ADD);
11888                 if (rc < 0)
11889                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11890                                   rc);
11891
11892                 bnx2x_free_mcast_macs_list(&rparam);
11893         }
11894
11895         return rc;
11896 }
11897
11898 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11899 void bnx2x_set_rx_mode(struct net_device *dev)
11900 {
11901         struct bnx2x *bp = netdev_priv(dev);
11902
11903         if (bp->state != BNX2X_STATE_OPEN) {
11904                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11905                 return;
11906         } else {
11907                 /* Schedule an SP task to handle rest of change */
11908                 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
11909                 smp_mb__before_clear_bit();
11910                 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
11911                 smp_mb__after_clear_bit();
11912                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11913         }
11914 }
11915
11916 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
11917 {
11918         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11919
11920         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11921
11922         netif_addr_lock_bh(bp->dev);
11923
11924         if (bp->dev->flags & IFF_PROMISC) {
11925                 rx_mode = BNX2X_RX_MODE_PROMISC;
11926         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
11927                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
11928                     CHIP_IS_E1(bp))) {
11929                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11930         } else {
11931                 if (IS_PF(bp)) {
11932                         /* some multicasts */
11933                         if (bnx2x_set_mc_list(bp) < 0)
11934                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11935
11936                         /* release bh lock, as bnx2x_set_uc_list might sleep */
11937                         netif_addr_unlock_bh(bp->dev);
11938                         if (bnx2x_set_uc_list(bp) < 0)
11939                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11940                         netif_addr_lock_bh(bp->dev);
11941                 } else {
11942                         /* configuring mcast to a vf involves sleeping (when we
11943                          * wait for the pf's response).
11944                          */
11945                         smp_mb__before_clear_bit();
11946                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11947                                 &bp->sp_rtnl_state);
11948                         smp_mb__after_clear_bit();
11949                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11950                 }
11951         }
11952
11953         bp->rx_mode = rx_mode;
11954         /* handle ISCSI SD mode */
11955         if (IS_MF_ISCSI_SD(bp))
11956                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11957
11958         /* Schedule the rx_mode command */
11959         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11960                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11961                 netif_addr_unlock_bh(bp->dev);
11962                 return;
11963         }
11964
11965         if (IS_PF(bp)) {
11966                 bnx2x_set_storm_rx_mode(bp);
11967                 netif_addr_unlock_bh(bp->dev);
11968         } else {
11969                 /* VF will need to request the PF to make this change, and so
11970                  * the VF needs to release the bottom-half lock prior to the
11971                  * request (as it will likely require sleep on the VF side)
11972                  */
11973                 netif_addr_unlock_bh(bp->dev);
11974                 bnx2x_vfpf_storm_rx_mode(bp);
11975         }
11976 }
11977
11978 /* called with rtnl_lock */
11979 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11980                            int devad, u16 addr)
11981 {
11982         struct bnx2x *bp = netdev_priv(netdev);
11983         u16 value;
11984         int rc;
11985
11986         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11987            prtad, devad, addr);
11988
11989         /* The HW expects different devad if CL22 is used */
11990         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11991
11992         bnx2x_acquire_phy_lock(bp);
11993         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11994         bnx2x_release_phy_lock(bp);
11995         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11996
11997         if (!rc)
11998                 rc = value;
11999         return rc;
12000 }
12001
12002 /* called with rtnl_lock */
12003 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12004                             u16 addr, u16 value)
12005 {
12006         struct bnx2x *bp = netdev_priv(netdev);
12007         int rc;
12008
12009         DP(NETIF_MSG_LINK,
12010            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12011            prtad, devad, addr, value);
12012
12013         /* The HW expects different devad if CL22 is used */
12014         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12015
12016         bnx2x_acquire_phy_lock(bp);
12017         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12018         bnx2x_release_phy_lock(bp);
12019         return rc;
12020 }
12021
12022 /* called with rtnl_lock */
12023 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12024 {
12025         struct bnx2x *bp = netdev_priv(dev);
12026         struct mii_ioctl_data *mdio = if_mii(ifr);
12027
12028         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12029            mdio->phy_id, mdio->reg_num, mdio->val_in);
12030
12031         if (!netif_running(dev))
12032                 return -EAGAIN;
12033
12034         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12035 }
12036
12037 #ifdef CONFIG_NET_POLL_CONTROLLER
12038 static void poll_bnx2x(struct net_device *dev)
12039 {
12040         struct bnx2x *bp = netdev_priv(dev);
12041         int i;
12042
12043         for_each_eth_queue(bp, i) {
12044                 struct bnx2x_fastpath *fp = &bp->fp[i];
12045                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12046         }
12047 }
12048 #endif
12049
12050 static int bnx2x_validate_addr(struct net_device *dev)
12051 {
12052         struct bnx2x *bp = netdev_priv(dev);
12053
12054         /* query the bulletin board for mac address configured by the PF */
12055         if (IS_VF(bp))
12056                 bnx2x_sample_bulletin(bp);
12057
12058         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12059                 BNX2X_ERR("Non-valid Ethernet address\n");
12060                 return -EADDRNOTAVAIL;
12061         }
12062         return 0;
12063 }
12064
12065 static const struct net_device_ops bnx2x_netdev_ops = {
12066         .ndo_open               = bnx2x_open,
12067         .ndo_stop               = bnx2x_close,
12068         .ndo_start_xmit         = bnx2x_start_xmit,
12069         .ndo_select_queue       = bnx2x_select_queue,
12070         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12071         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12072         .ndo_validate_addr      = bnx2x_validate_addr,
12073         .ndo_do_ioctl           = bnx2x_ioctl,
12074         .ndo_change_mtu         = bnx2x_change_mtu,
12075         .ndo_fix_features       = bnx2x_fix_features,
12076         .ndo_set_features       = bnx2x_set_features,
12077         .ndo_tx_timeout         = bnx2x_tx_timeout,
12078 #ifdef CONFIG_NET_POLL_CONTROLLER
12079         .ndo_poll_controller    = poll_bnx2x,
12080 #endif
12081         .ndo_setup_tc           = bnx2x_setup_tc,
12082 #ifdef CONFIG_BNX2X_SRIOV
12083         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12084         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12085         .ndo_get_vf_config      = bnx2x_get_vf_config,
12086 #endif
12087 #ifdef NETDEV_FCOE_WWNN
12088         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12089 #endif
12090
12091 #ifdef CONFIG_NET_RX_BUSY_POLL
12092         .ndo_busy_poll          = bnx2x_low_latency_recv,
12093 #endif
12094 };
12095
12096 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12097 {
12098         struct device *dev = &bp->pdev->dev;
12099
12100         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12101                 bp->flags |= USING_DAC_FLAG;
12102                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12103                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12104                         return -EIO;
12105                 }
12106         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12107                 dev_err(dev, "System does not support DMA, aborting\n");
12108                 return -EIO;
12109         }
12110
12111         return 0;
12112 }
12113
12114 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12115                           struct net_device *dev, unsigned long board_type)
12116 {
12117         int rc;
12118         u32 pci_cfg_dword;
12119         bool chip_is_e1x = (board_type == BCM57710 ||
12120                             board_type == BCM57711 ||
12121                             board_type == BCM57711E);
12122
12123         SET_NETDEV_DEV(dev, &pdev->dev);
12124
12125         bp->dev = dev;
12126         bp->pdev = pdev;
12127
12128         rc = pci_enable_device(pdev);
12129         if (rc) {
12130                 dev_err(&bp->pdev->dev,
12131                         "Cannot enable PCI device, aborting\n");
12132                 goto err_out;
12133         }
12134
12135         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12136                 dev_err(&bp->pdev->dev,
12137                         "Cannot find PCI device base address, aborting\n");
12138                 rc = -ENODEV;
12139                 goto err_out_disable;
12140         }
12141
12142         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12143                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12144                 rc = -ENODEV;
12145                 goto err_out_disable;
12146         }
12147
12148         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12149         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12150             PCICFG_REVESION_ID_ERROR_VAL) {
12151                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12152                 rc = -ENODEV;
12153                 goto err_out_disable;
12154         }
12155
12156         if (atomic_read(&pdev->enable_cnt) == 1) {
12157                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12158                 if (rc) {
12159                         dev_err(&bp->pdev->dev,
12160                                 "Cannot obtain PCI resources, aborting\n");
12161                         goto err_out_disable;
12162                 }
12163
12164                 pci_set_master(pdev);
12165                 pci_save_state(pdev);
12166         }
12167
12168         if (IS_PF(bp)) {
12169                 if (!pdev->pm_cap) {
12170                         dev_err(&bp->pdev->dev,
12171                                 "Cannot find power management capability, aborting\n");
12172                         rc = -EIO;
12173                         goto err_out_release;
12174                 }
12175         }
12176
12177         if (!pci_is_pcie(pdev)) {
12178                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12179                 rc = -EIO;
12180                 goto err_out_release;
12181         }
12182
12183         rc = bnx2x_set_coherency_mask(bp);
12184         if (rc)
12185                 goto err_out_release;
12186
12187         dev->mem_start = pci_resource_start(pdev, 0);
12188         dev->base_addr = dev->mem_start;
12189         dev->mem_end = pci_resource_end(pdev, 0);
12190
12191         dev->irq = pdev->irq;
12192
12193         bp->regview = pci_ioremap_bar(pdev, 0);
12194         if (!bp->regview) {
12195                 dev_err(&bp->pdev->dev,
12196                         "Cannot map register space, aborting\n");
12197                 rc = -ENOMEM;
12198                 goto err_out_release;
12199         }
12200
12201         /* In E1/E1H use pci device function given by kernel.
12202          * In E2/E3 read physical function from ME register since these chips
12203          * support Physical Device Assignment where kernel BDF maybe arbitrary
12204          * (depending on hypervisor).
12205          */
12206         if (chip_is_e1x) {
12207                 bp->pf_num = PCI_FUNC(pdev->devfn);
12208         } else {
12209                 /* chip is E2/3*/
12210                 pci_read_config_dword(bp->pdev,
12211                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12212                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12213                                   ME_REG_ABS_PF_NUM_SHIFT);
12214         }
12215         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12216
12217         /* clean indirect addresses */
12218         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12219                                PCICFG_VENDOR_ID_OFFSET);
12220         /*
12221          * Clean the following indirect addresses for all functions since it
12222          * is not used by the driver.
12223          */
12224         if (IS_PF(bp)) {
12225                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12226                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12227                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12228                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12229
12230                 if (chip_is_e1x) {
12231                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12232                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12233                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12234                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12235                 }
12236
12237                 /* Enable internal target-read (in case we are probed after PF
12238                  * FLR). Must be done prior to any BAR read access. Only for
12239                  * 57712 and up
12240                  */
12241                 if (!chip_is_e1x)
12242                         REG_WR(bp,
12243                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12244         }
12245
12246         dev->watchdog_timeo = TX_TIMEOUT;
12247
12248         dev->netdev_ops = &bnx2x_netdev_ops;
12249         bnx2x_set_ethtool_ops(bp, dev);
12250
12251         dev->priv_flags |= IFF_UNICAST_FLT;
12252
12253         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12254                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12255                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12256                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12257         if (!CHIP_IS_E1x(bp)) {
12258                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12259                 dev->hw_enc_features =
12260                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12261                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12262                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12263         }
12264
12265         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12266                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12267
12268         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12269         if (bp->flags & USING_DAC_FLAG)
12270                 dev->features |= NETIF_F_HIGHDMA;
12271
12272         /* Add Loopback capability to the device */
12273         dev->hw_features |= NETIF_F_LOOPBACK;
12274
12275 #ifdef BCM_DCBNL
12276         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12277 #endif
12278
12279         /* get_port_hwinfo() will set prtad and mmds properly */
12280         bp->mdio.prtad = MDIO_PRTAD_NONE;
12281         bp->mdio.mmds = 0;
12282         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12283         bp->mdio.dev = dev;
12284         bp->mdio.mdio_read = bnx2x_mdio_read;
12285         bp->mdio.mdio_write = bnx2x_mdio_write;
12286
12287         return 0;
12288
12289 err_out_release:
12290         if (atomic_read(&pdev->enable_cnt) == 1)
12291                 pci_release_regions(pdev);
12292
12293 err_out_disable:
12294         pci_disable_device(pdev);
12295         pci_set_drvdata(pdev, NULL);
12296
12297 err_out:
12298         return rc;
12299 }
12300
12301 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12302                                        enum bnx2x_pci_bus_speed *speed)
12303 {
12304         u32 link_speed, val = 0;
12305
12306         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12307         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12308
12309         link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12310
12311         switch (link_speed) {
12312         case 3:
12313                 *speed = BNX2X_PCI_LINK_SPEED_8000;
12314                 break;
12315         case 2:
12316                 *speed = BNX2X_PCI_LINK_SPEED_5000;
12317                 break;
12318         default:
12319                 *speed = BNX2X_PCI_LINK_SPEED_2500;
12320         }
12321 }
12322
12323 static int bnx2x_check_firmware(struct bnx2x *bp)
12324 {
12325         const struct firmware *firmware = bp->firmware;
12326         struct bnx2x_fw_file_hdr *fw_hdr;
12327         struct bnx2x_fw_file_section *sections;
12328         u32 offset, len, num_ops;
12329         __be16 *ops_offsets;
12330         int i;
12331         const u8 *fw_ver;
12332
12333         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12334                 BNX2X_ERR("Wrong FW size\n");
12335                 return -EINVAL;
12336         }
12337
12338         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12339         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12340
12341         /* Make sure none of the offsets and sizes make us read beyond
12342          * the end of the firmware data */
12343         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12344                 offset = be32_to_cpu(sections[i].offset);
12345                 len = be32_to_cpu(sections[i].len);
12346                 if (offset + len > firmware->size) {
12347                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12348                         return -EINVAL;
12349                 }
12350         }
12351
12352         /* Likewise for the init_ops offsets */
12353         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12354         ops_offsets = (__force __be16 *)(firmware->data + offset);
12355         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12356
12357         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12358                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12359                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12360                         return -EINVAL;
12361                 }
12362         }
12363
12364         /* Check FW version */
12365         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12366         fw_ver = firmware->data + offset;
12367         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12368             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12369             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12370             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12371                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12372                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12373                        BCM_5710_FW_MAJOR_VERSION,
12374                        BCM_5710_FW_MINOR_VERSION,
12375                        BCM_5710_FW_REVISION_VERSION,
12376                        BCM_5710_FW_ENGINEERING_VERSION);
12377                 return -EINVAL;
12378         }
12379
12380         return 0;
12381 }
12382
12383 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12384 {
12385         const __be32 *source = (const __be32 *)_source;
12386         u32 *target = (u32 *)_target;
12387         u32 i;
12388
12389         for (i = 0; i < n/4; i++)
12390                 target[i] = be32_to_cpu(source[i]);
12391 }
12392
12393 /*
12394    Ops array is stored in the following format:
12395    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12396  */
12397 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12398 {
12399         const __be32 *source = (const __be32 *)_source;
12400         struct raw_op *target = (struct raw_op *)_target;
12401         u32 i, j, tmp;
12402
12403         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12404                 tmp = be32_to_cpu(source[j]);
12405                 target[i].op = (tmp >> 24) & 0xff;
12406                 target[i].offset = tmp & 0xffffff;
12407                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12408         }
12409 }
12410
12411 /* IRO array is stored in the following format:
12412  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12413  */
12414 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12415 {
12416         const __be32 *source = (const __be32 *)_source;
12417         struct iro *target = (struct iro *)_target;
12418         u32 i, j, tmp;
12419
12420         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12421                 target[i].base = be32_to_cpu(source[j]);
12422                 j++;
12423                 tmp = be32_to_cpu(source[j]);
12424                 target[i].m1 = (tmp >> 16) & 0xffff;
12425                 target[i].m2 = tmp & 0xffff;
12426                 j++;
12427                 tmp = be32_to_cpu(source[j]);
12428                 target[i].m3 = (tmp >> 16) & 0xffff;
12429                 target[i].size = tmp & 0xffff;
12430                 j++;
12431         }
12432 }
12433
12434 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12435 {
12436         const __be16 *source = (const __be16 *)_source;
12437         u16 *target = (u16 *)_target;
12438         u32 i;
12439
12440         for (i = 0; i < n/2; i++)
12441                 target[i] = be16_to_cpu(source[i]);
12442 }
12443
12444 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12445 do {                                                                    \
12446         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12447         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12448         if (!bp->arr)                                                   \
12449                 goto lbl;                                               \
12450         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12451              (u8 *)bp->arr, len);                                       \
12452 } while (0)
12453
12454 static int bnx2x_init_firmware(struct bnx2x *bp)
12455 {
12456         const char *fw_file_name;
12457         struct bnx2x_fw_file_hdr *fw_hdr;
12458         int rc;
12459
12460         if (bp->firmware)
12461                 return 0;
12462
12463         if (CHIP_IS_E1(bp))
12464                 fw_file_name = FW_FILE_NAME_E1;
12465         else if (CHIP_IS_E1H(bp))
12466                 fw_file_name = FW_FILE_NAME_E1H;
12467         else if (!CHIP_IS_E1x(bp))
12468                 fw_file_name = FW_FILE_NAME_E2;
12469         else {
12470                 BNX2X_ERR("Unsupported chip revision\n");
12471                 return -EINVAL;
12472         }
12473         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12474
12475         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12476         if (rc) {
12477                 BNX2X_ERR("Can't load firmware file %s\n",
12478                           fw_file_name);
12479                 goto request_firmware_exit;
12480         }
12481
12482         rc = bnx2x_check_firmware(bp);
12483         if (rc) {
12484                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12485                 goto request_firmware_exit;
12486         }
12487
12488         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12489
12490         /* Initialize the pointers to the init arrays */
12491         /* Blob */
12492         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12493
12494         /* Opcodes */
12495         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12496
12497         /* Offsets */
12498         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12499                             be16_to_cpu_n);
12500
12501         /* STORMs firmware */
12502         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12503                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12504         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12505                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12506         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12507                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12508         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12509                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12510         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12511                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12512         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12513                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12514         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12515                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12516         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12517                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12518         /* IRO */
12519         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12520
12521         return 0;
12522
12523 iro_alloc_err:
12524         kfree(bp->init_ops_offsets);
12525 init_offsets_alloc_err:
12526         kfree(bp->init_ops);
12527 init_ops_alloc_err:
12528         kfree(bp->init_data);
12529 request_firmware_exit:
12530         release_firmware(bp->firmware);
12531         bp->firmware = NULL;
12532
12533         return rc;
12534 }
12535
12536 static void bnx2x_release_firmware(struct bnx2x *bp)
12537 {
12538         kfree(bp->init_ops_offsets);
12539         kfree(bp->init_ops);
12540         kfree(bp->init_data);
12541         release_firmware(bp->firmware);
12542         bp->firmware = NULL;
12543 }
12544
12545 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12546         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12547         .init_hw_cmn      = bnx2x_init_hw_common,
12548         .init_hw_port     = bnx2x_init_hw_port,
12549         .init_hw_func     = bnx2x_init_hw_func,
12550
12551         .reset_hw_cmn     = bnx2x_reset_common,
12552         .reset_hw_port    = bnx2x_reset_port,
12553         .reset_hw_func    = bnx2x_reset_func,
12554
12555         .gunzip_init      = bnx2x_gunzip_init,
12556         .gunzip_end       = bnx2x_gunzip_end,
12557
12558         .init_fw          = bnx2x_init_firmware,
12559         .release_fw       = bnx2x_release_firmware,
12560 };
12561
12562 void bnx2x__init_func_obj(struct bnx2x *bp)
12563 {
12564         /* Prepare DMAE related driver resources */
12565         bnx2x_setup_dmae(bp);
12566
12567         bnx2x_init_func_obj(bp, &bp->func_obj,
12568                             bnx2x_sp(bp, func_rdata),
12569                             bnx2x_sp_mapping(bp, func_rdata),
12570                             bnx2x_sp(bp, func_afex_rdata),
12571                             bnx2x_sp_mapping(bp, func_afex_rdata),
12572                             &bnx2x_func_sp_drv);
12573 }
12574
12575 /* must be called after sriov-enable */
12576 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12577 {
12578         int cid_count = BNX2X_L2_MAX_CID(bp);
12579
12580         if (IS_SRIOV(bp))
12581                 cid_count += BNX2X_VF_CIDS;
12582
12583         if (CNIC_SUPPORT(bp))
12584                 cid_count += CNIC_CID_MAX;
12585
12586         return roundup(cid_count, QM_CID_ROUND);
12587 }
12588
12589 /**
12590  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12591  *
12592  * @dev:        pci device
12593  *
12594  */
12595 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12596 {
12597         int index;
12598         u16 control = 0;
12599
12600         /*
12601          * If MSI-X is not supported - return number of SBs needed to support
12602          * one fast path queue: one FP queue + SB for CNIC
12603          */
12604         if (!pdev->msix_cap) {
12605                 dev_info(&pdev->dev, "no msix capability found\n");
12606                 return 1 + cnic_cnt;
12607         }
12608         dev_info(&pdev->dev, "msix capability found\n");
12609
12610         /*
12611          * The value in the PCI configuration space is the index of the last
12612          * entry, namely one less than the actual size of the table, which is
12613          * exactly what we want to return from this function: number of all SBs
12614          * without the default SB.
12615          * For VFs there is no default SB, then we return (index+1).
12616          */
12617         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12618
12619         index = control & PCI_MSIX_FLAGS_QSIZE;
12620
12621         return index;
12622 }
12623
12624 static int set_max_cos_est(int chip_id)
12625 {
12626         switch (chip_id) {
12627         case BCM57710:
12628         case BCM57711:
12629         case BCM57711E:
12630                 return BNX2X_MULTI_TX_COS_E1X;
12631         case BCM57712:
12632         case BCM57712_MF:
12633                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12634         case BCM57800:
12635         case BCM57800_MF:
12636         case BCM57810:
12637         case BCM57810_MF:
12638         case BCM57840_4_10:
12639         case BCM57840_2_20:
12640         case BCM57840_O:
12641         case BCM57840_MFO:
12642         case BCM57840_MF:
12643         case BCM57811:
12644         case BCM57811_MF:
12645                 return BNX2X_MULTI_TX_COS_E3B0;
12646         case BCM57712_VF:
12647         case BCM57800_VF:
12648         case BCM57810_VF:
12649         case BCM57840_VF:
12650         case BCM57811_VF:
12651                 return 1;
12652         default:
12653                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12654                 return -ENODEV;
12655         }
12656 }
12657
12658 static int set_is_vf(int chip_id)
12659 {
12660         switch (chip_id) {
12661         case BCM57712_VF:
12662         case BCM57800_VF:
12663         case BCM57810_VF:
12664         case BCM57840_VF:
12665         case BCM57811_VF:
12666                 return true;
12667         default:
12668                 return false;
12669         }
12670 }
12671
12672 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12673
12674 static int bnx2x_init_one(struct pci_dev *pdev,
12675                                     const struct pci_device_id *ent)
12676 {
12677         struct net_device *dev = NULL;
12678         struct bnx2x *bp;
12679         int pcie_width;
12680         enum bnx2x_pci_bus_speed pcie_speed;
12681         int rc, max_non_def_sbs;
12682         int rx_count, tx_count, rss_count, doorbell_size;
12683         int max_cos_est;
12684         bool is_vf;
12685         int cnic_cnt;
12686
12687         /* An estimated maximum supported CoS number according to the chip
12688          * version.
12689          * We will try to roughly estimate the maximum number of CoSes this chip
12690          * may support in order to minimize the memory allocated for Tx
12691          * netdev_queue's. This number will be accurately calculated during the
12692          * initialization of bp->max_cos based on the chip versions AND chip
12693          * revision in the bnx2x_init_bp().
12694          */
12695         max_cos_est = set_max_cos_est(ent->driver_data);
12696         if (max_cos_est < 0)
12697                 return max_cos_est;
12698         is_vf = set_is_vf(ent->driver_data);
12699         cnic_cnt = is_vf ? 0 : 1;
12700
12701         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12702
12703         /* add another SB for VF as it has no default SB */
12704         max_non_def_sbs += is_vf ? 1 : 0;
12705
12706         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12707         rss_count = max_non_def_sbs - cnic_cnt;
12708
12709         if (rss_count < 1)
12710                 return -EINVAL;
12711
12712         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12713         rx_count = rss_count + cnic_cnt;
12714
12715         /* Maximum number of netdev Tx queues:
12716          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12717          */
12718         tx_count = rss_count * max_cos_est + cnic_cnt;
12719
12720         /* dev zeroed in init_etherdev */
12721         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12722         if (!dev)
12723                 return -ENOMEM;
12724
12725         bp = netdev_priv(dev);
12726
12727         bp->flags = 0;
12728         if (is_vf)
12729                 bp->flags |= IS_VF_FLAG;
12730
12731         bp->igu_sb_cnt = max_non_def_sbs;
12732         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12733         bp->msg_enable = debug;
12734         bp->cnic_support = cnic_cnt;
12735         bp->cnic_probe = bnx2x_cnic_probe;
12736
12737         pci_set_drvdata(pdev, dev);
12738
12739         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12740         if (rc < 0) {
12741                 free_netdev(dev);
12742                 return rc;
12743         }
12744
12745         BNX2X_DEV_INFO("This is a %s function\n",
12746                        IS_PF(bp) ? "physical" : "virtual");
12747         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12748         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12749         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12750                        tx_count, rx_count);
12751
12752         rc = bnx2x_init_bp(bp);
12753         if (rc)
12754                 goto init_one_exit;
12755
12756         /* Map doorbells here as we need the real value of bp->max_cos which
12757          * is initialized in bnx2x_init_bp() to determine the number of
12758          * l2 connections.
12759          */
12760         if (IS_VF(bp)) {
12761                 bp->doorbells = bnx2x_vf_doorbells(bp);
12762                 rc = bnx2x_vf_pci_alloc(bp);
12763                 if (rc)
12764                         goto init_one_exit;
12765         } else {
12766                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12767                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12768                         dev_err(&bp->pdev->dev,
12769                                 "Cannot map doorbells, bar size too small, aborting\n");
12770                         rc = -ENOMEM;
12771                         goto init_one_exit;
12772                 }
12773                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12774                                                 doorbell_size);
12775         }
12776         if (!bp->doorbells) {
12777                 dev_err(&bp->pdev->dev,
12778                         "Cannot map doorbell space, aborting\n");
12779                 rc = -ENOMEM;
12780                 goto init_one_exit;
12781         }
12782
12783         if (IS_VF(bp)) {
12784                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12785                 if (rc)
12786                         goto init_one_exit;
12787         }
12788
12789         /* Enable SRIOV if capability found in configuration space */
12790         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12791         if (rc)
12792                 goto init_one_exit;
12793
12794         /* calc qm_cid_count */
12795         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12796         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12797
12798         /* disable FCOE L2 queue for E1x*/
12799         if (CHIP_IS_E1x(bp))
12800                 bp->flags |= NO_FCOE_FLAG;
12801
12802         /* Set bp->num_queues for MSI-X mode*/
12803         bnx2x_set_num_queues(bp);
12804
12805         /* Configure interrupt mode: try to enable MSI-X/MSI if
12806          * needed.
12807          */
12808         rc = bnx2x_set_int_mode(bp);
12809         if (rc) {
12810                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12811                 goto init_one_exit;
12812         }
12813         BNX2X_DEV_INFO("set interrupts successfully\n");
12814
12815         /* register the net device */
12816         rc = register_netdev(dev);
12817         if (rc) {
12818                 dev_err(&pdev->dev, "Cannot register net device\n");
12819                 goto init_one_exit;
12820         }
12821         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12822
12823         if (!NO_FCOE(bp)) {
12824                 /* Add storage MAC address */
12825                 rtnl_lock();
12826                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12827                 rtnl_unlock();
12828         }
12829
12830         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12831         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12832                        pcie_width, pcie_speed);
12833
12834         BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12835                        board_info[ent->driver_data].name,
12836                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12837                        pcie_width,
12838                        pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12839                        pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12840                        pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12841                        "Unknown",
12842                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12843
12844         return 0;
12845
12846 init_one_exit:
12847         if (bp->regview)
12848                 iounmap(bp->regview);
12849
12850         if (IS_PF(bp) && bp->doorbells)
12851                 iounmap(bp->doorbells);
12852
12853         free_netdev(dev);
12854
12855         if (atomic_read(&pdev->enable_cnt) == 1)
12856                 pci_release_regions(pdev);
12857
12858         pci_disable_device(pdev);
12859         pci_set_drvdata(pdev, NULL);
12860
12861         return rc;
12862 }
12863
12864 static void __bnx2x_remove(struct pci_dev *pdev,
12865                            struct net_device *dev,
12866                            struct bnx2x *bp,
12867                            bool remove_netdev)
12868 {
12869         /* Delete storage MAC address */
12870         if (!NO_FCOE(bp)) {
12871                 rtnl_lock();
12872                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12873                 rtnl_unlock();
12874         }
12875
12876 #ifdef BCM_DCBNL
12877         /* Delete app tlvs from dcbnl */
12878         bnx2x_dcbnl_update_applist(bp, true);
12879 #endif
12880
12881         if (IS_PF(bp) &&
12882             !BP_NOMCP(bp) &&
12883             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12884                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12885
12886         /* Close the interface - either directly or implicitly */
12887         if (remove_netdev) {
12888                 unregister_netdev(dev);
12889         } else {
12890                 rtnl_lock();
12891                 dev_close(dev);
12892                 rtnl_unlock();
12893         }
12894
12895         bnx2x_iov_remove_one(bp);
12896
12897         /* Power on: we can't let PCI layer write to us while we are in D3 */
12898         if (IS_PF(bp))
12899                 bnx2x_set_power_state(bp, PCI_D0);
12900
12901         /* Disable MSI/MSI-X */
12902         bnx2x_disable_msi(bp);
12903
12904         /* Power off */
12905         if (IS_PF(bp))
12906                 bnx2x_set_power_state(bp, PCI_D3hot);
12907
12908         /* Make sure RESET task is not scheduled before continuing */
12909         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12910
12911         /* send message via vfpf channel to release the resources of this vf */
12912         if (IS_VF(bp))
12913                 bnx2x_vfpf_release(bp);
12914
12915         /* Assumes no further PCIe PM changes will occur */
12916         if (system_state == SYSTEM_POWER_OFF) {
12917                 pci_wake_from_d3(pdev, bp->wol);
12918                 pci_set_power_state(pdev, PCI_D3hot);
12919         }
12920
12921         if (bp->regview)
12922                 iounmap(bp->regview);
12923
12924         /* for vf doorbells are part of the regview and were unmapped along with
12925          * it. FW is only loaded by PF.
12926          */
12927         if (IS_PF(bp)) {
12928                 if (bp->doorbells)
12929                         iounmap(bp->doorbells);
12930
12931                 bnx2x_release_firmware(bp);
12932         }
12933         bnx2x_free_mem_bp(bp);
12934
12935         if (remove_netdev)
12936                 free_netdev(dev);
12937
12938         if (atomic_read(&pdev->enable_cnt) == 1)
12939                 pci_release_regions(pdev);
12940
12941         pci_disable_device(pdev);
12942         pci_set_drvdata(pdev, NULL);
12943 }
12944
12945 static void bnx2x_remove_one(struct pci_dev *pdev)
12946 {
12947         struct net_device *dev = pci_get_drvdata(pdev);
12948         struct bnx2x *bp;
12949
12950         if (!dev) {
12951                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12952                 return;
12953         }
12954         bp = netdev_priv(dev);
12955
12956         __bnx2x_remove(pdev, dev, bp, true);
12957 }
12958
12959 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12960 {
12961         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12962
12963         bp->rx_mode = BNX2X_RX_MODE_NONE;
12964
12965         if (CNIC_LOADED(bp))
12966                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12967
12968         /* Stop Tx */
12969         bnx2x_tx_disable(bp);
12970         /* Delete all NAPI objects */
12971         bnx2x_del_all_napi(bp);
12972         if (CNIC_LOADED(bp))
12973                 bnx2x_del_all_napi_cnic(bp);
12974         netdev_reset_tc(bp->dev);
12975
12976         del_timer_sync(&bp->timer);
12977         cancel_delayed_work(&bp->sp_task);
12978         cancel_delayed_work(&bp->period_task);
12979
12980         spin_lock_bh(&bp->stats_lock);
12981         bp->stats_state = STATS_STATE_DISABLED;
12982         spin_unlock_bh(&bp->stats_lock);
12983
12984         bnx2x_save_statistics(bp);
12985
12986         netif_carrier_off(bp->dev);
12987
12988         return 0;
12989 }
12990
12991 /**
12992  * bnx2x_io_error_detected - called when PCI error is detected
12993  * @pdev: Pointer to PCI device
12994  * @state: The current pci connection state
12995  *
12996  * This function is called after a PCI bus error affecting
12997  * this device has been detected.
12998  */
12999 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13000                                                 pci_channel_state_t state)
13001 {
13002         struct net_device *dev = pci_get_drvdata(pdev);
13003         struct bnx2x *bp = netdev_priv(dev);
13004
13005         rtnl_lock();
13006
13007         BNX2X_ERR("IO error detected\n");
13008
13009         netif_device_detach(dev);
13010
13011         if (state == pci_channel_io_perm_failure) {
13012                 rtnl_unlock();
13013                 return PCI_ERS_RESULT_DISCONNECT;
13014         }
13015
13016         if (netif_running(dev))
13017                 bnx2x_eeh_nic_unload(bp);
13018
13019         bnx2x_prev_path_mark_eeh(bp);
13020
13021         pci_disable_device(pdev);
13022
13023         rtnl_unlock();
13024
13025         /* Request a slot reset */
13026         return PCI_ERS_RESULT_NEED_RESET;
13027 }
13028
13029 /**
13030  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13031  * @pdev: Pointer to PCI device
13032  *
13033  * Restart the card from scratch, as if from a cold-boot.
13034  */
13035 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13036 {
13037         struct net_device *dev = pci_get_drvdata(pdev);
13038         struct bnx2x *bp = netdev_priv(dev);
13039         int i;
13040
13041         rtnl_lock();
13042         BNX2X_ERR("IO slot reset initializing...\n");
13043         if (pci_enable_device(pdev)) {
13044                 dev_err(&pdev->dev,
13045                         "Cannot re-enable PCI device after reset\n");
13046                 rtnl_unlock();
13047                 return PCI_ERS_RESULT_DISCONNECT;
13048         }
13049
13050         pci_set_master(pdev);
13051         pci_restore_state(pdev);
13052         pci_save_state(pdev);
13053
13054         if (netif_running(dev))
13055                 bnx2x_set_power_state(bp, PCI_D0);
13056
13057         if (netif_running(dev)) {
13058                 BNX2X_ERR("IO slot reset --> driver unload\n");
13059
13060                 /* MCP should have been reset; Need to wait for validity */
13061                 bnx2x_init_shmem(bp);
13062
13063                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13064                         u32 v;
13065
13066                         v = SHMEM2_RD(bp,
13067                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13068                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13069                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13070                 }
13071                 bnx2x_drain_tx_queues(bp);
13072                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13073                 bnx2x_netif_stop(bp, 1);
13074                 bnx2x_free_irq(bp);
13075
13076                 /* Report UNLOAD_DONE to MCP */
13077                 bnx2x_send_unload_done(bp, true);
13078
13079                 bp->sp_state = 0;
13080                 bp->port.pmf = 0;
13081
13082                 bnx2x_prev_unload(bp);
13083
13084                 /* We should have reseted the engine, so It's fair to
13085                  * assume the FW will no longer write to the bnx2x driver.
13086                  */
13087                 bnx2x_squeeze_objects(bp);
13088                 bnx2x_free_skbs(bp);
13089                 for_each_rx_queue(bp, i)
13090                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13091                 bnx2x_free_fp_mem(bp);
13092                 bnx2x_free_mem(bp);
13093
13094                 bp->state = BNX2X_STATE_CLOSED;
13095         }
13096
13097         rtnl_unlock();
13098
13099         return PCI_ERS_RESULT_RECOVERED;
13100 }
13101
13102 /**
13103  * bnx2x_io_resume - called when traffic can start flowing again
13104  * @pdev: Pointer to PCI device
13105  *
13106  * This callback is called when the error recovery driver tells us that
13107  * its OK to resume normal operation.
13108  */
13109 static void bnx2x_io_resume(struct pci_dev *pdev)
13110 {
13111         struct net_device *dev = pci_get_drvdata(pdev);
13112         struct bnx2x *bp = netdev_priv(dev);
13113
13114         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13115                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13116                 return;
13117         }
13118
13119         rtnl_lock();
13120
13121         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13122                                                         DRV_MSG_SEQ_NUMBER_MASK;
13123
13124         if (netif_running(dev))
13125                 bnx2x_nic_load(bp, LOAD_NORMAL);
13126
13127         netif_device_attach(dev);
13128
13129         rtnl_unlock();
13130 }
13131
13132 static const struct pci_error_handlers bnx2x_err_handler = {
13133         .error_detected = bnx2x_io_error_detected,
13134         .slot_reset     = bnx2x_io_slot_reset,
13135         .resume         = bnx2x_io_resume,
13136 };
13137
13138 static void bnx2x_shutdown(struct pci_dev *pdev)
13139 {
13140         struct net_device *dev = pci_get_drvdata(pdev);
13141         struct bnx2x *bp;
13142
13143         if (!dev)
13144                 return;
13145
13146         bp = netdev_priv(dev);
13147         if (!bp)
13148                 return;
13149
13150         rtnl_lock();
13151         netif_device_detach(dev);
13152         rtnl_unlock();
13153
13154         /* Don't remove the netdevice, as there are scenarios which will cause
13155          * the kernel to hang, e.g., when trying to remove bnx2i while the
13156          * rootfs is mounted from SAN.
13157          */
13158         __bnx2x_remove(pdev, dev, bp, false);
13159 }
13160
13161 static struct pci_driver bnx2x_pci_driver = {
13162         .name        = DRV_MODULE_NAME,
13163         .id_table    = bnx2x_pci_tbl,
13164         .probe       = bnx2x_init_one,
13165         .remove      = bnx2x_remove_one,
13166         .suspend     = bnx2x_suspend,
13167         .resume      = bnx2x_resume,
13168         .err_handler = &bnx2x_err_handler,
13169 #ifdef CONFIG_BNX2X_SRIOV
13170         .sriov_configure = bnx2x_sriov_configure,
13171 #endif
13172         .shutdown    = bnx2x_shutdown,
13173 };
13174
13175 static int __init bnx2x_init(void)
13176 {
13177         int ret;
13178
13179         pr_info("%s", version);
13180
13181         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13182         if (bnx2x_wq == NULL) {
13183                 pr_err("Cannot create workqueue\n");
13184                 return -ENOMEM;
13185         }
13186
13187         ret = pci_register_driver(&bnx2x_pci_driver);
13188         if (ret) {
13189                 pr_err("Cannot register driver\n");
13190                 destroy_workqueue(bnx2x_wq);
13191         }
13192         return ret;
13193 }
13194
13195 static void __exit bnx2x_cleanup(void)
13196 {
13197         struct list_head *pos, *q;
13198
13199         pci_unregister_driver(&bnx2x_pci_driver);
13200
13201         destroy_workqueue(bnx2x_wq);
13202
13203         /* Free globally allocated resources */
13204         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13205                 struct bnx2x_prev_path_list *tmp =
13206                         list_entry(pos, struct bnx2x_prev_path_list, list);
13207                 list_del(pos);
13208                 kfree(tmp);
13209         }
13210 }
13211
13212 void bnx2x_notify_link_changed(struct bnx2x *bp)
13213 {
13214         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13215 }
13216
13217 module_init(bnx2x_init);
13218 module_exit(bnx2x_cleanup);
13219
13220 /**
13221  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13222  *
13223  * @bp:         driver handle
13224  * @set:        set or clear the CAM entry
13225  *
13226  * This function will wait until the ramrod completion returns.
13227  * Return 0 if success, -ENODEV if ramrod doesn't return.
13228  */
13229 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13230 {
13231         unsigned long ramrod_flags = 0;
13232
13233         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13234         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13235                                  &bp->iscsi_l2_mac_obj, true,
13236                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13237 }
13238
13239 /* count denotes the number of new completions we have seen */
13240 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13241 {
13242         struct eth_spe *spe;
13243         int cxt_index, cxt_offset;
13244
13245 #ifdef BNX2X_STOP_ON_ERROR
13246         if (unlikely(bp->panic))
13247                 return;
13248 #endif
13249
13250         spin_lock_bh(&bp->spq_lock);
13251         BUG_ON(bp->cnic_spq_pending < count);
13252         bp->cnic_spq_pending -= count;
13253
13254         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13255                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13256                                 & SPE_HDR_CONN_TYPE) >>
13257                                 SPE_HDR_CONN_TYPE_SHIFT;
13258                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13259                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13260
13261                 /* Set validation for iSCSI L2 client before sending SETUP
13262                  *  ramrod
13263                  */
13264                 if (type == ETH_CONNECTION_TYPE) {
13265                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13266                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13267                                         ILT_PAGE_CIDS;
13268                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13269                                         (cxt_index * ILT_PAGE_CIDS);
13270                                 bnx2x_set_ctx_validation(bp,
13271                                         &bp->context[cxt_index].
13272                                                          vcxt[cxt_offset].eth,
13273                                         BNX2X_ISCSI_ETH_CID(bp));
13274                         }
13275                 }
13276
13277                 /*
13278                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13279                  * and in the air. We also check that number of outstanding
13280                  * COMMON ramrods is not more than the EQ and SPQ can
13281                  * accommodate.
13282                  */
13283                 if (type == ETH_CONNECTION_TYPE) {
13284                         if (!atomic_read(&bp->cq_spq_left))
13285                                 break;
13286                         else
13287                                 atomic_dec(&bp->cq_spq_left);
13288                 } else if (type == NONE_CONNECTION_TYPE) {
13289                         if (!atomic_read(&bp->eq_spq_left))
13290                                 break;
13291                         else
13292                                 atomic_dec(&bp->eq_spq_left);
13293                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13294                            (type == FCOE_CONNECTION_TYPE)) {
13295                         if (bp->cnic_spq_pending >=
13296                             bp->cnic_eth_dev.max_kwqe_pending)
13297                                 break;
13298                         else
13299                                 bp->cnic_spq_pending++;
13300                 } else {
13301                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13302                         bnx2x_panic();
13303                         break;
13304                 }
13305
13306                 spe = bnx2x_sp_get_next(bp);
13307                 *spe = *bp->cnic_kwq_cons;
13308
13309                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13310                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13311
13312                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13313                         bp->cnic_kwq_cons = bp->cnic_kwq;
13314                 else
13315                         bp->cnic_kwq_cons++;
13316         }
13317         bnx2x_sp_prod_update(bp);
13318         spin_unlock_bh(&bp->spq_lock);
13319 }
13320
13321 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13322                                struct kwqe_16 *kwqes[], u32 count)
13323 {
13324         struct bnx2x *bp = netdev_priv(dev);
13325         int i;
13326
13327 #ifdef BNX2X_STOP_ON_ERROR
13328         if (unlikely(bp->panic)) {
13329                 BNX2X_ERR("Can't post to SP queue while panic\n");
13330                 return -EIO;
13331         }
13332 #endif
13333
13334         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13335             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13336                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13337                 return -EAGAIN;
13338         }
13339
13340         spin_lock_bh(&bp->spq_lock);
13341
13342         for (i = 0; i < count; i++) {
13343                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13344
13345                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13346                         break;
13347
13348                 *bp->cnic_kwq_prod = *spe;
13349
13350                 bp->cnic_kwq_pending++;
13351
13352                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13353                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13354                    spe->data.update_data_addr.hi,
13355                    spe->data.update_data_addr.lo,
13356                    bp->cnic_kwq_pending);
13357
13358                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13359                         bp->cnic_kwq_prod = bp->cnic_kwq;
13360                 else
13361                         bp->cnic_kwq_prod++;
13362         }
13363
13364         spin_unlock_bh(&bp->spq_lock);
13365
13366         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13367                 bnx2x_cnic_sp_post(bp, 0);
13368
13369         return i;
13370 }
13371
13372 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13373 {
13374         struct cnic_ops *c_ops;
13375         int rc = 0;
13376
13377         mutex_lock(&bp->cnic_mutex);
13378         c_ops = rcu_dereference_protected(bp->cnic_ops,
13379                                           lockdep_is_held(&bp->cnic_mutex));
13380         if (c_ops)
13381                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13382         mutex_unlock(&bp->cnic_mutex);
13383
13384         return rc;
13385 }
13386
13387 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13388 {
13389         struct cnic_ops *c_ops;
13390         int rc = 0;
13391
13392         rcu_read_lock();
13393         c_ops = rcu_dereference(bp->cnic_ops);
13394         if (c_ops)
13395                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13396         rcu_read_unlock();
13397
13398         return rc;
13399 }
13400
13401 /*
13402  * for commands that have no data
13403  */
13404 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13405 {
13406         struct cnic_ctl_info ctl = {0};
13407
13408         ctl.cmd = cmd;
13409
13410         return bnx2x_cnic_ctl_send(bp, &ctl);
13411 }
13412
13413 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13414 {
13415         struct cnic_ctl_info ctl = {0};
13416
13417         /* first we tell CNIC and only then we count this as a completion */
13418         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13419         ctl.data.comp.cid = cid;
13420         ctl.data.comp.error = err;
13421
13422         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13423         bnx2x_cnic_sp_post(bp, 0);
13424 }
13425
13426 /* Called with netif_addr_lock_bh() taken.
13427  * Sets an rx_mode config for an iSCSI ETH client.
13428  * Doesn't block.
13429  * Completion should be checked outside.
13430  */
13431 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13432 {
13433         unsigned long accept_flags = 0, ramrod_flags = 0;
13434         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13435         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13436
13437         if (start) {
13438                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13439                  * because it's the only way for UIO Queue to accept
13440                  * multicasts (in non-promiscuous mode only one Queue per
13441                  * function will receive multicast packets (leading in our
13442                  * case).
13443                  */
13444                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13445                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13446                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13447                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13448
13449                 /* Clear STOP_PENDING bit if START is requested */
13450                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13451
13452                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13453         } else
13454                 /* Clear START_PENDING bit if STOP is requested */
13455                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13456
13457         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13458                 set_bit(sched_state, &bp->sp_state);
13459         else {
13460                 __set_bit(RAMROD_RX, &ramrod_flags);
13461                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13462                                     ramrod_flags);
13463         }
13464 }
13465
13466 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13467 {
13468         struct bnx2x *bp = netdev_priv(dev);
13469         int rc = 0;
13470
13471         switch (ctl->cmd) {
13472         case DRV_CTL_CTXTBL_WR_CMD: {
13473                 u32 index = ctl->data.io.offset;
13474                 dma_addr_t addr = ctl->data.io.dma_addr;
13475
13476                 bnx2x_ilt_wr(bp, index, addr);
13477                 break;
13478         }
13479
13480         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13481                 int count = ctl->data.credit.credit_count;
13482
13483                 bnx2x_cnic_sp_post(bp, count);
13484                 break;
13485         }
13486
13487         /* rtnl_lock is held.  */
13488         case DRV_CTL_START_L2_CMD: {
13489                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13490                 unsigned long sp_bits = 0;
13491
13492                 /* Configure the iSCSI classification object */
13493                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13494                                    cp->iscsi_l2_client_id,
13495                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13496                                    bnx2x_sp(bp, mac_rdata),
13497                                    bnx2x_sp_mapping(bp, mac_rdata),
13498                                    BNX2X_FILTER_MAC_PENDING,
13499                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13500                                    &bp->macs_pool);
13501
13502                 /* Set iSCSI MAC address */
13503                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13504                 if (rc)
13505                         break;
13506
13507                 mmiowb();
13508                 barrier();
13509
13510                 /* Start accepting on iSCSI L2 ring */
13511
13512                 netif_addr_lock_bh(dev);
13513                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13514                 netif_addr_unlock_bh(dev);
13515
13516                 /* bits to wait on */
13517                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13518                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13519
13520                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13521                         BNX2X_ERR("rx_mode completion timed out!\n");
13522
13523                 break;
13524         }
13525
13526         /* rtnl_lock is held.  */
13527         case DRV_CTL_STOP_L2_CMD: {
13528                 unsigned long sp_bits = 0;
13529
13530                 /* Stop accepting on iSCSI L2 ring */
13531                 netif_addr_lock_bh(dev);
13532                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13533                 netif_addr_unlock_bh(dev);
13534
13535                 /* bits to wait on */
13536                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13537                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13538
13539                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13540                         BNX2X_ERR("rx_mode completion timed out!\n");
13541
13542                 mmiowb();
13543                 barrier();
13544
13545                 /* Unset iSCSI L2 MAC */
13546                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13547                                         BNX2X_ISCSI_ETH_MAC, true);
13548                 break;
13549         }
13550         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13551                 int count = ctl->data.credit.credit_count;
13552
13553                 smp_mb__before_atomic_inc();
13554                 atomic_add(count, &bp->cq_spq_left);
13555                 smp_mb__after_atomic_inc();
13556                 break;
13557         }
13558         case DRV_CTL_ULP_REGISTER_CMD: {
13559                 int ulp_type = ctl->data.register_data.ulp_type;
13560
13561                 if (CHIP_IS_E3(bp)) {
13562                         int idx = BP_FW_MB_IDX(bp);
13563                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13564                         int path = BP_PATH(bp);
13565                         int port = BP_PORT(bp);
13566                         int i;
13567                         u32 scratch_offset;
13568                         u32 *host_addr;
13569
13570                         /* first write capability to shmem2 */
13571                         if (ulp_type == CNIC_ULP_ISCSI)
13572                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13573                         else if (ulp_type == CNIC_ULP_FCOE)
13574                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13575                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13576
13577                         if ((ulp_type != CNIC_ULP_FCOE) ||
13578                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13579                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13580                                 break;
13581
13582                         /* if reached here - should write fcoe capabilities */
13583                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13584                         if (!scratch_offset)
13585                                 break;
13586                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13587                                                    fcoe_features[path][port]);
13588                         host_addr = (u32 *) &(ctl->data.register_data.
13589                                               fcoe_features);
13590                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13591                              i += 4)
13592                                 REG_WR(bp, scratch_offset + i,
13593                                        *(host_addr + i/4));
13594                 }
13595                 break;
13596         }
13597
13598         case DRV_CTL_ULP_UNREGISTER_CMD: {
13599                 int ulp_type = ctl->data.ulp_type;
13600
13601                 if (CHIP_IS_E3(bp)) {
13602                         int idx = BP_FW_MB_IDX(bp);
13603                         u32 cap;
13604
13605                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13606                         if (ulp_type == CNIC_ULP_ISCSI)
13607                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13608                         else if (ulp_type == CNIC_ULP_FCOE)
13609                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13610                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13611                 }
13612                 break;
13613         }
13614
13615         default:
13616                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13617                 rc = -EINVAL;
13618         }
13619
13620         return rc;
13621 }
13622
13623 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13624 {
13625         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13626
13627         if (bp->flags & USING_MSIX_FLAG) {
13628                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13629                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13630                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13631         } else {
13632                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13633                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13634         }
13635         if (!CHIP_IS_E1x(bp))
13636                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13637         else
13638                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13639
13640         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13641         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13642         cp->irq_arr[1].status_blk = bp->def_status_blk;
13643         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13644         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13645
13646         cp->num_irq = 2;
13647 }
13648
13649 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13650 {
13651         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13652
13653         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13654                              bnx2x_cid_ilt_lines(bp);
13655         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13656         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13657         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13658
13659         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13660            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13661            cp->iscsi_l2_cid);
13662
13663         if (NO_ISCSI_OOO(bp))
13664                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13665 }
13666
13667 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13668                                void *data)
13669 {
13670         struct bnx2x *bp = netdev_priv(dev);
13671         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13672         int rc;
13673
13674         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13675
13676         if (ops == NULL) {
13677                 BNX2X_ERR("NULL ops received\n");
13678                 return -EINVAL;
13679         }
13680
13681         if (!CNIC_SUPPORT(bp)) {
13682                 BNX2X_ERR("Can't register CNIC when not supported\n");
13683                 return -EOPNOTSUPP;
13684         }
13685
13686         if (!CNIC_LOADED(bp)) {
13687                 rc = bnx2x_load_cnic(bp);
13688                 if (rc) {
13689                         BNX2X_ERR("CNIC-related load failed\n");
13690                         return rc;
13691                 }
13692         }
13693
13694         bp->cnic_enabled = true;
13695
13696         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13697         if (!bp->cnic_kwq)
13698                 return -ENOMEM;
13699
13700         bp->cnic_kwq_cons = bp->cnic_kwq;
13701         bp->cnic_kwq_prod = bp->cnic_kwq;
13702         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13703
13704         bp->cnic_spq_pending = 0;
13705         bp->cnic_kwq_pending = 0;
13706
13707         bp->cnic_data = data;
13708
13709         cp->num_irq = 0;
13710         cp->drv_state |= CNIC_DRV_STATE_REGD;
13711         cp->iro_arr = bp->iro_arr;
13712
13713         bnx2x_setup_cnic_irq_info(bp);
13714
13715         rcu_assign_pointer(bp->cnic_ops, ops);
13716
13717         return 0;
13718 }
13719
13720 static int bnx2x_unregister_cnic(struct net_device *dev)
13721 {
13722         struct bnx2x *bp = netdev_priv(dev);
13723         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13724
13725         mutex_lock(&bp->cnic_mutex);
13726         cp->drv_state = 0;
13727         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13728         mutex_unlock(&bp->cnic_mutex);
13729         synchronize_rcu();
13730         bp->cnic_enabled = false;
13731         kfree(bp->cnic_kwq);
13732         bp->cnic_kwq = NULL;
13733
13734         return 0;
13735 }
13736
13737 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13738 {
13739         struct bnx2x *bp = netdev_priv(dev);
13740         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13741
13742         /* If both iSCSI and FCoE are disabled - return NULL in
13743          * order to indicate CNIC that it should not try to work
13744          * with this device.
13745          */
13746         if (NO_ISCSI(bp) && NO_FCOE(bp))
13747                 return NULL;
13748
13749         cp->drv_owner = THIS_MODULE;
13750         cp->chip_id = CHIP_ID(bp);
13751         cp->pdev = bp->pdev;
13752         cp->io_base = bp->regview;
13753         cp->io_base2 = bp->doorbells;
13754         cp->max_kwqe_pending = 8;
13755         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13756         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13757                              bnx2x_cid_ilt_lines(bp);
13758         cp->ctx_tbl_len = CNIC_ILT_LINES;
13759         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13760         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13761         cp->drv_ctl = bnx2x_drv_ctl;
13762         cp->drv_register_cnic = bnx2x_register_cnic;
13763         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13764         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13765         cp->iscsi_l2_client_id =
13766                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13767         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13768
13769         if (NO_ISCSI_OOO(bp))
13770                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13771
13772         if (NO_ISCSI(bp))
13773                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13774
13775         if (NO_FCOE(bp))
13776                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13777
13778         BNX2X_DEV_INFO(
13779                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13780            cp->ctx_blk_size,
13781            cp->ctx_tbl_offset,
13782            cp->ctx_tbl_len,
13783            cp->starting_cid);
13784         return cp;
13785 }
13786
13787 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13788 {
13789         struct bnx2x *bp = fp->bp;
13790         u32 offset = BAR_USTRORM_INTMEM;
13791
13792         if (IS_VF(bp))
13793                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13794         else if (!CHIP_IS_E1x(bp))
13795                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13796         else
13797                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13798
13799         return offset;
13800 }
13801
13802 /* called only on E1H or E2.
13803  * When pretending to be PF, the pretend value is the function number 0...7
13804  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13805  * combination
13806  */
13807 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13808 {
13809         u32 pretend_reg;
13810
13811         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13812                 return -1;
13813
13814         /* get my own pretend register */
13815         pretend_reg = bnx2x_get_pretend_reg(bp);
13816         REG_WR(bp, pretend_reg, pretend_func_val);
13817         REG_RD(bp, pretend_reg);
13818         return 0;
13819 }