drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/rtc.h>
  37 #include <linux/bpf.h>
  38 #include <net/ip.h>
  39 #include <net/tcp.h>
  40 #include <net/udp.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <net/udp_tunnel.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/cache.h>
  47 #include <linux/log2.h>
  48 #include <linux/aer.h>
  49 #include <linux/bitmap.h>
  50 #include <linux/cpu_rmap.h>
  51
  52 #include "bnxt_hsi.h"
  53 #include "bnxt.h"
  54 #include "bnxt_ulp.h"
  55 #include "bnxt_sriov.h"
  56 #include "bnxt_ethtool.h"
  57 #include "bnxt_dcb.h"
  58 #include "bnxt_xdp.h"
  59
  60 #define BNXT_TX_TIMEOUT         (5 * HZ)
  61
  62 static const char version[] =
  63         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  64
  65 MODULE_LICENSE("GPL");
  66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  67 MODULE_VERSION(DRV_MODULE_VERSION);
  68
  69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  71 #define BNXT_RX_COPY_THRESH 256
  72
  73 #define BNXT_TX_PUSH_THRESH 164
  74
  75 enum board_idx {
  76         BCM57301,
  77         BCM57302,
  78         BCM57304,
  79         BCM57417_NPAR,
  80         BCM58700,
  81         BCM57311,
  82         BCM57312,
  83         BCM57402,
  84         BCM57404,
  85         BCM57406,
  86         BCM57402_NPAR,
  87         BCM57407,
  88         BCM57412,
  89         BCM57414,
  90         BCM57416,
  91         BCM57417,
  92         BCM57412_NPAR,
  93         BCM57314,
  94         BCM57417_SFP,
  95         BCM57416_SFP,
  96         BCM57404_NPAR,
  97         BCM57406_NPAR,
  98         BCM57407_SFP,
  99         BCM57407_NPAR,
 100         BCM57414_NPAR,
 101         BCM57416_NPAR,
 102         BCM57452,
 103         BCM57454,
 104         NETXTREME_E_VF,
 105         NETXTREME_C_VF,
 106 };
 107
 108 /* indexed by enum above */
 109 static const struct {
 110         char *name;
 111 } board_info[] = {
 112         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 113         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 114         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 115         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 116         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 117         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 118         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 119         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 120         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 121         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 122         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 123         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 124         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 125         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 126         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 127         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 128         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 130         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 131         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 132         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 134         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 135         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 136         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 137         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 138         { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 139         { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 140         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 141         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 142 };
 143
 144 static const struct pci_device_id bnxt_pci_tbl[] = {
 145         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 146         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 147         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 148         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 149         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 150         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 151         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 152         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 157         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 160         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 161         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 162         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 164         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 165         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 166         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 169         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 174         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177 #ifdef CONFIG_BNXT_SRIOV
 178         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 179         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 180         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 181         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 182         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 183         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 184 #endif
 185         { 0 }
 186 };
 187
 188 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 189
 190 static const u16 bnxt_vf_req_snif[] = {
 191         HWRM_FUNC_CFG,
 192         HWRM_PORT_PHY_QCFG,
 193         HWRM_CFA_L2_FILTER_ALLOC,
 194 };
 195
 196 static const u16 bnxt_async_events_arr[] = {
 197         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 198         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 199         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 200         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 201         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 202 };
 203
 204 static bool bnxt_vf_pciid(enum board_idx idx)
 205 {
 206         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 207 }
 208
 209 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 210 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 211 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 212
 213 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 214                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 215
 216 #define BNXT_CP_DB(db, raw_cons)                                        \
 217                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 218
 219 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 220                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 221
 222 const u16 bnxt_lhint_arr[] = {
 223         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 224         TX_BD_FLAGS_LHINT_512_TO_1023,
 225         TX_BD_FLAGS_LHINT_1024_TO_2047,
 226         TX_BD_FLAGS_LHINT_1024_TO_2047,
 227         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 228         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242 };
 243
 244 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 245 {
 246         struct bnxt *bp = netdev_priv(dev);
 247         struct tx_bd *txbd;
 248         struct tx_bd_ext *txbd1;
 249         struct netdev_queue *txq;
 250         int i;
 251         dma_addr_t mapping;
 252         unsigned int length, pad = 0;
 253         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 254         u16 prod, last_frag;
 255         struct pci_dev *pdev = bp->pdev;
 256         struct bnxt_tx_ring_info *txr;
 257         struct bnxt_sw_tx_bd *tx_buf;
 258
 259         i = skb_get_queue_mapping(skb);
 260         if (unlikely(i >= bp->tx_nr_rings)) {
 261                 dev_kfree_skb_any(skb);
 262                 return NETDEV_TX_OK;
 263         }
 264
 265         txq = netdev_get_tx_queue(dev, i);
 266         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 267         prod = txr->tx_prod;
 268
 269         free_size = bnxt_tx_avail(bp, txr);
 270         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 271                 netif_tx_stop_queue(txq);
 272                 return NETDEV_TX_BUSY;
 273         }
 274
 275         length = skb->len;
 276         len = skb_headlen(skb);
 277         last_frag = skb_shinfo(skb)->nr_frags;
 278
 279         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 280
 281         txbd->tx_bd_opaque = prod;
 282
 283         tx_buf = &txr->tx_buf_ring[prod];
 284         tx_buf->skb = skb;
 285         tx_buf->nr_frags = last_frag;
 286
 287         vlan_tag_flags = 0;
 288         cfa_action = 0;
 289         if (skb_vlan_tag_present(skb)) {
 290                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 291                                  skb_vlan_tag_get(skb);
 292                 /* Currently supports 8021Q, 8021AD vlan offloads
 293                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 294                  */
 295                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 296                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 297         }
 298
 299         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 300                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 301                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 302                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 303                 void *pdata = tx_push_buf->data;
 304                 u64 *end;
 305                 int j, push_len;
 306
 307                 /* Set COAL_NOW to be ready quickly for the next push */
 308                 tx_push->tx_bd_len_flags_type =
 309                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 310                                         TX_BD_TYPE_LONG_TX_BD |
 311                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 312                                         TX_BD_FLAGS_COAL_NOW |
 313                                         TX_BD_FLAGS_PACKET_END |
 314                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 315
 316                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 317                         tx_push1->tx_bd_hsize_lflags =
 318                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 319                 else
 320                         tx_push1->tx_bd_hsize_lflags = 0;
 321
 322                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 323                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 324
 325                 end = pdata + length;
 326                 end = PTR_ALIGN(end, 8) - 1;
 327                 *end = 0;
 328
 329                 skb_copy_from_linear_data(skb, pdata, len);
 330                 pdata += len;
 331                 for (j = 0; j < last_frag; j++) {
 332                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 333                         void *fptr;
 334
 335                         fptr = skb_frag_address_safe(frag);
 336                         if (!fptr)
 337                                 goto normal_tx;
 338
 339                         memcpy(pdata, fptr, skb_frag_size(frag));
 340                         pdata += skb_frag_size(frag);
 341                 }
 342
 343                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 344                 txbd->tx_bd_haddr = txr->data_mapping;
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347                 memcpy(txbd, tx_push1, sizeof(*txbd));
 348                 prod = NEXT_TX(prod);
 349                 tx_push->doorbell =
 350                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 351                 txr->tx_prod = prod;
 352
 353                 tx_buf->is_push = 1;
 354                 netdev_tx_sent_queue(txq, skb->len);
 355                 wmb();  /* Sync is_push and byte queue before pushing data */
 356
 357                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 358                 if (push_len > 16) {
 359                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 360                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 361                                          (push_len - 16) << 1);
 362                 } else {
 363                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 364                                          push_len);
 365                 }
 366
 367                 goto tx_done;
 368         }
 369
 370 normal_tx:
 371         if (length < BNXT_MIN_PKT_SIZE) {
 372                 pad = BNXT_MIN_PKT_SIZE - length;
 373                 if (skb_pad(skb, pad)) {
 374                         /* SKB already freed. */
 375                         tx_buf->skb = NULL;
 376                         return NETDEV_TX_OK;
 377                 }
 378                 length = BNXT_MIN_PKT_SIZE;
 379         }
 380
 381         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 382
 383         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 384                 dev_kfree_skb_any(skb);
 385                 tx_buf->skb = NULL;
 386                 return NETDEV_TX_OK;
 387         }
 388
 389         dma_unmap_addr_set(tx_buf, mapping, mapping);
 390         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 391                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 392
 393         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 394
 395         prod = NEXT_TX(prod);
 396         txbd1 = (struct tx_bd_ext *)
 397                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 398
 399         txbd1->tx_bd_hsize_lflags = 0;
 400         if (skb_is_gso(skb)) {
 401                 u32 hdr_len;
 402
 403                 if (skb->encapsulation)
 404                         hdr_len = skb_inner_network_offset(skb) +
 405                                 skb_inner_network_header_len(skb) +
 406                                 inner_tcp_hdrlen(skb);
 407                 else
 408                         hdr_len = skb_transport_offset(skb) +
 409                                 tcp_hdrlen(skb);
 410
 411                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 412                                         TX_BD_FLAGS_T_IPID |
 413                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 414                 length = skb_shinfo(skb)->gso_size;
 415                 txbd1->tx_bd_mss = cpu_to_le32(length);
 416                 length += hdr_len;
 417         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 418                 txbd1->tx_bd_hsize_lflags =
 419                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 420                 txbd1->tx_bd_mss = 0;
 421         }
 422
 423         length >>= 9;
 424         flags |= bnxt_lhint_arr[length];
 425         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 426
 427         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 428         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 429         for (i = 0; i < last_frag; i++) {
 430                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 431
 432                 prod = NEXT_TX(prod);
 433                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 434
 435                 len = skb_frag_size(frag);
 436                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 437                                            DMA_TO_DEVICE);
 438
 439                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 440                         goto tx_dma_error;
 441
 442                 tx_buf = &txr->tx_buf_ring[prod];
 443                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 444
 445                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 446
 447                 flags = len << TX_BD_LEN_SHIFT;
 448                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 449         }
 450
 451         flags &= ~TX_BD_LEN;
 452         txbd->tx_bd_len_flags_type =
 453                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 454                             TX_BD_FLAGS_PACKET_END);
 455
 456         netdev_tx_sent_queue(txq, skb->len);
 457
 458         /* Sync BD data before updating doorbell */
 459         wmb();
 460
 461         prod = NEXT_TX(prod);
 462         txr->tx_prod = prod;
 463
 464         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 465         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 466
 467 tx_done:
 468
 469         mmiowb();
 470
 471         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 472                 netif_tx_stop_queue(txq);
 473
 474                 /* netif_tx_stop_queue() must be done before checking
 475                  * tx index in bnxt_tx_avail() below, because in
 476                  * bnxt_tx_int(), we update tx index before checking for
 477                  * netif_tx_queue_stopped().
 478                  */
 479                 smp_mb();
 480                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 481                         netif_tx_wake_queue(txq);
 482         }
 483         return NETDEV_TX_OK;
 484
 485 tx_dma_error:
 486         last_frag = i;
 487
 488         /* start back at beginning and unmap skb */
 489         prod = txr->tx_prod;
 490         tx_buf = &txr->tx_buf_ring[prod];
 491         tx_buf->skb = NULL;
 492         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 493                          skb_headlen(skb), PCI_DMA_TODEVICE);
 494         prod = NEXT_TX(prod);
 495
 496         /* unmap remaining mapped pages */
 497         for (i = 0; i < last_frag; i++) {
 498                 prod = NEXT_TX(prod);
 499                 tx_buf = &txr->tx_buf_ring[prod];
 500                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 501                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 502                                PCI_DMA_TODEVICE);
 503         }
 504
 505         dev_kfree_skb_any(skb);
 506         return NETDEV_TX_OK;
 507 }
 508
 509 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 510 {
 511         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 512         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 513         u16 cons = txr->tx_cons;
 514         struct pci_dev *pdev = bp->pdev;
 515         int i;
 516         unsigned int tx_bytes = 0;
 517
 518         for (i = 0; i < nr_pkts; i++) {
 519                 struct bnxt_sw_tx_bd *tx_buf;
 520                 struct sk_buff *skb;
 521                 int j, last;
 522
 523                 tx_buf = &txr->tx_buf_ring[cons];
 524                 cons = NEXT_TX(cons);
 525                 skb = tx_buf->skb;
 526                 tx_buf->skb = NULL;
 527
 528                 if (tx_buf->is_push) {
 529                         tx_buf->is_push = 0;
 530                         goto next_tx_int;
 531                 }
 532
 533                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 534                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 535                 last = tx_buf->nr_frags;
 536
 537                 for (j = 0; j < last; j++) {
 538                         cons = NEXT_TX(cons);
 539                         tx_buf = &txr->tx_buf_ring[cons];
 540                         dma_unmap_page(
 541                                 &pdev->dev,
 542                                 dma_unmap_addr(tx_buf, mapping),
 543                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 544                                 PCI_DMA_TODEVICE);
 545                 }
 546
 547 next_tx_int:
 548                 cons = NEXT_TX(cons);
 549
 550                 tx_bytes += skb->len;
 551                 dev_kfree_skb_any(skb);
 552         }
 553
 554         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 555         txr->tx_cons = cons;
 556
 557         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 558          * before checking for netif_tx_queue_stopped().  Without the
 559          * memory barrier, there is a small possibility that bnxt_start_xmit()
 560          * will miss it and cause the queue to be stopped forever.
 561          */
 562         smp_mb();
 563
 564         if (unlikely(netif_tx_queue_stopped(txq)) &&
 565             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 566                 __netif_tx_lock(txq, smp_processor_id());
 567                 if (netif_tx_queue_stopped(txq) &&
 568                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 569                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 570                         netif_tx_wake_queue(txq);
 571                 __netif_tx_unlock(txq);
 572         }
 573 }
 574
 575 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 576                                          gfp_t gfp)
 577 {
 578         struct device *dev = &bp->pdev->dev;
 579         struct page *page;
 580
 581         page = alloc_page(gfp);
 582         if (!page)
 583                 return NULL;
 584
 585         *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir);
 586         if (dma_mapping_error(dev, *mapping)) {
 587                 __free_page(page);
 588                 return NULL;
 589         }
 590         *mapping += bp->rx_dma_offset;
 591         return page;
 592 }
 593
 594 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 595                                        gfp_t gfp)
 596 {
 597         u8 *data;
 598         struct pci_dev *pdev = bp->pdev;
 599
 600         data = kmalloc(bp->rx_buf_size, gfp);
 601         if (!data)
 602                 return NULL;
 603
 604         *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset,
 605                                   bp->rx_buf_use_size, bp->rx_dir);
 606
 607         if (dma_mapping_error(&pdev->dev, *mapping)) {
 608                 kfree(data);
 609                 data = NULL;
 610         }
 611         return data;
 612 }
 613
 614 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 615                        u16 prod, gfp_t gfp)
 616 {
 617         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 618         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 619         dma_addr_t mapping;
 620
 621         if (BNXT_RX_PAGE_MODE(bp)) {
 622                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 623
 624                 if (!page)
 625                         return -ENOMEM;
 626
 627                 rx_buf->data = page;
 628                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 629         } else {
 630                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 631
 632                 if (!data)
 633                         return -ENOMEM;
 634
 635                 rx_buf->data = data;
 636                 rx_buf->data_ptr = data + bp->rx_offset;
 637         }
 638         rx_buf->mapping = mapping;
 639
 640         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 641         return 0;
 642 }
 643
 644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 645 {
 646         u16 prod = rxr->rx_prod;
 647         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 648         struct rx_bd *cons_bd, *prod_bd;
 649
 650         prod_rx_buf = &rxr->rx_buf_ring[prod];
 651         cons_rx_buf = &rxr->rx_buf_ring[cons];
 652
 653         prod_rx_buf->data = data;
 654         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 655
 656         prod_rx_buf->mapping = cons_rx_buf->mapping;
 657
 658         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 659         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 660
 661         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 662 }
 663
 664 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 665 {
 666         u16 next, max = rxr->rx_agg_bmap_size;
 667
 668         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 669         if (next >= max)
 670                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 671         return next;
 672 }
 673
 674 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 675                                      struct bnxt_rx_ring_info *rxr,
 676                                      u16 prod, gfp_t gfp)
 677 {
 678         struct rx_bd *rxbd =
 679                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 680         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 681         struct pci_dev *pdev = bp->pdev;
 682         struct page *page;
 683         dma_addr_t mapping;
 684         u16 sw_prod = rxr->rx_sw_agg_prod;
 685         unsigned int offset = 0;
 686
 687         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 688                 page = rxr->rx_page;
 689                 if (!page) {
 690                         page = alloc_page(gfp);
 691                         if (!page)
 692                                 return -ENOMEM;
 693                         rxr->rx_page = page;
 694                         rxr->rx_page_offset = 0;
 695                 }
 696                 offset = rxr->rx_page_offset;
 697                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 698                 if (rxr->rx_page_offset == PAGE_SIZE)
 699                         rxr->rx_page = NULL;
 700                 else
 701                         get_page(page);
 702         } else {
 703                 page = alloc_page(gfp);
 704                 if (!page)
 705                         return -ENOMEM;
 706         }
 707
 708         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 709                                PCI_DMA_FROMDEVICE);
 710         if (dma_mapping_error(&pdev->dev, mapping)) {
 711                 __free_page(page);
 712                 return -EIO;
 713         }
 714
 715         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 716                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 717
 718         __set_bit(sw_prod, rxr->rx_agg_bmap);
 719         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 720         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 721
 722         rx_agg_buf->page = page;
 723         rx_agg_buf->offset = offset;
 724         rx_agg_buf->mapping = mapping;
 725         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 726         rxbd->rx_bd_opaque = sw_prod;
 727         return 0;
 728 }
 729
 730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 731                                    u32 agg_bufs)
 732 {
 733         struct bnxt *bp = bnapi->bp;
 734         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 735         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 736         u16 prod = rxr->rx_agg_prod;
 737         u16 sw_prod = rxr->rx_sw_agg_prod;
 738         u32 i;
 739
 740         for (i = 0; i < agg_bufs; i++) {
 741                 u16 cons;
 742                 struct rx_agg_cmp *agg;
 743                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 744                 struct rx_bd *prod_bd;
 745                 struct page *page;
 746
 747                 agg = (struct rx_agg_cmp *)
 748                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 749                 cons = agg->rx_agg_cmp_opaque;
 750                 __clear_bit(cons, rxr->rx_agg_bmap);
 751
 752                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 753                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 754
 755                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 756                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 757                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 758
 759                 /* It is possible for sw_prod to be equal to cons, so
 760                  * set cons_rx_buf->page to NULL first.
 761                  */
 762                 page = cons_rx_buf->page;
 763                 cons_rx_buf->page = NULL;
 764                 prod_rx_buf->page = page;
 765                 prod_rx_buf->offset = cons_rx_buf->offset;
 766
 767                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 768
 769                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 770
 771                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 772                 prod_bd->rx_bd_opaque = sw_prod;
 773
 774                 prod = NEXT_RX_AGG(prod);
 775                 sw_prod = NEXT_RX_AGG(sw_prod);
 776                 cp_cons = NEXT_CMP(cp_cons);
 777         }
 778         rxr->rx_agg_prod = prod;
 779         rxr->rx_sw_agg_prod = sw_prod;
 780 }
 781
 782 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 783                                         struct bnxt_rx_ring_info *rxr,
 784                                         u16 cons, void *data, u8 *data_ptr,
 785                                         dma_addr_t dma_addr,
 786                                         unsigned int offset_and_len)
 787 {
 788         unsigned int payload = offset_and_len >> 16;
 789         unsigned int len = offset_and_len & 0xffff;
 790         struct skb_frag_struct *frag;
 791         struct page *page = data;
 792         u16 prod = rxr->rx_prod;
 793         struct sk_buff *skb;
 794         int off, err;
 795
 796         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 797         if (unlikely(err)) {
 798                 bnxt_reuse_rx_data(rxr, cons, data);
 799                 return NULL;
 800         }
 801         dma_addr -= bp->rx_dma_offset;
 802         dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir);
 803
 804         if (unlikely(!payload))
 805                 payload = eth_get_headlen(data_ptr, len);
 806
 807         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 808         if (!skb) {
 809                 __free_page(page);
 810                 return NULL;
 811         }
 812
 813         off = (void *)data_ptr - page_address(page);
 814         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 815         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 816                payload + NET_IP_ALIGN);
 817
 818         frag = &skb_shinfo(skb)->frags[0];
 819         skb_frag_size_sub(frag, payload);
 820         frag->page_offset += payload;
 821         skb->data_len -= payload;
 822         skb->tail += payload;
 823
 824         return skb;
 825 }
 826
 827 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 828                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 829                                    void *data, u8 *data_ptr,
 830                                    dma_addr_t dma_addr,
 831                                    unsigned int offset_and_len)
 832 {
 833         u16 prod = rxr->rx_prod;
 834         struct sk_buff *skb;
 835         int err;
 836
 837         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 838         if (unlikely(err)) {
 839                 bnxt_reuse_rx_data(rxr, cons, data);
 840                 return NULL;
 841         }
 842
 843         skb = build_skb(data, 0);
 844         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 845                          bp->rx_dir);
 846         if (!skb) {
 847                 kfree(data);
 848                 return NULL;
 849         }
 850
 851         skb_reserve(skb, bp->rx_offset);
 852         skb_put(skb, offset_and_len & 0xffff);
 853         return skb;
 854 }
 855
 856 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 857                                      struct sk_buff *skb, u16 cp_cons,
 858                                      u32 agg_bufs)
 859 {
 860         struct pci_dev *pdev = bp->pdev;
 861         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 862         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 863         u16 prod = rxr->rx_agg_prod;
 864         u32 i;
 865
 866         for (i = 0; i < agg_bufs; i++) {
 867                 u16 cons, frag_len;
 868                 struct rx_agg_cmp *agg;
 869                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 870                 struct page *page;
 871                 dma_addr_t mapping;
 872
 873                 agg = (struct rx_agg_cmp *)
 874                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 875                 cons = agg->rx_agg_cmp_opaque;
 876                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 877                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 878
 879                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 880                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 881                                    cons_rx_buf->offset, frag_len);
 882                 __clear_bit(cons, rxr->rx_agg_bmap);
 883
 884                 /* It is possible for bnxt_alloc_rx_page() to allocate
 885                  * a sw_prod index that equals the cons index, so we
 886                  * need to clear the cons entry now.
 887                  */
 888                 mapping = cons_rx_buf->mapping;
 889                 page = cons_rx_buf->page;
 890                 cons_rx_buf->page = NULL;
 891
 892                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 893                         struct skb_shared_info *shinfo;
 894                         unsigned int nr_frags;
 895
 896                         shinfo = skb_shinfo(skb);
 897                         nr_frags = --shinfo->nr_frags;
 898                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 899
 900                         dev_kfree_skb(skb);
 901
 902                         cons_rx_buf->page = page;
 903
 904                         /* Update prod since possibly some pages have been
 905                          * allocated already.
 906                          */
 907                         rxr->rx_agg_prod = prod;
 908                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 909                         return NULL;
 910                 }
 911
 912                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 913                                PCI_DMA_FROMDEVICE);
 914
 915                 skb->data_len += frag_len;
 916                 skb->len += frag_len;
 917                 skb->truesize += PAGE_SIZE;
 918
 919                 prod = NEXT_RX_AGG(prod);
 920                 cp_cons = NEXT_CMP(cp_cons);
 921         }
 922         rxr->rx_agg_prod = prod;
 923         return skb;
 924 }
 925
 926 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 927                                u8 agg_bufs, u32 *raw_cons)
 928 {
 929         u16 last;
 930         struct rx_agg_cmp *agg;
 931
 932         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 933         last = RING_CMP(*raw_cons);
 934         agg = (struct rx_agg_cmp *)
 935                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 936         return RX_AGG_CMP_VALID(agg, *raw_cons);
 937 }
 938
 939 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 940                                             unsigned int len,
 941                                             dma_addr_t mapping)
 942 {
 943         struct bnxt *bp = bnapi->bp;
 944         struct pci_dev *pdev = bp->pdev;
 945         struct sk_buff *skb;
 946
 947         skb = napi_alloc_skb(&bnapi->napi, len);
 948         if (!skb)
 949                 return NULL;
 950
 951         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 952                                 bp->rx_dir);
 953
 954         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
 955                len + NET_IP_ALIGN);
 956
 957         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
 958                                    bp->rx_dir);
 959
 960         skb_put(skb, len);
 961         return skb;
 962 }
 963
 964 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 965                            u32 *raw_cons, void *cmp)
 966 {
 967         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 968         struct rx_cmp *rxcmp = cmp;
 969         u32 tmp_raw_cons = *raw_cons;
 970         u8 cmp_type, agg_bufs = 0;
 971
 972         cmp_type = RX_CMP_TYPE(rxcmp);
 973
 974         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 975                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 976                             RX_CMP_AGG_BUFS) >>
 977                            RX_CMP_AGG_BUFS_SHIFT;
 978         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 979                 struct rx_tpa_end_cmp *tpa_end = cmp;
 980
 981                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 982                             RX_TPA_END_CMP_AGG_BUFS) >>
 983                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 984         }
 985
 986         if (agg_bufs) {
 987                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 988                         return -EBUSY;
 989         }
 990         *raw_cons = tmp_raw_cons;
 991         return 0;
 992 }
 993
 994 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 995 {
 996         if (!rxr->bnapi->in_reset) {
 997                 rxr->bnapi->in_reset = true;
 998                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 999                 schedule_work(&bp->sp_task);
1000         }
1001         rxr->rx_next_cons = 0xffff;
1002 }
1003
1004 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1005                            struct rx_tpa_start_cmp *tpa_start,
1006                            struct rx_tpa_start_cmp_ext *tpa_start1)
1007 {
1008         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1009         u16 cons, prod;
1010         struct bnxt_tpa_info *tpa_info;
1011         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1012         struct rx_bd *prod_bd;
1013         dma_addr_t mapping;
1014
1015         cons = tpa_start->rx_tpa_start_cmp_opaque;
1016         prod = rxr->rx_prod;
1017         cons_rx_buf = &rxr->rx_buf_ring[cons];
1018         prod_rx_buf = &rxr->rx_buf_ring[prod];
1019         tpa_info = &rxr->rx_tpa[agg_id];
1020
1021         if (unlikely(cons != rxr->rx_next_cons)) {
1022                 bnxt_sched_reset(bp, rxr);
1023                 return;
1024         }
1025
1026         prod_rx_buf->data = tpa_info->data;
1027         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1028
1029         mapping = tpa_info->mapping;
1030         prod_rx_buf->mapping = mapping;
1031
1032         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1033
1034         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1035
1036         tpa_info->data = cons_rx_buf->data;
1037         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1038         cons_rx_buf->data = NULL;
1039         tpa_info->mapping = cons_rx_buf->mapping;
1040
1041         tpa_info->len =
1042                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1043                                 RX_TPA_START_CMP_LEN_SHIFT;
1044         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1045                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1046
1047                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1048                 tpa_info->gso_type = SKB_GSO_TCPV4;
1049                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1050                 if (hash_type == 3)
1051                         tpa_info->gso_type = SKB_GSO_TCPV6;
1052                 tpa_info->rss_hash =
1053                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1054         } else {
1055                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1056                 tpa_info->gso_type = 0;
1057                 if (netif_msg_rx_err(bp))
1058                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1059         }
1060         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1061         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1062         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1063
1064         rxr->rx_prod = NEXT_RX(prod);
1065         cons = NEXT_RX(cons);
1066         rxr->rx_next_cons = NEXT_RX(cons);
1067         cons_rx_buf = &rxr->rx_buf_ring[cons];
1068
1069         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1070         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1071         cons_rx_buf->data = NULL;
1072 }
1073
1074 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1075                            u16 cp_cons, u32 agg_bufs)
1076 {
1077         if (agg_bufs)
1078                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1079 }
1080
1081 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1082                                            int payload_off, int tcp_ts,
1083                                            struct sk_buff *skb)
1084 {
1085 #ifdef CONFIG_INET
1086         struct tcphdr *th;
1087         int len, nw_off;
1088         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1089         u32 hdr_info = tpa_info->hdr_info;
1090         bool loopback = false;
1091
1092         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1093         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1094         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1095
1096         /* If the packet is an internal loopback packet, the offsets will
1097          * have an extra 4 bytes.
1098          */
1099         if (inner_mac_off == 4) {
1100                 loopback = true;
1101         } else if (inner_mac_off > 4) {
1102                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1103                                             ETH_HLEN - 2));
1104
1105                 /* We only support inner iPv4/ipv6.  If we don't see the
1106                  * correct protocol ID, it must be a loopback packet where
1107                  * the offsets are off by 4.
1108                  */
1109                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1110                         loopback = true;
1111         }
1112         if (loopback) {
1113                 /* internal loopback packet, subtract all offsets by 4 */
1114                 inner_ip_off -= 4;
1115                 inner_mac_off -= 4;
1116                 outer_ip_off -= 4;
1117         }
1118
1119         nw_off = inner_ip_off - ETH_HLEN;
1120         skb_set_network_header(skb, nw_off);
1121         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1122                 struct ipv6hdr *iph = ipv6_hdr(skb);
1123
1124                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1125                 len = skb->len - skb_transport_offset(skb);
1126                 th = tcp_hdr(skb);
1127                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1128         } else {
1129                 struct iphdr *iph = ip_hdr(skb);
1130
1131                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1132                 len = skb->len - skb_transport_offset(skb);
1133                 th = tcp_hdr(skb);
1134                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1135         }
1136
1137         if (inner_mac_off) { /* tunnel */
1138                 struct udphdr *uh = NULL;
1139                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1140                                             ETH_HLEN - 2));
1141
1142                 if (proto == htons(ETH_P_IP)) {
1143                         struct iphdr *iph = (struct iphdr *)skb->data;
1144
1145                         if (iph->protocol == IPPROTO_UDP)
1146                                 uh = (struct udphdr *)(iph + 1);
1147                 } else {
1148                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1149
1150                         if (iph->nexthdr == IPPROTO_UDP)
1151                                 uh = (struct udphdr *)(iph + 1);
1152                 }
1153                 if (uh) {
1154                         if (uh->check)
1155                                 skb_shinfo(skb)->gso_type |=
1156                                         SKB_GSO_UDP_TUNNEL_CSUM;
1157                         else
1158                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1159                 }
1160         }
1161 #endif
1162         return skb;
1163 }
1164
1165 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1166 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1167
1168 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1169                                            int payload_off, int tcp_ts,
1170                                            struct sk_buff *skb)
1171 {
1172 #ifdef CONFIG_INET
1173         struct tcphdr *th;
1174         int len, nw_off, tcp_opt_len = 0;
1175
1176         if (tcp_ts)
1177                 tcp_opt_len = 12;
1178
1179         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1180                 struct iphdr *iph;
1181
1182                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1183                          ETH_HLEN;
1184                 skb_set_network_header(skb, nw_off);
1185                 iph = ip_hdr(skb);
1186                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1187                 len = skb->len - skb_transport_offset(skb);
1188                 th = tcp_hdr(skb);
1189                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1190         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1191                 struct ipv6hdr *iph;
1192
1193                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1194                          ETH_HLEN;
1195                 skb_set_network_header(skb, nw_off);
1196                 iph = ipv6_hdr(skb);
1197                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1198                 len = skb->len - skb_transport_offset(skb);
1199                 th = tcp_hdr(skb);
1200                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1201         } else {
1202                 dev_kfree_skb_any(skb);
1203                 return NULL;
1204         }
1205
1206         if (nw_off) { /* tunnel */
1207                 struct udphdr *uh = NULL;
1208
1209                 if (skb->protocol == htons(ETH_P_IP)) {
1210                         struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212                         if (iph->protocol == IPPROTO_UDP)
1213                                 uh = (struct udphdr *)(iph + 1);
1214                 } else {
1215                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217                         if (iph->nexthdr == IPPROTO_UDP)
1218                                 uh = (struct udphdr *)(iph + 1);
1219                 }
1220                 if (uh) {
1221                         if (uh->check)
1222                                 skb_shinfo(skb)->gso_type |=
1223                                         SKB_GSO_UDP_TUNNEL_CSUM;
1224                         else
1225                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226                 }
1227         }
1228 #endif
1229         return skb;
1230 }
1231
1232 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1233                                            struct bnxt_tpa_info *tpa_info,
1234                                            struct rx_tpa_end_cmp *tpa_end,
1235                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1236                                            struct sk_buff *skb)
1237 {
1238 #ifdef CONFIG_INET
1239         int payload_off;
1240         u16 segs;
1241
1242         segs = TPA_END_TPA_SEGS(tpa_end);
1243         if (segs == 1)
1244                 return skb;
1245
1246         NAPI_GRO_CB(skb)->count = segs;
1247         skb_shinfo(skb)->gso_size =
1248                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1249         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1250         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1251                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1252                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1253         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1254         if (likely(skb))
1255                 tcp_gro_complete(skb);
1256 #endif
1257         return skb;
1258 }
1259
1260 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1261                                            struct bnxt_napi *bnapi,
1262                                            u32 *raw_cons,
1263                                            struct rx_tpa_end_cmp *tpa_end,
1264                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1265                                            u8 *event)
1266 {
1267         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1268         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1269         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1270         u8 *data_ptr, agg_bufs;
1271         u16 cp_cons = RING_CMP(*raw_cons);
1272         unsigned int len;
1273         struct bnxt_tpa_info *tpa_info;
1274         dma_addr_t mapping;
1275         struct sk_buff *skb;
1276         void *data;
1277
1278         if (unlikely(bnapi->in_reset)) {
1279                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1280
1281                 if (rc < 0)
1282                         return ERR_PTR(-EBUSY);
1283                 return NULL;
1284         }
1285
1286         tpa_info = &rxr->rx_tpa[agg_id];
1287         data = tpa_info->data;
1288         data_ptr = tpa_info->data_ptr;
1289         prefetch(data_ptr);
1290         len = tpa_info->len;
1291         mapping = tpa_info->mapping;
1292
1293         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1294                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1295
1296         if (agg_bufs) {
1297                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1298                         return ERR_PTR(-EBUSY);
1299
1300                 *event |= BNXT_AGG_EVENT;
1301                 cp_cons = NEXT_CMP(cp_cons);
1302         }
1303
1304         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1305                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1306                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1307                             agg_bufs, (int)MAX_SKB_FRAGS);
1308                 return NULL;
1309         }
1310
1311         if (len <= bp->rx_copy_thresh) {
1312                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1313                 if (!skb) {
1314                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1315                         return NULL;
1316                 }
1317         } else {
1318                 u8 *new_data;
1319                 dma_addr_t new_mapping;
1320
1321                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1322                 if (!new_data) {
1323                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1324                         return NULL;
1325                 }
1326
1327                 tpa_info->data = new_data;
1328                 tpa_info->data_ptr = new_data + bp->rx_offset;
1329                 tpa_info->mapping = new_mapping;
1330
1331                 skb = build_skb(data, 0);
1332                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1333                                  bp->rx_dir);
1334
1335                 if (!skb) {
1336                         kfree(data);
1337                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1338                         return NULL;
1339                 }
1340                 skb_reserve(skb, bp->rx_offset);
1341                 skb_put(skb, len);
1342         }
1343
1344         if (agg_bufs) {
1345                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1346                 if (!skb) {
1347                         /* Page reuse already handled by bnxt_rx_pages(). */
1348                         return NULL;
1349                 }
1350         }
1351         skb->protocol = eth_type_trans(skb, bp->dev);
1352
1353         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1354                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1355
1356         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1357             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1358                 u16 vlan_proto = tpa_info->metadata >>
1359                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1360                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1361
1362                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1363         }
1364
1365         skb_checksum_none_assert(skb);
1366         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1367                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1368                 skb->csum_level =
1369                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1370         }
1371
1372         if (TPA_END_GRO(tpa_end))
1373                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1374
1375         return skb;
1376 }
1377
1378 /* returns the following:
1379  * 1       - 1 packet successfully received
1380  * 0       - successful TPA_START, packet not completed yet
1381  * -EBUSY  - completion ring does not have all the agg buffers yet
1382  * -ENOMEM - packet aborted due to out of memory
1383  * -EIO    - packet aborted due to hw error indicated in BD
1384  */
1385 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1386                        u8 *event)
1387 {
1388         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1389         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1390         struct net_device *dev = bp->dev;
1391         struct rx_cmp *rxcmp;
1392         struct rx_cmp_ext *rxcmp1;
1393         u32 tmp_raw_cons = *raw_cons;
1394         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1395         struct bnxt_sw_rx_bd *rx_buf;
1396         unsigned int len;
1397         u8 *data_ptr, agg_bufs, cmp_type;
1398         dma_addr_t dma_addr;
1399         struct sk_buff *skb;
1400         void *data;
1401         int rc = 0;
1402         u32 misc;
1403
1404         rxcmp = (struct rx_cmp *)
1405                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1406
1407         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1408         cp_cons = RING_CMP(tmp_raw_cons);
1409         rxcmp1 = (struct rx_cmp_ext *)
1410                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1411
1412         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1413                 return -EBUSY;
1414
1415         cmp_type = RX_CMP_TYPE(rxcmp);
1416
1417         prod = rxr->rx_prod;
1418
1419         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1420                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1421                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1422
1423                 *event |= BNXT_RX_EVENT;
1424                 goto next_rx_no_prod;
1425
1426         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1427                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1428                                    (struct rx_tpa_end_cmp *)rxcmp,
1429                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1430
1431                 if (unlikely(IS_ERR(skb)))
1432                         return -EBUSY;
1433
1434                 rc = -ENOMEM;
1435                 if (likely(skb)) {
1436                         skb_record_rx_queue(skb, bnapi->index);
1437                         napi_gro_receive(&bnapi->napi, skb);
1438                         rc = 1;
1439                 }
1440                 *event |= BNXT_RX_EVENT;
1441                 goto next_rx_no_prod;
1442         }
1443
1444         cons = rxcmp->rx_cmp_opaque;
1445         rx_buf = &rxr->rx_buf_ring[cons];
1446         data = rx_buf->data;
1447         data_ptr = rx_buf->data_ptr;
1448         if (unlikely(cons != rxr->rx_next_cons)) {
1449                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1450
1451                 bnxt_sched_reset(bp, rxr);
1452                 return rc1;
1453         }
1454         prefetch(data_ptr);
1455
1456         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1457         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1458
1459         if (agg_bufs) {
1460                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1461                         return -EBUSY;
1462
1463                 cp_cons = NEXT_CMP(cp_cons);
1464                 *event |= BNXT_AGG_EVENT;
1465         }
1466         *event |= BNXT_RX_EVENT;
1467
1468         rx_buf->data = NULL;
1469         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1470                 bnxt_reuse_rx_data(rxr, cons, data);
1471                 if (agg_bufs)
1472                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1473
1474                 rc = -EIO;
1475                 goto next_rx;
1476         }
1477
1478         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1479         dma_addr = rx_buf->mapping;
1480
1481         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1482                 rc = 1;
1483                 goto next_rx;
1484         }
1485
1486         if (len <= bp->rx_copy_thresh) {
1487                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1488                 bnxt_reuse_rx_data(rxr, cons, data);
1489                 if (!skb) {
1490                         rc = -ENOMEM;
1491                         goto next_rx;
1492                 }
1493         } else {
1494                 u32 payload;
1495
1496                 if (rx_buf->data_ptr == data_ptr)
1497                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1498                 else
1499                         payload = 0;
1500                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1501                                       payload | len);
1502                 if (!skb) {
1503                         rc = -ENOMEM;
1504                         goto next_rx;
1505                 }
1506         }
1507
1508         if (agg_bufs) {
1509                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1510                 if (!skb) {
1511                         rc = -ENOMEM;
1512                         goto next_rx;
1513                 }
1514         }
1515
1516         if (RX_CMP_HASH_VALID(rxcmp)) {
1517                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1518                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1519
1520                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1521                 if (hash_type != 1 && hash_type != 3)
1522                         type = PKT_HASH_TYPE_L3;
1523                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1524         }
1525
1526         skb->protocol = eth_type_trans(skb, dev);
1527
1528         if ((rxcmp1->rx_cmp_flags2 &
1529              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1530             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1531                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1532                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1533                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1534
1535                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1536         }
1537
1538         skb_checksum_none_assert(skb);
1539         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1540                 if (dev->features & NETIF_F_RXCSUM) {
1541                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1542                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1543                 }
1544         } else {
1545                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1546                         if (dev->features & NETIF_F_RXCSUM)
1547                                 cpr->rx_l4_csum_errors++;
1548                 }
1549         }
1550
1551         skb_record_rx_queue(skb, bnapi->index);
1552         napi_gro_receive(&bnapi->napi, skb);
1553         rc = 1;
1554
1555 next_rx:
1556         rxr->rx_prod = NEXT_RX(prod);
1557         rxr->rx_next_cons = NEXT_RX(cons);
1558
1559 next_rx_no_prod:
1560         *raw_cons = tmp_raw_cons;
1561
1562         return rc;
1563 }
1564
1565 #define BNXT_GET_EVENT_PORT(data)       \
1566         ((data) &                       \
1567          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1568
1569 static int bnxt_async_event_process(struct bnxt *bp,
1570                                     struct hwrm_async_event_cmpl *cmpl)
1571 {
1572         u16 event_id = le16_to_cpu(cmpl->event_id);
1573
1574         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1575         switch (event_id) {
1576         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1577                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1578                 struct bnxt_link_info *link_info = &bp->link_info;
1579
1580                 if (BNXT_VF(bp))
1581                         goto async_event_process_exit;
1582                 if (data1 & 0x20000) {
1583                         u16 fw_speed = link_info->force_link_speed;
1584                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1585
1586                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1587                                     speed);
1588                 }
1589                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1590                 /* fall thru */
1591         }
1592         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1593                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1594                 break;
1595         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1596                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1597                 break;
1598         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1599                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1600                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1601
1602                 if (BNXT_VF(bp))
1603                         break;
1604
1605                 if (bp->pf.port_id != port_id)
1606                         break;
1607
1608                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1609                 break;
1610         }
1611         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1612                 if (BNXT_PF(bp))
1613                         goto async_event_process_exit;
1614                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1615                 break;
1616         default:
1617                 goto async_event_process_exit;
1618         }
1619         schedule_work(&bp->sp_task);
1620 async_event_process_exit:
1621         bnxt_ulp_async_events(bp, cmpl);
1622         return 0;
1623 }
1624
1625 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1626 {
1627         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1628         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1629         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1630                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1631
1632         switch (cmpl_type) {
1633         case CMPL_BASE_TYPE_HWRM_DONE:
1634                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1635                 if (seq_id == bp->hwrm_intr_seq_id)
1636                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1637                 else
1638                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1639                 break;
1640
1641         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1642                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1643
1644                 if ((vf_id < bp->pf.first_vf_id) ||
1645                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1646                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1647                                    vf_id);
1648                         return -EINVAL;
1649                 }
1650
1651                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1652                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1653                 schedule_work(&bp->sp_task);
1654                 break;
1655
1656         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1657                 bnxt_async_event_process(bp,
1658                                          (struct hwrm_async_event_cmpl *)txcmp);
1659
1660         default:
1661                 break;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1668 {
1669         struct bnxt_napi *bnapi = dev_instance;
1670         struct bnxt *bp = bnapi->bp;
1671         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1672         u32 cons = RING_CMP(cpr->cp_raw_cons);
1673
1674         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1675         napi_schedule(&bnapi->napi);
1676         return IRQ_HANDLED;
1677 }
1678
1679 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1680 {
1681         u32 raw_cons = cpr->cp_raw_cons;
1682         u16 cons = RING_CMP(raw_cons);
1683         struct tx_cmp *txcmp;
1684
1685         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1686
1687         return TX_CMP_VALID(txcmp, raw_cons);
1688 }
1689
1690 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1691 {
1692         struct bnxt_napi *bnapi = dev_instance;
1693         struct bnxt *bp = bnapi->bp;
1694         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1695         u32 cons = RING_CMP(cpr->cp_raw_cons);
1696         u32 int_status;
1697
1698         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1699
1700         if (!bnxt_has_work(bp, cpr)) {
1701                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1702                 /* return if erroneous interrupt */
1703                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1704                         return IRQ_NONE;
1705         }
1706
1707         /* disable ring IRQ */
1708         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1709
1710         /* Return here if interrupt is shared and is disabled. */
1711         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1712                 return IRQ_HANDLED;
1713
1714         napi_schedule(&bnapi->napi);
1715         return IRQ_HANDLED;
1716 }
1717
1718 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1719 {
1720         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1721         u32 raw_cons = cpr->cp_raw_cons;
1722         u32 cons;
1723         int tx_pkts = 0;
1724         int rx_pkts = 0;
1725         u8 event = 0;
1726         struct tx_cmp *txcmp;
1727
1728         while (1) {
1729                 int rc;
1730
1731                 cons = RING_CMP(raw_cons);
1732                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1733
1734                 if (!TX_CMP_VALID(txcmp, raw_cons))
1735                         break;
1736
1737                 /* The valid test of the entry must be done first before
1738                  * reading any further.
1739                  */
1740                 dma_rmb();
1741                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1742                         tx_pkts++;
1743                         /* return full budget so NAPI will complete. */
1744                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1745                                 rx_pkts = budget;
1746                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1747                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1748                         if (likely(rc >= 0))
1749                                 rx_pkts += rc;
1750                         else if (rc == -EBUSY)  /* partial completion */
1751                                 break;
1752                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1753                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1754                                     (TX_CMP_TYPE(txcmp) ==
1755                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1756                                     (TX_CMP_TYPE(txcmp) ==
1757                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1758                         bnxt_hwrm_handler(bp, txcmp);
1759                 }
1760                 raw_cons = NEXT_RAW_CMP(raw_cons);
1761
1762                 if (rx_pkts == budget)
1763                         break;
1764         }
1765
1766         if (event & BNXT_TX_EVENT) {
1767                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1768                 void __iomem *db = txr->tx_doorbell;
1769                 u16 prod = txr->tx_prod;
1770
1771                 /* Sync BD data before updating doorbell */
1772                 wmb();
1773
1774                 writel(DB_KEY_TX | prod, db);
1775                 writel(DB_KEY_TX | prod, db);
1776         }
1777
1778         cpr->cp_raw_cons = raw_cons;
1779         /* ACK completion ring before freeing tx ring and producing new
1780          * buffers in rx/agg rings to prevent overflowing the completion
1781          * ring.
1782          */
1783         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1784
1785         if (tx_pkts)
1786                 bnapi->tx_int(bp, bnapi, tx_pkts);
1787
1788         if (event & BNXT_RX_EVENT) {
1789                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1790
1791                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1792                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1793                 if (event & BNXT_AGG_EVENT) {
1794                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1795                                rxr->rx_agg_doorbell);
1796                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1797                                rxr->rx_agg_doorbell);
1798                 }
1799         }
1800         return rx_pkts;
1801 }
1802
1803 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1804 {
1805         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1806         struct bnxt *bp = bnapi->bp;
1807         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1808         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1809         struct tx_cmp *txcmp;
1810         struct rx_cmp_ext *rxcmp1;
1811         u32 cp_cons, tmp_raw_cons;
1812         u32 raw_cons = cpr->cp_raw_cons;
1813         u32 rx_pkts = 0;
1814         u8 event = 0;
1815
1816         while (1) {
1817                 int rc;
1818
1819                 cp_cons = RING_CMP(raw_cons);
1820                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1821
1822                 if (!TX_CMP_VALID(txcmp, raw_cons))
1823                         break;
1824
1825                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1826                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1827                         cp_cons = RING_CMP(tmp_raw_cons);
1828                         rxcmp1 = (struct rx_cmp_ext *)
1829                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1830
1831                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1832                                 break;
1833
1834                         /* force an error to recycle the buffer */
1835                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1836                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1837
1838                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1839                         if (likely(rc == -EIO))
1840                                 rx_pkts++;
1841                         else if (rc == -EBUSY)  /* partial completion */
1842                                 break;
1843                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1844                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1845                         bnxt_hwrm_handler(bp, txcmp);
1846                 } else {
1847                         netdev_err(bp->dev,
1848                                    "Invalid completion received on special ring\n");
1849                 }
1850                 raw_cons = NEXT_RAW_CMP(raw_cons);
1851
1852                 if (rx_pkts == budget)
1853                         break;
1854         }
1855
1856         cpr->cp_raw_cons = raw_cons;
1857         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1858         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1859         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1860
1861         if (event & BNXT_AGG_EVENT) {
1862                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1863                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1864         }
1865
1866         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1867                 napi_complete_done(napi, rx_pkts);
1868                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1869         }
1870         return rx_pkts;
1871 }
1872
1873 static int bnxt_poll(struct napi_struct *napi, int budget)
1874 {
1875         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1876         struct bnxt *bp = bnapi->bp;
1877         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1878         int work_done = 0;
1879
1880         while (1) {
1881                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1882
1883                 if (work_done >= budget)
1884                         break;
1885
1886                 if (!bnxt_has_work(bp, cpr)) {
1887                         if (napi_complete_done(napi, work_done))
1888                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1889                                                  cpr->cp_raw_cons);
1890                         break;
1891                 }
1892         }
1893         mmiowb();
1894         return work_done;
1895 }
1896
1897 static void bnxt_free_tx_skbs(struct bnxt *bp)
1898 {
1899         int i, max_idx;
1900         struct pci_dev *pdev = bp->pdev;
1901
1902         if (!bp->tx_ring)
1903                 return;
1904
1905         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1906         for (i = 0; i < bp->tx_nr_rings; i++) {
1907                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1908                 int j;
1909
1910                 for (j = 0; j < max_idx;) {
1911                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1912                         struct sk_buff *skb = tx_buf->skb;
1913                         int k, last;
1914
1915                         if (!skb) {
1916                                 j++;
1917                                 continue;
1918                         }
1919
1920                         tx_buf->skb = NULL;
1921
1922                         if (tx_buf->is_push) {
1923                                 dev_kfree_skb(skb);
1924                                 j += 2;
1925                                 continue;
1926                         }
1927
1928                         dma_unmap_single(&pdev->dev,
1929                                          dma_unmap_addr(tx_buf, mapping),
1930                                          skb_headlen(skb),
1931                                          PCI_DMA_TODEVICE);
1932
1933                         last = tx_buf->nr_frags;
1934                         j += 2;
1935                         for (k = 0; k < last; k++, j++) {
1936                                 int ring_idx = j & bp->tx_ring_mask;
1937                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1938
1939                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1940                                 dma_unmap_page(
1941                                         &pdev->dev,
1942                                         dma_unmap_addr(tx_buf, mapping),
1943                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1944                         }
1945                         dev_kfree_skb(skb);
1946                 }
1947                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1948         }
1949 }
1950
1951 static void bnxt_free_rx_skbs(struct bnxt *bp)
1952 {
1953         int i, max_idx, max_agg_idx;
1954         struct pci_dev *pdev = bp->pdev;
1955
1956         if (!bp->rx_ring)
1957                 return;
1958
1959         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1960         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1961         for (i = 0; i < bp->rx_nr_rings; i++) {
1962                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1963                 int j;
1964
1965                 if (rxr->rx_tpa) {
1966                         for (j = 0; j < MAX_TPA; j++) {
1967                                 struct bnxt_tpa_info *tpa_info =
1968                                                         &rxr->rx_tpa[j];
1969                                 u8 *data = tpa_info->data;
1970
1971                                 if (!data)
1972                                         continue;
1973
1974                                 dma_unmap_single(&pdev->dev, tpa_info->mapping,
1975                                                  bp->rx_buf_use_size,
1976                                                  bp->rx_dir);
1977
1978                                 tpa_info->data = NULL;
1979
1980                                 kfree(data);
1981                         }
1982                 }
1983
1984                 for (j = 0; j < max_idx; j++) {
1985                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1986                         dma_addr_t mapping = rx_buf->mapping;
1987                         void *data = rx_buf->data;
1988
1989                         if (!data)
1990                                 continue;
1991
1992                         rx_buf->data = NULL;
1993
1994                         if (BNXT_RX_PAGE_MODE(bp)) {
1995                                 mapping -= bp->rx_dma_offset;
1996                                 dma_unmap_page(&pdev->dev, mapping,
1997                                                PAGE_SIZE, bp->rx_dir);
1998                                 __free_page(data);
1999                         } else {
2000                                 dma_unmap_single(&pdev->dev, mapping,
2001                                                  bp->rx_buf_use_size,
2002                                                  bp->rx_dir);
2003                                 kfree(data);
2004                         }
2005                 }
2006
2007                 for (j = 0; j < max_agg_idx; j++) {
2008                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2009                                 &rxr->rx_agg_ring[j];
2010                         struct page *page = rx_agg_buf->page;
2011
2012                         if (!page)
2013                                 continue;
2014
2015                         dma_unmap_page(&pdev->dev, rx_agg_buf->mapping,
2016                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
2017
2018                         rx_agg_buf->page = NULL;
2019                         __clear_bit(j, rxr->rx_agg_bmap);
2020
2021                         __free_page(page);
2022                 }
2023                 if (rxr->rx_page) {
2024                         __free_page(rxr->rx_page);
2025                         rxr->rx_page = NULL;
2026                 }
2027         }
2028 }
2029
2030 static void bnxt_free_skbs(struct bnxt *bp)
2031 {
2032         bnxt_free_tx_skbs(bp);
2033         bnxt_free_rx_skbs(bp);
2034 }
2035
2036 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2037 {
2038         struct pci_dev *pdev = bp->pdev;
2039         int i;
2040
2041         for (i = 0; i < ring->nr_pages; i++) {
2042                 if (!ring->pg_arr[i])
2043                         continue;
2044
2045                 dma_free_coherent(&pdev->dev, ring->page_size,
2046                                   ring->pg_arr[i], ring->dma_arr[i]);
2047
2048                 ring->pg_arr[i] = NULL;
2049         }
2050         if (ring->pg_tbl) {
2051                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2052                                   ring->pg_tbl, ring->pg_tbl_map);
2053                 ring->pg_tbl = NULL;
2054         }
2055         if (ring->vmem_size && *ring->vmem) {
2056                 vfree(*ring->vmem);
2057                 *ring->vmem = NULL;
2058         }
2059 }
2060
2061 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2062 {
2063         int i;
2064         struct pci_dev *pdev = bp->pdev;
2065
2066         if (ring->nr_pages > 1) {
2067                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2068                                                   ring->nr_pages * 8,
2069                                                   &ring->pg_tbl_map,
2070                                                   GFP_KERNEL);
2071                 if (!ring->pg_tbl)
2072                         return -ENOMEM;
2073         }
2074
2075         for (i = 0; i < ring->nr_pages; i++) {
2076                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2077                                                      ring->page_size,
2078                                                      &ring->dma_arr[i],
2079                                                      GFP_KERNEL);
2080                 if (!ring->pg_arr[i])
2081                         return -ENOMEM;
2082
2083                 if (ring->nr_pages > 1)
2084                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2085         }
2086
2087         if (ring->vmem_size) {
2088                 *ring->vmem = vzalloc(ring->vmem_size);
2089                 if (!(*ring->vmem))
2090                         return -ENOMEM;
2091         }
2092         return 0;
2093 }
2094
2095 static void bnxt_free_rx_rings(struct bnxt *bp)
2096 {
2097         int i;
2098
2099         if (!bp->rx_ring)
2100                 return;
2101
2102         for (i = 0; i < bp->rx_nr_rings; i++) {
2103                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2104                 struct bnxt_ring_struct *ring;
2105
2106                 if (rxr->xdp_prog)
2107                         bpf_prog_put(rxr->xdp_prog);
2108
2109                 kfree(rxr->rx_tpa);
2110                 rxr->rx_tpa = NULL;
2111
2112                 kfree(rxr->rx_agg_bmap);
2113                 rxr->rx_agg_bmap = NULL;
2114
2115                 ring = &rxr->rx_ring_struct;
2116                 bnxt_free_ring(bp, ring);
2117
2118                 ring = &rxr->rx_agg_ring_struct;
2119                 bnxt_free_ring(bp, ring);
2120         }
2121 }
2122
2123 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2124 {
2125         int i, rc, agg_rings = 0, tpa_rings = 0;
2126
2127         if (!bp->rx_ring)
2128                 return -ENOMEM;
2129
2130         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2131                 agg_rings = 1;
2132
2133         if (bp->flags & BNXT_FLAG_TPA)
2134                 tpa_rings = 1;
2135
2136         for (i = 0; i < bp->rx_nr_rings; i++) {
2137                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2138                 struct bnxt_ring_struct *ring;
2139
2140                 ring = &rxr->rx_ring_struct;
2141
2142                 rc = bnxt_alloc_ring(bp, ring);
2143                 if (rc)
2144                         return rc;
2145
2146                 if (agg_rings) {
2147                         u16 mem_size;
2148
2149                         ring = &rxr->rx_agg_ring_struct;
2150                         rc = bnxt_alloc_ring(bp, ring);
2151                         if (rc)
2152                                 return rc;
2153
2154                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2155                         mem_size = rxr->rx_agg_bmap_size / 8;
2156                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2157                         if (!rxr->rx_agg_bmap)
2158                                 return -ENOMEM;
2159
2160                         if (tpa_rings) {
2161                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2162                                                 sizeof(struct bnxt_tpa_info),
2163                                                 GFP_KERNEL);
2164                                 if (!rxr->rx_tpa)
2165                                         return -ENOMEM;
2166                         }
2167                 }
2168         }
2169         return 0;
2170 }
2171
2172 static void bnxt_free_tx_rings(struct bnxt *bp)
2173 {
2174         int i;
2175         struct pci_dev *pdev = bp->pdev;
2176
2177         if (!bp->tx_ring)
2178                 return;
2179
2180         for (i = 0; i < bp->tx_nr_rings; i++) {
2181                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2182                 struct bnxt_ring_struct *ring;
2183
2184                 if (txr->tx_push) {
2185                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2186                                           txr->tx_push, txr->tx_push_mapping);
2187                         txr->tx_push = NULL;
2188                 }
2189
2190                 ring = &txr->tx_ring_struct;
2191
2192                 bnxt_free_ring(bp, ring);
2193         }
2194 }
2195
2196 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2197 {
2198         int i, j, rc;
2199         struct pci_dev *pdev = bp->pdev;
2200
2201         bp->tx_push_size = 0;
2202         if (bp->tx_push_thresh) {
2203                 int push_size;
2204
2205                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2206                                         bp->tx_push_thresh);
2207
2208                 if (push_size > 256) {
2209                         push_size = 0;
2210                         bp->tx_push_thresh = 0;
2211                 }
2212
2213                 bp->tx_push_size = push_size;
2214         }
2215
2216         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2217                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2218                 struct bnxt_ring_struct *ring;
2219
2220                 ring = &txr->tx_ring_struct;
2221
2222                 rc = bnxt_alloc_ring(bp, ring);
2223                 if (rc)
2224                         return rc;
2225
2226                 if (bp->tx_push_size) {
2227                         dma_addr_t mapping;
2228
2229                         /* One pre-allocated DMA buffer to backup
2230                          * TX push operation
2231                          */
2232                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2233                                                 bp->tx_push_size,
2234                                                 &txr->tx_push_mapping,
2235                                                 GFP_KERNEL);
2236
2237                         if (!txr->tx_push)
2238                                 return -ENOMEM;
2239
2240                         mapping = txr->tx_push_mapping +
2241                                 sizeof(struct tx_push_bd);
2242                         txr->data_mapping = cpu_to_le64(mapping);
2243
2244                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2245                 }
2246                 ring->queue_id = bp->q_info[j].queue_id;
2247                 if (i < bp->tx_nr_rings_xdp)
2248                         continue;
2249                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2250                         j++;
2251         }
2252         return 0;
2253 }
2254
2255 static void bnxt_free_cp_rings(struct bnxt *bp)
2256 {
2257         int i;
2258
2259         if (!bp->bnapi)
2260                 return;
2261
2262         for (i = 0; i < bp->cp_nr_rings; i++) {
2263                 struct bnxt_napi *bnapi = bp->bnapi[i];
2264                 struct bnxt_cp_ring_info *cpr;
2265                 struct bnxt_ring_struct *ring;
2266
2267                 if (!bnapi)
2268                         continue;
2269
2270                 cpr = &bnapi->cp_ring;
2271                 ring = &cpr->cp_ring_struct;
2272
2273                 bnxt_free_ring(bp, ring);
2274         }
2275 }
2276
2277 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2278 {
2279         int i, rc;
2280
2281         for (i = 0; i < bp->cp_nr_rings; i++) {
2282                 struct bnxt_napi *bnapi = bp->bnapi[i];
2283                 struct bnxt_cp_ring_info *cpr;
2284                 struct bnxt_ring_struct *ring;
2285
2286                 if (!bnapi)
2287                         continue;
2288
2289                 cpr = &bnapi->cp_ring;
2290                 ring = &cpr->cp_ring_struct;
2291
2292                 rc = bnxt_alloc_ring(bp, ring);
2293                 if (rc)
2294                         return rc;
2295         }
2296         return 0;
2297 }
2298
2299 static void bnxt_init_ring_struct(struct bnxt *bp)
2300 {
2301         int i;
2302
2303         for (i = 0; i < bp->cp_nr_rings; i++) {
2304                 struct bnxt_napi *bnapi = bp->bnapi[i];
2305                 struct bnxt_cp_ring_info *cpr;
2306                 struct bnxt_rx_ring_info *rxr;
2307                 struct bnxt_tx_ring_info *txr;
2308                 struct bnxt_ring_struct *ring;
2309
2310                 if (!bnapi)
2311                         continue;
2312
2313                 cpr = &bnapi->cp_ring;
2314                 ring = &cpr->cp_ring_struct;
2315                 ring->nr_pages = bp->cp_nr_pages;
2316                 ring->page_size = HW_CMPD_RING_SIZE;
2317                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2318                 ring->dma_arr = cpr->cp_desc_mapping;
2319                 ring->vmem_size = 0;
2320
2321                 rxr = bnapi->rx_ring;
2322                 if (!rxr)
2323                         goto skip_rx;
2324
2325                 ring = &rxr->rx_ring_struct;
2326                 ring->nr_pages = bp->rx_nr_pages;
2327                 ring->page_size = HW_RXBD_RING_SIZE;
2328                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2329                 ring->dma_arr = rxr->rx_desc_mapping;
2330                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2331                 ring->vmem = (void **)&rxr->rx_buf_ring;
2332
2333                 ring = &rxr->rx_agg_ring_struct;
2334                 ring->nr_pages = bp->rx_agg_nr_pages;
2335                 ring->page_size = HW_RXBD_RING_SIZE;
2336                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2337                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2338                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2339                 ring->vmem = (void **)&rxr->rx_agg_ring;
2340
2341 skip_rx:
2342                 txr = bnapi->tx_ring;
2343                 if (!txr)
2344                         continue;
2345
2346                 ring = &txr->tx_ring_struct;
2347                 ring->nr_pages = bp->tx_nr_pages;
2348                 ring->page_size = HW_RXBD_RING_SIZE;
2349                 ring->pg_arr = (void **)txr->tx_desc_ring;
2350                 ring->dma_arr = txr->tx_desc_mapping;
2351                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2352                 ring->vmem = (void **)&txr->tx_buf_ring;
2353         }
2354 }
2355
2356 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2357 {
2358         int i;
2359         u32 prod;
2360         struct rx_bd **rx_buf_ring;
2361
2362         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2363         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2364                 int j;
2365                 struct rx_bd *rxbd;
2366
2367                 rxbd = rx_buf_ring[i];
2368                 if (!rxbd)
2369                         continue;
2370
2371                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2372                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2373                         rxbd->rx_bd_opaque = prod;
2374                 }
2375         }
2376 }
2377
2378 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2379 {
2380         struct net_device *dev = bp->dev;
2381         struct bnxt_rx_ring_info *rxr;
2382         struct bnxt_ring_struct *ring;
2383         u32 prod, type;
2384         int i;
2385
2386         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2387                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2388
2389         if (NET_IP_ALIGN == 2)
2390                 type |= RX_BD_FLAGS_SOP;
2391
2392         rxr = &bp->rx_ring[ring_nr];
2393         ring = &rxr->rx_ring_struct;
2394         bnxt_init_rxbd_pages(ring, type);
2395
2396         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2397                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2398                 if (IS_ERR(rxr->xdp_prog)) {
2399                         int rc = PTR_ERR(rxr->xdp_prog);
2400
2401                         rxr->xdp_prog = NULL;
2402                         return rc;
2403                 }
2404         }
2405         prod = rxr->rx_prod;
2406         for (i = 0; i < bp->rx_ring_size; i++) {
2407                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2408                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2409                                     ring_nr, i, bp->rx_ring_size);
2410                         break;
2411                 }
2412                 prod = NEXT_RX(prod);
2413         }
2414         rxr->rx_prod = prod;
2415         ring->fw_ring_id = INVALID_HW_RING_ID;
2416
2417         ring = &rxr->rx_agg_ring_struct;
2418         ring->fw_ring_id = INVALID_HW_RING_ID;
2419
2420         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2421                 return 0;
2422
2423         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2424                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2425
2426         bnxt_init_rxbd_pages(ring, type);
2427
2428         prod = rxr->rx_agg_prod;
2429         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2430                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2431                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2432                                     ring_nr, i, bp->rx_ring_size);
2433                         break;
2434                 }
2435                 prod = NEXT_RX_AGG(prod);
2436         }
2437         rxr->rx_agg_prod = prod;
2438
2439         if (bp->flags & BNXT_FLAG_TPA) {
2440                 if (rxr->rx_tpa) {
2441                         u8 *data;
2442                         dma_addr_t mapping;
2443
2444                         for (i = 0; i < MAX_TPA; i++) {
2445                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2446                                                             GFP_KERNEL);
2447                                 if (!data)
2448                                         return -ENOMEM;
2449
2450                                 rxr->rx_tpa[i].data = data;
2451                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2452                                 rxr->rx_tpa[i].mapping = mapping;
2453                         }
2454                 } else {
2455                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2456                         return -ENOMEM;
2457                 }
2458         }
2459
2460         return 0;
2461 }
2462
2463 static void bnxt_init_cp_rings(struct bnxt *bp)
2464 {
2465         int i;
2466
2467         for (i = 0; i < bp->cp_nr_rings; i++) {
2468                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2469                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2470
2471                 ring->fw_ring_id = INVALID_HW_RING_ID;
2472         }
2473 }
2474
2475 static int bnxt_init_rx_rings(struct bnxt *bp)
2476 {
2477         int i, rc = 0;
2478
2479         if (BNXT_RX_PAGE_MODE(bp)) {
2480                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2481                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2482         } else {
2483                 bp->rx_offset = BNXT_RX_OFFSET;
2484                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2485         }
2486
2487         for (i = 0; i < bp->rx_nr_rings; i++) {
2488                 rc = bnxt_init_one_rx_ring(bp, i);
2489                 if (rc)
2490                         break;
2491         }
2492
2493         return rc;
2494 }
2495
2496 static int bnxt_init_tx_rings(struct bnxt *bp)
2497 {
2498         u16 i;
2499
2500         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2501                                    MAX_SKB_FRAGS + 1);
2502
2503         for (i = 0; i < bp->tx_nr_rings; i++) {
2504                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2505                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2506
2507                 ring->fw_ring_id = INVALID_HW_RING_ID;
2508         }
2509
2510         return 0;
2511 }
2512
2513 static void bnxt_free_ring_grps(struct bnxt *bp)
2514 {
2515         kfree(bp->grp_info);
2516         bp->grp_info = NULL;
2517 }
2518
2519 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2520 {
2521         int i;
2522
2523         if (irq_re_init) {
2524                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2525                                        sizeof(struct bnxt_ring_grp_info),
2526                                        GFP_KERNEL);
2527                 if (!bp->grp_info)
2528                         return -ENOMEM;
2529         }
2530         for (i = 0; i < bp->cp_nr_rings; i++) {
2531                 if (irq_re_init)
2532                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2533                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2534                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2535                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2536                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2537         }
2538         return 0;
2539 }
2540
2541 static void bnxt_free_vnics(struct bnxt *bp)
2542 {
2543         kfree(bp->vnic_info);
2544         bp->vnic_info = NULL;
2545         bp->nr_vnics = 0;
2546 }
2547
2548 static int bnxt_alloc_vnics(struct bnxt *bp)
2549 {
2550         int num_vnics = 1;
2551
2552 #ifdef CONFIG_RFS_ACCEL
2553         if (bp->flags & BNXT_FLAG_RFS)
2554                 num_vnics += bp->rx_nr_rings;
2555 #endif
2556
2557         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2558                 num_vnics++;
2559
2560         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2561                                 GFP_KERNEL);
2562         if (!bp->vnic_info)
2563                 return -ENOMEM;
2564
2565         bp->nr_vnics = num_vnics;
2566         return 0;
2567 }
2568
2569 static void bnxt_init_vnics(struct bnxt *bp)
2570 {
2571         int i;
2572
2573         for (i = 0; i < bp->nr_vnics; i++) {
2574                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2575
2576                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2577                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2578                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2579                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2580
2581                 if (bp->vnic_info[i].rss_hash_key) {
2582                         if (i == 0)
2583                                 prandom_bytes(vnic->rss_hash_key,
2584                                               HW_HASH_KEY_SIZE);
2585                         else
2586                                 memcpy(vnic->rss_hash_key,
2587                                        bp->vnic_info[0].rss_hash_key,
2588                                        HW_HASH_KEY_SIZE);
2589                 }
2590         }
2591 }
2592
2593 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2594 {
2595         int pages;
2596
2597         pages = ring_size / desc_per_pg;
2598
2599         if (!pages)
2600                 return 1;
2601
2602         pages++;
2603
2604         while (pages & (pages - 1))
2605                 pages++;
2606
2607         return pages;
2608 }
2609
2610 void bnxt_set_tpa_flags(struct bnxt *bp)
2611 {
2612         bp->flags &= ~BNXT_FLAG_TPA;
2613         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2614                 return;
2615         if (bp->dev->features & NETIF_F_LRO)
2616                 bp->flags |= BNXT_FLAG_LRO;
2617         if (bp->dev->features & NETIF_F_GRO)
2618                 bp->flags |= BNXT_FLAG_GRO;
2619 }
2620
2621 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2622  * be set on entry.
2623  */
2624 void bnxt_set_ring_params(struct bnxt *bp)
2625 {
2626         u32 ring_size, rx_size, rx_space;
2627         u32 agg_factor = 0, agg_ring_size = 0;
2628
2629         /* 8 for CRC and VLAN */
2630         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2631
2632         rx_space = rx_size + NET_SKB_PAD +
2633                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2634
2635         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2636         ring_size = bp->rx_ring_size;
2637         bp->rx_agg_ring_size = 0;
2638         bp->rx_agg_nr_pages = 0;
2639
2640         if (bp->flags & BNXT_FLAG_TPA)
2641                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2642
2643         bp->flags &= ~BNXT_FLAG_JUMBO;
2644         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2645                 u32 jumbo_factor;
2646
2647                 bp->flags |= BNXT_FLAG_JUMBO;
2648                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2649                 if (jumbo_factor > agg_factor)
2650                         agg_factor = jumbo_factor;
2651         }
2652         agg_ring_size = ring_size * agg_factor;
2653
2654         if (agg_ring_size) {
2655                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2656                                                         RX_DESC_CNT);
2657                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2658                         u32 tmp = agg_ring_size;
2659
2660                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2661                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2662                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2663                                     tmp, agg_ring_size);
2664                 }
2665                 bp->rx_agg_ring_size = agg_ring_size;
2666                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2667                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2668                 rx_space = rx_size + NET_SKB_PAD +
2669                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2670         }
2671
2672         bp->rx_buf_use_size = rx_size;
2673         bp->rx_buf_size = rx_space;
2674
2675         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2676         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2677
2678         ring_size = bp->tx_ring_size;
2679         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2680         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2681
2682         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2683         bp->cp_ring_size = ring_size;
2684
2685         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2686         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2687                 bp->cp_nr_pages = MAX_CP_PAGES;
2688                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2689                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2690                             ring_size, bp->cp_ring_size);
2691         }
2692         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2693         bp->cp_ring_mask = bp->cp_bit - 1;
2694 }
2695
2696 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2697 {
2698         if (page_mode) {
2699                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2700                         return -EOPNOTSUPP;
2701                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2702                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2703                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2704                 bp->dev->hw_features &= ~NETIF_F_LRO;
2705                 bp->dev->features &= ~NETIF_F_LRO;
2706                 bp->rx_dir = DMA_BIDIRECTIONAL;
2707                 bp->rx_skb_func = bnxt_rx_page_skb;
2708         } else {
2709                 bp->dev->max_mtu = BNXT_MAX_MTU;
2710                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2711                 bp->rx_dir = DMA_FROM_DEVICE;
2712                 bp->rx_skb_func = bnxt_rx_skb;
2713         }
2714         return 0;
2715 }
2716
2717 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2718 {
2719         int i;
2720         struct bnxt_vnic_info *vnic;
2721         struct pci_dev *pdev = bp->pdev;
2722
2723         if (!bp->vnic_info)
2724                 return;
2725
2726         for (i = 0; i < bp->nr_vnics; i++) {
2727                 vnic = &bp->vnic_info[i];
2728
2729                 kfree(vnic->fw_grp_ids);
2730                 vnic->fw_grp_ids = NULL;
2731
2732                 kfree(vnic->uc_list);
2733                 vnic->uc_list = NULL;
2734
2735                 if (vnic->mc_list) {
2736                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2737                                           vnic->mc_list, vnic->mc_list_mapping);
2738                         vnic->mc_list = NULL;
2739                 }
2740
2741                 if (vnic->rss_table) {
2742                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2743                                           vnic->rss_table,
2744                                           vnic->rss_table_dma_addr);
2745                         vnic->rss_table = NULL;
2746                 }
2747
2748                 vnic->rss_hash_key = NULL;
2749                 vnic->flags = 0;
2750         }
2751 }
2752
2753 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2754 {
2755         int i, rc = 0, size;
2756         struct bnxt_vnic_info *vnic;
2757         struct pci_dev *pdev = bp->pdev;
2758         int max_rings;
2759
2760         for (i = 0; i < bp->nr_vnics; i++) {
2761                 vnic = &bp->vnic_info[i];
2762
2763                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2764                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2765
2766                         if (mem_size > 0) {
2767                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2768                                 if (!vnic->uc_list) {
2769                                         rc = -ENOMEM;
2770                                         goto out;
2771                                 }
2772                         }
2773                 }
2774
2775                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2776                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2777                         vnic->mc_list =
2778                                 dma_alloc_coherent(&pdev->dev,
2779                                                    vnic->mc_list_size,
2780                                                    &vnic->mc_list_mapping,
2781                                                    GFP_KERNEL);
2782                         if (!vnic->mc_list) {
2783                                 rc = -ENOMEM;
2784                                 goto out;
2785                         }
2786                 }
2787
2788                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2789                         max_rings = bp->rx_nr_rings;
2790                 else
2791                         max_rings = 1;
2792
2793                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2794                 if (!vnic->fw_grp_ids) {
2795                         rc = -ENOMEM;
2796                         goto out;
2797                 }
2798
2799                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2800                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2801                         continue;
2802
2803                 /* Allocate rss table and hash key */
2804                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2805                                                      &vnic->rss_table_dma_addr,
2806                                                      GFP_KERNEL);
2807                 if (!vnic->rss_table) {
2808                         rc = -ENOMEM;
2809                         goto out;
2810                 }
2811
2812                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2813
2814                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2815                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2816         }
2817         return 0;
2818
2819 out:
2820         return rc;
2821 }
2822
2823 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2824 {
2825         struct pci_dev *pdev = bp->pdev;
2826
2827         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2828                           bp->hwrm_cmd_resp_dma_addr);
2829
2830         bp->hwrm_cmd_resp_addr = NULL;
2831         if (bp->hwrm_dbg_resp_addr) {
2832                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2833                                   bp->hwrm_dbg_resp_addr,
2834                                   bp->hwrm_dbg_resp_dma_addr);
2835
2836                 bp->hwrm_dbg_resp_addr = NULL;
2837         }
2838 }
2839
2840 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2841 {
2842         struct pci_dev *pdev = bp->pdev;
2843
2844         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2845                                                    &bp->hwrm_cmd_resp_dma_addr,
2846                                                    GFP_KERNEL);
2847         if (!bp->hwrm_cmd_resp_addr)
2848                 return -ENOMEM;
2849         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2850                                                     HWRM_DBG_REG_BUF_SIZE,
2851                                                     &bp->hwrm_dbg_resp_dma_addr,
2852                                                     GFP_KERNEL);
2853         if (!bp->hwrm_dbg_resp_addr)
2854                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2855
2856         return 0;
2857 }
2858
2859 static void bnxt_free_stats(struct bnxt *bp)
2860 {
2861         u32 size, i;
2862         struct pci_dev *pdev = bp->pdev;
2863
2864         if (bp->hw_rx_port_stats) {
2865                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2866                                   bp->hw_rx_port_stats,
2867                                   bp->hw_rx_port_stats_map);
2868                 bp->hw_rx_port_stats = NULL;
2869                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2870         }
2871
2872         if (!bp->bnapi)
2873                 return;
2874
2875         size = sizeof(struct ctx_hw_stats);
2876
2877         for (i = 0; i < bp->cp_nr_rings; i++) {
2878                 struct bnxt_napi *bnapi = bp->bnapi[i];
2879                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2880
2881                 if (cpr->hw_stats) {
2882                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2883                                           cpr->hw_stats_map);
2884                         cpr->hw_stats = NULL;
2885                 }
2886         }
2887 }
2888
2889 static int bnxt_alloc_stats(struct bnxt *bp)
2890 {
2891         u32 size, i;
2892         struct pci_dev *pdev = bp->pdev;
2893
2894         size = sizeof(struct ctx_hw_stats);
2895
2896         for (i = 0; i < bp->cp_nr_rings; i++) {
2897                 struct bnxt_napi *bnapi = bp->bnapi[i];
2898                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2899
2900                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2901                                                    &cpr->hw_stats_map,
2902                                                    GFP_KERNEL);
2903                 if (!cpr->hw_stats)
2904                         return -ENOMEM;
2905
2906                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2907         }
2908
2909         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2910                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2911                                          sizeof(struct tx_port_stats) + 1024;
2912
2913                 bp->hw_rx_port_stats =
2914                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2915                                            &bp->hw_rx_port_stats_map,
2916                                            GFP_KERNEL);
2917                 if (!bp->hw_rx_port_stats)
2918                         return -ENOMEM;
2919
2920                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2921                                        512;
2922                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2923                                            sizeof(struct rx_port_stats) + 512;
2924                 bp->flags |= BNXT_FLAG_PORT_STATS;
2925         }
2926         return 0;
2927 }
2928
2929 static void bnxt_clear_ring_indices(struct bnxt *bp)
2930 {
2931         int i;
2932
2933         if (!bp->bnapi)
2934                 return;
2935
2936         for (i = 0; i < bp->cp_nr_rings; i++) {
2937                 struct bnxt_napi *bnapi = bp->bnapi[i];
2938                 struct bnxt_cp_ring_info *cpr;
2939                 struct bnxt_rx_ring_info *rxr;
2940                 struct bnxt_tx_ring_info *txr;
2941
2942                 if (!bnapi)
2943                         continue;
2944
2945                 cpr = &bnapi->cp_ring;
2946                 cpr->cp_raw_cons = 0;
2947
2948                 txr = bnapi->tx_ring;
2949                 if (txr) {
2950                         txr->tx_prod = 0;
2951                         txr->tx_cons = 0;
2952                 }
2953
2954                 rxr = bnapi->rx_ring;
2955                 if (rxr) {
2956                         rxr->rx_prod = 0;
2957                         rxr->rx_agg_prod = 0;
2958                         rxr->rx_sw_agg_prod = 0;
2959                         rxr->rx_next_cons = 0;
2960                 }
2961         }
2962 }
2963
2964 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2965 {
2966 #ifdef CONFIG_RFS_ACCEL
2967         int i;
2968
2969         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2970          * safe to delete the hash table.
2971          */
2972         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2973                 struct hlist_head *head;
2974                 struct hlist_node *tmp;
2975                 struct bnxt_ntuple_filter *fltr;
2976
2977                 head = &bp->ntp_fltr_hash_tbl[i];
2978                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2979                         hlist_del(&fltr->hash);
2980                         kfree(fltr);
2981                 }
2982         }
2983         if (irq_reinit) {
2984                 kfree(bp->ntp_fltr_bmap);
2985                 bp->ntp_fltr_bmap = NULL;
2986         }
2987         bp->ntp_fltr_count = 0;
2988 #endif
2989 }
2990
2991 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2992 {
2993 #ifdef CONFIG_RFS_ACCEL
2994         int i, rc = 0;
2995
2996         if (!(bp->flags & BNXT_FLAG_RFS))
2997                 return 0;
2998
2999         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3000                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3001
3002         bp->ntp_fltr_count = 0;
3003         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3004                                     sizeof(long),
3005                                     GFP_KERNEL);
3006
3007         if (!bp->ntp_fltr_bmap)
3008                 rc = -ENOMEM;
3009
3010         return rc;
3011 #else
3012         return 0;
3013 #endif
3014 }
3015
3016 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3017 {
3018         bnxt_free_vnic_attributes(bp);
3019         bnxt_free_tx_rings(bp);
3020         bnxt_free_rx_rings(bp);
3021         bnxt_free_cp_rings(bp);
3022         bnxt_free_ntp_fltrs(bp, irq_re_init);
3023         if (irq_re_init) {
3024                 bnxt_free_stats(bp);
3025                 bnxt_free_ring_grps(bp);
3026                 bnxt_free_vnics(bp);
3027                 kfree(bp->tx_ring_map);
3028                 bp->tx_ring_map = NULL;
3029                 kfree(bp->tx_ring);
3030                 bp->tx_ring = NULL;
3031                 kfree(bp->rx_ring);
3032                 bp->rx_ring = NULL;
3033                 kfree(bp->bnapi);
3034                 bp->bnapi = NULL;
3035         } else {
3036                 bnxt_clear_ring_indices(bp);
3037         }
3038 }
3039
3040 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3041 {
3042         int i, j, rc, size, arr_size;
3043         void *bnapi;
3044
3045         if (irq_re_init) {
3046                 /* Allocate bnapi mem pointer array and mem block for
3047                  * all queues
3048                  */
3049                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3050                                 bp->cp_nr_rings);
3051                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3052                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3053                 if (!bnapi)
3054                         return -ENOMEM;
3055
3056                 bp->bnapi = bnapi;
3057                 bnapi += arr_size;
3058                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3059                         bp->bnapi[i] = bnapi;
3060                         bp->bnapi[i]->index = i;
3061                         bp->bnapi[i]->bp = bp;
3062                 }
3063
3064                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3065                                       sizeof(struct bnxt_rx_ring_info),
3066                                       GFP_KERNEL);
3067                 if (!bp->rx_ring)
3068                         return -ENOMEM;
3069
3070                 for (i = 0; i < bp->rx_nr_rings; i++) {
3071                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3072                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3073                 }
3074
3075                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3076                                       sizeof(struct bnxt_tx_ring_info),
3077                                       GFP_KERNEL);
3078                 if (!bp->tx_ring)
3079                         return -ENOMEM;
3080
3081                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3082                                           GFP_KERNEL);
3083
3084                 if (!bp->tx_ring_map)
3085                         return -ENOMEM;
3086
3087                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3088                         j = 0;
3089                 else
3090                         j = bp->rx_nr_rings;
3091
3092                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3093                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3094                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3095                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3096                         if (i >= bp->tx_nr_rings_xdp) {
3097                                 bp->tx_ring[i].txq_index = i -
3098                                         bp->tx_nr_rings_xdp;
3099                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3100                         } else {
3101                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3102                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3103                         }
3104                 }
3105
3106                 rc = bnxt_alloc_stats(bp);
3107                 if (rc)
3108                         goto alloc_mem_err;
3109
3110                 rc = bnxt_alloc_ntp_fltrs(bp);
3111                 if (rc)
3112                         goto alloc_mem_err;
3113
3114                 rc = bnxt_alloc_vnics(bp);
3115                 if (rc)
3116                         goto alloc_mem_err;
3117         }
3118
3119         bnxt_init_ring_struct(bp);
3120
3121         rc = bnxt_alloc_rx_rings(bp);
3122         if (rc)
3123                 goto alloc_mem_err;
3124
3125         rc = bnxt_alloc_tx_rings(bp);
3126         if (rc)
3127                 goto alloc_mem_err;
3128
3129         rc = bnxt_alloc_cp_rings(bp);
3130         if (rc)
3131                 goto alloc_mem_err;
3132
3133         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3134                                   BNXT_VNIC_UCAST_FLAG;
3135         rc = bnxt_alloc_vnic_attributes(bp);
3136         if (rc)
3137                 goto alloc_mem_err;
3138         return 0;
3139
3140 alloc_mem_err:
3141         bnxt_free_mem(bp, true);
3142         return rc;
3143 }
3144
3145 static void bnxt_disable_int(struct bnxt *bp)
3146 {
3147         int i;
3148
3149         if (!bp->bnapi)
3150                 return;
3151
3152         for (i = 0; i < bp->cp_nr_rings; i++) {
3153                 struct bnxt_napi *bnapi = bp->bnapi[i];
3154                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3155                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3156
3157                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3158                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3159         }
3160 }
3161
3162 static void bnxt_disable_int_sync(struct bnxt *bp)
3163 {
3164         int i;
3165
3166         atomic_inc(&bp->intr_sem);
3167
3168         bnxt_disable_int(bp);
3169         for (i = 0; i < bp->cp_nr_rings; i++)
3170                 synchronize_irq(bp->irq_tbl[i].vector);
3171 }
3172
3173 static void bnxt_enable_int(struct bnxt *bp)
3174 {
3175         int i;
3176
3177         atomic_set(&bp->intr_sem, 0);
3178         for (i = 0; i < bp->cp_nr_rings; i++) {
3179                 struct bnxt_napi *bnapi = bp->bnapi[i];
3180                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3181
3182                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3183         }
3184 }
3185
3186 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3187                             u16 cmpl_ring, u16 target_id)
3188 {
3189         struct input *req = request;
3190
3191         req->req_type = cpu_to_le16(req_type);
3192         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3193         req->target_id = cpu_to_le16(target_id);
3194         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3195 }
3196
3197 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3198                                  int timeout, bool silent)
3199 {
3200         int i, intr_process, rc, tmo_count;
3201         struct input *req = msg;
3202         u32 *data = msg;
3203         __le32 *resp_len, *valid;
3204         u16 cp_ring_id, len = 0;
3205         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3206
3207         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3208         memset(resp, 0, PAGE_SIZE);
3209         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3210         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3211
3212         /* Write request msg to hwrm channel */
3213         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3214
3215         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3216                 writel(0, bp->bar0 + i);
3217
3218         /* currently supports only one outstanding message */
3219         if (intr_process)
3220                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3221
3222         /* Ring channel doorbell */
3223         writel(1, bp->bar0 + 0x100);
3224
3225         if (!timeout)
3226                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3227
3228         i = 0;
3229         tmo_count = timeout * 40;
3230         if (intr_process) {
3231                 /* Wait until hwrm response cmpl interrupt is processed */
3232                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3233                        i++ < tmo_count) {
3234                         usleep_range(25, 40);
3235                 }
3236
3237                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3238                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3239                                    le16_to_cpu(req->req_type));
3240                         return -1;
3241                 }
3242         } else {
3243                 /* Check if response len is updated */
3244                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3245                 for (i = 0; i < tmo_count; i++) {
3246                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3247                               HWRM_RESP_LEN_SFT;
3248                         if (len)
3249                                 break;
3250                         usleep_range(25, 40);
3251                 }
3252
3253                 if (i >= tmo_count) {
3254                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3255                                    timeout, le16_to_cpu(req->req_type),
3256                                    le16_to_cpu(req->seq_id), len);
3257                         return -1;
3258                 }
3259
3260                 /* Last word of resp contains valid bit */
3261                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3262                 for (i = 0; i < 5; i++) {
3263                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3264                                 break;
3265                         udelay(1);
3266                 }
3267
3268                 if (i >= 5) {
3269                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3270                                    timeout, le16_to_cpu(req->req_type),
3271                                    le16_to_cpu(req->seq_id), len, *valid);
3272                         return -1;
3273                 }
3274         }
3275
3276         rc = le16_to_cpu(resp->error_code);
3277         if (rc && !silent)
3278                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3279                            le16_to_cpu(resp->req_type),
3280                            le16_to_cpu(resp->seq_id), rc);
3281         return rc;
3282 }
3283
3284 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3285 {
3286         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3287 }
3288
3289 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3290 {
3291         int rc;
3292
3293         mutex_lock(&bp->hwrm_cmd_lock);
3294         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3295         mutex_unlock(&bp->hwrm_cmd_lock);
3296         return rc;
3297 }
3298
3299 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3300                              int timeout)
3301 {
3302         int rc;
3303
3304         mutex_lock(&bp->hwrm_cmd_lock);
3305         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3306         mutex_unlock(&bp->hwrm_cmd_lock);
3307         return rc;
3308 }
3309
3310 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3311                                      int bmap_size)
3312 {
3313         struct hwrm_func_drv_rgtr_input req = {0};
3314         DECLARE_BITMAP(async_events_bmap, 256);
3315         u32 *events = (u32 *)async_events_bmap;
3316         int i;
3317
3318         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3319
3320         req.enables =
3321                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3322
3323         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3324         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3325                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3326
3327         if (bmap && bmap_size) {
3328                 for (i = 0; i < bmap_size; i++) {
3329                         if (test_bit(i, bmap))
3330                                 __set_bit(i, async_events_bmap);
3331                 }
3332         }
3333
3334         for (i = 0; i < 8; i++)
3335                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3336
3337         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3338 }
3339
3340 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3341 {
3342         struct hwrm_func_drv_rgtr_input req = {0};
3343
3344         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3345
3346         req.enables =
3347                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3348                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3349
3350         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3351         req.ver_maj = DRV_VER_MAJ;
3352         req.ver_min = DRV_VER_MIN;
3353         req.ver_upd = DRV_VER_UPD;
3354
3355         if (BNXT_PF(bp)) {
3356                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3357                 u32 *data = (u32 *)vf_req_snif_bmap;
3358                 int i;
3359
3360                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3361                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3362                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3363
3364                 for (i = 0; i < 8; i++)
3365                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3366
3367                 req.enables |=
3368                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3369         }
3370
3371         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3372 }
3373
3374 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3375 {
3376         struct hwrm_func_drv_unrgtr_input req = {0};
3377
3378         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3379         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3380 }
3381
3382 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3383 {
3384         u32 rc = 0;
3385         struct hwrm_tunnel_dst_port_free_input req = {0};
3386
3387         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3388         req.tunnel_type = tunnel_type;
3389
3390         switch (tunnel_type) {
3391         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3392                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3393                 break;
3394         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3395                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3396                 break;
3397         default:
3398                 break;
3399         }
3400
3401         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3402         if (rc)
3403                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3404                            rc);
3405         return rc;
3406 }
3407
3408 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3409                                            u8 tunnel_type)
3410 {
3411         u32 rc = 0;
3412         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3413         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3414
3415         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3416
3417         req.tunnel_type = tunnel_type;
3418         req.tunnel_dst_port_val = port;
3419
3420         mutex_lock(&bp->hwrm_cmd_lock);
3421         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3422         if (rc) {
3423                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3424                            rc);
3425                 goto err_out;
3426         }
3427
3428         switch (tunnel_type) {
3429         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3430                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3431                 break;
3432         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3433                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3434                 break;
3435         default:
3436                 break;
3437         }
3438
3439 err_out:
3440         mutex_unlock(&bp->hwrm_cmd_lock);
3441         return rc;
3442 }
3443
3444 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3445 {
3446         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3447         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3448
3449         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3450         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3451
3452         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3453         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3454         req.mask = cpu_to_le32(vnic->rx_mask);
3455         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3456 }
3457
3458 #ifdef CONFIG_RFS_ACCEL
3459 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3460                                             struct bnxt_ntuple_filter *fltr)
3461 {
3462         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3463
3464         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3465         req.ntuple_filter_id = fltr->filter_id;
3466         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3467 }
3468
3469 #define BNXT_NTP_FLTR_FLAGS                                     \
3470         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3471          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3472          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3473          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3474          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3475          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3476          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3477          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3478          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3479          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3480          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3481          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3482          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3483          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3484
3485 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3486                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3487
3488 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3489                                              struct bnxt_ntuple_filter *fltr)
3490 {
3491         int rc = 0;
3492         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3493         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3494                 bp->hwrm_cmd_resp_addr;
3495         struct flow_keys *keys = &fltr->fkeys;
3496         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3497
3498         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3499         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3500
3501         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3502
3503         req.ethertype = htons(ETH_P_IP);
3504         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3505         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3506         req.ip_protocol = keys->basic.ip_proto;
3507
3508         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3509                 int i;
3510
3511                 req.ethertype = htons(ETH_P_IPV6);
3512                 req.ip_addr_type =
3513                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3514                 *(struct in6_addr *)&req.src_ipaddr[0] =
3515                         keys->addrs.v6addrs.src;
3516                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3517                         keys->addrs.v6addrs.dst;
3518                 for (i = 0; i < 4; i++) {
3519                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3520                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3521                 }
3522         } else {
3523                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3524                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3525                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3526                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3527         }
3528         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3529                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3530                 req.tunnel_type =
3531                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3532         }
3533
3534         req.src_port = keys->ports.src;
3535         req.src_port_mask = cpu_to_be16(0xffff);
3536         req.dst_port = keys->ports.dst;
3537         req.dst_port_mask = cpu_to_be16(0xffff);
3538
3539         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3540         mutex_lock(&bp->hwrm_cmd_lock);
3541         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3542         if (!rc)
3543                 fltr->filter_id = resp->ntuple_filter_id;
3544         mutex_unlock(&bp->hwrm_cmd_lock);
3545         return rc;
3546 }
3547 #endif
3548
3549 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3550                                      u8 *mac_addr)
3551 {
3552         u32 rc = 0;
3553         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3554         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3555
3556         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3557         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3558         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3559                 req.flags |=
3560                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3561         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3562         req.enables =
3563                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3564                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3565                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3566         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3567         req.l2_addr_mask[0] = 0xff;
3568         req.l2_addr_mask[1] = 0xff;
3569         req.l2_addr_mask[2] = 0xff;
3570         req.l2_addr_mask[3] = 0xff;
3571         req.l2_addr_mask[4] = 0xff;
3572         req.l2_addr_mask[5] = 0xff;
3573
3574         mutex_lock(&bp->hwrm_cmd_lock);
3575         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3576         if (!rc)
3577                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3578                                                         resp->l2_filter_id;
3579         mutex_unlock(&bp->hwrm_cmd_lock);
3580         return rc;
3581 }
3582
3583 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3584 {
3585         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3586         int rc = 0;
3587
3588         /* Any associated ntuple filters will also be cleared by firmware. */
3589         mutex_lock(&bp->hwrm_cmd_lock);
3590         for (i = 0; i < num_of_vnics; i++) {
3591                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3592
3593                 for (j = 0; j < vnic->uc_filter_count; j++) {
3594                         struct hwrm_cfa_l2_filter_free_input req = {0};
3595
3596                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3597                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3598
3599                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3600
3601                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3602                                                 HWRM_CMD_TIMEOUT);
3603                 }
3604                 vnic->uc_filter_count = 0;
3605         }
3606         mutex_unlock(&bp->hwrm_cmd_lock);
3607
3608         return rc;
3609 }
3610
3611 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3612 {
3613         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3614         struct hwrm_vnic_tpa_cfg_input req = {0};
3615
3616         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3617
3618         if (tpa_flags) {
3619                 u16 mss = bp->dev->mtu - 40;
3620                 u32 nsegs, n, segs = 0, flags;
3621
3622                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3623                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3624                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3625                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3626                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3627                 if (tpa_flags & BNXT_FLAG_GRO)
3628                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3629
3630                 req.flags = cpu_to_le32(flags);
3631
3632                 req.enables =
3633                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3634                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3635                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3636
3637                 /* Number of segs are log2 units, and first packet is not
3638                  * included as part of this units.
3639                  */
3640                 if (mss <= BNXT_RX_PAGE_SIZE) {
3641                         n = BNXT_RX_PAGE_SIZE / mss;
3642                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3643                 } else {
3644                         n = mss / BNXT_RX_PAGE_SIZE;
3645                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3646                                 n++;
3647                         nsegs = (MAX_SKB_FRAGS - n) / n;
3648                 }
3649
3650                 segs = ilog2(nsegs);
3651                 req.max_agg_segs = cpu_to_le16(segs);
3652                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3653
3654                 req.min_agg_len = cpu_to_le32(512);
3655         }
3656         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3657
3658         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3659 }
3660
3661 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3662 {
3663         u32 i, j, max_rings;
3664         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3665         struct hwrm_vnic_rss_cfg_input req = {0};
3666
3667         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3668                 return 0;
3669
3670         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3671         if (set_rss) {
3672                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3673                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3674                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3675                                 max_rings = bp->rx_nr_rings - 1;
3676                         else
3677                                 max_rings = bp->rx_nr_rings;
3678                 } else {
3679                         max_rings = 1;
3680                 }
3681
3682                 /* Fill the RSS indirection table with ring group ids */
3683                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3684                         if (j == max_rings)
3685                                 j = 0;
3686                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3687                 }
3688
3689                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3690                 req.hash_key_tbl_addr =
3691                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3692         }
3693         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3694         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3695 }
3696
3697 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3698 {
3699         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3700         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3701
3702         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3703         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3704                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3705                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3706         req.enables =
3707                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3708                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3709         /* thresholds not implemented in firmware yet */
3710         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3711         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3712         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3713         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3714 }
3715
3716 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3717                                         u16 ctx_idx)
3718 {
3719         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3720
3721         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3722         req.rss_cos_lb_ctx_id =
3723                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3724
3725         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3726         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3727 }
3728
3729 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3730 {
3731         int i, j;
3732
3733         for (i = 0; i < bp->nr_vnics; i++) {
3734                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3735
3736                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3737                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3738                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3739                 }
3740         }
3741         bp->rsscos_nr_ctxs = 0;
3742 }
3743
3744 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3745 {
3746         int rc;
3747         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3748         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3749                                                 bp->hwrm_cmd_resp_addr;
3750
3751         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3752                                -1);
3753
3754         mutex_lock(&bp->hwrm_cmd_lock);
3755         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3756         if (!rc)
3757                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3758                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3759         mutex_unlock(&bp->hwrm_cmd_lock);
3760
3761         return rc;
3762 }
3763
3764 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3765 {
3766         unsigned int ring = 0, grp_idx;
3767         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3768         struct hwrm_vnic_cfg_input req = {0};
3769         u16 def_vlan = 0;
3770
3771         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3772
3773         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3774         /* Only RSS support for now TBD: COS & LB */
3775         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3776                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3777                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3778                                            VNIC_CFG_REQ_ENABLES_MRU);
3779         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3780                 req.rss_rule =
3781                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3782                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3783                                            VNIC_CFG_REQ_ENABLES_MRU);
3784                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3785         } else {
3786                 req.rss_rule = cpu_to_le16(0xffff);
3787         }
3788
3789         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3790             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3791                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3792                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3793         } else {
3794                 req.cos_rule = cpu_to_le16(0xffff);
3795         }
3796
3797         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3798                 ring = 0;
3799         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3800                 ring = vnic_id - 1;
3801         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3802                 ring = bp->rx_nr_rings - 1;
3803
3804         grp_idx = bp->rx_ring[ring].bnapi->index;
3805         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3806         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3807
3808         req.lb_rule = cpu_to_le16(0xffff);
3809         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3810                               VLAN_HLEN);
3811
3812 #ifdef CONFIG_BNXT_SRIOV
3813         if (BNXT_VF(bp))
3814                 def_vlan = bp->vf.vlan;
3815 #endif
3816         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3817                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3818         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3819                 req.flags |=
3820                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
3821
3822         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3823 }
3824
3825 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3826 {
3827         u32 rc = 0;
3828
3829         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3830                 struct hwrm_vnic_free_input req = {0};
3831
3832                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3833                 req.vnic_id =
3834                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3835
3836                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3837                 if (rc)
3838                         return rc;
3839                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3840         }
3841         return rc;
3842 }
3843
3844 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3845 {
3846         u16 i;
3847
3848         for (i = 0; i < bp->nr_vnics; i++)
3849                 bnxt_hwrm_vnic_free_one(bp, i);
3850 }
3851
3852 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3853                                 unsigned int start_rx_ring_idx,
3854                                 unsigned int nr_rings)
3855 {
3856         int rc = 0;
3857         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3858         struct hwrm_vnic_alloc_input req = {0};
3859         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3860
3861         /* map ring groups to this vnic */
3862         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3863                 grp_idx = bp->rx_ring[i].bnapi->index;
3864                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3865                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3866                                    j, nr_rings);
3867                         break;
3868                 }
3869                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3870                                         bp->grp_info[grp_idx].fw_grp_id;
3871         }
3872
3873         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3874         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3875         if (vnic_id == 0)
3876                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3877
3878         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3879
3880         mutex_lock(&bp->hwrm_cmd_lock);
3881         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3882         if (!rc)
3883                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3884         mutex_unlock(&bp->hwrm_cmd_lock);
3885         return rc;
3886 }
3887
3888 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3889 {
3890         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3891         struct hwrm_vnic_qcaps_input req = {0};
3892         int rc;
3893
3894         if (bp->hwrm_spec_code < 0x10600)
3895                 return 0;
3896
3897         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3898         mutex_lock(&bp->hwrm_cmd_lock);
3899         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3900         if (!rc) {
3901                 if (resp->flags &
3902                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3903                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3904         }
3905         mutex_unlock(&bp->hwrm_cmd_lock);
3906         return rc;
3907 }
3908
3909 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3910 {
3911         u16 i;
3912         u32 rc = 0;
3913
3914         mutex_lock(&bp->hwrm_cmd_lock);
3915         for (i = 0; i < bp->rx_nr_rings; i++) {
3916                 struct hwrm_ring_grp_alloc_input req = {0};
3917                 struct hwrm_ring_grp_alloc_output *resp =
3918                                         bp->hwrm_cmd_resp_addr;
3919                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3920
3921                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3922
3923                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3924                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3925                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3926                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3927
3928                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3929                                         HWRM_CMD_TIMEOUT);
3930                 if (rc)
3931                         break;
3932
3933                 bp->grp_info[grp_idx].fw_grp_id =
3934                         le32_to_cpu(resp->ring_group_id);
3935         }
3936         mutex_unlock(&bp->hwrm_cmd_lock);
3937         return rc;
3938 }
3939
3940 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3941 {
3942         u16 i;
3943         u32 rc = 0;
3944         struct hwrm_ring_grp_free_input req = {0};
3945
3946         if (!bp->grp_info)
3947                 return 0;
3948
3949         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3950
3951         mutex_lock(&bp->hwrm_cmd_lock);
3952         for (i = 0; i < bp->cp_nr_rings; i++) {
3953                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3954                         continue;
3955                 req.ring_group_id =
3956                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3957
3958                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3959                                         HWRM_CMD_TIMEOUT);
3960                 if (rc)
3961                         break;
3962                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3963         }
3964         mutex_unlock(&bp->hwrm_cmd_lock);
3965         return rc;
3966 }
3967
3968 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3969                                     struct bnxt_ring_struct *ring,
3970                                     u32 ring_type, u32 map_index,
3971                                     u32 stats_ctx_id)
3972 {
3973         int rc = 0, err = 0;
3974         struct hwrm_ring_alloc_input req = {0};
3975         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3976         u16 ring_id;
3977
3978         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3979
3980         req.enables = 0;
3981         if (ring->nr_pages > 1) {
3982                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3983                 /* Page size is in log2 units */
3984                 req.page_size = BNXT_PAGE_SHIFT;
3985                 req.page_tbl_depth = 1;
3986         } else {
3987                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3988         }
3989         req.fbo = 0;
3990         /* Association of ring index with doorbell index and MSIX number */
3991         req.logical_id = cpu_to_le16(map_index);
3992
3993         switch (ring_type) {
3994         case HWRM_RING_ALLOC_TX:
3995                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3996                 /* Association of transmit ring with completion ring */
3997                 req.cmpl_ring_id =
3998                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3999                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4000                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4001                 req.queue_id = cpu_to_le16(ring->queue_id);
4002                 break;
4003         case HWRM_RING_ALLOC_RX:
4004                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4005                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4006                 break;
4007         case HWRM_RING_ALLOC_AGG:
4008                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4009                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4010                 break;
4011         case HWRM_RING_ALLOC_CMPL:
4012                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4013                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4014                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4015                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4016                 break;
4017         default:
4018                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4019                            ring_type);
4020                 return -1;
4021         }
4022
4023         mutex_lock(&bp->hwrm_cmd_lock);
4024         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4025         err = le16_to_cpu(resp->error_code);
4026         ring_id = le16_to_cpu(resp->ring_id);
4027         mutex_unlock(&bp->hwrm_cmd_lock);
4028
4029         if (rc || err) {
4030                 switch (ring_type) {
4031                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4032                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4033                                    rc, err);
4034                         return -1;
4035
4036                 case RING_FREE_REQ_RING_TYPE_RX:
4037                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4038                                    rc, err);
4039                         return -1;
4040
4041                 case RING_FREE_REQ_RING_TYPE_TX:
4042                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4043                                    rc, err);
4044                         return -1;
4045
4046                 default:
4047                         netdev_err(bp->dev, "Invalid ring\n");
4048                         return -1;
4049                 }
4050         }
4051         ring->fw_ring_id = ring_id;
4052         return rc;
4053 }
4054
4055 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4056 {
4057         int rc;
4058
4059         if (BNXT_PF(bp)) {
4060                 struct hwrm_func_cfg_input req = {0};
4061
4062                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4063                 req.fid = cpu_to_le16(0xffff);
4064                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4065                 req.async_event_cr = cpu_to_le16(idx);
4066                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4067         } else {
4068                 struct hwrm_func_vf_cfg_input req = {0};
4069
4070                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4071                 req.enables =
4072                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4073                 req.async_event_cr = cpu_to_le16(idx);
4074                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4075         }
4076         return rc;
4077 }
4078
4079 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4080 {
4081         int i, rc = 0;
4082
4083         for (i = 0; i < bp->cp_nr_rings; i++) {
4084                 struct bnxt_napi *bnapi = bp->bnapi[i];
4085                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4086                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4087
4088                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4089                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4090                                               INVALID_STATS_CTX_ID);
4091                 if (rc)
4092                         goto err_out;
4093                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4094                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4095
4096                 if (!i) {
4097                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4098                         if (rc)
4099                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4100                 }
4101         }
4102
4103         for (i = 0; i < bp->tx_nr_rings; i++) {
4104                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4105                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4106                 u32 map_idx = txr->bnapi->index;
4107                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4108
4109                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4110                                               map_idx, fw_stats_ctx);
4111                 if (rc)
4112                         goto err_out;
4113                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4114         }
4115
4116         for (i = 0; i < bp->rx_nr_rings; i++) {
4117                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4118                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4119                 u32 map_idx = rxr->bnapi->index;
4120
4121                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4122                                               map_idx, INVALID_STATS_CTX_ID);
4123                 if (rc)
4124                         goto err_out;
4125                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4126                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4127                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4128         }
4129
4130         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4131                 for (i = 0; i < bp->rx_nr_rings; i++) {
4132                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4133                         struct bnxt_ring_struct *ring =
4134                                                 &rxr->rx_agg_ring_struct;
4135                         u32 grp_idx = rxr->bnapi->index;
4136                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4137
4138                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4139                                                       HWRM_RING_ALLOC_AGG,
4140                                                       map_idx,
4141                                                       INVALID_STATS_CTX_ID);
4142                         if (rc)
4143                                 goto err_out;
4144
4145                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4146                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4147                                rxr->rx_agg_doorbell);
4148                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4149                 }
4150         }
4151 err_out:
4152         return rc;
4153 }
4154
4155 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4156                                    struct bnxt_ring_struct *ring,
4157                                    u32 ring_type, int cmpl_ring_id)
4158 {
4159         int rc;
4160         struct hwrm_ring_free_input req = {0};
4161         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4162         u16 error_code;
4163
4164         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4165         req.ring_type = ring_type;
4166         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4167
4168         mutex_lock(&bp->hwrm_cmd_lock);
4169         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4170         error_code = le16_to_cpu(resp->error_code);
4171         mutex_unlock(&bp->hwrm_cmd_lock);
4172
4173         if (rc || error_code) {
4174                 switch (ring_type) {
4175                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4176                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4177                                    rc);
4178                         return rc;
4179                 case RING_FREE_REQ_RING_TYPE_RX:
4180                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4181                                    rc);
4182                         return rc;
4183                 case RING_FREE_REQ_RING_TYPE_TX:
4184                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4185                                    rc);
4186                         return rc;
4187                 default:
4188                         netdev_err(bp->dev, "Invalid ring\n");
4189                         return -1;
4190                 }
4191         }
4192         return 0;
4193 }
4194
4195 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4196 {
4197         int i;
4198
4199         if (!bp->bnapi)
4200                 return;
4201
4202         for (i = 0; i < bp->tx_nr_rings; i++) {
4203                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4204                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4205                 u32 grp_idx = txr->bnapi->index;
4206                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4207
4208                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4209                         hwrm_ring_free_send_msg(bp, ring,
4210                                                 RING_FREE_REQ_RING_TYPE_TX,
4211                                                 close_path ? cmpl_ring_id :
4212                                                 INVALID_HW_RING_ID);
4213                         ring->fw_ring_id = INVALID_HW_RING_ID;
4214                 }
4215         }
4216
4217         for (i = 0; i < bp->rx_nr_rings; i++) {
4218                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4219                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4220                 u32 grp_idx = rxr->bnapi->index;
4221                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4222
4223                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4224                         hwrm_ring_free_send_msg(bp, ring,
4225                                                 RING_FREE_REQ_RING_TYPE_RX,
4226                                                 close_path ? cmpl_ring_id :
4227                                                 INVALID_HW_RING_ID);
4228                         ring->fw_ring_id = INVALID_HW_RING_ID;
4229                         bp->grp_info[grp_idx].rx_fw_ring_id =
4230                                 INVALID_HW_RING_ID;
4231                 }
4232         }
4233
4234         for (i = 0; i < bp->rx_nr_rings; i++) {
4235                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4236                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4237                 u32 grp_idx = rxr->bnapi->index;
4238                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4239
4240                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4241                         hwrm_ring_free_send_msg(bp, ring,
4242                                                 RING_FREE_REQ_RING_TYPE_RX,
4243                                                 close_path ? cmpl_ring_id :
4244                                                 INVALID_HW_RING_ID);
4245                         ring->fw_ring_id = INVALID_HW_RING_ID;
4246                         bp->grp_info[grp_idx].agg_fw_ring_id =
4247                                 INVALID_HW_RING_ID;
4248                 }
4249         }
4250
4251         /* The completion rings are about to be freed.  After that the
4252          * IRQ doorbell will not work anymore.  So we need to disable
4253          * IRQ here.
4254          */
4255         bnxt_disable_int_sync(bp);
4256
4257         for (i = 0; i < bp->cp_nr_rings; i++) {
4258                 struct bnxt_napi *bnapi = bp->bnapi[i];
4259                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4260                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4261
4262                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4263                         hwrm_ring_free_send_msg(bp, ring,
4264                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4265                                                 INVALID_HW_RING_ID);
4266                         ring->fw_ring_id = INVALID_HW_RING_ID;
4267                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4268                 }
4269         }
4270 }
4271
4272 /* Caller must hold bp->hwrm_cmd_lock */
4273 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4274 {
4275         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4276         struct hwrm_func_qcfg_input req = {0};
4277         int rc;
4278
4279         if (bp->hwrm_spec_code < 0x10601)
4280                 return 0;
4281
4282         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4283         req.fid = cpu_to_le16(fid);
4284         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4285         if (!rc)
4286                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4287
4288         return rc;
4289 }
4290
4291 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4292 {
4293         struct hwrm_func_cfg_input req = {0};
4294         int rc;
4295
4296         if (bp->hwrm_spec_code < 0x10601)
4297                 return 0;
4298
4299         if (BNXT_VF(bp))
4300                 return 0;
4301
4302         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4303         req.fid = cpu_to_le16(0xffff);
4304         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4305         req.num_tx_rings = cpu_to_le16(*tx_rings);
4306         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4307         if (rc)
4308                 return rc;
4309
4310         mutex_lock(&bp->hwrm_cmd_lock);
4311         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4312         mutex_unlock(&bp->hwrm_cmd_lock);
4313         return rc;
4314 }
4315
4316 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4317         u32 buf_tmrs, u16 flags,
4318         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4319 {
4320         req->flags = cpu_to_le16(flags);
4321         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4322         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4323         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4324         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4325         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4326         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4327         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4328         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4329 }
4330
4331 int bnxt_hwrm_set_coal(struct bnxt *bp)
4332 {
4333         int i, rc = 0;
4334         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4335                                                            req_tx = {0}, *req;
4336         u16 max_buf, max_buf_irq;
4337         u16 buf_tmr, buf_tmr_irq;
4338         u32 flags;
4339
4340         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4341                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4342         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4343                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4344
4345         /* Each rx completion (2 records) should be DMAed immediately.
4346          * DMA 1/4 of the completion buffers at a time.
4347          */
4348         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4349         /* max_buf must not be zero */
4350         max_buf = clamp_t(u16, max_buf, 1, 63);
4351         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4352         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4353         /* buf timer set to 1/4 of interrupt timer */
4354         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4355         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4356         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4357
4358         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4359
4360         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4361          * if coal_ticks is less than 25 us.
4362          */
4363         if (bp->rx_coal_ticks < 25)
4364                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4365
4366         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4367                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4368
4369         /* max_buf must not be zero */
4370         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4371         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4372         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4373         /* buf timer set to 1/4 of interrupt timer */
4374         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4375         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4376         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4377
4378         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4379         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4380                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4381
4382         mutex_lock(&bp->hwrm_cmd_lock);
4383         for (i = 0; i < bp->cp_nr_rings; i++) {
4384                 struct bnxt_napi *bnapi = bp->bnapi[i];
4385
4386                 req = &req_rx;
4387                 if (!bnapi->rx_ring)
4388                         req = &req_tx;
4389                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4390
4391                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4392                                         HWRM_CMD_TIMEOUT);
4393                 if (rc)
4394                         break;
4395         }
4396         mutex_unlock(&bp->hwrm_cmd_lock);
4397         return rc;
4398 }
4399
4400 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4401 {
4402         int rc = 0, i;
4403         struct hwrm_stat_ctx_free_input req = {0};
4404
4405         if (!bp->bnapi)
4406                 return 0;
4407
4408         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4409                 return 0;
4410
4411         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4412
4413         mutex_lock(&bp->hwrm_cmd_lock);
4414         for (i = 0; i < bp->cp_nr_rings; i++) {
4415                 struct bnxt_napi *bnapi = bp->bnapi[i];
4416                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4417
4418                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4419                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4420
4421                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4422                                                 HWRM_CMD_TIMEOUT);
4423                         if (rc)
4424                                 break;
4425
4426                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4427                 }
4428         }
4429         mutex_unlock(&bp->hwrm_cmd_lock);
4430         return rc;
4431 }
4432
4433 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4434 {
4435         int rc = 0, i;
4436         struct hwrm_stat_ctx_alloc_input req = {0};
4437         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4438
4439         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4440                 return 0;
4441
4442         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4443
4444         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4445
4446         mutex_lock(&bp->hwrm_cmd_lock);
4447         for (i = 0; i < bp->cp_nr_rings; i++) {
4448                 struct bnxt_napi *bnapi = bp->bnapi[i];
4449                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4450
4451                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4452
4453                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4454                                         HWRM_CMD_TIMEOUT);
4455                 if (rc)
4456                         break;
4457
4458                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4459
4460                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4461         }
4462         mutex_unlock(&bp->hwrm_cmd_lock);
4463         return rc;
4464 }
4465
4466 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4467 {
4468         struct hwrm_func_qcfg_input req = {0};
4469         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4470         int rc;
4471
4472         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4473         req.fid = cpu_to_le16(0xffff);
4474         mutex_lock(&bp->hwrm_cmd_lock);
4475         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4476         if (rc)
4477                 goto func_qcfg_exit;
4478
4479 #ifdef CONFIG_BNXT_SRIOV
4480         if (BNXT_VF(bp)) {
4481                 struct bnxt_vf_info *vf = &bp->vf;
4482
4483                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4484         }
4485 #endif
4486         if (BNXT_PF(bp)) {
4487                 u16 flags = le16_to_cpu(resp->flags);
4488
4489                 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4490                              FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED))
4491                         bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4492                 if (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)
4493                         bp->flags |= BNXT_FLAG_MULTI_HOST;
4494         }
4495
4496         switch (resp->port_partition_type) {
4497         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4498         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4499         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4500                 bp->port_partition_type = resp->port_partition_type;
4501                 break;
4502         }
4503
4504 func_qcfg_exit:
4505         mutex_unlock(&bp->hwrm_cmd_lock);
4506         return rc;
4507 }
4508
4509 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4510 {
4511         int rc = 0;
4512         struct hwrm_func_qcaps_input req = {0};
4513         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4514
4515         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4516         req.fid = cpu_to_le16(0xffff);
4517
4518         mutex_lock(&bp->hwrm_cmd_lock);
4519         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4520         if (rc)
4521                 goto hwrm_func_qcaps_exit;
4522
4523         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4524                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4525         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4526                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4527
4528         bp->tx_push_thresh = 0;
4529         if (resp->flags &
4530             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4531                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4532
4533         if (BNXT_PF(bp)) {
4534                 struct bnxt_pf_info *pf = &bp->pf;
4535
4536                 pf->fw_fid = le16_to_cpu(resp->fid);
4537                 pf->port_id = le16_to_cpu(resp->port_id);
4538                 bp->dev->dev_port = pf->port_id;
4539                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4540                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4541                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4542                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4543                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4544                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4545                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4546                 if (!pf->max_hw_ring_grps)
4547                         pf->max_hw_ring_grps = pf->max_tx_rings;
4548                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4549                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4550                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4551                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4552                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4553                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4554                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4555                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4556                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4557                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4558                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4559                 if (resp->flags &
4560                     cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4561                         bp->flags |= BNXT_FLAG_WOL_CAP;
4562         } else {
4563 #ifdef CONFIG_BNXT_SRIOV
4564                 struct bnxt_vf_info *vf = &bp->vf;
4565
4566                 vf->fw_fid = le16_to_cpu(resp->fid);
4567
4568                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4569                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4570                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4571                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4572                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4573                 if (!vf->max_hw_ring_grps)
4574                         vf->max_hw_ring_grps = vf->max_tx_rings;
4575                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4576                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4577                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4578
4579                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4580                 mutex_unlock(&bp->hwrm_cmd_lock);
4581
4582                 if (is_valid_ether_addr(vf->mac_addr)) {
4583                         /* overwrite netdev dev_adr with admin VF MAC */
4584                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4585                 } else {
4586                         eth_hw_addr_random(bp->dev);
4587                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4588                 }
4589                 return rc;
4590 #endif
4591         }
4592
4593 hwrm_func_qcaps_exit:
4594         mutex_unlock(&bp->hwrm_cmd_lock);
4595         return rc;
4596 }
4597
4598 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4599 {
4600         struct hwrm_func_reset_input req = {0};
4601
4602         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4603         req.enables = 0;
4604
4605         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4606 }
4607
4608 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4609 {
4610         int rc = 0;
4611         struct hwrm_queue_qportcfg_input req = {0};
4612         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4613         u8 i, *qptr;
4614
4615         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4616
4617         mutex_lock(&bp->hwrm_cmd_lock);
4618         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4619         if (rc)
4620                 goto qportcfg_exit;
4621
4622         if (!resp->max_configurable_queues) {
4623                 rc = -EINVAL;
4624                 goto qportcfg_exit;
4625         }
4626         bp->max_tc = resp->max_configurable_queues;
4627         bp->max_lltc = resp->max_configurable_lossless_queues;
4628         if (bp->max_tc > BNXT_MAX_QUEUE)
4629                 bp->max_tc = BNXT_MAX_QUEUE;
4630
4631         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4632                 bp->max_tc = 1;
4633
4634         if (bp->max_lltc > bp->max_tc)
4635                 bp->max_lltc = bp->max_tc;
4636
4637         qptr = &resp->queue_id0;
4638         for (i = 0; i < bp->max_tc; i++) {
4639                 bp->q_info[i].queue_id = *qptr++;
4640                 bp->q_info[i].queue_profile = *qptr++;
4641         }
4642
4643 qportcfg_exit:
4644         mutex_unlock(&bp->hwrm_cmd_lock);
4645         return rc;
4646 }
4647
4648 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4649 {
4650         int rc;
4651         struct hwrm_ver_get_input req = {0};
4652         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4653
4654         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4655         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4656         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4657         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4658         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4659         mutex_lock(&bp->hwrm_cmd_lock);
4660         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4661         if (rc)
4662                 goto hwrm_ver_get_exit;
4663
4664         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4665
4666         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4667                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4668         if (resp->hwrm_intf_maj < 1) {
4669                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4670                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4671                             resp->hwrm_intf_upd);
4672                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4673         }
4674         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4675                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4676                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4677
4678         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4679         if (!bp->hwrm_cmd_timeout)
4680                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4681
4682         if (resp->hwrm_intf_maj >= 1)
4683                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4684
4685         bp->chip_num = le16_to_cpu(resp->chip_num);
4686         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4687             !resp->chip_metal)
4688                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4689
4690 hwrm_ver_get_exit:
4691         mutex_unlock(&bp->hwrm_cmd_lock);
4692         return rc;
4693 }
4694
4695 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4696 {
4697 #if IS_ENABLED(CONFIG_RTC_LIB)
4698         struct hwrm_fw_set_time_input req = {0};
4699         struct rtc_time tm;
4700         struct timeval tv;
4701
4702         if (bp->hwrm_spec_code < 0x10400)
4703                 return -EOPNOTSUPP;
4704
4705         do_gettimeofday(&tv);
4706         rtc_time_to_tm(tv.tv_sec, &tm);
4707         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4708         req.year = cpu_to_le16(1900 + tm.tm_year);
4709         req.month = 1 + tm.tm_mon;
4710         req.day = tm.tm_mday;
4711         req.hour = tm.tm_hour;
4712         req.minute = tm.tm_min;
4713         req.second = tm.tm_sec;
4714         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4715 #else
4716         return -EOPNOTSUPP;
4717 #endif
4718 }
4719
4720 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4721 {
4722         int rc;
4723         struct bnxt_pf_info *pf = &bp->pf;
4724         struct hwrm_port_qstats_input req = {0};
4725
4726         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4727                 return 0;
4728
4729         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4730         req.port_id = cpu_to_le16(pf->port_id);
4731         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4732         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4733         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4734         return rc;
4735 }
4736
4737 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4738 {
4739         if (bp->vxlan_port_cnt) {
4740                 bnxt_hwrm_tunnel_dst_port_free(
4741                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4742         }
4743         bp->vxlan_port_cnt = 0;
4744         if (bp->nge_port_cnt) {
4745                 bnxt_hwrm_tunnel_dst_port_free(
4746                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4747         }
4748         bp->nge_port_cnt = 0;
4749 }
4750
4751 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4752 {
4753         int rc, i;
4754         u32 tpa_flags = 0;
4755
4756         if (set_tpa)
4757                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4758         for (i = 0; i < bp->nr_vnics; i++) {
4759                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4760                 if (rc) {
4761                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4762                                    i, rc);
4763                         return rc;
4764                 }
4765         }
4766         return 0;
4767 }
4768
4769 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4770 {
4771         int i;
4772
4773         for (i = 0; i < bp->nr_vnics; i++)
4774                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4775 }
4776
4777 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4778                                     bool irq_re_init)
4779 {
4780         if (bp->vnic_info) {
4781                 bnxt_hwrm_clear_vnic_filter(bp);
4782                 /* clear all RSS setting before free vnic ctx */
4783                 bnxt_hwrm_clear_vnic_rss(bp);
4784                 bnxt_hwrm_vnic_ctx_free(bp);
4785                 /* before free the vnic, undo the vnic tpa settings */
4786                 if (bp->flags & BNXT_FLAG_TPA)
4787                         bnxt_set_tpa(bp, false);
4788                 bnxt_hwrm_vnic_free(bp);
4789         }
4790         bnxt_hwrm_ring_free(bp, close_path);
4791         bnxt_hwrm_ring_grp_free(bp);
4792         if (irq_re_init) {
4793                 bnxt_hwrm_stat_ctx_free(bp);
4794                 bnxt_hwrm_free_tunnel_ports(bp);
4795         }
4796 }
4797
4798 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4799 {
4800         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4801         int rc;
4802
4803         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4804                 goto skip_rss_ctx;
4805
4806         /* allocate context for vnic */
4807         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4808         if (rc) {
4809                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4810                            vnic_id, rc);
4811                 goto vnic_setup_err;
4812         }
4813         bp->rsscos_nr_ctxs++;
4814
4815         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4816                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4817                 if (rc) {
4818                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4819                                    vnic_id, rc);
4820                         goto vnic_setup_err;
4821                 }
4822                 bp->rsscos_nr_ctxs++;
4823         }
4824
4825 skip_rss_ctx:
4826         /* configure default vnic, ring grp */
4827         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4828         if (rc) {
4829                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4830                            vnic_id, rc);
4831                 goto vnic_setup_err;
4832         }
4833
4834         /* Enable RSS hashing on vnic */
4835         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4836         if (rc) {
4837                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4838                            vnic_id, rc);
4839                 goto vnic_setup_err;
4840         }
4841
4842         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4843                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4844                 if (rc) {
4845                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4846                                    vnic_id, rc);
4847                 }
4848         }
4849
4850 vnic_setup_err:
4851         return rc;
4852 }
4853
4854 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4855 {
4856 #ifdef CONFIG_RFS_ACCEL
4857         int i, rc = 0;
4858
4859         for (i = 0; i < bp->rx_nr_rings; i++) {
4860                 struct bnxt_vnic_info *vnic;
4861                 u16 vnic_id = i + 1;
4862                 u16 ring_id = i;
4863
4864                 if (vnic_id >= bp->nr_vnics)
4865                         break;
4866
4867                 vnic = &bp->vnic_info[vnic_id];
4868                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4869                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4870                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
4871                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4872                 if (rc) {
4873                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4874                                    vnic_id, rc);
4875                         break;
4876                 }
4877                 rc = bnxt_setup_vnic(bp, vnic_id);
4878                 if (rc)
4879                         break;
4880         }
4881         return rc;
4882 #else
4883         return 0;
4884 #endif
4885 }
4886
4887 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4888 static bool bnxt_promisc_ok(struct bnxt *bp)
4889 {
4890 #ifdef CONFIG_BNXT_SRIOV
4891         if (BNXT_VF(bp) && !bp->vf.vlan)
4892                 return false;
4893 #endif
4894         return true;
4895 }
4896
4897 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4898 {
4899         unsigned int rc = 0;
4900
4901         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4902         if (rc) {
4903                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4904                            rc);
4905                 return rc;
4906         }
4907
4908         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4909         if (rc) {
4910                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4911                            rc);
4912                 return rc;
4913         }
4914         return rc;
4915 }
4916
4917 static int bnxt_cfg_rx_mode(struct bnxt *);
4918 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4919
4920 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4921 {
4922         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4923         int rc = 0;
4924         unsigned int rx_nr_rings = bp->rx_nr_rings;
4925
4926         if (irq_re_init) {
4927                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4928                 if (rc) {
4929                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4930                                    rc);
4931                         goto err_out;
4932                 }
4933         }
4934
4935         rc = bnxt_hwrm_ring_alloc(bp);
4936         if (rc) {
4937                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4938                 goto err_out;
4939         }
4940
4941         rc = bnxt_hwrm_ring_grp_alloc(bp);
4942         if (rc) {
4943                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4944                 goto err_out;
4945         }
4946
4947         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4948                 rx_nr_rings--;
4949
4950         /* default vnic 0 */
4951         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4952         if (rc) {
4953                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4954                 goto err_out;
4955         }
4956
4957         rc = bnxt_setup_vnic(bp, 0);
4958         if (rc)
4959                 goto err_out;
4960
4961         if (bp->flags & BNXT_FLAG_RFS) {
4962                 rc = bnxt_alloc_rfs_vnics(bp);
4963                 if (rc)
4964                         goto err_out;
4965         }
4966
4967         if (bp->flags & BNXT_FLAG_TPA) {
4968                 rc = bnxt_set_tpa(bp, true);
4969                 if (rc)
4970                         goto err_out;
4971         }
4972
4973         if (BNXT_VF(bp))
4974                 bnxt_update_vf_mac(bp);
4975
4976         /* Filter for default vnic 0 */
4977         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4978         if (rc) {
4979                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4980                 goto err_out;
4981         }
4982         vnic->uc_filter_count = 1;
4983
4984         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4985
4986         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4987                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4988
4989         if (bp->dev->flags & IFF_ALLMULTI) {
4990                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4991                 vnic->mc_list_count = 0;
4992         } else {
4993                 u32 mask = 0;
4994
4995                 bnxt_mc_list_updated(bp, &mask);
4996                 vnic->rx_mask |= mask;
4997         }
4998
4999         rc = bnxt_cfg_rx_mode(bp);
5000         if (rc)
5001                 goto err_out;
5002
5003         rc = bnxt_hwrm_set_coal(bp);
5004         if (rc)
5005                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5006                                 rc);
5007
5008         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5009                 rc = bnxt_setup_nitroa0_vnic(bp);
5010                 if (rc)
5011                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5012                                    rc);
5013         }
5014
5015         if (BNXT_VF(bp)) {
5016                 bnxt_hwrm_func_qcfg(bp);
5017                 netdev_update_features(bp->dev);
5018         }
5019
5020         return 0;
5021
5022 err_out:
5023         bnxt_hwrm_resource_free(bp, 0, true);
5024
5025         return rc;
5026 }
5027
5028 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5029 {
5030         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5031         return 0;
5032 }
5033
5034 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5035 {
5036         bnxt_init_cp_rings(bp);
5037         bnxt_init_rx_rings(bp);
5038         bnxt_init_tx_rings(bp);
5039         bnxt_init_ring_grps(bp, irq_re_init);
5040         bnxt_init_vnics(bp);
5041
5042         return bnxt_init_chip(bp, irq_re_init);
5043 }
5044
5045 static int bnxt_set_real_num_queues(struct bnxt *bp)
5046 {
5047         int rc;
5048         struct net_device *dev = bp->dev;
5049
5050         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5051                                           bp->tx_nr_rings_xdp);
5052         if (rc)
5053                 return rc;
5054
5055         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5056         if (rc)
5057                 return rc;
5058
5059 #ifdef CONFIG_RFS_ACCEL
5060         if (bp->flags & BNXT_FLAG_RFS)
5061                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5062 #endif
5063
5064         return rc;
5065 }
5066
5067 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5068                            bool shared)
5069 {
5070         int _rx = *rx, _tx = *tx;
5071
5072         if (shared) {
5073                 *rx = min_t(int, _rx, max);
5074                 *tx = min_t(int, _tx, max);
5075         } else {
5076                 if (max < 2)
5077                         return -ENOMEM;
5078
5079                 while (_rx + _tx > max) {
5080                         if (_rx > _tx && _rx > 1)
5081                                 _rx--;
5082                         else if (_tx > 1)
5083                                 _tx--;
5084                 }
5085                 *rx = _rx;
5086                 *tx = _tx;
5087         }
5088         return 0;
5089 }
5090
5091 static void bnxt_setup_msix(struct bnxt *bp)
5092 {
5093         const int len = sizeof(bp->irq_tbl[0].name);
5094         struct net_device *dev = bp->dev;
5095         int tcs, i;
5096
5097         tcs = netdev_get_num_tc(dev);
5098         if (tcs > 1) {
5099                 int i, off, count;
5100
5101                 for (i = 0; i < tcs; i++) {
5102                         count = bp->tx_nr_rings_per_tc;
5103                         off = i * count;
5104                         netdev_set_tc_queue(dev, i, count, off);
5105                 }
5106         }
5107
5108         for (i = 0; i < bp->cp_nr_rings; i++) {
5109                 char *attr;
5110
5111                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5112                         attr = "TxRx";
5113                 else if (i < bp->rx_nr_rings)
5114                         attr = "rx";
5115                 else
5116                         attr = "tx";
5117
5118                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5119                          i);
5120                 bp->irq_tbl[i].handler = bnxt_msix;
5121         }
5122 }
5123
5124 static void bnxt_setup_inta(struct bnxt *bp)
5125 {
5126         const int len = sizeof(bp->irq_tbl[0].name);
5127
5128         if (netdev_get_num_tc(bp->dev))
5129                 netdev_reset_tc(bp->dev);
5130
5131         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5132                  0);
5133         bp->irq_tbl[0].handler = bnxt_inta;
5134 }
5135
5136 static int bnxt_setup_int_mode(struct bnxt *bp)
5137 {
5138         int rc;
5139
5140         if (bp->flags & BNXT_FLAG_USING_MSIX)
5141                 bnxt_setup_msix(bp);
5142         else
5143                 bnxt_setup_inta(bp);
5144
5145         rc = bnxt_set_real_num_queues(bp);
5146         return rc;
5147 }
5148
5149 #ifdef CONFIG_RFS_ACCEL
5150 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5151 {
5152 #if defined(CONFIG_BNXT_SRIOV)
5153         if (BNXT_VF(bp))
5154                 return bp->vf.max_rsscos_ctxs;
5155 #endif
5156         return bp->pf.max_rsscos_ctxs;
5157 }
5158
5159 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5160 {
5161 #if defined(CONFIG_BNXT_SRIOV)
5162         if (BNXT_VF(bp))
5163                 return bp->vf.max_vnics;
5164 #endif
5165         return bp->pf.max_vnics;
5166 }
5167 #endif
5168
5169 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5170 {
5171 #if defined(CONFIG_BNXT_SRIOV)
5172         if (BNXT_VF(bp))
5173                 return bp->vf.max_stat_ctxs;
5174 #endif
5175         return bp->pf.max_stat_ctxs;
5176 }
5177
5178 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5179 {
5180 #if defined(CONFIG_BNXT_SRIOV)
5181         if (BNXT_VF(bp))
5182                 bp->vf.max_stat_ctxs = max;
5183         else
5184 #endif
5185                 bp->pf.max_stat_ctxs = max;
5186 }
5187
5188 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5189 {
5190 #if defined(CONFIG_BNXT_SRIOV)
5191         if (BNXT_VF(bp))
5192                 return bp->vf.max_cp_rings;
5193 #endif
5194         return bp->pf.max_cp_rings;
5195 }
5196
5197 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5198 {
5199 #if defined(CONFIG_BNXT_SRIOV)
5200         if (BNXT_VF(bp))
5201                 bp->vf.max_cp_rings = max;
5202         else
5203 #endif
5204                 bp->pf.max_cp_rings = max;
5205 }
5206
5207 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5208 {
5209 #if defined(CONFIG_BNXT_SRIOV)
5210         if (BNXT_VF(bp))
5211                 return min_t(unsigned int, bp->vf.max_irqs,
5212                              bp->vf.max_cp_rings);
5213 #endif
5214         return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5215 }
5216
5217 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5218 {
5219 #if defined(CONFIG_BNXT_SRIOV)
5220         if (BNXT_VF(bp))
5221                 bp->vf.max_irqs = max_irqs;
5222         else
5223 #endif
5224                 bp->pf.max_irqs = max_irqs;
5225 }
5226
5227 static int bnxt_init_msix(struct bnxt *bp)
5228 {
5229         int i, total_vecs, rc = 0, min = 1;
5230         struct msix_entry *msix_ent;
5231
5232         total_vecs = bnxt_get_max_func_irqs(bp);
5233         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5234         if (!msix_ent)
5235                 return -ENOMEM;
5236
5237         for (i = 0; i < total_vecs; i++) {
5238                 msix_ent[i].entry = i;
5239                 msix_ent[i].vector = 0;
5240         }
5241
5242         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5243                 min = 2;
5244
5245         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5246         if (total_vecs < 0) {
5247                 rc = -ENODEV;
5248                 goto msix_setup_exit;
5249         }
5250
5251         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5252         if (bp->irq_tbl) {
5253                 for (i = 0; i < total_vecs; i++)
5254                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5255
5256                 bp->total_irqs = total_vecs;
5257                 /* Trim rings based upon num of vectors allocated */
5258                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5259                                      total_vecs, min == 1);
5260                 if (rc)
5261                         goto msix_setup_exit;
5262
5263                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5264                 bp->cp_nr_rings = (min == 1) ?
5265                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5266                                   bp->tx_nr_rings + bp->rx_nr_rings;
5267
5268         } else {
5269                 rc = -ENOMEM;
5270                 goto msix_setup_exit;
5271         }
5272         bp->flags |= BNXT_FLAG_USING_MSIX;
5273         kfree(msix_ent);
5274         return 0;
5275
5276 msix_setup_exit:
5277         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5278         kfree(bp->irq_tbl);
5279         bp->irq_tbl = NULL;
5280         pci_disable_msix(bp->pdev);
5281         kfree(msix_ent);
5282         return rc;
5283 }
5284
5285 static int bnxt_init_inta(struct bnxt *bp)
5286 {
5287         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5288         if (!bp->irq_tbl)
5289                 return -ENOMEM;
5290
5291         bp->total_irqs = 1;
5292         bp->rx_nr_rings = 1;
5293         bp->tx_nr_rings = 1;
5294         bp->cp_nr_rings = 1;
5295         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5296         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5297         bp->irq_tbl[0].vector = bp->pdev->irq;
5298         return 0;
5299 }
5300
5301 static int bnxt_init_int_mode(struct bnxt *bp)
5302 {
5303         int rc = 0;
5304
5305         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5306                 rc = bnxt_init_msix(bp);
5307
5308         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5309                 /* fallback to INTA */
5310                 rc = bnxt_init_inta(bp);
5311         }
5312         return rc;
5313 }
5314
5315 static void bnxt_clear_int_mode(struct bnxt *bp)
5316 {
5317         if (bp->flags & BNXT_FLAG_USING_MSIX)
5318                 pci_disable_msix(bp->pdev);
5319
5320         kfree(bp->irq_tbl);
5321         bp->irq_tbl = NULL;
5322         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5323 }
5324
5325 static void bnxt_free_irq(struct bnxt *bp)
5326 {
5327         struct bnxt_irq *irq;
5328         int i;
5329
5330 #ifdef CONFIG_RFS_ACCEL
5331         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5332         bp->dev->rx_cpu_rmap = NULL;
5333 #endif
5334         if (!bp->irq_tbl)
5335                 return;
5336
5337         for (i = 0; i < bp->cp_nr_rings; i++) {
5338                 irq = &bp->irq_tbl[i];
5339                 if (irq->requested)
5340                         free_irq(irq->vector, bp->bnapi[i]);
5341                 irq->requested = 0;
5342         }
5343 }
5344
5345 static int bnxt_request_irq(struct bnxt *bp)
5346 {
5347         int i, j, rc = 0;
5348         unsigned long flags = 0;
5349 #ifdef CONFIG_RFS_ACCEL
5350         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5351 #endif
5352
5353         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5354                 flags = IRQF_SHARED;
5355
5356         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5357                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5358 #ifdef CONFIG_RFS_ACCEL
5359                 if (rmap && bp->bnapi[i]->rx_ring) {
5360                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5361                         if (rc)
5362                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5363                                             j);
5364                         j++;
5365                 }
5366 #endif
5367                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5368                                  bp->bnapi[i]);
5369                 if (rc)
5370                         break;
5371
5372                 irq->requested = 1;
5373         }
5374         return rc;
5375 }
5376
5377 static void bnxt_del_napi(struct bnxt *bp)
5378 {
5379         int i;
5380
5381         if (!bp->bnapi)
5382                 return;
5383
5384         for (i = 0; i < bp->cp_nr_rings; i++) {
5385                 struct bnxt_napi *bnapi = bp->bnapi[i];
5386
5387                 napi_hash_del(&bnapi->napi);
5388                 netif_napi_del(&bnapi->napi);
5389         }
5390         /* We called napi_hash_del() before netif_napi_del(), we need
5391          * to respect an RCU grace period before freeing napi structures.
5392          */
5393         synchronize_net();
5394 }
5395
5396 static void bnxt_init_napi(struct bnxt *bp)
5397 {
5398         int i;
5399         unsigned int cp_nr_rings = bp->cp_nr_rings;
5400         struct bnxt_napi *bnapi;
5401
5402         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5403                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5404                         cp_nr_rings--;
5405                 for (i = 0; i < cp_nr_rings; i++) {
5406                         bnapi = bp->bnapi[i];
5407                         netif_napi_add(bp->dev, &bnapi->napi,
5408                                        bnxt_poll, 64);
5409                 }
5410                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5411                         bnapi = bp->bnapi[cp_nr_rings];
5412                         netif_napi_add(bp->dev, &bnapi->napi,
5413                                        bnxt_poll_nitroa0, 64);
5414                 }
5415         } else {
5416                 bnapi = bp->bnapi[0];
5417                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5418         }
5419 }
5420
5421 static void bnxt_disable_napi(struct bnxt *bp)
5422 {
5423         int i;
5424
5425         if (!bp->bnapi)
5426                 return;
5427
5428         for (i = 0; i < bp->cp_nr_rings; i++)
5429                 napi_disable(&bp->bnapi[i]->napi);
5430 }
5431
5432 static void bnxt_enable_napi(struct bnxt *bp)
5433 {
5434         int i;
5435
5436         for (i = 0; i < bp->cp_nr_rings; i++) {
5437                 bp->bnapi[i]->in_reset = false;
5438                 napi_enable(&bp->bnapi[i]->napi);
5439         }
5440 }
5441
5442 void bnxt_tx_disable(struct bnxt *bp)
5443 {
5444         int i;
5445         struct bnxt_tx_ring_info *txr;
5446         struct netdev_queue *txq;
5447
5448         if (bp->tx_ring) {
5449                 for (i = 0; i < bp->tx_nr_rings; i++) {
5450                         txr = &bp->tx_ring[i];
5451                         txq = netdev_get_tx_queue(bp->dev, i);
5452                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5453                 }
5454         }
5455         /* Stop all TX queues */
5456         netif_tx_disable(bp->dev);
5457         netif_carrier_off(bp->dev);
5458 }
5459
5460 void bnxt_tx_enable(struct bnxt *bp)
5461 {
5462         int i;
5463         struct bnxt_tx_ring_info *txr;
5464         struct netdev_queue *txq;
5465
5466         for (i = 0; i < bp->tx_nr_rings; i++) {
5467                 txr = &bp->tx_ring[i];
5468                 txq = netdev_get_tx_queue(bp->dev, i);
5469                 txr->dev_state = 0;
5470         }
5471         netif_tx_wake_all_queues(bp->dev);
5472         if (bp->link_info.link_up)
5473                 netif_carrier_on(bp->dev);
5474 }
5475
5476 static void bnxt_report_link(struct bnxt *bp)
5477 {
5478         if (bp->link_info.link_up) {
5479                 const char *duplex;
5480                 const char *flow_ctrl;
5481                 u32 speed;
5482                 u16 fec;
5483
5484                 netif_carrier_on(bp->dev);
5485                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5486                         duplex = "full";
5487                 else
5488                         duplex = "half";
5489                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5490                         flow_ctrl = "ON - receive & transmit";
5491                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5492                         flow_ctrl = "ON - transmit";
5493                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5494                         flow_ctrl = "ON - receive";
5495                 else
5496                         flow_ctrl = "none";
5497                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5498                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5499                             speed, duplex, flow_ctrl);
5500                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5501                         netdev_info(bp->dev, "EEE is %s\n",
5502                                     bp->eee.eee_active ? "active" :
5503                                                          "not active");
5504                 fec = bp->link_info.fec_cfg;
5505                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5506                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5507                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5508                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5509                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5510         } else {
5511                 netif_carrier_off(bp->dev);
5512                 netdev_err(bp->dev, "NIC Link is Down\n");
5513         }
5514 }
5515
5516 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5517 {
5518         int rc = 0;
5519         struct hwrm_port_phy_qcaps_input req = {0};
5520         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5521         struct bnxt_link_info *link_info = &bp->link_info;
5522
5523         if (bp->hwrm_spec_code < 0x10201)
5524                 return 0;
5525
5526         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5527
5528         mutex_lock(&bp->hwrm_cmd_lock);
5529         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5530         if (rc)
5531                 goto hwrm_phy_qcaps_exit;
5532
5533         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5534                 struct ethtool_eee *eee = &bp->eee;
5535                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5536
5537                 bp->flags |= BNXT_FLAG_EEE_CAP;
5538                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5539                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5540                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5541                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5542                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5543         }
5544         if (resp->supported_speeds_auto_mode)
5545                 link_info->support_auto_speeds =
5546                         le16_to_cpu(resp->supported_speeds_auto_mode);
5547
5548 hwrm_phy_qcaps_exit:
5549         mutex_unlock(&bp->hwrm_cmd_lock);
5550         return rc;
5551 }
5552
5553 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5554 {
5555         int rc = 0;
5556         struct bnxt_link_info *link_info = &bp->link_info;
5557         struct hwrm_port_phy_qcfg_input req = {0};
5558         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5559         u8 link_up = link_info->link_up;
5560         u16 diff;
5561
5562         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5563
5564         mutex_lock(&bp->hwrm_cmd_lock);
5565         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5566         if (rc) {
5567                 mutex_unlock(&bp->hwrm_cmd_lock);
5568                 return rc;
5569         }
5570
5571         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5572         link_info->phy_link_status = resp->link;
5573         link_info->duplex =  resp->duplex;
5574         link_info->pause = resp->pause;
5575         link_info->auto_mode = resp->auto_mode;
5576         link_info->auto_pause_setting = resp->auto_pause;
5577         link_info->lp_pause = resp->link_partner_adv_pause;
5578         link_info->force_pause_setting = resp->force_pause;
5579         link_info->duplex_setting = resp->duplex;
5580         if (link_info->phy_link_status == BNXT_LINK_LINK)
5581                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5582         else
5583                 link_info->link_speed = 0;
5584         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5585         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5586         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5587         link_info->lp_auto_link_speeds =
5588                 le16_to_cpu(resp->link_partner_adv_speeds);
5589         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5590         link_info->phy_ver[0] = resp->phy_maj;
5591         link_info->phy_ver[1] = resp->phy_min;
5592         link_info->phy_ver[2] = resp->phy_bld;
5593         link_info->media_type = resp->media_type;
5594         link_info->phy_type = resp->phy_type;
5595         link_info->transceiver = resp->xcvr_pkg_type;
5596         link_info->phy_addr = resp->eee_config_phy_addr &
5597                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5598         link_info->module_status = resp->module_status;
5599
5600         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5601                 struct ethtool_eee *eee = &bp->eee;
5602                 u16 fw_speeds;
5603
5604                 eee->eee_active = 0;
5605                 if (resp->eee_config_phy_addr &
5606                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5607                         eee->eee_active = 1;
5608                         fw_speeds = le16_to_cpu(
5609                                 resp->link_partner_adv_eee_link_speed_mask);
5610                         eee->lp_advertised =
5611                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5612                 }
5613
5614                 /* Pull initial EEE config */
5615                 if (!chng_link_state) {
5616                         if (resp->eee_config_phy_addr &
5617                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5618                                 eee->eee_enabled = 1;
5619
5620                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5621                         eee->advertised =
5622                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5623
5624                         if (resp->eee_config_phy_addr &
5625                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5626                                 __le32 tmr;
5627
5628                                 eee->tx_lpi_enabled = 1;
5629                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5630                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5631                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5632                         }
5633                 }
5634         }
5635
5636         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5637         if (bp->hwrm_spec_code >= 0x10504)
5638                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5639
5640         /* TODO: need to add more logic to report VF link */
5641         if (chng_link_state) {
5642                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5643                         link_info->link_up = 1;
5644                 else
5645                         link_info->link_up = 0;
5646                 if (link_up != link_info->link_up)
5647                         bnxt_report_link(bp);
5648         } else {
5649                 /* alwasy link down if not require to update link state */
5650                 link_info->link_up = 0;
5651         }
5652         mutex_unlock(&bp->hwrm_cmd_lock);
5653
5654         diff = link_info->support_auto_speeds ^ link_info->advertising;
5655         if ((link_info->support_auto_speeds | diff) !=
5656             link_info->support_auto_speeds) {
5657                 /* An advertised speed is no longer supported, so we need to
5658                  * update the advertisement settings.  Caller holds RTNL
5659                  * so we can modify link settings.
5660                  */
5661                 link_info->advertising = link_info->support_auto_speeds;
5662                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5663                         bnxt_hwrm_set_link_setting(bp, true, false);
5664         }
5665         return 0;
5666 }
5667
5668 static void bnxt_get_port_module_status(struct bnxt *bp)
5669 {
5670         struct bnxt_link_info *link_info = &bp->link_info;
5671         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5672         u8 module_status;
5673
5674         if (bnxt_update_link(bp, true))
5675                 return;
5676
5677         module_status = link_info->module_status;
5678         switch (module_status) {
5679         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5680         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5681         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5682                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5683                             bp->pf.port_id);
5684                 if (bp->hwrm_spec_code >= 0x10201) {
5685                         netdev_warn(bp->dev, "Module part number %s\n",
5686                                     resp->phy_vendor_partnumber);
5687                 }
5688                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5689                         netdev_warn(bp->dev, "TX is disabled\n");
5690                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5691                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5692         }
5693 }
5694
5695 static void
5696 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5697 {
5698         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5699                 if (bp->hwrm_spec_code >= 0x10201)
5700                         req->auto_pause =
5701                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5702                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5703                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5704                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5705                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5706                 req->enables |=
5707                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5708         } else {
5709                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5710                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5711                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5712                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5713                 req->enables |=
5714                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5715                 if (bp->hwrm_spec_code >= 0x10201) {
5716                         req->auto_pause = req->force_pause;
5717                         req->enables |= cpu_to_le32(
5718                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5719                 }
5720         }
5721 }
5722
5723 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5724                                       struct hwrm_port_phy_cfg_input *req)
5725 {
5726         u8 autoneg = bp->link_info.autoneg;
5727         u16 fw_link_speed = bp->link_info.req_link_speed;
5728         u16 advertising = bp->link_info.advertising;
5729
5730         if (autoneg & BNXT_AUTONEG_SPEED) {
5731                 req->auto_mode |=
5732                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5733
5734                 req->enables |= cpu_to_le32(
5735                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5736                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5737
5738                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5739                 req->flags |=
5740                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5741         } else {
5742                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5743                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5744         }
5745
5746         /* tell chimp that the setting takes effect immediately */
5747         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5748 }
5749
5750 int bnxt_hwrm_set_pause(struct bnxt *bp)
5751 {
5752         struct hwrm_port_phy_cfg_input req = {0};
5753         int rc;
5754
5755         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5756         bnxt_hwrm_set_pause_common(bp, &req);
5757
5758         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5759             bp->link_info.force_link_chng)
5760                 bnxt_hwrm_set_link_common(bp, &req);
5761
5762         mutex_lock(&bp->hwrm_cmd_lock);
5763         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5764         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5765                 /* since changing of pause setting doesn't trigger any link
5766                  * change event, the driver needs to update the current pause
5767                  * result upon successfully return of the phy_cfg command
5768                  */
5769                 bp->link_info.pause =
5770                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5771                 bp->link_info.auto_pause_setting = 0;
5772                 if (!bp->link_info.force_link_chng)
5773                         bnxt_report_link(bp);
5774         }
5775         bp->link_info.force_link_chng = false;
5776         mutex_unlock(&bp->hwrm_cmd_lock);
5777         return rc;
5778 }
5779
5780 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5781                               struct hwrm_port_phy_cfg_input *req)
5782 {
5783         struct ethtool_eee *eee = &bp->eee;
5784
5785         if (eee->eee_enabled) {
5786                 u16 eee_speeds;
5787                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5788
5789                 if (eee->tx_lpi_enabled)
5790                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5791                 else
5792                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5793
5794                 req->flags |= cpu_to_le32(flags);
5795                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5796                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5797                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5798         } else {
5799                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5800         }
5801 }
5802
5803 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5804 {
5805         struct hwrm_port_phy_cfg_input req = {0};
5806
5807         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5808         if (set_pause)
5809                 bnxt_hwrm_set_pause_common(bp, &req);
5810
5811         bnxt_hwrm_set_link_common(bp, &req);
5812
5813         if (set_eee)
5814                 bnxt_hwrm_set_eee(bp, &req);
5815         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5816 }
5817
5818 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5819 {
5820         struct hwrm_port_phy_cfg_input req = {0};
5821
5822         if (!BNXT_SINGLE_PF(bp))
5823                 return 0;
5824
5825         if (pci_num_vf(bp->pdev))
5826                 return 0;
5827
5828         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5829         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
5830         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5831 }
5832
5833 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5834 {
5835         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5836         struct hwrm_port_led_qcaps_input req = {0};
5837         struct bnxt_pf_info *pf = &bp->pf;
5838         int rc;
5839
5840         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5841                 return 0;
5842
5843         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5844         req.port_id = cpu_to_le16(pf->port_id);
5845         mutex_lock(&bp->hwrm_cmd_lock);
5846         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5847         if (rc) {
5848                 mutex_unlock(&bp->hwrm_cmd_lock);
5849                 return rc;
5850         }
5851         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5852                 int i;
5853
5854                 bp->num_leds = resp->num_leds;
5855                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5856                                                  bp->num_leds);
5857                 for (i = 0; i < bp->num_leds; i++) {
5858                         struct bnxt_led_info *led = &bp->leds[i];
5859                         __le16 caps = led->led_state_caps;
5860
5861                         if (!led->led_group_id ||
5862                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
5863                                 bp->num_leds = 0;
5864                                 break;
5865                         }
5866                 }
5867         }
5868         mutex_unlock(&bp->hwrm_cmd_lock);
5869         return 0;
5870 }
5871
5872 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
5873 {
5874         struct hwrm_wol_filter_alloc_input req = {0};
5875         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5876         int rc;
5877
5878         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
5879         req.port_id = cpu_to_le16(bp->pf.port_id);
5880         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
5881         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
5882         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
5883         mutex_lock(&bp->hwrm_cmd_lock);
5884         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5885         if (!rc)
5886                 bp->wol_filter_id = resp->wol_filter_id;
5887         mutex_unlock(&bp->hwrm_cmd_lock);
5888         return rc;
5889 }
5890
5891 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
5892 {
5893         struct hwrm_wol_filter_free_input req = {0};
5894         int rc;
5895
5896         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
5897         req.port_id = cpu_to_le16(bp->pf.port_id);
5898         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
5899         req.wol_filter_id = bp->wol_filter_id;
5900         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5901         return rc;
5902 }
5903
5904 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
5905 {
5906         struct hwrm_wol_filter_qcfg_input req = {0};
5907         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5908         u16 next_handle = 0;
5909         int rc;
5910
5911         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
5912         req.port_id = cpu_to_le16(bp->pf.port_id);
5913         req.handle = cpu_to_le16(handle);
5914         mutex_lock(&bp->hwrm_cmd_lock);
5915         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5916         if (!rc) {
5917                 next_handle = le16_to_cpu(resp->next_handle);
5918                 if (next_handle != 0) {
5919                         if (resp->wol_type ==
5920                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
5921                                 bp->wol = 1;
5922                                 bp->wol_filter_id = resp->wol_filter_id;
5923                         }
5924                 }
5925         }
5926         mutex_unlock(&bp->hwrm_cmd_lock);
5927         return next_handle;
5928 }
5929
5930 static void bnxt_get_wol_settings(struct bnxt *bp)
5931 {
5932         u16 handle = 0;
5933
5934         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
5935                 return;
5936
5937         do {
5938                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
5939         } while (handle && handle != 0xffff);
5940 }
5941
5942 static bool bnxt_eee_config_ok(struct bnxt *bp)
5943 {
5944         struct ethtool_eee *eee = &bp->eee;
5945         struct bnxt_link_info *link_info = &bp->link_info;
5946
5947         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5948                 return true;
5949
5950         if (eee->eee_enabled) {
5951                 u32 advertising =
5952                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5953
5954                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5955                         eee->eee_enabled = 0;
5956                         return false;
5957                 }
5958                 if (eee->advertised & ~advertising) {
5959                         eee->advertised = advertising & eee->supported;
5960                         return false;
5961                 }
5962         }
5963         return true;
5964 }
5965
5966 static int bnxt_update_phy_setting(struct bnxt *bp)
5967 {
5968         int rc;
5969         bool update_link = false;
5970         bool update_pause = false;
5971         bool update_eee = false;
5972         struct bnxt_link_info *link_info = &bp->link_info;
5973
5974         rc = bnxt_update_link(bp, true);
5975         if (rc) {
5976                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5977                            rc);
5978                 return rc;
5979         }
5980         if (!BNXT_SINGLE_PF(bp))
5981                 return 0;
5982
5983         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5984             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5985             link_info->req_flow_ctrl)
5986                 update_pause = true;
5987         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5988             link_info->force_pause_setting != link_info->req_flow_ctrl)
5989                 update_pause = true;
5990         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5991                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5992                         update_link = true;
5993                 if (link_info->req_link_speed != link_info->force_link_speed)
5994                         update_link = true;
5995                 if (link_info->req_duplex != link_info->duplex_setting)
5996                         update_link = true;
5997         } else {
5998                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5999                         update_link = true;
6000                 if (link_info->advertising != link_info->auto_link_speeds)
6001                         update_link = true;
6002         }
6003
6004         /* The last close may have shutdown the link, so need to call
6005          * PHY_CFG to bring it back up.
6006          */
6007         if (!netif_carrier_ok(bp->dev))
6008                 update_link = true;
6009
6010         if (!bnxt_eee_config_ok(bp))
6011                 update_eee = true;
6012
6013         if (update_link)
6014                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6015         else if (update_pause)
6016                 rc = bnxt_hwrm_set_pause(bp);
6017         if (rc) {
6018                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6019                            rc);
6020                 return rc;
6021         }
6022
6023         return rc;
6024 }
6025
6026 /* Common routine to pre-map certain register block to different GRC window.
6027  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6028  * in PF and 3 windows in VF that can be customized to map in different
6029  * register blocks.
6030  */
6031 static void bnxt_preset_reg_win(struct bnxt *bp)
6032 {
6033         if (BNXT_PF(bp)) {
6034                 /* CAG registers map to GRC window #4 */
6035                 writel(BNXT_CAG_REG_BASE,
6036                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6037         }
6038 }
6039
6040 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6041 {
6042         int rc = 0;
6043
6044         bnxt_preset_reg_win(bp);
6045         netif_carrier_off(bp->dev);
6046         if (irq_re_init) {
6047                 rc = bnxt_setup_int_mode(bp);
6048                 if (rc) {
6049                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6050                                    rc);
6051                         return rc;
6052                 }
6053         }
6054         if ((bp->flags & BNXT_FLAG_RFS) &&
6055             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6056                 /* disable RFS if falling back to INTA */
6057                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6058                 bp->flags &= ~BNXT_FLAG_RFS;
6059         }
6060
6061         rc = bnxt_alloc_mem(bp, irq_re_init);
6062         if (rc) {
6063                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6064                 goto open_err_free_mem;
6065         }
6066
6067         if (irq_re_init) {
6068                 bnxt_init_napi(bp);
6069                 rc = bnxt_request_irq(bp);
6070                 if (rc) {
6071                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6072                         goto open_err;
6073                 }
6074         }
6075
6076         bnxt_enable_napi(bp);
6077
6078         rc = bnxt_init_nic(bp, irq_re_init);
6079         if (rc) {
6080                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6081                 goto open_err;
6082         }
6083
6084         if (link_re_init) {
6085                 rc = bnxt_update_phy_setting(bp);
6086                 if (rc)
6087                         netdev_warn(bp->dev, "failed to update phy settings\n");
6088         }
6089
6090         if (irq_re_init)
6091                 udp_tunnel_get_rx_info(bp->dev);
6092
6093         set_bit(BNXT_STATE_OPEN, &bp->state);
6094         bnxt_enable_int(bp);
6095         /* Enable TX queues */
6096         bnxt_tx_enable(bp);
6097         mod_timer(&bp->timer, jiffies + bp->current_interval);
6098         /* Poll link status and check for SFP+ module status */
6099         bnxt_get_port_module_status(bp);
6100
6101         return 0;
6102
6103 open_err:
6104         bnxt_disable_napi(bp);
6105         bnxt_del_napi(bp);
6106
6107 open_err_free_mem:
6108         bnxt_free_skbs(bp);
6109         bnxt_free_irq(bp);
6110         bnxt_free_mem(bp, true);
6111         return rc;
6112 }
6113
6114 /* rtnl_lock held */
6115 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6116 {
6117         int rc = 0;
6118
6119         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6120         if (rc) {
6121                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6122                 dev_close(bp->dev);
6123         }
6124         return rc;
6125 }
6126
6127 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6128  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6129  * self tests.
6130  */
6131 int bnxt_half_open_nic(struct bnxt *bp)
6132 {
6133         int rc = 0;
6134
6135         rc = bnxt_alloc_mem(bp, false);
6136         if (rc) {
6137                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6138                 goto half_open_err;
6139         }
6140         rc = bnxt_init_nic(bp, false);
6141         if (rc) {
6142                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6143                 goto half_open_err;
6144         }
6145         return 0;
6146
6147 half_open_err:
6148         bnxt_free_skbs(bp);
6149         bnxt_free_mem(bp, false);
6150         dev_close(bp->dev);
6151         return rc;
6152 }
6153
6154 /* rtnl_lock held, this call can only be made after a previous successful
6155  * call to bnxt_half_open_nic().
6156  */
6157 void bnxt_half_close_nic(struct bnxt *bp)
6158 {
6159         bnxt_hwrm_resource_free(bp, false, false);
6160         bnxt_free_skbs(bp);
6161         bnxt_free_mem(bp, false);
6162 }
6163
6164 static int bnxt_open(struct net_device *dev)
6165 {
6166         struct bnxt *bp = netdev_priv(dev);
6167
6168         return __bnxt_open_nic(bp, true, true);
6169 }
6170
6171 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6172 {
6173         int rc = 0;
6174
6175 #ifdef CONFIG_BNXT_SRIOV
6176         if (bp->sriov_cfg) {
6177                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6178                                                       !bp->sriov_cfg,
6179                                                       BNXT_SRIOV_CFG_WAIT_TMO);
6180                 if (rc)
6181                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6182         }
6183 #endif
6184         /* Change device state to avoid TX queue wake up's */
6185         bnxt_tx_disable(bp);
6186
6187         clear_bit(BNXT_STATE_OPEN, &bp->state);
6188         smp_mb__after_atomic();
6189         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
6190                 msleep(20);
6191
6192         /* Flush rings and and disable interrupts */
6193         bnxt_shutdown_nic(bp, irq_re_init);
6194
6195         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6196
6197         bnxt_disable_napi(bp);
6198         del_timer_sync(&bp->timer);
6199         bnxt_free_skbs(bp);
6200
6201         if (irq_re_init) {
6202                 bnxt_free_irq(bp);
6203                 bnxt_del_napi(bp);
6204         }
6205         bnxt_free_mem(bp, irq_re_init);
6206         return rc;
6207 }
6208
6209 static int bnxt_close(struct net_device *dev)
6210 {
6211         struct bnxt *bp = netdev_priv(dev);
6212
6213         bnxt_close_nic(bp, true, true);
6214         bnxt_hwrm_shutdown_link(bp);
6215         return 0;
6216 }
6217
6218 /* rtnl_lock held */
6219 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6220 {
6221         switch (cmd) {
6222         case SIOCGMIIPHY:
6223                 /* fallthru */
6224         case SIOCGMIIREG: {
6225                 if (!netif_running(dev))
6226                         return -EAGAIN;
6227
6228                 return 0;
6229         }
6230
6231         case SIOCSMIIREG:
6232                 if (!netif_running(dev))
6233                         return -EAGAIN;
6234
6235                 return 0;
6236
6237         default:
6238                 /* do nothing */
6239                 break;
6240         }
6241         return -EOPNOTSUPP;
6242 }
6243
6244 static void
6245 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6246 {
6247         u32 i;
6248         struct bnxt *bp = netdev_priv(dev);
6249
6250         if (!bp->bnapi)
6251                 return;
6252
6253         /* TODO check if we need to synchronize with bnxt_close path */
6254         for (i = 0; i < bp->cp_nr_rings; i++) {
6255                 struct bnxt_napi *bnapi = bp->bnapi[i];
6256                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6257                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6258
6259                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6260                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6261                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6262
6263                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6264                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6265                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6266
6267                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6268                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6269                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6270
6271                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6272                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6273                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6274
6275                 stats->rx_missed_errors +=
6276                         le64_to_cpu(hw_stats->rx_discard_pkts);
6277
6278                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6279
6280                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6281         }
6282
6283         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6284                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6285                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6286
6287                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6288                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6289                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6290                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6291                                           le64_to_cpu(rx->rx_runt_frames);
6292                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6293                                    le64_to_cpu(rx->rx_jbr_frames);
6294                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6295                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6296                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6297         }
6298 }
6299
6300 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6301 {
6302         struct net_device *dev = bp->dev;
6303         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6304         struct netdev_hw_addr *ha;
6305         u8 *haddr;
6306         int mc_count = 0;
6307         bool update = false;
6308         int off = 0;
6309
6310         netdev_for_each_mc_addr(ha, dev) {
6311                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6312                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6313                         vnic->mc_list_count = 0;
6314                         return false;
6315                 }
6316                 haddr = ha->addr;
6317                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6318                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6319                         update = true;
6320                 }
6321                 off += ETH_ALEN;
6322                 mc_count++;
6323         }
6324         if (mc_count)
6325                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6326
6327         if (mc_count != vnic->mc_list_count) {
6328                 vnic->mc_list_count = mc_count;
6329                 update = true;
6330         }
6331         return update;
6332 }
6333
6334 static bool bnxt_uc_list_updated(struct bnxt *bp)
6335 {
6336         struct net_device *dev = bp->dev;
6337         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6338         struct netdev_hw_addr *ha;
6339         int off = 0;
6340
6341         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6342                 return true;
6343
6344         netdev_for_each_uc_addr(ha, dev) {
6345                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6346                         return true;
6347
6348                 off += ETH_ALEN;
6349         }
6350         return false;
6351 }
6352
6353 static void bnxt_set_rx_mode(struct net_device *dev)
6354 {
6355         struct bnxt *bp = netdev_priv(dev);
6356         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6357         u32 mask = vnic->rx_mask;
6358         bool mc_update = false;
6359         bool uc_update;
6360
6361         if (!netif_running(dev))
6362                 return;
6363
6364         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6365                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6366                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6367
6368         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6369                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6370
6371         uc_update = bnxt_uc_list_updated(bp);
6372
6373         if (dev->flags & IFF_ALLMULTI) {
6374                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6375                 vnic->mc_list_count = 0;
6376         } else {
6377                 mc_update = bnxt_mc_list_updated(bp, &mask);
6378         }
6379
6380         if (mask != vnic->rx_mask || uc_update || mc_update) {
6381                 vnic->rx_mask = mask;
6382
6383                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6384                 schedule_work(&bp->sp_task);
6385         }
6386 }
6387
6388 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6389 {
6390         struct net_device *dev = bp->dev;
6391         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6392         struct netdev_hw_addr *ha;
6393         int i, off = 0, rc;
6394         bool uc_update;
6395
6396         netif_addr_lock_bh(dev);
6397         uc_update = bnxt_uc_list_updated(bp);
6398         netif_addr_unlock_bh(dev);
6399
6400         if (!uc_update)
6401                 goto skip_uc;
6402
6403         mutex_lock(&bp->hwrm_cmd_lock);
6404         for (i = 1; i < vnic->uc_filter_count; i++) {
6405                 struct hwrm_cfa_l2_filter_free_input req = {0};
6406
6407                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6408                                        -1);
6409
6410                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6411
6412                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6413                                         HWRM_CMD_TIMEOUT);
6414         }
6415         mutex_unlock(&bp->hwrm_cmd_lock);
6416
6417         vnic->uc_filter_count = 1;
6418
6419         netif_addr_lock_bh(dev);
6420         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6421                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6422         } else {
6423                 netdev_for_each_uc_addr(ha, dev) {
6424                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6425                         off += ETH_ALEN;
6426                         vnic->uc_filter_count++;
6427                 }
6428         }
6429         netif_addr_unlock_bh(dev);
6430
6431         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6432                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6433                 if (rc) {
6434                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6435                                    rc);
6436                         vnic->uc_filter_count = i;
6437                         return rc;
6438                 }
6439         }
6440
6441 skip_uc:
6442         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6443         if (rc)
6444                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6445                            rc);
6446
6447         return rc;
6448 }
6449
6450 /* If the chip and firmware supports RFS */
6451 static bool bnxt_rfs_supported(struct bnxt *bp)
6452 {
6453         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6454                 return true;
6455         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6456                 return true;
6457         return false;
6458 }
6459
6460 /* If runtime conditions support RFS */
6461 static bool bnxt_rfs_capable(struct bnxt *bp)
6462 {
6463 #ifdef CONFIG_RFS_ACCEL
6464         int vnics, max_vnics, max_rss_ctxs;
6465
6466         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6467                 return false;
6468
6469         vnics = 1 + bp->rx_nr_rings;
6470         max_vnics = bnxt_get_max_func_vnics(bp);
6471         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6472
6473         /* RSS contexts not a limiting factor */
6474         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6475                 max_rss_ctxs = max_vnics;
6476         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6477                 netdev_warn(bp->dev,
6478                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6479                             min(max_rss_ctxs - 1, max_vnics - 1));
6480                 return false;
6481         }
6482
6483         return true;
6484 #else
6485         return false;
6486 #endif
6487 }
6488
6489 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6490                                            netdev_features_t features)
6491 {
6492         struct bnxt *bp = netdev_priv(dev);
6493
6494         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6495                 features &= ~NETIF_F_NTUPLE;
6496
6497         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6498          * turned on or off together.
6499          */
6500         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6501             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6502                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6503                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6504                                       NETIF_F_HW_VLAN_STAG_RX);
6505                 else
6506                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6507                                     NETIF_F_HW_VLAN_STAG_RX;
6508         }
6509 #ifdef CONFIG_BNXT_SRIOV
6510         if (BNXT_VF(bp)) {
6511                 if (bp->vf.vlan) {
6512                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6513                                       NETIF_F_HW_VLAN_STAG_RX);
6514                 }
6515         }
6516 #endif
6517         return features;
6518 }
6519
6520 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6521 {
6522         struct bnxt *bp = netdev_priv(dev);
6523         u32 flags = bp->flags;
6524         u32 changes;
6525         int rc = 0;
6526         bool re_init = false;
6527         bool update_tpa = false;
6528
6529         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6530         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6531                 flags |= BNXT_FLAG_GRO;
6532         if (features & NETIF_F_LRO)
6533                 flags |= BNXT_FLAG_LRO;
6534
6535         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6536                 flags &= ~BNXT_FLAG_TPA;
6537
6538         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6539                 flags |= BNXT_FLAG_STRIP_VLAN;
6540
6541         if (features & NETIF_F_NTUPLE)
6542                 flags |= BNXT_FLAG_RFS;
6543
6544         changes = flags ^ bp->flags;
6545         if (changes & BNXT_FLAG_TPA) {
6546                 update_tpa = true;
6547                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6548                     (flags & BNXT_FLAG_TPA) == 0)
6549                         re_init = true;
6550         }
6551
6552         if (changes & ~BNXT_FLAG_TPA)
6553                 re_init = true;
6554
6555         if (flags != bp->flags) {
6556                 u32 old_flags = bp->flags;
6557
6558                 bp->flags = flags;
6559
6560                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6561                         if (update_tpa)
6562                                 bnxt_set_ring_params(bp);
6563                         return rc;
6564                 }
6565
6566                 if (re_init) {
6567                         bnxt_close_nic(bp, false, false);
6568                         if (update_tpa)
6569                                 bnxt_set_ring_params(bp);
6570
6571                         return bnxt_open_nic(bp, false, false);
6572                 }
6573                 if (update_tpa) {
6574                         rc = bnxt_set_tpa(bp,
6575                                           (flags & BNXT_FLAG_TPA) ?
6576                                           true : false);
6577                         if (rc)
6578                                 bp->flags = old_flags;
6579                 }
6580         }
6581         return rc;
6582 }
6583
6584 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6585 {
6586         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6587         int i = bnapi->index;
6588
6589         if (!txr)
6590                 return;
6591
6592         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6593                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6594                     txr->tx_cons);
6595 }
6596
6597 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6598 {
6599         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6600         int i = bnapi->index;
6601
6602         if (!rxr)
6603                 return;
6604
6605         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6606                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6607                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6608                     rxr->rx_sw_agg_prod);
6609 }
6610
6611 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6612 {
6613         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6614         int i = bnapi->index;
6615
6616         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6617                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6618 }
6619
6620 static void bnxt_dbg_dump_states(struct bnxt *bp)
6621 {
6622         int i;
6623         struct bnxt_napi *bnapi;
6624
6625         for (i = 0; i < bp->cp_nr_rings; i++) {
6626                 bnapi = bp->bnapi[i];
6627                 if (netif_msg_drv(bp)) {
6628                         bnxt_dump_tx_sw_state(bnapi);
6629                         bnxt_dump_rx_sw_state(bnapi);
6630                         bnxt_dump_cp_sw_state(bnapi);
6631                 }
6632         }
6633 }
6634
6635 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6636 {
6637         if (!silent)
6638                 bnxt_dbg_dump_states(bp);
6639         if (netif_running(bp->dev)) {
6640                 int rc;
6641
6642                 if (!silent)
6643                         bnxt_ulp_stop(bp);
6644                 bnxt_close_nic(bp, false, false);
6645                 rc = bnxt_open_nic(bp, false, false);
6646                 if (!silent && !rc)
6647                         bnxt_ulp_start(bp);
6648         }
6649 }
6650
6651 static void bnxt_tx_timeout(struct net_device *dev)
6652 {
6653         struct bnxt *bp = netdev_priv(dev);
6654
6655         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6656         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6657         schedule_work(&bp->sp_task);
6658 }
6659
6660 #ifdef CONFIG_NET_POLL_CONTROLLER
6661 static void bnxt_poll_controller(struct net_device *dev)
6662 {
6663         struct bnxt *bp = netdev_priv(dev);
6664         int i;
6665
6666         for (i = 0; i < bp->cp_nr_rings; i++) {
6667                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6668
6669                 disable_irq(irq->vector);
6670                 irq->handler(irq->vector, bp->bnapi[i]);
6671                 enable_irq(irq->vector);
6672         }
6673 }
6674 #endif
6675
6676 static void bnxt_timer(unsigned long data)
6677 {
6678         struct bnxt *bp = (struct bnxt *)data;
6679         struct net_device *dev = bp->dev;
6680
6681         if (!netif_running(dev))
6682                 return;
6683
6684         if (atomic_read(&bp->intr_sem) != 0)
6685                 goto bnxt_restart_timer;
6686
6687         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6688                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6689                 schedule_work(&bp->sp_task);
6690         }
6691 bnxt_restart_timer:
6692         mod_timer(&bp->timer, jiffies + bp->current_interval);
6693 }
6694
6695 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6696 {
6697         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6698          * set.  If the device is being closed, bnxt_close() may be holding
6699          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6700          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6701          */
6702         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6703         rtnl_lock();
6704 }
6705
6706 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6707 {
6708         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6709         rtnl_unlock();
6710 }
6711
6712 /* Only called from bnxt_sp_task() */
6713 static void bnxt_reset(struct bnxt *bp, bool silent)
6714 {
6715         bnxt_rtnl_lock_sp(bp);
6716         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6717                 bnxt_reset_task(bp, silent);
6718         bnxt_rtnl_unlock_sp(bp);
6719 }
6720
6721 static void bnxt_cfg_ntp_filters(struct bnxt *);
6722
6723 static void bnxt_sp_task(struct work_struct *work)
6724 {
6725         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6726
6727         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6728         smp_mb__after_atomic();
6729         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6730                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6731                 return;
6732         }
6733
6734         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6735                 bnxt_cfg_rx_mode(bp);
6736
6737         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6738                 bnxt_cfg_ntp_filters(bp);
6739         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6740                 bnxt_hwrm_exec_fwd_req(bp);
6741         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6742                 bnxt_hwrm_tunnel_dst_port_alloc(
6743                         bp, bp->vxlan_port,
6744                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6745         }
6746         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6747                 bnxt_hwrm_tunnel_dst_port_free(
6748                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6749         }
6750         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6751                 bnxt_hwrm_tunnel_dst_port_alloc(
6752                         bp, bp->nge_port,
6753                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6754         }
6755         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6756                 bnxt_hwrm_tunnel_dst_port_free(
6757                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6758         }
6759         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6760                 bnxt_hwrm_port_qstats(bp);
6761
6762         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
6763          * must be the last functions to be called before exiting.
6764          */
6765         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6766                 int rc = 0;
6767
6768                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6769                                        &bp->sp_event))
6770                         bnxt_hwrm_phy_qcaps(bp);
6771
6772                 bnxt_rtnl_lock_sp(bp);
6773                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6774                         rc = bnxt_update_link(bp, true);
6775                 bnxt_rtnl_unlock_sp(bp);
6776                 if (rc)
6777                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6778                                    rc);
6779         }
6780         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6781                 bnxt_rtnl_lock_sp(bp);
6782                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6783                         bnxt_get_port_module_status(bp);
6784                 bnxt_rtnl_unlock_sp(bp);
6785         }
6786         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6787                 bnxt_reset(bp, false);
6788
6789         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6790                 bnxt_reset(bp, true);
6791
6792         smp_mb__before_atomic();
6793         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6794 }
6795
6796 /* Under rtnl_lock */
6797 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
6798 {
6799         int max_rx, max_tx, tx_sets = 1;
6800         int tx_rings_needed;
6801         bool sh = true;
6802         int rc;
6803
6804         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6805                 sh = false;
6806
6807         if (tcs)
6808                 tx_sets = tcs;
6809
6810         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6811         if (rc)
6812                 return rc;
6813
6814         if (max_rx < rx)
6815                 return -ENOMEM;
6816
6817         tx_rings_needed = tx * tx_sets + tx_xdp;
6818         if (max_tx < tx_rings_needed)
6819                 return -ENOMEM;
6820
6821         if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
6822             tx_rings_needed < (tx * tx_sets + tx_xdp))
6823                 return -ENOMEM;
6824         return 0;
6825 }
6826
6827 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
6828 {
6829         if (bp->bar2) {
6830                 pci_iounmap(pdev, bp->bar2);
6831                 bp->bar2 = NULL;
6832         }
6833
6834         if (bp->bar1) {
6835                 pci_iounmap(pdev, bp->bar1);
6836                 bp->bar1 = NULL;
6837         }
6838
6839         if (bp->bar0) {
6840                 pci_iounmap(pdev, bp->bar0);
6841                 bp->bar0 = NULL;
6842         }
6843 }
6844
6845 static void bnxt_cleanup_pci(struct bnxt *bp)
6846 {
6847         bnxt_unmap_bars(bp, bp->pdev);
6848         pci_release_regions(bp->pdev);
6849         pci_disable_device(bp->pdev);
6850 }
6851
6852 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6853 {
6854         int rc;
6855         struct bnxt *bp = netdev_priv(dev);
6856
6857         SET_NETDEV_DEV(dev, &pdev->dev);
6858
6859         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6860         rc = pci_enable_device(pdev);
6861         if (rc) {
6862                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6863                 goto init_err;
6864         }
6865
6866         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6867                 dev_err(&pdev->dev,
6868                         "Cannot find PCI device base address, aborting\n");
6869                 rc = -ENODEV;
6870                 goto init_err_disable;
6871         }
6872
6873         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6874         if (rc) {
6875                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6876                 goto init_err_disable;
6877         }
6878
6879         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6880             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6881                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6882                 goto init_err_disable;
6883         }
6884
6885         pci_set_master(pdev);
6886
6887         bp->dev = dev;
6888         bp->pdev = pdev;
6889
6890         bp->bar0 = pci_ioremap_bar(pdev, 0);
6891         if (!bp->bar0) {
6892                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6893                 rc = -ENOMEM;
6894                 goto init_err_release;
6895         }
6896
6897         bp->bar1 = pci_ioremap_bar(pdev, 2);
6898         if (!bp->bar1) {
6899                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6900                 rc = -ENOMEM;
6901                 goto init_err_release;
6902         }
6903
6904         bp->bar2 = pci_ioremap_bar(pdev, 4);
6905         if (!bp->bar2) {
6906                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6907                 rc = -ENOMEM;
6908                 goto init_err_release;
6909         }
6910
6911         pci_enable_pcie_error_reporting(pdev);
6912
6913         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6914
6915         spin_lock_init(&bp->ntp_fltr_lock);
6916
6917         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6918         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6919
6920         /* tick values in micro seconds */
6921         bp->rx_coal_ticks = 12;
6922         bp->rx_coal_bufs = 30;
6923         bp->rx_coal_ticks_irq = 1;
6924         bp->rx_coal_bufs_irq = 2;
6925
6926         bp->tx_coal_ticks = 25;
6927         bp->tx_coal_bufs = 30;
6928         bp->tx_coal_ticks_irq = 2;
6929         bp->tx_coal_bufs_irq = 2;
6930
6931         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6932
6933         init_timer(&bp->timer);
6934         bp->timer.data = (unsigned long)bp;
6935         bp->timer.function = bnxt_timer;
6936         bp->current_interval = BNXT_TIMER_INTERVAL;
6937
6938         clear_bit(BNXT_STATE_OPEN, &bp->state);
6939         return 0;
6940
6941 init_err_release:
6942         bnxt_unmap_bars(bp, pdev);
6943         pci_release_regions(pdev);
6944
6945 init_err_disable:
6946         pci_disable_device(pdev);
6947
6948 init_err:
6949         return rc;
6950 }
6951
6952 /* rtnl_lock held */
6953 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6954 {
6955         struct sockaddr *addr = p;
6956         struct bnxt *bp = netdev_priv(dev);
6957         int rc = 0;
6958
6959         if (!is_valid_ether_addr(addr->sa_data))
6960                 return -EADDRNOTAVAIL;
6961
6962         rc = bnxt_approve_mac(bp, addr->sa_data);
6963         if (rc)
6964                 return rc;
6965
6966         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6967                 return 0;
6968
6969         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6970         if (netif_running(dev)) {
6971                 bnxt_close_nic(bp, false, false);
6972                 rc = bnxt_open_nic(bp, false, false);
6973         }
6974
6975         return rc;
6976 }
6977
6978 /* rtnl_lock held */
6979 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6980 {
6981         struct bnxt *bp = netdev_priv(dev);
6982
6983         if (netif_running(dev))
6984                 bnxt_close_nic(bp, false, false);
6985
6986         dev->mtu = new_mtu;
6987         bnxt_set_ring_params(bp);
6988
6989         if (netif_running(dev))
6990                 return bnxt_open_nic(bp, false, false);
6991
6992         return 0;
6993 }
6994
6995 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
6996 {
6997         struct bnxt *bp = netdev_priv(dev);
6998         bool sh = false;
6999         int rc;
7000
7001         if (tc > bp->max_tc) {
7002                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7003                            tc, bp->max_tc);
7004                 return -EINVAL;
7005         }
7006
7007         if (netdev_get_num_tc(dev) == tc)
7008                 return 0;
7009
7010         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7011                 sh = true;
7012
7013         rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7014                                 tc, bp->tx_nr_rings_xdp);
7015         if (rc)
7016                 return rc;
7017
7018         /* Needs to close the device and do hw resource re-allocations */
7019         if (netif_running(bp->dev))
7020                 bnxt_close_nic(bp, true, false);
7021
7022         if (tc) {
7023                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7024                 netdev_set_num_tc(dev, tc);
7025         } else {
7026                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7027                 netdev_reset_tc(dev);
7028         }
7029         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7030                                bp->tx_nr_rings + bp->rx_nr_rings;
7031         bp->num_stat_ctxs = bp->cp_nr_rings;
7032
7033         if (netif_running(bp->dev))
7034                 return bnxt_open_nic(bp, true, false);
7035
7036         return 0;
7037 }
7038
7039 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
7040                          struct tc_to_netdev *ntc)
7041 {
7042         if (ntc->type != TC_SETUP_MQPRIO)
7043                 return -EINVAL;
7044
7045         ntc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7046
7047         return bnxt_setup_mq_tc(dev, ntc->mqprio->num_tc);
7048 }
7049
7050 #ifdef CONFIG_RFS_ACCEL
7051 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7052                             struct bnxt_ntuple_filter *f2)
7053 {
7054         struct flow_keys *keys1 = &f1->fkeys;
7055         struct flow_keys *keys2 = &f2->fkeys;
7056
7057         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7058             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7059             keys1->ports.ports == keys2->ports.ports &&
7060             keys1->basic.ip_proto == keys2->basic.ip_proto &&
7061             keys1->basic.n_proto == keys2->basic.n_proto &&
7062             keys1->control.flags == keys2->control.flags &&
7063             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7064             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7065                 return true;
7066
7067         return false;
7068 }
7069
7070 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7071                               u16 rxq_index, u32 flow_id)
7072 {
7073         struct bnxt *bp = netdev_priv(dev);
7074         struct bnxt_ntuple_filter *fltr, *new_fltr;
7075         struct flow_keys *fkeys;
7076         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7077         int rc = 0, idx, bit_id, l2_idx = 0;
7078         struct hlist_head *head;
7079
7080         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7081                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7082                 int off = 0, j;
7083
7084                 netif_addr_lock_bh(dev);
7085                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7086                         if (ether_addr_equal(eth->h_dest,
7087                                              vnic->uc_list + off)) {
7088                                 l2_idx = j + 1;
7089                                 break;
7090                         }
7091                 }
7092                 netif_addr_unlock_bh(dev);
7093                 if (!l2_idx)
7094                         return -EINVAL;
7095         }
7096         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7097         if (!new_fltr)
7098                 return -ENOMEM;
7099
7100         fkeys = &new_fltr->fkeys;
7101         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7102                 rc = -EPROTONOSUPPORT;
7103                 goto err_free;
7104         }
7105
7106         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7107              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7108             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7109              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7110                 rc = -EPROTONOSUPPORT;
7111                 goto err_free;
7112         }
7113         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7114             bp->hwrm_spec_code < 0x10601) {
7115                 rc = -EPROTONOSUPPORT;
7116                 goto err_free;
7117         }
7118         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7119             bp->hwrm_spec_code < 0x10601) {
7120                 rc = -EPROTONOSUPPORT;
7121                 goto err_free;
7122         }
7123
7124         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7125         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7126
7127         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7128         head = &bp->ntp_fltr_hash_tbl[idx];
7129         rcu_read_lock();
7130         hlist_for_each_entry_rcu(fltr, head, hash) {
7131                 if (bnxt_fltr_match(fltr, new_fltr)) {
7132                         rcu_read_unlock();
7133                         rc = 0;
7134                         goto err_free;
7135                 }
7136         }
7137         rcu_read_unlock();
7138
7139         spin_lock_bh(&bp->ntp_fltr_lock);
7140         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7141                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
7142         if (bit_id < 0) {
7143                 spin_unlock_bh(&bp->ntp_fltr_lock);
7144                 rc = -ENOMEM;
7145                 goto err_free;
7146         }
7147
7148         new_fltr->sw_id = (u16)bit_id;
7149         new_fltr->flow_id = flow_id;
7150         new_fltr->l2_fltr_idx = l2_idx;
7151         new_fltr->rxq = rxq_index;
7152         hlist_add_head_rcu(&new_fltr->hash, head);
7153         bp->ntp_fltr_count++;
7154         spin_unlock_bh(&bp->ntp_fltr_lock);
7155
7156         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7157         schedule_work(&bp->sp_task);
7158
7159         return new_fltr->sw_id;
7160
7161 err_free:
7162         kfree(new_fltr);
7163         return rc;
7164 }
7165
7166 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7167 {
7168         int i;
7169
7170         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7171                 struct hlist_head *head;
7172                 struct hlist_node *tmp;
7173                 struct bnxt_ntuple_filter *fltr;
7174                 int rc;
7175
7176                 head = &bp->ntp_fltr_hash_tbl[i];
7177                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7178                         bool del = false;
7179
7180                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7181                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7182                                                         fltr->flow_id,
7183                                                         fltr->sw_id)) {
7184                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
7185                                                                          fltr);
7186                                         del = true;
7187                                 }
7188                         } else {
7189                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7190                                                                        fltr);
7191                                 if (rc)
7192                                         del = true;
7193                                 else
7194                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
7195                         }
7196
7197                         if (del) {
7198                                 spin_lock_bh(&bp->ntp_fltr_lock);
7199                                 hlist_del_rcu(&fltr->hash);
7200                                 bp->ntp_fltr_count--;
7201                                 spin_unlock_bh(&bp->ntp_fltr_lock);
7202                                 synchronize_rcu();
7203                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7204                                 kfree(fltr);
7205                         }
7206                 }
7207         }
7208         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7209                 netdev_info(bp->dev, "Receive PF driver unload event!");
7210 }
7211
7212 #else
7213
7214 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7215 {
7216 }
7217
7218 #endif /* CONFIG_RFS_ACCEL */
7219
7220 static void bnxt_udp_tunnel_add(struct net_device *dev,
7221                                 struct udp_tunnel_info *ti)
7222 {
7223         struct bnxt *bp = netdev_priv(dev);
7224
7225         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7226                 return;
7227
7228         if (!netif_running(dev))
7229                 return;
7230
7231         switch (ti->type) {
7232         case UDP_TUNNEL_TYPE_VXLAN:
7233                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7234                         return;
7235
7236                 bp->vxlan_port_cnt++;
7237                 if (bp->vxlan_port_cnt == 1) {
7238                         bp->vxlan_port = ti->port;
7239                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7240                         schedule_work(&bp->sp_task);
7241                 }
7242                 break;
7243         case UDP_TUNNEL_TYPE_GENEVE:
7244                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7245                         return;
7246
7247                 bp->nge_port_cnt++;
7248                 if (bp->nge_port_cnt == 1) {
7249                         bp->nge_port = ti->port;
7250                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7251                 }
7252                 break;
7253         default:
7254                 return;
7255         }
7256
7257         schedule_work(&bp->sp_task);
7258 }
7259
7260 static void bnxt_udp_tunnel_del(struct net_device *dev,
7261                                 struct udp_tunnel_info *ti)
7262 {
7263         struct bnxt *bp = netdev_priv(dev);
7264
7265         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7266                 return;
7267
7268         if (!netif_running(dev))
7269                 return;
7270
7271         switch (ti->type) {
7272         case UDP_TUNNEL_TYPE_VXLAN:
7273                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7274                         return;
7275                 bp->vxlan_port_cnt--;
7276
7277                 if (bp->vxlan_port_cnt != 0)
7278                         return;
7279
7280                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7281                 break;
7282         case UDP_TUNNEL_TYPE_GENEVE:
7283                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7284                         return;
7285                 bp->nge_port_cnt--;
7286
7287                 if (bp->nge_port_cnt != 0)
7288                         return;
7289
7290                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7291                 break;
7292         default:
7293                 return;
7294         }
7295
7296         schedule_work(&bp->sp_task);
7297 }
7298
7299 static const struct net_device_ops bnxt_netdev_ops = {
7300         .ndo_open               = bnxt_open,
7301         .ndo_start_xmit         = bnxt_start_xmit,
7302         .ndo_stop               = bnxt_close,
7303         .ndo_get_stats64        = bnxt_get_stats64,
7304         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7305         .ndo_do_ioctl           = bnxt_ioctl,
7306         .ndo_validate_addr      = eth_validate_addr,
7307         .ndo_set_mac_address    = bnxt_change_mac_addr,
7308         .ndo_change_mtu         = bnxt_change_mtu,
7309         .ndo_fix_features       = bnxt_fix_features,
7310         .ndo_set_features       = bnxt_set_features,
7311         .ndo_tx_timeout         = bnxt_tx_timeout,
7312 #ifdef CONFIG_BNXT_SRIOV
7313         .ndo_get_vf_config      = bnxt_get_vf_config,
7314         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7315         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7316         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7317         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7318         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7319 #endif
7320 #ifdef CONFIG_NET_POLL_CONTROLLER
7321         .ndo_poll_controller    = bnxt_poll_controller,
7322 #endif
7323         .ndo_setup_tc           = bnxt_setup_tc,
7324 #ifdef CONFIG_RFS_ACCEL
7325         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7326 #endif
7327         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7328         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7329         .ndo_xdp                = bnxt_xdp,
7330 };
7331
7332 static void bnxt_remove_one(struct pci_dev *pdev)
7333 {
7334         struct net_device *dev = pci_get_drvdata(pdev);
7335         struct bnxt *bp = netdev_priv(dev);
7336
7337         if (BNXT_PF(bp))
7338                 bnxt_sriov_disable(bp);
7339
7340         pci_disable_pcie_error_reporting(pdev);
7341         unregister_netdev(dev);
7342         cancel_work_sync(&bp->sp_task);
7343         bp->sp_event = 0;
7344
7345         bnxt_clear_int_mode(bp);
7346         bnxt_hwrm_func_drv_unrgtr(bp);
7347         bnxt_free_hwrm_resources(bp);
7348         bnxt_ethtool_free(bp);
7349         bnxt_dcb_free(bp);
7350         kfree(bp->edev);
7351         bp->edev = NULL;
7352         if (bp->xdp_prog)
7353                 bpf_prog_put(bp->xdp_prog);
7354         bnxt_cleanup_pci(bp);
7355         free_netdev(dev);
7356 }
7357
7358 static int bnxt_probe_phy(struct bnxt *bp)
7359 {
7360         int rc = 0;
7361         struct bnxt_link_info *link_info = &bp->link_info;
7362
7363         rc = bnxt_hwrm_phy_qcaps(bp);
7364         if (rc) {
7365                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7366                            rc);
7367                 return rc;
7368         }
7369
7370         rc = bnxt_update_link(bp, false);
7371         if (rc) {
7372                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7373                            rc);
7374                 return rc;
7375         }
7376
7377         /* Older firmware does not have supported_auto_speeds, so assume
7378          * that all supported speeds can be autonegotiated.
7379          */
7380         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7381                 link_info->support_auto_speeds = link_info->support_speeds;
7382
7383         /*initialize the ethool setting copy with NVM settings */
7384         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7385                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7386                 if (bp->hwrm_spec_code >= 0x10201) {
7387                         if (link_info->auto_pause_setting &
7388                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7389                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7390                 } else {
7391                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7392                 }
7393                 link_info->advertising = link_info->auto_link_speeds;
7394         } else {
7395                 link_info->req_link_speed = link_info->force_link_speed;
7396                 link_info->req_duplex = link_info->duplex_setting;
7397         }
7398         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7399                 link_info->req_flow_ctrl =
7400                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7401         else
7402                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7403         return rc;
7404 }
7405
7406 static int bnxt_get_max_irq(struct pci_dev *pdev)
7407 {
7408         u16 ctrl;
7409
7410         if (!pdev->msix_cap)
7411                 return 1;
7412
7413         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7414         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7415 }
7416
7417 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7418                                 int *max_cp)
7419 {
7420         int max_ring_grps = 0;
7421
7422 #ifdef CONFIG_BNXT_SRIOV
7423         if (!BNXT_PF(bp)) {
7424                 *max_tx = bp->vf.max_tx_rings;
7425                 *max_rx = bp->vf.max_rx_rings;
7426                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7427                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7428                 max_ring_grps = bp->vf.max_hw_ring_grps;
7429         } else
7430 #endif
7431         {
7432                 *max_tx = bp->pf.max_tx_rings;
7433                 *max_rx = bp->pf.max_rx_rings;
7434                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7435                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7436                 max_ring_grps = bp->pf.max_hw_ring_grps;
7437         }
7438         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7439                 *max_cp -= 1;
7440                 *max_rx -= 2;
7441         }
7442         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7443                 *max_rx >>= 1;
7444         *max_rx = min_t(int, *max_rx, max_ring_grps);
7445 }
7446
7447 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7448 {
7449         int rx, tx, cp;
7450
7451         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7452         if (!rx || !tx || !cp)
7453                 return -ENOMEM;
7454
7455         *max_rx = rx;
7456         *max_tx = tx;
7457         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7458 }
7459
7460 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7461                                bool shared)
7462 {
7463         int rc;
7464
7465         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7466         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7467                 /* Not enough rings, try disabling agg rings. */
7468                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7469                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7470                 if (rc)
7471                         return rc;
7472                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7473                 bp->dev->hw_features &= ~NETIF_F_LRO;
7474                 bp->dev->features &= ~NETIF_F_LRO;
7475                 bnxt_set_ring_params(bp);
7476         }
7477
7478         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7479                 int max_cp, max_stat, max_irq;
7480
7481                 /* Reserve minimum resources for RoCE */
7482                 max_cp = bnxt_get_max_func_cp_rings(bp);
7483                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7484                 max_irq = bnxt_get_max_func_irqs(bp);
7485                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7486                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7487                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7488                         return 0;
7489
7490                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7491                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7492                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7493                 max_cp = min_t(int, max_cp, max_irq);
7494                 max_cp = min_t(int, max_cp, max_stat);
7495                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7496                 if (rc)
7497                         rc = 0;
7498         }
7499         return rc;
7500 }
7501
7502 static int bnxt_set_dflt_rings(struct bnxt *bp)
7503 {
7504         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7505         bool sh = true;
7506
7507         if (sh)
7508                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7509         dflt_rings = netif_get_num_default_rss_queues();
7510         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7511         if (rc)
7512                 return rc;
7513         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7514         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7515
7516         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7517         if (rc)
7518                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7519
7520         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7521         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7522                                bp->tx_nr_rings + bp->rx_nr_rings;
7523         bp->num_stat_ctxs = bp->cp_nr_rings;
7524         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7525                 bp->rx_nr_rings++;
7526                 bp->cp_nr_rings++;
7527         }
7528         return rc;
7529 }
7530
7531 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7532 {
7533         ASSERT_RTNL();
7534         bnxt_hwrm_func_qcaps(bp);
7535         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7536 }
7537
7538 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7539 {
7540         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7541         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7542
7543         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7544             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7545                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7546         else
7547                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7548                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7549                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7550                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7551                             "Unknown", width);
7552 }
7553
7554 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7555 {
7556         static int version_printed;
7557         struct net_device *dev;
7558         struct bnxt *bp;
7559         int rc, max_irqs;
7560
7561         if (pci_is_bridge(pdev))
7562                 return -ENODEV;
7563
7564         if (version_printed++ == 0)
7565                 pr_info("%s", version);
7566
7567         max_irqs = bnxt_get_max_irq(pdev);
7568         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7569         if (!dev)
7570                 return -ENOMEM;
7571
7572         bp = netdev_priv(dev);
7573
7574         if (bnxt_vf_pciid(ent->driver_data))
7575                 bp->flags |= BNXT_FLAG_VF;
7576
7577         if (pdev->msix_cap)
7578                 bp->flags |= BNXT_FLAG_MSIX_CAP;
7579
7580         rc = bnxt_init_board(pdev, dev);
7581         if (rc < 0)
7582                 goto init_err_free;
7583
7584         dev->netdev_ops = &bnxt_netdev_ops;
7585         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7586         dev->ethtool_ops = &bnxt_ethtool_ops;
7587         pci_set_drvdata(pdev, dev);
7588
7589         rc = bnxt_alloc_hwrm_resources(bp);
7590         if (rc)
7591                 goto init_err_pci_clean;
7592
7593         mutex_init(&bp->hwrm_cmd_lock);
7594         rc = bnxt_hwrm_ver_get(bp);
7595         if (rc)
7596                 goto init_err_pci_clean;
7597
7598         rc = bnxt_hwrm_func_reset(bp);
7599         if (rc)
7600                 goto init_err_pci_clean;
7601
7602         bnxt_hwrm_fw_set_time(bp);
7603
7604         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7605                            NETIF_F_TSO | NETIF_F_TSO6 |
7606                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7607                            NETIF_F_GSO_IPXIP4 |
7608                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7609                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
7610                            NETIF_F_RXCSUM | NETIF_F_GRO;
7611
7612         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7613                 dev->hw_features |= NETIF_F_LRO;
7614
7615         dev->hw_enc_features =
7616                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7617                         NETIF_F_TSO | NETIF_F_TSO6 |
7618                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7619                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7620                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
7621         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7622                                     NETIF_F_GSO_GRE_CSUM;
7623         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7624         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7625                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7626         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7627         dev->priv_flags |= IFF_UNICAST_FLT;
7628
7629         /* MTU range: 60 - 9500 */
7630         dev->min_mtu = ETH_ZLEN;
7631         dev->max_mtu = BNXT_MAX_MTU;
7632
7633 #ifdef CONFIG_BNXT_SRIOV
7634         init_waitqueue_head(&bp->sriov_cfg_wait);
7635 #endif
7636         bp->gro_func = bnxt_gro_func_5730x;
7637         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7638                 bp->gro_func = bnxt_gro_func_5731x;
7639
7640         rc = bnxt_hwrm_func_drv_rgtr(bp);
7641         if (rc)
7642                 goto init_err_pci_clean;
7643
7644         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7645         if (rc)
7646                 goto init_err_pci_clean;
7647
7648         bp->ulp_probe = bnxt_ulp_probe;
7649
7650         /* Get the MAX capabilities for this function */
7651         rc = bnxt_hwrm_func_qcaps(bp);
7652         if (rc) {
7653                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7654                            rc);
7655                 rc = -1;
7656                 goto init_err_pci_clean;
7657         }
7658
7659         rc = bnxt_hwrm_queue_qportcfg(bp);
7660         if (rc) {
7661                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7662                            rc);
7663                 rc = -1;
7664                 goto init_err_pci_clean;
7665         }
7666
7667         bnxt_hwrm_func_qcfg(bp);
7668         bnxt_hwrm_port_led_qcaps(bp);
7669         bnxt_ethtool_init(bp);
7670         bnxt_dcb_init(bp);
7671
7672         bnxt_set_rx_skb_mode(bp, false);
7673         bnxt_set_tpa_flags(bp);
7674         bnxt_set_ring_params(bp);
7675         bnxt_set_max_func_irqs(bp, max_irqs);
7676         rc = bnxt_set_dflt_rings(bp);
7677         if (rc) {
7678                 netdev_err(bp->dev, "Not enough rings available.\n");
7679                 rc = -ENOMEM;
7680                 goto init_err_pci_clean;
7681         }
7682
7683         /* Default RSS hash cfg. */
7684         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7685                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7686                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7687                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7688         if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7689             !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7690             bp->hwrm_spec_code >= 0x10501) {
7691                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7692                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7693                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7694         }
7695
7696         bnxt_hwrm_vnic_qcaps(bp);
7697         if (bnxt_rfs_supported(bp)) {
7698                 dev->hw_features |= NETIF_F_NTUPLE;
7699                 if (bnxt_rfs_capable(bp)) {
7700                         bp->flags |= BNXT_FLAG_RFS;
7701                         dev->features |= NETIF_F_NTUPLE;
7702                 }
7703         }
7704
7705         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7706                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7707
7708         rc = bnxt_probe_phy(bp);
7709         if (rc)
7710                 goto init_err_pci_clean;
7711
7712         rc = bnxt_init_int_mode(bp);
7713         if (rc)
7714                 goto init_err_pci_clean;
7715
7716         bnxt_get_wol_settings(bp);
7717         if (bp->flags & BNXT_FLAG_WOL_CAP)
7718                 device_set_wakeup_enable(&pdev->dev, bp->wol);
7719         else
7720                 device_set_wakeup_capable(&pdev->dev, false);
7721
7722         rc = register_netdev(dev);
7723         if (rc)
7724                 goto init_err_clr_int;
7725
7726         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7727                     board_info[ent->driver_data].name,
7728                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
7729
7730         bnxt_parse_log_pcie_link(bp);
7731
7732         return 0;
7733
7734 init_err_clr_int:
7735         bnxt_clear_int_mode(bp);
7736
7737 init_err_pci_clean:
7738         bnxt_cleanup_pci(bp);
7739
7740 init_err_free:
7741         free_netdev(dev);
7742         return rc;
7743 }
7744
7745 static void bnxt_shutdown(struct pci_dev *pdev)
7746 {
7747         struct net_device *dev = pci_get_drvdata(pdev);
7748         struct bnxt *bp;
7749
7750         if (!dev)
7751                 return;
7752
7753         rtnl_lock();
7754         bp = netdev_priv(dev);
7755         if (!bp)
7756                 goto shutdown_exit;
7757
7758         if (netif_running(dev))
7759                 dev_close(dev);
7760
7761         if (system_state == SYSTEM_POWER_OFF) {
7762                 bnxt_clear_int_mode(bp);
7763                 pci_wake_from_d3(pdev, bp->wol);
7764                 pci_set_power_state(pdev, PCI_D3hot);
7765         }
7766
7767 shutdown_exit:
7768         rtnl_unlock();
7769 }
7770
7771 #ifdef CONFIG_PM_SLEEP
7772 static int bnxt_suspend(struct device *device)
7773 {
7774         struct pci_dev *pdev = to_pci_dev(device);
7775         struct net_device *dev = pci_get_drvdata(pdev);
7776         struct bnxt *bp = netdev_priv(dev);
7777         int rc = 0;
7778
7779         rtnl_lock();
7780         if (netif_running(dev)) {
7781                 netif_device_detach(dev);
7782                 rc = bnxt_close(dev);
7783         }
7784         bnxt_hwrm_func_drv_unrgtr(bp);
7785         rtnl_unlock();
7786         return rc;
7787 }
7788
7789 static int bnxt_resume(struct device *device)
7790 {
7791         struct pci_dev *pdev = to_pci_dev(device);
7792         struct net_device *dev = pci_get_drvdata(pdev);
7793         struct bnxt *bp = netdev_priv(dev);
7794         int rc = 0;
7795
7796         rtnl_lock();
7797         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
7798                 rc = -ENODEV;
7799                 goto resume_exit;
7800         }
7801         rc = bnxt_hwrm_func_reset(bp);
7802         if (rc) {
7803                 rc = -EBUSY;
7804                 goto resume_exit;
7805         }
7806         bnxt_get_wol_settings(bp);
7807         if (netif_running(dev)) {
7808                 rc = bnxt_open(dev);
7809                 if (!rc)
7810                         netif_device_attach(dev);
7811         }
7812
7813 resume_exit:
7814         rtnl_unlock();
7815         return rc;
7816 }
7817
7818 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
7819 #define BNXT_PM_OPS (&bnxt_pm_ops)
7820
7821 #else
7822
7823 #define BNXT_PM_OPS NULL
7824
7825 #endif /* CONFIG_PM_SLEEP */
7826
7827 /**
7828  * bnxt_io_error_detected - called when PCI error is detected
7829  * @pdev: Pointer to PCI device
7830  * @state: The current pci connection state
7831  *
7832  * This function is called after a PCI bus error affecting
7833  * this device has been detected.
7834  */
7835 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7836                                                pci_channel_state_t state)
7837 {
7838         struct net_device *netdev = pci_get_drvdata(pdev);
7839         struct bnxt *bp = netdev_priv(netdev);
7840
7841         netdev_info(netdev, "PCI I/O error detected\n");
7842
7843         rtnl_lock();
7844         netif_device_detach(netdev);
7845
7846         bnxt_ulp_stop(bp);
7847
7848         if (state == pci_channel_io_perm_failure) {
7849                 rtnl_unlock();
7850                 return PCI_ERS_RESULT_DISCONNECT;
7851         }
7852
7853         if (netif_running(netdev))
7854                 bnxt_close(netdev);
7855
7856         pci_disable_device(pdev);
7857         rtnl_unlock();
7858
7859         /* Request a slot slot reset. */
7860         return PCI_ERS_RESULT_NEED_RESET;
7861 }
7862
7863 /**
7864  * bnxt_io_slot_reset - called after the pci bus has been reset.
7865  * @pdev: Pointer to PCI device
7866  *
7867  * Restart the card from scratch, as if from a cold-boot.
7868  * At this point, the card has exprienced a hard reset,
7869  * followed by fixups by BIOS, and has its config space
7870  * set up identically to what it was at cold boot.
7871  */
7872 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7873 {
7874         struct net_device *netdev = pci_get_drvdata(pdev);
7875         struct bnxt *bp = netdev_priv(netdev);
7876         int err = 0;
7877         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7878
7879         netdev_info(bp->dev, "PCI Slot Reset\n");
7880
7881         rtnl_lock();
7882
7883         if (pci_enable_device(pdev)) {
7884                 dev_err(&pdev->dev,
7885                         "Cannot re-enable PCI device after reset.\n");
7886         } else {
7887                 pci_set_master(pdev);
7888
7889                 err = bnxt_hwrm_func_reset(bp);
7890                 if (!err && netif_running(netdev))
7891                         err = bnxt_open(netdev);
7892
7893                 if (!err) {
7894                         result = PCI_ERS_RESULT_RECOVERED;
7895                         bnxt_ulp_start(bp);
7896                 }
7897         }
7898
7899         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7900                 dev_close(netdev);
7901
7902         rtnl_unlock();
7903
7904         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7905         if (err) {
7906                 dev_err(&pdev->dev,
7907                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7908                          err); /* non-fatal, continue */
7909         }
7910
7911         return PCI_ERS_RESULT_RECOVERED;
7912 }
7913
7914 /**
7915  * bnxt_io_resume - called when traffic can start flowing again.
7916  * @pdev: Pointer to PCI device
7917  *
7918  * This callback is called when the error recovery driver tells
7919  * us that its OK to resume normal operation.
7920  */
7921 static void bnxt_io_resume(struct pci_dev *pdev)
7922 {
7923         struct net_device *netdev = pci_get_drvdata(pdev);
7924
7925         rtnl_lock();
7926
7927         netif_device_attach(netdev);
7928
7929         rtnl_unlock();
7930 }
7931
7932 static const struct pci_error_handlers bnxt_err_handler = {
7933         .error_detected = bnxt_io_error_detected,
7934         .slot_reset     = bnxt_io_slot_reset,
7935         .resume         = bnxt_io_resume
7936 };
7937
7938 static struct pci_driver bnxt_pci_driver = {
7939         .name           = DRV_MODULE_NAME,
7940         .id_table       = bnxt_pci_tbl,
7941         .probe          = bnxt_init_one,
7942         .remove         = bnxt_remove_one,
7943         .shutdown       = bnxt_shutdown,
7944         .driver.pm      = BNXT_PM_OPS,
7945         .err_handler    = &bnxt_err_handler,
7946 #if defined(CONFIG_BNXT_SRIOV)
7947         .sriov_configure = bnxt_sriov_configure,
7948 #endif
7949 };
7950
7951 module_pci_driver(bnxt_pci_driver);