drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 92
  73
  74 enum board_idx {
  75         BCM57301,
  76         BCM57302,
  77         BCM57304,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57304_VF,
  82         BCM57404_VF,
  83 };
  84
  85 /* indexed by enum above */
  86 static const struct {
  87         char *name;
  88 } board_info[] = {
  89         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  90         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
  91         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  92         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
  93         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  94         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
  95         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
  96         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
  97 };
  98
  99 static const struct pci_device_id bnxt_pci_tbl[] = {
 100         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 101         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 102         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 103         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 104         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 105         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 106 #ifdef CONFIG_BNXT_SRIOV
 107         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 108         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 109 #endif
 110         { 0 }
 111 };
 112
 113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 114
 115 static const u16 bnxt_vf_req_snif[] = {
 116         HWRM_FUNC_CFG,
 117         HWRM_PORT_PHY_QCFG,
 118         HWRM_CFA_L2_FILTER_ALLOC,
 119 };
 120
 121 static bool bnxt_vf_pciid(enum board_idx idx)
 122 {
 123         return (idx == BCM57304_VF || idx == BCM57404_VF);
 124 }
 125
 126 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 127 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 128 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 129
 130 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 131                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 132
 133 #define BNXT_CP_DB(db, raw_cons)                                        \
 134                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 135
 136 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 137                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 138
 139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 140 {
 141         /* Tell compiler to fetch tx indices from memory. */
 142         barrier();
 143
 144         return bp->tx_ring_size -
 145                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 146 }
 147
 148 static const u16 bnxt_lhint_arr[] = {
 149         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 150         TX_BD_FLAGS_LHINT_512_TO_1023,
 151         TX_BD_FLAGS_LHINT_1024_TO_2047,
 152         TX_BD_FLAGS_LHINT_1024_TO_2047,
 153         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 154         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 155         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 156         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 157         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 158         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 159         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 160         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 161         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 162         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 163         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 164         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 165         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 166         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 167         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 168 };
 169
 170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 171 {
 172         struct bnxt *bp = netdev_priv(dev);
 173         struct tx_bd *txbd;
 174         struct tx_bd_ext *txbd1;
 175         struct netdev_queue *txq;
 176         int i;
 177         dma_addr_t mapping;
 178         unsigned int length, pad = 0;
 179         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 180         u16 prod, last_frag;
 181         struct pci_dev *pdev = bp->pdev;
 182         struct bnxt_tx_ring_info *txr;
 183         struct bnxt_sw_tx_bd *tx_buf;
 184
 185         i = skb_get_queue_mapping(skb);
 186         if (unlikely(i >= bp->tx_nr_rings)) {
 187                 dev_kfree_skb_any(skb);
 188                 return NETDEV_TX_OK;
 189         }
 190
 191         txr = &bp->tx_ring[i];
 192         txq = netdev_get_tx_queue(dev, i);
 193         prod = txr->tx_prod;
 194
 195         free_size = bnxt_tx_avail(bp, txr);
 196         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 197                 netif_tx_stop_queue(txq);
 198                 return NETDEV_TX_BUSY;
 199         }
 200
 201         length = skb->len;
 202         len = skb_headlen(skb);
 203         last_frag = skb_shinfo(skb)->nr_frags;
 204
 205         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 206
 207         txbd->tx_bd_opaque = prod;
 208
 209         tx_buf = &txr->tx_buf_ring[prod];
 210         tx_buf->skb = skb;
 211         tx_buf->nr_frags = last_frag;
 212
 213         vlan_tag_flags = 0;
 214         cfa_action = 0;
 215         if (skb_vlan_tag_present(skb)) {
 216                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 217                                  skb_vlan_tag_get(skb);
 218                 /* Currently supports 8021Q, 8021AD vlan offloads
 219                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 220                  */
 221                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 222                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 223         }
 224
 225         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 226                 struct tx_push_bd *push = txr->tx_push;
 227                 struct tx_bd *tx_push = &push->txbd1;
 228                 struct tx_bd_ext *tx_push1 = &push->txbd2;
 229                 void *pdata = tx_push1 + 1;
 230                 int j;
 231
 232                 /* Set COAL_NOW to be ready quickly for the next push */
 233                 tx_push->tx_bd_len_flags_type =
 234                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 235                                         TX_BD_TYPE_LONG_TX_BD |
 236                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 237                                         TX_BD_FLAGS_COAL_NOW |
 238                                         TX_BD_FLAGS_PACKET_END |
 239                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 240
 241                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 242                         tx_push1->tx_bd_hsize_lflags =
 243                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 244                 else
 245                         tx_push1->tx_bd_hsize_lflags = 0;
 246
 247                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 248                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 249
 250                 skb_copy_from_linear_data(skb, pdata, len);
 251                 pdata += len;
 252                 for (j = 0; j < last_frag; j++) {
 253                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 254                         void *fptr;
 255
 256                         fptr = skb_frag_address_safe(frag);
 257                         if (!fptr)
 258                                 goto normal_tx;
 259
 260                         memcpy(pdata, fptr, skb_frag_size(frag));
 261                         pdata += skb_frag_size(frag);
 262                 }
 263
 264                 memcpy(txbd, tx_push, sizeof(*txbd));
 265                 prod = NEXT_TX(prod);
 266                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 267                 memcpy(txbd, tx_push1, sizeof(*txbd));
 268                 prod = NEXT_TX(prod);
 269                 push->doorbell =
 270                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 271                 txr->tx_prod = prod;
 272
 273                 netdev_tx_sent_queue(txq, skb->len);
 274
 275                 __iowrite64_copy(txr->tx_doorbell, push,
 276                                  (length + sizeof(*push) + 8) / 8);
 277
 278                 tx_buf->is_push = 1;
 279
 280                 goto tx_done;
 281         }
 282
 283 normal_tx:
 284         if (length < BNXT_MIN_PKT_SIZE) {
 285                 pad = BNXT_MIN_PKT_SIZE - length;
 286                 if (skb_pad(skb, pad)) {
 287                         /* SKB already freed. */
 288                         tx_buf->skb = NULL;
 289                         return NETDEV_TX_OK;
 290                 }
 291                 length = BNXT_MIN_PKT_SIZE;
 292         }
 293
 294         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 295
 296         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 297                 dev_kfree_skb_any(skb);
 298                 tx_buf->skb = NULL;
 299                 return NETDEV_TX_OK;
 300         }
 301
 302         dma_unmap_addr_set(tx_buf, mapping, mapping);
 303         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 304                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 305
 306         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 307
 308         prod = NEXT_TX(prod);
 309         txbd1 = (struct tx_bd_ext *)
 310                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 311
 312         txbd1->tx_bd_hsize_lflags = 0;
 313         if (skb_is_gso(skb)) {
 314                 u32 hdr_len;
 315
 316                 if (skb->encapsulation)
 317                         hdr_len = skb_inner_network_offset(skb) +
 318                                 skb_inner_network_header_len(skb) +
 319                                 inner_tcp_hdrlen(skb);
 320                 else
 321                         hdr_len = skb_transport_offset(skb) +
 322                                 tcp_hdrlen(skb);
 323
 324                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 325                                         TX_BD_FLAGS_T_IPID |
 326                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 327                 length = skb_shinfo(skb)->gso_size;
 328                 txbd1->tx_bd_mss = cpu_to_le32(length);
 329                 length += hdr_len;
 330         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 331                 txbd1->tx_bd_hsize_lflags =
 332                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 333                 txbd1->tx_bd_mss = 0;
 334         }
 335
 336         length >>= 9;
 337         flags |= bnxt_lhint_arr[length];
 338         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 339
 340         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 341         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 342         for (i = 0; i < last_frag; i++) {
 343                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 344
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347
 348                 len = skb_frag_size(frag);
 349                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 350                                            DMA_TO_DEVICE);
 351
 352                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 353                         goto tx_dma_error;
 354
 355                 tx_buf = &txr->tx_buf_ring[prod];
 356                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 357
 358                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 359
 360                 flags = len << TX_BD_LEN_SHIFT;
 361                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 362         }
 363
 364         flags &= ~TX_BD_LEN;
 365         txbd->tx_bd_len_flags_type =
 366                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 367                             TX_BD_FLAGS_PACKET_END);
 368
 369         netdev_tx_sent_queue(txq, skb->len);
 370
 371         /* Sync BD data before updating doorbell */
 372         wmb();
 373
 374         prod = NEXT_TX(prod);
 375         txr->tx_prod = prod;
 376
 377         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 378         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 379
 380 tx_done:
 381
 382         mmiowb();
 383
 384         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 385                 netif_tx_stop_queue(txq);
 386
 387                 /* netif_tx_stop_queue() must be done before checking
 388                  * tx index in bnxt_tx_avail() below, because in
 389                  * bnxt_tx_int(), we update tx index before checking for
 390                  * netif_tx_queue_stopped().
 391                  */
 392                 smp_mb();
 393                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 394                         netif_tx_wake_queue(txq);
 395         }
 396         return NETDEV_TX_OK;
 397
 398 tx_dma_error:
 399         last_frag = i;
 400
 401         /* start back at beginning and unmap skb */
 402         prod = txr->tx_prod;
 403         tx_buf = &txr->tx_buf_ring[prod];
 404         tx_buf->skb = NULL;
 405         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 406                          skb_headlen(skb), PCI_DMA_TODEVICE);
 407         prod = NEXT_TX(prod);
 408
 409         /* unmap remaining mapped pages */
 410         for (i = 0; i < last_frag; i++) {
 411                 prod = NEXT_TX(prod);
 412                 tx_buf = &txr->tx_buf_ring[prod];
 413                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 414                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 415                                PCI_DMA_TODEVICE);
 416         }
 417
 418         dev_kfree_skb_any(skb);
 419         return NETDEV_TX_OK;
 420 }
 421
 422 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 423 {
 424         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 425         int index = txr - &bp->tx_ring[0];
 426         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 427         u16 cons = txr->tx_cons;
 428         struct pci_dev *pdev = bp->pdev;
 429         int i;
 430         unsigned int tx_bytes = 0;
 431
 432         for (i = 0; i < nr_pkts; i++) {
 433                 struct bnxt_sw_tx_bd *tx_buf;
 434                 struct sk_buff *skb;
 435                 int j, last;
 436
 437                 tx_buf = &txr->tx_buf_ring[cons];
 438                 cons = NEXT_TX(cons);
 439                 skb = tx_buf->skb;
 440                 tx_buf->skb = NULL;
 441
 442                 if (tx_buf->is_push) {
 443                         tx_buf->is_push = 0;
 444                         goto next_tx_int;
 445                 }
 446
 447                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 448                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 449                 last = tx_buf->nr_frags;
 450
 451                 for (j = 0; j < last; j++) {
 452                         cons = NEXT_TX(cons);
 453                         tx_buf = &txr->tx_buf_ring[cons];
 454                         dma_unmap_page(
 455                                 &pdev->dev,
 456                                 dma_unmap_addr(tx_buf, mapping),
 457                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 458                                 PCI_DMA_TODEVICE);
 459                 }
 460
 461 next_tx_int:
 462                 cons = NEXT_TX(cons);
 463
 464                 tx_bytes += skb->len;
 465                 dev_kfree_skb_any(skb);
 466         }
 467
 468         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 469         txr->tx_cons = cons;
 470
 471         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 472          * before checking for netif_tx_queue_stopped().  Without the
 473          * memory barrier, there is a small possibility that bnxt_start_xmit()
 474          * will miss it and cause the queue to be stopped forever.
 475          */
 476         smp_mb();
 477
 478         if (unlikely(netif_tx_queue_stopped(txq)) &&
 479             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 480                 __netif_tx_lock(txq, smp_processor_id());
 481                 if (netif_tx_queue_stopped(txq) &&
 482                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 483                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 484                         netif_tx_wake_queue(txq);
 485                 __netif_tx_unlock(txq);
 486         }
 487 }
 488
 489 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 490                                        gfp_t gfp)
 491 {
 492         u8 *data;
 493         struct pci_dev *pdev = bp->pdev;
 494
 495         data = kmalloc(bp->rx_buf_size, gfp);
 496         if (!data)
 497                 return NULL;
 498
 499         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 500                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 501
 502         if (dma_mapping_error(&pdev->dev, *mapping)) {
 503                 kfree(data);
 504                 data = NULL;
 505         }
 506         return data;
 507 }
 508
 509 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 510                                      struct bnxt_rx_ring_info *rxr,
 511                                      u16 prod, gfp_t gfp)
 512 {
 513         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 514         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 515         u8 *data;
 516         dma_addr_t mapping;
 517
 518         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 519         if (!data)
 520                 return -ENOMEM;
 521
 522         rx_buf->data = data;
 523         dma_unmap_addr_set(rx_buf, mapping, mapping);
 524
 525         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 526
 527         return 0;
 528 }
 529
 530 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 531                                u8 *data)
 532 {
 533         u16 prod = rxr->rx_prod;
 534         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 535         struct rx_bd *cons_bd, *prod_bd;
 536
 537         prod_rx_buf = &rxr->rx_buf_ring[prod];
 538         cons_rx_buf = &rxr->rx_buf_ring[cons];
 539
 540         prod_rx_buf->data = data;
 541
 542         dma_unmap_addr_set(prod_rx_buf, mapping,
 543                            dma_unmap_addr(cons_rx_buf, mapping));
 544
 545         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 546         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 547
 548         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 549 }
 550
 551 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 552 {
 553         u16 next, max = rxr->rx_agg_bmap_size;
 554
 555         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 556         if (next >= max)
 557                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 558         return next;
 559 }
 560
 561 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 562                                      struct bnxt_rx_ring_info *rxr,
 563                                      u16 prod, gfp_t gfp)
 564 {
 565         struct rx_bd *rxbd =
 566                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 567         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 568         struct pci_dev *pdev = bp->pdev;
 569         struct page *page;
 570         dma_addr_t mapping;
 571         u16 sw_prod = rxr->rx_sw_agg_prod;
 572
 573         page = alloc_page(gfp);
 574         if (!page)
 575                 return -ENOMEM;
 576
 577         mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
 578                                PCI_DMA_FROMDEVICE);
 579         if (dma_mapping_error(&pdev->dev, mapping)) {
 580                 __free_page(page);
 581                 return -EIO;
 582         }
 583
 584         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 585                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 586
 587         __set_bit(sw_prod, rxr->rx_agg_bmap);
 588         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 589         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 590
 591         rx_agg_buf->page = page;
 592         rx_agg_buf->mapping = mapping;
 593         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 594         rxbd->rx_bd_opaque = sw_prod;
 595         return 0;
 596 }
 597
 598 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 599                                    u32 agg_bufs)
 600 {
 601         struct bnxt *bp = bnapi->bp;
 602         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 603         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 604         u16 prod = rxr->rx_agg_prod;
 605         u16 sw_prod = rxr->rx_sw_agg_prod;
 606         u32 i;
 607
 608         for (i = 0; i < agg_bufs; i++) {
 609                 u16 cons;
 610                 struct rx_agg_cmp *agg;
 611                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 612                 struct rx_bd *prod_bd;
 613                 struct page *page;
 614
 615                 agg = (struct rx_agg_cmp *)
 616                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 617                 cons = agg->rx_agg_cmp_opaque;
 618                 __clear_bit(cons, rxr->rx_agg_bmap);
 619
 620                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 621                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 622
 623                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 624                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 625                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 626
 627                 /* It is possible for sw_prod to be equal to cons, so
 628                  * set cons_rx_buf->page to NULL first.
 629                  */
 630                 page = cons_rx_buf->page;
 631                 cons_rx_buf->page = NULL;
 632                 prod_rx_buf->page = page;
 633
 634                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 635
 636                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 637
 638                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 639                 prod_bd->rx_bd_opaque = sw_prod;
 640
 641                 prod = NEXT_RX_AGG(prod);
 642                 sw_prod = NEXT_RX_AGG(sw_prod);
 643                 cp_cons = NEXT_CMP(cp_cons);
 644         }
 645         rxr->rx_agg_prod = prod;
 646         rxr->rx_sw_agg_prod = sw_prod;
 647 }
 648
 649 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 650                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 651                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 652                                    unsigned int len)
 653 {
 654         int err;
 655         struct sk_buff *skb;
 656
 657         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 658         if (unlikely(err)) {
 659                 bnxt_reuse_rx_data(rxr, cons, data);
 660                 return NULL;
 661         }
 662
 663         skb = build_skb(data, 0);
 664         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 665                          PCI_DMA_FROMDEVICE);
 666         if (!skb) {
 667                 kfree(data);
 668                 return NULL;
 669         }
 670
 671         skb_reserve(skb, BNXT_RX_OFFSET);
 672         skb_put(skb, len);
 673         return skb;
 674 }
 675
 676 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 677                                      struct sk_buff *skb, u16 cp_cons,
 678                                      u32 agg_bufs)
 679 {
 680         struct pci_dev *pdev = bp->pdev;
 681         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 682         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 683         u16 prod = rxr->rx_agg_prod;
 684         u32 i;
 685
 686         for (i = 0; i < agg_bufs; i++) {
 687                 u16 cons, frag_len;
 688                 struct rx_agg_cmp *agg;
 689                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 690                 struct page *page;
 691                 dma_addr_t mapping;
 692
 693                 agg = (struct rx_agg_cmp *)
 694                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 695                 cons = agg->rx_agg_cmp_opaque;
 696                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 697                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 698
 699                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 700                 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
 701                 __clear_bit(cons, rxr->rx_agg_bmap);
 702
 703                 /* It is possible for bnxt_alloc_rx_page() to allocate
 704                  * a sw_prod index that equals the cons index, so we
 705                  * need to clear the cons entry now.
 706                  */
 707                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 708                 page = cons_rx_buf->page;
 709                 cons_rx_buf->page = NULL;
 710
 711                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 712                         struct skb_shared_info *shinfo;
 713                         unsigned int nr_frags;
 714
 715                         shinfo = skb_shinfo(skb);
 716                         nr_frags = --shinfo->nr_frags;
 717                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 718
 719                         dev_kfree_skb(skb);
 720
 721                         cons_rx_buf->page = page;
 722
 723                         /* Update prod since possibly some pages have been
 724                          * allocated already.
 725                          */
 726                         rxr->rx_agg_prod = prod;
 727                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 728                         return NULL;
 729                 }
 730
 731                 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
 732                                PCI_DMA_FROMDEVICE);
 733
 734                 skb->data_len += frag_len;
 735                 skb->len += frag_len;
 736                 skb->truesize += PAGE_SIZE;
 737
 738                 prod = NEXT_RX_AGG(prod);
 739                 cp_cons = NEXT_CMP(cp_cons);
 740         }
 741         rxr->rx_agg_prod = prod;
 742         return skb;
 743 }
 744
 745 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 746                                u8 agg_bufs, u32 *raw_cons)
 747 {
 748         u16 last;
 749         struct rx_agg_cmp *agg;
 750
 751         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 752         last = RING_CMP(*raw_cons);
 753         agg = (struct rx_agg_cmp *)
 754                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 755         return RX_AGG_CMP_VALID(agg, *raw_cons);
 756 }
 757
 758 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 759                                             unsigned int len,
 760                                             dma_addr_t mapping)
 761 {
 762         struct bnxt *bp = bnapi->bp;
 763         struct pci_dev *pdev = bp->pdev;
 764         struct sk_buff *skb;
 765
 766         skb = napi_alloc_skb(&bnapi->napi, len);
 767         if (!skb)
 768                 return NULL;
 769
 770         dma_sync_single_for_cpu(&pdev->dev, mapping,
 771                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 772
 773         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 774
 775         dma_sync_single_for_device(&pdev->dev, mapping,
 776                                    bp->rx_copy_thresh,
 777                                    PCI_DMA_FROMDEVICE);
 778
 779         skb_put(skb, len);
 780         return skb;
 781 }
 782
 783 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 784                            struct rx_tpa_start_cmp *tpa_start,
 785                            struct rx_tpa_start_cmp_ext *tpa_start1)
 786 {
 787         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 788         u16 cons, prod;
 789         struct bnxt_tpa_info *tpa_info;
 790         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 791         struct rx_bd *prod_bd;
 792         dma_addr_t mapping;
 793
 794         cons = tpa_start->rx_tpa_start_cmp_opaque;
 795         prod = rxr->rx_prod;
 796         cons_rx_buf = &rxr->rx_buf_ring[cons];
 797         prod_rx_buf = &rxr->rx_buf_ring[prod];
 798         tpa_info = &rxr->rx_tpa[agg_id];
 799
 800         prod_rx_buf->data = tpa_info->data;
 801
 802         mapping = tpa_info->mapping;
 803         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 804
 805         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 806
 807         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 808
 809         tpa_info->data = cons_rx_buf->data;
 810         cons_rx_buf->data = NULL;
 811         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 812
 813         tpa_info->len =
 814                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 815                                 RX_TPA_START_CMP_LEN_SHIFT;
 816         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 817                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 818
 819                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 820                 tpa_info->gso_type = SKB_GSO_TCPV4;
 821                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 822                 if (hash_type == 3)
 823                         tpa_info->gso_type = SKB_GSO_TCPV6;
 824                 tpa_info->rss_hash =
 825                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 826         } else {
 827                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 828                 tpa_info->gso_type = 0;
 829                 if (netif_msg_rx_err(bp))
 830                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 831         }
 832         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 833         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 834
 835         rxr->rx_prod = NEXT_RX(prod);
 836         cons = NEXT_RX(cons);
 837         cons_rx_buf = &rxr->rx_buf_ring[cons];
 838
 839         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 840         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 841         cons_rx_buf->data = NULL;
 842 }
 843
 844 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 845                            u16 cp_cons, u32 agg_bufs)
 846 {
 847         if (agg_bufs)
 848                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 849 }
 850
 851 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 852 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 853
 854 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 855                                            struct rx_tpa_end_cmp *tpa_end,
 856                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 857                                            struct sk_buff *skb)
 858 {
 859 #ifdef CONFIG_INET
 860         struct tcphdr *th;
 861         int payload_off, tcp_opt_len = 0;
 862         int len, nw_off;
 863         u16 segs;
 864
 865         segs = TPA_END_TPA_SEGS(tpa_end);
 866         if (segs == 1)
 867                 return skb;
 868
 869         NAPI_GRO_CB(skb)->count = segs;
 870         skb_shinfo(skb)->gso_size =
 871                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 872         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 873         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 874                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 875                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 876         if (TPA_END_GRO_TS(tpa_end))
 877                 tcp_opt_len = 12;
 878
 879         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 880                 struct iphdr *iph;
 881
 882                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 883                          ETH_HLEN;
 884                 skb_set_network_header(skb, nw_off);
 885                 iph = ip_hdr(skb);
 886                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 887                 len = skb->len - skb_transport_offset(skb);
 888                 th = tcp_hdr(skb);
 889                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 890         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 891                 struct ipv6hdr *iph;
 892
 893                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 894                          ETH_HLEN;
 895                 skb_set_network_header(skb, nw_off);
 896                 iph = ipv6_hdr(skb);
 897                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 898                 len = skb->len - skb_transport_offset(skb);
 899                 th = tcp_hdr(skb);
 900                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 901         } else {
 902                 dev_kfree_skb_any(skb);
 903                 return NULL;
 904         }
 905         tcp_gro_complete(skb);
 906
 907         if (nw_off) { /* tunnel */
 908                 struct udphdr *uh = NULL;
 909
 910                 if (skb->protocol == htons(ETH_P_IP)) {
 911                         struct iphdr *iph = (struct iphdr *)skb->data;
 912
 913                         if (iph->protocol == IPPROTO_UDP)
 914                                 uh = (struct udphdr *)(iph + 1);
 915                 } else {
 916                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
 917
 918                         if (iph->nexthdr == IPPROTO_UDP)
 919                                 uh = (struct udphdr *)(iph + 1);
 920                 }
 921                 if (uh) {
 922                         if (uh->check)
 923                                 skb_shinfo(skb)->gso_type |=
 924                                         SKB_GSO_UDP_TUNNEL_CSUM;
 925                         else
 926                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
 927                 }
 928         }
 929 #endif
 930         return skb;
 931 }
 932
 933 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
 934                                            struct bnxt_napi *bnapi,
 935                                            u32 *raw_cons,
 936                                            struct rx_tpa_end_cmp *tpa_end,
 937                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 938                                            bool *agg_event)
 939 {
 940         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 941         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 942         u8 agg_id = TPA_END_AGG_ID(tpa_end);
 943         u8 *data, agg_bufs;
 944         u16 cp_cons = RING_CMP(*raw_cons);
 945         unsigned int len;
 946         struct bnxt_tpa_info *tpa_info;
 947         dma_addr_t mapping;
 948         struct sk_buff *skb;
 949
 950         tpa_info = &rxr->rx_tpa[agg_id];
 951         data = tpa_info->data;
 952         prefetch(data);
 953         len = tpa_info->len;
 954         mapping = tpa_info->mapping;
 955
 956         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 957                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 958
 959         if (agg_bufs) {
 960                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
 961                         return ERR_PTR(-EBUSY);
 962
 963                 *agg_event = true;
 964                 cp_cons = NEXT_CMP(cp_cons);
 965         }
 966
 967         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
 968                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 969                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
 970                             agg_bufs, (int)MAX_SKB_FRAGS);
 971                 return NULL;
 972         }
 973
 974         if (len <= bp->rx_copy_thresh) {
 975                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
 976                 if (!skb) {
 977                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 978                         return NULL;
 979                 }
 980         } else {
 981                 u8 *new_data;
 982                 dma_addr_t new_mapping;
 983
 984                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
 985                 if (!new_data) {
 986                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 987                         return NULL;
 988                 }
 989
 990                 tpa_info->data = new_data;
 991                 tpa_info->mapping = new_mapping;
 992
 993                 skb = build_skb(data, 0);
 994                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
 995                                  PCI_DMA_FROMDEVICE);
 996
 997                 if (!skb) {
 998                         kfree(data);
 999                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1000                         return NULL;
1001                 }
1002                 skb_reserve(skb, BNXT_RX_OFFSET);
1003                 skb_put(skb, len);
1004         }
1005
1006         if (agg_bufs) {
1007                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1008                 if (!skb) {
1009                         /* Page reuse already handled by bnxt_rx_pages(). */
1010                         return NULL;
1011                 }
1012         }
1013         skb->protocol = eth_type_trans(skb, bp->dev);
1014
1015         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1016                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1017
1018         if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1019                 netdev_features_t features = skb->dev->features;
1020                 u16 vlan_proto = tpa_info->metadata >>
1021                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1022
1023                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1024                      vlan_proto == ETH_P_8021Q) ||
1025                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1026                      vlan_proto == ETH_P_8021AD)) {
1027                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1028                                                tpa_info->metadata &
1029                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1030                 }
1031         }
1032
1033         skb_checksum_none_assert(skb);
1034         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1035                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1036                 skb->csum_level =
1037                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1038         }
1039
1040         if (TPA_END_GRO(tpa_end))
1041                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1042
1043         return skb;
1044 }
1045
1046 /* returns the following:
1047  * 1       - 1 packet successfully received
1048  * 0       - successful TPA_START, packet not completed yet
1049  * -EBUSY  - completion ring does not have all the agg buffers yet
1050  * -ENOMEM - packet aborted due to out of memory
1051  * -EIO    - packet aborted due to hw error indicated in BD
1052  */
1053 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1054                        bool *agg_event)
1055 {
1056         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1057         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1058         struct net_device *dev = bp->dev;
1059         struct rx_cmp *rxcmp;
1060         struct rx_cmp_ext *rxcmp1;
1061         u32 tmp_raw_cons = *raw_cons;
1062         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1063         struct bnxt_sw_rx_bd *rx_buf;
1064         unsigned int len;
1065         u8 *data, agg_bufs, cmp_type;
1066         dma_addr_t dma_addr;
1067         struct sk_buff *skb;
1068         int rc = 0;
1069
1070         rxcmp = (struct rx_cmp *)
1071                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1072
1073         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1074         cp_cons = RING_CMP(tmp_raw_cons);
1075         rxcmp1 = (struct rx_cmp_ext *)
1076                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1077
1078         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1079                 return -EBUSY;
1080
1081         cmp_type = RX_CMP_TYPE(rxcmp);
1082
1083         prod = rxr->rx_prod;
1084
1085         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1086                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1087                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1088
1089                 goto next_rx_no_prod;
1090
1091         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1092                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1093                                    (struct rx_tpa_end_cmp *)rxcmp,
1094                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1095                                    agg_event);
1096
1097                 if (unlikely(IS_ERR(skb)))
1098                         return -EBUSY;
1099
1100                 rc = -ENOMEM;
1101                 if (likely(skb)) {
1102                         skb_record_rx_queue(skb, bnapi->index);
1103                         skb_mark_napi_id(skb, &bnapi->napi);
1104                         if (bnxt_busy_polling(bnapi))
1105                                 netif_receive_skb(skb);
1106                         else
1107                                 napi_gro_receive(&bnapi->napi, skb);
1108                         rc = 1;
1109                 }
1110                 goto next_rx_no_prod;
1111         }
1112
1113         cons = rxcmp->rx_cmp_opaque;
1114         rx_buf = &rxr->rx_buf_ring[cons];
1115         data = rx_buf->data;
1116         prefetch(data);
1117
1118         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1119                                 RX_CMP_AGG_BUFS_SHIFT;
1120
1121         if (agg_bufs) {
1122                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1123                         return -EBUSY;
1124
1125                 cp_cons = NEXT_CMP(cp_cons);
1126                 *agg_event = true;
1127         }
1128
1129         rx_buf->data = NULL;
1130         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1131                 bnxt_reuse_rx_data(rxr, cons, data);
1132                 if (agg_bufs)
1133                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1134
1135                 rc = -EIO;
1136                 goto next_rx;
1137         }
1138
1139         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1140         dma_addr = dma_unmap_addr(rx_buf, mapping);
1141
1142         if (len <= bp->rx_copy_thresh) {
1143                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1144                 bnxt_reuse_rx_data(rxr, cons, data);
1145                 if (!skb) {
1146                         rc = -ENOMEM;
1147                         goto next_rx;
1148                 }
1149         } else {
1150                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1151                 if (!skb) {
1152                         rc = -ENOMEM;
1153                         goto next_rx;
1154                 }
1155         }
1156
1157         if (agg_bufs) {
1158                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1159                 if (!skb) {
1160                         rc = -ENOMEM;
1161                         goto next_rx;
1162                 }
1163         }
1164
1165         if (RX_CMP_HASH_VALID(rxcmp)) {
1166                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1167                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1168
1169                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1170                 if (hash_type != 1 && hash_type != 3)
1171                         type = PKT_HASH_TYPE_L3;
1172                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1173         }
1174
1175         skb->protocol = eth_type_trans(skb, dev);
1176
1177         if (rxcmp1->rx_cmp_flags2 &
1178             cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1179                 netdev_features_t features = skb->dev->features;
1180                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1181                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1182
1183                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1184                      vlan_proto == ETH_P_8021Q) ||
1185                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1186                      vlan_proto == ETH_P_8021AD))
1187                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1188                                                meta_data &
1189                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1190         }
1191
1192         skb_checksum_none_assert(skb);
1193         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1194                 if (dev->features & NETIF_F_RXCSUM) {
1195                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1196                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1197                 }
1198         } else {
1199                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1200                         if (dev->features & NETIF_F_RXCSUM)
1201                                 cpr->rx_l4_csum_errors++;
1202                 }
1203         }
1204
1205         skb_record_rx_queue(skb, bnapi->index);
1206         skb_mark_napi_id(skb, &bnapi->napi);
1207         if (bnxt_busy_polling(bnapi))
1208                 netif_receive_skb(skb);
1209         else
1210                 napi_gro_receive(&bnapi->napi, skb);
1211         rc = 1;
1212
1213 next_rx:
1214         rxr->rx_prod = NEXT_RX(prod);
1215
1216 next_rx_no_prod:
1217         *raw_cons = tmp_raw_cons;
1218
1219         return rc;
1220 }
1221
1222 static int bnxt_async_event_process(struct bnxt *bp,
1223                                     struct hwrm_async_event_cmpl *cmpl)
1224 {
1225         u16 event_id = le16_to_cpu(cmpl->event_id);
1226
1227         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1228         switch (event_id) {
1229         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1230                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1231                 schedule_work(&bp->sp_task);
1232                 break;
1233         default:
1234                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1235                            event_id);
1236                 break;
1237         }
1238         return 0;
1239 }
1240
1241 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1242 {
1243         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1244         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1245         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1246                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1247
1248         switch (cmpl_type) {
1249         case CMPL_BASE_TYPE_HWRM_DONE:
1250                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1251                 if (seq_id == bp->hwrm_intr_seq_id)
1252                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1253                 else
1254                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1255                 break;
1256
1257         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1258                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1259
1260                 if ((vf_id < bp->pf.first_vf_id) ||
1261                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1262                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1263                                    vf_id);
1264                         return -EINVAL;
1265                 }
1266
1267                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1268                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1269                 schedule_work(&bp->sp_task);
1270                 break;
1271
1272         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1273                 bnxt_async_event_process(bp,
1274                                          (struct hwrm_async_event_cmpl *)txcmp);
1275
1276         default:
1277                 break;
1278         }
1279
1280         return 0;
1281 }
1282
1283 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1284 {
1285         struct bnxt_napi *bnapi = dev_instance;
1286         struct bnxt *bp = bnapi->bp;
1287         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1288         u32 cons = RING_CMP(cpr->cp_raw_cons);
1289
1290         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1291         napi_schedule(&bnapi->napi);
1292         return IRQ_HANDLED;
1293 }
1294
1295 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1296 {
1297         u32 raw_cons = cpr->cp_raw_cons;
1298         u16 cons = RING_CMP(raw_cons);
1299         struct tx_cmp *txcmp;
1300
1301         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1302
1303         return TX_CMP_VALID(txcmp, raw_cons);
1304 }
1305
1306 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1307 {
1308         struct bnxt_napi *bnapi = dev_instance;
1309         struct bnxt *bp = bnapi->bp;
1310         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311         u32 cons = RING_CMP(cpr->cp_raw_cons);
1312         u32 int_status;
1313
1314         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1315
1316         if (!bnxt_has_work(bp, cpr)) {
1317                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1318                 /* return if erroneous interrupt */
1319                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1320                         return IRQ_NONE;
1321         }
1322
1323         /* disable ring IRQ */
1324         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1325
1326         /* Return here if interrupt is shared and is disabled. */
1327         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1328                 return IRQ_HANDLED;
1329
1330         napi_schedule(&bnapi->napi);
1331         return IRQ_HANDLED;
1332 }
1333
1334 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1335 {
1336         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1337         u32 raw_cons = cpr->cp_raw_cons;
1338         u32 cons;
1339         int tx_pkts = 0;
1340         int rx_pkts = 0;
1341         bool rx_event = false;
1342         bool agg_event = false;
1343         struct tx_cmp *txcmp;
1344
1345         while (1) {
1346                 int rc;
1347
1348                 cons = RING_CMP(raw_cons);
1349                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1350
1351                 if (!TX_CMP_VALID(txcmp, raw_cons))
1352                         break;
1353
1354                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1355                         tx_pkts++;
1356                         /* return full budget so NAPI will complete. */
1357                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1358                                 rx_pkts = budget;
1359                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1360                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1361                         if (likely(rc >= 0))
1362                                 rx_pkts += rc;
1363                         else if (rc == -EBUSY)  /* partial completion */
1364                                 break;
1365                         rx_event = true;
1366                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1367                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1368                                     (TX_CMP_TYPE(txcmp) ==
1369                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1370                                     (TX_CMP_TYPE(txcmp) ==
1371                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1372                         bnxt_hwrm_handler(bp, txcmp);
1373                 }
1374                 raw_cons = NEXT_RAW_CMP(raw_cons);
1375
1376                 if (rx_pkts == budget)
1377                         break;
1378         }
1379
1380         cpr->cp_raw_cons = raw_cons;
1381         /* ACK completion ring before freeing tx ring and producing new
1382          * buffers in rx/agg rings to prevent overflowing the completion
1383          * ring.
1384          */
1385         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1386
1387         if (tx_pkts)
1388                 bnxt_tx_int(bp, bnapi, tx_pkts);
1389
1390         if (rx_event) {
1391                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1392
1393                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1394                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1395                 if (agg_event) {
1396                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1397                                rxr->rx_agg_doorbell);
1398                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1399                                rxr->rx_agg_doorbell);
1400                 }
1401         }
1402         return rx_pkts;
1403 }
1404
1405 static int bnxt_poll(struct napi_struct *napi, int budget)
1406 {
1407         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1408         struct bnxt *bp = bnapi->bp;
1409         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1410         int work_done = 0;
1411
1412         if (!bnxt_lock_napi(bnapi))
1413                 return budget;
1414
1415         while (1) {
1416                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1417
1418                 if (work_done >= budget)
1419                         break;
1420
1421                 if (!bnxt_has_work(bp, cpr)) {
1422                         napi_complete(napi);
1423                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1424                         break;
1425                 }
1426         }
1427         mmiowb();
1428         bnxt_unlock_napi(bnapi);
1429         return work_done;
1430 }
1431
1432 #ifdef CONFIG_NET_RX_BUSY_POLL
1433 static int bnxt_busy_poll(struct napi_struct *napi)
1434 {
1435         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1436         struct bnxt *bp = bnapi->bp;
1437         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1438         int rx_work, budget = 4;
1439
1440         if (atomic_read(&bp->intr_sem) != 0)
1441                 return LL_FLUSH_FAILED;
1442
1443         if (!bnxt_lock_poll(bnapi))
1444                 return LL_FLUSH_BUSY;
1445
1446         rx_work = bnxt_poll_work(bp, bnapi, budget);
1447
1448         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1449
1450         bnxt_unlock_poll(bnapi);
1451         return rx_work;
1452 }
1453 #endif
1454
1455 static void bnxt_free_tx_skbs(struct bnxt *bp)
1456 {
1457         int i, max_idx;
1458         struct pci_dev *pdev = bp->pdev;
1459
1460         if (!bp->tx_ring)
1461                 return;
1462
1463         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1464         for (i = 0; i < bp->tx_nr_rings; i++) {
1465                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1466                 int j;
1467
1468                 for (j = 0; j < max_idx;) {
1469                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1470                         struct sk_buff *skb = tx_buf->skb;
1471                         int k, last;
1472
1473                         if (!skb) {
1474                                 j++;
1475                                 continue;
1476                         }
1477
1478                         tx_buf->skb = NULL;
1479
1480                         if (tx_buf->is_push) {
1481                                 dev_kfree_skb(skb);
1482                                 j += 2;
1483                                 continue;
1484                         }
1485
1486                         dma_unmap_single(&pdev->dev,
1487                                          dma_unmap_addr(tx_buf, mapping),
1488                                          skb_headlen(skb),
1489                                          PCI_DMA_TODEVICE);
1490
1491                         last = tx_buf->nr_frags;
1492                         j += 2;
1493                         for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1494                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1495
1496                                 tx_buf = &txr->tx_buf_ring[j];
1497                                 dma_unmap_page(
1498                                         &pdev->dev,
1499                                         dma_unmap_addr(tx_buf, mapping),
1500                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1501                         }
1502                         dev_kfree_skb(skb);
1503                 }
1504                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1505         }
1506 }
1507
1508 static void bnxt_free_rx_skbs(struct bnxt *bp)
1509 {
1510         int i, max_idx, max_agg_idx;
1511         struct pci_dev *pdev = bp->pdev;
1512
1513         if (!bp->rx_ring)
1514                 return;
1515
1516         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1517         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1518         for (i = 0; i < bp->rx_nr_rings; i++) {
1519                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1520                 int j;
1521
1522                 if (rxr->rx_tpa) {
1523                         for (j = 0; j < MAX_TPA; j++) {
1524                                 struct bnxt_tpa_info *tpa_info =
1525                                                         &rxr->rx_tpa[j];
1526                                 u8 *data = tpa_info->data;
1527
1528                                 if (!data)
1529                                         continue;
1530
1531                                 dma_unmap_single(
1532                                         &pdev->dev,
1533                                         dma_unmap_addr(tpa_info, mapping),
1534                                         bp->rx_buf_use_size,
1535                                         PCI_DMA_FROMDEVICE);
1536
1537                                 tpa_info->data = NULL;
1538
1539                                 kfree(data);
1540                         }
1541                 }
1542
1543                 for (j = 0; j < max_idx; j++) {
1544                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1545                         u8 *data = rx_buf->data;
1546
1547                         if (!data)
1548                                 continue;
1549
1550                         dma_unmap_single(&pdev->dev,
1551                                          dma_unmap_addr(rx_buf, mapping),
1552                                          bp->rx_buf_use_size,
1553                                          PCI_DMA_FROMDEVICE);
1554
1555                         rx_buf->data = NULL;
1556
1557                         kfree(data);
1558                 }
1559
1560                 for (j = 0; j < max_agg_idx; j++) {
1561                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1562                                 &rxr->rx_agg_ring[j];
1563                         struct page *page = rx_agg_buf->page;
1564
1565                         if (!page)
1566                                 continue;
1567
1568                         dma_unmap_page(&pdev->dev,
1569                                        dma_unmap_addr(rx_agg_buf, mapping),
1570                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
1571
1572                         rx_agg_buf->page = NULL;
1573                         __clear_bit(j, rxr->rx_agg_bmap);
1574
1575                         __free_page(page);
1576                 }
1577         }
1578 }
1579
1580 static void bnxt_free_skbs(struct bnxt *bp)
1581 {
1582         bnxt_free_tx_skbs(bp);
1583         bnxt_free_rx_skbs(bp);
1584 }
1585
1586 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1587 {
1588         struct pci_dev *pdev = bp->pdev;
1589         int i;
1590
1591         for (i = 0; i < ring->nr_pages; i++) {
1592                 if (!ring->pg_arr[i])
1593                         continue;
1594
1595                 dma_free_coherent(&pdev->dev, ring->page_size,
1596                                   ring->pg_arr[i], ring->dma_arr[i]);
1597
1598                 ring->pg_arr[i] = NULL;
1599         }
1600         if (ring->pg_tbl) {
1601                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1602                                   ring->pg_tbl, ring->pg_tbl_map);
1603                 ring->pg_tbl = NULL;
1604         }
1605         if (ring->vmem_size && *ring->vmem) {
1606                 vfree(*ring->vmem);
1607                 *ring->vmem = NULL;
1608         }
1609 }
1610
1611 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1612 {
1613         int i;
1614         struct pci_dev *pdev = bp->pdev;
1615
1616         if (ring->nr_pages > 1) {
1617                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1618                                                   ring->nr_pages * 8,
1619                                                   &ring->pg_tbl_map,
1620                                                   GFP_KERNEL);
1621                 if (!ring->pg_tbl)
1622                         return -ENOMEM;
1623         }
1624
1625         for (i = 0; i < ring->nr_pages; i++) {
1626                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1627                                                      ring->page_size,
1628                                                      &ring->dma_arr[i],
1629                                                      GFP_KERNEL);
1630                 if (!ring->pg_arr[i])
1631                         return -ENOMEM;
1632
1633                 if (ring->nr_pages > 1)
1634                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1635         }
1636
1637         if (ring->vmem_size) {
1638                 *ring->vmem = vzalloc(ring->vmem_size);
1639                 if (!(*ring->vmem))
1640                         return -ENOMEM;
1641         }
1642         return 0;
1643 }
1644
1645 static void bnxt_free_rx_rings(struct bnxt *bp)
1646 {
1647         int i;
1648
1649         if (!bp->rx_ring)
1650                 return;
1651
1652         for (i = 0; i < bp->rx_nr_rings; i++) {
1653                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1654                 struct bnxt_ring_struct *ring;
1655
1656                 kfree(rxr->rx_tpa);
1657                 rxr->rx_tpa = NULL;
1658
1659                 kfree(rxr->rx_agg_bmap);
1660                 rxr->rx_agg_bmap = NULL;
1661
1662                 ring = &rxr->rx_ring_struct;
1663                 bnxt_free_ring(bp, ring);
1664
1665                 ring = &rxr->rx_agg_ring_struct;
1666                 bnxt_free_ring(bp, ring);
1667         }
1668 }
1669
1670 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1671 {
1672         int i, rc, agg_rings = 0, tpa_rings = 0;
1673
1674         if (!bp->rx_ring)
1675                 return -ENOMEM;
1676
1677         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1678                 agg_rings = 1;
1679
1680         if (bp->flags & BNXT_FLAG_TPA)
1681                 tpa_rings = 1;
1682
1683         for (i = 0; i < bp->rx_nr_rings; i++) {
1684                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1685                 struct bnxt_ring_struct *ring;
1686
1687                 ring = &rxr->rx_ring_struct;
1688
1689                 rc = bnxt_alloc_ring(bp, ring);
1690                 if (rc)
1691                         return rc;
1692
1693                 if (agg_rings) {
1694                         u16 mem_size;
1695
1696                         ring = &rxr->rx_agg_ring_struct;
1697                         rc = bnxt_alloc_ring(bp, ring);
1698                         if (rc)
1699                                 return rc;
1700
1701                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1702                         mem_size = rxr->rx_agg_bmap_size / 8;
1703                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1704                         if (!rxr->rx_agg_bmap)
1705                                 return -ENOMEM;
1706
1707                         if (tpa_rings) {
1708                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1709                                                 sizeof(struct bnxt_tpa_info),
1710                                                 GFP_KERNEL);
1711                                 if (!rxr->rx_tpa)
1712                                         return -ENOMEM;
1713                         }
1714                 }
1715         }
1716         return 0;
1717 }
1718
1719 static void bnxt_free_tx_rings(struct bnxt *bp)
1720 {
1721         int i;
1722         struct pci_dev *pdev = bp->pdev;
1723
1724         if (!bp->tx_ring)
1725                 return;
1726
1727         for (i = 0; i < bp->tx_nr_rings; i++) {
1728                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1729                 struct bnxt_ring_struct *ring;
1730
1731                 if (txr->tx_push) {
1732                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1733                                           txr->tx_push, txr->tx_push_mapping);
1734                         txr->tx_push = NULL;
1735                 }
1736
1737                 ring = &txr->tx_ring_struct;
1738
1739                 bnxt_free_ring(bp, ring);
1740         }
1741 }
1742
1743 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1744 {
1745         int i, j, rc;
1746         struct pci_dev *pdev = bp->pdev;
1747
1748         bp->tx_push_size = 0;
1749         if (bp->tx_push_thresh) {
1750                 int push_size;
1751
1752                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1753                                         bp->tx_push_thresh);
1754
1755                 if (push_size > 128) {
1756                         push_size = 0;
1757                         bp->tx_push_thresh = 0;
1758                 }
1759
1760                 bp->tx_push_size = push_size;
1761         }
1762
1763         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1764                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1765                 struct bnxt_ring_struct *ring;
1766
1767                 ring = &txr->tx_ring_struct;
1768
1769                 rc = bnxt_alloc_ring(bp, ring);
1770                 if (rc)
1771                         return rc;
1772
1773                 if (bp->tx_push_size) {
1774                         struct tx_bd *txbd;
1775                         dma_addr_t mapping;
1776
1777                         /* One pre-allocated DMA buffer to backup
1778                          * TX push operation
1779                          */
1780                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1781                                                 bp->tx_push_size,
1782                                                 &txr->tx_push_mapping,
1783                                                 GFP_KERNEL);
1784
1785                         if (!txr->tx_push)
1786                                 return -ENOMEM;
1787
1788                         txbd = &txr->tx_push->txbd1;
1789
1790                         mapping = txr->tx_push_mapping +
1791                                 sizeof(struct tx_push_bd);
1792                         txbd->tx_bd_haddr = cpu_to_le64(mapping);
1793
1794                         memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1795                 }
1796                 ring->queue_id = bp->q_info[j].queue_id;
1797                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1798                         j++;
1799         }
1800         return 0;
1801 }
1802
1803 static void bnxt_free_cp_rings(struct bnxt *bp)
1804 {
1805         int i;
1806
1807         if (!bp->bnapi)
1808                 return;
1809
1810         for (i = 0; i < bp->cp_nr_rings; i++) {
1811                 struct bnxt_napi *bnapi = bp->bnapi[i];
1812                 struct bnxt_cp_ring_info *cpr;
1813                 struct bnxt_ring_struct *ring;
1814
1815                 if (!bnapi)
1816                         continue;
1817
1818                 cpr = &bnapi->cp_ring;
1819                 ring = &cpr->cp_ring_struct;
1820
1821                 bnxt_free_ring(bp, ring);
1822         }
1823 }
1824
1825 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1826 {
1827         int i, rc;
1828
1829         for (i = 0; i < bp->cp_nr_rings; i++) {
1830                 struct bnxt_napi *bnapi = bp->bnapi[i];
1831                 struct bnxt_cp_ring_info *cpr;
1832                 struct bnxt_ring_struct *ring;
1833
1834                 if (!bnapi)
1835                         continue;
1836
1837                 cpr = &bnapi->cp_ring;
1838                 ring = &cpr->cp_ring_struct;
1839
1840                 rc = bnxt_alloc_ring(bp, ring);
1841                 if (rc)
1842                         return rc;
1843         }
1844         return 0;
1845 }
1846
1847 static void bnxt_init_ring_struct(struct bnxt *bp)
1848 {
1849         int i;
1850
1851         for (i = 0; i < bp->cp_nr_rings; i++) {
1852                 struct bnxt_napi *bnapi = bp->bnapi[i];
1853                 struct bnxt_cp_ring_info *cpr;
1854                 struct bnxt_rx_ring_info *rxr;
1855                 struct bnxt_tx_ring_info *txr;
1856                 struct bnxt_ring_struct *ring;
1857
1858                 if (!bnapi)
1859                         continue;
1860
1861                 cpr = &bnapi->cp_ring;
1862                 ring = &cpr->cp_ring_struct;
1863                 ring->nr_pages = bp->cp_nr_pages;
1864                 ring->page_size = HW_CMPD_RING_SIZE;
1865                 ring->pg_arr = (void **)cpr->cp_desc_ring;
1866                 ring->dma_arr = cpr->cp_desc_mapping;
1867                 ring->vmem_size = 0;
1868
1869                 rxr = bnapi->rx_ring;
1870                 if (!rxr)
1871                         goto skip_rx;
1872
1873                 ring = &rxr->rx_ring_struct;
1874                 ring->nr_pages = bp->rx_nr_pages;
1875                 ring->page_size = HW_RXBD_RING_SIZE;
1876                 ring->pg_arr = (void **)rxr->rx_desc_ring;
1877                 ring->dma_arr = rxr->rx_desc_mapping;
1878                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1879                 ring->vmem = (void **)&rxr->rx_buf_ring;
1880
1881                 ring = &rxr->rx_agg_ring_struct;
1882                 ring->nr_pages = bp->rx_agg_nr_pages;
1883                 ring->page_size = HW_RXBD_RING_SIZE;
1884                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1885                 ring->dma_arr = rxr->rx_agg_desc_mapping;
1886                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1887                 ring->vmem = (void **)&rxr->rx_agg_ring;
1888
1889 skip_rx:
1890                 txr = bnapi->tx_ring;
1891                 if (!txr)
1892                         continue;
1893
1894                 ring = &txr->tx_ring_struct;
1895                 ring->nr_pages = bp->tx_nr_pages;
1896                 ring->page_size = HW_RXBD_RING_SIZE;
1897                 ring->pg_arr = (void **)txr->tx_desc_ring;
1898                 ring->dma_arr = txr->tx_desc_mapping;
1899                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1900                 ring->vmem = (void **)&txr->tx_buf_ring;
1901         }
1902 }
1903
1904 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1905 {
1906         int i;
1907         u32 prod;
1908         struct rx_bd **rx_buf_ring;
1909
1910         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1911         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1912                 int j;
1913                 struct rx_bd *rxbd;
1914
1915                 rxbd = rx_buf_ring[i];
1916                 if (!rxbd)
1917                         continue;
1918
1919                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1920                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1921                         rxbd->rx_bd_opaque = prod;
1922                 }
1923         }
1924 }
1925
1926 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1927 {
1928         struct net_device *dev = bp->dev;
1929         struct bnxt_rx_ring_info *rxr;
1930         struct bnxt_ring_struct *ring;
1931         u32 prod, type;
1932         int i;
1933
1934         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1935                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1936
1937         if (NET_IP_ALIGN == 2)
1938                 type |= RX_BD_FLAGS_SOP;
1939
1940         rxr = &bp->rx_ring[ring_nr];
1941         ring = &rxr->rx_ring_struct;
1942         bnxt_init_rxbd_pages(ring, type);
1943
1944         prod = rxr->rx_prod;
1945         for (i = 0; i < bp->rx_ring_size; i++) {
1946                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1947                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1948                                     ring_nr, i, bp->rx_ring_size);
1949                         break;
1950                 }
1951                 prod = NEXT_RX(prod);
1952         }
1953         rxr->rx_prod = prod;
1954         ring->fw_ring_id = INVALID_HW_RING_ID;
1955
1956         ring = &rxr->rx_agg_ring_struct;
1957         ring->fw_ring_id = INVALID_HW_RING_ID;
1958
1959         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1960                 return 0;
1961
1962         type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1963                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1964
1965         bnxt_init_rxbd_pages(ring, type);
1966
1967         prod = rxr->rx_agg_prod;
1968         for (i = 0; i < bp->rx_agg_ring_size; i++) {
1969                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1970                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1971                                     ring_nr, i, bp->rx_ring_size);
1972                         break;
1973                 }
1974                 prod = NEXT_RX_AGG(prod);
1975         }
1976         rxr->rx_agg_prod = prod;
1977
1978         if (bp->flags & BNXT_FLAG_TPA) {
1979                 if (rxr->rx_tpa) {
1980                         u8 *data;
1981                         dma_addr_t mapping;
1982
1983                         for (i = 0; i < MAX_TPA; i++) {
1984                                 data = __bnxt_alloc_rx_data(bp, &mapping,
1985                                                             GFP_KERNEL);
1986                                 if (!data)
1987                                         return -ENOMEM;
1988
1989                                 rxr->rx_tpa[i].data = data;
1990                                 rxr->rx_tpa[i].mapping = mapping;
1991                         }
1992                 } else {
1993                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
1994                         return -ENOMEM;
1995                 }
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int bnxt_init_rx_rings(struct bnxt *bp)
2002 {
2003         int i, rc = 0;
2004
2005         for (i = 0; i < bp->rx_nr_rings; i++) {
2006                 rc = bnxt_init_one_rx_ring(bp, i);
2007                 if (rc)
2008                         break;
2009         }
2010
2011         return rc;
2012 }
2013
2014 static int bnxt_init_tx_rings(struct bnxt *bp)
2015 {
2016         u16 i;
2017
2018         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2019                                    MAX_SKB_FRAGS + 1);
2020
2021         for (i = 0; i < bp->tx_nr_rings; i++) {
2022                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2023                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2024
2025                 ring->fw_ring_id = INVALID_HW_RING_ID;
2026         }
2027
2028         return 0;
2029 }
2030
2031 static void bnxt_free_ring_grps(struct bnxt *bp)
2032 {
2033         kfree(bp->grp_info);
2034         bp->grp_info = NULL;
2035 }
2036
2037 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2038 {
2039         int i;
2040
2041         if (irq_re_init) {
2042                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2043                                        sizeof(struct bnxt_ring_grp_info),
2044                                        GFP_KERNEL);
2045                 if (!bp->grp_info)
2046                         return -ENOMEM;
2047         }
2048         for (i = 0; i < bp->cp_nr_rings; i++) {
2049                 if (irq_re_init)
2050                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2051                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2052                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2053                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2054                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2055         }
2056         return 0;
2057 }
2058
2059 static void bnxt_free_vnics(struct bnxt *bp)
2060 {
2061         kfree(bp->vnic_info);
2062         bp->vnic_info = NULL;
2063         bp->nr_vnics = 0;
2064 }
2065
2066 static int bnxt_alloc_vnics(struct bnxt *bp)
2067 {
2068         int num_vnics = 1;
2069
2070 #ifdef CONFIG_RFS_ACCEL
2071         if (bp->flags & BNXT_FLAG_RFS)
2072                 num_vnics += bp->rx_nr_rings;
2073 #endif
2074
2075         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2076                                 GFP_KERNEL);
2077         if (!bp->vnic_info)
2078                 return -ENOMEM;
2079
2080         bp->nr_vnics = num_vnics;
2081         return 0;
2082 }
2083
2084 static void bnxt_init_vnics(struct bnxt *bp)
2085 {
2086         int i;
2087
2088         for (i = 0; i < bp->nr_vnics; i++) {
2089                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2090
2091                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2092                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2093                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2094
2095                 if (bp->vnic_info[i].rss_hash_key) {
2096                         if (i == 0)
2097                                 prandom_bytes(vnic->rss_hash_key,
2098                                               HW_HASH_KEY_SIZE);
2099                         else
2100                                 memcpy(vnic->rss_hash_key,
2101                                        bp->vnic_info[0].rss_hash_key,
2102                                        HW_HASH_KEY_SIZE);
2103                 }
2104         }
2105 }
2106
2107 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2108 {
2109         int pages;
2110
2111         pages = ring_size / desc_per_pg;
2112
2113         if (!pages)
2114                 return 1;
2115
2116         pages++;
2117
2118         while (pages & (pages - 1))
2119                 pages++;
2120
2121         return pages;
2122 }
2123
2124 static void bnxt_set_tpa_flags(struct bnxt *bp)
2125 {
2126         bp->flags &= ~BNXT_FLAG_TPA;
2127         if (bp->dev->features & NETIF_F_LRO)
2128                 bp->flags |= BNXT_FLAG_LRO;
2129         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2130                 bp->flags |= BNXT_FLAG_GRO;
2131 }
2132
2133 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2134  * be set on entry.
2135  */
2136 void bnxt_set_ring_params(struct bnxt *bp)
2137 {
2138         u32 ring_size, rx_size, rx_space;
2139         u32 agg_factor = 0, agg_ring_size = 0;
2140
2141         /* 8 for CRC and VLAN */
2142         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2143
2144         rx_space = rx_size + NET_SKB_PAD +
2145                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2146
2147         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2148         ring_size = bp->rx_ring_size;
2149         bp->rx_agg_ring_size = 0;
2150         bp->rx_agg_nr_pages = 0;
2151
2152         if (bp->flags & BNXT_FLAG_TPA)
2153                 agg_factor = 4;
2154
2155         bp->flags &= ~BNXT_FLAG_JUMBO;
2156         if (rx_space > PAGE_SIZE) {
2157                 u32 jumbo_factor;
2158
2159                 bp->flags |= BNXT_FLAG_JUMBO;
2160                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2161                 if (jumbo_factor > agg_factor)
2162                         agg_factor = jumbo_factor;
2163         }
2164         agg_ring_size = ring_size * agg_factor;
2165
2166         if (agg_ring_size) {
2167                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2168                                                         RX_DESC_CNT);
2169                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2170                         u32 tmp = agg_ring_size;
2171
2172                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2173                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2174                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2175                                     tmp, agg_ring_size);
2176                 }
2177                 bp->rx_agg_ring_size = agg_ring_size;
2178                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2179                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2180                 rx_space = rx_size + NET_SKB_PAD +
2181                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2182         }
2183
2184         bp->rx_buf_use_size = rx_size;
2185         bp->rx_buf_size = rx_space;
2186
2187         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2188         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2189
2190         ring_size = bp->tx_ring_size;
2191         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2192         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2193
2194         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2195         bp->cp_ring_size = ring_size;
2196
2197         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2198         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2199                 bp->cp_nr_pages = MAX_CP_PAGES;
2200                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2201                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2202                             ring_size, bp->cp_ring_size);
2203         }
2204         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2205         bp->cp_ring_mask = bp->cp_bit - 1;
2206 }
2207
2208 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2209 {
2210         int i;
2211         struct bnxt_vnic_info *vnic;
2212         struct pci_dev *pdev = bp->pdev;
2213
2214         if (!bp->vnic_info)
2215                 return;
2216
2217         for (i = 0; i < bp->nr_vnics; i++) {
2218                 vnic = &bp->vnic_info[i];
2219
2220                 kfree(vnic->fw_grp_ids);
2221                 vnic->fw_grp_ids = NULL;
2222
2223                 kfree(vnic->uc_list);
2224                 vnic->uc_list = NULL;
2225
2226                 if (vnic->mc_list) {
2227                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2228                                           vnic->mc_list, vnic->mc_list_mapping);
2229                         vnic->mc_list = NULL;
2230                 }
2231
2232                 if (vnic->rss_table) {
2233                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2234                                           vnic->rss_table,
2235                                           vnic->rss_table_dma_addr);
2236                         vnic->rss_table = NULL;
2237                 }
2238
2239                 vnic->rss_hash_key = NULL;
2240                 vnic->flags = 0;
2241         }
2242 }
2243
2244 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2245 {
2246         int i, rc = 0, size;
2247         struct bnxt_vnic_info *vnic;
2248         struct pci_dev *pdev = bp->pdev;
2249         int max_rings;
2250
2251         for (i = 0; i < bp->nr_vnics; i++) {
2252                 vnic = &bp->vnic_info[i];
2253
2254                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2255                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2256
2257                         if (mem_size > 0) {
2258                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2259                                 if (!vnic->uc_list) {
2260                                         rc = -ENOMEM;
2261                                         goto out;
2262                                 }
2263                         }
2264                 }
2265
2266                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2267                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2268                         vnic->mc_list =
2269                                 dma_alloc_coherent(&pdev->dev,
2270                                                    vnic->mc_list_size,
2271                                                    &vnic->mc_list_mapping,
2272                                                    GFP_KERNEL);
2273                         if (!vnic->mc_list) {
2274                                 rc = -ENOMEM;
2275                                 goto out;
2276                         }
2277                 }
2278
2279                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2280                         max_rings = bp->rx_nr_rings;
2281                 else
2282                         max_rings = 1;
2283
2284                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2285                 if (!vnic->fw_grp_ids) {
2286                         rc = -ENOMEM;
2287                         goto out;
2288                 }
2289
2290                 /* Allocate rss table and hash key */
2291                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2292                                                      &vnic->rss_table_dma_addr,
2293                                                      GFP_KERNEL);
2294                 if (!vnic->rss_table) {
2295                         rc = -ENOMEM;
2296                         goto out;
2297                 }
2298
2299                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2300
2301                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2302                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2303         }
2304         return 0;
2305
2306 out:
2307         return rc;
2308 }
2309
2310 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2311 {
2312         struct pci_dev *pdev = bp->pdev;
2313
2314         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2315                           bp->hwrm_cmd_resp_dma_addr);
2316
2317         bp->hwrm_cmd_resp_addr = NULL;
2318         if (bp->hwrm_dbg_resp_addr) {
2319                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2320                                   bp->hwrm_dbg_resp_addr,
2321                                   bp->hwrm_dbg_resp_dma_addr);
2322
2323                 bp->hwrm_dbg_resp_addr = NULL;
2324         }
2325 }
2326
2327 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2328 {
2329         struct pci_dev *pdev = bp->pdev;
2330
2331         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2332                                                    &bp->hwrm_cmd_resp_dma_addr,
2333                                                    GFP_KERNEL);
2334         if (!bp->hwrm_cmd_resp_addr)
2335                 return -ENOMEM;
2336         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2337                                                     HWRM_DBG_REG_BUF_SIZE,
2338                                                     &bp->hwrm_dbg_resp_dma_addr,
2339                                                     GFP_KERNEL);
2340         if (!bp->hwrm_dbg_resp_addr)
2341                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2342
2343         return 0;
2344 }
2345
2346 static void bnxt_free_stats(struct bnxt *bp)
2347 {
2348         u32 size, i;
2349         struct pci_dev *pdev = bp->pdev;
2350
2351         if (!bp->bnapi)
2352                 return;
2353
2354         size = sizeof(struct ctx_hw_stats);
2355
2356         for (i = 0; i < bp->cp_nr_rings; i++) {
2357                 struct bnxt_napi *bnapi = bp->bnapi[i];
2358                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2359
2360                 if (cpr->hw_stats) {
2361                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2362                                           cpr->hw_stats_map);
2363                         cpr->hw_stats = NULL;
2364                 }
2365         }
2366 }
2367
2368 static int bnxt_alloc_stats(struct bnxt *bp)
2369 {
2370         u32 size, i;
2371         struct pci_dev *pdev = bp->pdev;
2372
2373         size = sizeof(struct ctx_hw_stats);
2374
2375         for (i = 0; i < bp->cp_nr_rings; i++) {
2376                 struct bnxt_napi *bnapi = bp->bnapi[i];
2377                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2378
2379                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2380                                                    &cpr->hw_stats_map,
2381                                                    GFP_KERNEL);
2382                 if (!cpr->hw_stats)
2383                         return -ENOMEM;
2384
2385                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2386         }
2387         return 0;
2388 }
2389
2390 static void bnxt_clear_ring_indices(struct bnxt *bp)
2391 {
2392         int i;
2393
2394         if (!bp->bnapi)
2395                 return;
2396
2397         for (i = 0; i < bp->cp_nr_rings; i++) {
2398                 struct bnxt_napi *bnapi = bp->bnapi[i];
2399                 struct bnxt_cp_ring_info *cpr;
2400                 struct bnxt_rx_ring_info *rxr;
2401                 struct bnxt_tx_ring_info *txr;
2402
2403                 if (!bnapi)
2404                         continue;
2405
2406                 cpr = &bnapi->cp_ring;
2407                 cpr->cp_raw_cons = 0;
2408
2409                 txr = bnapi->tx_ring;
2410                 if (txr) {
2411                         txr->tx_prod = 0;
2412                         txr->tx_cons = 0;
2413                 }
2414
2415                 rxr = bnapi->rx_ring;
2416                 if (rxr) {
2417                         rxr->rx_prod = 0;
2418                         rxr->rx_agg_prod = 0;
2419                         rxr->rx_sw_agg_prod = 0;
2420                 }
2421         }
2422 }
2423
2424 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2425 {
2426 #ifdef CONFIG_RFS_ACCEL
2427         int i;
2428
2429         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2430          * safe to delete the hash table.
2431          */
2432         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2433                 struct hlist_head *head;
2434                 struct hlist_node *tmp;
2435                 struct bnxt_ntuple_filter *fltr;
2436
2437                 head = &bp->ntp_fltr_hash_tbl[i];
2438                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2439                         hlist_del(&fltr->hash);
2440                         kfree(fltr);
2441                 }
2442         }
2443         if (irq_reinit) {
2444                 kfree(bp->ntp_fltr_bmap);
2445                 bp->ntp_fltr_bmap = NULL;
2446         }
2447         bp->ntp_fltr_count = 0;
2448 #endif
2449 }
2450
2451 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2452 {
2453 #ifdef CONFIG_RFS_ACCEL
2454         int i, rc = 0;
2455
2456         if (!(bp->flags & BNXT_FLAG_RFS))
2457                 return 0;
2458
2459         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2460                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2461
2462         bp->ntp_fltr_count = 0;
2463         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2464                                     GFP_KERNEL);
2465
2466         if (!bp->ntp_fltr_bmap)
2467                 rc = -ENOMEM;
2468
2469         return rc;
2470 #else
2471         return 0;
2472 #endif
2473 }
2474
2475 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2476 {
2477         bnxt_free_vnic_attributes(bp);
2478         bnxt_free_tx_rings(bp);
2479         bnxt_free_rx_rings(bp);
2480         bnxt_free_cp_rings(bp);
2481         bnxt_free_ntp_fltrs(bp, irq_re_init);
2482         if (irq_re_init) {
2483                 bnxt_free_stats(bp);
2484                 bnxt_free_ring_grps(bp);
2485                 bnxt_free_vnics(bp);
2486                 kfree(bp->tx_ring);
2487                 bp->tx_ring = NULL;
2488                 kfree(bp->rx_ring);
2489                 bp->rx_ring = NULL;
2490                 kfree(bp->bnapi);
2491                 bp->bnapi = NULL;
2492         } else {
2493                 bnxt_clear_ring_indices(bp);
2494         }
2495 }
2496
2497 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2498 {
2499         int i, j, rc, size, arr_size;
2500         void *bnapi;
2501
2502         if (irq_re_init) {
2503                 /* Allocate bnapi mem pointer array and mem block for
2504                  * all queues
2505                  */
2506                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2507                                 bp->cp_nr_rings);
2508                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2509                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2510                 if (!bnapi)
2511                         return -ENOMEM;
2512
2513                 bp->bnapi = bnapi;
2514                 bnapi += arr_size;
2515                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2516                         bp->bnapi[i] = bnapi;
2517                         bp->bnapi[i]->index = i;
2518                         bp->bnapi[i]->bp = bp;
2519                 }
2520
2521                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2522                                       sizeof(struct bnxt_rx_ring_info),
2523                                       GFP_KERNEL);
2524                 if (!bp->rx_ring)
2525                         return -ENOMEM;
2526
2527                 for (i = 0; i < bp->rx_nr_rings; i++) {
2528                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2529                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2530                 }
2531
2532                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2533                                       sizeof(struct bnxt_tx_ring_info),
2534                                       GFP_KERNEL);
2535                 if (!bp->tx_ring)
2536                         return -ENOMEM;
2537
2538                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2539                         j = 0;
2540                 else
2541                         j = bp->rx_nr_rings;
2542
2543                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2544                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2545                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2546                 }
2547
2548                 rc = bnxt_alloc_stats(bp);
2549                 if (rc)
2550                         goto alloc_mem_err;
2551
2552                 rc = bnxt_alloc_ntp_fltrs(bp);
2553                 if (rc)
2554                         goto alloc_mem_err;
2555
2556                 rc = bnxt_alloc_vnics(bp);
2557                 if (rc)
2558                         goto alloc_mem_err;
2559         }
2560
2561         bnxt_init_ring_struct(bp);
2562
2563         rc = bnxt_alloc_rx_rings(bp);
2564         if (rc)
2565                 goto alloc_mem_err;
2566
2567         rc = bnxt_alloc_tx_rings(bp);
2568         if (rc)
2569                 goto alloc_mem_err;
2570
2571         rc = bnxt_alloc_cp_rings(bp);
2572         if (rc)
2573                 goto alloc_mem_err;
2574
2575         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2576                                   BNXT_VNIC_UCAST_FLAG;
2577         rc = bnxt_alloc_vnic_attributes(bp);
2578         if (rc)
2579                 goto alloc_mem_err;
2580         return 0;
2581
2582 alloc_mem_err:
2583         bnxt_free_mem(bp, true);
2584         return rc;
2585 }
2586
2587 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2588                             u16 cmpl_ring, u16 target_id)
2589 {
2590         struct hwrm_cmd_req_hdr *req = request;
2591
2592         req->cmpl_ring_req_type =
2593                 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2594         req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2595         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2596 }
2597
2598 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2599 {
2600         int i, intr_process, rc;
2601         struct hwrm_cmd_req_hdr *req = msg;
2602         u32 *data = msg;
2603         __le32 *resp_len, *valid;
2604         u16 cp_ring_id, len = 0;
2605         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2606
2607         req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2608         memset(resp, 0, PAGE_SIZE);
2609         cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2610                       HWRM_CMPL_RING_MASK) >>
2611                      HWRM_CMPL_RING_SFT;
2612         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2613
2614         /* Write request msg to hwrm channel */
2615         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2616
2617         for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
2618                 writel(0, bp->bar0 + i);
2619
2620         /* currently supports only one outstanding message */
2621         if (intr_process)
2622                 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2623                                        HWRM_SEQ_ID_MASK;
2624
2625         /* Ring channel doorbell */
2626         writel(1, bp->bar0 + 0x100);
2627
2628         i = 0;
2629         if (intr_process) {
2630                 /* Wait until hwrm response cmpl interrupt is processed */
2631                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2632                        i++ < timeout) {
2633                         usleep_range(600, 800);
2634                 }
2635
2636                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2637                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2638                                    req->cmpl_ring_req_type);
2639                         return -1;
2640                 }
2641         } else {
2642                 /* Check if response len is updated */
2643                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2644                 for (i = 0; i < timeout; i++) {
2645                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2646                               HWRM_RESP_LEN_SFT;
2647                         if (len)
2648                                 break;
2649                         usleep_range(600, 800);
2650                 }
2651
2652                 if (i >= timeout) {
2653                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2654                                    timeout, req->cmpl_ring_req_type,
2655                                    req->target_id_seq_id, *resp_len);
2656                         return -1;
2657                 }
2658
2659                 /* Last word of resp contains valid bit */
2660                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2661                 for (i = 0; i < timeout; i++) {
2662                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2663                                 break;
2664                         usleep_range(600, 800);
2665                 }
2666
2667                 if (i >= timeout) {
2668                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2669                                    timeout, req->cmpl_ring_req_type,
2670                                    req->target_id_seq_id, len, *valid);
2671                         return -1;
2672                 }
2673         }
2674
2675         rc = le16_to_cpu(resp->error_code);
2676         if (rc) {
2677                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2678                            le16_to_cpu(resp->req_type),
2679                            le16_to_cpu(resp->seq_id), rc);
2680                 return rc;
2681         }
2682         return 0;
2683 }
2684
2685 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2686 {
2687         int rc;
2688
2689         mutex_lock(&bp->hwrm_cmd_lock);
2690         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2691         mutex_unlock(&bp->hwrm_cmd_lock);
2692         return rc;
2693 }
2694
2695 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2696 {
2697         struct hwrm_func_drv_rgtr_input req = {0};
2698         int i;
2699
2700         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2701
2702         req.enables =
2703                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2704                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2705                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2706
2707         /* TODO: current async event fwd bits are not defined and the firmware
2708          * only checks if it is non-zero to enable async event forwarding
2709          */
2710         req.async_event_fwd[0] |= cpu_to_le32(1);
2711         req.os_type = cpu_to_le16(1);
2712         req.ver_maj = DRV_VER_MAJ;
2713         req.ver_min = DRV_VER_MIN;
2714         req.ver_upd = DRV_VER_UPD;
2715
2716         if (BNXT_PF(bp)) {
2717                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2718                 u32 *data = (u32 *)vf_req_snif_bmap;
2719
2720                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2721                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2722                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2723
2724                 for (i = 0; i < 8; i++)
2725                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2726
2727                 req.enables |=
2728                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2729         }
2730
2731         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2732 }
2733
2734 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2735 {
2736         struct hwrm_func_drv_unrgtr_input req = {0};
2737
2738         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2739         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2740 }
2741
2742 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2743 {
2744         u32 rc = 0;
2745         struct hwrm_tunnel_dst_port_free_input req = {0};
2746
2747         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2748         req.tunnel_type = tunnel_type;
2749
2750         switch (tunnel_type) {
2751         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2752                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2753                 break;
2754         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2755                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2756                 break;
2757         default:
2758                 break;
2759         }
2760
2761         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2762         if (rc)
2763                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2764                            rc);
2765         return rc;
2766 }
2767
2768 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2769                                            u8 tunnel_type)
2770 {
2771         u32 rc = 0;
2772         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2773         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2774
2775         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2776
2777         req.tunnel_type = tunnel_type;
2778         req.tunnel_dst_port_val = port;
2779
2780         mutex_lock(&bp->hwrm_cmd_lock);
2781         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2782         if (rc) {
2783                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2784                            rc);
2785                 goto err_out;
2786         }
2787
2788         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2789                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2790
2791         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2792                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2793 err_out:
2794         mutex_unlock(&bp->hwrm_cmd_lock);
2795         return rc;
2796 }
2797
2798 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2799 {
2800         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2801         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2802
2803         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2804         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2805
2806         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2807         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2808         req.mask = cpu_to_le32(vnic->rx_mask);
2809         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2810 }
2811
2812 #ifdef CONFIG_RFS_ACCEL
2813 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2814                                             struct bnxt_ntuple_filter *fltr)
2815 {
2816         struct hwrm_cfa_ntuple_filter_free_input req = {0};
2817
2818         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2819         req.ntuple_filter_id = fltr->filter_id;
2820         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2821 }
2822
2823 #define BNXT_NTP_FLTR_FLAGS                                     \
2824         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
2825          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
2826          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
2827          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
2828          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
2829          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
2830          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
2831          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
2832          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
2833          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
2834          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
2835          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
2836          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
2837          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2838
2839 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2840                                              struct bnxt_ntuple_filter *fltr)
2841 {
2842         int rc = 0;
2843         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2844         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2845                 bp->hwrm_cmd_resp_addr;
2846         struct flow_keys *keys = &fltr->fkeys;
2847         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2848
2849         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2850         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2851
2852         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2853
2854         req.ethertype = htons(ETH_P_IP);
2855         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2856         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2857         req.ip_protocol = keys->basic.ip_proto;
2858
2859         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2860         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2861         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2862         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2863
2864         req.src_port = keys->ports.src;
2865         req.src_port_mask = cpu_to_be16(0xffff);
2866         req.dst_port = keys->ports.dst;
2867         req.dst_port_mask = cpu_to_be16(0xffff);
2868
2869         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2870         mutex_lock(&bp->hwrm_cmd_lock);
2871         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2872         if (!rc)
2873                 fltr->filter_id = resp->ntuple_filter_id;
2874         mutex_unlock(&bp->hwrm_cmd_lock);
2875         return rc;
2876 }
2877 #endif
2878
2879 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2880                                      u8 *mac_addr)
2881 {
2882         u32 rc = 0;
2883         struct hwrm_cfa_l2_filter_alloc_input req = {0};
2884         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2885
2886         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2887         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2888                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2889         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2890         req.enables =
2891                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2892                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
2893                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2894         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2895         req.l2_addr_mask[0] = 0xff;
2896         req.l2_addr_mask[1] = 0xff;
2897         req.l2_addr_mask[2] = 0xff;
2898         req.l2_addr_mask[3] = 0xff;
2899         req.l2_addr_mask[4] = 0xff;
2900         req.l2_addr_mask[5] = 0xff;
2901
2902         mutex_lock(&bp->hwrm_cmd_lock);
2903         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2904         if (!rc)
2905                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2906                                                         resp->l2_filter_id;
2907         mutex_unlock(&bp->hwrm_cmd_lock);
2908         return rc;
2909 }
2910
2911 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2912 {
2913         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2914         int rc = 0;
2915
2916         /* Any associated ntuple filters will also be cleared by firmware. */
2917         mutex_lock(&bp->hwrm_cmd_lock);
2918         for (i = 0; i < num_of_vnics; i++) {
2919                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2920
2921                 for (j = 0; j < vnic->uc_filter_count; j++) {
2922                         struct hwrm_cfa_l2_filter_free_input req = {0};
2923
2924                         bnxt_hwrm_cmd_hdr_init(bp, &req,
2925                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
2926
2927                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
2928
2929                         rc = _hwrm_send_message(bp, &req, sizeof(req),
2930                                                 HWRM_CMD_TIMEOUT);
2931                 }
2932                 vnic->uc_filter_count = 0;
2933         }
2934         mutex_unlock(&bp->hwrm_cmd_lock);
2935
2936         return rc;
2937 }
2938
2939 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2940 {
2941         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2942         struct hwrm_vnic_tpa_cfg_input req = {0};
2943
2944         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2945
2946         if (tpa_flags) {
2947                 u16 mss = bp->dev->mtu - 40;
2948                 u32 nsegs, n, segs = 0, flags;
2949
2950                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2951                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2952                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2953                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2954                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2955                 if (tpa_flags & BNXT_FLAG_GRO)
2956                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2957
2958                 req.flags = cpu_to_le32(flags);
2959
2960                 req.enables =
2961                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2962                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2963                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
2964
2965                 /* Number of segs are log2 units, and first packet is not
2966                  * included as part of this units.
2967                  */
2968                 if (mss <= PAGE_SIZE) {
2969                         n = PAGE_SIZE / mss;
2970                         nsegs = (MAX_SKB_FRAGS - 1) * n;
2971                 } else {
2972                         n = mss / PAGE_SIZE;
2973                         if (mss & (PAGE_SIZE - 1))
2974                                 n++;
2975                         nsegs = (MAX_SKB_FRAGS - n) / n;
2976                 }
2977
2978                 segs = ilog2(nsegs);
2979                 req.max_agg_segs = cpu_to_le16(segs);
2980                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2981
2982                 req.min_agg_len = cpu_to_le32(512);
2983         }
2984         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2985
2986         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2987 }
2988
2989 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2990 {
2991         u32 i, j, max_rings;
2992         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2993         struct hwrm_vnic_rss_cfg_input req = {0};
2994
2995         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2996                 return 0;
2997
2998         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2999         if (set_rss) {
3000                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3001                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3002                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3003                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3004
3005                 req.hash_type = cpu_to_le32(vnic->hash_type);
3006
3007                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3008                         max_rings = bp->rx_nr_rings;
3009                 else
3010                         max_rings = 1;
3011
3012                 /* Fill the RSS indirection table with ring group ids */
3013                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3014                         if (j == max_rings)
3015                                 j = 0;
3016                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3017                 }
3018
3019                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3020                 req.hash_key_tbl_addr =
3021                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3022         }
3023         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3024         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3025 }
3026
3027 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3028 {
3029         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3030         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3031
3032         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3033         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3034                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3035                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3036         req.enables =
3037                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3038                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3039         /* thresholds not implemented in firmware yet */
3040         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3041         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3042         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3043         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3044 }
3045
3046 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3047 {
3048         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3049
3050         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3051         req.rss_cos_lb_ctx_id =
3052                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3053
3054         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3055         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3056 }
3057
3058 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3059 {
3060         int i;
3061
3062         for (i = 0; i < bp->nr_vnics; i++) {
3063                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3064
3065                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3066                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3067         }
3068         bp->rsscos_nr_ctxs = 0;
3069 }
3070
3071 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3072 {
3073         int rc;
3074         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3075         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3076                                                 bp->hwrm_cmd_resp_addr;
3077
3078         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3079                                -1);
3080
3081         mutex_lock(&bp->hwrm_cmd_lock);
3082         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3083         if (!rc)
3084                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3085                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3086         mutex_unlock(&bp->hwrm_cmd_lock);
3087
3088         return rc;
3089 }
3090
3091 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3092 {
3093         unsigned int ring = 0, grp_idx;
3094         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3095         struct hwrm_vnic_cfg_input req = {0};
3096
3097         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3098         /* Only RSS support for now TBD: COS & LB */
3099         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3100                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3101         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3102         req.cos_rule = cpu_to_le16(0xffff);
3103         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3104                 ring = 0;
3105         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3106                 ring = vnic_id - 1;
3107
3108         grp_idx = bp->rx_ring[ring].bnapi->index;
3109         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3110         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3111
3112         req.lb_rule = cpu_to_le16(0xffff);
3113         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3114                               VLAN_HLEN);
3115
3116         if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3117                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3118
3119         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3120 }
3121
3122 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3123 {
3124         u32 rc = 0;
3125
3126         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3127                 struct hwrm_vnic_free_input req = {0};
3128
3129                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3130                 req.vnic_id =
3131                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3132
3133                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3134                 if (rc)
3135                         return rc;
3136                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3137         }
3138         return rc;
3139 }
3140
3141 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3142 {
3143         u16 i;
3144
3145         for (i = 0; i < bp->nr_vnics; i++)
3146                 bnxt_hwrm_vnic_free_one(bp, i);
3147 }
3148
3149 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3150                                 unsigned int start_rx_ring_idx,
3151                                 unsigned int nr_rings)
3152 {
3153         int rc = 0;
3154         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3155         struct hwrm_vnic_alloc_input req = {0};
3156         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3157
3158         /* map ring groups to this vnic */
3159         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3160                 grp_idx = bp->rx_ring[i].bnapi->index;
3161                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3162                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3163                                    j, nr_rings);
3164                         break;
3165                 }
3166                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3167                                         bp->grp_info[grp_idx].fw_grp_id;
3168         }
3169
3170         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3171         if (vnic_id == 0)
3172                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3173
3174         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3175
3176         mutex_lock(&bp->hwrm_cmd_lock);
3177         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3178         if (!rc)
3179                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3180         mutex_unlock(&bp->hwrm_cmd_lock);
3181         return rc;
3182 }
3183
3184 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3185 {
3186         u16 i;
3187         u32 rc = 0;
3188
3189         mutex_lock(&bp->hwrm_cmd_lock);
3190         for (i = 0; i < bp->rx_nr_rings; i++) {
3191                 struct hwrm_ring_grp_alloc_input req = {0};
3192                 struct hwrm_ring_grp_alloc_output *resp =
3193                                         bp->hwrm_cmd_resp_addr;
3194                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3195
3196                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3197
3198                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3199                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3200                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3201                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3202
3203                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3204                                         HWRM_CMD_TIMEOUT);
3205                 if (rc)
3206                         break;
3207
3208                 bp->grp_info[grp_idx].fw_grp_id =
3209                         le32_to_cpu(resp->ring_group_id);
3210         }
3211         mutex_unlock(&bp->hwrm_cmd_lock);
3212         return rc;
3213 }
3214
3215 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3216 {
3217         u16 i;
3218         u32 rc = 0;
3219         struct hwrm_ring_grp_free_input req = {0};
3220
3221         if (!bp->grp_info)
3222                 return 0;
3223
3224         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3225
3226         mutex_lock(&bp->hwrm_cmd_lock);
3227         for (i = 0; i < bp->cp_nr_rings; i++) {
3228                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3229                         continue;
3230                 req.ring_group_id =
3231                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3232
3233                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3234                                         HWRM_CMD_TIMEOUT);
3235                 if (rc)
3236                         break;
3237                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3238         }
3239         mutex_unlock(&bp->hwrm_cmd_lock);
3240         return rc;
3241 }
3242
3243 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3244                                     struct bnxt_ring_struct *ring,
3245                                     u32 ring_type, u32 map_index,
3246                                     u32 stats_ctx_id)
3247 {
3248         int rc = 0, err = 0;
3249         struct hwrm_ring_alloc_input req = {0};
3250         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3251         u16 ring_id;
3252
3253         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3254
3255         req.enables = 0;
3256         if (ring->nr_pages > 1) {
3257                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3258                 /* Page size is in log2 units */
3259                 req.page_size = BNXT_PAGE_SHIFT;
3260                 req.page_tbl_depth = 1;
3261         } else {
3262                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3263         }
3264         req.fbo = 0;
3265         /* Association of ring index with doorbell index and MSIX number */
3266         req.logical_id = cpu_to_le16(map_index);
3267
3268         switch (ring_type) {
3269         case HWRM_RING_ALLOC_TX:
3270                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3271                 /* Association of transmit ring with completion ring */
3272                 req.cmpl_ring_id =
3273                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3274                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3275                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3276                 req.queue_id = cpu_to_le16(ring->queue_id);
3277                 break;
3278         case HWRM_RING_ALLOC_RX:
3279                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3280                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3281                 break;
3282         case HWRM_RING_ALLOC_AGG:
3283                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3284                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3285                 break;
3286         case HWRM_RING_ALLOC_CMPL:
3287                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3288                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3289                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3290                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3291                 break;
3292         default:
3293                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3294                            ring_type);
3295                 return -1;
3296         }
3297
3298         mutex_lock(&bp->hwrm_cmd_lock);
3299         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3300         err = le16_to_cpu(resp->error_code);
3301         ring_id = le16_to_cpu(resp->ring_id);
3302         mutex_unlock(&bp->hwrm_cmd_lock);
3303
3304         if (rc || err) {
3305                 switch (ring_type) {
3306                 case RING_FREE_REQ_RING_TYPE_CMPL:
3307                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3308                                    rc, err);
3309                         return -1;
3310
3311                 case RING_FREE_REQ_RING_TYPE_RX:
3312                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3313                                    rc, err);
3314                         return -1;
3315
3316                 case RING_FREE_REQ_RING_TYPE_TX:
3317                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3318                                    rc, err);
3319                         return -1;
3320
3321                 default:
3322                         netdev_err(bp->dev, "Invalid ring\n");
3323                         return -1;
3324                 }
3325         }
3326         ring->fw_ring_id = ring_id;
3327         return rc;
3328 }
3329
3330 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3331 {
3332         int i, rc = 0;
3333
3334         for (i = 0; i < bp->cp_nr_rings; i++) {
3335                 struct bnxt_napi *bnapi = bp->bnapi[i];
3336                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3337                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3338
3339                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3340                                               INVALID_STATS_CTX_ID);
3341                 if (rc)
3342                         goto err_out;
3343                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3344                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3345                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3346         }
3347
3348         for (i = 0; i < bp->tx_nr_rings; i++) {
3349                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3350                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3351                 u32 map_idx = txr->bnapi->index;
3352                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3353
3354                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3355                                               map_idx, fw_stats_ctx);
3356                 if (rc)
3357                         goto err_out;
3358                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3359         }
3360
3361         for (i = 0; i < bp->rx_nr_rings; i++) {
3362                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3363                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3364                 u32 map_idx = rxr->bnapi->index;
3365
3366                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3367                                               map_idx, INVALID_STATS_CTX_ID);
3368                 if (rc)
3369                         goto err_out;
3370                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3371                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3372                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3373         }
3374
3375         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3376                 for (i = 0; i < bp->rx_nr_rings; i++) {
3377                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3378                         struct bnxt_ring_struct *ring =
3379                                                 &rxr->rx_agg_ring_struct;
3380                         u32 grp_idx = rxr->bnapi->index;
3381                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3382
3383                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3384                                                       HWRM_RING_ALLOC_AGG,
3385                                                       map_idx,
3386                                                       INVALID_STATS_CTX_ID);
3387                         if (rc)
3388                                 goto err_out;
3389
3390                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3391                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3392                                rxr->rx_agg_doorbell);
3393                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3394                 }
3395         }
3396 err_out:
3397         return rc;
3398 }
3399
3400 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3401                                    struct bnxt_ring_struct *ring,
3402                                    u32 ring_type, int cmpl_ring_id)
3403 {
3404         int rc;
3405         struct hwrm_ring_free_input req = {0};
3406         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3407         u16 error_code;
3408
3409         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3410         req.ring_type = ring_type;
3411         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3412
3413         mutex_lock(&bp->hwrm_cmd_lock);
3414         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3415         error_code = le16_to_cpu(resp->error_code);
3416         mutex_unlock(&bp->hwrm_cmd_lock);
3417
3418         if (rc || error_code) {
3419                 switch (ring_type) {
3420                 case RING_FREE_REQ_RING_TYPE_CMPL:
3421                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3422                                    rc);
3423                         return rc;
3424                 case RING_FREE_REQ_RING_TYPE_RX:
3425                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3426                                    rc);
3427                         return rc;
3428                 case RING_FREE_REQ_RING_TYPE_TX:
3429                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3430                                    rc);
3431                         return rc;
3432                 default:
3433                         netdev_err(bp->dev, "Invalid ring\n");
3434                         return -1;
3435                 }
3436         }
3437         return 0;
3438 }
3439
3440 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3441 {
3442         int i;
3443
3444         if (!bp->bnapi)
3445                 return;
3446
3447         for (i = 0; i < bp->tx_nr_rings; i++) {
3448                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3449                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3450                 u32 grp_idx = txr->bnapi->index;
3451                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3452
3453                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3454                         hwrm_ring_free_send_msg(bp, ring,
3455                                                 RING_FREE_REQ_RING_TYPE_TX,
3456                                                 close_path ? cmpl_ring_id :
3457                                                 INVALID_HW_RING_ID);
3458                         ring->fw_ring_id = INVALID_HW_RING_ID;
3459                 }
3460         }
3461
3462         for (i = 0; i < bp->rx_nr_rings; i++) {
3463                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3464                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3465                 u32 grp_idx = rxr->bnapi->index;
3466                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3467
3468                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3469                         hwrm_ring_free_send_msg(bp, ring,
3470                                                 RING_FREE_REQ_RING_TYPE_RX,
3471                                                 close_path ? cmpl_ring_id :
3472                                                 INVALID_HW_RING_ID);
3473                         ring->fw_ring_id = INVALID_HW_RING_ID;
3474                         bp->grp_info[grp_idx].rx_fw_ring_id =
3475                                 INVALID_HW_RING_ID;
3476                 }
3477         }
3478
3479         for (i = 0; i < bp->rx_nr_rings; i++) {
3480                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3481                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3482                 u32 grp_idx = rxr->bnapi->index;
3483                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3484
3485                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3486                         hwrm_ring_free_send_msg(bp, ring,
3487                                                 RING_FREE_REQ_RING_TYPE_RX,
3488                                                 close_path ? cmpl_ring_id :
3489                                                 INVALID_HW_RING_ID);
3490                         ring->fw_ring_id = INVALID_HW_RING_ID;
3491                         bp->grp_info[grp_idx].agg_fw_ring_id =
3492                                 INVALID_HW_RING_ID;
3493                 }
3494         }
3495
3496         for (i = 0; i < bp->cp_nr_rings; i++) {
3497                 struct bnxt_napi *bnapi = bp->bnapi[i];
3498                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3499                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3500
3501                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3502                         hwrm_ring_free_send_msg(bp, ring,
3503                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3504                                                 INVALID_HW_RING_ID);
3505                         ring->fw_ring_id = INVALID_HW_RING_ID;
3506                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3507                 }
3508         }
3509 }
3510
3511 int bnxt_hwrm_set_coal(struct bnxt *bp)
3512 {
3513         int i, rc = 0;
3514         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3515         u16 max_buf, max_buf_irq;
3516         u16 buf_tmr, buf_tmr_irq;
3517         u32 flags;
3518
3519         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3520                                -1, -1);
3521
3522         /* Each rx completion (2 records) should be DMAed immediately */
3523         max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3524         /* max_buf must not be zero */
3525         max_buf = clamp_t(u16, max_buf, 1, 63);
3526         max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3527         buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3528         buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3529
3530         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3531
3532         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3533          * if coal_ticks is less than 25 us.
3534          */
3535         if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3536                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3537
3538         req.flags = cpu_to_le16(flags);
3539         req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3540         req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3541         req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3542         req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3543         req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3544         req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3545         req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3546
3547         mutex_lock(&bp->hwrm_cmd_lock);
3548         for (i = 0; i < bp->cp_nr_rings; i++) {
3549                 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3550
3551                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3552                                         HWRM_CMD_TIMEOUT);
3553                 if (rc)
3554                         break;
3555         }
3556         mutex_unlock(&bp->hwrm_cmd_lock);
3557         return rc;
3558 }
3559
3560 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3561 {
3562         int rc = 0, i;
3563         struct hwrm_stat_ctx_free_input req = {0};
3564
3565         if (!bp->bnapi)
3566                 return 0;
3567
3568         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3569
3570         mutex_lock(&bp->hwrm_cmd_lock);
3571         for (i = 0; i < bp->cp_nr_rings; i++) {
3572                 struct bnxt_napi *bnapi = bp->bnapi[i];
3573                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3574
3575                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3576                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3577
3578                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3579                                                 HWRM_CMD_TIMEOUT);
3580                         if (rc)
3581                                 break;
3582
3583                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3584                 }
3585         }
3586         mutex_unlock(&bp->hwrm_cmd_lock);
3587         return rc;
3588 }
3589
3590 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3591 {
3592         int rc = 0, i;
3593         struct hwrm_stat_ctx_alloc_input req = {0};
3594         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3595
3596         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3597
3598         req.update_period_ms = cpu_to_le32(1000);
3599
3600         mutex_lock(&bp->hwrm_cmd_lock);
3601         for (i = 0; i < bp->cp_nr_rings; i++) {
3602                 struct bnxt_napi *bnapi = bp->bnapi[i];
3603                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3604
3605                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3606
3607                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3608                                         HWRM_CMD_TIMEOUT);
3609                 if (rc)
3610                         break;
3611
3612                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3613
3614                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3615         }
3616         mutex_unlock(&bp->hwrm_cmd_lock);
3617         return 0;
3618 }
3619
3620 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3621 {
3622         int rc = 0;
3623         struct hwrm_func_qcaps_input req = {0};
3624         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3625
3626         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3627         req.fid = cpu_to_le16(0xffff);
3628
3629         mutex_lock(&bp->hwrm_cmd_lock);
3630         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3631         if (rc)
3632                 goto hwrm_func_qcaps_exit;
3633
3634         if (BNXT_PF(bp)) {
3635                 struct bnxt_pf_info *pf = &bp->pf;
3636
3637                 pf->fw_fid = le16_to_cpu(resp->fid);
3638                 pf->port_id = le16_to_cpu(resp->port_id);
3639                 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3640                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3641                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3642                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3643                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3644                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3645                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3646                 if (!pf->max_hw_ring_grps)
3647                         pf->max_hw_ring_grps = pf->max_tx_rings;
3648                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3649                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3650                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3651                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3652                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3653                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3654                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3655                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3656                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3657                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3658                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3659         } else {
3660 #ifdef CONFIG_BNXT_SRIOV
3661                 struct bnxt_vf_info *vf = &bp->vf;
3662
3663                 vf->fw_fid = le16_to_cpu(resp->fid);
3664                 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3665                 if (is_valid_ether_addr(vf->mac_addr))
3666                         /* overwrite netdev dev_adr with admin VF MAC */
3667                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3668                 else
3669                         random_ether_addr(bp->dev->dev_addr);
3670
3671                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3672                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3673                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3674                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3675                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3676                 if (!vf->max_hw_ring_grps)
3677                         vf->max_hw_ring_grps = vf->max_tx_rings;
3678                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3679                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3680                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3681 #endif
3682         }
3683
3684         bp->tx_push_thresh = 0;
3685         if (resp->flags &
3686             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3687                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3688
3689 hwrm_func_qcaps_exit:
3690         mutex_unlock(&bp->hwrm_cmd_lock);
3691         return rc;
3692 }
3693
3694 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3695 {
3696         struct hwrm_func_reset_input req = {0};
3697
3698         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3699         req.enables = 0;
3700
3701         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3702 }
3703
3704 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3705 {
3706         int rc = 0;
3707         struct hwrm_queue_qportcfg_input req = {0};
3708         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3709         u8 i, *qptr;
3710
3711         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3712
3713         mutex_lock(&bp->hwrm_cmd_lock);
3714         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3715         if (rc)
3716                 goto qportcfg_exit;
3717
3718         if (!resp->max_configurable_queues) {
3719                 rc = -EINVAL;
3720                 goto qportcfg_exit;
3721         }
3722         bp->max_tc = resp->max_configurable_queues;
3723         if (bp->max_tc > BNXT_MAX_QUEUE)
3724                 bp->max_tc = BNXT_MAX_QUEUE;
3725
3726         qptr = &resp->queue_id0;
3727         for (i = 0; i < bp->max_tc; i++) {
3728                 bp->q_info[i].queue_id = *qptr++;
3729                 bp->q_info[i].queue_profile = *qptr++;
3730         }
3731
3732 qportcfg_exit:
3733         mutex_unlock(&bp->hwrm_cmd_lock);
3734         return rc;
3735 }
3736
3737 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3738 {
3739         int rc;
3740         struct hwrm_ver_get_input req = {0};
3741         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3742
3743         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3744         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3745         req.hwrm_intf_min = HWRM_VERSION_MINOR;
3746         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3747         mutex_lock(&bp->hwrm_cmd_lock);
3748         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3749         if (rc)
3750                 goto hwrm_ver_get_exit;
3751
3752         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3753
3754         if (resp->hwrm_intf_maj < 1) {
3755                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3756                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
3757                             resp->hwrm_intf_upd);
3758                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3759         }
3760         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3761                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3762                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3763
3764 hwrm_ver_get_exit:
3765         mutex_unlock(&bp->hwrm_cmd_lock);
3766         return rc;
3767 }
3768
3769 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3770 {
3771         if (bp->vxlan_port_cnt) {
3772                 bnxt_hwrm_tunnel_dst_port_free(
3773                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3774         }
3775         bp->vxlan_port_cnt = 0;
3776         if (bp->nge_port_cnt) {
3777                 bnxt_hwrm_tunnel_dst_port_free(
3778                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3779         }
3780         bp->nge_port_cnt = 0;
3781 }
3782
3783 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3784 {
3785         int rc, i;
3786         u32 tpa_flags = 0;
3787
3788         if (set_tpa)
3789                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3790         for (i = 0; i < bp->nr_vnics; i++) {
3791                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3792                 if (rc) {
3793                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3794                                    rc, i);
3795                         return rc;
3796                 }
3797         }
3798         return 0;
3799 }
3800
3801 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3802 {
3803         int i;
3804
3805         for (i = 0; i < bp->nr_vnics; i++)
3806                 bnxt_hwrm_vnic_set_rss(bp, i, false);
3807 }
3808
3809 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3810                                     bool irq_re_init)
3811 {
3812         if (bp->vnic_info) {
3813                 bnxt_hwrm_clear_vnic_filter(bp);
3814                 /* clear all RSS setting before free vnic ctx */
3815                 bnxt_hwrm_clear_vnic_rss(bp);
3816                 bnxt_hwrm_vnic_ctx_free(bp);
3817                 /* before free the vnic, undo the vnic tpa settings */
3818                 if (bp->flags & BNXT_FLAG_TPA)
3819                         bnxt_set_tpa(bp, false);
3820                 bnxt_hwrm_vnic_free(bp);
3821         }
3822         bnxt_hwrm_ring_free(bp, close_path);
3823         bnxt_hwrm_ring_grp_free(bp);
3824         if (irq_re_init) {
3825                 bnxt_hwrm_stat_ctx_free(bp);
3826                 bnxt_hwrm_free_tunnel_ports(bp);
3827         }
3828 }
3829
3830 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3831 {
3832         int rc;
3833
3834         /* allocate context for vnic */
3835         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3836         if (rc) {
3837                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3838                            vnic_id, rc);
3839                 goto vnic_setup_err;
3840         }
3841         bp->rsscos_nr_ctxs++;
3842
3843         /* configure default vnic, ring grp */
3844         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3845         if (rc) {
3846                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3847                            vnic_id, rc);
3848                 goto vnic_setup_err;
3849         }
3850
3851         /* Enable RSS hashing on vnic */
3852         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3853         if (rc) {
3854                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3855                            vnic_id, rc);
3856                 goto vnic_setup_err;
3857         }
3858
3859         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3860                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3861                 if (rc) {
3862                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3863                                    vnic_id, rc);
3864                 }
3865         }
3866
3867 vnic_setup_err:
3868         return rc;
3869 }
3870
3871 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3872 {
3873 #ifdef CONFIG_RFS_ACCEL
3874         int i, rc = 0;
3875
3876         for (i = 0; i < bp->rx_nr_rings; i++) {
3877                 u16 vnic_id = i + 1;
3878                 u16 ring_id = i;
3879
3880                 if (vnic_id >= bp->nr_vnics)
3881                         break;
3882
3883                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3884                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
3885                 if (rc) {
3886                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3887                                    vnic_id, rc);
3888                         break;
3889                 }
3890                 rc = bnxt_setup_vnic(bp, vnic_id);
3891                 if (rc)
3892                         break;
3893         }
3894         return rc;
3895 #else
3896         return 0;
3897 #endif
3898 }
3899
3900 static int bnxt_cfg_rx_mode(struct bnxt *);
3901
3902 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3903 {
3904         int rc = 0;
3905
3906         if (irq_re_init) {
3907                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3908                 if (rc) {
3909                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3910                                    rc);
3911                         goto err_out;
3912                 }
3913         }
3914
3915         rc = bnxt_hwrm_ring_alloc(bp);
3916         if (rc) {
3917                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3918                 goto err_out;
3919         }
3920
3921         rc = bnxt_hwrm_ring_grp_alloc(bp);
3922         if (rc) {
3923                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3924                 goto err_out;
3925         }
3926
3927         /* default vnic 0 */
3928         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3929         if (rc) {
3930                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3931                 goto err_out;
3932         }
3933
3934         rc = bnxt_setup_vnic(bp, 0);
3935         if (rc)
3936                 goto err_out;
3937
3938         if (bp->flags & BNXT_FLAG_RFS) {
3939                 rc = bnxt_alloc_rfs_vnics(bp);
3940                 if (rc)
3941                         goto err_out;
3942         }
3943
3944         if (bp->flags & BNXT_FLAG_TPA) {
3945                 rc = bnxt_set_tpa(bp, true);
3946                 if (rc)
3947                         goto err_out;
3948         }
3949
3950         if (BNXT_VF(bp))
3951                 bnxt_update_vf_mac(bp);
3952
3953         /* Filter for default vnic 0 */
3954         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3955         if (rc) {
3956                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3957                 goto err_out;
3958         }
3959         bp->vnic_info[0].uc_filter_count = 1;
3960
3961         bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3962
3963         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3964                 bp->vnic_info[0].rx_mask |=
3965                                 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3966
3967         rc = bnxt_cfg_rx_mode(bp);
3968         if (rc)
3969                 goto err_out;
3970
3971         rc = bnxt_hwrm_set_coal(bp);
3972         if (rc)
3973                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3974                             rc);
3975
3976         return 0;
3977
3978 err_out:
3979         bnxt_hwrm_resource_free(bp, 0, true);
3980
3981         return rc;
3982 }
3983
3984 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3985 {
3986         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3987         return 0;
3988 }
3989
3990 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3991 {
3992         bnxt_init_rx_rings(bp);
3993         bnxt_init_tx_rings(bp);
3994         bnxt_init_ring_grps(bp, irq_re_init);
3995         bnxt_init_vnics(bp);
3996
3997         return bnxt_init_chip(bp, irq_re_init);
3998 }
3999
4000 static void bnxt_disable_int(struct bnxt *bp)
4001 {
4002         int i;
4003
4004         if (!bp->bnapi)
4005                 return;
4006
4007         for (i = 0; i < bp->cp_nr_rings; i++) {
4008                 struct bnxt_napi *bnapi = bp->bnapi[i];
4009                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4010
4011                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4012         }
4013 }
4014
4015 static void bnxt_enable_int(struct bnxt *bp)
4016 {
4017         int i;
4018
4019         atomic_set(&bp->intr_sem, 0);
4020         for (i = 0; i < bp->cp_nr_rings; i++) {
4021                 struct bnxt_napi *bnapi = bp->bnapi[i];
4022                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4023
4024                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4025         }
4026 }
4027
4028 static int bnxt_set_real_num_queues(struct bnxt *bp)
4029 {
4030         int rc;
4031         struct net_device *dev = bp->dev;
4032
4033         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4034         if (rc)
4035                 return rc;
4036
4037         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4038         if (rc)
4039                 return rc;
4040
4041 #ifdef CONFIG_RFS_ACCEL
4042         if (bp->flags & BNXT_FLAG_RFS)
4043                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4044 #endif
4045
4046         return rc;
4047 }
4048
4049 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4050                            bool shared)
4051 {
4052         int _rx = *rx, _tx = *tx;
4053
4054         if (shared) {
4055                 *rx = min_t(int, _rx, max);
4056                 *tx = min_t(int, _tx, max);
4057         } else {
4058                 if (max < 2)
4059                         return -ENOMEM;
4060
4061                 while (_rx + _tx > max) {
4062                         if (_rx > _tx && _rx > 1)
4063                                 _rx--;
4064                         else if (_tx > 1)
4065                                 _tx--;
4066                 }
4067                 *rx = _rx;
4068                 *tx = _tx;
4069         }
4070         return 0;
4071 }
4072
4073 static int bnxt_setup_msix(struct bnxt *bp)
4074 {
4075         struct msix_entry *msix_ent;
4076         struct net_device *dev = bp->dev;
4077         int i, total_vecs, rc = 0, min = 1;
4078         const int len = sizeof(bp->irq_tbl[0].name);
4079
4080         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4081         total_vecs = bp->cp_nr_rings;
4082
4083         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4084         if (!msix_ent)
4085                 return -ENOMEM;
4086
4087         for (i = 0; i < total_vecs; i++) {
4088                 msix_ent[i].entry = i;
4089                 msix_ent[i].vector = 0;
4090         }
4091
4092         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4093                 min = 2;
4094
4095         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4096         if (total_vecs < 0) {
4097                 rc = -ENODEV;
4098                 goto msix_setup_exit;
4099         }
4100
4101         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4102         if (bp->irq_tbl) {
4103                 int tcs;
4104
4105                 /* Trim rings based upon num of vectors allocated */
4106                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4107                                      total_vecs, min == 1);
4108                 if (rc)
4109                         goto msix_setup_exit;
4110
4111                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4112                 tcs = netdev_get_num_tc(dev);
4113                 if (tcs > 1) {
4114                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4115                         if (bp->tx_nr_rings_per_tc == 0) {
4116                                 netdev_reset_tc(dev);
4117                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4118                         } else {
4119                                 int i, off, count;
4120
4121                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4122                                 for (i = 0; i < tcs; i++) {
4123                                         count = bp->tx_nr_rings_per_tc;
4124                                         off = i * count;
4125                                         netdev_set_tc_queue(dev, i, count, off);
4126                                 }
4127                         }
4128                 }
4129                 bp->cp_nr_rings = total_vecs;
4130
4131                 for (i = 0; i < bp->cp_nr_rings; i++) {
4132                         char *attr;
4133
4134                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4135                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4136                                 attr = "TxRx";
4137                         else if (i < bp->rx_nr_rings)
4138                                 attr = "rx";
4139                         else
4140                                 attr = "tx";
4141
4142                         snprintf(bp->irq_tbl[i].name, len,
4143                                  "%s-%s-%d", dev->name, attr, i);
4144                         bp->irq_tbl[i].handler = bnxt_msix;
4145                 }
4146                 rc = bnxt_set_real_num_queues(bp);
4147                 if (rc)
4148                         goto msix_setup_exit;
4149         } else {
4150                 rc = -ENOMEM;
4151                 goto msix_setup_exit;
4152         }
4153         bp->flags |= BNXT_FLAG_USING_MSIX;
4154         kfree(msix_ent);
4155         return 0;
4156
4157 msix_setup_exit:
4158         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4159         pci_disable_msix(bp->pdev);
4160         kfree(msix_ent);
4161         return rc;
4162 }
4163
4164 static int bnxt_setup_inta(struct bnxt *bp)
4165 {
4166         int rc;
4167         const int len = sizeof(bp->irq_tbl[0].name);
4168
4169         if (netdev_get_num_tc(bp->dev))
4170                 netdev_reset_tc(bp->dev);
4171
4172         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4173         if (!bp->irq_tbl) {
4174                 rc = -ENOMEM;
4175                 return rc;
4176         }
4177         bp->rx_nr_rings = 1;
4178         bp->tx_nr_rings = 1;
4179         bp->cp_nr_rings = 1;
4180         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4181         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4182         bp->irq_tbl[0].vector = bp->pdev->irq;
4183         snprintf(bp->irq_tbl[0].name, len,
4184                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4185         bp->irq_tbl[0].handler = bnxt_inta;
4186         rc = bnxt_set_real_num_queues(bp);
4187         return rc;
4188 }
4189
4190 static int bnxt_setup_int_mode(struct bnxt *bp)
4191 {
4192         int rc = 0;
4193
4194         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4195                 rc = bnxt_setup_msix(bp);
4196
4197         if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4198                 /* fallback to INTA */
4199                 rc = bnxt_setup_inta(bp);
4200         }
4201         return rc;
4202 }
4203
4204 static void bnxt_free_irq(struct bnxt *bp)
4205 {
4206         struct bnxt_irq *irq;
4207         int i;
4208
4209 #ifdef CONFIG_RFS_ACCEL
4210         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4211         bp->dev->rx_cpu_rmap = NULL;
4212 #endif
4213         if (!bp->irq_tbl)
4214                 return;
4215
4216         for (i = 0; i < bp->cp_nr_rings; i++) {
4217                 irq = &bp->irq_tbl[i];
4218                 if (irq->requested)
4219                         free_irq(irq->vector, bp->bnapi[i]);
4220                 irq->requested = 0;
4221         }
4222         if (bp->flags & BNXT_FLAG_USING_MSIX)
4223                 pci_disable_msix(bp->pdev);
4224         kfree(bp->irq_tbl);
4225         bp->irq_tbl = NULL;
4226 }
4227
4228 static int bnxt_request_irq(struct bnxt *bp)
4229 {
4230         int i, j, rc = 0;
4231         unsigned long flags = 0;
4232 #ifdef CONFIG_RFS_ACCEL
4233         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4234 #endif
4235
4236         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4237                 flags = IRQF_SHARED;
4238
4239         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4240                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4241 #ifdef CONFIG_RFS_ACCEL
4242                 if (rmap && bp->bnapi[i]->rx_ring) {
4243                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4244                         if (rc)
4245                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4246                                             j);
4247                         j++;
4248                 }
4249 #endif
4250                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4251                                  bp->bnapi[i]);
4252                 if (rc)
4253                         break;
4254
4255                 irq->requested = 1;
4256         }
4257         return rc;
4258 }
4259
4260 static void bnxt_del_napi(struct bnxt *bp)
4261 {
4262         int i;
4263
4264         if (!bp->bnapi)
4265                 return;
4266
4267         for (i = 0; i < bp->cp_nr_rings; i++) {
4268                 struct bnxt_napi *bnapi = bp->bnapi[i];
4269
4270                 napi_hash_del(&bnapi->napi);
4271                 netif_napi_del(&bnapi->napi);
4272         }
4273 }
4274
4275 static void bnxt_init_napi(struct bnxt *bp)
4276 {
4277         int i;
4278         struct bnxt_napi *bnapi;
4279
4280         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4281                 for (i = 0; i < bp->cp_nr_rings; i++) {
4282                         bnapi = bp->bnapi[i];
4283                         netif_napi_add(bp->dev, &bnapi->napi,
4284                                        bnxt_poll, 64);
4285                 }
4286         } else {
4287                 bnapi = bp->bnapi[0];
4288                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4289         }
4290 }
4291
4292 static void bnxt_disable_napi(struct bnxt *bp)
4293 {
4294         int i;
4295
4296         if (!bp->bnapi)
4297                 return;
4298
4299         for (i = 0; i < bp->cp_nr_rings; i++) {
4300                 napi_disable(&bp->bnapi[i]->napi);
4301                 bnxt_disable_poll(bp->bnapi[i]);
4302         }
4303 }
4304
4305 static void bnxt_enable_napi(struct bnxt *bp)
4306 {
4307         int i;
4308
4309         for (i = 0; i < bp->cp_nr_rings; i++) {
4310                 bnxt_enable_poll(bp->bnapi[i]);
4311                 napi_enable(&bp->bnapi[i]->napi);
4312         }
4313 }
4314
4315 static void bnxt_tx_disable(struct bnxt *bp)
4316 {
4317         int i;
4318         struct bnxt_tx_ring_info *txr;
4319         struct netdev_queue *txq;
4320
4321         if (bp->tx_ring) {
4322                 for (i = 0; i < bp->tx_nr_rings; i++) {
4323                         txr = &bp->tx_ring[i];
4324                         txq = netdev_get_tx_queue(bp->dev, i);
4325                         __netif_tx_lock(txq, smp_processor_id());
4326                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4327                         __netif_tx_unlock(txq);
4328                 }
4329         }
4330         /* Stop all TX queues */
4331         netif_tx_disable(bp->dev);
4332         netif_carrier_off(bp->dev);
4333 }
4334
4335 static void bnxt_tx_enable(struct bnxt *bp)
4336 {
4337         int i;
4338         struct bnxt_tx_ring_info *txr;
4339         struct netdev_queue *txq;
4340
4341         for (i = 0; i < bp->tx_nr_rings; i++) {
4342                 txr = &bp->tx_ring[i];
4343                 txq = netdev_get_tx_queue(bp->dev, i);
4344                 txr->dev_state = 0;
4345         }
4346         netif_tx_wake_all_queues(bp->dev);
4347         if (bp->link_info.link_up)
4348                 netif_carrier_on(bp->dev);
4349 }
4350
4351 static void bnxt_report_link(struct bnxt *bp)
4352 {
4353         if (bp->link_info.link_up) {
4354                 const char *duplex;
4355                 const char *flow_ctrl;
4356                 u16 speed;
4357
4358                 netif_carrier_on(bp->dev);
4359                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4360                         duplex = "full";
4361                 else
4362                         duplex = "half";
4363                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4364                         flow_ctrl = "ON - receive & transmit";
4365                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4366                         flow_ctrl = "ON - transmit";
4367                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4368                         flow_ctrl = "ON - receive";
4369                 else
4370                         flow_ctrl = "none";
4371                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4372                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4373                             speed, duplex, flow_ctrl);
4374         } else {
4375                 netif_carrier_off(bp->dev);
4376                 netdev_err(bp->dev, "NIC Link is Down\n");
4377         }
4378 }
4379
4380 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4381 {
4382         int rc = 0;
4383         struct bnxt_link_info *link_info = &bp->link_info;
4384         struct hwrm_port_phy_qcfg_input req = {0};
4385         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4386         u8 link_up = link_info->link_up;
4387
4388         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4389
4390         mutex_lock(&bp->hwrm_cmd_lock);
4391         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4392         if (rc) {
4393                 mutex_unlock(&bp->hwrm_cmd_lock);
4394                 return rc;
4395         }
4396
4397         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4398         link_info->phy_link_status = resp->link;
4399         link_info->duplex =  resp->duplex;
4400         link_info->pause = resp->pause;
4401         link_info->auto_mode = resp->auto_mode;
4402         link_info->auto_pause_setting = resp->auto_pause;
4403         link_info->force_pause_setting = resp->force_pause;
4404         link_info->duplex_setting = resp->duplex;
4405         if (link_info->phy_link_status == BNXT_LINK_LINK)
4406                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4407         else
4408                 link_info->link_speed = 0;
4409         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4410         link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4411         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4412         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4413         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4414         link_info->phy_ver[0] = resp->phy_maj;
4415         link_info->phy_ver[1] = resp->phy_min;
4416         link_info->phy_ver[2] = resp->phy_bld;
4417         link_info->media_type = resp->media_type;
4418         link_info->transceiver = resp->transceiver_type;
4419         link_info->phy_addr = resp->phy_addr;
4420
4421         /* TODO: need to add more logic to report VF link */
4422         if (chng_link_state) {
4423                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4424                         link_info->link_up = 1;
4425                 else
4426                         link_info->link_up = 0;
4427                 if (link_up != link_info->link_up)
4428                         bnxt_report_link(bp);
4429         } else {
4430                 /* alwasy link down if not require to update link state */
4431                 link_info->link_up = 0;
4432         }
4433         mutex_unlock(&bp->hwrm_cmd_lock);
4434         return 0;
4435 }
4436
4437 static void
4438 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4439 {
4440         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4441                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4442                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4443                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4444                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4445                 req->enables |=
4446                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4447         } else {
4448                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4449                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4450                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4451                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4452                 req->enables |=
4453                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4454         }
4455 }
4456
4457 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4458                                       struct hwrm_port_phy_cfg_input *req)
4459 {
4460         u8 autoneg = bp->link_info.autoneg;
4461         u16 fw_link_speed = bp->link_info.req_link_speed;
4462         u32 advertising = bp->link_info.advertising;
4463
4464         if (autoneg & BNXT_AUTONEG_SPEED) {
4465                 req->auto_mode |=
4466                         PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4467
4468                 req->enables |= cpu_to_le32(
4469                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4470                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4471
4472                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4473                 req->flags |=
4474                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4475         } else {
4476                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4477                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4478         }
4479
4480         /* currently don't support half duplex */
4481         req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4482         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4483         /* tell chimp that the setting takes effect immediately */
4484         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4485 }
4486
4487 int bnxt_hwrm_set_pause(struct bnxt *bp)
4488 {
4489         struct hwrm_port_phy_cfg_input req = {0};
4490         int rc;
4491
4492         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4493         bnxt_hwrm_set_pause_common(bp, &req);
4494
4495         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4496             bp->link_info.force_link_chng)
4497                 bnxt_hwrm_set_link_common(bp, &req);
4498
4499         mutex_lock(&bp->hwrm_cmd_lock);
4500         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4501         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4502                 /* since changing of pause setting doesn't trigger any link
4503                  * change event, the driver needs to update the current pause
4504                  * result upon successfully return of the phy_cfg command
4505                  */
4506                 bp->link_info.pause =
4507                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4508                 bp->link_info.auto_pause_setting = 0;
4509                 if (!bp->link_info.force_link_chng)
4510                         bnxt_report_link(bp);
4511         }
4512         bp->link_info.force_link_chng = false;
4513         mutex_unlock(&bp->hwrm_cmd_lock);
4514         return rc;
4515 }
4516
4517 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4518 {
4519         struct hwrm_port_phy_cfg_input req = {0};
4520
4521         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4522         if (set_pause)
4523                 bnxt_hwrm_set_pause_common(bp, &req);
4524
4525         bnxt_hwrm_set_link_common(bp, &req);
4526         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4527 }
4528
4529 static int bnxt_update_phy_setting(struct bnxt *bp)
4530 {
4531         int rc;
4532         bool update_link = false;
4533         bool update_pause = false;
4534         struct bnxt_link_info *link_info = &bp->link_info;
4535
4536         rc = bnxt_update_link(bp, true);
4537         if (rc) {
4538                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4539                            rc);
4540                 return rc;
4541         }
4542         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4543             link_info->auto_pause_setting != link_info->req_flow_ctrl)
4544                 update_pause = true;
4545         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4546             link_info->force_pause_setting != link_info->req_flow_ctrl)
4547                 update_pause = true;
4548         if (link_info->req_duplex != link_info->duplex_setting)
4549                 update_link = true;
4550         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4551                 if (BNXT_AUTO_MODE(link_info->auto_mode))
4552                         update_link = true;
4553                 if (link_info->req_link_speed != link_info->force_link_speed)
4554                         update_link = true;
4555         } else {
4556                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4557                         update_link = true;
4558                 if (link_info->advertising != link_info->auto_link_speeds)
4559                         update_link = true;
4560                 if (link_info->req_link_speed != link_info->auto_link_speed)
4561                         update_link = true;
4562         }
4563
4564         if (update_link)
4565                 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4566         else if (update_pause)
4567                 rc = bnxt_hwrm_set_pause(bp);
4568         if (rc) {
4569                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4570                            rc);
4571                 return rc;
4572         }
4573
4574         return rc;
4575 }
4576
4577 /* Common routine to pre-map certain register block to different GRC window.
4578  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4579  * in PF and 3 windows in VF that can be customized to map in different
4580  * register blocks.
4581  */
4582 static void bnxt_preset_reg_win(struct bnxt *bp)
4583 {
4584         if (BNXT_PF(bp)) {
4585                 /* CAG registers map to GRC window #4 */
4586                 writel(BNXT_CAG_REG_BASE,
4587                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4588         }
4589 }
4590
4591 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4592 {
4593         int rc = 0;
4594
4595         bnxt_preset_reg_win(bp);
4596         netif_carrier_off(bp->dev);
4597         if (irq_re_init) {
4598                 rc = bnxt_setup_int_mode(bp);
4599                 if (rc) {
4600                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4601                                    rc);
4602                         return rc;
4603                 }
4604         }
4605         if ((bp->flags & BNXT_FLAG_RFS) &&
4606             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4607                 /* disable RFS if falling back to INTA */
4608                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4609                 bp->flags &= ~BNXT_FLAG_RFS;
4610         }
4611
4612         rc = bnxt_alloc_mem(bp, irq_re_init);
4613         if (rc) {
4614                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4615                 goto open_err_free_mem;
4616         }
4617
4618         if (irq_re_init) {
4619                 bnxt_init_napi(bp);
4620                 rc = bnxt_request_irq(bp);
4621                 if (rc) {
4622                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4623                         goto open_err;
4624                 }
4625         }
4626
4627         bnxt_enable_napi(bp);
4628
4629         rc = bnxt_init_nic(bp, irq_re_init);
4630         if (rc) {
4631                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4632                 goto open_err;
4633         }
4634
4635         if (link_re_init) {
4636                 rc = bnxt_update_phy_setting(bp);
4637                 if (rc)
4638                         goto open_err;
4639         }
4640
4641         if (irq_re_init) {
4642 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4643                 vxlan_get_rx_port(bp->dev);
4644 #endif
4645                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4646                                 bp, htons(0x17c1),
4647                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4648                         bp->nge_port_cnt = 1;
4649         }
4650
4651         set_bit(BNXT_STATE_OPEN, &bp->state);
4652         bnxt_enable_int(bp);
4653         /* Enable TX queues */
4654         bnxt_tx_enable(bp);
4655         mod_timer(&bp->timer, jiffies + bp->current_interval);
4656
4657         return 0;
4658
4659 open_err:
4660         bnxt_disable_napi(bp);
4661         bnxt_del_napi(bp);
4662
4663 open_err_free_mem:
4664         bnxt_free_skbs(bp);
4665         bnxt_free_irq(bp);
4666         bnxt_free_mem(bp, true);
4667         return rc;
4668 }
4669
4670 /* rtnl_lock held */
4671 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4672 {
4673         int rc = 0;
4674
4675         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4676         if (rc) {
4677                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4678                 dev_close(bp->dev);
4679         }
4680         return rc;
4681 }
4682
4683 static int bnxt_open(struct net_device *dev)
4684 {
4685         struct bnxt *bp = netdev_priv(dev);
4686         int rc = 0;
4687
4688         rc = bnxt_hwrm_func_reset(bp);
4689         if (rc) {
4690                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4691                            rc);
4692                 rc = -1;
4693                 return rc;
4694         }
4695         return __bnxt_open_nic(bp, true, true);
4696 }
4697
4698 static void bnxt_disable_int_sync(struct bnxt *bp)
4699 {
4700         int i;
4701
4702         atomic_inc(&bp->intr_sem);
4703         if (!netif_running(bp->dev))
4704                 return;
4705
4706         bnxt_disable_int(bp);
4707         for (i = 0; i < bp->cp_nr_rings; i++)
4708                 synchronize_irq(bp->irq_tbl[i].vector);
4709 }
4710
4711 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4712 {
4713         int rc = 0;
4714
4715 #ifdef CONFIG_BNXT_SRIOV
4716         if (bp->sriov_cfg) {
4717                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4718                                                       !bp->sriov_cfg,
4719                                                       BNXT_SRIOV_CFG_WAIT_TMO);
4720                 if (rc)
4721                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4722         }
4723 #endif
4724         /* Change device state to avoid TX queue wake up's */
4725         bnxt_tx_disable(bp);
4726
4727         clear_bit(BNXT_STATE_OPEN, &bp->state);
4728         smp_mb__after_atomic();
4729         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4730                 msleep(20);
4731
4732         /* Flush rings before disabling interrupts */
4733         bnxt_shutdown_nic(bp, irq_re_init);
4734
4735         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4736
4737         bnxt_disable_napi(bp);
4738         bnxt_disable_int_sync(bp);
4739         del_timer_sync(&bp->timer);
4740         bnxt_free_skbs(bp);
4741
4742         if (irq_re_init) {
4743                 bnxt_free_irq(bp);
4744                 bnxt_del_napi(bp);
4745         }
4746         bnxt_free_mem(bp, irq_re_init);
4747         return rc;
4748 }
4749
4750 static int bnxt_close(struct net_device *dev)
4751 {
4752         struct bnxt *bp = netdev_priv(dev);
4753
4754         bnxt_close_nic(bp, true, true);
4755         return 0;
4756 }
4757
4758 /* rtnl_lock held */
4759 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4760 {
4761         switch (cmd) {
4762         case SIOCGMIIPHY:
4763                 /* fallthru */
4764         case SIOCGMIIREG: {
4765                 if (!netif_running(dev))
4766                         return -EAGAIN;
4767
4768                 return 0;
4769         }
4770
4771         case SIOCSMIIREG:
4772                 if (!netif_running(dev))
4773                         return -EAGAIN;
4774
4775                 return 0;
4776
4777         default:
4778                 /* do nothing */
4779                 break;
4780         }
4781         return -EOPNOTSUPP;
4782 }
4783
4784 static struct rtnl_link_stats64 *
4785 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4786 {
4787         u32 i;
4788         struct bnxt *bp = netdev_priv(dev);
4789
4790         memset(stats, 0, sizeof(struct rtnl_link_stats64));
4791
4792         if (!bp->bnapi)
4793                 return stats;
4794
4795         /* TODO check if we need to synchronize with bnxt_close path */
4796         for (i = 0; i < bp->cp_nr_rings; i++) {
4797                 struct bnxt_napi *bnapi = bp->bnapi[i];
4798                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4799                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4800
4801                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4802                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4803                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4804
4805                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4806                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4807                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4808
4809                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4810                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4811                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4812
4813                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4814                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4815                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4816
4817                 stats->rx_missed_errors +=
4818                         le64_to_cpu(hw_stats->rx_discard_pkts);
4819
4820                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4821
4822                 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4823
4824                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4825         }
4826
4827         return stats;
4828 }
4829
4830 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4831 {
4832         struct net_device *dev = bp->dev;
4833         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4834         struct netdev_hw_addr *ha;
4835         u8 *haddr;
4836         int mc_count = 0;
4837         bool update = false;
4838         int off = 0;
4839
4840         netdev_for_each_mc_addr(ha, dev) {
4841                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4842                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4843                         vnic->mc_list_count = 0;
4844                         return false;
4845                 }
4846                 haddr = ha->addr;
4847                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4848                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4849                         update = true;
4850                 }
4851                 off += ETH_ALEN;
4852                 mc_count++;
4853         }
4854         if (mc_count)
4855                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4856
4857         if (mc_count != vnic->mc_list_count) {
4858                 vnic->mc_list_count = mc_count;
4859                 update = true;
4860         }
4861         return update;
4862 }
4863
4864 static bool bnxt_uc_list_updated(struct bnxt *bp)
4865 {
4866         struct net_device *dev = bp->dev;
4867         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4868         struct netdev_hw_addr *ha;
4869         int off = 0;
4870
4871         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4872                 return true;
4873
4874         netdev_for_each_uc_addr(ha, dev) {
4875                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4876                         return true;
4877
4878                 off += ETH_ALEN;
4879         }
4880         return false;
4881 }
4882
4883 static void bnxt_set_rx_mode(struct net_device *dev)
4884 {
4885         struct bnxt *bp = netdev_priv(dev);
4886         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4887         u32 mask = vnic->rx_mask;
4888         bool mc_update = false;
4889         bool uc_update;
4890
4891         if (!netif_running(dev))
4892                 return;
4893
4894         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4895                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4896                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4897
4898         /* Only allow PF to be in promiscuous mode */
4899         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4900                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4901
4902         uc_update = bnxt_uc_list_updated(bp);
4903
4904         if (dev->flags & IFF_ALLMULTI) {
4905                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4906                 vnic->mc_list_count = 0;
4907         } else {
4908                 mc_update = bnxt_mc_list_updated(bp, &mask);
4909         }
4910
4911         if (mask != vnic->rx_mask || uc_update || mc_update) {
4912                 vnic->rx_mask = mask;
4913
4914                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4915                 schedule_work(&bp->sp_task);
4916         }
4917 }
4918
4919 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4920 {
4921         struct net_device *dev = bp->dev;
4922         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4923         struct netdev_hw_addr *ha;
4924         int i, off = 0, rc;
4925         bool uc_update;
4926
4927         netif_addr_lock_bh(dev);
4928         uc_update = bnxt_uc_list_updated(bp);
4929         netif_addr_unlock_bh(dev);
4930
4931         if (!uc_update)
4932                 goto skip_uc;
4933
4934         mutex_lock(&bp->hwrm_cmd_lock);
4935         for (i = 1; i < vnic->uc_filter_count; i++) {
4936                 struct hwrm_cfa_l2_filter_free_input req = {0};
4937
4938                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4939                                        -1);
4940
4941                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4942
4943                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4944                                         HWRM_CMD_TIMEOUT);
4945         }
4946         mutex_unlock(&bp->hwrm_cmd_lock);
4947
4948         vnic->uc_filter_count = 1;
4949
4950         netif_addr_lock_bh(dev);
4951         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4952                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4953         } else {
4954                 netdev_for_each_uc_addr(ha, dev) {
4955                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4956                         off += ETH_ALEN;
4957                         vnic->uc_filter_count++;
4958                 }
4959         }
4960         netif_addr_unlock_bh(dev);
4961
4962         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4963                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4964                 if (rc) {
4965                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4966                                    rc);
4967                         vnic->uc_filter_count = i;
4968                         return rc;
4969                 }
4970         }
4971
4972 skip_uc:
4973         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4974         if (rc)
4975                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4976                            rc);
4977
4978         return rc;
4979 }
4980
4981 static bool bnxt_rfs_capable(struct bnxt *bp)
4982 {
4983 #ifdef CONFIG_RFS_ACCEL
4984         struct bnxt_pf_info *pf = &bp->pf;
4985         int vnics;
4986
4987         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
4988                 return false;
4989
4990         vnics = 1 + bp->rx_nr_rings;
4991         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
4992                 return false;
4993
4994         return true;
4995 #else
4996         return false;
4997 #endif
4998 }
4999
5000 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5001                                            netdev_features_t features)
5002 {
5003         struct bnxt *bp = netdev_priv(dev);
5004
5005         if (!bnxt_rfs_capable(bp))
5006                 features &= ~NETIF_F_NTUPLE;
5007         return features;
5008 }
5009
5010 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5011 {
5012         struct bnxt *bp = netdev_priv(dev);
5013         u32 flags = bp->flags;
5014         u32 changes;
5015         int rc = 0;
5016         bool re_init = false;
5017         bool update_tpa = false;
5018
5019         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5020         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5021                 flags |= BNXT_FLAG_GRO;
5022         if (features & NETIF_F_LRO)
5023                 flags |= BNXT_FLAG_LRO;
5024
5025         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5026                 flags |= BNXT_FLAG_STRIP_VLAN;
5027
5028         if (features & NETIF_F_NTUPLE)
5029                 flags |= BNXT_FLAG_RFS;
5030
5031         changes = flags ^ bp->flags;
5032         if (changes & BNXT_FLAG_TPA) {
5033                 update_tpa = true;
5034                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5035                     (flags & BNXT_FLAG_TPA) == 0)
5036                         re_init = true;
5037         }
5038
5039         if (changes & ~BNXT_FLAG_TPA)
5040                 re_init = true;
5041
5042         if (flags != bp->flags) {
5043                 u32 old_flags = bp->flags;
5044
5045                 bp->flags = flags;
5046
5047                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5048                         if (update_tpa)
5049                                 bnxt_set_ring_params(bp);
5050                         return rc;
5051                 }
5052
5053                 if (re_init) {
5054                         bnxt_close_nic(bp, false, false);
5055                         if (update_tpa)
5056                                 bnxt_set_ring_params(bp);
5057
5058                         return bnxt_open_nic(bp, false, false);
5059                 }
5060                 if (update_tpa) {
5061                         rc = bnxt_set_tpa(bp,
5062                                           (flags & BNXT_FLAG_TPA) ?
5063                                           true : false);
5064                         if (rc)
5065                                 bp->flags = old_flags;
5066                 }
5067         }
5068         return rc;
5069 }
5070
5071 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5072 {
5073         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5074         int i = bnapi->index;
5075
5076         if (!txr)
5077                 return;
5078
5079         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5080                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5081                     txr->tx_cons);
5082 }
5083
5084 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5085 {
5086         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5087         int i = bnapi->index;
5088
5089         if (!rxr)
5090                 return;
5091
5092         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5093                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5094                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5095                     rxr->rx_sw_agg_prod);
5096 }
5097
5098 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5099 {
5100         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5101         int i = bnapi->index;
5102
5103         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5104                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5105 }
5106
5107 static void bnxt_dbg_dump_states(struct bnxt *bp)
5108 {
5109         int i;
5110         struct bnxt_napi *bnapi;
5111
5112         for (i = 0; i < bp->cp_nr_rings; i++) {
5113                 bnapi = bp->bnapi[i];
5114                 if (netif_msg_drv(bp)) {
5115                         bnxt_dump_tx_sw_state(bnapi);
5116                         bnxt_dump_rx_sw_state(bnapi);
5117                         bnxt_dump_cp_sw_state(bnapi);
5118                 }
5119         }
5120 }
5121
5122 static void bnxt_reset_task(struct bnxt *bp)
5123 {
5124         bnxt_dbg_dump_states(bp);
5125         if (netif_running(bp->dev)) {
5126                 bnxt_close_nic(bp, false, false);
5127                 bnxt_open_nic(bp, false, false);
5128         }
5129 }
5130
5131 static void bnxt_tx_timeout(struct net_device *dev)
5132 {
5133         struct bnxt *bp = netdev_priv(dev);
5134
5135         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5136         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5137         schedule_work(&bp->sp_task);
5138 }
5139
5140 #ifdef CONFIG_NET_POLL_CONTROLLER
5141 static void bnxt_poll_controller(struct net_device *dev)
5142 {
5143         struct bnxt *bp = netdev_priv(dev);
5144         int i;
5145
5146         for (i = 0; i < bp->cp_nr_rings; i++) {
5147                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5148
5149                 disable_irq(irq->vector);
5150                 irq->handler(irq->vector, bp->bnapi[i]);
5151                 enable_irq(irq->vector);
5152         }
5153 }
5154 #endif
5155
5156 static void bnxt_timer(unsigned long data)
5157 {
5158         struct bnxt *bp = (struct bnxt *)data;
5159         struct net_device *dev = bp->dev;
5160
5161         if (!netif_running(dev))
5162                 return;
5163
5164         if (atomic_read(&bp->intr_sem) != 0)
5165                 goto bnxt_restart_timer;
5166
5167 bnxt_restart_timer:
5168         mod_timer(&bp->timer, jiffies + bp->current_interval);
5169 }
5170
5171 static void bnxt_cfg_ntp_filters(struct bnxt *);
5172
5173 static void bnxt_sp_task(struct work_struct *work)
5174 {
5175         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5176         int rc;
5177
5178         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5179         smp_mb__after_atomic();
5180         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5181                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5182                 return;
5183         }
5184
5185         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5186                 bnxt_cfg_rx_mode(bp);
5187
5188         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5189                 bnxt_cfg_ntp_filters(bp);
5190         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5191                 rc = bnxt_update_link(bp, true);
5192                 if (rc)
5193                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5194                                    rc);
5195         }
5196         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5197                 bnxt_hwrm_exec_fwd_req(bp);
5198         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5199                 bnxt_hwrm_tunnel_dst_port_alloc(
5200                         bp, bp->vxlan_port,
5201                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5202         }
5203         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5204                 bnxt_hwrm_tunnel_dst_port_free(
5205                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5206         }
5207         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5208                 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5209                  * for BNXT_STATE_IN_SP_TASK to clear.
5210                  */
5211                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5212                 rtnl_lock();
5213                 bnxt_reset_task(bp);
5214                 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5215                 rtnl_unlock();
5216         }
5217
5218         smp_mb__before_atomic();
5219         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5220 }
5221
5222 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5223 {
5224         int rc;
5225         struct bnxt *bp = netdev_priv(dev);
5226
5227         SET_NETDEV_DEV(dev, &pdev->dev);
5228
5229         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5230         rc = pci_enable_device(pdev);
5231         if (rc) {
5232                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5233                 goto init_err;
5234         }
5235
5236         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5237                 dev_err(&pdev->dev,
5238                         "Cannot find PCI device base address, aborting\n");
5239                 rc = -ENODEV;
5240                 goto init_err_disable;
5241         }
5242
5243         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5244         if (rc) {
5245                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5246                 goto init_err_disable;
5247         }
5248
5249         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5250             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5251                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5252                 goto init_err_disable;
5253         }
5254
5255         pci_set_master(pdev);
5256
5257         bp->dev = dev;
5258         bp->pdev = pdev;
5259
5260         bp->bar0 = pci_ioremap_bar(pdev, 0);
5261         if (!bp->bar0) {
5262                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5263                 rc = -ENOMEM;
5264                 goto init_err_release;
5265         }
5266
5267         bp->bar1 = pci_ioremap_bar(pdev, 2);
5268         if (!bp->bar1) {
5269                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5270                 rc = -ENOMEM;
5271                 goto init_err_release;
5272         }
5273
5274         bp->bar2 = pci_ioremap_bar(pdev, 4);
5275         if (!bp->bar2) {
5276                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5277                 rc = -ENOMEM;
5278                 goto init_err_release;
5279         }
5280
5281         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5282
5283         spin_lock_init(&bp->ntp_fltr_lock);
5284
5285         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5286         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5287
5288         bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5289         bp->coal_bufs = 20;
5290         bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5291         bp->coal_bufs_irq = 2;
5292
5293         init_timer(&bp->timer);
5294         bp->timer.data = (unsigned long)bp;
5295         bp->timer.function = bnxt_timer;
5296         bp->current_interval = BNXT_TIMER_INTERVAL;
5297
5298         clear_bit(BNXT_STATE_OPEN, &bp->state);
5299
5300         return 0;
5301
5302 init_err_release:
5303         if (bp->bar2) {
5304                 pci_iounmap(pdev, bp->bar2);
5305                 bp->bar2 = NULL;
5306         }
5307
5308         if (bp->bar1) {
5309                 pci_iounmap(pdev, bp->bar1);
5310                 bp->bar1 = NULL;
5311         }
5312
5313         if (bp->bar0) {
5314                 pci_iounmap(pdev, bp->bar0);
5315                 bp->bar0 = NULL;
5316         }
5317
5318         pci_release_regions(pdev);
5319
5320 init_err_disable:
5321         pci_disable_device(pdev);
5322
5323 init_err:
5324         return rc;
5325 }
5326
5327 /* rtnl_lock held */
5328 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5329 {
5330         struct sockaddr *addr = p;
5331         struct bnxt *bp = netdev_priv(dev);
5332         int rc = 0;
5333
5334         if (!is_valid_ether_addr(addr->sa_data))
5335                 return -EADDRNOTAVAIL;
5336
5337 #ifdef CONFIG_BNXT_SRIOV
5338         if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5339                 return -EADDRNOTAVAIL;
5340 #endif
5341
5342         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5343                 return 0;
5344
5345         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5346         if (netif_running(dev)) {
5347                 bnxt_close_nic(bp, false, false);
5348                 rc = bnxt_open_nic(bp, false, false);
5349         }
5350
5351         return rc;
5352 }
5353
5354 /* rtnl_lock held */
5355 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5356 {
5357         struct bnxt *bp = netdev_priv(dev);
5358
5359         if (new_mtu < 60 || new_mtu > 9000)
5360                 return -EINVAL;
5361
5362         if (netif_running(dev))
5363                 bnxt_close_nic(bp, false, false);
5364
5365         dev->mtu = new_mtu;
5366         bnxt_set_ring_params(bp);
5367
5368         if (netif_running(dev))
5369                 return bnxt_open_nic(bp, false, false);
5370
5371         return 0;
5372 }
5373
5374 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5375 {
5376         struct bnxt *bp = netdev_priv(dev);
5377
5378         if (tc > bp->max_tc) {
5379                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5380                            tc, bp->max_tc);
5381                 return -EINVAL;
5382         }
5383
5384         if (netdev_get_num_tc(dev) == tc)
5385                 return 0;
5386
5387         if (tc) {
5388                 int max_rx_rings, max_tx_rings, rc;
5389                 bool sh = false;
5390
5391                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5392                         sh = true;
5393
5394                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5395                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5396                         return -ENOMEM;
5397         }
5398
5399         /* Needs to close the device and do hw resource re-allocations */
5400         if (netif_running(bp->dev))
5401                 bnxt_close_nic(bp, true, false);
5402
5403         if (tc) {
5404                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5405                 netdev_set_num_tc(dev, tc);
5406         } else {
5407                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5408                 netdev_reset_tc(dev);
5409         }
5410         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5411         bp->num_stat_ctxs = bp->cp_nr_rings;
5412
5413         if (netif_running(bp->dev))
5414                 return bnxt_open_nic(bp, true, false);
5415
5416         return 0;
5417 }
5418
5419 #ifdef CONFIG_RFS_ACCEL
5420 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5421                             struct bnxt_ntuple_filter *f2)
5422 {
5423         struct flow_keys *keys1 = &f1->fkeys;
5424         struct flow_keys *keys2 = &f2->fkeys;
5425
5426         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5427             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5428             keys1->ports.ports == keys2->ports.ports &&
5429             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5430             keys1->basic.n_proto == keys2->basic.n_proto &&
5431             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5432                 return true;
5433
5434         return false;
5435 }
5436
5437 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5438                               u16 rxq_index, u32 flow_id)
5439 {
5440         struct bnxt *bp = netdev_priv(dev);
5441         struct bnxt_ntuple_filter *fltr, *new_fltr;
5442         struct flow_keys *fkeys;
5443         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5444         int rc = 0, idx, bit_id;
5445         struct hlist_head *head;
5446
5447         if (skb->encapsulation)
5448                 return -EPROTONOSUPPORT;
5449
5450         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5451         if (!new_fltr)
5452                 return -ENOMEM;
5453
5454         fkeys = &new_fltr->fkeys;
5455         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5456                 rc = -EPROTONOSUPPORT;
5457                 goto err_free;
5458         }
5459
5460         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5461             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5462              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5463                 rc = -EPROTONOSUPPORT;
5464                 goto err_free;
5465         }
5466
5467         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5468
5469         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5470         head = &bp->ntp_fltr_hash_tbl[idx];
5471         rcu_read_lock();
5472         hlist_for_each_entry_rcu(fltr, head, hash) {
5473                 if (bnxt_fltr_match(fltr, new_fltr)) {
5474                         rcu_read_unlock();
5475                         rc = 0;
5476                         goto err_free;
5477                 }
5478         }
5479         rcu_read_unlock();
5480
5481         spin_lock_bh(&bp->ntp_fltr_lock);
5482         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5483                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
5484         if (bit_id < 0) {
5485                 spin_unlock_bh(&bp->ntp_fltr_lock);
5486                 rc = -ENOMEM;
5487                 goto err_free;
5488         }
5489
5490         new_fltr->sw_id = (u16)bit_id;
5491         new_fltr->flow_id = flow_id;
5492         new_fltr->rxq = rxq_index;
5493         hlist_add_head_rcu(&new_fltr->hash, head);
5494         bp->ntp_fltr_count++;
5495         spin_unlock_bh(&bp->ntp_fltr_lock);
5496
5497         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5498         schedule_work(&bp->sp_task);
5499
5500         return new_fltr->sw_id;
5501
5502 err_free:
5503         kfree(new_fltr);
5504         return rc;
5505 }
5506
5507 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5508 {
5509         int i;
5510
5511         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5512                 struct hlist_head *head;
5513                 struct hlist_node *tmp;
5514                 struct bnxt_ntuple_filter *fltr;
5515                 int rc;
5516
5517                 head = &bp->ntp_fltr_hash_tbl[i];
5518                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5519                         bool del = false;
5520
5521                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5522                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5523                                                         fltr->flow_id,
5524                                                         fltr->sw_id)) {
5525                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
5526                                                                          fltr);
5527                                         del = true;
5528                                 }
5529                         } else {
5530                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5531                                                                        fltr);
5532                                 if (rc)
5533                                         del = true;
5534                                 else
5535                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
5536                         }
5537
5538                         if (del) {
5539                                 spin_lock_bh(&bp->ntp_fltr_lock);
5540                                 hlist_del_rcu(&fltr->hash);
5541                                 bp->ntp_fltr_count--;
5542                                 spin_unlock_bh(&bp->ntp_fltr_lock);
5543                                 synchronize_rcu();
5544                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5545                                 kfree(fltr);
5546                         }
5547                 }
5548         }
5549 }
5550
5551 #else
5552
5553 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5554 {
5555 }
5556
5557 #endif /* CONFIG_RFS_ACCEL */
5558
5559 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5560                                 __be16 port)
5561 {
5562         struct bnxt *bp = netdev_priv(dev);
5563
5564         if (!netif_running(dev))
5565                 return;
5566
5567         if (sa_family != AF_INET6 && sa_family != AF_INET)
5568                 return;
5569
5570         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5571                 return;
5572
5573         bp->vxlan_port_cnt++;
5574         if (bp->vxlan_port_cnt == 1) {
5575                 bp->vxlan_port = port;
5576                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5577                 schedule_work(&bp->sp_task);
5578         }
5579 }
5580
5581 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5582                                 __be16 port)
5583 {
5584         struct bnxt *bp = netdev_priv(dev);
5585
5586         if (!netif_running(dev))
5587                 return;
5588
5589         if (sa_family != AF_INET6 && sa_family != AF_INET)
5590                 return;
5591
5592         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5593                 bp->vxlan_port_cnt--;
5594
5595                 if (bp->vxlan_port_cnt == 0) {
5596                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5597                         schedule_work(&bp->sp_task);
5598                 }
5599         }
5600 }
5601
5602 static const struct net_device_ops bnxt_netdev_ops = {
5603         .ndo_open               = bnxt_open,
5604         .ndo_start_xmit         = bnxt_start_xmit,
5605         .ndo_stop               = bnxt_close,
5606         .ndo_get_stats64        = bnxt_get_stats64,
5607         .ndo_set_rx_mode        = bnxt_set_rx_mode,
5608         .ndo_do_ioctl           = bnxt_ioctl,
5609         .ndo_validate_addr      = eth_validate_addr,
5610         .ndo_set_mac_address    = bnxt_change_mac_addr,
5611         .ndo_change_mtu         = bnxt_change_mtu,
5612         .ndo_fix_features       = bnxt_fix_features,
5613         .ndo_set_features       = bnxt_set_features,
5614         .ndo_tx_timeout         = bnxt_tx_timeout,
5615 #ifdef CONFIG_BNXT_SRIOV
5616         .ndo_get_vf_config      = bnxt_get_vf_config,
5617         .ndo_set_vf_mac         = bnxt_set_vf_mac,
5618         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
5619         .ndo_set_vf_rate        = bnxt_set_vf_bw,
5620         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
5621         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
5622 #endif
5623 #ifdef CONFIG_NET_POLL_CONTROLLER
5624         .ndo_poll_controller    = bnxt_poll_controller,
5625 #endif
5626         .ndo_setup_tc           = bnxt_setup_tc,
5627 #ifdef CONFIG_RFS_ACCEL
5628         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
5629 #endif
5630         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
5631         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
5632 #ifdef CONFIG_NET_RX_BUSY_POLL
5633         .ndo_busy_poll          = bnxt_busy_poll,
5634 #endif
5635 };
5636
5637 static void bnxt_remove_one(struct pci_dev *pdev)
5638 {
5639         struct net_device *dev = pci_get_drvdata(pdev);
5640         struct bnxt *bp = netdev_priv(dev);
5641
5642         if (BNXT_PF(bp))
5643                 bnxt_sriov_disable(bp);
5644
5645         unregister_netdev(dev);
5646         cancel_work_sync(&bp->sp_task);
5647         bp->sp_event = 0;
5648
5649         bnxt_hwrm_func_drv_unrgtr(bp);
5650         bnxt_free_hwrm_resources(bp);
5651         pci_iounmap(pdev, bp->bar2);
5652         pci_iounmap(pdev, bp->bar1);
5653         pci_iounmap(pdev, bp->bar0);
5654         free_netdev(dev);
5655
5656         pci_release_regions(pdev);
5657         pci_disable_device(pdev);
5658 }
5659
5660 static int bnxt_probe_phy(struct bnxt *bp)
5661 {
5662         int rc = 0;
5663         struct bnxt_link_info *link_info = &bp->link_info;
5664         char phy_ver[PHY_VER_STR_LEN];
5665
5666         rc = bnxt_update_link(bp, false);
5667         if (rc) {
5668                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5669                            rc);
5670                 return rc;
5671         }
5672
5673         /*initialize the ethool setting copy with NVM settings */
5674         if (BNXT_AUTO_MODE(link_info->auto_mode))
5675                 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5676
5677         if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5678                 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5679                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5680                 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5681         } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5682                 link_info->req_flow_ctrl = link_info->force_pause_setting;
5683         }
5684         link_info->req_duplex = link_info->duplex_setting;
5685         if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5686                 link_info->req_link_speed = link_info->auto_link_speed;
5687         else
5688                 link_info->req_link_speed = link_info->force_link_speed;
5689         link_info->advertising = link_info->auto_link_speeds;
5690         snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5691                  link_info->phy_ver[0],
5692                  link_info->phy_ver[1],
5693                  link_info->phy_ver[2]);
5694         strcat(bp->fw_ver_str, phy_ver);
5695         return rc;
5696 }
5697
5698 static int bnxt_get_max_irq(struct pci_dev *pdev)
5699 {
5700         u16 ctrl;
5701
5702         if (!pdev->msix_cap)
5703                 return 1;
5704
5705         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5706         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5707 }
5708
5709 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5710                                 int *max_cp)
5711 {
5712         int max_ring_grps = 0;
5713
5714 #ifdef CONFIG_BNXT_SRIOV
5715         if (!BNXT_PF(bp)) {
5716                 *max_tx = bp->vf.max_tx_rings;
5717                 *max_rx = bp->vf.max_rx_rings;
5718                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5719                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
5720                 max_ring_grps = bp->vf.max_hw_ring_grps;
5721         } else
5722 #endif
5723         {
5724                 *max_tx = bp->pf.max_tx_rings;
5725                 *max_rx = bp->pf.max_rx_rings;
5726                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5727                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5728                 max_ring_grps = bp->pf.max_hw_ring_grps;
5729         }
5730
5731         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5732                 *max_rx >>= 1;
5733         *max_rx = min_t(int, *max_rx, max_ring_grps);
5734 }
5735
5736 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5737 {
5738         int rx, tx, cp;
5739
5740         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5741         if (!rx || !tx || !cp)
5742                 return -ENOMEM;
5743
5744         *max_rx = rx;
5745         *max_tx = tx;
5746         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5747 }
5748
5749 static int bnxt_set_dflt_rings(struct bnxt *bp)
5750 {
5751         int dflt_rings, max_rx_rings, max_tx_rings, rc;
5752         bool sh = true;
5753
5754         if (sh)
5755                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5756         dflt_rings = netif_get_num_default_rss_queues();
5757         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5758         if (rc)
5759                 return rc;
5760         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5761         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5762         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5763         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5764                                bp->tx_nr_rings + bp->rx_nr_rings;
5765         bp->num_stat_ctxs = bp->cp_nr_rings;
5766         return rc;
5767 }
5768
5769 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5770 {
5771         static int version_printed;
5772         struct net_device *dev;
5773         struct bnxt *bp;
5774         int rc, max_irqs;
5775
5776         if (version_printed++ == 0)
5777                 pr_info("%s", version);
5778
5779         max_irqs = bnxt_get_max_irq(pdev);
5780         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5781         if (!dev)
5782                 return -ENOMEM;
5783
5784         bp = netdev_priv(dev);
5785
5786         if (bnxt_vf_pciid(ent->driver_data))
5787                 bp->flags |= BNXT_FLAG_VF;
5788
5789         if (pdev->msix_cap)
5790                 bp->flags |= BNXT_FLAG_MSIX_CAP;
5791
5792         rc = bnxt_init_board(pdev, dev);
5793         if (rc < 0)
5794                 goto init_err_free;
5795
5796         dev->netdev_ops = &bnxt_netdev_ops;
5797         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5798         dev->ethtool_ops = &bnxt_ethtool_ops;
5799
5800         pci_set_drvdata(pdev, dev);
5801
5802         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5803                            NETIF_F_TSO | NETIF_F_TSO6 |
5804                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5805                            NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5806                            NETIF_F_RXHASH |
5807                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5808
5809         dev->hw_enc_features =
5810                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5811                         NETIF_F_TSO | NETIF_F_TSO6 |
5812                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5813                         NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5814         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5815         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5816                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5817         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5818         dev->priv_flags |= IFF_UNICAST_FLT;
5819
5820 #ifdef CONFIG_BNXT_SRIOV
5821         init_waitqueue_head(&bp->sriov_cfg_wait);
5822 #endif
5823         rc = bnxt_alloc_hwrm_resources(bp);
5824         if (rc)
5825                 goto init_err;
5826
5827         mutex_init(&bp->hwrm_cmd_lock);
5828         bnxt_hwrm_ver_get(bp);
5829
5830         rc = bnxt_hwrm_func_drv_rgtr(bp);
5831         if (rc)
5832                 goto init_err;
5833
5834         /* Get the MAX capabilities for this function */
5835         rc = bnxt_hwrm_func_qcaps(bp);
5836         if (rc) {
5837                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5838                            rc);
5839                 rc = -1;
5840                 goto init_err;
5841         }
5842
5843         rc = bnxt_hwrm_queue_qportcfg(bp);
5844         if (rc) {
5845                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5846                            rc);
5847                 rc = -1;
5848                 goto init_err;
5849         }
5850
5851         bnxt_set_tpa_flags(bp);
5852         bnxt_set_ring_params(bp);
5853         if (BNXT_PF(bp))
5854                 bp->pf.max_irqs = max_irqs;
5855 #if defined(CONFIG_BNXT_SRIOV)
5856         else
5857                 bp->vf.max_irqs = max_irqs;
5858 #endif
5859         bnxt_set_dflt_rings(bp);
5860
5861         if (BNXT_PF(bp)) {
5862                 dev->hw_features |= NETIF_F_NTUPLE;
5863                 if (bnxt_rfs_capable(bp)) {
5864                         bp->flags |= BNXT_FLAG_RFS;
5865                         dev->features |= NETIF_F_NTUPLE;
5866                 }
5867         }
5868
5869         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5870                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5871
5872         rc = bnxt_probe_phy(bp);
5873         if (rc)
5874                 goto init_err;
5875
5876         rc = register_netdev(dev);
5877         if (rc)
5878                 goto init_err;
5879
5880         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5881                     board_info[ent->driver_data].name,
5882                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
5883
5884         return 0;
5885
5886 init_err:
5887         pci_iounmap(pdev, bp->bar0);
5888         pci_release_regions(pdev);
5889         pci_disable_device(pdev);
5890
5891 init_err_free:
5892         free_netdev(dev);
5893         return rc;
5894 }
5895
5896 static struct pci_driver bnxt_pci_driver = {
5897         .name           = DRV_MODULE_NAME,
5898         .id_table       = bnxt_pci_tbl,
5899         .probe          = bnxt_init_one,
5900         .remove         = bnxt_remove_one,
5901 #if defined(CONFIG_BNXT_SRIOV)
5902         .sriov_configure = bnxt_sriov_configure,
5903 #endif
5904 };
5905
5906 module_pci_driver(bnxt_pci_driver);