drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 92
  73
  74 enum board_idx {
  75         BCM57302,
  76         BCM57304,
  77         BCM57404,
  78         BCM57406,
  79         BCM57304_VF,
  80         BCM57404_VF,
  81 };
  82
  83 /* indexed by enum above */
  84 static const struct {
  85         char *name;
  86 } board_info[] = {
  87         { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  88         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  89         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  90         { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" },
  91         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
  92         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
  93 };
  94
  95 static const struct pci_device_id bnxt_pci_tbl[] = {
  96         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
  97         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
  98         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
  99         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 100 #ifdef CONFIG_BNXT_SRIOV
 101         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 102         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 103 #endif
 104         { 0 }
 105 };
 106
 107 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 108
 109 static const u16 bnxt_vf_req_snif[] = {
 110         HWRM_FUNC_CFG,
 111         HWRM_PORT_PHY_QCFG,
 112         HWRM_CFA_L2_FILTER_ALLOC,
 113 };
 114
 115 static bool bnxt_vf_pciid(enum board_idx idx)
 116 {
 117         return (idx == BCM57304_VF || idx == BCM57404_VF);
 118 }
 119
 120 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 121 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 122 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 123
 124 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 125                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 126
 127 #define BNXT_CP_DB(db, raw_cons)                                        \
 128                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 129
 130 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 131                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 132
 133 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 134 {
 135         /* Tell compiler to fetch tx indices from memory. */
 136         barrier();
 137
 138         return bp->tx_ring_size -
 139                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 140 }
 141
 142 static const u16 bnxt_lhint_arr[] = {
 143         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 144         TX_BD_FLAGS_LHINT_512_TO_1023,
 145         TX_BD_FLAGS_LHINT_1024_TO_2047,
 146         TX_BD_FLAGS_LHINT_1024_TO_2047,
 147         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 148         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 149         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 150         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 151         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 152         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 153         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 154         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 155         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 156         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 157         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 158         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 159         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 160         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 161         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 162 };
 163
 164 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 165 {
 166         struct bnxt *bp = netdev_priv(dev);
 167         struct tx_bd *txbd;
 168         struct tx_bd_ext *txbd1;
 169         struct netdev_queue *txq;
 170         int i;
 171         dma_addr_t mapping;
 172         unsigned int length, pad = 0;
 173         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 174         u16 prod, last_frag;
 175         struct pci_dev *pdev = bp->pdev;
 176         struct bnxt_napi *bnapi;
 177         struct bnxt_tx_ring_info *txr;
 178         struct bnxt_sw_tx_bd *tx_buf;
 179
 180         i = skb_get_queue_mapping(skb);
 181         if (unlikely(i >= bp->tx_nr_rings)) {
 182                 dev_kfree_skb_any(skb);
 183                 return NETDEV_TX_OK;
 184         }
 185
 186         bnapi = bp->bnapi[i];
 187         txr = &bnapi->tx_ring;
 188         txq = netdev_get_tx_queue(dev, i);
 189         prod = txr->tx_prod;
 190
 191         free_size = bnxt_tx_avail(bp, txr);
 192         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 193                 netif_tx_stop_queue(txq);
 194                 return NETDEV_TX_BUSY;
 195         }
 196
 197         length = skb->len;
 198         len = skb_headlen(skb);
 199         last_frag = skb_shinfo(skb)->nr_frags;
 200
 201         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 202
 203         txbd->tx_bd_opaque = prod;
 204
 205         tx_buf = &txr->tx_buf_ring[prod];
 206         tx_buf->skb = skb;
 207         tx_buf->nr_frags = last_frag;
 208
 209         vlan_tag_flags = 0;
 210         cfa_action = 0;
 211         if (skb_vlan_tag_present(skb)) {
 212                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 213                                  skb_vlan_tag_get(skb);
 214                 /* Currently supports 8021Q, 8021AD vlan offloads
 215                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 216                  */
 217                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 218                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 219         }
 220
 221         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 222                 struct tx_push_bd *push = txr->tx_push;
 223                 struct tx_bd *tx_push = &push->txbd1;
 224                 struct tx_bd_ext *tx_push1 = &push->txbd2;
 225                 void *pdata = tx_push1 + 1;
 226                 int j;
 227
 228                 /* Set COAL_NOW to be ready quickly for the next push */
 229                 tx_push->tx_bd_len_flags_type =
 230                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 231                                         TX_BD_TYPE_LONG_TX_BD |
 232                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 233                                         TX_BD_FLAGS_COAL_NOW |
 234                                         TX_BD_FLAGS_PACKET_END |
 235                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 236
 237                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 238                         tx_push1->tx_bd_hsize_lflags =
 239                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 240                 else
 241                         tx_push1->tx_bd_hsize_lflags = 0;
 242
 243                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 244                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 245
 246                 skb_copy_from_linear_data(skb, pdata, len);
 247                 pdata += len;
 248                 for (j = 0; j < last_frag; j++) {
 249                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 250                         void *fptr;
 251
 252                         fptr = skb_frag_address_safe(frag);
 253                         if (!fptr)
 254                                 goto normal_tx;
 255
 256                         memcpy(pdata, fptr, skb_frag_size(frag));
 257                         pdata += skb_frag_size(frag);
 258                 }
 259
 260                 memcpy(txbd, tx_push, sizeof(*txbd));
 261                 prod = NEXT_TX(prod);
 262                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 263                 memcpy(txbd, tx_push1, sizeof(*txbd));
 264                 prod = NEXT_TX(prod);
 265                 push->doorbell =
 266                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 267                 txr->tx_prod = prod;
 268
 269                 netdev_tx_sent_queue(txq, skb->len);
 270
 271                 __iowrite64_copy(txr->tx_doorbell, push,
 272                                  (length + sizeof(*push) + 8) / 8);
 273
 274                 tx_buf->is_push = 1;
 275
 276                 goto tx_done;
 277         }
 278
 279 normal_tx:
 280         if (length < BNXT_MIN_PKT_SIZE) {
 281                 pad = BNXT_MIN_PKT_SIZE - length;
 282                 if (skb_pad(skb, pad)) {
 283                         /* SKB already freed. */
 284                         tx_buf->skb = NULL;
 285                         return NETDEV_TX_OK;
 286                 }
 287                 length = BNXT_MIN_PKT_SIZE;
 288         }
 289
 290         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 291
 292         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 293                 dev_kfree_skb_any(skb);
 294                 tx_buf->skb = NULL;
 295                 return NETDEV_TX_OK;
 296         }
 297
 298         dma_unmap_addr_set(tx_buf, mapping, mapping);
 299         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 300                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 301
 302         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 303
 304         prod = NEXT_TX(prod);
 305         txbd1 = (struct tx_bd_ext *)
 306                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 307
 308         txbd1->tx_bd_hsize_lflags = 0;
 309         if (skb_is_gso(skb)) {
 310                 u32 hdr_len;
 311
 312                 if (skb->encapsulation)
 313                         hdr_len = skb_inner_network_offset(skb) +
 314                                 skb_inner_network_header_len(skb) +
 315                                 inner_tcp_hdrlen(skb);
 316                 else
 317                         hdr_len = skb_transport_offset(skb) +
 318                                 tcp_hdrlen(skb);
 319
 320                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 321                                         TX_BD_FLAGS_T_IPID |
 322                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 323                 length = skb_shinfo(skb)->gso_size;
 324                 txbd1->tx_bd_mss = cpu_to_le32(length);
 325                 length += hdr_len;
 326         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 327                 txbd1->tx_bd_hsize_lflags =
 328                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 329                 txbd1->tx_bd_mss = 0;
 330         }
 331
 332         length >>= 9;
 333         flags |= bnxt_lhint_arr[length];
 334         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 335
 336         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 337         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 338         for (i = 0; i < last_frag; i++) {
 339                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 340
 341                 prod = NEXT_TX(prod);
 342                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 343
 344                 len = skb_frag_size(frag);
 345                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 346                                            DMA_TO_DEVICE);
 347
 348                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 349                         goto tx_dma_error;
 350
 351                 tx_buf = &txr->tx_buf_ring[prod];
 352                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 353
 354                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 355
 356                 flags = len << TX_BD_LEN_SHIFT;
 357                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 358         }
 359
 360         flags &= ~TX_BD_LEN;
 361         txbd->tx_bd_len_flags_type =
 362                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 363                             TX_BD_FLAGS_PACKET_END);
 364
 365         netdev_tx_sent_queue(txq, skb->len);
 366
 367         /* Sync BD data before updating doorbell */
 368         wmb();
 369
 370         prod = NEXT_TX(prod);
 371         txr->tx_prod = prod;
 372
 373         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 374         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 375
 376 tx_done:
 377
 378         mmiowb();
 379
 380         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 381                 netif_tx_stop_queue(txq);
 382
 383                 /* netif_tx_stop_queue() must be done before checking
 384                  * tx index in bnxt_tx_avail() below, because in
 385                  * bnxt_tx_int(), we update tx index before checking for
 386                  * netif_tx_queue_stopped().
 387                  */
 388                 smp_mb();
 389                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 390                         netif_tx_wake_queue(txq);
 391         }
 392         return NETDEV_TX_OK;
 393
 394 tx_dma_error:
 395         last_frag = i;
 396
 397         /* start back at beginning and unmap skb */
 398         prod = txr->tx_prod;
 399         tx_buf = &txr->tx_buf_ring[prod];
 400         tx_buf->skb = NULL;
 401         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 402                          skb_headlen(skb), PCI_DMA_TODEVICE);
 403         prod = NEXT_TX(prod);
 404
 405         /* unmap remaining mapped pages */
 406         for (i = 0; i < last_frag; i++) {
 407                 prod = NEXT_TX(prod);
 408                 tx_buf = &txr->tx_buf_ring[prod];
 409                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 410                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 411                                PCI_DMA_TODEVICE);
 412         }
 413
 414         dev_kfree_skb_any(skb);
 415         return NETDEV_TX_OK;
 416 }
 417
 418 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 419 {
 420         struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
 421         int index = bnapi->index;
 422         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 423         u16 cons = txr->tx_cons;
 424         struct pci_dev *pdev = bp->pdev;
 425         int i;
 426         unsigned int tx_bytes = 0;
 427
 428         for (i = 0; i < nr_pkts; i++) {
 429                 struct bnxt_sw_tx_bd *tx_buf;
 430                 struct sk_buff *skb;
 431                 int j, last;
 432
 433                 tx_buf = &txr->tx_buf_ring[cons];
 434                 cons = NEXT_TX(cons);
 435                 skb = tx_buf->skb;
 436                 tx_buf->skb = NULL;
 437
 438                 if (tx_buf->is_push) {
 439                         tx_buf->is_push = 0;
 440                         goto next_tx_int;
 441                 }
 442
 443                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 444                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 445                 last = tx_buf->nr_frags;
 446
 447                 for (j = 0; j < last; j++) {
 448                         cons = NEXT_TX(cons);
 449                         tx_buf = &txr->tx_buf_ring[cons];
 450                         dma_unmap_page(
 451                                 &pdev->dev,
 452                                 dma_unmap_addr(tx_buf, mapping),
 453                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 454                                 PCI_DMA_TODEVICE);
 455                 }
 456
 457 next_tx_int:
 458                 cons = NEXT_TX(cons);
 459
 460                 tx_bytes += skb->len;
 461                 dev_kfree_skb_any(skb);
 462         }
 463
 464         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 465         txr->tx_cons = cons;
 466
 467         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 468          * before checking for netif_tx_queue_stopped().  Without the
 469          * memory barrier, there is a small possibility that bnxt_start_xmit()
 470          * will miss it and cause the queue to be stopped forever.
 471          */
 472         smp_mb();
 473
 474         if (unlikely(netif_tx_queue_stopped(txq)) &&
 475             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 476                 __netif_tx_lock(txq, smp_processor_id());
 477                 if (netif_tx_queue_stopped(txq) &&
 478                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 479                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 480                         netif_tx_wake_queue(txq);
 481                 __netif_tx_unlock(txq);
 482         }
 483 }
 484
 485 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 486                                        gfp_t gfp)
 487 {
 488         u8 *data;
 489         struct pci_dev *pdev = bp->pdev;
 490
 491         data = kmalloc(bp->rx_buf_size, gfp);
 492         if (!data)
 493                 return NULL;
 494
 495         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 496                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 497
 498         if (dma_mapping_error(&pdev->dev, *mapping)) {
 499                 kfree(data);
 500                 data = NULL;
 501         }
 502         return data;
 503 }
 504
 505 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 506                                      struct bnxt_rx_ring_info *rxr,
 507                                      u16 prod, gfp_t gfp)
 508 {
 509         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 510         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 511         u8 *data;
 512         dma_addr_t mapping;
 513
 514         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 515         if (!data)
 516                 return -ENOMEM;
 517
 518         rx_buf->data = data;
 519         dma_unmap_addr_set(rx_buf, mapping, mapping);
 520
 521         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 522
 523         return 0;
 524 }
 525
 526 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 527                                u8 *data)
 528 {
 529         u16 prod = rxr->rx_prod;
 530         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 531         struct rx_bd *cons_bd, *prod_bd;
 532
 533         prod_rx_buf = &rxr->rx_buf_ring[prod];
 534         cons_rx_buf = &rxr->rx_buf_ring[cons];
 535
 536         prod_rx_buf->data = data;
 537
 538         dma_unmap_addr_set(prod_rx_buf, mapping,
 539                            dma_unmap_addr(cons_rx_buf, mapping));
 540
 541         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 542         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 543
 544         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 545 }
 546
 547 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 548 {
 549         u16 next, max = rxr->rx_agg_bmap_size;
 550
 551         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 552         if (next >= max)
 553                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 554         return next;
 555 }
 556
 557 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 558                                      struct bnxt_rx_ring_info *rxr,
 559                                      u16 prod, gfp_t gfp)
 560 {
 561         struct rx_bd *rxbd =
 562                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 563         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 564         struct pci_dev *pdev = bp->pdev;
 565         struct page *page;
 566         dma_addr_t mapping;
 567         u16 sw_prod = rxr->rx_sw_agg_prod;
 568
 569         page = alloc_page(gfp);
 570         if (!page)
 571                 return -ENOMEM;
 572
 573         mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
 574                                PCI_DMA_FROMDEVICE);
 575         if (dma_mapping_error(&pdev->dev, mapping)) {
 576                 __free_page(page);
 577                 return -EIO;
 578         }
 579
 580         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 581                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 582
 583         __set_bit(sw_prod, rxr->rx_agg_bmap);
 584         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 585         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 586
 587         rx_agg_buf->page = page;
 588         rx_agg_buf->mapping = mapping;
 589         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 590         rxbd->rx_bd_opaque = sw_prod;
 591         return 0;
 592 }
 593
 594 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 595                                    u32 agg_bufs)
 596 {
 597         struct bnxt *bp = bnapi->bp;
 598         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 599         struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
 600         u16 prod = rxr->rx_agg_prod;
 601         u16 sw_prod = rxr->rx_sw_agg_prod;
 602         u32 i;
 603
 604         for (i = 0; i < agg_bufs; i++) {
 605                 u16 cons;
 606                 struct rx_agg_cmp *agg;
 607                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 608                 struct rx_bd *prod_bd;
 609                 struct page *page;
 610
 611                 agg = (struct rx_agg_cmp *)
 612                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 613                 cons = agg->rx_agg_cmp_opaque;
 614                 __clear_bit(cons, rxr->rx_agg_bmap);
 615
 616                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 617                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 618
 619                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 620                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 621                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 622
 623                 /* It is possible for sw_prod to be equal to cons, so
 624                  * set cons_rx_buf->page to NULL first.
 625                  */
 626                 page = cons_rx_buf->page;
 627                 cons_rx_buf->page = NULL;
 628                 prod_rx_buf->page = page;
 629
 630                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 631
 632                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 633
 634                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 635                 prod_bd->rx_bd_opaque = sw_prod;
 636
 637                 prod = NEXT_RX_AGG(prod);
 638                 sw_prod = NEXT_RX_AGG(sw_prod);
 639                 cp_cons = NEXT_CMP(cp_cons);
 640         }
 641         rxr->rx_agg_prod = prod;
 642         rxr->rx_sw_agg_prod = sw_prod;
 643 }
 644
 645 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 646                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 647                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 648                                    unsigned int len)
 649 {
 650         int err;
 651         struct sk_buff *skb;
 652
 653         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 654         if (unlikely(err)) {
 655                 bnxt_reuse_rx_data(rxr, cons, data);
 656                 return NULL;
 657         }
 658
 659         skb = build_skb(data, 0);
 660         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 661                          PCI_DMA_FROMDEVICE);
 662         if (!skb) {
 663                 kfree(data);
 664                 return NULL;
 665         }
 666
 667         skb_reserve(skb, BNXT_RX_OFFSET);
 668         skb_put(skb, len);
 669         return skb;
 670 }
 671
 672 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 673                                      struct sk_buff *skb, u16 cp_cons,
 674                                      u32 agg_bufs)
 675 {
 676         struct pci_dev *pdev = bp->pdev;
 677         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 678         struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
 679         u16 prod = rxr->rx_agg_prod;
 680         u32 i;
 681
 682         for (i = 0; i < agg_bufs; i++) {
 683                 u16 cons, frag_len;
 684                 struct rx_agg_cmp *agg;
 685                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 686                 struct page *page;
 687                 dma_addr_t mapping;
 688
 689                 agg = (struct rx_agg_cmp *)
 690                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 691                 cons = agg->rx_agg_cmp_opaque;
 692                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 693                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 694
 695                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 696                 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
 697                 __clear_bit(cons, rxr->rx_agg_bmap);
 698
 699                 /* It is possible for bnxt_alloc_rx_page() to allocate
 700                  * a sw_prod index that equals the cons index, so we
 701                  * need to clear the cons entry now.
 702                  */
 703                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 704                 page = cons_rx_buf->page;
 705                 cons_rx_buf->page = NULL;
 706
 707                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 708                         struct skb_shared_info *shinfo;
 709                         unsigned int nr_frags;
 710
 711                         shinfo = skb_shinfo(skb);
 712                         nr_frags = --shinfo->nr_frags;
 713                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 714
 715                         dev_kfree_skb(skb);
 716
 717                         cons_rx_buf->page = page;
 718
 719                         /* Update prod since possibly some pages have been
 720                          * allocated already.
 721                          */
 722                         rxr->rx_agg_prod = prod;
 723                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 724                         return NULL;
 725                 }
 726
 727                 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
 728                                PCI_DMA_FROMDEVICE);
 729
 730                 skb->data_len += frag_len;
 731                 skb->len += frag_len;
 732                 skb->truesize += PAGE_SIZE;
 733
 734                 prod = NEXT_RX_AGG(prod);
 735                 cp_cons = NEXT_CMP(cp_cons);
 736         }
 737         rxr->rx_agg_prod = prod;
 738         return skb;
 739 }
 740
 741 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 742                                u8 agg_bufs, u32 *raw_cons)
 743 {
 744         u16 last;
 745         struct rx_agg_cmp *agg;
 746
 747         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 748         last = RING_CMP(*raw_cons);
 749         agg = (struct rx_agg_cmp *)
 750                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 751         return RX_AGG_CMP_VALID(agg, *raw_cons);
 752 }
 753
 754 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 755                                             unsigned int len,
 756                                             dma_addr_t mapping)
 757 {
 758         struct bnxt *bp = bnapi->bp;
 759         struct pci_dev *pdev = bp->pdev;
 760         struct sk_buff *skb;
 761
 762         skb = napi_alloc_skb(&bnapi->napi, len);
 763         if (!skb)
 764                 return NULL;
 765
 766         dma_sync_single_for_cpu(&pdev->dev, mapping,
 767                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 768
 769         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 770
 771         dma_sync_single_for_device(&pdev->dev, mapping,
 772                                    bp->rx_copy_thresh,
 773                                    PCI_DMA_FROMDEVICE);
 774
 775         skb_put(skb, len);
 776         return skb;
 777 }
 778
 779 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 780                            struct rx_tpa_start_cmp *tpa_start,
 781                            struct rx_tpa_start_cmp_ext *tpa_start1)
 782 {
 783         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 784         u16 cons, prod;
 785         struct bnxt_tpa_info *tpa_info;
 786         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 787         struct rx_bd *prod_bd;
 788         dma_addr_t mapping;
 789
 790         cons = tpa_start->rx_tpa_start_cmp_opaque;
 791         prod = rxr->rx_prod;
 792         cons_rx_buf = &rxr->rx_buf_ring[cons];
 793         prod_rx_buf = &rxr->rx_buf_ring[prod];
 794         tpa_info = &rxr->rx_tpa[agg_id];
 795
 796         prod_rx_buf->data = tpa_info->data;
 797
 798         mapping = tpa_info->mapping;
 799         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 800
 801         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 802
 803         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 804
 805         tpa_info->data = cons_rx_buf->data;
 806         cons_rx_buf->data = NULL;
 807         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 808
 809         tpa_info->len =
 810                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 811                                 RX_TPA_START_CMP_LEN_SHIFT;
 812         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 813                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 814
 815                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 816                 tpa_info->gso_type = SKB_GSO_TCPV4;
 817                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 818                 if (hash_type == 3)
 819                         tpa_info->gso_type = SKB_GSO_TCPV6;
 820                 tpa_info->rss_hash =
 821                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 822         } else {
 823                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 824                 tpa_info->gso_type = 0;
 825                 if (netif_msg_rx_err(bp))
 826                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 827         }
 828         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 829         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 830
 831         rxr->rx_prod = NEXT_RX(prod);
 832         cons = NEXT_RX(cons);
 833         cons_rx_buf = &rxr->rx_buf_ring[cons];
 834
 835         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 836         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 837         cons_rx_buf->data = NULL;
 838 }
 839
 840 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 841                            u16 cp_cons, u32 agg_bufs)
 842 {
 843         if (agg_bufs)
 844                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 845 }
 846
 847 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 848 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 849
 850 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 851                                            struct rx_tpa_end_cmp *tpa_end,
 852                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 853                                            struct sk_buff *skb)
 854 {
 855 #ifdef CONFIG_INET
 856         struct tcphdr *th;
 857         int payload_off, tcp_opt_len = 0;
 858         int len, nw_off;
 859
 860         NAPI_GRO_CB(skb)->count = TPA_END_TPA_SEGS(tpa_end);
 861         skb_shinfo(skb)->gso_size =
 862                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 863         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 864         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 865                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 866                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 867         if (TPA_END_GRO_TS(tpa_end))
 868                 tcp_opt_len = 12;
 869
 870         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 871                 struct iphdr *iph;
 872
 873                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 874                          ETH_HLEN;
 875                 skb_set_network_header(skb, nw_off);
 876                 iph = ip_hdr(skb);
 877                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 878                 len = skb->len - skb_transport_offset(skb);
 879                 th = tcp_hdr(skb);
 880                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 881         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 882                 struct ipv6hdr *iph;
 883
 884                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 885                          ETH_HLEN;
 886                 skb_set_network_header(skb, nw_off);
 887                 iph = ipv6_hdr(skb);
 888                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 889                 len = skb->len - skb_transport_offset(skb);
 890                 th = tcp_hdr(skb);
 891                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 892         } else {
 893                 dev_kfree_skb_any(skb);
 894                 return NULL;
 895         }
 896         tcp_gro_complete(skb);
 897
 898         if (nw_off) { /* tunnel */
 899                 struct udphdr *uh = NULL;
 900
 901                 if (skb->protocol == htons(ETH_P_IP)) {
 902                         struct iphdr *iph = (struct iphdr *)skb->data;
 903
 904                         if (iph->protocol == IPPROTO_UDP)
 905                                 uh = (struct udphdr *)(iph + 1);
 906                 } else {
 907                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
 908
 909                         if (iph->nexthdr == IPPROTO_UDP)
 910                                 uh = (struct udphdr *)(iph + 1);
 911                 }
 912                 if (uh) {
 913                         if (uh->check)
 914                                 skb_shinfo(skb)->gso_type |=
 915                                         SKB_GSO_UDP_TUNNEL_CSUM;
 916                         else
 917                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
 918                 }
 919         }
 920 #endif
 921         return skb;
 922 }
 923
 924 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
 925                                            struct bnxt_napi *bnapi,
 926                                            u32 *raw_cons,
 927                                            struct rx_tpa_end_cmp *tpa_end,
 928                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 929                                            bool *agg_event)
 930 {
 931         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 932         struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
 933         u8 agg_id = TPA_END_AGG_ID(tpa_end);
 934         u8 *data, agg_bufs;
 935         u16 cp_cons = RING_CMP(*raw_cons);
 936         unsigned int len;
 937         struct bnxt_tpa_info *tpa_info;
 938         dma_addr_t mapping;
 939         struct sk_buff *skb;
 940
 941         tpa_info = &rxr->rx_tpa[agg_id];
 942         data = tpa_info->data;
 943         prefetch(data);
 944         len = tpa_info->len;
 945         mapping = tpa_info->mapping;
 946
 947         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 948                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 949
 950         if (agg_bufs) {
 951                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
 952                         return ERR_PTR(-EBUSY);
 953
 954                 *agg_event = true;
 955                 cp_cons = NEXT_CMP(cp_cons);
 956         }
 957
 958         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
 959                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 960                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
 961                             agg_bufs, (int)MAX_SKB_FRAGS);
 962                 return NULL;
 963         }
 964
 965         if (len <= bp->rx_copy_thresh) {
 966                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
 967                 if (!skb) {
 968                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 969                         return NULL;
 970                 }
 971         } else {
 972                 u8 *new_data;
 973                 dma_addr_t new_mapping;
 974
 975                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
 976                 if (!new_data) {
 977                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 978                         return NULL;
 979                 }
 980
 981                 tpa_info->data = new_data;
 982                 tpa_info->mapping = new_mapping;
 983
 984                 skb = build_skb(data, 0);
 985                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
 986                                  PCI_DMA_FROMDEVICE);
 987
 988                 if (!skb) {
 989                         kfree(data);
 990                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 991                         return NULL;
 992                 }
 993                 skb_reserve(skb, BNXT_RX_OFFSET);
 994                 skb_put(skb, len);
 995         }
 996
 997         if (agg_bufs) {
 998                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
 999                 if (!skb) {
1000                         /* Page reuse already handled by bnxt_rx_pages(). */
1001                         return NULL;
1002                 }
1003         }
1004         skb->protocol = eth_type_trans(skb, bp->dev);
1005
1006         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1007                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1008
1009         if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1010                 netdev_features_t features = skb->dev->features;
1011                 u16 vlan_proto = tpa_info->metadata >>
1012                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1013
1014                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1015                      vlan_proto == ETH_P_8021Q) ||
1016                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1017                      vlan_proto == ETH_P_8021AD)) {
1018                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1019                                                tpa_info->metadata &
1020                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1021                 }
1022         }
1023
1024         skb_checksum_none_assert(skb);
1025         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1026                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1027                 skb->csum_level =
1028                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1029         }
1030
1031         if (TPA_END_GRO(tpa_end))
1032                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1033
1034         return skb;
1035 }
1036
1037 /* returns the following:
1038  * 1       - 1 packet successfully received
1039  * 0       - successful TPA_START, packet not completed yet
1040  * -EBUSY  - completion ring does not have all the agg buffers yet
1041  * -ENOMEM - packet aborted due to out of memory
1042  * -EIO    - packet aborted due to hw error indicated in BD
1043  */
1044 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1045                        bool *agg_event)
1046 {
1047         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1048         struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1049         struct net_device *dev = bp->dev;
1050         struct rx_cmp *rxcmp;
1051         struct rx_cmp_ext *rxcmp1;
1052         u32 tmp_raw_cons = *raw_cons;
1053         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1054         struct bnxt_sw_rx_bd *rx_buf;
1055         unsigned int len;
1056         u8 *data, agg_bufs, cmp_type;
1057         dma_addr_t dma_addr;
1058         struct sk_buff *skb;
1059         int rc = 0;
1060
1061         rxcmp = (struct rx_cmp *)
1062                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1063
1064         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1065         cp_cons = RING_CMP(tmp_raw_cons);
1066         rxcmp1 = (struct rx_cmp_ext *)
1067                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1068
1069         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1070                 return -EBUSY;
1071
1072         cmp_type = RX_CMP_TYPE(rxcmp);
1073
1074         prod = rxr->rx_prod;
1075
1076         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1077                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1078                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1079
1080                 goto next_rx_no_prod;
1081
1082         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1083                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1084                                    (struct rx_tpa_end_cmp *)rxcmp,
1085                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1086                                    agg_event);
1087
1088                 if (unlikely(IS_ERR(skb)))
1089                         return -EBUSY;
1090
1091                 rc = -ENOMEM;
1092                 if (likely(skb)) {
1093                         skb_record_rx_queue(skb, bnapi->index);
1094                         skb_mark_napi_id(skb, &bnapi->napi);
1095                         if (bnxt_busy_polling(bnapi))
1096                                 netif_receive_skb(skb);
1097                         else
1098                                 napi_gro_receive(&bnapi->napi, skb);
1099                         rc = 1;
1100                 }
1101                 goto next_rx_no_prod;
1102         }
1103
1104         cons = rxcmp->rx_cmp_opaque;
1105         rx_buf = &rxr->rx_buf_ring[cons];
1106         data = rx_buf->data;
1107         prefetch(data);
1108
1109         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1110                                 RX_CMP_AGG_BUFS_SHIFT;
1111
1112         if (agg_bufs) {
1113                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1114                         return -EBUSY;
1115
1116                 cp_cons = NEXT_CMP(cp_cons);
1117                 *agg_event = true;
1118         }
1119
1120         rx_buf->data = NULL;
1121         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1122                 bnxt_reuse_rx_data(rxr, cons, data);
1123                 if (agg_bufs)
1124                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1125
1126                 rc = -EIO;
1127                 goto next_rx;
1128         }
1129
1130         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1131         dma_addr = dma_unmap_addr(rx_buf, mapping);
1132
1133         if (len <= bp->rx_copy_thresh) {
1134                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1135                 bnxt_reuse_rx_data(rxr, cons, data);
1136                 if (!skb) {
1137                         rc = -ENOMEM;
1138                         goto next_rx;
1139                 }
1140         } else {
1141                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1142                 if (!skb) {
1143                         rc = -ENOMEM;
1144                         goto next_rx;
1145                 }
1146         }
1147
1148         if (agg_bufs) {
1149                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1150                 if (!skb) {
1151                         rc = -ENOMEM;
1152                         goto next_rx;
1153                 }
1154         }
1155
1156         if (RX_CMP_HASH_VALID(rxcmp)) {
1157                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1158                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1159
1160                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1161                 if (hash_type != 1 && hash_type != 3)
1162                         type = PKT_HASH_TYPE_L3;
1163                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1164         }
1165
1166         skb->protocol = eth_type_trans(skb, dev);
1167
1168         if (rxcmp1->rx_cmp_flags2 &
1169             cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1170                 netdev_features_t features = skb->dev->features;
1171                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1172                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1173
1174                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1175                      vlan_proto == ETH_P_8021Q) ||
1176                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1177                      vlan_proto == ETH_P_8021AD))
1178                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1179                                                meta_data &
1180                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1181         }
1182
1183         skb_checksum_none_assert(skb);
1184         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1185                 if (dev->features & NETIF_F_RXCSUM) {
1186                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1187                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1188                 }
1189         } else {
1190                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)
1191                         cpr->rx_l4_csum_errors++;
1192         }
1193
1194         skb_record_rx_queue(skb, bnapi->index);
1195         skb_mark_napi_id(skb, &bnapi->napi);
1196         if (bnxt_busy_polling(bnapi))
1197                 netif_receive_skb(skb);
1198         else
1199                 napi_gro_receive(&bnapi->napi, skb);
1200         rc = 1;
1201
1202 next_rx:
1203         rxr->rx_prod = NEXT_RX(prod);
1204
1205 next_rx_no_prod:
1206         *raw_cons = tmp_raw_cons;
1207
1208         return rc;
1209 }
1210
1211 static int bnxt_async_event_process(struct bnxt *bp,
1212                                     struct hwrm_async_event_cmpl *cmpl)
1213 {
1214         u16 event_id = le16_to_cpu(cmpl->event_id);
1215
1216         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1217         switch (event_id) {
1218         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1219                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1220                 schedule_work(&bp->sp_task);
1221                 break;
1222         default:
1223                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1224                            event_id);
1225                 break;
1226         }
1227         return 0;
1228 }
1229
1230 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1231 {
1232         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1233         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1234         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1235                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1236
1237         switch (cmpl_type) {
1238         case CMPL_BASE_TYPE_HWRM_DONE:
1239                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1240                 if (seq_id == bp->hwrm_intr_seq_id)
1241                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1242                 else
1243                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1244                 break;
1245
1246         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1247                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1248
1249                 if ((vf_id < bp->pf.first_vf_id) ||
1250                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1251                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1252                                    vf_id);
1253                         return -EINVAL;
1254                 }
1255
1256                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1257                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1258                 schedule_work(&bp->sp_task);
1259                 break;
1260
1261         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1262                 bnxt_async_event_process(bp,
1263                                          (struct hwrm_async_event_cmpl *)txcmp);
1264
1265         default:
1266                 break;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1273 {
1274         struct bnxt_napi *bnapi = dev_instance;
1275         struct bnxt *bp = bnapi->bp;
1276         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1277         u32 cons = RING_CMP(cpr->cp_raw_cons);
1278
1279         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1280         napi_schedule(&bnapi->napi);
1281         return IRQ_HANDLED;
1282 }
1283
1284 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1285 {
1286         u32 raw_cons = cpr->cp_raw_cons;
1287         u16 cons = RING_CMP(raw_cons);
1288         struct tx_cmp *txcmp;
1289
1290         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1291
1292         return TX_CMP_VALID(txcmp, raw_cons);
1293 }
1294
1295 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1296 {
1297         struct bnxt_napi *bnapi = dev_instance;
1298         struct bnxt *bp = bnapi->bp;
1299         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1300         u32 cons = RING_CMP(cpr->cp_raw_cons);
1301         u32 int_status;
1302
1303         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1304
1305         if (!bnxt_has_work(bp, cpr)) {
1306                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1307                 /* return if erroneous interrupt */
1308                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1309                         return IRQ_NONE;
1310         }
1311
1312         /* disable ring IRQ */
1313         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1314
1315         /* Return here if interrupt is shared and is disabled. */
1316         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1317                 return IRQ_HANDLED;
1318
1319         napi_schedule(&bnapi->napi);
1320         return IRQ_HANDLED;
1321 }
1322
1323 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1324 {
1325         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1326         u32 raw_cons = cpr->cp_raw_cons;
1327         u32 cons;
1328         int tx_pkts = 0;
1329         int rx_pkts = 0;
1330         bool rx_event = false;
1331         bool agg_event = false;
1332         struct tx_cmp *txcmp;
1333
1334         while (1) {
1335                 int rc;
1336
1337                 cons = RING_CMP(raw_cons);
1338                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1339
1340                 if (!TX_CMP_VALID(txcmp, raw_cons))
1341                         break;
1342
1343                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1344                         tx_pkts++;
1345                         /* return full budget so NAPI will complete. */
1346                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1347                                 rx_pkts = budget;
1348                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1349                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1350                         if (likely(rc >= 0))
1351                                 rx_pkts += rc;
1352                         else if (rc == -EBUSY)  /* partial completion */
1353                                 break;
1354                         rx_event = true;
1355                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1356                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1357                                     (TX_CMP_TYPE(txcmp) ==
1358                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1359                                     (TX_CMP_TYPE(txcmp) ==
1360                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1361                         bnxt_hwrm_handler(bp, txcmp);
1362                 }
1363                 raw_cons = NEXT_RAW_CMP(raw_cons);
1364
1365                 if (rx_pkts == budget)
1366                         break;
1367         }
1368
1369         cpr->cp_raw_cons = raw_cons;
1370         /* ACK completion ring before freeing tx ring and producing new
1371          * buffers in rx/agg rings to prevent overflowing the completion
1372          * ring.
1373          */
1374         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1375
1376         if (tx_pkts)
1377                 bnxt_tx_int(bp, bnapi, tx_pkts);
1378
1379         if (rx_event) {
1380                 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
1381
1382                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1383                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1384                 if (agg_event) {
1385                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1386                                rxr->rx_agg_doorbell);
1387                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1388                                rxr->rx_agg_doorbell);
1389                 }
1390         }
1391         return rx_pkts;
1392 }
1393
1394 static int bnxt_poll(struct napi_struct *napi, int budget)
1395 {
1396         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1397         struct bnxt *bp = bnapi->bp;
1398         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1399         int work_done = 0;
1400
1401         if (!bnxt_lock_napi(bnapi))
1402                 return budget;
1403
1404         while (1) {
1405                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1406
1407                 if (work_done >= budget)
1408                         break;
1409
1410                 if (!bnxt_has_work(bp, cpr)) {
1411                         napi_complete(napi);
1412                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1413                         break;
1414                 }
1415         }
1416         mmiowb();
1417         bnxt_unlock_napi(bnapi);
1418         return work_done;
1419 }
1420
1421 #ifdef CONFIG_NET_RX_BUSY_POLL
1422 static int bnxt_busy_poll(struct napi_struct *napi)
1423 {
1424         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1425         struct bnxt *bp = bnapi->bp;
1426         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1427         int rx_work, budget = 4;
1428
1429         if (atomic_read(&bp->intr_sem) != 0)
1430                 return LL_FLUSH_FAILED;
1431
1432         if (!bnxt_lock_poll(bnapi))
1433                 return LL_FLUSH_BUSY;
1434
1435         rx_work = bnxt_poll_work(bp, bnapi, budget);
1436
1437         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1438
1439         bnxt_unlock_poll(bnapi);
1440         return rx_work;
1441 }
1442 #endif
1443
1444 static void bnxt_free_tx_skbs(struct bnxt *bp)
1445 {
1446         int i, max_idx;
1447         struct pci_dev *pdev = bp->pdev;
1448
1449         if (!bp->bnapi)
1450                 return;
1451
1452         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1453         for (i = 0; i < bp->tx_nr_rings; i++) {
1454                 struct bnxt_napi *bnapi = bp->bnapi[i];
1455                 struct bnxt_tx_ring_info *txr;
1456                 int j;
1457
1458                 if (!bnapi)
1459                         continue;
1460
1461                 txr = &bnapi->tx_ring;
1462                 for (j = 0; j < max_idx;) {
1463                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1464                         struct sk_buff *skb = tx_buf->skb;
1465                         int k, last;
1466
1467                         if (!skb) {
1468                                 j++;
1469                                 continue;
1470                         }
1471
1472                         tx_buf->skb = NULL;
1473
1474                         if (tx_buf->is_push) {
1475                                 dev_kfree_skb(skb);
1476                                 j += 2;
1477                                 continue;
1478                         }
1479
1480                         dma_unmap_single(&pdev->dev,
1481                                          dma_unmap_addr(tx_buf, mapping),
1482                                          skb_headlen(skb),
1483                                          PCI_DMA_TODEVICE);
1484
1485                         last = tx_buf->nr_frags;
1486                         j += 2;
1487                         for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1488                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1489
1490                                 tx_buf = &txr->tx_buf_ring[j];
1491                                 dma_unmap_page(
1492                                         &pdev->dev,
1493                                         dma_unmap_addr(tx_buf, mapping),
1494                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1495                         }
1496                         dev_kfree_skb(skb);
1497                 }
1498                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1499         }
1500 }
1501
1502 static void bnxt_free_rx_skbs(struct bnxt *bp)
1503 {
1504         int i, max_idx, max_agg_idx;
1505         struct pci_dev *pdev = bp->pdev;
1506
1507         if (!bp->bnapi)
1508                 return;
1509
1510         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1511         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1512         for (i = 0; i < bp->rx_nr_rings; i++) {
1513                 struct bnxt_napi *bnapi = bp->bnapi[i];
1514                 struct bnxt_rx_ring_info *rxr;
1515                 int j;
1516
1517                 if (!bnapi)
1518                         continue;
1519
1520                 rxr = &bnapi->rx_ring;
1521
1522                 if (rxr->rx_tpa) {
1523                         for (j = 0; j < MAX_TPA; j++) {
1524                                 struct bnxt_tpa_info *tpa_info =
1525                                                         &rxr->rx_tpa[j];
1526                                 u8 *data = tpa_info->data;
1527
1528                                 if (!data)
1529                                         continue;
1530
1531                                 dma_unmap_single(
1532                                         &pdev->dev,
1533                                         dma_unmap_addr(tpa_info, mapping),
1534                                         bp->rx_buf_use_size,
1535                                         PCI_DMA_FROMDEVICE);
1536
1537                                 tpa_info->data = NULL;
1538
1539                                 kfree(data);
1540                         }
1541                 }
1542
1543                 for (j = 0; j < max_idx; j++) {
1544                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1545                         u8 *data = rx_buf->data;
1546
1547                         if (!data)
1548                                 continue;
1549
1550                         dma_unmap_single(&pdev->dev,
1551                                          dma_unmap_addr(rx_buf, mapping),
1552                                          bp->rx_buf_use_size,
1553                                          PCI_DMA_FROMDEVICE);
1554
1555                         rx_buf->data = NULL;
1556
1557                         kfree(data);
1558                 }
1559
1560                 for (j = 0; j < max_agg_idx; j++) {
1561                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1562                                 &rxr->rx_agg_ring[j];
1563                         struct page *page = rx_agg_buf->page;
1564
1565                         if (!page)
1566                                 continue;
1567
1568                         dma_unmap_page(&pdev->dev,
1569                                        dma_unmap_addr(rx_agg_buf, mapping),
1570                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
1571
1572                         rx_agg_buf->page = NULL;
1573                         __clear_bit(j, rxr->rx_agg_bmap);
1574
1575                         __free_page(page);
1576                 }
1577         }
1578 }
1579
1580 static void bnxt_free_skbs(struct bnxt *bp)
1581 {
1582         bnxt_free_tx_skbs(bp);
1583         bnxt_free_rx_skbs(bp);
1584 }
1585
1586 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1587 {
1588         struct pci_dev *pdev = bp->pdev;
1589         int i;
1590
1591         for (i = 0; i < ring->nr_pages; i++) {
1592                 if (!ring->pg_arr[i])
1593                         continue;
1594
1595                 dma_free_coherent(&pdev->dev, ring->page_size,
1596                                   ring->pg_arr[i], ring->dma_arr[i]);
1597
1598                 ring->pg_arr[i] = NULL;
1599         }
1600         if (ring->pg_tbl) {
1601                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1602                                   ring->pg_tbl, ring->pg_tbl_map);
1603                 ring->pg_tbl = NULL;
1604         }
1605         if (ring->vmem_size && *ring->vmem) {
1606                 vfree(*ring->vmem);
1607                 *ring->vmem = NULL;
1608         }
1609 }
1610
1611 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1612 {
1613         int i;
1614         struct pci_dev *pdev = bp->pdev;
1615
1616         if (ring->nr_pages > 1) {
1617                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1618                                                   ring->nr_pages * 8,
1619                                                   &ring->pg_tbl_map,
1620                                                   GFP_KERNEL);
1621                 if (!ring->pg_tbl)
1622                         return -ENOMEM;
1623         }
1624
1625         for (i = 0; i < ring->nr_pages; i++) {
1626                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1627                                                      ring->page_size,
1628                                                      &ring->dma_arr[i],
1629                                                      GFP_KERNEL);
1630                 if (!ring->pg_arr[i])
1631                         return -ENOMEM;
1632
1633                 if (ring->nr_pages > 1)
1634                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1635         }
1636
1637         if (ring->vmem_size) {
1638                 *ring->vmem = vzalloc(ring->vmem_size);
1639                 if (!(*ring->vmem))
1640                         return -ENOMEM;
1641         }
1642         return 0;
1643 }
1644
1645 static void bnxt_free_rx_rings(struct bnxt *bp)
1646 {
1647         int i;
1648
1649         if (!bp->bnapi)
1650                 return;
1651
1652         for (i = 0; i < bp->rx_nr_rings; i++) {
1653                 struct bnxt_napi *bnapi = bp->bnapi[i];
1654                 struct bnxt_rx_ring_info *rxr;
1655                 struct bnxt_ring_struct *ring;
1656
1657                 if (!bnapi)
1658                         continue;
1659
1660                 rxr = &bnapi->rx_ring;
1661
1662                 kfree(rxr->rx_tpa);
1663                 rxr->rx_tpa = NULL;
1664
1665                 kfree(rxr->rx_agg_bmap);
1666                 rxr->rx_agg_bmap = NULL;
1667
1668                 ring = &rxr->rx_ring_struct;
1669                 bnxt_free_ring(bp, ring);
1670
1671                 ring = &rxr->rx_agg_ring_struct;
1672                 bnxt_free_ring(bp, ring);
1673         }
1674 }
1675
1676 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1677 {
1678         int i, rc, agg_rings = 0, tpa_rings = 0;
1679
1680         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1681                 agg_rings = 1;
1682
1683         if (bp->flags & BNXT_FLAG_TPA)
1684                 tpa_rings = 1;
1685
1686         for (i = 0; i < bp->rx_nr_rings; i++) {
1687                 struct bnxt_napi *bnapi = bp->bnapi[i];
1688                 struct bnxt_rx_ring_info *rxr;
1689                 struct bnxt_ring_struct *ring;
1690
1691                 if (!bnapi)
1692                         continue;
1693
1694                 rxr = &bnapi->rx_ring;
1695                 ring = &rxr->rx_ring_struct;
1696
1697                 rc = bnxt_alloc_ring(bp, ring);
1698                 if (rc)
1699                         return rc;
1700
1701                 if (agg_rings) {
1702                         u16 mem_size;
1703
1704                         ring = &rxr->rx_agg_ring_struct;
1705                         rc = bnxt_alloc_ring(bp, ring);
1706                         if (rc)
1707                                 return rc;
1708
1709                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1710                         mem_size = rxr->rx_agg_bmap_size / 8;
1711                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1712                         if (!rxr->rx_agg_bmap)
1713                                 return -ENOMEM;
1714
1715                         if (tpa_rings) {
1716                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1717                                                 sizeof(struct bnxt_tpa_info),
1718                                                 GFP_KERNEL);
1719                                 if (!rxr->rx_tpa)
1720                                         return -ENOMEM;
1721                         }
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 static void bnxt_free_tx_rings(struct bnxt *bp)
1728 {
1729         int i;
1730         struct pci_dev *pdev = bp->pdev;
1731
1732         if (!bp->bnapi)
1733                 return;
1734
1735         for (i = 0; i < bp->tx_nr_rings; i++) {
1736                 struct bnxt_napi *bnapi = bp->bnapi[i];
1737                 struct bnxt_tx_ring_info *txr;
1738                 struct bnxt_ring_struct *ring;
1739
1740                 if (!bnapi)
1741                         continue;
1742
1743                 txr = &bnapi->tx_ring;
1744
1745                 if (txr->tx_push) {
1746                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1747                                           txr->tx_push, txr->tx_push_mapping);
1748                         txr->tx_push = NULL;
1749                 }
1750
1751                 ring = &txr->tx_ring_struct;
1752
1753                 bnxt_free_ring(bp, ring);
1754         }
1755 }
1756
1757 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1758 {
1759         int i, j, rc;
1760         struct pci_dev *pdev = bp->pdev;
1761
1762         bp->tx_push_size = 0;
1763         if (bp->tx_push_thresh) {
1764                 int push_size;
1765
1766                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1767                                         bp->tx_push_thresh);
1768
1769                 if (push_size > 128) {
1770                         push_size = 0;
1771                         bp->tx_push_thresh = 0;
1772                 }
1773
1774                 bp->tx_push_size = push_size;
1775         }
1776
1777         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1778                 struct bnxt_napi *bnapi = bp->bnapi[i];
1779                 struct bnxt_tx_ring_info *txr;
1780                 struct bnxt_ring_struct *ring;
1781
1782                 if (!bnapi)
1783                         continue;
1784
1785                 txr = &bnapi->tx_ring;
1786                 ring = &txr->tx_ring_struct;
1787
1788                 rc = bnxt_alloc_ring(bp, ring);
1789                 if (rc)
1790                         return rc;
1791
1792                 if (bp->tx_push_size) {
1793                         struct tx_bd *txbd;
1794                         dma_addr_t mapping;
1795
1796                         /* One pre-allocated DMA buffer to backup
1797                          * TX push operation
1798                          */
1799                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1800                                                 bp->tx_push_size,
1801                                                 &txr->tx_push_mapping,
1802                                                 GFP_KERNEL);
1803
1804                         if (!txr->tx_push)
1805                                 return -ENOMEM;
1806
1807                         txbd = &txr->tx_push->txbd1;
1808
1809                         mapping = txr->tx_push_mapping +
1810                                 sizeof(struct tx_push_bd);
1811                         txbd->tx_bd_haddr = cpu_to_le64(mapping);
1812
1813                         memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1814                 }
1815                 ring->queue_id = bp->q_info[j].queue_id;
1816                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1817                         j++;
1818         }
1819         return 0;
1820 }
1821
1822 static void bnxt_free_cp_rings(struct bnxt *bp)
1823 {
1824         int i;
1825
1826         if (!bp->bnapi)
1827                 return;
1828
1829         for (i = 0; i < bp->cp_nr_rings; i++) {
1830                 struct bnxt_napi *bnapi = bp->bnapi[i];
1831                 struct bnxt_cp_ring_info *cpr;
1832                 struct bnxt_ring_struct *ring;
1833
1834                 if (!bnapi)
1835                         continue;
1836
1837                 cpr = &bnapi->cp_ring;
1838                 ring = &cpr->cp_ring_struct;
1839
1840                 bnxt_free_ring(bp, ring);
1841         }
1842 }
1843
1844 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1845 {
1846         int i, rc;
1847
1848         for (i = 0; i < bp->cp_nr_rings; i++) {
1849                 struct bnxt_napi *bnapi = bp->bnapi[i];
1850                 struct bnxt_cp_ring_info *cpr;
1851                 struct bnxt_ring_struct *ring;
1852
1853                 if (!bnapi)
1854                         continue;
1855
1856                 cpr = &bnapi->cp_ring;
1857                 ring = &cpr->cp_ring_struct;
1858
1859                 rc = bnxt_alloc_ring(bp, ring);
1860                 if (rc)
1861                         return rc;
1862         }
1863         return 0;
1864 }
1865
1866 static void bnxt_init_ring_struct(struct bnxt *bp)
1867 {
1868         int i;
1869
1870         for (i = 0; i < bp->cp_nr_rings; i++) {
1871                 struct bnxt_napi *bnapi = bp->bnapi[i];
1872                 struct bnxt_cp_ring_info *cpr;
1873                 struct bnxt_rx_ring_info *rxr;
1874                 struct bnxt_tx_ring_info *txr;
1875                 struct bnxt_ring_struct *ring;
1876
1877                 if (!bnapi)
1878                         continue;
1879
1880                 cpr = &bnapi->cp_ring;
1881                 ring = &cpr->cp_ring_struct;
1882                 ring->nr_pages = bp->cp_nr_pages;
1883                 ring->page_size = HW_CMPD_RING_SIZE;
1884                 ring->pg_arr = (void **)cpr->cp_desc_ring;
1885                 ring->dma_arr = cpr->cp_desc_mapping;
1886                 ring->vmem_size = 0;
1887
1888                 rxr = &bnapi->rx_ring;
1889                 ring = &rxr->rx_ring_struct;
1890                 ring->nr_pages = bp->rx_nr_pages;
1891                 ring->page_size = HW_RXBD_RING_SIZE;
1892                 ring->pg_arr = (void **)rxr->rx_desc_ring;
1893                 ring->dma_arr = rxr->rx_desc_mapping;
1894                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1895                 ring->vmem = (void **)&rxr->rx_buf_ring;
1896
1897                 ring = &rxr->rx_agg_ring_struct;
1898                 ring->nr_pages = bp->rx_agg_nr_pages;
1899                 ring->page_size = HW_RXBD_RING_SIZE;
1900                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1901                 ring->dma_arr = rxr->rx_agg_desc_mapping;
1902                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1903                 ring->vmem = (void **)&rxr->rx_agg_ring;
1904
1905                 txr = &bnapi->tx_ring;
1906                 ring = &txr->tx_ring_struct;
1907                 ring->nr_pages = bp->tx_nr_pages;
1908                 ring->page_size = HW_RXBD_RING_SIZE;
1909                 ring->pg_arr = (void **)txr->tx_desc_ring;
1910                 ring->dma_arr = txr->tx_desc_mapping;
1911                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1912                 ring->vmem = (void **)&txr->tx_buf_ring;
1913         }
1914 }
1915
1916 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1917 {
1918         int i;
1919         u32 prod;
1920         struct rx_bd **rx_buf_ring;
1921
1922         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1923         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1924                 int j;
1925                 struct rx_bd *rxbd;
1926
1927                 rxbd = rx_buf_ring[i];
1928                 if (!rxbd)
1929                         continue;
1930
1931                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1932                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1933                         rxbd->rx_bd_opaque = prod;
1934                 }
1935         }
1936 }
1937
1938 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1939 {
1940         struct net_device *dev = bp->dev;
1941         struct bnxt_napi *bnapi = bp->bnapi[ring_nr];
1942         struct bnxt_rx_ring_info *rxr;
1943         struct bnxt_ring_struct *ring;
1944         u32 prod, type;
1945         int i;
1946
1947         if (!bnapi)
1948                 return -EINVAL;
1949
1950         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1951                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1952
1953         if (NET_IP_ALIGN == 2)
1954                 type |= RX_BD_FLAGS_SOP;
1955
1956         rxr = &bnapi->rx_ring;
1957         ring = &rxr->rx_ring_struct;
1958         bnxt_init_rxbd_pages(ring, type);
1959
1960         prod = rxr->rx_prod;
1961         for (i = 0; i < bp->rx_ring_size; i++) {
1962                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1963                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1964                                     ring_nr, i, bp->rx_ring_size);
1965                         break;
1966                 }
1967                 prod = NEXT_RX(prod);
1968         }
1969         rxr->rx_prod = prod;
1970         ring->fw_ring_id = INVALID_HW_RING_ID;
1971
1972         ring = &rxr->rx_agg_ring_struct;
1973         ring->fw_ring_id = INVALID_HW_RING_ID;
1974
1975         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1976                 return 0;
1977
1978         type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1979                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1980
1981         bnxt_init_rxbd_pages(ring, type);
1982
1983         prod = rxr->rx_agg_prod;
1984         for (i = 0; i < bp->rx_agg_ring_size; i++) {
1985                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1986                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1987                                     ring_nr, i, bp->rx_ring_size);
1988                         break;
1989                 }
1990                 prod = NEXT_RX_AGG(prod);
1991         }
1992         rxr->rx_agg_prod = prod;
1993
1994         if (bp->flags & BNXT_FLAG_TPA) {
1995                 if (rxr->rx_tpa) {
1996                         u8 *data;
1997                         dma_addr_t mapping;
1998
1999                         for (i = 0; i < MAX_TPA; i++) {
2000                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2001                                                             GFP_KERNEL);
2002                                 if (!data)
2003                                         return -ENOMEM;
2004
2005                                 rxr->rx_tpa[i].data = data;
2006                                 rxr->rx_tpa[i].mapping = mapping;
2007                         }
2008                 } else {
2009                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2010                         return -ENOMEM;
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int bnxt_init_rx_rings(struct bnxt *bp)
2018 {
2019         int i, rc = 0;
2020
2021         for (i = 0; i < bp->rx_nr_rings; i++) {
2022                 rc = bnxt_init_one_rx_ring(bp, i);
2023                 if (rc)
2024                         break;
2025         }
2026
2027         return rc;
2028 }
2029
2030 static int bnxt_init_tx_rings(struct bnxt *bp)
2031 {
2032         u16 i;
2033
2034         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2035                                    MAX_SKB_FRAGS + 1);
2036
2037         for (i = 0; i < bp->tx_nr_rings; i++) {
2038                 struct bnxt_napi *bnapi = bp->bnapi[i];
2039                 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
2040                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2041
2042                 ring->fw_ring_id = INVALID_HW_RING_ID;
2043         }
2044
2045         return 0;
2046 }
2047
2048 static void bnxt_free_ring_grps(struct bnxt *bp)
2049 {
2050         kfree(bp->grp_info);
2051         bp->grp_info = NULL;
2052 }
2053
2054 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2055 {
2056         int i;
2057
2058         if (irq_re_init) {
2059                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2060                                        sizeof(struct bnxt_ring_grp_info),
2061                                        GFP_KERNEL);
2062                 if (!bp->grp_info)
2063                         return -ENOMEM;
2064         }
2065         for (i = 0; i < bp->cp_nr_rings; i++) {
2066                 if (irq_re_init)
2067                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2068                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2069                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2070                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2071                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2072         }
2073         return 0;
2074 }
2075
2076 static void bnxt_free_vnics(struct bnxt *bp)
2077 {
2078         kfree(bp->vnic_info);
2079         bp->vnic_info = NULL;
2080         bp->nr_vnics = 0;
2081 }
2082
2083 static int bnxt_alloc_vnics(struct bnxt *bp)
2084 {
2085         int num_vnics = 1;
2086
2087 #ifdef CONFIG_RFS_ACCEL
2088         if (bp->flags & BNXT_FLAG_RFS)
2089                 num_vnics += bp->rx_nr_rings;
2090 #endif
2091
2092         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2093                                 GFP_KERNEL);
2094         if (!bp->vnic_info)
2095                 return -ENOMEM;
2096
2097         bp->nr_vnics = num_vnics;
2098         return 0;
2099 }
2100
2101 static void bnxt_init_vnics(struct bnxt *bp)
2102 {
2103         int i;
2104
2105         for (i = 0; i < bp->nr_vnics; i++) {
2106                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2107
2108                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2109                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2110                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2111
2112                 if (bp->vnic_info[i].rss_hash_key) {
2113                         if (i == 0)
2114                                 prandom_bytes(vnic->rss_hash_key,
2115                                               HW_HASH_KEY_SIZE);
2116                         else
2117                                 memcpy(vnic->rss_hash_key,
2118                                        bp->vnic_info[0].rss_hash_key,
2119                                        HW_HASH_KEY_SIZE);
2120                 }
2121         }
2122 }
2123
2124 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2125 {
2126         int pages;
2127
2128         pages = ring_size / desc_per_pg;
2129
2130         if (!pages)
2131                 return 1;
2132
2133         pages++;
2134
2135         while (pages & (pages - 1))
2136                 pages++;
2137
2138         return pages;
2139 }
2140
2141 static void bnxt_set_tpa_flags(struct bnxt *bp)
2142 {
2143         bp->flags &= ~BNXT_FLAG_TPA;
2144         if (bp->dev->features & NETIF_F_LRO)
2145                 bp->flags |= BNXT_FLAG_LRO;
2146         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2147                 bp->flags |= BNXT_FLAG_GRO;
2148 }
2149
2150 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2151  * be set on entry.
2152  */
2153 void bnxt_set_ring_params(struct bnxt *bp)
2154 {
2155         u32 ring_size, rx_size, rx_space;
2156         u32 agg_factor = 0, agg_ring_size = 0;
2157
2158         /* 8 for CRC and VLAN */
2159         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2160
2161         rx_space = rx_size + NET_SKB_PAD +
2162                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2163
2164         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2165         ring_size = bp->rx_ring_size;
2166         bp->rx_agg_ring_size = 0;
2167         bp->rx_agg_nr_pages = 0;
2168
2169         if (bp->flags & BNXT_FLAG_TPA)
2170                 agg_factor = 4;
2171
2172         bp->flags &= ~BNXT_FLAG_JUMBO;
2173         if (rx_space > PAGE_SIZE) {
2174                 u32 jumbo_factor;
2175
2176                 bp->flags |= BNXT_FLAG_JUMBO;
2177                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2178                 if (jumbo_factor > agg_factor)
2179                         agg_factor = jumbo_factor;
2180         }
2181         agg_ring_size = ring_size * agg_factor;
2182
2183         if (agg_ring_size) {
2184                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2185                                                         RX_DESC_CNT);
2186                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2187                         u32 tmp = agg_ring_size;
2188
2189                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2190                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2191                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2192                                     tmp, agg_ring_size);
2193                 }
2194                 bp->rx_agg_ring_size = agg_ring_size;
2195                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2196                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2197                 rx_space = rx_size + NET_SKB_PAD +
2198                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2199         }
2200
2201         bp->rx_buf_use_size = rx_size;
2202         bp->rx_buf_size = rx_space;
2203
2204         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2205         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2206
2207         ring_size = bp->tx_ring_size;
2208         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2209         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2210
2211         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2212         bp->cp_ring_size = ring_size;
2213
2214         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2215         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2216                 bp->cp_nr_pages = MAX_CP_PAGES;
2217                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2218                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2219                             ring_size, bp->cp_ring_size);
2220         }
2221         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2222         bp->cp_ring_mask = bp->cp_bit - 1;
2223 }
2224
2225 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2226 {
2227         int i;
2228         struct bnxt_vnic_info *vnic;
2229         struct pci_dev *pdev = bp->pdev;
2230
2231         if (!bp->vnic_info)
2232                 return;
2233
2234         for (i = 0; i < bp->nr_vnics; i++) {
2235                 vnic = &bp->vnic_info[i];
2236
2237                 kfree(vnic->fw_grp_ids);
2238                 vnic->fw_grp_ids = NULL;
2239
2240                 kfree(vnic->uc_list);
2241                 vnic->uc_list = NULL;
2242
2243                 if (vnic->mc_list) {
2244                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2245                                           vnic->mc_list, vnic->mc_list_mapping);
2246                         vnic->mc_list = NULL;
2247                 }
2248
2249                 if (vnic->rss_table) {
2250                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2251                                           vnic->rss_table,
2252                                           vnic->rss_table_dma_addr);
2253                         vnic->rss_table = NULL;
2254                 }
2255
2256                 vnic->rss_hash_key = NULL;
2257                 vnic->flags = 0;
2258         }
2259 }
2260
2261 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2262 {
2263         int i, rc = 0, size;
2264         struct bnxt_vnic_info *vnic;
2265         struct pci_dev *pdev = bp->pdev;
2266         int max_rings;
2267
2268         for (i = 0; i < bp->nr_vnics; i++) {
2269                 vnic = &bp->vnic_info[i];
2270
2271                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2272                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2273
2274                         if (mem_size > 0) {
2275                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2276                                 if (!vnic->uc_list) {
2277                                         rc = -ENOMEM;
2278                                         goto out;
2279                                 }
2280                         }
2281                 }
2282
2283                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2284                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2285                         vnic->mc_list =
2286                                 dma_alloc_coherent(&pdev->dev,
2287                                                    vnic->mc_list_size,
2288                                                    &vnic->mc_list_mapping,
2289                                                    GFP_KERNEL);
2290                         if (!vnic->mc_list) {
2291                                 rc = -ENOMEM;
2292                                 goto out;
2293                         }
2294                 }
2295
2296                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2297                         max_rings = bp->rx_nr_rings;
2298                 else
2299                         max_rings = 1;
2300
2301                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2302                 if (!vnic->fw_grp_ids) {
2303                         rc = -ENOMEM;
2304                         goto out;
2305                 }
2306
2307                 /* Allocate rss table and hash key */
2308                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2309                                                      &vnic->rss_table_dma_addr,
2310                                                      GFP_KERNEL);
2311                 if (!vnic->rss_table) {
2312                         rc = -ENOMEM;
2313                         goto out;
2314                 }
2315
2316                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2317
2318                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2319                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2320         }
2321         return 0;
2322
2323 out:
2324         return rc;
2325 }
2326
2327 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2328 {
2329         struct pci_dev *pdev = bp->pdev;
2330
2331         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2332                           bp->hwrm_cmd_resp_dma_addr);
2333
2334         bp->hwrm_cmd_resp_addr = NULL;
2335         if (bp->hwrm_dbg_resp_addr) {
2336                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2337                                   bp->hwrm_dbg_resp_addr,
2338                                   bp->hwrm_dbg_resp_dma_addr);
2339
2340                 bp->hwrm_dbg_resp_addr = NULL;
2341         }
2342 }
2343
2344 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2345 {
2346         struct pci_dev *pdev = bp->pdev;
2347
2348         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2349                                                    &bp->hwrm_cmd_resp_dma_addr,
2350                                                    GFP_KERNEL);
2351         if (!bp->hwrm_cmd_resp_addr)
2352                 return -ENOMEM;
2353         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2354                                                     HWRM_DBG_REG_BUF_SIZE,
2355                                                     &bp->hwrm_dbg_resp_dma_addr,
2356                                                     GFP_KERNEL);
2357         if (!bp->hwrm_dbg_resp_addr)
2358                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2359
2360         return 0;
2361 }
2362
2363 static void bnxt_free_stats(struct bnxt *bp)
2364 {
2365         u32 size, i;
2366         struct pci_dev *pdev = bp->pdev;
2367
2368         if (!bp->bnapi)
2369                 return;
2370
2371         size = sizeof(struct ctx_hw_stats);
2372
2373         for (i = 0; i < bp->cp_nr_rings; i++) {
2374                 struct bnxt_napi *bnapi = bp->bnapi[i];
2375                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2376
2377                 if (cpr->hw_stats) {
2378                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2379                                           cpr->hw_stats_map);
2380                         cpr->hw_stats = NULL;
2381                 }
2382         }
2383 }
2384
2385 static int bnxt_alloc_stats(struct bnxt *bp)
2386 {
2387         u32 size, i;
2388         struct pci_dev *pdev = bp->pdev;
2389
2390         size = sizeof(struct ctx_hw_stats);
2391
2392         for (i = 0; i < bp->cp_nr_rings; i++) {
2393                 struct bnxt_napi *bnapi = bp->bnapi[i];
2394                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2395
2396                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2397                                                    &cpr->hw_stats_map,
2398                                                    GFP_KERNEL);
2399                 if (!cpr->hw_stats)
2400                         return -ENOMEM;
2401
2402                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2403         }
2404         return 0;
2405 }
2406
2407 static void bnxt_clear_ring_indices(struct bnxt *bp)
2408 {
2409         int i;
2410
2411         if (!bp->bnapi)
2412                 return;
2413
2414         for (i = 0; i < bp->cp_nr_rings; i++) {
2415                 struct bnxt_napi *bnapi = bp->bnapi[i];
2416                 struct bnxt_cp_ring_info *cpr;
2417                 struct bnxt_rx_ring_info *rxr;
2418                 struct bnxt_tx_ring_info *txr;
2419
2420                 if (!bnapi)
2421                         continue;
2422
2423                 cpr = &bnapi->cp_ring;
2424                 cpr->cp_raw_cons = 0;
2425
2426                 txr = &bnapi->tx_ring;
2427                 txr->tx_prod = 0;
2428                 txr->tx_cons = 0;
2429
2430                 rxr = &bnapi->rx_ring;
2431                 rxr->rx_prod = 0;
2432                 rxr->rx_agg_prod = 0;
2433                 rxr->rx_sw_agg_prod = 0;
2434         }
2435 }
2436
2437 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2438 {
2439 #ifdef CONFIG_RFS_ACCEL
2440         int i;
2441
2442         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2443          * safe to delete the hash table.
2444          */
2445         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2446                 struct hlist_head *head;
2447                 struct hlist_node *tmp;
2448                 struct bnxt_ntuple_filter *fltr;
2449
2450                 head = &bp->ntp_fltr_hash_tbl[i];
2451                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2452                         hlist_del(&fltr->hash);
2453                         kfree(fltr);
2454                 }
2455         }
2456         if (irq_reinit) {
2457                 kfree(bp->ntp_fltr_bmap);
2458                 bp->ntp_fltr_bmap = NULL;
2459         }
2460         bp->ntp_fltr_count = 0;
2461 #endif
2462 }
2463
2464 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2465 {
2466 #ifdef CONFIG_RFS_ACCEL
2467         int i, rc = 0;
2468
2469         if (!(bp->flags & BNXT_FLAG_RFS))
2470                 return 0;
2471
2472         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2473                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2474
2475         bp->ntp_fltr_count = 0;
2476         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2477                                     GFP_KERNEL);
2478
2479         if (!bp->ntp_fltr_bmap)
2480                 rc = -ENOMEM;
2481
2482         return rc;
2483 #else
2484         return 0;
2485 #endif
2486 }
2487
2488 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2489 {
2490         bnxt_free_vnic_attributes(bp);
2491         bnxt_free_tx_rings(bp);
2492         bnxt_free_rx_rings(bp);
2493         bnxt_free_cp_rings(bp);
2494         bnxt_free_ntp_fltrs(bp, irq_re_init);
2495         if (irq_re_init) {
2496                 bnxt_free_stats(bp);
2497                 bnxt_free_ring_grps(bp);
2498                 bnxt_free_vnics(bp);
2499                 kfree(bp->bnapi);
2500                 bp->bnapi = NULL;
2501         } else {
2502                 bnxt_clear_ring_indices(bp);
2503         }
2504 }
2505
2506 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2507 {
2508         int i, rc, size, arr_size;
2509         void *bnapi;
2510
2511         if (irq_re_init) {
2512                 /* Allocate bnapi mem pointer array and mem block for
2513                  * all queues
2514                  */
2515                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2516                                 bp->cp_nr_rings);
2517                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2518                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2519                 if (!bnapi)
2520                         return -ENOMEM;
2521
2522                 bp->bnapi = bnapi;
2523                 bnapi += arr_size;
2524                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2525                         bp->bnapi[i] = bnapi;
2526                         bp->bnapi[i]->index = i;
2527                         bp->bnapi[i]->bp = bp;
2528                 }
2529
2530                 rc = bnxt_alloc_stats(bp);
2531                 if (rc)
2532                         goto alloc_mem_err;
2533
2534                 rc = bnxt_alloc_ntp_fltrs(bp);
2535                 if (rc)
2536                         goto alloc_mem_err;
2537
2538                 rc = bnxt_alloc_vnics(bp);
2539                 if (rc)
2540                         goto alloc_mem_err;
2541         }
2542
2543         bnxt_init_ring_struct(bp);
2544
2545         rc = bnxt_alloc_rx_rings(bp);
2546         if (rc)
2547                 goto alloc_mem_err;
2548
2549         rc = bnxt_alloc_tx_rings(bp);
2550         if (rc)
2551                 goto alloc_mem_err;
2552
2553         rc = bnxt_alloc_cp_rings(bp);
2554         if (rc)
2555                 goto alloc_mem_err;
2556
2557         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2558                                   BNXT_VNIC_UCAST_FLAG;
2559         rc = bnxt_alloc_vnic_attributes(bp);
2560         if (rc)
2561                 goto alloc_mem_err;
2562         return 0;
2563
2564 alloc_mem_err:
2565         bnxt_free_mem(bp, true);
2566         return rc;
2567 }
2568
2569 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2570                             u16 cmpl_ring, u16 target_id)
2571 {
2572         struct hwrm_cmd_req_hdr *req = request;
2573
2574         req->cmpl_ring_req_type =
2575                 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2576         req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2577         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2578 }
2579
2580 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2581 {
2582         int i, intr_process, rc;
2583         struct hwrm_cmd_req_hdr *req = msg;
2584         u32 *data = msg;
2585         __le32 *resp_len, *valid;
2586         u16 cp_ring_id, len = 0;
2587         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2588
2589         req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2590         memset(resp, 0, PAGE_SIZE);
2591         cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2592                       HWRM_CMPL_RING_MASK) >>
2593                      HWRM_CMPL_RING_SFT;
2594         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2595
2596         /* Write request msg to hwrm channel */
2597         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2598
2599         /* currently supports only one outstanding message */
2600         if (intr_process)
2601                 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2602                                        HWRM_SEQ_ID_MASK;
2603
2604         /* Ring channel doorbell */
2605         writel(1, bp->bar0 + 0x100);
2606
2607         i = 0;
2608         if (intr_process) {
2609                 /* Wait until hwrm response cmpl interrupt is processed */
2610                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2611                        i++ < timeout) {
2612                         usleep_range(600, 800);
2613                 }
2614
2615                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2616                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2617                                    req->cmpl_ring_req_type);
2618                         return -1;
2619                 }
2620         } else {
2621                 /* Check if response len is updated */
2622                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2623                 for (i = 0; i < timeout; i++) {
2624                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2625                               HWRM_RESP_LEN_SFT;
2626                         if (len)
2627                                 break;
2628                         usleep_range(600, 800);
2629                 }
2630
2631                 if (i >= timeout) {
2632                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2633                                    timeout, req->cmpl_ring_req_type,
2634                                    req->target_id_seq_id, *resp_len);
2635                         return -1;
2636                 }
2637
2638                 /* Last word of resp contains valid bit */
2639                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2640                 for (i = 0; i < timeout; i++) {
2641                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2642                                 break;
2643                         usleep_range(600, 800);
2644                 }
2645
2646                 if (i >= timeout) {
2647                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2648                                    timeout, req->cmpl_ring_req_type,
2649                                    req->target_id_seq_id, len, *valid);
2650                         return -1;
2651                 }
2652         }
2653
2654         rc = le16_to_cpu(resp->error_code);
2655         if (rc) {
2656                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2657                            le16_to_cpu(resp->req_type),
2658                            le16_to_cpu(resp->seq_id), rc);
2659                 return rc;
2660         }
2661         return 0;
2662 }
2663
2664 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2665 {
2666         int rc;
2667
2668         mutex_lock(&bp->hwrm_cmd_lock);
2669         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2670         mutex_unlock(&bp->hwrm_cmd_lock);
2671         return rc;
2672 }
2673
2674 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2675 {
2676         struct hwrm_func_drv_rgtr_input req = {0};
2677         int i;
2678
2679         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2680
2681         req.enables =
2682                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2683                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2684                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2685
2686         /* TODO: current async event fwd bits are not defined and the firmware
2687          * only checks if it is non-zero to enable async event forwarding
2688          */
2689         req.async_event_fwd[0] |= cpu_to_le32(1);
2690         req.os_type = cpu_to_le16(1);
2691         req.ver_maj = DRV_VER_MAJ;
2692         req.ver_min = DRV_VER_MIN;
2693         req.ver_upd = DRV_VER_UPD;
2694
2695         if (BNXT_PF(bp)) {
2696                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2697                 u32 *data = (u32 *)vf_req_snif_bmap;
2698
2699                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2700                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2701                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2702
2703                 for (i = 0; i < 8; i++)
2704                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2705
2706                 req.enables |=
2707                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2708         }
2709
2710         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2711 }
2712
2713 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2714 {
2715         struct hwrm_func_drv_unrgtr_input req = {0};
2716
2717         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2718         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2719 }
2720
2721 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2722 {
2723         u32 rc = 0;
2724         struct hwrm_tunnel_dst_port_free_input req = {0};
2725
2726         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2727         req.tunnel_type = tunnel_type;
2728
2729         switch (tunnel_type) {
2730         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2731                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2732                 break;
2733         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2734                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2735                 break;
2736         default:
2737                 break;
2738         }
2739
2740         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2741         if (rc)
2742                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2743                            rc);
2744         return rc;
2745 }
2746
2747 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2748                                            u8 tunnel_type)
2749 {
2750         u32 rc = 0;
2751         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2752         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2753
2754         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2755
2756         req.tunnel_type = tunnel_type;
2757         req.tunnel_dst_port_val = port;
2758
2759         mutex_lock(&bp->hwrm_cmd_lock);
2760         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2761         if (rc) {
2762                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2763                            rc);
2764                 goto err_out;
2765         }
2766
2767         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2768                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2769
2770         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2771                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2772 err_out:
2773         mutex_unlock(&bp->hwrm_cmd_lock);
2774         return rc;
2775 }
2776
2777 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2778 {
2779         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2780         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2781
2782         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2783         req.dflt_vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2784
2785         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2786         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2787         req.mask = cpu_to_le32(vnic->rx_mask);
2788         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2789 }
2790
2791 #ifdef CONFIG_RFS_ACCEL
2792 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2793                                             struct bnxt_ntuple_filter *fltr)
2794 {
2795         struct hwrm_cfa_ntuple_filter_free_input req = {0};
2796
2797         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2798         req.ntuple_filter_id = fltr->filter_id;
2799         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2800 }
2801
2802 #define BNXT_NTP_FLTR_FLAGS                                     \
2803         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
2804          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
2805          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
2806          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
2807          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
2808          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
2809          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
2810          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
2811          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
2812          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
2813          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
2814          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
2815          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
2816          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID)
2817
2818 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2819                                              struct bnxt_ntuple_filter *fltr)
2820 {
2821         int rc = 0;
2822         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2823         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2824                 bp->hwrm_cmd_resp_addr;
2825         struct flow_keys *keys = &fltr->fkeys;
2826         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2827
2828         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2829         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2830
2831         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2832
2833         req.ethertype = htons(ETH_P_IP);
2834         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2835         req.ipaddr_type = 4;
2836         req.ip_protocol = keys->basic.ip_proto;
2837
2838         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2839         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2840         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2841         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2842
2843         req.src_port = keys->ports.src;
2844         req.src_port_mask = cpu_to_be16(0xffff);
2845         req.dst_port = keys->ports.dst;
2846         req.dst_port_mask = cpu_to_be16(0xffff);
2847
2848         req.dst_vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2849         mutex_lock(&bp->hwrm_cmd_lock);
2850         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2851         if (!rc)
2852                 fltr->filter_id = resp->ntuple_filter_id;
2853         mutex_unlock(&bp->hwrm_cmd_lock);
2854         return rc;
2855 }
2856 #endif
2857
2858 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2859                                      u8 *mac_addr)
2860 {
2861         u32 rc = 0;
2862         struct hwrm_cfa_l2_filter_alloc_input req = {0};
2863         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2864
2865         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2866         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2867                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2868         req.dst_vnic_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2869         req.enables =
2870                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2871                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID |
2872                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2873         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2874         req.l2_addr_mask[0] = 0xff;
2875         req.l2_addr_mask[1] = 0xff;
2876         req.l2_addr_mask[2] = 0xff;
2877         req.l2_addr_mask[3] = 0xff;
2878         req.l2_addr_mask[4] = 0xff;
2879         req.l2_addr_mask[5] = 0xff;
2880
2881         mutex_lock(&bp->hwrm_cmd_lock);
2882         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2883         if (!rc)
2884                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2885                                                         resp->l2_filter_id;
2886         mutex_unlock(&bp->hwrm_cmd_lock);
2887         return rc;
2888 }
2889
2890 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2891 {
2892         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2893         int rc = 0;
2894
2895         /* Any associated ntuple filters will also be cleared by firmware. */
2896         mutex_lock(&bp->hwrm_cmd_lock);
2897         for (i = 0; i < num_of_vnics; i++) {
2898                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2899
2900                 for (j = 0; j < vnic->uc_filter_count; j++) {
2901                         struct hwrm_cfa_l2_filter_free_input req = {0};
2902
2903                         bnxt_hwrm_cmd_hdr_init(bp, &req,
2904                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
2905
2906                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
2907
2908                         rc = _hwrm_send_message(bp, &req, sizeof(req),
2909                                                 HWRM_CMD_TIMEOUT);
2910                 }
2911                 vnic->uc_filter_count = 0;
2912         }
2913         mutex_unlock(&bp->hwrm_cmd_lock);
2914
2915         return rc;
2916 }
2917
2918 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2919 {
2920         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2921         struct hwrm_vnic_tpa_cfg_input req = {0};
2922
2923         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2924
2925         if (tpa_flags) {
2926                 u16 mss = bp->dev->mtu - 40;
2927                 u32 nsegs, n, segs = 0, flags;
2928
2929                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2930                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2931                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2932                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2933                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2934                 if (tpa_flags & BNXT_FLAG_GRO)
2935                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2936
2937                 req.flags = cpu_to_le32(flags);
2938
2939                 req.enables =
2940                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2941                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS);
2942
2943                 /* Number of segs are log2 units, and first packet is not
2944                  * included as part of this units.
2945                  */
2946                 if (mss <= PAGE_SIZE) {
2947                         n = PAGE_SIZE / mss;
2948                         nsegs = (MAX_SKB_FRAGS - 1) * n;
2949                 } else {
2950                         n = mss / PAGE_SIZE;
2951                         if (mss & (PAGE_SIZE - 1))
2952                                 n++;
2953                         nsegs = (MAX_SKB_FRAGS - n) / n;
2954                 }
2955
2956                 segs = ilog2(nsegs);
2957                 req.max_agg_segs = cpu_to_le16(segs);
2958                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2959         }
2960         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2961
2962         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2963 }
2964
2965 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2966 {
2967         u32 i, j, max_rings;
2968         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2969         struct hwrm_vnic_rss_cfg_input req = {0};
2970
2971         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2972                 return 0;
2973
2974         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2975         if (set_rss) {
2976                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
2977                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
2978                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
2979                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
2980
2981                 req.hash_type = cpu_to_le32(vnic->hash_type);
2982
2983                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2984                         max_rings = bp->rx_nr_rings;
2985                 else
2986                         max_rings = 1;
2987
2988                 /* Fill the RSS indirection table with ring group ids */
2989                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
2990                         if (j == max_rings)
2991                                 j = 0;
2992                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
2993                 }
2994
2995                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
2996                 req.hash_key_tbl_addr =
2997                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
2998         }
2999         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3000         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3001 }
3002
3003 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3004 {
3005         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3006         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3007
3008         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3009         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3010                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3011                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3012         req.enables =
3013                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3014                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3015         /* thresholds not implemented in firmware yet */
3016         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3017         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3018         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3019         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3020 }
3021
3022 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3023 {
3024         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3025
3026         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3027         req.rss_cos_lb_ctx_id =
3028                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3029
3030         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3031         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3032 }
3033
3034 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3035 {
3036         int i;
3037
3038         for (i = 0; i < bp->nr_vnics; i++) {
3039                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3040
3041                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3042                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3043         }
3044         bp->rsscos_nr_ctxs = 0;
3045 }
3046
3047 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3048 {
3049         int rc;
3050         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3051         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3052                                                 bp->hwrm_cmd_resp_addr;
3053
3054         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3055                                -1);
3056
3057         mutex_lock(&bp->hwrm_cmd_lock);
3058         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3059         if (!rc)
3060                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3061                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3062         mutex_unlock(&bp->hwrm_cmd_lock);
3063
3064         return rc;
3065 }
3066
3067 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3068 {
3069         int grp_idx = 0;
3070         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3071         struct hwrm_vnic_cfg_input req = {0};
3072
3073         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3074         /* Only RSS support for now TBD: COS & LB */
3075         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3076                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3077         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3078         req.cos_rule = cpu_to_le16(0xffff);
3079         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3080                 grp_idx = 0;
3081         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3082                 grp_idx = vnic_id - 1;
3083
3084         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3085         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3086
3087         req.lb_rule = cpu_to_le16(0xffff);
3088         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3089                               VLAN_HLEN);
3090
3091         if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3092                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3093
3094         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3095 }
3096
3097 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3098 {
3099         u32 rc = 0;
3100
3101         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3102                 struct hwrm_vnic_free_input req = {0};
3103
3104                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3105                 req.vnic_id =
3106                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3107
3108                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3109                 if (rc)
3110                         return rc;
3111                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3112         }
3113         return rc;
3114 }
3115
3116 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3117 {
3118         u16 i;
3119
3120         for (i = 0; i < bp->nr_vnics; i++)
3121                 bnxt_hwrm_vnic_free_one(bp, i);
3122 }
3123
3124 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, u16 start_grp_id,
3125                                 u16 end_grp_id)
3126 {
3127         u32 rc = 0, i, j;
3128         struct hwrm_vnic_alloc_input req = {0};
3129         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3130
3131         /* map ring groups to this vnic */
3132         for (i = start_grp_id, j = 0; i < end_grp_id; i++, j++) {
3133                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) {
3134                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3135                                    j, (end_grp_id - start_grp_id));
3136                         break;
3137                 }
3138                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3139                                         bp->grp_info[i].fw_grp_id;
3140         }
3141
3142         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3143         if (vnic_id == 0)
3144                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3145
3146         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3147
3148         mutex_lock(&bp->hwrm_cmd_lock);
3149         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3150         if (!rc)
3151                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3152         mutex_unlock(&bp->hwrm_cmd_lock);
3153         return rc;
3154 }
3155
3156 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3157 {
3158         u16 i;
3159         u32 rc = 0;
3160
3161         mutex_lock(&bp->hwrm_cmd_lock);
3162         for (i = 0; i < bp->rx_nr_rings; i++) {
3163                 struct hwrm_ring_grp_alloc_input req = {0};
3164                 struct hwrm_ring_grp_alloc_output *resp =
3165                                         bp->hwrm_cmd_resp_addr;
3166
3167                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3168
3169                 req.cr = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3170                 req.rr = cpu_to_le16(bp->grp_info[i].rx_fw_ring_id);
3171                 req.ar = cpu_to_le16(bp->grp_info[i].agg_fw_ring_id);
3172                 req.sc = cpu_to_le16(bp->grp_info[i].fw_stats_ctx);
3173
3174                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3175                                         HWRM_CMD_TIMEOUT);
3176                 if (rc)
3177                         break;
3178
3179                 bp->grp_info[i].fw_grp_id = le32_to_cpu(resp->ring_group_id);
3180         }
3181         mutex_unlock(&bp->hwrm_cmd_lock);
3182         return rc;
3183 }
3184
3185 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3186 {
3187         u16 i;
3188         u32 rc = 0;
3189         struct hwrm_ring_grp_free_input req = {0};
3190
3191         if (!bp->grp_info)
3192                 return 0;
3193
3194         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3195
3196         mutex_lock(&bp->hwrm_cmd_lock);
3197         for (i = 0; i < bp->cp_nr_rings; i++) {
3198                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3199                         continue;
3200                 req.ring_group_id =
3201                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3202
3203                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3204                                         HWRM_CMD_TIMEOUT);
3205                 if (rc)
3206                         break;
3207                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3208         }
3209         mutex_unlock(&bp->hwrm_cmd_lock);
3210         return rc;
3211 }
3212
3213 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3214                                     struct bnxt_ring_struct *ring,
3215                                     u32 ring_type, u32 map_index,
3216                                     u32 stats_ctx_id)
3217 {
3218         int rc = 0, err = 0;
3219         struct hwrm_ring_alloc_input req = {0};
3220         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3221         u16 ring_id;
3222
3223         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3224
3225         req.enables = 0;
3226         if (ring->nr_pages > 1) {
3227                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3228                 /* Page size is in log2 units */
3229                 req.page_size = BNXT_PAGE_SHIFT;
3230                 req.page_tbl_depth = 1;
3231         } else {
3232                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3233         }
3234         req.fbo = 0;
3235         /* Association of ring index with doorbell index and MSIX number */
3236         req.logical_id = cpu_to_le16(map_index);
3237
3238         switch (ring_type) {
3239         case HWRM_RING_ALLOC_TX:
3240                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3241                 /* Association of transmit ring with completion ring */
3242                 req.cmpl_ring_id =
3243                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3244                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3245                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3246                 req.queue_id = cpu_to_le16(ring->queue_id);
3247                 break;
3248         case HWRM_RING_ALLOC_RX:
3249                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3250                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3251                 break;
3252         case HWRM_RING_ALLOC_AGG:
3253                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3254                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3255                 break;
3256         case HWRM_RING_ALLOC_CMPL:
3257                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3258                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3259                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3260                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3261                 break;
3262         default:
3263                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3264                            ring_type);
3265                 return -1;
3266         }
3267
3268         mutex_lock(&bp->hwrm_cmd_lock);
3269         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3270         err = le16_to_cpu(resp->error_code);
3271         ring_id = le16_to_cpu(resp->ring_id);
3272         mutex_unlock(&bp->hwrm_cmd_lock);
3273
3274         if (rc || err) {
3275                 switch (ring_type) {
3276                 case RING_FREE_REQ_RING_TYPE_CMPL:
3277                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3278                                    rc, err);
3279                         return -1;
3280
3281                 case RING_FREE_REQ_RING_TYPE_RX:
3282                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3283                                    rc, err);
3284                         return -1;
3285
3286                 case RING_FREE_REQ_RING_TYPE_TX:
3287                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3288                                    rc, err);
3289                         return -1;
3290
3291                 default:
3292                         netdev_err(bp->dev, "Invalid ring\n");
3293                         return -1;
3294                 }
3295         }
3296         ring->fw_ring_id = ring_id;
3297         return rc;
3298 }
3299
3300 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3301 {
3302         int i, rc = 0;
3303
3304         for (i = 0; i < bp->cp_nr_rings; i++) {
3305                 struct bnxt_napi *bnapi = bp->bnapi[i];
3306                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3307                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3308
3309                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3310                                               INVALID_STATS_CTX_ID);
3311                 if (rc)
3312                         goto err_out;
3313                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3314                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3315                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3316         }
3317
3318         for (i = 0; i < bp->tx_nr_rings; i++) {
3319                 struct bnxt_napi *bnapi = bp->bnapi[i];
3320                 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3321                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3322                 u16 fw_stats_ctx = bp->grp_info[i].fw_stats_ctx;
3323
3324                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, i,
3325                                               fw_stats_ctx);
3326                 if (rc)
3327                         goto err_out;
3328                 txr->tx_doorbell = bp->bar1 + i * 0x80;
3329         }
3330
3331         for (i = 0; i < bp->rx_nr_rings; i++) {
3332                 struct bnxt_napi *bnapi = bp->bnapi[i];
3333                 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3334                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3335
3336                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, i,
3337                                               INVALID_STATS_CTX_ID);
3338                 if (rc)
3339                         goto err_out;
3340                 rxr->rx_doorbell = bp->bar1 + i * 0x80;
3341                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3342                 bp->grp_info[i].rx_fw_ring_id = ring->fw_ring_id;
3343         }
3344
3345         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3346                 for (i = 0; i < bp->rx_nr_rings; i++) {
3347                         struct bnxt_napi *bnapi = bp->bnapi[i];
3348                         struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3349                         struct bnxt_ring_struct *ring =
3350                                                 &rxr->rx_agg_ring_struct;
3351
3352                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3353                                                       HWRM_RING_ALLOC_AGG,
3354                                                       bp->rx_nr_rings + i,
3355                                                       INVALID_STATS_CTX_ID);
3356                         if (rc)
3357                                 goto err_out;
3358
3359                         rxr->rx_agg_doorbell =
3360                                 bp->bar1 + (bp->rx_nr_rings + i) * 0x80;
3361                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3362                                rxr->rx_agg_doorbell);
3363                         bp->grp_info[i].agg_fw_ring_id = ring->fw_ring_id;
3364                 }
3365         }
3366 err_out:
3367         return rc;
3368 }
3369
3370 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3371                                    struct bnxt_ring_struct *ring,
3372                                    u32 ring_type, int cmpl_ring_id)
3373 {
3374         int rc;
3375         struct hwrm_ring_free_input req = {0};
3376         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3377         u16 error_code;
3378
3379         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3380         req.ring_type = ring_type;
3381         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3382
3383         mutex_lock(&bp->hwrm_cmd_lock);
3384         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3385         error_code = le16_to_cpu(resp->error_code);
3386         mutex_unlock(&bp->hwrm_cmd_lock);
3387
3388         if (rc || error_code) {
3389                 switch (ring_type) {
3390                 case RING_FREE_REQ_RING_TYPE_CMPL:
3391                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3392                                    rc);
3393                         return rc;
3394                 case RING_FREE_REQ_RING_TYPE_RX:
3395                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3396                                    rc);
3397                         return rc;
3398                 case RING_FREE_REQ_RING_TYPE_TX:
3399                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3400                                    rc);
3401                         return rc;
3402                 default:
3403                         netdev_err(bp->dev, "Invalid ring\n");
3404                         return -1;
3405                 }
3406         }
3407         return 0;
3408 }
3409
3410 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3411 {
3412         int i;
3413
3414         if (!bp->bnapi)
3415                 return;
3416
3417         for (i = 0; i < bp->tx_nr_rings; i++) {
3418                 struct bnxt_napi *bnapi = bp->bnapi[i];
3419                 struct bnxt_tx_ring_info *txr = &bnapi->tx_ring;
3420                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3421                 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3422
3423                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3424                         hwrm_ring_free_send_msg(bp, ring,
3425                                                 RING_FREE_REQ_RING_TYPE_TX,
3426                                                 close_path ? cmpl_ring_id :
3427                                                 INVALID_HW_RING_ID);
3428                         ring->fw_ring_id = INVALID_HW_RING_ID;
3429                 }
3430         }
3431
3432         for (i = 0; i < bp->rx_nr_rings; i++) {
3433                 struct bnxt_napi *bnapi = bp->bnapi[i];
3434                 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3435                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3436                 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3437
3438                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3439                         hwrm_ring_free_send_msg(bp, ring,
3440                                                 RING_FREE_REQ_RING_TYPE_RX,
3441                                                 close_path ? cmpl_ring_id :
3442                                                 INVALID_HW_RING_ID);
3443                         ring->fw_ring_id = INVALID_HW_RING_ID;
3444                         bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3445                 }
3446         }
3447
3448         for (i = 0; i < bp->rx_nr_rings; i++) {
3449                 struct bnxt_napi *bnapi = bp->bnapi[i];
3450                 struct bnxt_rx_ring_info *rxr = &bnapi->rx_ring;
3451                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3452                 u32 cmpl_ring_id = bp->grp_info[i].cp_fw_ring_id;
3453
3454                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3455                         hwrm_ring_free_send_msg(bp, ring,
3456                                                 RING_FREE_REQ_RING_TYPE_RX,
3457                                                 close_path ? cmpl_ring_id :
3458                                                 INVALID_HW_RING_ID);
3459                         ring->fw_ring_id = INVALID_HW_RING_ID;
3460                         bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3461                 }
3462         }
3463
3464         for (i = 0; i < bp->cp_nr_rings; i++) {
3465                 struct bnxt_napi *bnapi = bp->bnapi[i];
3466                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3467                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3468
3469                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3470                         hwrm_ring_free_send_msg(bp, ring,
3471                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3472                                                 INVALID_HW_RING_ID);
3473                         ring->fw_ring_id = INVALID_HW_RING_ID;
3474                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3475                 }
3476         }
3477 }
3478
3479 int bnxt_hwrm_set_coal(struct bnxt *bp)
3480 {
3481         int i, rc = 0;
3482         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3483         u16 max_buf, max_buf_irq;
3484         u16 buf_tmr, buf_tmr_irq;
3485         u32 flags;
3486
3487         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3488                                -1, -1);
3489
3490         /* Each rx completion (2 records) should be DMAed immediately */
3491         max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3492         /* max_buf must not be zero */
3493         max_buf = clamp_t(u16, max_buf, 1, 63);
3494         max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3495         buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3496         buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3497
3498         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3499
3500         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3501          * if coal_ticks is less than 25 us.
3502          */
3503         if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3504                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3505
3506         req.flags = cpu_to_le16(flags);
3507         req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3508         req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3509         req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3510         req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3511         req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3512         req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3513         req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3514
3515         mutex_lock(&bp->hwrm_cmd_lock);
3516         for (i = 0; i < bp->cp_nr_rings; i++) {
3517                 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3518
3519                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3520                                         HWRM_CMD_TIMEOUT);
3521                 if (rc)
3522                         break;
3523         }
3524         mutex_unlock(&bp->hwrm_cmd_lock);
3525         return rc;
3526 }
3527
3528 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3529 {
3530         int rc = 0, i;
3531         struct hwrm_stat_ctx_free_input req = {0};
3532
3533         if (!bp->bnapi)
3534                 return 0;
3535
3536         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3537
3538         mutex_lock(&bp->hwrm_cmd_lock);
3539         for (i = 0; i < bp->cp_nr_rings; i++) {
3540                 struct bnxt_napi *bnapi = bp->bnapi[i];
3541                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3542
3543                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3544                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3545
3546                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3547                                                 HWRM_CMD_TIMEOUT);
3548                         if (rc)
3549                                 break;
3550
3551                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3552                 }
3553         }
3554         mutex_unlock(&bp->hwrm_cmd_lock);
3555         return rc;
3556 }
3557
3558 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3559 {
3560         int rc = 0, i;
3561         struct hwrm_stat_ctx_alloc_input req = {0};
3562         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3563
3564         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3565
3566         req.update_period_ms = cpu_to_le32(1000);
3567
3568         mutex_lock(&bp->hwrm_cmd_lock);
3569         for (i = 0; i < bp->cp_nr_rings; i++) {
3570                 struct bnxt_napi *bnapi = bp->bnapi[i];
3571                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3572
3573                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3574
3575                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3576                                         HWRM_CMD_TIMEOUT);
3577                 if (rc)
3578                         break;
3579
3580                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3581
3582                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3583         }
3584         mutex_unlock(&bp->hwrm_cmd_lock);
3585         return 0;
3586 }
3587
3588 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3589 {
3590         int rc = 0;
3591         struct hwrm_func_qcaps_input req = {0};
3592         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3593
3594         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3595         req.fid = cpu_to_le16(0xffff);
3596
3597         mutex_lock(&bp->hwrm_cmd_lock);
3598         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3599         if (rc)
3600                 goto hwrm_func_qcaps_exit;
3601
3602         if (BNXT_PF(bp)) {
3603                 struct bnxt_pf_info *pf = &bp->pf;
3604
3605                 pf->fw_fid = le16_to_cpu(resp->fid);
3606                 pf->port_id = le16_to_cpu(resp->port_id);
3607                 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3608                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3609                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3610                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3611                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3612                 pf->max_pf_tx_rings = pf->max_tx_rings;
3613                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3614                 pf->max_pf_rx_rings = pf->max_rx_rings;
3615                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3616                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3617                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3618                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3619                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3620                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3621                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3622                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3623                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3624                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3625                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3626         } else {
3627 #ifdef CONFIG_BNXT_SRIOV
3628                 struct bnxt_vf_info *vf = &bp->vf;
3629
3630                 vf->fw_fid = le16_to_cpu(resp->fid);
3631                 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3632                 if (is_valid_ether_addr(vf->mac_addr))
3633                         /* overwrite netdev dev_adr with admin VF MAC */
3634                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3635                 else
3636                         random_ether_addr(bp->dev->dev_addr);
3637
3638                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3639                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3640                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3641                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3642                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3643                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3644                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3645 #endif
3646         }
3647
3648         bp->tx_push_thresh = 0;
3649         if (resp->flags &
3650             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3651                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3652
3653 hwrm_func_qcaps_exit:
3654         mutex_unlock(&bp->hwrm_cmd_lock);
3655         return rc;
3656 }
3657
3658 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3659 {
3660         struct hwrm_func_reset_input req = {0};
3661
3662         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3663         req.enables = 0;
3664
3665         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3666 }
3667
3668 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3669 {
3670         int rc = 0;
3671         struct hwrm_queue_qportcfg_input req = {0};
3672         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3673         u8 i, *qptr;
3674
3675         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3676
3677         mutex_lock(&bp->hwrm_cmd_lock);
3678         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3679         if (rc)
3680                 goto qportcfg_exit;
3681
3682         if (!resp->max_configurable_queues) {
3683                 rc = -EINVAL;
3684                 goto qportcfg_exit;
3685         }
3686         bp->max_tc = resp->max_configurable_queues;
3687         if (bp->max_tc > BNXT_MAX_QUEUE)
3688                 bp->max_tc = BNXT_MAX_QUEUE;
3689
3690         qptr = &resp->queue_id0;
3691         for (i = 0; i < bp->max_tc; i++) {
3692                 bp->q_info[i].queue_id = *qptr++;
3693                 bp->q_info[i].queue_profile = *qptr++;
3694         }
3695
3696 qportcfg_exit:
3697         mutex_unlock(&bp->hwrm_cmd_lock);
3698         return rc;
3699 }
3700
3701 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3702 {
3703         int rc;
3704         struct hwrm_ver_get_input req = {0};
3705         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3706
3707         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3708         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3709         req.hwrm_intf_min = HWRM_VERSION_MINOR;
3710         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3711         mutex_lock(&bp->hwrm_cmd_lock);
3712         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3713         if (rc)
3714                 goto hwrm_ver_get_exit;
3715
3716         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3717
3718         if (req.hwrm_intf_maj != resp->hwrm_intf_maj ||
3719             req.hwrm_intf_min != resp->hwrm_intf_min ||
3720             req.hwrm_intf_upd != resp->hwrm_intf_upd) {
3721                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n",
3722                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
3723                             resp->hwrm_intf_upd, req.hwrm_intf_maj,
3724                             req.hwrm_intf_min, req.hwrm_intf_upd);
3725                 netdev_warn(bp->dev, "Please update driver or firmware with matching interface versions.\n");
3726         }
3727         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3728                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3729                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3730
3731 hwrm_ver_get_exit:
3732         mutex_unlock(&bp->hwrm_cmd_lock);
3733         return rc;
3734 }
3735
3736 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3737 {
3738         if (bp->vxlan_port_cnt) {
3739                 bnxt_hwrm_tunnel_dst_port_free(
3740                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3741         }
3742         bp->vxlan_port_cnt = 0;
3743         if (bp->nge_port_cnt) {
3744                 bnxt_hwrm_tunnel_dst_port_free(
3745                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3746         }
3747         bp->nge_port_cnt = 0;
3748 }
3749
3750 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3751 {
3752         int rc, i;
3753         u32 tpa_flags = 0;
3754
3755         if (set_tpa)
3756                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3757         for (i = 0; i < bp->nr_vnics; i++) {
3758                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3759                 if (rc) {
3760                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3761                                    rc, i);
3762                         return rc;
3763                 }
3764         }
3765         return 0;
3766 }
3767
3768 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3769 {
3770         int i;
3771
3772         for (i = 0; i < bp->nr_vnics; i++)
3773                 bnxt_hwrm_vnic_set_rss(bp, i, false);
3774 }
3775
3776 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3777                                     bool irq_re_init)
3778 {
3779         if (bp->vnic_info) {
3780                 bnxt_hwrm_clear_vnic_filter(bp);
3781                 /* clear all RSS setting before free vnic ctx */
3782                 bnxt_hwrm_clear_vnic_rss(bp);
3783                 bnxt_hwrm_vnic_ctx_free(bp);
3784                 /* before free the vnic, undo the vnic tpa settings */
3785                 if (bp->flags & BNXT_FLAG_TPA)
3786                         bnxt_set_tpa(bp, false);
3787                 bnxt_hwrm_vnic_free(bp);
3788         }
3789         bnxt_hwrm_ring_free(bp, close_path);
3790         bnxt_hwrm_ring_grp_free(bp);
3791         if (irq_re_init) {
3792                 bnxt_hwrm_stat_ctx_free(bp);
3793                 bnxt_hwrm_free_tunnel_ports(bp);
3794         }
3795 }
3796
3797 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3798 {
3799         int rc;
3800
3801         /* allocate context for vnic */
3802         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3803         if (rc) {
3804                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3805                            vnic_id, rc);
3806                 goto vnic_setup_err;
3807         }
3808         bp->rsscos_nr_ctxs++;
3809
3810         /* configure default vnic, ring grp */
3811         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3812         if (rc) {
3813                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3814                            vnic_id, rc);
3815                 goto vnic_setup_err;
3816         }
3817
3818         /* Enable RSS hashing on vnic */
3819         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3820         if (rc) {
3821                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3822                            vnic_id, rc);
3823                 goto vnic_setup_err;
3824         }
3825
3826         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3827                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3828                 if (rc) {
3829                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3830                                    vnic_id, rc);
3831                 }
3832         }
3833
3834 vnic_setup_err:
3835         return rc;
3836 }
3837
3838 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3839 {
3840 #ifdef CONFIG_RFS_ACCEL
3841         int i, rc = 0;
3842
3843         for (i = 0; i < bp->rx_nr_rings; i++) {
3844                 u16 vnic_id = i + 1;
3845                 u16 ring_id = i;
3846
3847                 if (vnic_id >= bp->nr_vnics)
3848                         break;
3849
3850                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3851                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, ring_id + 1);
3852                 if (rc) {
3853                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3854                                    vnic_id, rc);
3855                         break;
3856                 }
3857                 rc = bnxt_setup_vnic(bp, vnic_id);
3858                 if (rc)
3859                         break;
3860         }
3861         return rc;
3862 #else
3863         return 0;
3864 #endif
3865 }
3866
3867 static int bnxt_cfg_rx_mode(struct bnxt *);
3868
3869 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3870 {
3871         int rc = 0;
3872
3873         if (irq_re_init) {
3874                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3875                 if (rc) {
3876                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3877                                    rc);
3878                         goto err_out;
3879                 }
3880         }
3881
3882         rc = bnxt_hwrm_ring_alloc(bp);
3883         if (rc) {
3884                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3885                 goto err_out;
3886         }
3887
3888         rc = bnxt_hwrm_ring_grp_alloc(bp);
3889         if (rc) {
3890                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3891                 goto err_out;
3892         }
3893
3894         /* default vnic 0 */
3895         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3896         if (rc) {
3897                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3898                 goto err_out;
3899         }
3900
3901         rc = bnxt_setup_vnic(bp, 0);
3902         if (rc)
3903                 goto err_out;
3904
3905         if (bp->flags & BNXT_FLAG_RFS) {
3906                 rc = bnxt_alloc_rfs_vnics(bp);
3907                 if (rc)
3908                         goto err_out;
3909         }
3910
3911         if (bp->flags & BNXT_FLAG_TPA) {
3912                 rc = bnxt_set_tpa(bp, true);
3913                 if (rc)
3914                         goto err_out;
3915         }
3916
3917         if (BNXT_VF(bp))
3918                 bnxt_update_vf_mac(bp);
3919
3920         /* Filter for default vnic 0 */
3921         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3922         if (rc) {
3923                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3924                 goto err_out;
3925         }
3926         bp->vnic_info[0].uc_filter_count = 1;
3927
3928         bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST |
3929                                    CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3930
3931         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3932                 bp->vnic_info[0].rx_mask |=
3933                                 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3934
3935         rc = bnxt_cfg_rx_mode(bp);
3936         if (rc)
3937                 goto err_out;
3938
3939         rc = bnxt_hwrm_set_coal(bp);
3940         if (rc)
3941                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3942                             rc);
3943
3944         return 0;
3945
3946 err_out:
3947         bnxt_hwrm_resource_free(bp, 0, true);
3948
3949         return rc;
3950 }
3951
3952 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3953 {
3954         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3955         return 0;
3956 }
3957
3958 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3959 {
3960         bnxt_init_rx_rings(bp);
3961         bnxt_init_tx_rings(bp);
3962         bnxt_init_ring_grps(bp, irq_re_init);
3963         bnxt_init_vnics(bp);
3964
3965         return bnxt_init_chip(bp, irq_re_init);
3966 }
3967
3968 static void bnxt_disable_int(struct bnxt *bp)
3969 {
3970         int i;
3971
3972         if (!bp->bnapi)
3973                 return;
3974
3975         for (i = 0; i < bp->cp_nr_rings; i++) {
3976                 struct bnxt_napi *bnapi = bp->bnapi[i];
3977                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3978
3979                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3980         }
3981 }
3982
3983 static void bnxt_enable_int(struct bnxt *bp)
3984 {
3985         int i;
3986
3987         atomic_set(&bp->intr_sem, 0);
3988         for (i = 0; i < bp->cp_nr_rings; i++) {
3989                 struct bnxt_napi *bnapi = bp->bnapi[i];
3990                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3991
3992                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3993         }
3994 }
3995
3996 static int bnxt_set_real_num_queues(struct bnxt *bp)
3997 {
3998         int rc;
3999         struct net_device *dev = bp->dev;
4000
4001         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4002         if (rc)
4003                 return rc;
4004
4005         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4006         if (rc)
4007                 return rc;
4008
4009 #ifdef CONFIG_RFS_ACCEL
4010         if (bp->rx_nr_rings)
4011                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4012         if (!dev->rx_cpu_rmap)
4013                 rc = -ENOMEM;
4014 #endif
4015
4016         return rc;
4017 }
4018
4019 static int bnxt_setup_msix(struct bnxt *bp)
4020 {
4021         struct msix_entry *msix_ent;
4022         struct net_device *dev = bp->dev;
4023         int i, total_vecs, rc = 0;
4024         const int len = sizeof(bp->irq_tbl[0].name);
4025
4026         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4027         total_vecs = bp->cp_nr_rings;
4028
4029         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4030         if (!msix_ent)
4031                 return -ENOMEM;
4032
4033         for (i = 0; i < total_vecs; i++) {
4034                 msix_ent[i].entry = i;
4035                 msix_ent[i].vector = 0;
4036         }
4037
4038         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs);
4039         if (total_vecs < 0) {
4040                 rc = -ENODEV;
4041                 goto msix_setup_exit;
4042         }
4043
4044         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4045         if (bp->irq_tbl) {
4046                 int tcs;
4047
4048                 /* Trim rings based upon num of vectors allocated */
4049                 bp->rx_nr_rings = min_t(int, total_vecs, bp->rx_nr_rings);
4050                 bp->tx_nr_rings = min_t(int, total_vecs, bp->tx_nr_rings);
4051                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4052                 tcs = netdev_get_num_tc(dev);
4053                 if (tcs > 1) {
4054                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4055                         if (bp->tx_nr_rings_per_tc == 0) {
4056                                 netdev_reset_tc(dev);
4057                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4058                         } else {
4059                                 int i, off, count;
4060
4061                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4062                                 for (i = 0; i < tcs; i++) {
4063                                         count = bp->tx_nr_rings_per_tc;
4064                                         off = i * count;
4065                                         netdev_set_tc_queue(dev, i, count, off);
4066                                 }
4067                         }
4068                 }
4069                 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
4070
4071                 for (i = 0; i < bp->cp_nr_rings; i++) {
4072                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4073                         snprintf(bp->irq_tbl[i].name, len,
4074                                  "%s-%s-%d", dev->name, "TxRx", i);
4075                         bp->irq_tbl[i].handler = bnxt_msix;
4076                 }
4077                 rc = bnxt_set_real_num_queues(bp);
4078                 if (rc)
4079                         goto msix_setup_exit;
4080         } else {
4081                 rc = -ENOMEM;
4082                 goto msix_setup_exit;
4083         }
4084         bp->flags |= BNXT_FLAG_USING_MSIX;
4085         kfree(msix_ent);
4086         return 0;
4087
4088 msix_setup_exit:
4089         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4090         pci_disable_msix(bp->pdev);
4091         kfree(msix_ent);
4092         return rc;
4093 }
4094
4095 static int bnxt_setup_inta(struct bnxt *bp)
4096 {
4097         int rc;
4098         const int len = sizeof(bp->irq_tbl[0].name);
4099
4100         if (netdev_get_num_tc(bp->dev))
4101                 netdev_reset_tc(bp->dev);
4102
4103         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4104         if (!bp->irq_tbl) {
4105                 rc = -ENOMEM;
4106                 return rc;
4107         }
4108         bp->rx_nr_rings = 1;
4109         bp->tx_nr_rings = 1;
4110         bp->cp_nr_rings = 1;
4111         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4112         bp->irq_tbl[0].vector = bp->pdev->irq;
4113         snprintf(bp->irq_tbl[0].name, len,
4114                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4115         bp->irq_tbl[0].handler = bnxt_inta;
4116         rc = bnxt_set_real_num_queues(bp);
4117         return rc;
4118 }
4119
4120 static int bnxt_setup_int_mode(struct bnxt *bp)
4121 {
4122         int rc = 0;
4123
4124         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4125                 rc = bnxt_setup_msix(bp);
4126
4127         if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4128                 /* fallback to INTA */
4129                 rc = bnxt_setup_inta(bp);
4130         }
4131         return rc;
4132 }
4133
4134 static void bnxt_free_irq(struct bnxt *bp)
4135 {
4136         struct bnxt_irq *irq;
4137         int i;
4138
4139 #ifdef CONFIG_RFS_ACCEL
4140         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4141         bp->dev->rx_cpu_rmap = NULL;
4142 #endif
4143         if (!bp->irq_tbl)
4144                 return;
4145
4146         for (i = 0; i < bp->cp_nr_rings; i++) {
4147                 irq = &bp->irq_tbl[i];
4148                 if (irq->requested)
4149                         free_irq(irq->vector, bp->bnapi[i]);
4150                 irq->requested = 0;
4151         }
4152         if (bp->flags & BNXT_FLAG_USING_MSIX)
4153                 pci_disable_msix(bp->pdev);
4154         kfree(bp->irq_tbl);
4155         bp->irq_tbl = NULL;
4156 }
4157
4158 static int bnxt_request_irq(struct bnxt *bp)
4159 {
4160         int i, rc = 0;
4161         unsigned long flags = 0;
4162 #ifdef CONFIG_RFS_ACCEL
4163         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4164 #endif
4165
4166         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4167                 flags = IRQF_SHARED;
4168
4169         for (i = 0; i < bp->cp_nr_rings; i++) {
4170                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4171 #ifdef CONFIG_RFS_ACCEL
4172                 if (rmap && (i < bp->rx_nr_rings)) {
4173                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4174                         if (rc)
4175                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4176                                             i);
4177                 }
4178 #endif
4179                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4180                                  bp->bnapi[i]);
4181                 if (rc)
4182                         break;
4183
4184                 irq->requested = 1;
4185         }
4186         return rc;
4187 }
4188
4189 static void bnxt_del_napi(struct bnxt *bp)
4190 {
4191         int i;
4192
4193         if (!bp->bnapi)
4194                 return;
4195
4196         for (i = 0; i < bp->cp_nr_rings; i++) {
4197                 struct bnxt_napi *bnapi = bp->bnapi[i];
4198
4199                 napi_hash_del(&bnapi->napi);
4200                 netif_napi_del(&bnapi->napi);
4201         }
4202 }
4203
4204 static void bnxt_init_napi(struct bnxt *bp)
4205 {
4206         int i;
4207         struct bnxt_napi *bnapi;
4208
4209         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4210                 for (i = 0; i < bp->cp_nr_rings; i++) {
4211                         bnapi = bp->bnapi[i];
4212                         netif_napi_add(bp->dev, &bnapi->napi,
4213                                        bnxt_poll, 64);
4214                 }
4215         } else {
4216                 bnapi = bp->bnapi[0];
4217                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4218         }
4219 }
4220
4221 static void bnxt_disable_napi(struct bnxt *bp)
4222 {
4223         int i;
4224
4225         if (!bp->bnapi)
4226                 return;
4227
4228         for (i = 0; i < bp->cp_nr_rings; i++) {
4229                 napi_disable(&bp->bnapi[i]->napi);
4230                 bnxt_disable_poll(bp->bnapi[i]);
4231         }
4232 }
4233
4234 static void bnxt_enable_napi(struct bnxt *bp)
4235 {
4236         int i;
4237
4238         for (i = 0; i < bp->cp_nr_rings; i++) {
4239                 bnxt_enable_poll(bp->bnapi[i]);
4240                 napi_enable(&bp->bnapi[i]->napi);
4241         }
4242 }
4243
4244 static void bnxt_tx_disable(struct bnxt *bp)
4245 {
4246         int i;
4247         struct bnxt_napi *bnapi;
4248         struct bnxt_tx_ring_info *txr;
4249         struct netdev_queue *txq;
4250
4251         if (bp->bnapi) {
4252                 for (i = 0; i < bp->tx_nr_rings; i++) {
4253                         bnapi = bp->bnapi[i];
4254                         txr = &bnapi->tx_ring;
4255                         txq = netdev_get_tx_queue(bp->dev, i);
4256                         __netif_tx_lock(txq, smp_processor_id());
4257                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4258                         __netif_tx_unlock(txq);
4259                 }
4260         }
4261         /* Stop all TX queues */
4262         netif_tx_disable(bp->dev);
4263         netif_carrier_off(bp->dev);
4264 }
4265
4266 static void bnxt_tx_enable(struct bnxt *bp)
4267 {
4268         int i;
4269         struct bnxt_napi *bnapi;
4270         struct bnxt_tx_ring_info *txr;
4271         struct netdev_queue *txq;
4272
4273         for (i = 0; i < bp->tx_nr_rings; i++) {
4274                 bnapi = bp->bnapi[i];
4275                 txr = &bnapi->tx_ring;
4276                 txq = netdev_get_tx_queue(bp->dev, i);
4277                 txr->dev_state = 0;
4278         }
4279         netif_tx_wake_all_queues(bp->dev);
4280         if (bp->link_info.link_up)
4281                 netif_carrier_on(bp->dev);
4282 }
4283
4284 static void bnxt_report_link(struct bnxt *bp)
4285 {
4286         if (bp->link_info.link_up) {
4287                 const char *duplex;
4288                 const char *flow_ctrl;
4289                 u16 speed;
4290
4291                 netif_carrier_on(bp->dev);
4292                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4293                         duplex = "full";
4294                 else
4295                         duplex = "half";
4296                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4297                         flow_ctrl = "ON - receive & transmit";
4298                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4299                         flow_ctrl = "ON - transmit";
4300                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4301                         flow_ctrl = "ON - receive";
4302                 else
4303                         flow_ctrl = "none";
4304                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4305                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4306                             speed, duplex, flow_ctrl);
4307         } else {
4308                 netif_carrier_off(bp->dev);
4309                 netdev_err(bp->dev, "NIC Link is Down\n");
4310         }
4311 }
4312
4313 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4314 {
4315         int rc = 0;
4316         struct bnxt_link_info *link_info = &bp->link_info;
4317         struct hwrm_port_phy_qcfg_input req = {0};
4318         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4319         u8 link_up = link_info->link_up;
4320
4321         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4322
4323         mutex_lock(&bp->hwrm_cmd_lock);
4324         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4325         if (rc) {
4326                 mutex_unlock(&bp->hwrm_cmd_lock);
4327                 return rc;
4328         }
4329
4330         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4331         link_info->phy_link_status = resp->link;
4332         link_info->duplex =  resp->duplex;
4333         link_info->pause = resp->pause;
4334         link_info->auto_mode = resp->auto_mode;
4335         link_info->auto_pause_setting = resp->auto_pause;
4336         link_info->force_pause_setting = resp->force_pause;
4337         link_info->duplex_setting = resp->duplex_setting;
4338         if (link_info->phy_link_status == BNXT_LINK_LINK)
4339                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4340         else
4341                 link_info->link_speed = 0;
4342         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4343         link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4344         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4345         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4346         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4347         link_info->phy_ver[0] = resp->phy_maj;
4348         link_info->phy_ver[1] = resp->phy_min;
4349         link_info->phy_ver[2] = resp->phy_bld;
4350         link_info->media_type = resp->media_type;
4351         link_info->transceiver = resp->transceiver_type;
4352         link_info->phy_addr = resp->phy_addr;
4353
4354         /* TODO: need to add more logic to report VF link */
4355         if (chng_link_state) {
4356                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4357                         link_info->link_up = 1;
4358                 else
4359                         link_info->link_up = 0;
4360                 if (link_up != link_info->link_up)
4361                         bnxt_report_link(bp);
4362         } else {
4363                 /* alwasy link down if not require to update link state */
4364                 link_info->link_up = 0;
4365         }
4366         mutex_unlock(&bp->hwrm_cmd_lock);
4367         return 0;
4368 }
4369
4370 static void
4371 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4372 {
4373         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4374                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4375                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4376                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4377                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4378                 req->enables |=
4379                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4380         } else {
4381                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4382                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4383                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4384                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4385                 req->enables |=
4386                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4387         }
4388 }
4389
4390 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4391                                       struct hwrm_port_phy_cfg_input *req)
4392 {
4393         u8 autoneg = bp->link_info.autoneg;
4394         u16 fw_link_speed = bp->link_info.req_link_speed;
4395         u32 advertising = bp->link_info.advertising;
4396
4397         if (autoneg & BNXT_AUTONEG_SPEED) {
4398                 req->auto_mode |=
4399                         PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4400
4401                 req->enables |= cpu_to_le32(
4402                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4403                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4404
4405                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4406                 req->flags |=
4407                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4408         } else {
4409                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4410                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4411         }
4412
4413         /* currently don't support half duplex */
4414         req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4415         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4416         /* tell chimp that the setting takes effect immediately */
4417         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4418 }
4419
4420 int bnxt_hwrm_set_pause(struct bnxt *bp)
4421 {
4422         struct hwrm_port_phy_cfg_input req = {0};
4423         int rc;
4424
4425         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4426         bnxt_hwrm_set_pause_common(bp, &req);
4427
4428         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4429             bp->link_info.force_link_chng)
4430                 bnxt_hwrm_set_link_common(bp, &req);
4431
4432         mutex_lock(&bp->hwrm_cmd_lock);
4433         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4434         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4435                 /* since changing of pause setting doesn't trigger any link
4436                  * change event, the driver needs to update the current pause
4437                  * result upon successfully return of the phy_cfg command
4438                  */
4439                 bp->link_info.pause =
4440                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4441                 bp->link_info.auto_pause_setting = 0;
4442                 if (!bp->link_info.force_link_chng)
4443                         bnxt_report_link(bp);
4444         }
4445         bp->link_info.force_link_chng = false;
4446         mutex_unlock(&bp->hwrm_cmd_lock);
4447         return rc;
4448 }
4449
4450 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4451 {
4452         struct hwrm_port_phy_cfg_input req = {0};
4453
4454         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4455         if (set_pause)
4456                 bnxt_hwrm_set_pause_common(bp, &req);
4457
4458         bnxt_hwrm_set_link_common(bp, &req);
4459         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4460 }
4461
4462 static int bnxt_update_phy_setting(struct bnxt *bp)
4463 {
4464         int rc;
4465         bool update_link = false;
4466         bool update_pause = false;
4467         struct bnxt_link_info *link_info = &bp->link_info;
4468
4469         rc = bnxt_update_link(bp, true);
4470         if (rc) {
4471                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4472                            rc);
4473                 return rc;
4474         }
4475         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4476             link_info->auto_pause_setting != link_info->req_flow_ctrl)
4477                 update_pause = true;
4478         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4479             link_info->force_pause_setting != link_info->req_flow_ctrl)
4480                 update_pause = true;
4481         if (link_info->req_duplex != link_info->duplex_setting)
4482                 update_link = true;
4483         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4484                 if (BNXT_AUTO_MODE(link_info->auto_mode))
4485                         update_link = true;
4486                 if (link_info->req_link_speed != link_info->force_link_speed)
4487                         update_link = true;
4488         } else {
4489                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4490                         update_link = true;
4491                 if (link_info->advertising != link_info->auto_link_speeds)
4492                         update_link = true;
4493                 if (link_info->req_link_speed != link_info->auto_link_speed)
4494                         update_link = true;
4495         }
4496
4497         if (update_link)
4498                 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4499         else if (update_pause)
4500                 rc = bnxt_hwrm_set_pause(bp);
4501         if (rc) {
4502                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4503                            rc);
4504                 return rc;
4505         }
4506
4507         return rc;
4508 }
4509
4510 /* Common routine to pre-map certain register block to different GRC window.
4511  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4512  * in PF and 3 windows in VF that can be customized to map in different
4513  * register blocks.
4514  */
4515 static void bnxt_preset_reg_win(struct bnxt *bp)
4516 {
4517         if (BNXT_PF(bp)) {
4518                 /* CAG registers map to GRC window #4 */
4519                 writel(BNXT_CAG_REG_BASE,
4520                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4521         }
4522 }
4523
4524 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4525 {
4526         int rc = 0;
4527
4528         bnxt_preset_reg_win(bp);
4529         netif_carrier_off(bp->dev);
4530         if (irq_re_init) {
4531                 rc = bnxt_setup_int_mode(bp);
4532                 if (rc) {
4533                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4534                                    rc);
4535                         return rc;
4536                 }
4537         }
4538         if ((bp->flags & BNXT_FLAG_RFS) &&
4539             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4540                 /* disable RFS if falling back to INTA */
4541                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4542                 bp->flags &= ~BNXT_FLAG_RFS;
4543         }
4544
4545         rc = bnxt_alloc_mem(bp, irq_re_init);
4546         if (rc) {
4547                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4548                 goto open_err_free_mem;
4549         }
4550
4551         if (irq_re_init) {
4552                 bnxt_init_napi(bp);
4553                 rc = bnxt_request_irq(bp);
4554                 if (rc) {
4555                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4556                         goto open_err;
4557                 }
4558         }
4559
4560         bnxt_enable_napi(bp);
4561
4562         rc = bnxt_init_nic(bp, irq_re_init);
4563         if (rc) {
4564                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4565                 goto open_err;
4566         }
4567
4568         if (link_re_init) {
4569                 rc = bnxt_update_phy_setting(bp);
4570                 if (rc)
4571                         goto open_err;
4572         }
4573
4574         if (irq_re_init) {
4575 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4576                 vxlan_get_rx_port(bp->dev);
4577 #endif
4578                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4579                                 bp, htons(0x17c1),
4580                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4581                         bp->nge_port_cnt = 1;
4582         }
4583
4584         set_bit(BNXT_STATE_OPEN, &bp->state);
4585         bnxt_enable_int(bp);
4586         /* Enable TX queues */
4587         bnxt_tx_enable(bp);
4588         mod_timer(&bp->timer, jiffies + bp->current_interval);
4589
4590         return 0;
4591
4592 open_err:
4593         bnxt_disable_napi(bp);
4594         bnxt_del_napi(bp);
4595
4596 open_err_free_mem:
4597         bnxt_free_skbs(bp);
4598         bnxt_free_irq(bp);
4599         bnxt_free_mem(bp, true);
4600         return rc;
4601 }
4602
4603 /* rtnl_lock held */
4604 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4605 {
4606         int rc = 0;
4607
4608         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4609         if (rc) {
4610                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4611                 dev_close(bp->dev);
4612         }
4613         return rc;
4614 }
4615
4616 static int bnxt_open(struct net_device *dev)
4617 {
4618         struct bnxt *bp = netdev_priv(dev);
4619         int rc = 0;
4620
4621         rc = bnxt_hwrm_func_reset(bp);
4622         if (rc) {
4623                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4624                            rc);
4625                 rc = -1;
4626                 return rc;
4627         }
4628         return __bnxt_open_nic(bp, true, true);
4629 }
4630
4631 static void bnxt_disable_int_sync(struct bnxt *bp)
4632 {
4633         int i;
4634
4635         atomic_inc(&bp->intr_sem);
4636         if (!netif_running(bp->dev))
4637                 return;
4638
4639         bnxt_disable_int(bp);
4640         for (i = 0; i < bp->cp_nr_rings; i++)
4641                 synchronize_irq(bp->irq_tbl[i].vector);
4642 }
4643
4644 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4645 {
4646         int rc = 0;
4647
4648 #ifdef CONFIG_BNXT_SRIOV
4649         if (bp->sriov_cfg) {
4650                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4651                                                       !bp->sriov_cfg,
4652                                                       BNXT_SRIOV_CFG_WAIT_TMO);
4653                 if (rc)
4654                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4655         }
4656 #endif
4657         /* Change device state to avoid TX queue wake up's */
4658         bnxt_tx_disable(bp);
4659
4660         clear_bit(BNXT_STATE_OPEN, &bp->state);
4661         smp_mb__after_atomic();
4662         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4663                 msleep(20);
4664
4665         /* Flush rings before disabling interrupts */
4666         bnxt_shutdown_nic(bp, irq_re_init);
4667
4668         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4669
4670         bnxt_disable_napi(bp);
4671         bnxt_disable_int_sync(bp);
4672         del_timer_sync(&bp->timer);
4673         bnxt_free_skbs(bp);
4674
4675         if (irq_re_init) {
4676                 bnxt_free_irq(bp);
4677                 bnxt_del_napi(bp);
4678         }
4679         bnxt_free_mem(bp, irq_re_init);
4680         return rc;
4681 }
4682
4683 static int bnxt_close(struct net_device *dev)
4684 {
4685         struct bnxt *bp = netdev_priv(dev);
4686
4687         bnxt_close_nic(bp, true, true);
4688         return 0;
4689 }
4690
4691 /* rtnl_lock held */
4692 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4693 {
4694         switch (cmd) {
4695         case SIOCGMIIPHY:
4696                 /* fallthru */
4697         case SIOCGMIIREG: {
4698                 if (!netif_running(dev))
4699                         return -EAGAIN;
4700
4701                 return 0;
4702         }
4703
4704         case SIOCSMIIREG:
4705                 if (!netif_running(dev))
4706                         return -EAGAIN;
4707
4708                 return 0;
4709
4710         default:
4711                 /* do nothing */
4712                 break;
4713         }
4714         return -EOPNOTSUPP;
4715 }
4716
4717 static struct rtnl_link_stats64 *
4718 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4719 {
4720         u32 i;
4721         struct bnxt *bp = netdev_priv(dev);
4722
4723         memset(stats, 0, sizeof(struct rtnl_link_stats64));
4724
4725         if (!bp->bnapi)
4726                 return stats;
4727
4728         /* TODO check if we need to synchronize with bnxt_close path */
4729         for (i = 0; i < bp->cp_nr_rings; i++) {
4730                 struct bnxt_napi *bnapi = bp->bnapi[i];
4731                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4732                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4733
4734                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4735                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4736                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4737
4738                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4739                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4740                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4741
4742                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4743                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4744                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4745
4746                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4747                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4748                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4749
4750                 stats->rx_missed_errors +=
4751                         le64_to_cpu(hw_stats->rx_discard_pkts);
4752
4753                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4754
4755                 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4756
4757                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4758         }
4759
4760         return stats;
4761 }
4762
4763 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4764 {
4765         struct net_device *dev = bp->dev;
4766         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4767         struct netdev_hw_addr *ha;
4768         u8 *haddr;
4769         int mc_count = 0;
4770         bool update = false;
4771         int off = 0;
4772
4773         netdev_for_each_mc_addr(ha, dev) {
4774                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4775                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4776                         vnic->mc_list_count = 0;
4777                         return false;
4778                 }
4779                 haddr = ha->addr;
4780                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4781                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4782                         update = true;
4783                 }
4784                 off += ETH_ALEN;
4785                 mc_count++;
4786         }
4787         if (mc_count)
4788                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4789
4790         if (mc_count != vnic->mc_list_count) {
4791                 vnic->mc_list_count = mc_count;
4792                 update = true;
4793         }
4794         return update;
4795 }
4796
4797 static bool bnxt_uc_list_updated(struct bnxt *bp)
4798 {
4799         struct net_device *dev = bp->dev;
4800         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4801         struct netdev_hw_addr *ha;
4802         int off = 0;
4803
4804         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4805                 return true;
4806
4807         netdev_for_each_uc_addr(ha, dev) {
4808                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4809                         return true;
4810
4811                 off += ETH_ALEN;
4812         }
4813         return false;
4814 }
4815
4816 static void bnxt_set_rx_mode(struct net_device *dev)
4817 {
4818         struct bnxt *bp = netdev_priv(dev);
4819         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4820         u32 mask = vnic->rx_mask;
4821         bool mc_update = false;
4822         bool uc_update;
4823
4824         if (!netif_running(dev))
4825                 return;
4826
4827         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4828                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4829                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4830
4831         /* Only allow PF to be in promiscuous mode */
4832         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4833                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4834
4835         uc_update = bnxt_uc_list_updated(bp);
4836
4837         if (dev->flags & IFF_ALLMULTI) {
4838                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4839                 vnic->mc_list_count = 0;
4840         } else {
4841                 mc_update = bnxt_mc_list_updated(bp, &mask);
4842         }
4843
4844         if (mask != vnic->rx_mask || uc_update || mc_update) {
4845                 vnic->rx_mask = mask;
4846
4847                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4848                 schedule_work(&bp->sp_task);
4849         }
4850 }
4851
4852 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4853 {
4854         struct net_device *dev = bp->dev;
4855         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4856         struct netdev_hw_addr *ha;
4857         int i, off = 0, rc;
4858         bool uc_update;
4859
4860         netif_addr_lock_bh(dev);
4861         uc_update = bnxt_uc_list_updated(bp);
4862         netif_addr_unlock_bh(dev);
4863
4864         if (!uc_update)
4865                 goto skip_uc;
4866
4867         mutex_lock(&bp->hwrm_cmd_lock);
4868         for (i = 1; i < vnic->uc_filter_count; i++) {
4869                 struct hwrm_cfa_l2_filter_free_input req = {0};
4870
4871                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4872                                        -1);
4873
4874                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4875
4876                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4877                                         HWRM_CMD_TIMEOUT);
4878         }
4879         mutex_unlock(&bp->hwrm_cmd_lock);
4880
4881         vnic->uc_filter_count = 1;
4882
4883         netif_addr_lock_bh(dev);
4884         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4885                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4886         } else {
4887                 netdev_for_each_uc_addr(ha, dev) {
4888                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4889                         off += ETH_ALEN;
4890                         vnic->uc_filter_count++;
4891                 }
4892         }
4893         netif_addr_unlock_bh(dev);
4894
4895         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4896                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4897                 if (rc) {
4898                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4899                                    rc);
4900                         vnic->uc_filter_count = i;
4901                         return rc;
4902                 }
4903         }
4904
4905 skip_uc:
4906         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4907         if (rc)
4908                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4909                            rc);
4910
4911         return rc;
4912 }
4913
4914 static netdev_features_t bnxt_fix_features(struct net_device *dev,
4915                                            netdev_features_t features)
4916 {
4917         return features;
4918 }
4919
4920 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
4921 {
4922         struct bnxt *bp = netdev_priv(dev);
4923         u32 flags = bp->flags;
4924         u32 changes;
4925         int rc = 0;
4926         bool re_init = false;
4927         bool update_tpa = false;
4928
4929         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
4930         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
4931                 flags |= BNXT_FLAG_GRO;
4932         if (features & NETIF_F_LRO)
4933                 flags |= BNXT_FLAG_LRO;
4934
4935         if (features & NETIF_F_HW_VLAN_CTAG_RX)
4936                 flags |= BNXT_FLAG_STRIP_VLAN;
4937
4938         if (features & NETIF_F_NTUPLE)
4939                 flags |= BNXT_FLAG_RFS;
4940
4941         changes = flags ^ bp->flags;
4942         if (changes & BNXT_FLAG_TPA) {
4943                 update_tpa = true;
4944                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
4945                     (flags & BNXT_FLAG_TPA) == 0)
4946                         re_init = true;
4947         }
4948
4949         if (changes & ~BNXT_FLAG_TPA)
4950                 re_init = true;
4951
4952         if (flags != bp->flags) {
4953                 u32 old_flags = bp->flags;
4954
4955                 bp->flags = flags;
4956
4957                 if (!netif_running(dev)) {
4958                         if (update_tpa)
4959                                 bnxt_set_ring_params(bp);
4960                         return rc;
4961                 }
4962
4963                 if (re_init) {
4964                         bnxt_close_nic(bp, false, false);
4965                         if (update_tpa)
4966                                 bnxt_set_ring_params(bp);
4967
4968                         return bnxt_open_nic(bp, false, false);
4969                 }
4970                 if (update_tpa) {
4971                         rc = bnxt_set_tpa(bp,
4972                                           (flags & BNXT_FLAG_TPA) ?
4973                                           true : false);
4974                         if (rc)
4975                                 bp->flags = old_flags;
4976                 }
4977         }
4978         return rc;
4979 }
4980
4981 static void bnxt_dbg_dump_states(struct bnxt *bp)
4982 {
4983         int i;
4984         struct bnxt_napi *bnapi;
4985         struct bnxt_tx_ring_info *txr;
4986         struct bnxt_rx_ring_info *rxr;
4987         struct bnxt_cp_ring_info *cpr;
4988
4989         for (i = 0; i < bp->cp_nr_rings; i++) {
4990                 bnapi = bp->bnapi[i];
4991                 txr = &bnapi->tx_ring;
4992                 rxr = &bnapi->rx_ring;
4993                 cpr = &bnapi->cp_ring;
4994                 if (netif_msg_drv(bp)) {
4995                         netdev_info(bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
4996                                     i, txr->tx_ring_struct.fw_ring_id,
4997                                     txr->tx_prod, txr->tx_cons);
4998                         netdev_info(bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
4999                                     i, rxr->rx_ring_struct.fw_ring_id,
5000                                     rxr->rx_prod,
5001                                     rxr->rx_agg_ring_struct.fw_ring_id,
5002                                     rxr->rx_agg_prod, rxr->rx_sw_agg_prod);
5003                         netdev_info(bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5004                                     i, cpr->cp_ring_struct.fw_ring_id,
5005                                     cpr->cp_raw_cons);
5006                 }
5007         }
5008 }
5009
5010 static void bnxt_reset_task(struct bnxt *bp)
5011 {
5012         bnxt_dbg_dump_states(bp);
5013         if (netif_running(bp->dev)) {
5014                 bnxt_close_nic(bp, false, false);
5015                 bnxt_open_nic(bp, false, false);
5016         }
5017 }
5018
5019 static void bnxt_tx_timeout(struct net_device *dev)
5020 {
5021         struct bnxt *bp = netdev_priv(dev);
5022
5023         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5024         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5025         schedule_work(&bp->sp_task);
5026 }
5027
5028 #ifdef CONFIG_NET_POLL_CONTROLLER
5029 static void bnxt_poll_controller(struct net_device *dev)
5030 {
5031         struct bnxt *bp = netdev_priv(dev);
5032         int i;
5033
5034         for (i = 0; i < bp->cp_nr_rings; i++) {
5035                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5036
5037                 disable_irq(irq->vector);
5038                 irq->handler(irq->vector, bp->bnapi[i]);
5039                 enable_irq(irq->vector);
5040         }
5041 }
5042 #endif
5043
5044 static void bnxt_timer(unsigned long data)
5045 {
5046         struct bnxt *bp = (struct bnxt *)data;
5047         struct net_device *dev = bp->dev;
5048
5049         if (!netif_running(dev))
5050                 return;
5051
5052         if (atomic_read(&bp->intr_sem) != 0)
5053                 goto bnxt_restart_timer;
5054
5055 bnxt_restart_timer:
5056         mod_timer(&bp->timer, jiffies + bp->current_interval);
5057 }
5058
5059 static void bnxt_cfg_ntp_filters(struct bnxt *);
5060
5061 static void bnxt_sp_task(struct work_struct *work)
5062 {
5063         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5064         int rc;
5065
5066         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5067         smp_mb__after_atomic();
5068         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5069                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5070                 return;
5071         }
5072
5073         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5074                 bnxt_cfg_rx_mode(bp);
5075
5076         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5077                 bnxt_cfg_ntp_filters(bp);
5078         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5079                 rc = bnxt_update_link(bp, true);
5080                 if (rc)
5081                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5082                                    rc);
5083         }
5084         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5085                 bnxt_hwrm_exec_fwd_req(bp);
5086         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5087                 bnxt_hwrm_tunnel_dst_port_alloc(
5088                         bp, bp->vxlan_port,
5089                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5090         }
5091         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5092                 bnxt_hwrm_tunnel_dst_port_free(
5093                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5094         }
5095         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5096                 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5097                  * for BNXT_STATE_IN_SP_TASK to clear.
5098                  */
5099                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5100                 rtnl_lock();
5101                 bnxt_reset_task(bp);
5102                 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5103                 rtnl_unlock();
5104         }
5105
5106         smp_mb__before_atomic();
5107         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5108 }
5109
5110 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5111 {
5112         int rc;
5113         struct bnxt *bp = netdev_priv(dev);
5114
5115         SET_NETDEV_DEV(dev, &pdev->dev);
5116
5117         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5118         rc = pci_enable_device(pdev);
5119         if (rc) {
5120                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5121                 goto init_err;
5122         }
5123
5124         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5125                 dev_err(&pdev->dev,
5126                         "Cannot find PCI device base address, aborting\n");
5127                 rc = -ENODEV;
5128                 goto init_err_disable;
5129         }
5130
5131         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5132         if (rc) {
5133                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5134                 goto init_err_disable;
5135         }
5136
5137         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5138             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5139                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5140                 goto init_err_disable;
5141         }
5142
5143         pci_set_master(pdev);
5144
5145         bp->dev = dev;
5146         bp->pdev = pdev;
5147
5148         bp->bar0 = pci_ioremap_bar(pdev, 0);
5149         if (!bp->bar0) {
5150                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5151                 rc = -ENOMEM;
5152                 goto init_err_release;
5153         }
5154
5155         bp->bar1 = pci_ioremap_bar(pdev, 2);
5156         if (!bp->bar1) {
5157                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5158                 rc = -ENOMEM;
5159                 goto init_err_release;
5160         }
5161
5162         bp->bar2 = pci_ioremap_bar(pdev, 4);
5163         if (!bp->bar2) {
5164                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5165                 rc = -ENOMEM;
5166                 goto init_err_release;
5167         }
5168
5169         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5170
5171         spin_lock_init(&bp->ntp_fltr_lock);
5172
5173         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5174         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5175
5176         bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5177         bp->coal_bufs = 20;
5178         bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5179         bp->coal_bufs_irq = 2;
5180
5181         init_timer(&bp->timer);
5182         bp->timer.data = (unsigned long)bp;
5183         bp->timer.function = bnxt_timer;
5184         bp->current_interval = BNXT_TIMER_INTERVAL;
5185
5186         clear_bit(BNXT_STATE_OPEN, &bp->state);
5187
5188         return 0;
5189
5190 init_err_release:
5191         if (bp->bar2) {
5192                 pci_iounmap(pdev, bp->bar2);
5193                 bp->bar2 = NULL;
5194         }
5195
5196         if (bp->bar1) {
5197                 pci_iounmap(pdev, bp->bar1);
5198                 bp->bar1 = NULL;
5199         }
5200
5201         if (bp->bar0) {
5202                 pci_iounmap(pdev, bp->bar0);
5203                 bp->bar0 = NULL;
5204         }
5205
5206         pci_release_regions(pdev);
5207
5208 init_err_disable:
5209         pci_disable_device(pdev);
5210
5211 init_err:
5212         return rc;
5213 }
5214
5215 /* rtnl_lock held */
5216 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5217 {
5218         struct sockaddr *addr = p;
5219         struct bnxt *bp = netdev_priv(dev);
5220         int rc = 0;
5221
5222         if (!is_valid_ether_addr(addr->sa_data))
5223                 return -EADDRNOTAVAIL;
5224
5225 #ifdef CONFIG_BNXT_SRIOV
5226         if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5227                 return -EADDRNOTAVAIL;
5228 #endif
5229
5230         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5231                 return 0;
5232
5233         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5234         if (netif_running(dev)) {
5235                 bnxt_close_nic(bp, false, false);
5236                 rc = bnxt_open_nic(bp, false, false);
5237         }
5238
5239         return rc;
5240 }
5241
5242 /* rtnl_lock held */
5243 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5244 {
5245         struct bnxt *bp = netdev_priv(dev);
5246
5247         if (new_mtu < 60 || new_mtu > 9000)
5248                 return -EINVAL;
5249
5250         if (netif_running(dev))
5251                 bnxt_close_nic(bp, false, false);
5252
5253         dev->mtu = new_mtu;
5254         bnxt_set_ring_params(bp);
5255
5256         if (netif_running(dev))
5257                 return bnxt_open_nic(bp, false, false);
5258
5259         return 0;
5260 }
5261
5262 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5263 {
5264         struct bnxt *bp = netdev_priv(dev);
5265
5266         if (tc > bp->max_tc) {
5267                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5268                            tc, bp->max_tc);
5269                 return -EINVAL;
5270         }
5271
5272         if (netdev_get_num_tc(dev) == tc)
5273                 return 0;
5274
5275         if (tc) {
5276                 int max_rx_rings, max_tx_rings;
5277
5278                 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5279                 if (bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5280                         return -ENOMEM;
5281         }
5282
5283         /* Needs to close the device and do hw resource re-allocations */
5284         if (netif_running(bp->dev))
5285                 bnxt_close_nic(bp, true, false);
5286
5287         if (tc) {
5288                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5289                 netdev_set_num_tc(dev, tc);
5290         } else {
5291                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5292                 netdev_reset_tc(dev);
5293         }
5294         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5295         bp->num_stat_ctxs = bp->cp_nr_rings;
5296
5297         if (netif_running(bp->dev))
5298                 return bnxt_open_nic(bp, true, false);
5299
5300         return 0;
5301 }
5302
5303 #ifdef CONFIG_RFS_ACCEL
5304 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5305                             struct bnxt_ntuple_filter *f2)
5306 {
5307         struct flow_keys *keys1 = &f1->fkeys;
5308         struct flow_keys *keys2 = &f2->fkeys;
5309
5310         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5311             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5312             keys1->ports.ports == keys2->ports.ports &&
5313             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5314             keys1->basic.n_proto == keys2->basic.n_proto &&
5315             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5316                 return true;
5317
5318         return false;
5319 }
5320
5321 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5322                               u16 rxq_index, u32 flow_id)
5323 {
5324         struct bnxt *bp = netdev_priv(dev);
5325         struct bnxt_ntuple_filter *fltr, *new_fltr;
5326         struct flow_keys *fkeys;
5327         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5328         int rc = 0, idx, bit_id;
5329         struct hlist_head *head;
5330
5331         if (skb->encapsulation)
5332                 return -EPROTONOSUPPORT;
5333
5334         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5335         if (!new_fltr)
5336                 return -ENOMEM;
5337
5338         fkeys = &new_fltr->fkeys;
5339         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5340                 rc = -EPROTONOSUPPORT;
5341                 goto err_free;
5342         }
5343
5344         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5345             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5346              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5347                 rc = -EPROTONOSUPPORT;
5348                 goto err_free;
5349         }
5350
5351         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5352
5353         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5354         head = &bp->ntp_fltr_hash_tbl[idx];
5355         rcu_read_lock();
5356         hlist_for_each_entry_rcu(fltr, head, hash) {
5357                 if (bnxt_fltr_match(fltr, new_fltr)) {
5358                         rcu_read_unlock();
5359                         rc = 0;
5360                         goto err_free;
5361                 }
5362         }
5363         rcu_read_unlock();
5364
5365         spin_lock_bh(&bp->ntp_fltr_lock);
5366         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5367                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
5368         if (bit_id < 0) {
5369                 spin_unlock_bh(&bp->ntp_fltr_lock);
5370                 rc = -ENOMEM;
5371                 goto err_free;
5372         }
5373
5374         new_fltr->sw_id = (u16)bit_id;
5375         new_fltr->flow_id = flow_id;
5376         new_fltr->rxq = rxq_index;
5377         hlist_add_head_rcu(&new_fltr->hash, head);
5378         bp->ntp_fltr_count++;
5379         spin_unlock_bh(&bp->ntp_fltr_lock);
5380
5381         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5382         schedule_work(&bp->sp_task);
5383
5384         return new_fltr->sw_id;
5385
5386 err_free:
5387         kfree(new_fltr);
5388         return rc;
5389 }
5390
5391 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5392 {
5393         int i;
5394
5395         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5396                 struct hlist_head *head;
5397                 struct hlist_node *tmp;
5398                 struct bnxt_ntuple_filter *fltr;
5399                 int rc;
5400
5401                 head = &bp->ntp_fltr_hash_tbl[i];
5402                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5403                         bool del = false;
5404
5405                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5406                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5407                                                         fltr->flow_id,
5408                                                         fltr->sw_id)) {
5409                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
5410                                                                          fltr);
5411                                         del = true;
5412                                 }
5413                         } else {
5414                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5415                                                                        fltr);
5416                                 if (rc)
5417                                         del = true;
5418                                 else
5419                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
5420                         }
5421
5422                         if (del) {
5423                                 spin_lock_bh(&bp->ntp_fltr_lock);
5424                                 hlist_del_rcu(&fltr->hash);
5425                                 bp->ntp_fltr_count--;
5426                                 spin_unlock_bh(&bp->ntp_fltr_lock);
5427                                 synchronize_rcu();
5428                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5429                                 kfree(fltr);
5430                         }
5431                 }
5432         }
5433 }
5434
5435 #else
5436
5437 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5438 {
5439 }
5440
5441 #endif /* CONFIG_RFS_ACCEL */
5442
5443 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5444                                 __be16 port)
5445 {
5446         struct bnxt *bp = netdev_priv(dev);
5447
5448         if (!netif_running(dev))
5449                 return;
5450
5451         if (sa_family != AF_INET6 && sa_family != AF_INET)
5452                 return;
5453
5454         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5455                 return;
5456
5457         bp->vxlan_port_cnt++;
5458         if (bp->vxlan_port_cnt == 1) {
5459                 bp->vxlan_port = port;
5460                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5461                 schedule_work(&bp->sp_task);
5462         }
5463 }
5464
5465 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5466                                 __be16 port)
5467 {
5468         struct bnxt *bp = netdev_priv(dev);
5469
5470         if (!netif_running(dev))
5471                 return;
5472
5473         if (sa_family != AF_INET6 && sa_family != AF_INET)
5474                 return;
5475
5476         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5477                 bp->vxlan_port_cnt--;
5478
5479                 if (bp->vxlan_port_cnt == 0) {
5480                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5481                         schedule_work(&bp->sp_task);
5482                 }
5483         }
5484 }
5485
5486 static const struct net_device_ops bnxt_netdev_ops = {
5487         .ndo_open               = bnxt_open,
5488         .ndo_start_xmit         = bnxt_start_xmit,
5489         .ndo_stop               = bnxt_close,
5490         .ndo_get_stats64        = bnxt_get_stats64,
5491         .ndo_set_rx_mode        = bnxt_set_rx_mode,
5492         .ndo_do_ioctl           = bnxt_ioctl,
5493         .ndo_validate_addr      = eth_validate_addr,
5494         .ndo_set_mac_address    = bnxt_change_mac_addr,
5495         .ndo_change_mtu         = bnxt_change_mtu,
5496         .ndo_fix_features       = bnxt_fix_features,
5497         .ndo_set_features       = bnxt_set_features,
5498         .ndo_tx_timeout         = bnxt_tx_timeout,
5499 #ifdef CONFIG_BNXT_SRIOV
5500         .ndo_get_vf_config      = bnxt_get_vf_config,
5501         .ndo_set_vf_mac         = bnxt_set_vf_mac,
5502         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
5503         .ndo_set_vf_rate        = bnxt_set_vf_bw,
5504         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
5505         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
5506 #endif
5507 #ifdef CONFIG_NET_POLL_CONTROLLER
5508         .ndo_poll_controller    = bnxt_poll_controller,
5509 #endif
5510         .ndo_setup_tc           = bnxt_setup_tc,
5511 #ifdef CONFIG_RFS_ACCEL
5512         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
5513 #endif
5514         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
5515         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
5516 #ifdef CONFIG_NET_RX_BUSY_POLL
5517         .ndo_busy_poll          = bnxt_busy_poll,
5518 #endif
5519 };
5520
5521 static void bnxt_remove_one(struct pci_dev *pdev)
5522 {
5523         struct net_device *dev = pci_get_drvdata(pdev);
5524         struct bnxt *bp = netdev_priv(dev);
5525
5526         if (BNXT_PF(bp))
5527                 bnxt_sriov_disable(bp);
5528
5529         unregister_netdev(dev);
5530         cancel_work_sync(&bp->sp_task);
5531         bp->sp_event = 0;
5532
5533         bnxt_hwrm_func_drv_unrgtr(bp);
5534         bnxt_free_hwrm_resources(bp);
5535         pci_iounmap(pdev, bp->bar2);
5536         pci_iounmap(pdev, bp->bar1);
5537         pci_iounmap(pdev, bp->bar0);
5538         free_netdev(dev);
5539
5540         pci_release_regions(pdev);
5541         pci_disable_device(pdev);
5542 }
5543
5544 static int bnxt_probe_phy(struct bnxt *bp)
5545 {
5546         int rc = 0;
5547         struct bnxt_link_info *link_info = &bp->link_info;
5548         char phy_ver[PHY_VER_STR_LEN];
5549
5550         rc = bnxt_update_link(bp, false);
5551         if (rc) {
5552                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5553                            rc);
5554                 return rc;
5555         }
5556
5557         /*initialize the ethool setting copy with NVM settings */
5558         if (BNXT_AUTO_MODE(link_info->auto_mode))
5559                 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5560
5561         if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5562                 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5563                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5564                 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5565         } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5566                 link_info->req_flow_ctrl = link_info->force_pause_setting;
5567         }
5568         link_info->req_duplex = link_info->duplex_setting;
5569         if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5570                 link_info->req_link_speed = link_info->auto_link_speed;
5571         else
5572                 link_info->req_link_speed = link_info->force_link_speed;
5573         link_info->advertising = link_info->auto_link_speeds;
5574         snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5575                  link_info->phy_ver[0],
5576                  link_info->phy_ver[1],
5577                  link_info->phy_ver[2]);
5578         strcat(bp->fw_ver_str, phy_ver);
5579         return rc;
5580 }
5581
5582 static int bnxt_get_max_irq(struct pci_dev *pdev)
5583 {
5584         u16 ctrl;
5585
5586         if (!pdev->msix_cap)
5587                 return 1;
5588
5589         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5590         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5591 }
5592
5593 void bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx)
5594 {
5595         int max_rings = 0;
5596
5597         if (BNXT_PF(bp)) {
5598                 *max_tx = bp->pf.max_pf_tx_rings;
5599                 *max_rx = bp->pf.max_pf_rx_rings;
5600                 max_rings = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5601                 max_rings = min_t(int, max_rings, bp->pf.max_stat_ctxs);
5602         } else {
5603 #ifdef CONFIG_BNXT_SRIOV
5604                 *max_tx = bp->vf.max_tx_rings;
5605                 *max_rx = bp->vf.max_rx_rings;
5606                 max_rings = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5607                 max_rings = min_t(int, max_rings, bp->vf.max_stat_ctxs);
5608 #endif
5609         }
5610         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5611                 *max_rx >>= 1;
5612
5613         *max_rx = min_t(int, *max_rx, max_rings);
5614         *max_tx = min_t(int, *max_tx, max_rings);
5615 }
5616
5617 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5618 {
5619         static int version_printed;
5620         struct net_device *dev;
5621         struct bnxt *bp;
5622         int rc, max_rx_rings, max_tx_rings, max_irqs, dflt_rings;
5623
5624         if (version_printed++ == 0)
5625                 pr_info("%s", version);
5626
5627         max_irqs = bnxt_get_max_irq(pdev);
5628         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5629         if (!dev)
5630                 return -ENOMEM;
5631
5632         bp = netdev_priv(dev);
5633
5634         if (bnxt_vf_pciid(ent->driver_data))
5635                 bp->flags |= BNXT_FLAG_VF;
5636
5637         if (pdev->msix_cap) {
5638                 bp->flags |= BNXT_FLAG_MSIX_CAP;
5639                 if (BNXT_PF(bp))
5640                         bp->flags |= BNXT_FLAG_RFS;
5641         }
5642
5643         rc = bnxt_init_board(pdev, dev);
5644         if (rc < 0)
5645                 goto init_err_free;
5646
5647         dev->netdev_ops = &bnxt_netdev_ops;
5648         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5649         dev->ethtool_ops = &bnxt_ethtool_ops;
5650
5651         pci_set_drvdata(pdev, dev);
5652
5653         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5654                            NETIF_F_TSO | NETIF_F_TSO6 |
5655                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5656                            NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5657                            NETIF_F_RXHASH |
5658                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5659
5660         if (bp->flags & BNXT_FLAG_RFS)
5661                 dev->hw_features |= NETIF_F_NTUPLE;
5662
5663         dev->hw_enc_features =
5664                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5665                         NETIF_F_TSO | NETIF_F_TSO6 |
5666                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5667                         NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5668         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5669         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5670                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5671         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5672         dev->priv_flags |= IFF_UNICAST_FLT;
5673
5674 #ifdef CONFIG_BNXT_SRIOV
5675         init_waitqueue_head(&bp->sriov_cfg_wait);
5676 #endif
5677         rc = bnxt_alloc_hwrm_resources(bp);
5678         if (rc)
5679                 goto init_err;
5680
5681         mutex_init(&bp->hwrm_cmd_lock);
5682         bnxt_hwrm_ver_get(bp);
5683
5684         rc = bnxt_hwrm_func_drv_rgtr(bp);
5685         if (rc)
5686                 goto init_err;
5687
5688         /* Get the MAX capabilities for this function */
5689         rc = bnxt_hwrm_func_qcaps(bp);
5690         if (rc) {
5691                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5692                            rc);
5693                 rc = -1;
5694                 goto init_err;
5695         }
5696
5697         rc = bnxt_hwrm_queue_qportcfg(bp);
5698         if (rc) {
5699                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5700                            rc);
5701                 rc = -1;
5702                 goto init_err;
5703         }
5704
5705         bnxt_set_tpa_flags(bp);
5706         bnxt_set_ring_params(bp);
5707         dflt_rings = netif_get_num_default_rss_queues();
5708         if (BNXT_PF(bp))
5709                 bp->pf.max_irqs = max_irqs;
5710 #if defined(CONFIG_BNXT_SRIOV)
5711         else
5712                 bp->vf.max_irqs = max_irqs;
5713 #endif
5714         bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings);
5715         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5716         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5717         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5718         bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
5719         bp->num_stat_ctxs = bp->cp_nr_rings;
5720
5721         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5722                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5723
5724         rc = bnxt_probe_phy(bp);
5725         if (rc)
5726                 goto init_err;
5727
5728         rc = register_netdev(dev);
5729         if (rc)
5730                 goto init_err;
5731
5732         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5733                     board_info[ent->driver_data].name,
5734                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
5735
5736         return 0;
5737
5738 init_err:
5739         pci_iounmap(pdev, bp->bar0);
5740         pci_release_regions(pdev);
5741         pci_disable_device(pdev);
5742
5743 init_err_free:
5744         free_netdev(dev);
5745         return rc;
5746 }
5747
5748 static struct pci_driver bnxt_pci_driver = {
5749         .name           = DRV_MODULE_NAME,
5750         .id_table       = bnxt_pci_tbl,
5751         .probe          = bnxt_init_one,
5752         .remove         = bnxt_remove_one,
5753 #if defined(CONFIG_BNXT_SRIOV)
5754         .sriov_configure = bnxt_sriov_configure,
5755 #endif
5756 };
5757
5758 module_pci_driver(bnxt_pci_driver);