1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 #define DRV_MODULE_NAME "bnxt_en"
14 #define DRV_MODULE_VERSION "1.6.0"
21 __le32 tx_bd_len_flags_type;
22 #define TX_BD_TYPE (0x3f << 0)
23 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
24 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
25 #define TX_BD_FLAGS_PACKET_END (1 << 6)
26 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
27 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
28 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
29 #define TX_BD_FLAGS_LHINT (3 << 13)
30 #define TX_BD_FLAGS_LHINT_SHIFT 13
31 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
32 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
33 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
34 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
35 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
36 #define TX_BD_LEN (0xffff << 16)
37 #define TX_BD_LEN_SHIFT 16
44 __le32 tx_bd_hsize_lflags;
45 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
46 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
47 #define TX_BD_FLAGS_NO_CRC (1 << 2)
48 #define TX_BD_FLAGS_STAMP (1 << 3)
49 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
50 #define TX_BD_FLAGS_LSO (1 << 5)
51 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
52 #define TX_BD_FLAGS_T_IPID (1 << 7)
53 #define TX_BD_HSIZE (0xff << 16)
54 #define TX_BD_HSIZE_SHIFT 16
57 __le32 tx_bd_cfa_action;
58 #define TX_BD_CFA_ACTION (0xffff << 16)
59 #define TX_BD_CFA_ACTION_SHIFT 16
61 __le32 tx_bd_cfa_meta;
62 #define TX_BD_CFA_META_MASK 0xfffffff
63 #define TX_BD_CFA_META_VID_MASK 0xfff
64 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
65 #define TX_BD_CFA_META_PRI_SHIFT 12
66 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
67 #define TX_BD_CFA_META_TPID_SHIFT 16
68 #define TX_BD_CFA_META_KEY (0xf << 28)
69 #define TX_BD_CFA_META_KEY_SHIFT 28
70 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
74 __le32 rx_bd_len_flags_type;
75 #define RX_BD_TYPE (0x3f << 0)
76 #define RX_BD_TYPE_RX_PACKET_BD 0x4
77 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
78 #define RX_BD_TYPE_RX_AGG_BD 0x6
79 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
80 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
81 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
82 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
83 #define RX_BD_FLAGS_SOP (1 << 6)
84 #define RX_BD_FLAGS_EOP (1 << 7)
85 #define RX_BD_FLAGS_BUFFERS (3 << 8)
86 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
87 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
88 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
89 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
90 #define RX_BD_LEN (0xffff << 16)
91 #define RX_BD_LEN_SHIFT 16
98 __le32 tx_cmp_flags_type;
99 #define CMP_TYPE (0x3f << 0)
100 #define CMP_TYPE_TX_L2_CMP 0
101 #define CMP_TYPE_RX_L2_CMP 17
102 #define CMP_TYPE_RX_AGG_CMP 18
103 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
104 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
105 #define CMP_TYPE_STATUS_CMP 32
106 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
107 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
108 #define CMP_TYPE_ERROR_STATUS 48
109 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
110 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
111 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
112 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
113 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
115 #define TX_CMP_FLAGS_ERROR (1 << 6)
116 #define TX_CMP_FLAGS_PUSH (1 << 7)
119 __le32 tx_cmp_errors_v;
120 #define TX_CMP_V (1 << 0)
121 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
122 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
123 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
124 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
125 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
126 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
127 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
128 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
129 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
131 __le32 tx_cmp_unsed_3;
135 __le32 rx_cmp_len_flags_type;
136 #define RX_CMP_CMP_TYPE (0x3f << 0)
137 #define RX_CMP_FLAGS_ERROR (1 << 6)
138 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
139 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
140 #define RX_CMP_FLAGS_UNUSED (1 << 11)
141 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
142 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
143 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
144 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
145 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
146 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
147 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
148 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
149 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
150 #define RX_CMP_LEN (0xffff << 16)
151 #define RX_CMP_LEN_SHIFT 16
154 __le32 rx_cmp_misc_v1;
155 #define RX_CMP_V1 (1 << 0)
156 #define RX_CMP_AGG_BUFS (0x1f << 1)
157 #define RX_CMP_AGG_BUFS_SHIFT 1
158 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
159 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
160 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
161 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
163 __le32 rx_cmp_rss_hash;
166 #define RX_CMP_HASH_VALID(rxcmp) \
167 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
169 #define RSS_PROFILE_ID_MASK 0x1f
171 #define RX_CMP_HASH_TYPE(rxcmp) \
172 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
173 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
176 __le32 rx_cmp_flags2;
177 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
178 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
179 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
180 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
181 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
182 __le32 rx_cmp_meta_data;
183 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
184 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
185 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
186 __le32 rx_cmp_cfa_code_errors_v2;
187 #define RX_CMP_V (1 << 0)
188 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
189 #define RX_CMPL_ERRORS_SFT 1
190 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
191 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
192 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
193 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
194 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
195 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
196 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
197 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
198 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
199 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
200 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
201 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
202 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
203 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
204 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
205 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
206 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
207 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
208 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
209 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
210 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
211 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
212 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
213 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
214 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
215 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
216 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
217 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
219 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
220 #define RX_CMPL_CFA_CODE_SFT 16
222 __le32 rx_cmp_unused3;
225 #define RX_CMP_L2_ERRORS \
226 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
228 #define RX_CMP_L4_CS_BITS \
229 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
231 #define RX_CMP_L4_CS_ERR_BITS \
232 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
234 #define RX_CMP_L4_CS_OK(rxcmp1) \
235 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
236 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
238 #define RX_CMP_ENCAP(rxcmp1) \
239 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
240 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
243 __le32 rx_agg_cmp_len_flags_type;
244 #define RX_AGG_CMP_TYPE (0x3f << 0)
245 #define RX_AGG_CMP_LEN (0xffff << 16)
246 #define RX_AGG_CMP_LEN_SHIFT 16
247 u32 rx_agg_cmp_opaque;
249 #define RX_AGG_CMP_V (1 << 0)
250 __le32 rx_agg_cmp_unused;
253 struct rx_tpa_start_cmp {
254 __le32 rx_tpa_start_cmp_len_flags_type;
255 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
256 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
257 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
258 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
259 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
260 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
261 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
262 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
263 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
264 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
265 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
266 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
267 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
268 #define RX_TPA_START_CMP_LEN (0xffff << 16)
269 #define RX_TPA_START_CMP_LEN_SHIFT 16
271 u32 rx_tpa_start_cmp_opaque;
272 __le32 rx_tpa_start_cmp_misc_v1;
273 #define RX_TPA_START_CMP_V1 (0x1 << 0)
274 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
275 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
276 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
277 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
279 __le32 rx_tpa_start_cmp_rss_hash;
282 #define TPA_START_HASH_VALID(rx_tpa_start) \
283 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
284 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
286 #define TPA_START_HASH_TYPE(rx_tpa_start) \
287 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
288 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
289 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
291 #define TPA_START_AGG_ID(rx_tpa_start) \
292 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
293 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
295 struct rx_tpa_start_cmp_ext {
296 __le32 rx_tpa_start_cmp_flags2;
297 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
298 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
299 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
300 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
301 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
303 __le32 rx_tpa_start_cmp_metadata;
304 __le32 rx_tpa_start_cmp_cfa_code_v2;
305 #define RX_TPA_START_CMP_V2 (0x1 << 0)
306 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
307 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
308 __le32 rx_tpa_start_cmp_hdr_info;
311 struct rx_tpa_end_cmp {
312 __le32 rx_tpa_end_cmp_len_flags_type;
313 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
314 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
315 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
316 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
317 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
318 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
319 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
320 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
321 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
322 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
323 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
324 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
325 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
326 #define RX_TPA_END_CMP_LEN (0xffff << 16)
327 #define RX_TPA_END_CMP_LEN_SHIFT 16
329 u32 rx_tpa_end_cmp_opaque;
330 __le32 rx_tpa_end_cmp_misc_v1;
331 #define RX_TPA_END_CMP_V1 (0x1 << 0)
332 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
333 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
334 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
335 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
336 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
337 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
338 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
339 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
341 __le32 rx_tpa_end_cmp_tsdelta;
342 #define RX_TPA_END_GRO_TS (0x1 << 31)
345 #define TPA_END_AGG_ID(rx_tpa_end) \
346 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
347 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
349 #define TPA_END_TPA_SEGS(rx_tpa_end) \
350 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
351 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
353 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
354 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
355 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
357 #define TPA_END_GRO(rx_tpa_end) \
358 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
359 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
361 #define TPA_END_GRO_TS(rx_tpa_end) \
362 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
363 cpu_to_le32(RX_TPA_END_GRO_TS)))
365 struct rx_tpa_end_cmp_ext {
366 __le32 rx_tpa_end_cmp_dup_acks;
367 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
369 __le32 rx_tpa_end_cmp_seg_len;
370 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
372 __le32 rx_tpa_end_cmp_errors_v2;
373 #define RX_TPA_END_CMP_V2 (0x1 << 0)
374 #define RX_TPA_END_CMP_ERRORS (0x7fff << 1)
375 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
377 u32 rx_tpa_end_cmp_start_opaque;
380 #define DB_IDX_MASK 0xffffff
381 #define DB_IDX_VALID (0x1 << 26)
382 #define DB_IRQ_DIS (0x1 << 27)
383 #define DB_KEY_TX (0x0 << 28)
384 #define DB_KEY_RX (0x1 << 28)
385 #define DB_KEY_CP (0x2 << 28)
386 #define DB_KEY_ST (0x3 << 28)
387 #define DB_KEY_TX_PUSH (0x4 << 28)
388 #define DB_LONG_TX_PUSH (0x2 << 24)
390 #define BNXT_MIN_ROCE_CP_RINGS 2
391 #define BNXT_MIN_ROCE_STAT_CTXS 1
393 #define INVALID_HW_RING_ID ((u16)-1)
395 /* The hardware supports certain page sizes. Use the supported page sizes
396 * to allocate the rings.
398 #if (PAGE_SHIFT < 12)
399 #define BNXT_PAGE_SHIFT 12
400 #elif (PAGE_SHIFT <= 13)
401 #define BNXT_PAGE_SHIFT PAGE_SHIFT
402 #elif (PAGE_SHIFT < 16)
403 #define BNXT_PAGE_SHIFT 13
405 #define BNXT_PAGE_SHIFT 16
408 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
410 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
411 #if (PAGE_SHIFT > 15)
412 #define BNXT_RX_PAGE_SHIFT 15
414 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
417 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
419 #define BNXT_MAX_MTU 9500
420 #define BNXT_MAX_PAGE_MODE_MTU \
421 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
424 #define BNXT_MIN_PKT_SIZE 52
426 #define BNXT_NUM_TESTS(bp) 0
428 #define BNXT_DEFAULT_RX_RING_SIZE 511
429 #define BNXT_DEFAULT_TX_RING_SIZE 511
433 #if (BNXT_PAGE_SHIFT == 16)
434 #define MAX_RX_PAGES 1
435 #define MAX_RX_AGG_PAGES 4
436 #define MAX_TX_PAGES 1
437 #define MAX_CP_PAGES 8
439 #define MAX_RX_PAGES 8
440 #define MAX_RX_AGG_PAGES 32
441 #define MAX_TX_PAGES 8
442 #define MAX_CP_PAGES 64
445 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
446 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
447 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
449 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
450 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
452 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
454 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
455 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
457 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
459 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
460 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
461 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
463 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
464 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
466 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
467 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
469 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
470 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
472 #define TX_CMP_VALID(txcmp, raw_cons) \
473 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
474 !((raw_cons) & bp->cp_bit))
476 #define RX_CMP_VALID(rxcmp1, raw_cons) \
477 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
478 !((raw_cons) & bp->cp_bit))
480 #define RX_AGG_CMP_VALID(agg, raw_cons) \
481 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
482 !((raw_cons) & bp->cp_bit))
484 #define TX_CMP_TYPE(txcmp) \
485 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
487 #define RX_CMP_TYPE(rxcmp) \
488 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
490 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
492 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
494 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
496 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
497 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
498 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
499 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
501 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
502 #define DFLT_HWRM_CMD_TIMEOUT 500
503 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
504 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
505 #define HWRM_RESP_ERR_CODE_MASK 0xffff
506 #define HWRM_RESP_LEN_OFFSET 4
507 #define HWRM_RESP_LEN_MASK 0xffff0000
508 #define HWRM_RESP_LEN_SFT 16
509 #define HWRM_RESP_VALID_MASK 0xff000000
510 #define HWRM_SEQ_ID_INVALID -1
511 #define BNXT_HWRM_REQ_MAX_SIZE 128
512 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
513 BNXT_HWRM_REQ_MAX_SIZE)
515 #define BNXT_RX_EVENT 1
516 #define BNXT_AGG_EVENT 2
518 struct bnxt_sw_tx_bd {
520 DEFINE_DMA_UNMAP_ADDR(mapping);
523 unsigned short nr_frags;
526 struct bnxt_sw_rx_bd {
532 struct bnxt_sw_rx_agg_bd {
538 struct bnxt_ring_struct {
545 dma_addr_t pg_tbl_map;
550 u16 fw_ring_id; /* Ring id filled by Chimp FW */
556 __le32 tx_bd_len_flags_type;
558 struct tx_bd_ext txbd2;
561 struct tx_push_buffer {
562 struct tx_push_bd push_bd;
566 struct bnxt_tx_ring_info {
567 struct bnxt_napi *bnapi;
571 void __iomem *tx_doorbell;
573 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
574 struct bnxt_sw_tx_bd *tx_buf_ring;
576 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
578 struct tx_push_buffer *tx_push;
579 dma_addr_t tx_push_mapping;
582 #define BNXT_DEV_STATE_CLOSING 0x1
585 struct bnxt_ring_struct tx_ring_struct;
588 struct bnxt_tpa_info {
593 unsigned short gso_type;
596 enum pkt_hash_types hash_type;
600 #define BNXT_TPA_L4_SIZE(hdr_info) \
601 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
603 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
604 (((hdr_info) >> 18) & 0x1ff)
606 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
607 (((hdr_info) >> 9) & 0x1ff)
609 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
613 struct bnxt_rx_ring_info {
614 struct bnxt_napi *bnapi;
619 void __iomem *rx_doorbell;
620 void __iomem *rx_agg_doorbell;
622 struct bpf_prog *xdp_prog;
624 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
625 struct bnxt_sw_rx_bd *rx_buf_ring;
627 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
628 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
630 unsigned long *rx_agg_bmap;
631 u16 rx_agg_bmap_size;
633 struct page *rx_page;
634 unsigned int rx_page_offset;
636 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
637 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
639 struct bnxt_tpa_info *rx_tpa;
641 struct bnxt_ring_struct rx_ring_struct;
642 struct bnxt_ring_struct rx_agg_ring_struct;
645 struct bnxt_cp_ring_info {
647 void __iomem *cp_doorbell;
649 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
651 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
653 struct ctx_hw_stats *hw_stats;
654 dma_addr_t hw_stats_map;
656 u64 rx_l4_csum_errors;
658 struct bnxt_ring_struct cp_ring_struct;
662 struct napi_struct napi;
666 struct bnxt_cp_ring_info cp_ring;
667 struct bnxt_rx_ring_info *rx_ring;
668 struct bnxt_tx_ring_info *tx_ring;
670 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
673 #define BNXT_NAPI_FLAG_XDP 0x1
679 irq_handler_t handler;
682 char name[IFNAMSIZ + 2];
685 #define HWRM_RING_ALLOC_TX 0x1
686 #define HWRM_RING_ALLOC_RX 0x2
687 #define HWRM_RING_ALLOC_AGG 0x4
688 #define HWRM_RING_ALLOC_CMPL 0x8
690 #define INVALID_STATS_CTX_ID -1
692 struct bnxt_ring_grp_info {
700 struct bnxt_vnic_info {
701 u16 fw_vnic_id; /* returned by Chimp during alloc */
702 #define BNXT_MAX_CTX_PER_VNIC 2
703 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
705 #define BNXT_MAX_UC_ADDRS 4
706 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
707 /* index 0 always dev_addr */
712 dma_addr_t rss_table_dma_addr;
714 dma_addr_t rss_hash_key_dma_addr;
721 dma_addr_t mc_list_mapping;
722 #define BNXT_MAX_MC_ADDRS 16
725 #define BNXT_VNIC_RSS_FLAG 1
726 #define BNXT_VNIC_RFS_FLAG 2
727 #define BNXT_VNIC_MCAST_FLAG 4
728 #define BNXT_VNIC_UCAST_FLAG 8
729 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
732 #if defined(CONFIG_BNXT_SRIOV)
733 struct bnxt_vf_info {
735 u8 mac_addr[ETH_ALEN];
740 u16 max_hw_ring_grps;
747 #define BNXT_VF_QOS 0x1
748 #define BNXT_VF_SPOOFCHK 0x2
749 #define BNXT_VF_LINK_FORCED 0x4
750 #define BNXT_VF_LINK_UP 0x8
751 u32 func_flags; /* func cfg flags */
754 void *hwrm_cmd_req_addr;
755 dma_addr_t hwrm_cmd_req_dma_addr;
759 struct bnxt_pf_info {
760 #define BNXT_FIRST_PF_FID 1
761 #define BNXT_FIRST_VF_FID 128
764 u8 mac_addr[ETH_ALEN];
767 u16 max_tx_rings; /* HW assigned max tx rings for this PF */
768 u16 max_rx_rings; /* HW assigned max rx rings for this PF */
769 u16 max_hw_ring_grps;
777 u32 max_encap_records;
778 u32 max_decap_records;
783 unsigned long *vf_event_bmap;
784 u16 hwrm_cmd_req_pages;
785 void *hwrm_cmd_req_addr[4];
786 dma_addr_t hwrm_cmd_req_dma_addr[4];
787 struct bnxt_vf_info *vf;
790 struct bnxt_ntuple_filter {
791 struct hlist_node hash;
792 u8 dst_mac_addr[ETH_ALEN];
793 u8 src_mac_addr[ETH_ALEN];
794 struct flow_keys fkeys;
801 #define BNXT_FLTR_VALID 0
802 #define BNXT_FLTR_UPDATE 1
805 struct bnxt_link_info {
811 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
812 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
813 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
818 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF
819 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL
821 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
822 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
823 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
824 PORT_PHY_QCFG_RESP_PAUSE_TX)
826 u8 auto_pause_setting;
827 u8 force_pause_setting;
830 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
831 (mode) <= BNXT_LINK_AUTO_MSK)
832 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
833 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
834 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
835 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
836 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
837 #define PHY_VER_LEN 3
838 u8 phy_ver[PHY_VER_LEN];
840 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
841 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
842 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
843 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
844 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
845 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
846 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
847 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
848 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
850 u16 auto_link_speeds; /* fw adv setting */
851 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
852 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
853 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
854 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
855 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
856 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
857 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
858 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
859 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
860 u16 support_auto_speeds;
861 u16 lp_auto_link_speeds;
862 u16 force_link_speed;
866 /* copy of requested setting from ethtool cmd */
868 #define BNXT_AUTONEG_SPEED 1
869 #define BNXT_AUTONEG_FLOW_CTRL 2
873 u16 advertising; /* user adv setting */
874 bool force_link_chng;
876 /* a copy of phy_qcfg output used to report link
879 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
882 #define BNXT_MAX_QUEUE 8
884 struct bnxt_queue_info {
889 #define BNXT_MAX_LED 4
891 struct bnxt_led_info {
896 __le16 led_state_caps;
897 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
898 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
900 __le16 led_color_caps;
903 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
904 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
905 #define BNXT_CAG_REG_BASE 0x300000
914 #define CHIP_NUM_57301 0x16c8
915 #define CHIP_NUM_57302 0x16c9
916 #define CHIP_NUM_57304 0x16ca
917 #define CHIP_NUM_58700 0x16cd
918 #define CHIP_NUM_57402 0x16d0
919 #define CHIP_NUM_57404 0x16d1
920 #define CHIP_NUM_57406 0x16d2
922 #define CHIP_NUM_57311 0x16ce
923 #define CHIP_NUM_57312 0x16cf
924 #define CHIP_NUM_57314 0x16df
925 #define CHIP_NUM_57412 0x16d6
926 #define CHIP_NUM_57414 0x16d7
927 #define CHIP_NUM_57416 0x16d8
928 #define CHIP_NUM_57417 0x16d9
930 #define BNXT_CHIP_NUM_5730X(chip_num) \
931 ((chip_num) >= CHIP_NUM_57301 && \
932 (chip_num) <= CHIP_NUM_57304)
934 #define BNXT_CHIP_NUM_5740X(chip_num) \
935 ((chip_num) >= CHIP_NUM_57402 && \
936 (chip_num) <= CHIP_NUM_57406)
938 #define BNXT_CHIP_NUM_5731X(chip_num) \
939 ((chip_num) == CHIP_NUM_57311 || \
940 (chip_num) == CHIP_NUM_57312 || \
941 (chip_num) == CHIP_NUM_57314)
943 #define BNXT_CHIP_NUM_5741X(chip_num) \
944 ((chip_num) >= CHIP_NUM_57412 && \
945 (chip_num) <= CHIP_NUM_57417)
947 #define BNXT_CHIP_NUM_57X0X(chip_num) \
948 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
950 #define BNXT_CHIP_NUM_57X1X(chip_num) \
951 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
953 struct net_device *dev;
954 struct pci_dev *pdev;
959 #define BNXT_FLAG_DCB_ENABLED 0x1
960 #define BNXT_FLAG_VF 0x2
961 #define BNXT_FLAG_LRO 0x4
963 #define BNXT_FLAG_GRO 0x8
965 /* Cannot support hardware GRO if CONFIG_INET is not set */
966 #define BNXT_FLAG_GRO 0x0
968 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
969 #define BNXT_FLAG_JUMBO 0x10
970 #define BNXT_FLAG_STRIP_VLAN 0x20
971 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
973 #define BNXT_FLAG_USING_MSIX 0x40
974 #define BNXT_FLAG_MSIX_CAP 0x80
975 #define BNXT_FLAG_RFS 0x100
976 #define BNXT_FLAG_SHARED_RINGS 0x200
977 #define BNXT_FLAG_PORT_STATS 0x400
978 #define BNXT_FLAG_UDP_RSS_CAP 0x800
979 #define BNXT_FLAG_EEE_CAP 0x1000
980 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
981 #define BNXT_FLAG_ROCEV1_CAP 0x8000
982 #define BNXT_FLAG_ROCEV2_CAP 0x10000
983 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
984 BNXT_FLAG_ROCEV2_CAP)
985 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
986 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
987 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
989 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
991 BNXT_FLAG_STRIP_VLAN)
993 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
994 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
995 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
996 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp))
997 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
998 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1000 struct bnxt_en_dev *edev;
1001 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1003 struct bnxt_napi **bnapi;
1005 struct bnxt_rx_ring_info *rx_ring;
1006 struct bnxt_tx_ring_info *tx_ring;
1009 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1012 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1013 struct bnxt_rx_ring_info *,
1014 u16, void *, u8 *, dma_addr_t,
1018 u32 rx_buf_use_size; /* useable size */
1021 enum dma_data_direction rx_dir;
1023 u32 rx_agg_ring_size;
1026 u32 rx_agg_ring_mask;
1028 int rx_agg_nr_pages;
1036 int tx_nr_rings_per_tc;
1037 int tx_nr_rings_xdp;
1051 /* grp_info indexed by completion ring index */
1052 struct bnxt_ring_grp_info *grp_info;
1053 struct bnxt_vnic_info *vnic_info;
1058 u8 max_lltc; /* lossless TCs */
1059 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1061 unsigned int current_interval;
1062 #define BNXT_TIMER_INTERVAL HZ
1064 struct timer_list timer;
1066 unsigned long state;
1067 #define BNXT_STATE_OPEN 0
1068 #define BNXT_STATE_IN_SP_TASK 1
1070 struct bnxt_irq *irq_tbl;
1072 u8 mac_addr[ETH_ALEN];
1074 #ifdef CONFIG_BNXT_DCB
1075 struct ieee_pfc *ieee_pfc;
1076 struct ieee_ets *ieee_ets;
1079 #endif /* CONFIG_BNXT_DCB */
1085 u32 hwrm_intr_seq_id;
1086 void *hwrm_cmd_resp_addr;
1087 dma_addr_t hwrm_cmd_resp_dma_addr;
1088 void *hwrm_dbg_resp_addr;
1089 dma_addr_t hwrm_dbg_resp_dma_addr;
1090 #define HWRM_DBG_REG_BUF_SIZE 128
1092 struct rx_port_stats *hw_rx_port_stats;
1093 struct tx_port_stats *hw_tx_port_stats;
1094 dma_addr_t hw_rx_port_stats_map;
1095 dma_addr_t hw_tx_port_stats_map;
1096 int hw_port_stats_size;
1098 u16 hwrm_max_req_len;
1099 int hwrm_cmd_timeout;
1100 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1101 struct hwrm_ver_get_output ver_resp;
1102 #define FW_VER_STR_LEN 32
1103 #define BC_HWRM_STR_LEN 21
1104 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1105 char fw_ver_str[FW_VER_STR_LEN];
1108 __le16 vxlan_fw_dst_port_id;
1111 __le16 nge_fw_dst_port_id;
1112 u8 port_partition_type;
1115 u16 rx_coal_ticks_irq;
1117 u16 rx_coal_bufs_irq;
1119 u16 tx_coal_ticks_irq;
1121 u16 tx_coal_bufs_irq;
1123 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1125 u32 stats_coal_ticks;
1126 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1127 #define BNXT_MIN_STATS_COAL_TICKS 250000
1128 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1130 struct work_struct sp_task;
1131 unsigned long sp_event;
1132 #define BNXT_RX_MASK_SP_EVENT 0
1133 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1134 #define BNXT_LINK_CHNG_SP_EVENT 2
1135 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1136 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1137 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1138 #define BNXT_RESET_TASK_SP_EVENT 6
1139 #define BNXT_RST_RING_SP_EVENT 7
1140 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1141 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1142 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1143 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1144 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1145 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1146 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1148 struct bnxt_pf_info pf;
1149 #ifdef CONFIG_BNXT_SRIOV
1151 struct bnxt_vf_info vf;
1152 wait_queue_head_t sriov_cfg_wait;
1154 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1157 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1158 #define BNXT_NTP_FLTR_HASH_SIZE 512
1159 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1160 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1161 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1163 unsigned long *ntp_fltr_bmap;
1166 struct bnxt_link_info link_info;
1167 struct ethtool_eee eee;
1172 struct bnxt_led_info leds[BNXT_MAX_LED];
1174 struct bpf_prog *xdp_prog;
1177 #define BNXT_RX_STATS_OFFSET(counter) \
1178 (offsetof(struct rx_port_stats, counter) / 8)
1180 #define BNXT_TX_STATS_OFFSET(counter) \
1181 ((offsetof(struct tx_port_stats, counter) + \
1182 sizeof(struct rx_port_stats) + 512) / 8)
1184 #define I2C_DEV_ADDR_A0 0xa0
1185 #define I2C_DEV_ADDR_A2 0xa2
1186 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
1187 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1
1188 #define SFF_MODULE_ID_SFP 0x3
1189 #define SFF_MODULE_ID_QSFP 0xc
1190 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1191 #define SFF_MODULE_ID_QSFP28 0x11
1192 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1194 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1195 void bnxt_set_tpa_flags(struct bnxt *bp);
1196 void bnxt_set_ring_params(struct bnxt *);
1197 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1198 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1199 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1200 int hwrm_send_message(struct bnxt *, void *, u32, int);
1201 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1202 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1204 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1205 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1206 int bnxt_hwrm_set_coal(struct bnxt *);
1207 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1208 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1209 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1210 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max);
1211 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max);
1212 void bnxt_tx_disable(struct bnxt *bp);
1213 void bnxt_tx_enable(struct bnxt *bp);
1214 int bnxt_hwrm_set_pause(struct bnxt *);
1215 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1216 int bnxt_hwrm_fw_set_time(struct bnxt *);
1217 int bnxt_open_nic(struct bnxt *, bool, bool);
1218 int bnxt_close_nic(struct bnxt *, bool, bool);
1219 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp);
1220 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1221 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1222 void bnxt_restore_pf_fw_resources(struct bnxt *bp);