2 * Broadcom GENET MDIO routines
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <linux/platform_data/bcmgenet.h>
30 /* read a value from the MII */
31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
34 struct net_device *dev = bus->priv;
35 struct bcmgenet_priv *priv = netdev_priv(dev);
38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
40 /* Start MDIO transaction*/
41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
42 reg |= MDIO_START_BUSY;
43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
44 wait_event_timeout(priv->wq,
45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
50 /* Some broken devices are known not to release the line during
51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
52 * that condition here and ignore the MDIO controller read failure
55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
61 /* write a value to the MII */
62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
63 int location, u16 val)
65 struct net_device *dev = bus->priv;
66 struct bcmgenet_priv *priv = netdev_priv(dev);
69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
70 (location << MDIO_REG_SHIFT) | (0xffff & val)),
72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
73 reg |= MDIO_START_BUSY;
74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
75 wait_event_timeout(priv->wq,
76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
83 /* setup netdev link state when PHY link status change and
84 * update UMAC and RGMII block when link up
86 void bcmgenet_mii_setup(struct net_device *dev)
88 struct bcmgenet_priv *priv = netdev_priv(dev);
89 struct phy_device *phydev = priv->phydev;
90 u32 reg, cmd_bits = 0;
91 bool status_changed = false;
93 if (priv->old_link != phydev->link) {
94 status_changed = true;
95 priv->old_link = phydev->link;
99 /* check speed/duplex/pause changes */
100 if (priv->old_speed != phydev->speed) {
101 status_changed = true;
102 priv->old_speed = phydev->speed;
105 if (priv->old_duplex != phydev->duplex) {
106 status_changed = true;
107 priv->old_duplex = phydev->duplex;
110 if (priv->old_pause != phydev->pause) {
111 status_changed = true;
112 priv->old_pause = phydev->pause;
115 /* done if nothing has changed */
120 if (phydev->speed == SPEED_1000)
121 cmd_bits = UMAC_SPEED_1000;
122 else if (phydev->speed == SPEED_100)
123 cmd_bits = UMAC_SPEED_100;
125 cmd_bits = UMAC_SPEED_10;
126 cmd_bits <<= CMD_SPEED_SHIFT;
129 if (phydev->duplex != DUPLEX_FULL)
130 cmd_bits |= CMD_HD_EN;
132 /* pause capability */
134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
137 * Program UMAC and RGMII block based on established
138 * link speed, duplex, and pause. The speed set in
139 * umac->cmd tell RGMII block which clock to use for
140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
141 * Receive clock is provided by the PHY.
143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
148 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
153 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
155 /* done if nothing has changed */
159 /* needed for MoCA fixed PHY to reflect correct link status */
160 netif_carrier_off(dev);
163 phy_print_status(phydev);
167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
168 struct fixed_phy_status *status)
170 if (dev && dev->phydev && status)
171 status->link = dev->phydev->link;
176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about
177 * not doing it and will start corrupting packets
179 void bcmgenet_mii_reset(struct net_device *dev)
181 struct bcmgenet_priv *priv = netdev_priv(dev);
183 if (GENET_IS_V4(priv))
187 phy_init_hw(priv->phydev);
188 phy_start_aneg(priv->phydev);
192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
194 struct bcmgenet_priv *priv = netdev_priv(dev);
197 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
198 if (!GENET_IS_V4(priv))
201 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
203 reg &= ~EXT_CK25_DIS;
204 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
207 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
208 reg |= EXT_GPHY_RESET;
209 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
212 reg &= ~EXT_GPHY_RESET;
214 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
215 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
219 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
223 static void bcmgenet_internal_phy_setup(struct net_device *dev)
225 struct bcmgenet_priv *priv = netdev_priv(dev);
229 bcmgenet_phy_power_set(dev, true);
231 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
232 reg |= EXT_PWR_DN_EN_LD;
233 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
234 bcmgenet_mii_reset(dev);
237 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
241 /* Speed settings are set in bcmgenet_mii_setup() */
242 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
243 reg |= LED_ACT_SOURCE_MAC;
244 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
246 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
247 fixed_phy_set_link_update(priv->phydev,
248 bcmgenet_fixed_phy_link_update);
251 int bcmgenet_mii_config(struct net_device *dev)
253 struct bcmgenet_priv *priv = netdev_priv(dev);
254 struct phy_device *phydev = priv->phydev;
255 struct device *kdev = &priv->pdev->dev;
256 const char *phy_name = NULL;
261 priv->ext_phy = !priv->internal_phy &&
262 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
264 if (priv->internal_phy)
265 priv->phy_interface = PHY_INTERFACE_MODE_NA;
267 switch (priv->phy_interface) {
268 case PHY_INTERFACE_MODE_NA:
269 case PHY_INTERFACE_MODE_MOCA:
270 /* Irrespective of the actually configured PHY speed (100 or
271 * 1000) GENETv4 only has an internal GPHY so we will just end
272 * up masking the Gigabit features from what we support, not
273 * switching to the EPHY
275 if (GENET_IS_V4(priv))
276 port_ctrl = PORT_MODE_INT_GPHY;
278 port_ctrl = PORT_MODE_INT_EPHY;
280 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
282 if (priv->internal_phy) {
283 phy_name = "internal PHY";
284 bcmgenet_internal_phy_setup(dev);
285 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
287 bcmgenet_moca_phy_setup(priv);
291 case PHY_INTERFACE_MODE_MII:
292 phy_name = "external MII";
293 phydev->supported &= PHY_BASIC_FEATURES;
294 bcmgenet_sys_writel(priv,
295 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
298 case PHY_INTERFACE_MODE_REVMII:
299 phy_name = "external RvMII";
300 /* of_mdiobus_register took care of reading the 'max-speed'
301 * PHY property for us, effectively limiting the PHY supported
302 * capabilities, use that knowledge to also configure the
303 * Reverse MII interface correctly.
305 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
307 port_ctrl = PORT_MODE_EXT_RVMII_25;
309 port_ctrl = PORT_MODE_EXT_RVMII_50;
310 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
313 case PHY_INTERFACE_MODE_RGMII:
314 /* RGMII_NO_ID: TXC transitions at the same time as TXD
315 * (requires PCB or receiver-side delay)
316 * RGMII: Add 2ns delay on TXC (90 degree shift)
318 * ID is implicitly disabled for 100Mbps (RG)MII operation.
320 id_mode_dis = BIT(16);
322 case PHY_INTERFACE_MODE_RGMII_TXID:
324 phy_name = "external RGMII (no delay)";
326 phy_name = "external RGMII (TX delay)";
327 bcmgenet_sys_writel(priv,
328 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
331 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
335 /* This is an external PHY (xMII), so we need to enable the RGMII
336 * block for the interface to work
339 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
340 reg |= RGMII_MODE_EN | id_mode_dis;
341 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
344 dev_info_once(kdev, "configuring instance for %s\n", phy_name);
349 int bcmgenet_mii_probe(struct net_device *dev)
351 struct bcmgenet_priv *priv = netdev_priv(dev);
352 struct device_node *dn = priv->pdev->dev.of_node;
353 struct phy_device *phydev;
357 /* Communicate the integrated PHY revision */
358 phy_flags = priv->gphy_rev;
360 /* Initialize link state variables that bcmgenet_mii_setup() uses */
362 priv->old_speed = -1;
363 priv->old_duplex = -1;
364 priv->old_pause = -1;
367 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
368 phy_flags, priv->phy_interface);
370 pr_err("could not attach to PHY\n");
374 phydev = priv->phydev;
375 phydev->dev_flags = phy_flags;
377 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
378 priv->phy_interface);
380 pr_err("could not attach to PHY\n");
385 priv->phydev = phydev;
387 /* Configure port multiplexer based on what the probed PHY device since
388 * reading the 'max-speed' property determines the maximum supported
389 * PHY speed which is needed for bcmgenet_mii_config() to configure
390 * things appropriately.
392 ret = bcmgenet_mii_config(dev);
394 phy_disconnect(priv->phydev);
398 phydev->advertising = phydev->supported;
400 /* The internal PHY has its link interrupts routed to the
403 if (priv->internal_phy)
404 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
406 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
411 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
412 * their internal MDIO management controller making them fail to successfully
413 * be read from or written to for the first transaction. We insert a dummy
414 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
415 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
416 * PHY device for this peripheral.
418 * Once the PHY driver is registered, we can workaround subsequent reads from
419 * there (e.g: during system-wide power management).
421 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
422 * therefore the right location to stick that workaround. Since we do not want
423 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
424 * Device Tree scan to limit the search area.
426 static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
428 struct net_device *dev = bus->priv;
429 struct bcmgenet_priv *priv = netdev_priv(dev);
430 struct device_node *np = priv->mdio_dn;
431 struct device_node *child = NULL;
436 read_mask = 1 << priv->phy_addr;
438 for_each_available_child_of_node(np, child) {
439 addr = of_mdio_parse_addr(&dev->dev, child);
443 read_mask |= 1 << addr;
447 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
448 if (read_mask & 1 << addr) {
449 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
450 mdiobus_read(bus, addr, MII_BMSR);
457 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
464 priv->mii_bus = mdiobus_alloc();
465 if (!priv->mii_bus) {
466 pr_err("failed to allocate\n");
471 bus->priv = priv->dev;
472 bus->name = "bcmgenet MII bus";
473 bus->parent = &priv->pdev->dev;
474 bus->read = bcmgenet_mii_read;
475 bus->write = bcmgenet_mii_write;
476 bus->reset = bcmgenet_mii_bus_reset;
477 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
478 priv->pdev->name, priv->pdev->id);
480 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
482 mdiobus_free(priv->mii_bus);
489 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
491 struct device_node *dn = priv->pdev->dev.of_node;
492 struct device *kdev = &priv->pdev->dev;
493 const char *phy_mode_str = NULL;
494 struct phy_device *phydev = NULL;
499 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
503 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
505 if (!priv->mdio_dn) {
506 dev_err(kdev, "unable to find MDIO bus node\n");
510 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
512 dev_err(kdev, "failed to register MDIO bus\n");
516 /* Fetch the PHY phandle */
517 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
519 /* In the case of a fixed PHY, the DT node associated
520 * to the PHY is the Ethernet MAC DT node.
522 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
523 ret = of_phy_register_fixed_link(dn);
527 priv->phy_dn = of_node_get(dn);
530 /* Get the link mode */
531 phy_mode = of_get_phy_mode(dn);
532 priv->phy_interface = phy_mode;
534 /* We need to specifically look up whether this PHY interface is internal
535 * or not *before* we even try to probe the PHY driver over MDIO as we
536 * may have shut down the internal PHY for power saving purposes.
539 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
541 dev_err(kdev, "invalid PHY mode property\n");
545 priv->phy_interface = PHY_INTERFACE_MODE_NA;
546 if (!strcasecmp(phy_mode_str, "internal"))
547 priv->internal_phy = true;
550 /* Make sure we initialize MoCA PHYs with a link down */
551 if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
552 phydev = of_phy_find_device(dn);
560 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
562 struct device *kdev = &priv->pdev->dev;
563 struct bcmgenet_platform_data *pd = kdev->platform_data;
564 struct mii_bus *mdio = priv->mii_bus;
565 struct phy_device *phydev;
568 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
570 * Internal or external PHY with MDIO access
572 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
573 mdio->phy_mask = ~(1 << pd->phy_address);
577 ret = mdiobus_register(mdio);
579 dev_err(kdev, "failed to register MDIO bus\n");
583 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
584 phydev = mdio->phy_map[pd->phy_address];
586 phydev = phy_find_first(mdio);
589 dev_err(kdev, "failed to register PHY device\n");
590 mdiobus_unregister(mdio);
595 * MoCA port or no MDIO access.
596 * Use fixed PHY to represent the link layer.
598 struct fixed_phy_status fphy_status = {
600 .speed = pd->phy_speed,
601 .duplex = pd->phy_duplex,
606 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
607 if (!phydev || IS_ERR(phydev)) {
608 dev_err(kdev, "failed to register fixed PHY device\n");
612 /* Make sure we initialize MoCA PHYs with a link down */
617 priv->phydev = phydev;
618 priv->phy_interface = pd->phy_interface;
623 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
625 struct device_node *dn = priv->pdev->dev.of_node;
628 return bcmgenet_mii_of_init(priv);
630 return bcmgenet_mii_pd_init(priv);
633 int bcmgenet_mii_init(struct net_device *dev)
635 struct bcmgenet_priv *priv = netdev_priv(dev);
638 ret = bcmgenet_mii_alloc(priv);
642 ret = bcmgenet_mii_bus_init(priv);
649 of_node_put(priv->phy_dn);
650 mdiobus_unregister(priv->mii_bus);
651 kfree(priv->mii_bus->irq);
652 mdiobus_free(priv->mii_bus);
656 void bcmgenet_mii_exit(struct net_device *dev)
658 struct bcmgenet_priv *priv = netdev_priv(dev);
660 of_node_put(priv->phy_dn);
661 mdiobus_unregister(priv->mii_bus);
662 kfree(priv->mii_bus->irq);
663 mdiobus_free(priv->mii_bus);