2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 5000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 usleep_range(10, 40);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6237 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 ns = timespec_to_ns(ts);
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6248 tg3_full_unlock(tp);
6253 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6302 tg3_full_unlock(tp);
6312 static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6328 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6336 /* tp->lock must be held */
6337 static void tg3_ptp_init(struct tg3 *tp)
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6345 tp->ptp_info = tg3_ptp_caps;
6348 /* tp->lock must be held */
6349 static void tg3_ptp_resume(struct tg3 *tp)
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6358 static void tg3_ptp_fini(struct tg3 *tp)
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6363 ptp_clock_unregister(tp->ptp_clock);
6364 tp->ptp_clock = NULL;
6368 static inline int tg3_irq_sync(struct tg3 *tp)
6370 return tp->irq_sync;
6373 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6382 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6404 if (tg3_flag(tp, SUPPORT_MSIX))
6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6416 if (!tg3_flag(tp, 5705_PLUS)) {
6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6428 if (tg3_flag(tp, NVRAM))
6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6432 static void tg3_dump_state(struct tg3 *tp)
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6441 if (tg3_flag(tp, PCI_EXPRESS)) {
6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6446 tg3_dump_legacy_regs(tp, regs);
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6463 /* SW status block */
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6488 /* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6494 static void tg3_tx_recover(struct tg3 *tp)
6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6508 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6510 /* Tell compiler to fetch tx indices from memory. */
6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6516 /* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6520 static void tg3_tx(struct tg3_napi *tnapi)
6522 struct tg3 *tp = tnapi->tp;
6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6524 u32 sw_idx = tnapi->tx_cons;
6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
6527 unsigned int pkts_compl = 0, bytes_compl = 0;
6529 if (tg3_flag(tp, ENABLE_TSS))
6532 txq = netdev_get_tx_queue(tp->dev, index);
6534 while (sw_idx != hw_idx) {
6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6536 struct sk_buff *skb = ri->skb;
6539 if (unlikely(skb == NULL)) {
6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6549 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6551 skb_tstamp_tx(skb, ×tamp);
6554 pci_unmap_single(tp->pdev,
6555 dma_unmap_addr(ri, mapping),
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6567 sw_idx = NEXT_TX(sw_idx);
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6570 ri = &tnapi->tx_buffers[sw_idx];
6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6574 pci_unmap_page(tp->pdev,
6575 dma_unmap_addr(ri, mapping),
6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6585 sw_idx = NEXT_TX(sw_idx);
6589 bytes_compl += skb->len;
6591 dev_kfree_skb_any(skb);
6593 if (unlikely(tx_bug)) {
6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6601 tnapi->tx_cons = sw_idx;
6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6610 if (unlikely(netif_tx_queue_stopped(txq) &&
6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
6620 static void tg3_frag_free(bool is_frag, void *data)
6623 put_page(virt_to_head_page(data));
6628 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6637 map_sz, PCI_DMA_FROMDEVICE);
6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6643 /* Returns size of skb allocated or < 0 on error.
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6654 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
6658 struct tg3_rx_buffer_desc *desc;
6659 struct ring_info *map;
6662 int skb_size, data_size, dest_idx;
6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
6669 data_size = tp->rx_pkt_map_sz;
6672 case RXD_OPAQUE_RING_JUMBO:
6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6674 desc = &tpr->rx_jmb[dest_idx].std;
6675 map = &tpr->rx_jmb_buffers[dest_idx];
6676 data_size = TG3_RX_JMB_MAP_SZ;
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6704 PCI_DMA_FROMDEVICE);
6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6711 dma_unmap_addr_set(map, mapping, mapping);
6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6719 /* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
6721 * tg3_alloc_rx_data for full details.
6723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
6728 struct tg3 *tp = tnapi->tp;
6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
6743 case RXD_OPAQUE_RING_JUMBO:
6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
6755 dest_map->data = src_map->data;
6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6766 src_map->data = NULL;
6769 /* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6795 struct tg3 *tp = tnapi->tp;
6796 u32 work_mask, rx_std_posted = 0;
6797 u32 std_prod_idx, jmb_prod_idx;
6798 u32 sw_idx = tnapi->rx_rcb_ptr;
6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6813 while (sw_idx != hw_idx && budget > 0) {
6814 struct ring_info *ri;
6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6827 dma_addr = dma_unmap_addr(ri, mapping);
6829 post_ptr = &std_prod_idx;
6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6833 dma_addr = dma_unmap_addr(ri, mapping);
6835 post_ptr = &jmb_prod_idx;
6837 goto next_pkt_nopost;
6839 work_mask |= opaque_key;
6841 if (desc->err_vlan & RXD_ERR_MASK) {
6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
6844 desc_idx, *post_ptr);
6846 /* Other statistics kept track of by card. */
6851 prefetch(data + TG3_RX_OFFSET(tp));
6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6863 if (len > TG3_RX_COPY_THRESH(tp)) {
6865 unsigned int frag_size;
6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6868 *post_ptr, &frag_size);
6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6873 PCI_DMA_FROMDEVICE);
6875 /* Ensure that the update to the data happens
6876 * after the usage of the old DMA mapping.
6882 skb = build_skb(data, frag_size);
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
6890 desc_idx, *post_ptr);
6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6895 goto drop_it_no_recycle;
6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6900 data + TG3_RX_OFFSET(tp),
6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6916 skb_checksum_none_assert(skb);
6918 skb->protocol = eth_type_trans(skb, tp->dev);
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q)) {
6922 dev_kfree_skb_any(skb);
6923 goto drop_it_no_recycle;
6926 if (desc->type_flags & RXD_FLAG_VLAN &&
6927 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6929 desc->err_vlan & RXD_VLAN_MASK);
6931 napi_gro_receive(&tnapi->napi, skb);
6939 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6940 tpr->rx_std_prod_idx = std_prod_idx &
6941 tp->rx_std_ring_mask;
6942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6943 tpr->rx_std_prod_idx);
6944 work_mask &= ~RXD_OPAQUE_RING_STD;
6949 sw_idx &= tp->rx_ret_ring_mask;
6951 /* Refresh hw_idx to see if there is new work */
6952 if (sw_idx == hw_idx) {
6953 hw_idx = *(tnapi->rx_rcb_prod_idx);
6958 /* ACK the status ring. */
6959 tnapi->rx_rcb_ptr = sw_idx;
6960 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6962 /* Refill RX ring(s). */
6963 if (!tg3_flag(tp, ENABLE_RSS)) {
6964 /* Sync BD data before updating mailbox */
6967 if (work_mask & RXD_OPAQUE_RING_STD) {
6968 tpr->rx_std_prod_idx = std_prod_idx &
6969 tp->rx_std_ring_mask;
6970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6971 tpr->rx_std_prod_idx);
6973 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6974 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6975 tp->rx_jmb_ring_mask;
6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6977 tpr->rx_jmb_prod_idx);
6980 } else if (work_mask) {
6981 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6982 * updated before the producer indices can be updated.
6986 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6987 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6989 if (tnapi != &tp->napi[1]) {
6990 tp->rx_refill = true;
6991 napi_schedule(&tp->napi[1].napi);
6998 static void tg3_poll_link(struct tg3 *tp)
7000 /* handle link change and other phy events */
7001 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7002 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7004 if (sblk->status & SD_STATUS_LINK_CHG) {
7005 sblk->status = SD_STATUS_UPDATED |
7006 (sblk->status & ~SD_STATUS_LINK_CHG);
7007 spin_lock(&tp->lock);
7008 if (tg3_flag(tp, USE_PHYLIB)) {
7010 (MAC_STATUS_SYNC_CHANGED |
7011 MAC_STATUS_CFG_CHANGED |
7012 MAC_STATUS_MI_COMPLETION |
7013 MAC_STATUS_LNKSTATE_CHANGED));
7016 tg3_setup_phy(tp, false);
7017 spin_unlock(&tp->lock);
7022 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7023 struct tg3_rx_prodring_set *dpr,
7024 struct tg3_rx_prodring_set *spr)
7026 u32 si, di, cpycnt, src_prod_idx;
7030 src_prod_idx = spr->rx_std_prod_idx;
7032 /* Make sure updates to the rx_std_buffers[] entries and the
7033 * standard producer index are seen in the correct order.
7037 if (spr->rx_std_cons_idx == src_prod_idx)
7040 if (spr->rx_std_cons_idx < src_prod_idx)
7041 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7043 cpycnt = tp->rx_std_ring_mask + 1 -
7044 spr->rx_std_cons_idx;
7046 cpycnt = min(cpycnt,
7047 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7049 si = spr->rx_std_cons_idx;
7050 di = dpr->rx_std_prod_idx;
7052 for (i = di; i < di + cpycnt; i++) {
7053 if (dpr->rx_std_buffers[i].data) {
7063 /* Ensure that updates to the rx_std_buffers ring and the
7064 * shadowed hardware producer ring from tg3_recycle_skb() are
7065 * ordered correctly WRT the skb check above.
7069 memcpy(&dpr->rx_std_buffers[di],
7070 &spr->rx_std_buffers[si],
7071 cpycnt * sizeof(struct ring_info));
7073 for (i = 0; i < cpycnt; i++, di++, si++) {
7074 struct tg3_rx_buffer_desc *sbd, *dbd;
7075 sbd = &spr->rx_std[si];
7076 dbd = &dpr->rx_std[di];
7077 dbd->addr_hi = sbd->addr_hi;
7078 dbd->addr_lo = sbd->addr_lo;
7081 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7082 tp->rx_std_ring_mask;
7083 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7084 tp->rx_std_ring_mask;
7088 src_prod_idx = spr->rx_jmb_prod_idx;
7090 /* Make sure updates to the rx_jmb_buffers[] entries and
7091 * the jumbo producer index are seen in the correct order.
7095 if (spr->rx_jmb_cons_idx == src_prod_idx)
7098 if (spr->rx_jmb_cons_idx < src_prod_idx)
7099 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7101 cpycnt = tp->rx_jmb_ring_mask + 1 -
7102 spr->rx_jmb_cons_idx;
7104 cpycnt = min(cpycnt,
7105 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7107 si = spr->rx_jmb_cons_idx;
7108 di = dpr->rx_jmb_prod_idx;
7110 for (i = di; i < di + cpycnt; i++) {
7111 if (dpr->rx_jmb_buffers[i].data) {
7121 /* Ensure that updates to the rx_jmb_buffers ring and the
7122 * shadowed hardware producer ring from tg3_recycle_skb() are
7123 * ordered correctly WRT the skb check above.
7127 memcpy(&dpr->rx_jmb_buffers[di],
7128 &spr->rx_jmb_buffers[si],
7129 cpycnt * sizeof(struct ring_info));
7131 for (i = 0; i < cpycnt; i++, di++, si++) {
7132 struct tg3_rx_buffer_desc *sbd, *dbd;
7133 sbd = &spr->rx_jmb[si].std;
7134 dbd = &dpr->rx_jmb[di].std;
7135 dbd->addr_hi = sbd->addr_hi;
7136 dbd->addr_lo = sbd->addr_lo;
7139 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7140 tp->rx_jmb_ring_mask;
7141 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7142 tp->rx_jmb_ring_mask;
7148 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7150 struct tg3 *tp = tnapi->tp;
7152 /* run TX completion thread */
7153 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7155 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7159 if (!tnapi->rx_rcb_prod_idx)
7162 /* run RX thread, within the bounds set by NAPI.
7163 * All RX "locking" is done by ensuring outside
7164 * code synchronizes with tg3->napi.poll()
7166 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7167 work_done += tg3_rx(tnapi, budget - work_done);
7169 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7170 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7172 u32 std_prod_idx = dpr->rx_std_prod_idx;
7173 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7175 tp->rx_refill = false;
7176 for (i = 1; i <= tp->rxq_cnt; i++)
7177 err |= tg3_rx_prodring_xfer(tp, dpr,
7178 &tp->napi[i].prodring);
7182 if (std_prod_idx != dpr->rx_std_prod_idx)
7183 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7184 dpr->rx_std_prod_idx);
7186 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7187 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7188 dpr->rx_jmb_prod_idx);
7193 tw32_f(HOSTCC_MODE, tp->coal_now);
7199 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7201 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7202 schedule_work(&tp->reset_task);
7205 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7207 cancel_work_sync(&tp->reset_task);
7208 tg3_flag_clear(tp, RESET_TASK_PENDING);
7209 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7212 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7214 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7215 struct tg3 *tp = tnapi->tp;
7217 struct tg3_hw_status *sblk = tnapi->hw_status;
7220 work_done = tg3_poll_work(tnapi, work_done, budget);
7222 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7225 if (unlikely(work_done >= budget))
7228 /* tp->last_tag is used in tg3_int_reenable() below
7229 * to tell the hw how much work has been processed,
7230 * so we must read it before checking for more work.
7232 tnapi->last_tag = sblk->status_tag;
7233 tnapi->last_irq_tag = tnapi->last_tag;
7236 /* check for RX/TX work to do */
7237 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7238 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7240 /* This test here is not race free, but will reduce
7241 * the number of interrupts by looping again.
7243 if (tnapi == &tp->napi[1] && tp->rx_refill)
7246 napi_complete(napi);
7247 /* Reenable interrupts. */
7248 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7250 /* This test here is synchronized by napi_schedule()
7251 * and napi_complete() to close the race condition.
7253 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7254 tw32(HOSTCC_MODE, tp->coalesce_mode |
7255 HOSTCC_MODE_ENABLE |
7266 /* work_done is guaranteed to be less than budget. */
7267 napi_complete(napi);
7268 tg3_reset_task_schedule(tp);
7272 static void tg3_process_error(struct tg3 *tp)
7275 bool real_error = false;
7277 if (tg3_flag(tp, ERROR_PROCESSED))
7280 /* Check Flow Attention register */
7281 val = tr32(HOSTCC_FLOW_ATTN);
7282 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7283 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7287 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7288 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7292 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7293 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7302 tg3_flag_set(tp, ERROR_PROCESSED);
7303 tg3_reset_task_schedule(tp);
7306 static int tg3_poll(struct napi_struct *napi, int budget)
7308 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7309 struct tg3 *tp = tnapi->tp;
7311 struct tg3_hw_status *sblk = tnapi->hw_status;
7314 if (sblk->status & SD_STATUS_ERROR)
7315 tg3_process_error(tp);
7319 work_done = tg3_poll_work(tnapi, work_done, budget);
7321 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7324 if (unlikely(work_done >= budget))
7327 if (tg3_flag(tp, TAGGED_STATUS)) {
7328 /* tp->last_tag is used in tg3_int_reenable() below
7329 * to tell the hw how much work has been processed,
7330 * so we must read it before checking for more work.
7332 tnapi->last_tag = sblk->status_tag;
7333 tnapi->last_irq_tag = tnapi->last_tag;
7336 sblk->status &= ~SD_STATUS_UPDATED;
7338 if (likely(!tg3_has_work(tnapi))) {
7339 napi_complete(napi);
7340 tg3_int_reenable(tnapi);
7348 /* work_done is guaranteed to be less than budget. */
7349 napi_complete(napi);
7350 tg3_reset_task_schedule(tp);
7354 static void tg3_napi_disable(struct tg3 *tp)
7358 for (i = tp->irq_cnt - 1; i >= 0; i--)
7359 napi_disable(&tp->napi[i].napi);
7362 static void tg3_napi_enable(struct tg3 *tp)
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 napi_enable(&tp->napi[i].napi);
7370 static void tg3_napi_init(struct tg3 *tp)
7374 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7375 for (i = 1; i < tp->irq_cnt; i++)
7376 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7379 static void tg3_napi_fini(struct tg3 *tp)
7383 for (i = 0; i < tp->irq_cnt; i++)
7384 netif_napi_del(&tp->napi[i].napi);
7387 static inline void tg3_netif_stop(struct tg3 *tp)
7389 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7390 tg3_napi_disable(tp);
7391 netif_carrier_off(tp->dev);
7392 netif_tx_disable(tp->dev);
7395 /* tp->lock must be held */
7396 static inline void tg3_netif_start(struct tg3 *tp)
7400 /* NOTE: unconditional netif_tx_wake_all_queues is only
7401 * appropriate so long as all callers are assured to
7402 * have free tx slots (such as after tg3_init_hw)
7404 netif_tx_wake_all_queues(tp->dev);
7407 netif_carrier_on(tp->dev);
7409 tg3_napi_enable(tp);
7410 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7411 tg3_enable_ints(tp);
7414 static void tg3_irq_quiesce(struct tg3 *tp)
7418 BUG_ON(tp->irq_sync);
7423 for (i = 0; i < tp->irq_cnt; i++)
7424 synchronize_irq(tp->napi[i].irq_vec);
7427 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7428 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7429 * with as well. Most of the time, this is not necessary except when
7430 * shutting down the device.
7432 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7434 spin_lock_bh(&tp->lock);
7436 tg3_irq_quiesce(tp);
7439 static inline void tg3_full_unlock(struct tg3 *tp)
7441 spin_unlock_bh(&tp->lock);
7444 /* One-shot MSI handler - Chip automatically disables interrupt
7445 * after sending MSI so driver doesn't have to do it.
7447 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7449 struct tg3_napi *tnapi = dev_id;
7450 struct tg3 *tp = tnapi->tp;
7452 prefetch(tnapi->hw_status);
7454 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7456 if (likely(!tg3_irq_sync(tp)))
7457 napi_schedule(&tnapi->napi);
7462 /* MSI ISR - No need to check for interrupt sharing and no need to
7463 * flush status block and interrupt mailbox. PCI ordering rules
7464 * guarantee that MSI will arrive after the status block.
7466 static irqreturn_t tg3_msi(int irq, void *dev_id)
7468 struct tg3_napi *tnapi = dev_id;
7469 struct tg3 *tp = tnapi->tp;
7471 prefetch(tnapi->hw_status);
7473 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7475 * Writing any value to intr-mbox-0 clears PCI INTA# and
7476 * chip-internal interrupt pending events.
7477 * Writing non-zero to intr-mbox-0 additional tells the
7478 * NIC to stop sending us irqs, engaging "in-intr-handler"
7481 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7482 if (likely(!tg3_irq_sync(tp)))
7483 napi_schedule(&tnapi->napi);
7485 return IRQ_RETVAL(1);
7488 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7490 struct tg3_napi *tnapi = dev_id;
7491 struct tg3 *tp = tnapi->tp;
7492 struct tg3_hw_status *sblk = tnapi->hw_status;
7493 unsigned int handled = 1;
7495 /* In INTx mode, it is possible for the interrupt to arrive at
7496 * the CPU before the status block posted prior to the interrupt.
7497 * Reading the PCI State register will confirm whether the
7498 * interrupt is ours and will flush the status block.
7500 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7501 if (tg3_flag(tp, CHIP_RESETTING) ||
7502 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7509 * Writing any value to intr-mbox-0 clears PCI INTA# and
7510 * chip-internal interrupt pending events.
7511 * Writing non-zero to intr-mbox-0 additional tells the
7512 * NIC to stop sending us irqs, engaging "in-intr-handler"
7515 * Flush the mailbox to de-assert the IRQ immediately to prevent
7516 * spurious interrupts. The flush impacts performance but
7517 * excessive spurious interrupts can be worse in some cases.
7519 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7520 if (tg3_irq_sync(tp))
7522 sblk->status &= ~SD_STATUS_UPDATED;
7523 if (likely(tg3_has_work(tnapi))) {
7524 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7525 napi_schedule(&tnapi->napi);
7527 /* No work, shared interrupt perhaps? re-enable
7528 * interrupts, and flush that PCI write
7530 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7534 return IRQ_RETVAL(handled);
7537 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7539 struct tg3_napi *tnapi = dev_id;
7540 struct tg3 *tp = tnapi->tp;
7541 struct tg3_hw_status *sblk = tnapi->hw_status;
7542 unsigned int handled = 1;
7544 /* In INTx mode, it is possible for the interrupt to arrive at
7545 * the CPU before the status block posted prior to the interrupt.
7546 * Reading the PCI State register will confirm whether the
7547 * interrupt is ours and will flush the status block.
7549 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7550 if (tg3_flag(tp, CHIP_RESETTING) ||
7551 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7558 * writing any value to intr-mbox-0 clears PCI INTA# and
7559 * chip-internal interrupt pending events.
7560 * writing non-zero to intr-mbox-0 additional tells the
7561 * NIC to stop sending us irqs, engaging "in-intr-handler"
7564 * Flush the mailbox to de-assert the IRQ immediately to prevent
7565 * spurious interrupts. The flush impacts performance but
7566 * excessive spurious interrupts can be worse in some cases.
7568 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7571 * In a shared interrupt configuration, sometimes other devices'
7572 * interrupts will scream. We record the current status tag here
7573 * so that the above check can report that the screaming interrupts
7574 * are unhandled. Eventually they will be silenced.
7576 tnapi->last_irq_tag = sblk->status_tag;
7578 if (tg3_irq_sync(tp))
7581 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7583 napi_schedule(&tnapi->napi);
7586 return IRQ_RETVAL(handled);
7589 /* ISR for interrupt test */
7590 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7592 struct tg3_napi *tnapi = dev_id;
7593 struct tg3 *tp = tnapi->tp;
7594 struct tg3_hw_status *sblk = tnapi->hw_status;
7596 if ((sblk->status & SD_STATUS_UPDATED) ||
7597 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7598 tg3_disable_ints(tp);
7599 return IRQ_RETVAL(1);
7601 return IRQ_RETVAL(0);
7604 #ifdef CONFIG_NET_POLL_CONTROLLER
7605 static void tg3_poll_controller(struct net_device *dev)
7608 struct tg3 *tp = netdev_priv(dev);
7610 if (tg3_irq_sync(tp))
7613 for (i = 0; i < tp->irq_cnt; i++)
7614 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7618 static void tg3_tx_timeout(struct net_device *dev)
7620 struct tg3 *tp = netdev_priv(dev);
7622 if (netif_msg_tx_err(tp)) {
7623 netdev_err(dev, "transmit timed out, resetting\n");
7627 tg3_reset_task_schedule(tp);
7630 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7631 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7633 u32 base = (u32) mapping & 0xffffffff;
7635 return base + len + 8 < base;
7638 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7639 * of any 4GB boundaries: 4G, 8G, etc
7641 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7644 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7645 u32 base = (u32) mapping & 0xffffffff;
7647 return ((base + len + (mss & 0x3fff)) < base);
7652 /* Test for DMA addresses > 40-bit */
7653 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7656 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7657 if (tg3_flag(tp, 40BIT_DMA_BUG))
7658 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7665 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7666 dma_addr_t mapping, u32 len, u32 flags,
7669 txbd->addr_hi = ((u64) mapping >> 32);
7670 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7671 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7672 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7675 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7676 dma_addr_t map, u32 len, u32 flags,
7679 struct tg3 *tp = tnapi->tp;
7682 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7685 if (tg3_4g_overflow_test(map, len))
7688 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7691 if (tg3_40bit_overflow_test(tp, map, len))
7694 if (tp->dma_limit) {
7695 u32 prvidx = *entry;
7696 u32 tmp_flag = flags & ~TXD_FLAG_END;
7697 while (len > tp->dma_limit && *budget) {
7698 u32 frag_len = tp->dma_limit;
7699 len -= tp->dma_limit;
7701 /* Avoid the 8byte DMA problem */
7703 len += tp->dma_limit / 2;
7704 frag_len = tp->dma_limit / 2;
7707 tnapi->tx_buffers[*entry].fragmented = true;
7709 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7710 frag_len, tmp_flag, mss, vlan);
7713 *entry = NEXT_TX(*entry);
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
7723 *entry = NEXT_TX(*entry);
7726 tnapi->tx_buffers[prvidx].fragmented = false;
7730 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7731 len, flags, mss, vlan);
7732 *entry = NEXT_TX(*entry);
7738 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7741 struct sk_buff *skb;
7742 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7747 pci_unmap_single(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
7752 while (txb->fragmented) {
7753 txb->fragmented = false;
7754 entry = NEXT_TX(entry);
7755 txb = &tnapi->tx_buffers[entry];
7758 for (i = 0; i <= last; i++) {
7759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7761 entry = NEXT_TX(entry);
7762 txb = &tnapi->tx_buffers[entry];
7764 pci_unmap_page(tnapi->tp->pdev,
7765 dma_unmap_addr(txb, mapping),
7766 skb_frag_size(frag), PCI_DMA_TODEVICE);
7768 while (txb->fragmented) {
7769 txb->fragmented = false;
7770 entry = NEXT_TX(entry);
7771 txb = &tnapi->tx_buffers[entry];
7776 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7777 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7778 struct sk_buff **pskb,
7779 u32 *entry, u32 *budget,
7780 u32 base_flags, u32 mss, u32 vlan)
7782 struct tg3 *tp = tnapi->tp;
7783 struct sk_buff *new_skb, *skb = *pskb;
7784 dma_addr_t new_addr = 0;
7787 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7788 new_skb = skb_copy(skb, GFP_ATOMIC);
7790 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7792 new_skb = skb_copy_expand(skb,
7793 skb_headroom(skb) + more_headroom,
7794 skb_tailroom(skb), GFP_ATOMIC);
7800 /* New SKB is guaranteed to be linear. */
7801 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7803 /* Make sure the mapping succeeded */
7804 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7805 dev_kfree_skb_any(new_skb);
7808 u32 save_entry = *entry;
7810 base_flags |= TXD_FLAG_END;
7812 tnapi->tx_buffers[*entry].skb = new_skb;
7813 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7816 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7817 new_skb->len, base_flags,
7819 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7820 dev_kfree_skb_any(new_skb);
7826 dev_kfree_skb_any(skb);
7831 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7833 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7834 * indicated in tg3_tx_frag_set()
7836 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7837 struct netdev_queue *txq, struct sk_buff *skb)
7839 struct sk_buff *segs, *nskb;
7840 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7842 /* Estimate the number of fragments in the worst case */
7843 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7844 netif_tx_stop_queue(txq);
7846 /* netif_tx_stop_queue() must be done before checking
7847 * checking tx index in tg3_tx_avail() below, because in
7848 * tg3_tx(), we update tx index before checking for
7849 * netif_tx_queue_stopped().
7852 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7853 return NETDEV_TX_BUSY;
7855 netif_tx_wake_queue(txq);
7858 segs = skb_gso_segment(skb, tp->dev->features &
7859 ~(NETIF_F_TSO | NETIF_F_TSO6));
7860 if (IS_ERR(segs) || !segs)
7861 goto tg3_tso_bug_end;
7867 tg3_start_xmit(nskb, tp->dev);
7871 dev_kfree_skb_any(skb);
7873 return NETDEV_TX_OK;
7876 /* hard_start_xmit for all devices */
7877 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7879 struct tg3 *tp = netdev_priv(dev);
7880 u32 len, entry, base_flags, mss, vlan = 0;
7882 int i = -1, would_hit_hwbug;
7884 struct tg3_napi *tnapi;
7885 struct netdev_queue *txq;
7887 struct iphdr *iph = NULL;
7888 struct tcphdr *tcph = NULL;
7889 __sum16 tcp_csum = 0, ip_csum = 0;
7890 __be16 ip_tot_len = 0;
7892 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7893 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7894 if (tg3_flag(tp, ENABLE_TSS))
7897 budget = tg3_tx_avail(tnapi);
7899 /* We are running in BH disabled context with netif_tx_lock
7900 * and TX reclaim runs via tp->napi.poll inside of a software
7901 * interrupt. Furthermore, IRQ processing runs lockless so we have
7902 * no IRQ context deadlocks to worry about either. Rejoice!
7904 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7905 if (!netif_tx_queue_stopped(txq)) {
7906 netif_tx_stop_queue(txq);
7908 /* This is a hard error, log it. */
7910 "BUG! Tx Ring full when queue awake!\n");
7912 return NETDEV_TX_BUSY;
7915 entry = tnapi->tx_prod;
7917 if (skb->ip_summed == CHECKSUM_PARTIAL)
7918 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7920 mss = skb_shinfo(skb)->gso_size;
7922 u32 tcp_opt_len, hdr_len;
7924 if (skb_cow_head(skb, 0))
7928 tcp_opt_len = tcp_optlen(skb);
7930 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7932 if (!skb_is_gso_v6(skb)) {
7933 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7934 tg3_flag(tp, TSO_BUG))
7935 return tg3_tso_bug(tp, tnapi, txq, skb);
7937 ip_csum = iph->check;
7938 ip_tot_len = iph->tot_len;
7940 iph->tot_len = htons(mss + hdr_len);
7943 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7944 TXD_FLAG_CPU_POST_DMA);
7946 tcph = tcp_hdr(skb);
7947 tcp_csum = tcph->check;
7949 if (tg3_flag(tp, HW_TSO_1) ||
7950 tg3_flag(tp, HW_TSO_2) ||
7951 tg3_flag(tp, HW_TSO_3)) {
7953 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7955 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7959 if (tg3_flag(tp, HW_TSO_3)) {
7960 mss |= (hdr_len & 0xc) << 12;
7962 base_flags |= 0x00000010;
7963 base_flags |= (hdr_len & 0x3e0) << 5;
7964 } else if (tg3_flag(tp, HW_TSO_2))
7965 mss |= hdr_len << 9;
7966 else if (tg3_flag(tp, HW_TSO_1) ||
7967 tg3_asic_rev(tp) == ASIC_REV_5705) {
7968 if (tcp_opt_len || iph->ihl > 5) {
7971 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7972 mss |= (tsflags << 11);
7975 if (tcp_opt_len || iph->ihl > 5) {
7978 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7979 base_flags |= tsflags << 12;
7984 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7985 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7986 base_flags |= TXD_FLAG_JMB_PKT;
7988 if (vlan_tx_tag_present(skb)) {
7989 base_flags |= TXD_FLAG_VLAN;
7990 vlan = vlan_tx_tag_get(skb);
7993 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7994 tg3_flag(tp, TX_TSTAMP_EN)) {
7995 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7996 base_flags |= TXD_FLAG_HWTSTAMP;
7999 len = skb_headlen(skb);
8001 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8002 if (pci_dma_mapping_error(tp->pdev, mapping))
8006 tnapi->tx_buffers[entry].skb = skb;
8007 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8009 would_hit_hwbug = 0;
8011 if (tg3_flag(tp, 5701_DMA_BUG))
8012 would_hit_hwbug = 1;
8014 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8015 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8017 would_hit_hwbug = 1;
8018 } else if (skb_shinfo(skb)->nr_frags > 0) {
8021 if (!tg3_flag(tp, HW_TSO_1) &&
8022 !tg3_flag(tp, HW_TSO_2) &&
8023 !tg3_flag(tp, HW_TSO_3))
8026 /* Now loop through additional data
8027 * fragments, and queue them.
8029 last = skb_shinfo(skb)->nr_frags - 1;
8030 for (i = 0; i <= last; i++) {
8031 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8033 len = skb_frag_size(frag);
8034 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8035 len, DMA_TO_DEVICE);
8037 tnapi->tx_buffers[entry].skb = NULL;
8038 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8040 if (dma_mapping_error(&tp->pdev->dev, mapping))
8044 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8046 ((i == last) ? TXD_FLAG_END : 0),
8048 would_hit_hwbug = 1;
8054 if (would_hit_hwbug) {
8055 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8058 /* If it's a TSO packet, do GSO instead of
8059 * allocating and copying to a large linear SKB
8062 iph->check = ip_csum;
8063 iph->tot_len = ip_tot_len;
8065 tcph->check = tcp_csum;
8066 return tg3_tso_bug(tp, tnapi, txq, skb);
8069 /* If the workaround fails due to memory/mapping
8070 * failure, silently drop this packet.
8072 entry = tnapi->tx_prod;
8073 budget = tg3_tx_avail(tnapi);
8074 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8075 base_flags, mss, vlan))
8079 skb_tx_timestamp(skb);
8080 netdev_tx_sent_queue(txq, skb->len);
8082 /* Sync BD data before updating mailbox */
8085 /* Packets are ready, update Tx producer idx local and on card. */
8086 tw32_tx_mbox(tnapi->prodmbox, entry);
8088 tnapi->tx_prod = entry;
8089 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8090 netif_tx_stop_queue(txq);
8092 /* netif_tx_stop_queue() must be done before checking
8093 * checking tx index in tg3_tx_avail() below, because in
8094 * tg3_tx(), we update tx index before checking for
8095 * netif_tx_queue_stopped().
8098 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8099 netif_tx_wake_queue(txq);
8103 return NETDEV_TX_OK;
8106 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8107 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8109 dev_kfree_skb_any(skb);
8112 return NETDEV_TX_OK;
8115 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8118 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8119 MAC_MODE_PORT_MODE_MASK);
8121 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8123 if (!tg3_flag(tp, 5705_PLUS))
8124 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8126 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8127 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8129 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8131 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8133 if (tg3_flag(tp, 5705_PLUS) ||
8134 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8135 tg3_asic_rev(tp) == ASIC_REV_5700)
8136 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8139 tw32(MAC_MODE, tp->mac_mode);
8143 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8145 u32 val, bmcr, mac_mode, ptest = 0;
8147 tg3_phy_toggle_apd(tp, false);
8148 tg3_phy_toggle_automdix(tp, false);
8150 if (extlpbk && tg3_phy_set_extloopbk(tp))
8153 bmcr = BMCR_FULLDPLX;
8158 bmcr |= BMCR_SPEED100;
8162 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8164 bmcr |= BMCR_SPEED100;
8167 bmcr |= BMCR_SPEED1000;
8172 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8173 tg3_readphy(tp, MII_CTRL1000, &val);
8174 val |= CTL1000_AS_MASTER |
8175 CTL1000_ENABLE_MASTER;
8176 tg3_writephy(tp, MII_CTRL1000, val);
8178 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8179 MII_TG3_FET_PTEST_TRIM_2;
8180 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8183 bmcr |= BMCR_LOOPBACK;
8185 tg3_writephy(tp, MII_BMCR, bmcr);
8187 /* The write needs to be flushed for the FETs */
8188 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8189 tg3_readphy(tp, MII_BMCR, &bmcr);
8193 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8194 tg3_asic_rev(tp) == ASIC_REV_5785) {
8195 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8196 MII_TG3_FET_PTEST_FRC_TX_LINK |
8197 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8199 /* The write needs to be flushed for the AC131 */
8200 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8203 /* Reset to prevent losing 1st rx packet intermittently */
8204 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8205 tg3_flag(tp, 5780_CLASS)) {
8206 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8208 tw32_f(MAC_RX_MODE, tp->rx_mode);
8211 mac_mode = tp->mac_mode &
8212 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8213 if (speed == SPEED_1000)
8214 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8216 mac_mode |= MAC_MODE_PORT_MODE_MII;
8218 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8219 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8221 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8222 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8223 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8224 mac_mode |= MAC_MODE_LINK_POLARITY;
8226 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8227 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8230 tw32(MAC_MODE, mac_mode);
8236 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8238 struct tg3 *tp = netdev_priv(dev);
8240 if (features & NETIF_F_LOOPBACK) {
8241 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8244 spin_lock_bh(&tp->lock);
8245 tg3_mac_loopback(tp, true);
8246 netif_carrier_on(tp->dev);
8247 spin_unlock_bh(&tp->lock);
8248 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8250 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8253 spin_lock_bh(&tp->lock);
8254 tg3_mac_loopback(tp, false);
8255 /* Force link status check */
8256 tg3_setup_phy(tp, true);
8257 spin_unlock_bh(&tp->lock);
8258 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8262 static netdev_features_t tg3_fix_features(struct net_device *dev,
8263 netdev_features_t features)
8265 struct tg3 *tp = netdev_priv(dev);
8267 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8268 features &= ~NETIF_F_ALL_TSO;
8273 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8275 netdev_features_t changed = dev->features ^ features;
8277 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8278 tg3_set_loopback(dev, features);
8283 static void tg3_rx_prodring_free(struct tg3 *tp,
8284 struct tg3_rx_prodring_set *tpr)
8288 if (tpr != &tp->napi[0].prodring) {
8289 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8290 i = (i + 1) & tp->rx_std_ring_mask)
8291 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8294 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8295 for (i = tpr->rx_jmb_cons_idx;
8296 i != tpr->rx_jmb_prod_idx;
8297 i = (i + 1) & tp->rx_jmb_ring_mask) {
8298 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8306 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8307 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8310 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8311 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8312 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8317 /* Initialize rx rings for packet processing.
8319 * The chip has been shut down and the driver detached from
8320 * the networking, so no interrupts or new tx packets will
8321 * end up in the driver. tp->{tx,}lock are held and thus
8324 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8325 struct tg3_rx_prodring_set *tpr)
8327 u32 i, rx_pkt_dma_sz;
8329 tpr->rx_std_cons_idx = 0;
8330 tpr->rx_std_prod_idx = 0;
8331 tpr->rx_jmb_cons_idx = 0;
8332 tpr->rx_jmb_prod_idx = 0;
8334 if (tpr != &tp->napi[0].prodring) {
8335 memset(&tpr->rx_std_buffers[0], 0,
8336 TG3_RX_STD_BUFF_RING_SIZE(tp));
8337 if (tpr->rx_jmb_buffers)
8338 memset(&tpr->rx_jmb_buffers[0], 0,
8339 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8343 /* Zero out all descriptors. */
8344 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8346 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8347 if (tg3_flag(tp, 5780_CLASS) &&
8348 tp->dev->mtu > ETH_DATA_LEN)
8349 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8350 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8352 /* Initialize invariants of the rings, we only set this
8353 * stuff once. This works because the card does not
8354 * write into the rx buffer posting rings.
8356 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8357 struct tg3_rx_buffer_desc *rxd;
8359 rxd = &tpr->rx_std[i];
8360 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8361 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8362 rxd->opaque = (RXD_OPAQUE_RING_STD |
8363 (i << RXD_OPAQUE_INDEX_SHIFT));
8366 /* Now allocate fresh SKBs for each rx ring. */
8367 for (i = 0; i < tp->rx_pending; i++) {
8368 unsigned int frag_size;
8370 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8372 netdev_warn(tp->dev,
8373 "Using a smaller RX standard ring. Only "
8374 "%d out of %d buffers were allocated "
8375 "successfully\n", i, tp->rx_pending);
8383 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8386 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8388 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8391 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8392 struct tg3_rx_buffer_desc *rxd;
8394 rxd = &tpr->rx_jmb[i].std;
8395 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8396 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8398 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8399 (i << RXD_OPAQUE_INDEX_SHIFT));
8402 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8403 unsigned int frag_size;
8405 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8407 netdev_warn(tp->dev,
8408 "Using a smaller RX jumbo ring. Only %d "
8409 "out of %d buffers were allocated "
8410 "successfully\n", i, tp->rx_jumbo_pending);
8413 tp->rx_jumbo_pending = i;
8422 tg3_rx_prodring_free(tp, tpr);
8426 static void tg3_rx_prodring_fini(struct tg3 *tp,
8427 struct tg3_rx_prodring_set *tpr)
8429 kfree(tpr->rx_std_buffers);
8430 tpr->rx_std_buffers = NULL;
8431 kfree(tpr->rx_jmb_buffers);
8432 tpr->rx_jmb_buffers = NULL;
8434 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8435 tpr->rx_std, tpr->rx_std_mapping);
8439 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8440 tpr->rx_jmb, tpr->rx_jmb_mapping);
8445 static int tg3_rx_prodring_init(struct tg3 *tp,
8446 struct tg3_rx_prodring_set *tpr)
8448 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8450 if (!tpr->rx_std_buffers)
8453 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8454 TG3_RX_STD_RING_BYTES(tp),
8455 &tpr->rx_std_mapping,
8460 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8461 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8463 if (!tpr->rx_jmb_buffers)
8466 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8467 TG3_RX_JMB_RING_BYTES(tp),
8468 &tpr->rx_jmb_mapping,
8477 tg3_rx_prodring_fini(tp, tpr);
8481 /* Free up pending packets in all rx/tx rings.
8483 * The chip has been shut down and the driver detached from
8484 * the networking, so no interrupts or new tx packets will
8485 * end up in the driver. tp->{tx,}lock is not held and we are not
8486 * in an interrupt context and thus may sleep.
8488 static void tg3_free_rings(struct tg3 *tp)
8492 for (j = 0; j < tp->irq_cnt; j++) {
8493 struct tg3_napi *tnapi = &tp->napi[j];
8495 tg3_rx_prodring_free(tp, &tnapi->prodring);
8497 if (!tnapi->tx_buffers)
8500 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8501 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8506 tg3_tx_skb_unmap(tnapi, i,
8507 skb_shinfo(skb)->nr_frags - 1);
8509 dev_kfree_skb_any(skb);
8511 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8515 /* Initialize tx/rx rings for packet processing.
8517 * The chip has been shut down and the driver detached from
8518 * the networking, so no interrupts or new tx packets will
8519 * end up in the driver. tp->{tx,}lock are held and thus
8522 static int tg3_init_rings(struct tg3 *tp)
8526 /* Free up all the SKBs. */
8529 for (i = 0; i < tp->irq_cnt; i++) {
8530 struct tg3_napi *tnapi = &tp->napi[i];
8532 tnapi->last_tag = 0;
8533 tnapi->last_irq_tag = 0;
8534 tnapi->hw_status->status = 0;
8535 tnapi->hw_status->status_tag = 0;
8536 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8541 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8543 tnapi->rx_rcb_ptr = 0;
8545 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8547 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8556 static void tg3_mem_tx_release(struct tg3 *tp)
8560 for (i = 0; i < tp->irq_max; i++) {
8561 struct tg3_napi *tnapi = &tp->napi[i];
8563 if (tnapi->tx_ring) {
8564 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8565 tnapi->tx_ring, tnapi->tx_desc_mapping);
8566 tnapi->tx_ring = NULL;
8569 kfree(tnapi->tx_buffers);
8570 tnapi->tx_buffers = NULL;
8574 static int tg3_mem_tx_acquire(struct tg3 *tp)
8577 struct tg3_napi *tnapi = &tp->napi[0];
8579 /* If multivector TSS is enabled, vector 0 does not handle
8580 * tx interrupts. Don't allocate any resources for it.
8582 if (tg3_flag(tp, ENABLE_TSS))
8585 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8586 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8587 TG3_TX_RING_SIZE, GFP_KERNEL);
8588 if (!tnapi->tx_buffers)
8591 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8593 &tnapi->tx_desc_mapping,
8595 if (!tnapi->tx_ring)
8602 tg3_mem_tx_release(tp);
8606 static void tg3_mem_rx_release(struct tg3 *tp)
8610 for (i = 0; i < tp->irq_max; i++) {
8611 struct tg3_napi *tnapi = &tp->napi[i];
8613 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8618 dma_free_coherent(&tp->pdev->dev,
8619 TG3_RX_RCB_RING_BYTES(tp),
8621 tnapi->rx_rcb_mapping);
8622 tnapi->rx_rcb = NULL;
8626 static int tg3_mem_rx_acquire(struct tg3 *tp)
8628 unsigned int i, limit;
8630 limit = tp->rxq_cnt;
8632 /* If RSS is enabled, we need a (dummy) producer ring
8633 * set on vector zero. This is the true hw prodring.
8635 if (tg3_flag(tp, ENABLE_RSS))
8638 for (i = 0; i < limit; i++) {
8639 struct tg3_napi *tnapi = &tp->napi[i];
8641 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8644 /* If multivector RSS is enabled, vector 0
8645 * does not handle rx or tx interrupts.
8646 * Don't allocate any resources for it.
8648 if (!i && tg3_flag(tp, ENABLE_RSS))
8651 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8652 TG3_RX_RCB_RING_BYTES(tp),
8653 &tnapi->rx_rcb_mapping,
8662 tg3_mem_rx_release(tp);
8667 * Must not be invoked with interrupt sources disabled and
8668 * the hardware shutdown down.
8670 static void tg3_free_consistent(struct tg3 *tp)
8674 for (i = 0; i < tp->irq_cnt; i++) {
8675 struct tg3_napi *tnapi = &tp->napi[i];
8677 if (tnapi->hw_status) {
8678 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8680 tnapi->status_mapping);
8681 tnapi->hw_status = NULL;
8685 tg3_mem_rx_release(tp);
8686 tg3_mem_tx_release(tp);
8689 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8690 tp->hw_stats, tp->stats_mapping);
8691 tp->hw_stats = NULL;
8696 * Must not be invoked with interrupt sources disabled and
8697 * the hardware shutdown down. Can sleep.
8699 static int tg3_alloc_consistent(struct tg3 *tp)
8703 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8704 sizeof(struct tg3_hw_stats),
8705 &tp->stats_mapping, GFP_KERNEL);
8709 for (i = 0; i < tp->irq_cnt; i++) {
8710 struct tg3_napi *tnapi = &tp->napi[i];
8711 struct tg3_hw_status *sblk;
8713 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8715 &tnapi->status_mapping,
8717 if (!tnapi->hw_status)
8720 sblk = tnapi->hw_status;
8722 if (tg3_flag(tp, ENABLE_RSS)) {
8723 u16 *prodptr = NULL;
8726 * When RSS is enabled, the status block format changes
8727 * slightly. The "rx_jumbo_consumer", "reserved",
8728 * and "rx_mini_consumer" members get mapped to the
8729 * other three rx return ring producer indexes.
8733 prodptr = &sblk->idx[0].rx_producer;
8736 prodptr = &sblk->rx_jumbo_consumer;
8739 prodptr = &sblk->reserved;
8742 prodptr = &sblk->rx_mini_consumer;
8745 tnapi->rx_rcb_prod_idx = prodptr;
8747 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8751 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8757 tg3_free_consistent(tp);
8761 #define MAX_WAIT_CNT 1000
8763 /* To stop a block, clear the enable bit and poll till it
8764 * clears. tp->lock is held.
8766 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8771 if (tg3_flag(tp, 5705_PLUS)) {
8778 /* We can't enable/disable these bits of the
8779 * 5705/5750, just say success.
8792 for (i = 0; i < MAX_WAIT_CNT; i++) {
8793 if (pci_channel_offline(tp->pdev)) {
8794 dev_err(&tp->pdev->dev,
8795 "tg3_stop_block device offline, "
8796 "ofs=%lx enable_bit=%x\n",
8803 if ((val & enable_bit) == 0)
8807 if (i == MAX_WAIT_CNT && !silent) {
8808 dev_err(&tp->pdev->dev,
8809 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8817 /* tp->lock is held. */
8818 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8822 tg3_disable_ints(tp);
8824 if (pci_channel_offline(tp->pdev)) {
8825 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8826 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8831 tp->rx_mode &= ~RX_MODE_ENABLE;
8832 tw32_f(MAC_RX_MODE, tp->rx_mode);
8835 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8837 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8838 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8839 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8840 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8843 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8844 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8845 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8846 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8847 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8848 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8850 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8851 tw32_f(MAC_MODE, tp->mac_mode);
8854 tp->tx_mode &= ~TX_MODE_ENABLE;
8855 tw32_f(MAC_TX_MODE, tp->tx_mode);
8857 for (i = 0; i < MAX_WAIT_CNT; i++) {
8859 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8862 if (i >= MAX_WAIT_CNT) {
8863 dev_err(&tp->pdev->dev,
8864 "%s timed out, TX_MODE_ENABLE will not clear "
8865 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8869 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8870 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8871 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8873 tw32(FTQ_RESET, 0xffffffff);
8874 tw32(FTQ_RESET, 0x00000000);
8876 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8877 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8880 for (i = 0; i < tp->irq_cnt; i++) {
8881 struct tg3_napi *tnapi = &tp->napi[i];
8882 if (tnapi->hw_status)
8883 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8889 /* Save PCI command register before chip reset */
8890 static void tg3_save_pci_state(struct tg3 *tp)
8892 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8895 /* Restore PCI state after chip reset */
8896 static void tg3_restore_pci_state(struct tg3 *tp)
8900 /* Re-enable indirect register accesses. */
8901 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8902 tp->misc_host_ctrl);
8904 /* Set MAX PCI retry to zero. */
8905 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8906 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8907 tg3_flag(tp, PCIX_MODE))
8908 val |= PCISTATE_RETRY_SAME_DMA;
8909 /* Allow reads and writes to the APE register and memory space. */
8910 if (tg3_flag(tp, ENABLE_APE))
8911 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8912 PCISTATE_ALLOW_APE_SHMEM_WR |
8913 PCISTATE_ALLOW_APE_PSPACE_WR;
8914 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8916 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8918 if (!tg3_flag(tp, PCI_EXPRESS)) {
8919 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8920 tp->pci_cacheline_sz);
8921 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8925 /* Make sure PCI-X relaxed ordering bit is clear. */
8926 if (tg3_flag(tp, PCIX_MODE)) {
8929 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8931 pcix_cmd &= ~PCI_X_CMD_ERO;
8932 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8936 if (tg3_flag(tp, 5780_CLASS)) {
8938 /* Chip reset on 5780 will reset MSI enable bit,
8939 * so need to restore it.
8941 if (tg3_flag(tp, USING_MSI)) {
8944 pci_read_config_word(tp->pdev,
8945 tp->msi_cap + PCI_MSI_FLAGS,
8947 pci_write_config_word(tp->pdev,
8948 tp->msi_cap + PCI_MSI_FLAGS,
8949 ctrl | PCI_MSI_FLAGS_ENABLE);
8950 val = tr32(MSGINT_MODE);
8951 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8956 static void tg3_override_clk(struct tg3 *tp)
8960 switch (tg3_asic_rev(tp)) {
8962 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8963 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8964 TG3_CPMU_MAC_ORIDE_ENABLE);
8969 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8977 static void tg3_restore_clk(struct tg3 *tp)
8981 switch (tg3_asic_rev(tp)) {
8983 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8984 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8985 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8990 val = tr32(TG3_CPMU_CLCK_ORIDE);
8991 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8999 /* tp->lock is held. */
9000 static int tg3_chip_reset(struct tg3 *tp)
9003 void (*write_op)(struct tg3 *, u32, u32);
9006 if (!pci_device_is_present(tp->pdev))
9011 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9013 /* No matching tg3_nvram_unlock() after this because
9014 * chip reset below will undo the nvram lock.
9016 tp->nvram_lock_cnt = 0;
9018 /* GRC_MISC_CFG core clock reset will clear the memory
9019 * enable bit in PCI register 4 and the MSI enable bit
9020 * on some chips, so we save relevant registers here.
9022 tg3_save_pci_state(tp);
9024 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9025 tg3_flag(tp, 5755_PLUS))
9026 tw32(GRC_FASTBOOT_PC, 0);
9029 * We must avoid the readl() that normally takes place.
9030 * It locks machines, causes machine checks, and other
9031 * fun things. So, temporarily disable the 5701
9032 * hardware workaround, while we do the reset.
9034 write_op = tp->write32;
9035 if (write_op == tg3_write_flush_reg32)
9036 tp->write32 = tg3_write32;
9038 /* Prevent the irq handler from reading or writing PCI registers
9039 * during chip reset when the memory enable bit in the PCI command
9040 * register may be cleared. The chip does not generate interrupt
9041 * at this time, but the irq handler may still be called due to irq
9042 * sharing or irqpoll.
9044 tg3_flag_set(tp, CHIP_RESETTING);
9045 for (i = 0; i < tp->irq_cnt; i++) {
9046 struct tg3_napi *tnapi = &tp->napi[i];
9047 if (tnapi->hw_status) {
9048 tnapi->hw_status->status = 0;
9049 tnapi->hw_status->status_tag = 0;
9051 tnapi->last_tag = 0;
9052 tnapi->last_irq_tag = 0;
9056 for (i = 0; i < tp->irq_cnt; i++)
9057 synchronize_irq(tp->napi[i].irq_vec);
9059 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9060 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9061 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9065 val = GRC_MISC_CFG_CORECLK_RESET;
9067 if (tg3_flag(tp, PCI_EXPRESS)) {
9068 /* Force PCIe 1.0a mode */
9069 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9070 !tg3_flag(tp, 57765_PLUS) &&
9071 tr32(TG3_PCIE_PHY_TSTCTL) ==
9072 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9073 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9075 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9076 tw32(GRC_MISC_CFG, (1 << 29));
9081 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9082 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9083 tw32(GRC_VCPU_EXT_CTRL,
9084 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9087 /* Set the clock to the highest frequency to avoid timeouts. With link
9088 * aware mode, the clock speed could be slow and bootcode does not
9089 * complete within the expected time. Override the clock to allow the
9090 * bootcode to finish sooner and then restore it.
9092 tg3_override_clk(tp);
9094 /* Manage gphy power for all CPMU absent PCIe devices. */
9095 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9096 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9098 tw32(GRC_MISC_CFG, val);
9100 /* restore 5701 hardware bug workaround write method */
9101 tp->write32 = write_op;
9103 /* Unfortunately, we have to delay before the PCI read back.
9104 * Some 575X chips even will not respond to a PCI cfg access
9105 * when the reset command is given to the chip.
9107 * How do these hardware designers expect things to work
9108 * properly if the PCI write is posted for a long period
9109 * of time? It is always necessary to have some method by
9110 * which a register read back can occur to push the write
9111 * out which does the reset.
9113 * For most tg3 variants the trick below was working.
9118 /* Flush PCI posted writes. The normal MMIO registers
9119 * are inaccessible at this time so this is the only
9120 * way to make this reliably (actually, this is no longer
9121 * the case, see above). I tried to use indirect
9122 * register read/write but this upset some 5701 variants.
9124 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9128 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9131 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9135 /* Wait for link training to complete. */
9136 for (j = 0; j < 5000; j++)
9139 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9140 pci_write_config_dword(tp->pdev, 0xc4,
9141 cfg_val | (1 << 15));
9144 /* Clear the "no snoop" and "relaxed ordering" bits. */
9145 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9147 * Older PCIe devices only support the 128 byte
9148 * MPS setting. Enforce the restriction.
9150 if (!tg3_flag(tp, CPMU_PRESENT))
9151 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9152 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9154 /* Clear error status */
9155 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9156 PCI_EXP_DEVSTA_CED |
9157 PCI_EXP_DEVSTA_NFED |
9158 PCI_EXP_DEVSTA_FED |
9159 PCI_EXP_DEVSTA_URD);
9162 tg3_restore_pci_state(tp);
9164 tg3_flag_clear(tp, CHIP_RESETTING);
9165 tg3_flag_clear(tp, ERROR_PROCESSED);
9168 if (tg3_flag(tp, 5780_CLASS))
9169 val = tr32(MEMARB_MODE);
9170 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9172 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9174 tw32(0x5000, 0x400);
9177 if (tg3_flag(tp, IS_SSB_CORE)) {
9179 * BCM4785: In order to avoid repercussions from using
9180 * potentially defective internal ROM, stop the Rx RISC CPU,
9181 * which is not required.
9184 tg3_halt_cpu(tp, RX_CPU_BASE);
9187 err = tg3_poll_fw(tp);
9191 tw32(GRC_MODE, tp->grc_mode);
9193 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9196 tw32(0xc4, val | (1 << 15));
9199 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9200 tg3_asic_rev(tp) == ASIC_REV_5705) {
9201 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9202 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9203 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9204 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9207 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9208 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9210 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9211 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9216 tw32_f(MAC_MODE, val);
9219 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9223 if (tg3_flag(tp, PCI_EXPRESS) &&
9224 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9225 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9226 !tg3_flag(tp, 57765_PLUS)) {
9229 tw32(0x7c00, val | (1 << 25));
9232 tg3_restore_clk(tp);
9234 /* Reprobe ASF enable state. */
9235 tg3_flag_clear(tp, ENABLE_ASF);
9236 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9237 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9239 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9240 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9241 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9244 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9245 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9246 tg3_flag_set(tp, ENABLE_ASF);
9247 tp->last_event_jiffies = jiffies;
9248 if (tg3_flag(tp, 5750_PLUS))
9249 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9251 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9252 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9253 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9254 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9255 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9262 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9263 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9264 static void __tg3_set_rx_mode(struct net_device *);
9266 /* tp->lock is held. */
9267 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9273 tg3_write_sig_pre_reset(tp, kind);
9275 tg3_abort_hw(tp, silent);
9276 err = tg3_chip_reset(tp);
9278 __tg3_set_mac_addr(tp, false);
9280 tg3_write_sig_legacy(tp, kind);
9281 tg3_write_sig_post_reset(tp, kind);
9284 /* Save the stats across chip resets... */
9285 tg3_get_nstats(tp, &tp->net_stats_prev);
9286 tg3_get_estats(tp, &tp->estats_prev);
9288 /* And make sure the next sample is new data */
9289 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9295 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9297 struct tg3 *tp = netdev_priv(dev);
9298 struct sockaddr *addr = p;
9300 bool skip_mac_1 = false;
9302 if (!is_valid_ether_addr(addr->sa_data))
9303 return -EADDRNOTAVAIL;
9305 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9307 if (!netif_running(dev))
9310 if (tg3_flag(tp, ENABLE_ASF)) {
9311 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9313 addr0_high = tr32(MAC_ADDR_0_HIGH);
9314 addr0_low = tr32(MAC_ADDR_0_LOW);
9315 addr1_high = tr32(MAC_ADDR_1_HIGH);
9316 addr1_low = tr32(MAC_ADDR_1_LOW);
9318 /* Skip MAC addr 1 if ASF is using it. */
9319 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9320 !(addr1_high == 0 && addr1_low == 0))
9323 spin_lock_bh(&tp->lock);
9324 __tg3_set_mac_addr(tp, skip_mac_1);
9325 __tg3_set_rx_mode(dev);
9326 spin_unlock_bh(&tp->lock);
9331 /* tp->lock is held. */
9332 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9333 dma_addr_t mapping, u32 maxlen_flags,
9337 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9338 ((u64) mapping >> 32));
9340 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9341 ((u64) mapping & 0xffffffff));
9343 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9346 if (!tg3_flag(tp, 5705_PLUS))
9348 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9353 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9357 if (!tg3_flag(tp, ENABLE_TSS)) {
9358 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9359 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9360 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9362 tw32(HOSTCC_TXCOL_TICKS, 0);
9363 tw32(HOSTCC_TXMAX_FRAMES, 0);
9364 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9366 for (; i < tp->txq_cnt; i++) {
9369 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9370 tw32(reg, ec->tx_coalesce_usecs);
9371 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9372 tw32(reg, ec->tx_max_coalesced_frames);
9373 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9374 tw32(reg, ec->tx_max_coalesced_frames_irq);
9378 for (; i < tp->irq_max - 1; i++) {
9379 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9380 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9381 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9385 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9388 u32 limit = tp->rxq_cnt;
9390 if (!tg3_flag(tp, ENABLE_RSS)) {
9391 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9392 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9393 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9396 tw32(HOSTCC_RXCOL_TICKS, 0);
9397 tw32(HOSTCC_RXMAX_FRAMES, 0);
9398 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9401 for (; i < limit; i++) {
9404 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9405 tw32(reg, ec->rx_coalesce_usecs);
9406 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9407 tw32(reg, ec->rx_max_coalesced_frames);
9408 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9409 tw32(reg, ec->rx_max_coalesced_frames_irq);
9412 for (; i < tp->irq_max - 1; i++) {
9413 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9414 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9415 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9419 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9421 tg3_coal_tx_init(tp, ec);
9422 tg3_coal_rx_init(tp, ec);
9424 if (!tg3_flag(tp, 5705_PLUS)) {
9425 u32 val = ec->stats_block_coalesce_usecs;
9427 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9428 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9433 tw32(HOSTCC_STAT_COAL_TICKS, val);
9437 /* tp->lock is held. */
9438 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9442 /* Disable all transmit rings but the first. */
9443 if (!tg3_flag(tp, 5705_PLUS))
9444 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9445 else if (tg3_flag(tp, 5717_PLUS))
9446 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9447 else if (tg3_flag(tp, 57765_CLASS) ||
9448 tg3_asic_rev(tp) == ASIC_REV_5762)
9449 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9451 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9453 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9454 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9455 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9456 BDINFO_FLAGS_DISABLED);
9459 /* tp->lock is held. */
9460 static void tg3_tx_rcbs_init(struct tg3 *tp)
9463 u32 txrcb = NIC_SRAM_SEND_RCB;
9465 if (tg3_flag(tp, ENABLE_TSS))
9468 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9469 struct tg3_napi *tnapi = &tp->napi[i];
9471 if (!tnapi->tx_ring)
9474 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9475 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9476 NIC_SRAM_TX_BUFFER_DESC);
9480 /* tp->lock is held. */
9481 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9485 /* Disable all receive return rings but the first. */
9486 if (tg3_flag(tp, 5717_PLUS))
9487 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9488 else if (!tg3_flag(tp, 5705_PLUS))
9489 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9490 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9491 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9492 tg3_flag(tp, 57765_CLASS))
9493 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9495 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9497 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9498 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9499 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9500 BDINFO_FLAGS_DISABLED);
9503 /* tp->lock is held. */
9504 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9507 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9509 if (tg3_flag(tp, ENABLE_RSS))
9512 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9513 struct tg3_napi *tnapi = &tp->napi[i];
9518 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9519 (tp->rx_ret_ring_mask + 1) <<
9520 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9524 /* tp->lock is held. */
9525 static void tg3_rings_reset(struct tg3 *tp)
9529 struct tg3_napi *tnapi = &tp->napi[0];
9531 tg3_tx_rcbs_disable(tp);
9533 tg3_rx_ret_rcbs_disable(tp);
9535 /* Disable interrupts */
9536 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9537 tp->napi[0].chk_msi_cnt = 0;
9538 tp->napi[0].last_rx_cons = 0;
9539 tp->napi[0].last_tx_cons = 0;
9541 /* Zero mailbox registers. */
9542 if (tg3_flag(tp, SUPPORT_MSIX)) {
9543 for (i = 1; i < tp->irq_max; i++) {
9544 tp->napi[i].tx_prod = 0;
9545 tp->napi[i].tx_cons = 0;
9546 if (tg3_flag(tp, ENABLE_TSS))
9547 tw32_mailbox(tp->napi[i].prodmbox, 0);
9548 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9549 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9550 tp->napi[i].chk_msi_cnt = 0;
9551 tp->napi[i].last_rx_cons = 0;
9552 tp->napi[i].last_tx_cons = 0;
9554 if (!tg3_flag(tp, ENABLE_TSS))
9555 tw32_mailbox(tp->napi[0].prodmbox, 0);
9557 tp->napi[0].tx_prod = 0;
9558 tp->napi[0].tx_cons = 0;
9559 tw32_mailbox(tp->napi[0].prodmbox, 0);
9560 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9563 /* Make sure the NIC-based send BD rings are disabled. */
9564 if (!tg3_flag(tp, 5705_PLUS)) {
9565 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9566 for (i = 0; i < 16; i++)
9567 tw32_tx_mbox(mbox + i * 8, 0);
9570 /* Clear status block in ram. */
9571 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9573 /* Set status block DMA address */
9574 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9575 ((u64) tnapi->status_mapping >> 32));
9576 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9577 ((u64) tnapi->status_mapping & 0xffffffff));
9579 stblk = HOSTCC_STATBLCK_RING1;
9581 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9582 u64 mapping = (u64)tnapi->status_mapping;
9583 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9584 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9587 /* Clear status block in ram. */
9588 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9591 tg3_tx_rcbs_init(tp);
9592 tg3_rx_ret_rcbs_init(tp);
9595 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9597 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9599 if (!tg3_flag(tp, 5750_PLUS) ||
9600 tg3_flag(tp, 5780_CLASS) ||
9601 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9602 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9603 tg3_flag(tp, 57765_PLUS))
9604 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9605 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9606 tg3_asic_rev(tp) == ASIC_REV_5787)
9607 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9609 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9611 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9612 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9614 val = min(nic_rep_thresh, host_rep_thresh);
9615 tw32(RCVBDI_STD_THRESH, val);
9617 if (tg3_flag(tp, 57765_PLUS))
9618 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9620 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9623 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9625 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9627 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9628 tw32(RCVBDI_JUMBO_THRESH, val);
9630 if (tg3_flag(tp, 57765_PLUS))
9631 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9634 static inline u32 calc_crc(unsigned char *buf, int len)
9642 for (j = 0; j < len; j++) {
9645 for (k = 0; k < 8; k++) {
9658 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9660 /* accept or reject all multicast frames */
9661 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9662 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9663 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9664 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9667 static void __tg3_set_rx_mode(struct net_device *dev)
9669 struct tg3 *tp = netdev_priv(dev);
9672 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9673 RX_MODE_KEEP_VLAN_TAG);
9675 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9676 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9679 if (!tg3_flag(tp, ENABLE_ASF))
9680 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9683 if (dev->flags & IFF_PROMISC) {
9684 /* Promiscuous mode. */
9685 rx_mode |= RX_MODE_PROMISC;
9686 } else if (dev->flags & IFF_ALLMULTI) {
9687 /* Accept all multicast. */
9688 tg3_set_multi(tp, 1);
9689 } else if (netdev_mc_empty(dev)) {
9690 /* Reject all multicast. */
9691 tg3_set_multi(tp, 0);
9693 /* Accept one or more multicast(s). */
9694 struct netdev_hw_addr *ha;
9695 u32 mc_filter[4] = { 0, };
9700 netdev_for_each_mc_addr(ha, dev) {
9701 crc = calc_crc(ha->addr, ETH_ALEN);
9703 regidx = (bit & 0x60) >> 5;
9705 mc_filter[regidx] |= (1 << bit);
9708 tw32(MAC_HASH_REG_0, mc_filter[0]);
9709 tw32(MAC_HASH_REG_1, mc_filter[1]);
9710 tw32(MAC_HASH_REG_2, mc_filter[2]);
9711 tw32(MAC_HASH_REG_3, mc_filter[3]);
9714 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9715 rx_mode |= RX_MODE_PROMISC;
9716 } else if (!(dev->flags & IFF_PROMISC)) {
9717 /* Add all entries into to the mac addr filter list */
9719 struct netdev_hw_addr *ha;
9721 netdev_for_each_uc_addr(ha, dev) {
9722 __tg3_set_one_mac_addr(tp, ha->addr,
9723 i + TG3_UCAST_ADDR_IDX(tp));
9728 if (rx_mode != tp->rx_mode) {
9729 tp->rx_mode = rx_mode;
9730 tw32_f(MAC_RX_MODE, rx_mode);
9735 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9739 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9740 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9743 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9747 if (!tg3_flag(tp, SUPPORT_MSIX))
9750 if (tp->rxq_cnt == 1) {
9751 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9755 /* Validate table against current IRQ count */
9756 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9757 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9761 if (i != TG3_RSS_INDIR_TBL_SIZE)
9762 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9765 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9768 u32 reg = MAC_RSS_INDIR_TBL_0;
9770 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9771 u32 val = tp->rss_ind_tbl[i];
9773 for (; i % 8; i++) {
9775 val |= tp->rss_ind_tbl[i];
9782 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9784 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9785 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9787 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9790 /* tp->lock is held. */
9791 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9793 u32 val, rdmac_mode;
9795 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9797 tg3_disable_ints(tp);
9801 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9803 if (tg3_flag(tp, INIT_COMPLETE))
9804 tg3_abort_hw(tp, 1);
9806 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9807 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9808 tg3_phy_pull_config(tp);
9809 tg3_eee_pull_config(tp, NULL);
9810 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9813 /* Enable MAC control of LPI */
9814 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9820 err = tg3_chip_reset(tp);
9824 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9826 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9827 val = tr32(TG3_CPMU_CTRL);
9828 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9829 tw32(TG3_CPMU_CTRL, val);
9831 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9832 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9833 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9834 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9836 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9837 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9838 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9839 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9841 val = tr32(TG3_CPMU_HST_ACC);
9842 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9843 val |= CPMU_HST_ACC_MACCLK_6_25;
9844 tw32(TG3_CPMU_HST_ACC, val);
9847 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9848 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9849 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9850 PCIE_PWR_MGMT_L1_THRESH_4MS;
9851 tw32(PCIE_PWR_MGMT_THRESH, val);
9853 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9854 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9856 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9858 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9859 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9862 if (tg3_flag(tp, L1PLLPD_EN)) {
9863 u32 grc_mode = tr32(GRC_MODE);
9865 /* Access the lower 1K of PL PCIE block registers. */
9866 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9867 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9869 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9870 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9871 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9873 tw32(GRC_MODE, grc_mode);
9876 if (tg3_flag(tp, 57765_CLASS)) {
9877 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9878 u32 grc_mode = tr32(GRC_MODE);
9880 /* Access the lower 1K of PL PCIE block registers. */
9881 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9882 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9884 val = tr32(TG3_PCIE_TLDLPL_PORT +
9885 TG3_PCIE_PL_LO_PHYCTL5);
9886 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9887 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9889 tw32(GRC_MODE, grc_mode);
9892 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9895 /* Fix transmit hangs */
9896 val = tr32(TG3_CPMU_PADRNG_CTL);
9897 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9898 tw32(TG3_CPMU_PADRNG_CTL, val);
9900 grc_mode = tr32(GRC_MODE);
9902 /* Access the lower 1K of DL PCIE block registers. */
9903 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9904 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9906 val = tr32(TG3_PCIE_TLDLPL_PORT +
9907 TG3_PCIE_DL_LO_FTSMAX);
9908 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9909 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9910 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9912 tw32(GRC_MODE, grc_mode);
9915 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9916 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9917 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9918 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9921 /* This works around an issue with Athlon chipsets on
9922 * B3 tigon3 silicon. This bit has no effect on any
9923 * other revision. But do not set this on PCI Express
9924 * chips and don't even touch the clocks if the CPMU is present.
9926 if (!tg3_flag(tp, CPMU_PRESENT)) {
9927 if (!tg3_flag(tp, PCI_EXPRESS))
9928 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9929 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9932 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9933 tg3_flag(tp, PCIX_MODE)) {
9934 val = tr32(TG3PCI_PCISTATE);
9935 val |= PCISTATE_RETRY_SAME_DMA;
9936 tw32(TG3PCI_PCISTATE, val);
9939 if (tg3_flag(tp, ENABLE_APE)) {
9940 /* Allow reads and writes to the
9941 * APE register and memory space.
9943 val = tr32(TG3PCI_PCISTATE);
9944 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9945 PCISTATE_ALLOW_APE_SHMEM_WR |
9946 PCISTATE_ALLOW_APE_PSPACE_WR;
9947 tw32(TG3PCI_PCISTATE, val);
9950 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9951 /* Enable some hw fixes. */
9952 val = tr32(TG3PCI_MSI_DATA);
9953 val |= (1 << 26) | (1 << 28) | (1 << 29);
9954 tw32(TG3PCI_MSI_DATA, val);
9957 /* Descriptor ring init may make accesses to the
9958 * NIC SRAM area to setup the TX descriptors, so we
9959 * can only do this after the hardware has been
9960 * successfully reset.
9962 err = tg3_init_rings(tp);
9966 if (tg3_flag(tp, 57765_PLUS)) {
9967 val = tr32(TG3PCI_DMA_RW_CTRL) &
9968 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9969 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9970 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9971 if (!tg3_flag(tp, 57765_CLASS) &&
9972 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9973 tg3_asic_rev(tp) != ASIC_REV_5762)
9974 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9975 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9976 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9977 tg3_asic_rev(tp) != ASIC_REV_5761) {
9978 /* This value is determined during the probe time DMA
9979 * engine test, tg3_test_dma.
9981 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9984 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9985 GRC_MODE_4X_NIC_SEND_RINGS |
9986 GRC_MODE_NO_TX_PHDR_CSUM |
9987 GRC_MODE_NO_RX_PHDR_CSUM);
9988 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9990 /* Pseudo-header checksum is done by hardware logic and not
9991 * the offload processers, so make the chip do the pseudo-
9992 * header checksums on receive. For transmit it is more
9993 * convenient to do the pseudo-header checksum in software
9994 * as Linux does that on transmit for us in all cases.
9996 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9998 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10000 tw32(TG3_RX_PTP_CTL,
10001 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10003 if (tg3_flag(tp, PTP_CAPABLE))
10004 val |= GRC_MODE_TIME_SYNC_ENABLE;
10006 tw32(GRC_MODE, tp->grc_mode | val);
10008 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10009 val = tr32(GRC_MISC_CFG);
10011 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10012 tw32(GRC_MISC_CFG, val);
10014 /* Initialize MBUF/DESC pool. */
10015 if (tg3_flag(tp, 5750_PLUS)) {
10017 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10018 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10019 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10020 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10022 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10023 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10024 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10025 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10028 fw_len = tp->fw_len;
10029 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10030 tw32(BUFMGR_MB_POOL_ADDR,
10031 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10032 tw32(BUFMGR_MB_POOL_SIZE,
10033 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10036 if (tp->dev->mtu <= ETH_DATA_LEN) {
10037 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10038 tp->bufmgr_config.mbuf_read_dma_low_water);
10039 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10040 tp->bufmgr_config.mbuf_mac_rx_low_water);
10041 tw32(BUFMGR_MB_HIGH_WATER,
10042 tp->bufmgr_config.mbuf_high_water);
10044 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10045 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10046 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10047 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10048 tw32(BUFMGR_MB_HIGH_WATER,
10049 tp->bufmgr_config.mbuf_high_water_jumbo);
10051 tw32(BUFMGR_DMA_LOW_WATER,
10052 tp->bufmgr_config.dma_low_water);
10053 tw32(BUFMGR_DMA_HIGH_WATER,
10054 tp->bufmgr_config.dma_high_water);
10056 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10057 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10058 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10059 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10060 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10061 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10062 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10063 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10064 tw32(BUFMGR_MODE, val);
10065 for (i = 0; i < 2000; i++) {
10066 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10071 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10075 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10076 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10078 tg3_setup_rxbd_thresholds(tp);
10080 /* Initialize TG3_BDINFO's at:
10081 * RCVDBDI_STD_BD: standard eth size rx ring
10082 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10083 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10086 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10087 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10088 * ring attribute flags
10089 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10091 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10092 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10094 * The size of each ring is fixed in the firmware, but the location is
10097 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10098 ((u64) tpr->rx_std_mapping >> 32));
10099 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10100 ((u64) tpr->rx_std_mapping & 0xffffffff));
10101 if (!tg3_flag(tp, 5717_PLUS))
10102 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10103 NIC_SRAM_RX_BUFFER_DESC);
10105 /* Disable the mini ring */
10106 if (!tg3_flag(tp, 5705_PLUS))
10107 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10108 BDINFO_FLAGS_DISABLED);
10110 /* Program the jumbo buffer descriptor ring control
10111 * blocks on those devices that have them.
10113 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10114 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10116 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10117 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10118 ((u64) tpr->rx_jmb_mapping >> 32));
10119 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10120 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10121 val = TG3_RX_JMB_RING_SIZE(tp) <<
10122 BDINFO_FLAGS_MAXLEN_SHIFT;
10123 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10124 val | BDINFO_FLAGS_USE_EXT_RECV);
10125 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10126 tg3_flag(tp, 57765_CLASS) ||
10127 tg3_asic_rev(tp) == ASIC_REV_5762)
10128 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10129 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10131 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10132 BDINFO_FLAGS_DISABLED);
10135 if (tg3_flag(tp, 57765_PLUS)) {
10136 val = TG3_RX_STD_RING_SIZE(tp);
10137 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10138 val |= (TG3_RX_STD_DMA_SZ << 2);
10140 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10142 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10144 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10146 tpr->rx_std_prod_idx = tp->rx_pending;
10147 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10149 tpr->rx_jmb_prod_idx =
10150 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10151 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10153 tg3_rings_reset(tp);
10155 /* Initialize MAC address and backoff seed. */
10156 __tg3_set_mac_addr(tp, false);
10158 /* MTU + ethernet header + FCS + optional VLAN tag */
10159 tw32(MAC_RX_MTU_SIZE,
10160 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10162 /* The slot time is changed by tg3_setup_phy if we
10163 * run at gigabit with half duplex.
10165 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10166 (6 << TX_LENGTHS_IPG_SHIFT) |
10167 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10169 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10170 tg3_asic_rev(tp) == ASIC_REV_5762)
10171 val |= tr32(MAC_TX_LENGTHS) &
10172 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10173 TX_LENGTHS_CNT_DWN_VAL_MSK);
10175 tw32(MAC_TX_LENGTHS, val);
10177 /* Receive rules. */
10178 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10179 tw32(RCVLPC_CONFIG, 0x0181);
10181 /* Calculate RDMAC_MODE setting early, we need it to determine
10182 * the RCVLPC_STATE_ENABLE mask.
10184 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10185 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10186 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10187 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10188 RDMAC_MODE_LNGREAD_ENAB);
10190 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10191 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10193 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10194 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10195 tg3_asic_rev(tp) == ASIC_REV_57780)
10196 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10197 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10198 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10200 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10201 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10202 if (tg3_flag(tp, TSO_CAPABLE) &&
10203 tg3_asic_rev(tp) == ASIC_REV_5705) {
10204 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10205 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10206 !tg3_flag(tp, IS_5788)) {
10207 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10211 if (tg3_flag(tp, PCI_EXPRESS))
10212 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10214 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10216 if (tp->dev->mtu <= ETH_DATA_LEN) {
10217 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10218 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10222 if (tg3_flag(tp, HW_TSO_1) ||
10223 tg3_flag(tp, HW_TSO_2) ||
10224 tg3_flag(tp, HW_TSO_3))
10225 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10227 if (tg3_flag(tp, 57765_PLUS) ||
10228 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10229 tg3_asic_rev(tp) == ASIC_REV_57780)
10230 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10232 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10233 tg3_asic_rev(tp) == ASIC_REV_5762)
10234 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10236 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10237 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10238 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10239 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10240 tg3_flag(tp, 57765_PLUS)) {
10243 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10244 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10246 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10248 val = tr32(tgtreg);
10249 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5762) {
10251 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10252 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10253 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10254 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10255 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10256 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10258 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10261 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10262 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10263 tg3_asic_rev(tp) == ASIC_REV_5762) {
10266 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10267 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10269 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10271 val = tr32(tgtreg);
10273 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10274 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10277 /* Receive/send statistics. */
10278 if (tg3_flag(tp, 5750_PLUS)) {
10279 val = tr32(RCVLPC_STATS_ENABLE);
10280 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10281 tw32(RCVLPC_STATS_ENABLE, val);
10282 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10283 tg3_flag(tp, TSO_CAPABLE)) {
10284 val = tr32(RCVLPC_STATS_ENABLE);
10285 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10286 tw32(RCVLPC_STATS_ENABLE, val);
10288 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10290 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10291 tw32(SNDDATAI_STATSENAB, 0xffffff);
10292 tw32(SNDDATAI_STATSCTRL,
10293 (SNDDATAI_SCTRL_ENABLE |
10294 SNDDATAI_SCTRL_FASTUPD));
10296 /* Setup host coalescing engine. */
10297 tw32(HOSTCC_MODE, 0);
10298 for (i = 0; i < 2000; i++) {
10299 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10304 __tg3_set_coalesce(tp, &tp->coal);
10306 if (!tg3_flag(tp, 5705_PLUS)) {
10307 /* Status/statistics block address. See tg3_timer,
10308 * the tg3_periodic_fetch_stats call there, and
10309 * tg3_get_stats to see how this works for 5705/5750 chips.
10311 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10312 ((u64) tp->stats_mapping >> 32));
10313 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10314 ((u64) tp->stats_mapping & 0xffffffff));
10315 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10317 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10319 /* Clear statistics and status block memory areas */
10320 for (i = NIC_SRAM_STATS_BLK;
10321 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10322 i += sizeof(u32)) {
10323 tg3_write_mem(tp, i, 0);
10328 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10330 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10331 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10332 if (!tg3_flag(tp, 5705_PLUS))
10333 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10335 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10336 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10337 /* reset to prevent losing 1st rx packet intermittently */
10338 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10342 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10343 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10344 MAC_MODE_FHDE_ENABLE;
10345 if (tg3_flag(tp, ENABLE_APE))
10346 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10347 if (!tg3_flag(tp, 5705_PLUS) &&
10348 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10349 tg3_asic_rev(tp) != ASIC_REV_5700)
10350 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10351 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10354 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10355 * If TG3_FLAG_IS_NIC is zero, we should read the
10356 * register to preserve the GPIO settings for LOMs. The GPIOs,
10357 * whether used as inputs or outputs, are set by boot code after
10360 if (!tg3_flag(tp, IS_NIC)) {
10363 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10364 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10365 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10367 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10368 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10369 GRC_LCLCTRL_GPIO_OUTPUT3;
10371 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10372 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10374 tp->grc_local_ctrl &= ~gpio_mask;
10375 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10377 /* GPIO1 must be driven high for eeprom write protect */
10378 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10379 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10380 GRC_LCLCTRL_GPIO_OUTPUT1);
10382 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10385 if (tg3_flag(tp, USING_MSIX)) {
10386 val = tr32(MSGINT_MODE);
10387 val |= MSGINT_MODE_ENABLE;
10388 if (tp->irq_cnt > 1)
10389 val |= MSGINT_MODE_MULTIVEC_EN;
10390 if (!tg3_flag(tp, 1SHOT_MSI))
10391 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10392 tw32(MSGINT_MODE, val);
10395 if (!tg3_flag(tp, 5705_PLUS)) {
10396 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10400 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10401 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10402 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10403 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10404 WDMAC_MODE_LNGREAD_ENAB);
10406 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10407 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10408 if (tg3_flag(tp, TSO_CAPABLE) &&
10409 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10410 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10412 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10413 !tg3_flag(tp, IS_5788)) {
10414 val |= WDMAC_MODE_RX_ACCEL;
10418 /* Enable host coalescing bug fix */
10419 if (tg3_flag(tp, 5755_PLUS))
10420 val |= WDMAC_MODE_STATUS_TAG_FIX;
10422 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10423 val |= WDMAC_MODE_BURST_ALL_DATA;
10425 tw32_f(WDMAC_MODE, val);
10428 if (tg3_flag(tp, PCIX_MODE)) {
10431 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10433 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10434 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10435 pcix_cmd |= PCI_X_CMD_READ_2K;
10436 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10437 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10438 pcix_cmd |= PCI_X_CMD_READ_2K;
10440 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10444 tw32_f(RDMAC_MODE, rdmac_mode);
10447 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10448 tg3_asic_rev(tp) == ASIC_REV_5720) {
10449 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10450 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10453 if (i < TG3_NUM_RDMA_CHANNELS) {
10454 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10455 val |= tg3_lso_rd_dma_workaround_bit(tp);
10456 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10457 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10461 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10462 if (!tg3_flag(tp, 5705_PLUS))
10463 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10465 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10466 tw32(SNDDATAC_MODE,
10467 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10469 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10471 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10472 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10473 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10474 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10475 val |= RCVDBDI_MODE_LRG_RING_SZ;
10476 tw32(RCVDBDI_MODE, val);
10477 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10478 if (tg3_flag(tp, HW_TSO_1) ||
10479 tg3_flag(tp, HW_TSO_2) ||
10480 tg3_flag(tp, HW_TSO_3))
10481 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10482 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10483 if (tg3_flag(tp, ENABLE_TSS))
10484 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10485 tw32(SNDBDI_MODE, val);
10486 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10488 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10489 err = tg3_load_5701_a0_firmware_fix(tp);
10494 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10495 /* Ignore any errors for the firmware download. If download
10496 * fails, the device will operate with EEE disabled
10498 tg3_load_57766_firmware(tp);
10501 if (tg3_flag(tp, TSO_CAPABLE)) {
10502 err = tg3_load_tso_firmware(tp);
10507 tp->tx_mode = TX_MODE_ENABLE;
10509 if (tg3_flag(tp, 5755_PLUS) ||
10510 tg3_asic_rev(tp) == ASIC_REV_5906)
10511 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10513 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10514 tg3_asic_rev(tp) == ASIC_REV_5762) {
10515 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10516 tp->tx_mode &= ~val;
10517 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10520 tw32_f(MAC_TX_MODE, tp->tx_mode);
10523 if (tg3_flag(tp, ENABLE_RSS)) {
10524 tg3_rss_write_indir_tbl(tp);
10526 /* Setup the "secret" hash key. */
10527 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10528 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10529 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10530 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10531 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10532 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10533 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10534 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10535 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10536 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10539 tp->rx_mode = RX_MODE_ENABLE;
10540 if (tg3_flag(tp, 5755_PLUS))
10541 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10543 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10544 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10546 if (tg3_flag(tp, ENABLE_RSS))
10547 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10548 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10549 RX_MODE_RSS_IPV6_HASH_EN |
10550 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10551 RX_MODE_RSS_IPV4_HASH_EN |
10552 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10554 tw32_f(MAC_RX_MODE, tp->rx_mode);
10557 tw32(MAC_LED_CTRL, tp->led_ctrl);
10559 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10560 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10561 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10564 tw32_f(MAC_RX_MODE, tp->rx_mode);
10567 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10568 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10569 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10570 /* Set drive transmission level to 1.2V */
10571 /* only if the signal pre-emphasis bit is not set */
10572 val = tr32(MAC_SERDES_CFG);
10575 tw32(MAC_SERDES_CFG, val);
10577 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10578 tw32(MAC_SERDES_CFG, 0x616000);
10581 /* Prevent chip from dropping frames when flow control
10584 if (tg3_flag(tp, 57765_CLASS))
10588 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10590 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10591 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10592 /* Use hardware link auto-negotiation */
10593 tg3_flag_set(tp, HW_AUTONEG);
10596 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10597 tg3_asic_rev(tp) == ASIC_REV_5714) {
10600 tmp = tr32(SERDES_RX_CTRL);
10601 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10602 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10603 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10604 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10607 if (!tg3_flag(tp, USE_PHYLIB)) {
10608 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10609 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10611 err = tg3_setup_phy(tp, false);
10615 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10616 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10619 /* Clear CRC stats. */
10620 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10621 tg3_writephy(tp, MII_TG3_TEST1,
10622 tmp | MII_TG3_TEST1_CRC_EN);
10623 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10628 __tg3_set_rx_mode(tp->dev);
10630 /* Initialize receive rules. */
10631 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10632 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10633 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10634 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10636 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10640 if (tg3_flag(tp, ENABLE_ASF))
10644 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10646 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10648 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10650 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10652 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10654 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10656 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10658 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10660 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10662 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10664 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10666 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10668 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10670 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10678 if (tg3_flag(tp, ENABLE_APE))
10679 /* Write our heartbeat update interval to APE. */
10680 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10681 APE_HOST_HEARTBEAT_INT_DISABLE);
10683 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10688 /* Called at device open time to get the chip ready for
10689 * packet processing. Invoked with tp->lock held.
10691 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10693 /* Chip may have been just powered on. If so, the boot code may still
10694 * be running initialization. Wait for it to finish to avoid races in
10695 * accessing the hardware.
10697 tg3_enable_register_access(tp);
10700 tg3_switch_clocks(tp);
10702 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10704 return tg3_reset_hw(tp, reset_phy);
10707 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10711 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10712 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10714 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10717 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10718 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10719 memset(ocir, 0, TG3_OCIR_LEN);
10723 /* sysfs attributes for hwmon */
10724 static ssize_t tg3_show_temp(struct device *dev,
10725 struct device_attribute *devattr, char *buf)
10727 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10728 struct tg3 *tp = dev_get_drvdata(dev);
10731 spin_lock_bh(&tp->lock);
10732 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10733 sizeof(temperature));
10734 spin_unlock_bh(&tp->lock);
10735 return sprintf(buf, "%u\n", temperature);
10739 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10740 TG3_TEMP_SENSOR_OFFSET);
10741 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10742 TG3_TEMP_CAUTION_OFFSET);
10743 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10744 TG3_TEMP_MAX_OFFSET);
10746 static struct attribute *tg3_attrs[] = {
10747 &sensor_dev_attr_temp1_input.dev_attr.attr,
10748 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10749 &sensor_dev_attr_temp1_max.dev_attr.attr,
10752 ATTRIBUTE_GROUPS(tg3);
10754 static void tg3_hwmon_close(struct tg3 *tp)
10756 if (tp->hwmon_dev) {
10757 hwmon_device_unregister(tp->hwmon_dev);
10758 tp->hwmon_dev = NULL;
10762 static void tg3_hwmon_open(struct tg3 *tp)
10766 struct pci_dev *pdev = tp->pdev;
10767 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10769 tg3_sd_scan_scratchpad(tp, ocirs);
10771 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10772 if (!ocirs[i].src_data_length)
10775 size += ocirs[i].src_hdr_length;
10776 size += ocirs[i].src_data_length;
10782 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10784 if (IS_ERR(tp->hwmon_dev)) {
10785 tp->hwmon_dev = NULL;
10786 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10791 #define TG3_STAT_ADD32(PSTAT, REG) \
10792 do { u32 __val = tr32(REG); \
10793 (PSTAT)->low += __val; \
10794 if ((PSTAT)->low < __val) \
10795 (PSTAT)->high += 1; \
10798 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10800 struct tg3_hw_stats *sp = tp->hw_stats;
10805 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10806 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10807 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10808 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10809 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10810 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10811 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10812 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10813 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10814 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10815 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10816 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10817 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10818 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10819 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10820 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10823 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10824 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10825 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10826 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10829 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10830 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10831 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10832 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10833 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10834 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10835 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10836 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10837 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10838 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10839 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10840 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10841 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10842 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10844 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10845 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10846 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10847 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10848 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10849 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10851 u32 val = tr32(HOSTCC_FLOW_ATTN);
10852 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10854 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10855 sp->rx_discards.low += val;
10856 if (sp->rx_discards.low < val)
10857 sp->rx_discards.high += 1;
10859 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10861 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10864 static void tg3_chk_missed_msi(struct tg3 *tp)
10868 for (i = 0; i < tp->irq_cnt; i++) {
10869 struct tg3_napi *tnapi = &tp->napi[i];
10871 if (tg3_has_work(tnapi)) {
10872 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10873 tnapi->last_tx_cons == tnapi->tx_cons) {
10874 if (tnapi->chk_msi_cnt < 1) {
10875 tnapi->chk_msi_cnt++;
10881 tnapi->chk_msi_cnt = 0;
10882 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10883 tnapi->last_tx_cons = tnapi->tx_cons;
10887 static void tg3_timer(unsigned long __opaque)
10889 struct tg3 *tp = (struct tg3 *) __opaque;
10891 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10892 goto restart_timer;
10894 spin_lock(&tp->lock);
10896 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10897 tg3_flag(tp, 57765_CLASS))
10898 tg3_chk_missed_msi(tp);
10900 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10901 /* BCM4785: Flush posted writes from GbE to host memory. */
10905 if (!tg3_flag(tp, TAGGED_STATUS)) {
10906 /* All of this garbage is because when using non-tagged
10907 * IRQ status the mailbox/status_block protocol the chip
10908 * uses with the cpu is race prone.
10910 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10911 tw32(GRC_LOCAL_CTRL,
10912 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10914 tw32(HOSTCC_MODE, tp->coalesce_mode |
10915 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10918 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10919 spin_unlock(&tp->lock);
10920 tg3_reset_task_schedule(tp);
10921 goto restart_timer;
10925 /* This part only runs once per second. */
10926 if (!--tp->timer_counter) {
10927 if (tg3_flag(tp, 5705_PLUS))
10928 tg3_periodic_fetch_stats(tp);
10930 if (tp->setlpicnt && !--tp->setlpicnt)
10931 tg3_phy_eee_enable(tp);
10933 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10937 mac_stat = tr32(MAC_STATUS);
10940 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10941 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10943 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10947 tg3_setup_phy(tp, false);
10948 } else if (tg3_flag(tp, POLL_SERDES)) {
10949 u32 mac_stat = tr32(MAC_STATUS);
10950 int need_setup = 0;
10953 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10956 if (!tp->link_up &&
10957 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10958 MAC_STATUS_SIGNAL_DET))) {
10962 if (!tp->serdes_counter) {
10965 ~MAC_MODE_PORT_MODE_MASK));
10967 tw32_f(MAC_MODE, tp->mac_mode);
10970 tg3_setup_phy(tp, false);
10972 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10973 tg3_flag(tp, 5780_CLASS)) {
10974 tg3_serdes_parallel_detect(tp);
10975 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10976 u32 cpmu = tr32(TG3_CPMU_STATUS);
10977 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10978 TG3_CPMU_STATUS_LINK_MASK);
10980 if (link_up != tp->link_up)
10981 tg3_setup_phy(tp, false);
10984 tp->timer_counter = tp->timer_multiplier;
10987 /* Heartbeat is only sent once every 2 seconds.
10989 * The heartbeat is to tell the ASF firmware that the host
10990 * driver is still alive. In the event that the OS crashes,
10991 * ASF needs to reset the hardware to free up the FIFO space
10992 * that may be filled with rx packets destined for the host.
10993 * If the FIFO is full, ASF will no longer function properly.
10995 * Unintended resets have been reported on real time kernels
10996 * where the timer doesn't run on time. Netpoll will also have
10999 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11000 * to check the ring condition when the heartbeat is expiring
11001 * before doing the reset. This will prevent most unintended
11004 if (!--tp->asf_counter) {
11005 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11006 tg3_wait_for_event_ack(tp);
11008 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11009 FWCMD_NICDRV_ALIVE3);
11010 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11011 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11012 TG3_FW_UPDATE_TIMEOUT_SEC);
11014 tg3_generate_fw_event(tp);
11016 tp->asf_counter = tp->asf_multiplier;
11019 spin_unlock(&tp->lock);
11022 tp->timer.expires = jiffies + tp->timer_offset;
11023 add_timer(&tp->timer);
11026 static void tg3_timer_init(struct tg3 *tp)
11028 if (tg3_flag(tp, TAGGED_STATUS) &&
11029 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11030 !tg3_flag(tp, 57765_CLASS))
11031 tp->timer_offset = HZ;
11033 tp->timer_offset = HZ / 10;
11035 BUG_ON(tp->timer_offset > HZ);
11037 tp->timer_multiplier = (HZ / tp->timer_offset);
11038 tp->asf_multiplier = (HZ / tp->timer_offset) *
11039 TG3_FW_UPDATE_FREQ_SEC;
11041 init_timer(&tp->timer);
11042 tp->timer.data = (unsigned long) tp;
11043 tp->timer.function = tg3_timer;
11046 static void tg3_timer_start(struct tg3 *tp)
11048 tp->asf_counter = tp->asf_multiplier;
11049 tp->timer_counter = tp->timer_multiplier;
11051 tp->timer.expires = jiffies + tp->timer_offset;
11052 add_timer(&tp->timer);
11055 static void tg3_timer_stop(struct tg3 *tp)
11057 del_timer_sync(&tp->timer);
11060 /* Restart hardware after configuration changes, self-test, etc.
11061 * Invoked with tp->lock held.
11063 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11064 __releases(tp->lock)
11065 __acquires(tp->lock)
11069 err = tg3_init_hw(tp, reset_phy);
11071 netdev_err(tp->dev,
11072 "Failed to re-initialize device, aborting\n");
11073 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11074 tg3_full_unlock(tp);
11075 tg3_timer_stop(tp);
11077 tg3_napi_enable(tp);
11078 dev_close(tp->dev);
11079 tg3_full_lock(tp, 0);
11084 static void tg3_reset_task(struct work_struct *work)
11086 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11089 tg3_full_lock(tp, 0);
11091 if (!netif_running(tp->dev)) {
11092 tg3_flag_clear(tp, RESET_TASK_PENDING);
11093 tg3_full_unlock(tp);
11097 tg3_full_unlock(tp);
11101 tg3_netif_stop(tp);
11103 tg3_full_lock(tp, 1);
11105 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11106 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11107 tp->write32_rx_mbox = tg3_write_flush_reg32;
11108 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11109 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11112 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11113 err = tg3_init_hw(tp, true);
11117 tg3_netif_start(tp);
11120 tg3_full_unlock(tp);
11125 tg3_flag_clear(tp, RESET_TASK_PENDING);
11128 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11131 unsigned long flags;
11133 struct tg3_napi *tnapi = &tp->napi[irq_num];
11135 if (tp->irq_cnt == 1)
11136 name = tp->dev->name;
11138 name = &tnapi->irq_lbl[0];
11139 if (tnapi->tx_buffers && tnapi->rx_rcb)
11140 snprintf(name, IFNAMSIZ,
11141 "%s-txrx-%d", tp->dev->name, irq_num);
11142 else if (tnapi->tx_buffers)
11143 snprintf(name, IFNAMSIZ,
11144 "%s-tx-%d", tp->dev->name, irq_num);
11145 else if (tnapi->rx_rcb)
11146 snprintf(name, IFNAMSIZ,
11147 "%s-rx-%d", tp->dev->name, irq_num);
11149 snprintf(name, IFNAMSIZ,
11150 "%s-%d", tp->dev->name, irq_num);
11151 name[IFNAMSIZ-1] = 0;
11154 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11156 if (tg3_flag(tp, 1SHOT_MSI))
11157 fn = tg3_msi_1shot;
11160 fn = tg3_interrupt;
11161 if (tg3_flag(tp, TAGGED_STATUS))
11162 fn = tg3_interrupt_tagged;
11163 flags = IRQF_SHARED;
11166 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11169 static int tg3_test_interrupt(struct tg3 *tp)
11171 struct tg3_napi *tnapi = &tp->napi[0];
11172 struct net_device *dev = tp->dev;
11173 int err, i, intr_ok = 0;
11176 if (!netif_running(dev))
11179 tg3_disable_ints(tp);
11181 free_irq(tnapi->irq_vec, tnapi);
11184 * Turn off MSI one shot mode. Otherwise this test has no
11185 * observable way to know whether the interrupt was delivered.
11187 if (tg3_flag(tp, 57765_PLUS)) {
11188 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11189 tw32(MSGINT_MODE, val);
11192 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11193 IRQF_SHARED, dev->name, tnapi);
11197 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11198 tg3_enable_ints(tp);
11200 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11203 for (i = 0; i < 5; i++) {
11204 u32 int_mbox, misc_host_ctrl;
11206 int_mbox = tr32_mailbox(tnapi->int_mbox);
11207 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11209 if ((int_mbox != 0) ||
11210 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11215 if (tg3_flag(tp, 57765_PLUS) &&
11216 tnapi->hw_status->status_tag != tnapi->last_tag)
11217 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11222 tg3_disable_ints(tp);
11224 free_irq(tnapi->irq_vec, tnapi);
11226 err = tg3_request_irq(tp, 0);
11232 /* Reenable MSI one shot mode. */
11233 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11234 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11235 tw32(MSGINT_MODE, val);
11243 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11244 * successfully restored
11246 static int tg3_test_msi(struct tg3 *tp)
11251 if (!tg3_flag(tp, USING_MSI))
11254 /* Turn off SERR reporting in case MSI terminates with Master
11257 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11258 pci_write_config_word(tp->pdev, PCI_COMMAND,
11259 pci_cmd & ~PCI_COMMAND_SERR);
11261 err = tg3_test_interrupt(tp);
11263 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11268 /* other failures */
11272 /* MSI test failed, go back to INTx mode */
11273 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11274 "to INTx mode. Please report this failure to the PCI "
11275 "maintainer and include system chipset information\n");
11277 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11279 pci_disable_msi(tp->pdev);
11281 tg3_flag_clear(tp, USING_MSI);
11282 tp->napi[0].irq_vec = tp->pdev->irq;
11284 err = tg3_request_irq(tp, 0);
11288 /* Need to reset the chip because the MSI cycle may have terminated
11289 * with Master Abort.
11291 tg3_full_lock(tp, 1);
11293 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11294 err = tg3_init_hw(tp, true);
11296 tg3_full_unlock(tp);
11299 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11304 static int tg3_request_firmware(struct tg3 *tp)
11306 const struct tg3_firmware_hdr *fw_hdr;
11308 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11309 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11314 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11316 /* Firmware blob starts with version numbers, followed by
11317 * start address and _full_ length including BSS sections
11318 * (which must be longer than the actual data, of course
11321 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11322 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11323 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11324 tp->fw_len, tp->fw_needed);
11325 release_firmware(tp->fw);
11330 /* We no longer need firmware; we have it. */
11331 tp->fw_needed = NULL;
11335 static u32 tg3_irq_count(struct tg3 *tp)
11337 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11340 /* We want as many rx rings enabled as there are cpus.
11341 * In multiqueue MSI-X mode, the first MSI-X vector
11342 * only deals with link interrupts, etc, so we add
11343 * one to the number of vectors we are requesting.
11345 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11351 static bool tg3_enable_msix(struct tg3 *tp)
11354 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11356 tp->txq_cnt = tp->txq_req;
11357 tp->rxq_cnt = tp->rxq_req;
11359 tp->rxq_cnt = netif_get_num_default_rss_queues();
11360 if (tp->rxq_cnt > tp->rxq_max)
11361 tp->rxq_cnt = tp->rxq_max;
11363 /* Disable multiple TX rings by default. Simple round-robin hardware
11364 * scheduling of the TX rings can cause starvation of rings with
11365 * small packets when other rings have TSO or jumbo packets.
11370 tp->irq_cnt = tg3_irq_count(tp);
11372 for (i = 0; i < tp->irq_max; i++) {
11373 msix_ent[i].entry = i;
11374 msix_ent[i].vector = 0;
11377 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11380 } else if (rc < tp->irq_cnt) {
11381 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11384 tp->rxq_cnt = max(rc - 1, 1);
11386 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11389 for (i = 0; i < tp->irq_max; i++)
11390 tp->napi[i].irq_vec = msix_ent[i].vector;
11392 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11393 pci_disable_msix(tp->pdev);
11397 if (tp->irq_cnt == 1)
11400 tg3_flag_set(tp, ENABLE_RSS);
11402 if (tp->txq_cnt > 1)
11403 tg3_flag_set(tp, ENABLE_TSS);
11405 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11410 static void tg3_ints_init(struct tg3 *tp)
11412 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11413 !tg3_flag(tp, TAGGED_STATUS)) {
11414 /* All MSI supporting chips should support tagged
11415 * status. Assert that this is the case.
11417 netdev_warn(tp->dev,
11418 "MSI without TAGGED_STATUS? Not using MSI\n");
11422 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11423 tg3_flag_set(tp, USING_MSIX);
11424 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11425 tg3_flag_set(tp, USING_MSI);
11427 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11428 u32 msi_mode = tr32(MSGINT_MODE);
11429 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11430 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11431 if (!tg3_flag(tp, 1SHOT_MSI))
11432 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11433 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11436 if (!tg3_flag(tp, USING_MSIX)) {
11438 tp->napi[0].irq_vec = tp->pdev->irq;
11441 if (tp->irq_cnt == 1) {
11444 netif_set_real_num_tx_queues(tp->dev, 1);
11445 netif_set_real_num_rx_queues(tp->dev, 1);
11449 static void tg3_ints_fini(struct tg3 *tp)
11451 if (tg3_flag(tp, USING_MSIX))
11452 pci_disable_msix(tp->pdev);
11453 else if (tg3_flag(tp, USING_MSI))
11454 pci_disable_msi(tp->pdev);
11455 tg3_flag_clear(tp, USING_MSI);
11456 tg3_flag_clear(tp, USING_MSIX);
11457 tg3_flag_clear(tp, ENABLE_RSS);
11458 tg3_flag_clear(tp, ENABLE_TSS);
11461 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11464 struct net_device *dev = tp->dev;
11468 * Setup interrupts first so we know how
11469 * many NAPI resources to allocate
11473 tg3_rss_check_indir_tbl(tp);
11475 /* The placement of this call is tied
11476 * to the setup and use of Host TX descriptors.
11478 err = tg3_alloc_consistent(tp);
11480 goto out_ints_fini;
11484 tg3_napi_enable(tp);
11486 for (i = 0; i < tp->irq_cnt; i++) {
11487 struct tg3_napi *tnapi = &tp->napi[i];
11488 err = tg3_request_irq(tp, i);
11490 for (i--; i >= 0; i--) {
11491 tnapi = &tp->napi[i];
11492 free_irq(tnapi->irq_vec, tnapi);
11494 goto out_napi_fini;
11498 tg3_full_lock(tp, 0);
11501 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11503 err = tg3_init_hw(tp, reset_phy);
11505 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11506 tg3_free_rings(tp);
11509 tg3_full_unlock(tp);
11514 if (test_irq && tg3_flag(tp, USING_MSI)) {
11515 err = tg3_test_msi(tp);
11518 tg3_full_lock(tp, 0);
11519 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11520 tg3_free_rings(tp);
11521 tg3_full_unlock(tp);
11523 goto out_napi_fini;
11526 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11527 u32 val = tr32(PCIE_TRANSACTION_CFG);
11529 tw32(PCIE_TRANSACTION_CFG,
11530 val | PCIE_TRANS_CFG_1SHOT_MSI);
11536 tg3_hwmon_open(tp);
11538 tg3_full_lock(tp, 0);
11540 tg3_timer_start(tp);
11541 tg3_flag_set(tp, INIT_COMPLETE);
11542 tg3_enable_ints(tp);
11547 tg3_ptp_resume(tp);
11550 tg3_full_unlock(tp);
11552 netif_tx_start_all_queues(dev);
11555 * Reset loopback feature if it was turned on while the device was down
11556 * make sure that it's installed properly now.
11558 if (dev->features & NETIF_F_LOOPBACK)
11559 tg3_set_loopback(dev, dev->features);
11564 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11565 struct tg3_napi *tnapi = &tp->napi[i];
11566 free_irq(tnapi->irq_vec, tnapi);
11570 tg3_napi_disable(tp);
11572 tg3_free_consistent(tp);
11580 static void tg3_stop(struct tg3 *tp)
11584 tg3_reset_task_cancel(tp);
11585 tg3_netif_stop(tp);
11587 tg3_timer_stop(tp);
11589 tg3_hwmon_close(tp);
11593 tg3_full_lock(tp, 1);
11595 tg3_disable_ints(tp);
11597 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11598 tg3_free_rings(tp);
11599 tg3_flag_clear(tp, INIT_COMPLETE);
11601 tg3_full_unlock(tp);
11603 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11604 struct tg3_napi *tnapi = &tp->napi[i];
11605 free_irq(tnapi->irq_vec, tnapi);
11612 tg3_free_consistent(tp);
11615 static int tg3_open(struct net_device *dev)
11617 struct tg3 *tp = netdev_priv(dev);
11620 if (tp->fw_needed) {
11621 err = tg3_request_firmware(tp);
11622 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11624 netdev_warn(tp->dev, "EEE capability disabled\n");
11625 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11626 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11627 netdev_warn(tp->dev, "EEE capability restored\n");
11628 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11630 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11634 netdev_warn(tp->dev, "TSO capability disabled\n");
11635 tg3_flag_clear(tp, TSO_CAPABLE);
11636 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11637 netdev_notice(tp->dev, "TSO capability restored\n");
11638 tg3_flag_set(tp, TSO_CAPABLE);
11642 tg3_carrier_off(tp);
11644 err = tg3_power_up(tp);
11648 tg3_full_lock(tp, 0);
11650 tg3_disable_ints(tp);
11651 tg3_flag_clear(tp, INIT_COMPLETE);
11653 tg3_full_unlock(tp);
11655 err = tg3_start(tp,
11656 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11659 tg3_frob_aux_power(tp, false);
11660 pci_set_power_state(tp->pdev, PCI_D3hot);
11663 if (tg3_flag(tp, PTP_CAPABLE)) {
11664 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11666 if (IS_ERR(tp->ptp_clock))
11667 tp->ptp_clock = NULL;
11673 static int tg3_close(struct net_device *dev)
11675 struct tg3 *tp = netdev_priv(dev);
11681 /* Clear stats across close / open calls */
11682 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11683 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11685 if (pci_device_is_present(tp->pdev)) {
11686 tg3_power_down_prepare(tp);
11688 tg3_carrier_off(tp);
11693 static inline u64 get_stat64(tg3_stat64_t *val)
11695 return ((u64)val->high << 32) | ((u64)val->low);
11698 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11700 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11702 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11703 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11704 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11707 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11708 tg3_writephy(tp, MII_TG3_TEST1,
11709 val | MII_TG3_TEST1_CRC_EN);
11710 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11714 tp->phy_crc_errors += val;
11716 return tp->phy_crc_errors;
11719 return get_stat64(&hw_stats->rx_fcs_errors);
11722 #define ESTAT_ADD(member) \
11723 estats->member = old_estats->member + \
11724 get_stat64(&hw_stats->member)
11726 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11728 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11729 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11731 ESTAT_ADD(rx_octets);
11732 ESTAT_ADD(rx_fragments);
11733 ESTAT_ADD(rx_ucast_packets);
11734 ESTAT_ADD(rx_mcast_packets);
11735 ESTAT_ADD(rx_bcast_packets);
11736 ESTAT_ADD(rx_fcs_errors);
11737 ESTAT_ADD(rx_align_errors);
11738 ESTAT_ADD(rx_xon_pause_rcvd);
11739 ESTAT_ADD(rx_xoff_pause_rcvd);
11740 ESTAT_ADD(rx_mac_ctrl_rcvd);
11741 ESTAT_ADD(rx_xoff_entered);
11742 ESTAT_ADD(rx_frame_too_long_errors);
11743 ESTAT_ADD(rx_jabbers);
11744 ESTAT_ADD(rx_undersize_packets);
11745 ESTAT_ADD(rx_in_length_errors);
11746 ESTAT_ADD(rx_out_length_errors);
11747 ESTAT_ADD(rx_64_or_less_octet_packets);
11748 ESTAT_ADD(rx_65_to_127_octet_packets);
11749 ESTAT_ADD(rx_128_to_255_octet_packets);
11750 ESTAT_ADD(rx_256_to_511_octet_packets);
11751 ESTAT_ADD(rx_512_to_1023_octet_packets);
11752 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11753 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11754 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11755 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11756 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11758 ESTAT_ADD(tx_octets);
11759 ESTAT_ADD(tx_collisions);
11760 ESTAT_ADD(tx_xon_sent);
11761 ESTAT_ADD(tx_xoff_sent);
11762 ESTAT_ADD(tx_flow_control);
11763 ESTAT_ADD(tx_mac_errors);
11764 ESTAT_ADD(tx_single_collisions);
11765 ESTAT_ADD(tx_mult_collisions);
11766 ESTAT_ADD(tx_deferred);
11767 ESTAT_ADD(tx_excessive_collisions);
11768 ESTAT_ADD(tx_late_collisions);
11769 ESTAT_ADD(tx_collide_2times);
11770 ESTAT_ADD(tx_collide_3times);
11771 ESTAT_ADD(tx_collide_4times);
11772 ESTAT_ADD(tx_collide_5times);
11773 ESTAT_ADD(tx_collide_6times);
11774 ESTAT_ADD(tx_collide_7times);
11775 ESTAT_ADD(tx_collide_8times);
11776 ESTAT_ADD(tx_collide_9times);
11777 ESTAT_ADD(tx_collide_10times);
11778 ESTAT_ADD(tx_collide_11times);
11779 ESTAT_ADD(tx_collide_12times);
11780 ESTAT_ADD(tx_collide_13times);
11781 ESTAT_ADD(tx_collide_14times);
11782 ESTAT_ADD(tx_collide_15times);
11783 ESTAT_ADD(tx_ucast_packets);
11784 ESTAT_ADD(tx_mcast_packets);
11785 ESTAT_ADD(tx_bcast_packets);
11786 ESTAT_ADD(tx_carrier_sense_errors);
11787 ESTAT_ADD(tx_discards);
11788 ESTAT_ADD(tx_errors);
11790 ESTAT_ADD(dma_writeq_full);
11791 ESTAT_ADD(dma_write_prioq_full);
11792 ESTAT_ADD(rxbds_empty);
11793 ESTAT_ADD(rx_discards);
11794 ESTAT_ADD(rx_errors);
11795 ESTAT_ADD(rx_threshold_hit);
11797 ESTAT_ADD(dma_readq_full);
11798 ESTAT_ADD(dma_read_prioq_full);
11799 ESTAT_ADD(tx_comp_queue_full);
11801 ESTAT_ADD(ring_set_send_prod_index);
11802 ESTAT_ADD(ring_status_update);
11803 ESTAT_ADD(nic_irqs);
11804 ESTAT_ADD(nic_avoided_irqs);
11805 ESTAT_ADD(nic_tx_threshold_hit);
11807 ESTAT_ADD(mbuf_lwm_thresh_hit);
11810 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11812 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11813 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11815 stats->rx_packets = old_stats->rx_packets +
11816 get_stat64(&hw_stats->rx_ucast_packets) +
11817 get_stat64(&hw_stats->rx_mcast_packets) +
11818 get_stat64(&hw_stats->rx_bcast_packets);
11820 stats->tx_packets = old_stats->tx_packets +
11821 get_stat64(&hw_stats->tx_ucast_packets) +
11822 get_stat64(&hw_stats->tx_mcast_packets) +
11823 get_stat64(&hw_stats->tx_bcast_packets);
11825 stats->rx_bytes = old_stats->rx_bytes +
11826 get_stat64(&hw_stats->rx_octets);
11827 stats->tx_bytes = old_stats->tx_bytes +
11828 get_stat64(&hw_stats->tx_octets);
11830 stats->rx_errors = old_stats->rx_errors +
11831 get_stat64(&hw_stats->rx_errors);
11832 stats->tx_errors = old_stats->tx_errors +
11833 get_stat64(&hw_stats->tx_errors) +
11834 get_stat64(&hw_stats->tx_mac_errors) +
11835 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11836 get_stat64(&hw_stats->tx_discards);
11838 stats->multicast = old_stats->multicast +
11839 get_stat64(&hw_stats->rx_mcast_packets);
11840 stats->collisions = old_stats->collisions +
11841 get_stat64(&hw_stats->tx_collisions);
11843 stats->rx_length_errors = old_stats->rx_length_errors +
11844 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11845 get_stat64(&hw_stats->rx_undersize_packets);
11847 stats->rx_frame_errors = old_stats->rx_frame_errors +
11848 get_stat64(&hw_stats->rx_align_errors);
11849 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11850 get_stat64(&hw_stats->tx_discards);
11851 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11852 get_stat64(&hw_stats->tx_carrier_sense_errors);
11854 stats->rx_crc_errors = old_stats->rx_crc_errors +
11855 tg3_calc_crc_errors(tp);
11857 stats->rx_missed_errors = old_stats->rx_missed_errors +
11858 get_stat64(&hw_stats->rx_discards);
11860 stats->rx_dropped = tp->rx_dropped;
11861 stats->tx_dropped = tp->tx_dropped;
11864 static int tg3_get_regs_len(struct net_device *dev)
11866 return TG3_REG_BLK_SIZE;
11869 static void tg3_get_regs(struct net_device *dev,
11870 struct ethtool_regs *regs, void *_p)
11872 struct tg3 *tp = netdev_priv(dev);
11876 memset(_p, 0, TG3_REG_BLK_SIZE);
11878 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11881 tg3_full_lock(tp, 0);
11883 tg3_dump_legacy_regs(tp, (u32 *)_p);
11885 tg3_full_unlock(tp);
11888 static int tg3_get_eeprom_len(struct net_device *dev)
11890 struct tg3 *tp = netdev_priv(dev);
11892 return tp->nvram_size;
11895 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11897 struct tg3 *tp = netdev_priv(dev);
11898 int ret, cpmu_restore = 0;
11900 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11903 if (tg3_flag(tp, NO_NVRAM))
11906 offset = eeprom->offset;
11910 eeprom->magic = TG3_EEPROM_MAGIC;
11912 /* Override clock, link aware and link idle modes */
11913 if (tg3_flag(tp, CPMU_PRESENT)) {
11914 cpmu_val = tr32(TG3_CPMU_CTRL);
11915 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11916 CPMU_CTRL_LINK_IDLE_MODE)) {
11917 tw32(TG3_CPMU_CTRL, cpmu_val &
11918 ~(CPMU_CTRL_LINK_AWARE_MODE |
11919 CPMU_CTRL_LINK_IDLE_MODE));
11923 tg3_override_clk(tp);
11926 /* adjustments to start on required 4 byte boundary */
11927 b_offset = offset & 3;
11928 b_count = 4 - b_offset;
11929 if (b_count > len) {
11930 /* i.e. offset=1 len=2 */
11933 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11936 memcpy(data, ((char *)&val) + b_offset, b_count);
11939 eeprom->len += b_count;
11942 /* read bytes up to the last 4 byte boundary */
11943 pd = &data[eeprom->len];
11944 for (i = 0; i < (len - (len & 3)); i += 4) {
11945 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11952 memcpy(pd + i, &val, 4);
11953 if (need_resched()) {
11954 if (signal_pending(current)) {
11965 /* read last bytes not ending on 4 byte boundary */
11966 pd = &data[eeprom->len];
11968 b_offset = offset + len - b_count;
11969 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11972 memcpy(pd, &val, b_count);
11973 eeprom->len += b_count;
11978 /* Restore clock, link aware and link idle modes */
11979 tg3_restore_clk(tp);
11981 tw32(TG3_CPMU_CTRL, cpmu_val);
11986 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11988 struct tg3 *tp = netdev_priv(dev);
11990 u32 offset, len, b_offset, odd_len;
11994 if (tg3_flag(tp, NO_NVRAM) ||
11995 eeprom->magic != TG3_EEPROM_MAGIC)
11998 offset = eeprom->offset;
12001 if ((b_offset = (offset & 3))) {
12002 /* adjustments to start on required 4 byte boundary */
12003 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12014 /* adjustments to end on required 4 byte boundary */
12016 len = (len + 3) & ~3;
12017 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12023 if (b_offset || odd_len) {
12024 buf = kmalloc(len, GFP_KERNEL);
12028 memcpy(buf, &start, 4);
12030 memcpy(buf+len-4, &end, 4);
12031 memcpy(buf + b_offset, data, eeprom->len);
12034 ret = tg3_nvram_write_block(tp, offset, len, buf);
12042 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12044 struct tg3 *tp = netdev_priv(dev);
12046 if (tg3_flag(tp, USE_PHYLIB)) {
12047 struct phy_device *phydev;
12048 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12050 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12051 return phy_ethtool_gset(phydev, cmd);
12054 cmd->supported = (SUPPORTED_Autoneg);
12056 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12057 cmd->supported |= (SUPPORTED_1000baseT_Half |
12058 SUPPORTED_1000baseT_Full);
12060 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12061 cmd->supported |= (SUPPORTED_100baseT_Half |
12062 SUPPORTED_100baseT_Full |
12063 SUPPORTED_10baseT_Half |
12064 SUPPORTED_10baseT_Full |
12066 cmd->port = PORT_TP;
12068 cmd->supported |= SUPPORTED_FIBRE;
12069 cmd->port = PORT_FIBRE;
12072 cmd->advertising = tp->link_config.advertising;
12073 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12074 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12075 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12076 cmd->advertising |= ADVERTISED_Pause;
12078 cmd->advertising |= ADVERTISED_Pause |
12079 ADVERTISED_Asym_Pause;
12081 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12082 cmd->advertising |= ADVERTISED_Asym_Pause;
12085 if (netif_running(dev) && tp->link_up) {
12086 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12087 cmd->duplex = tp->link_config.active_duplex;
12088 cmd->lp_advertising = tp->link_config.rmt_adv;
12089 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12090 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12091 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12093 cmd->eth_tp_mdix = ETH_TP_MDI;
12096 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12097 cmd->duplex = DUPLEX_UNKNOWN;
12098 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12100 cmd->phy_address = tp->phy_addr;
12101 cmd->transceiver = XCVR_INTERNAL;
12102 cmd->autoneg = tp->link_config.autoneg;
12108 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12110 struct tg3 *tp = netdev_priv(dev);
12111 u32 speed = ethtool_cmd_speed(cmd);
12113 if (tg3_flag(tp, USE_PHYLIB)) {
12114 struct phy_device *phydev;
12115 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12117 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12118 return phy_ethtool_sset(phydev, cmd);
12121 if (cmd->autoneg != AUTONEG_ENABLE &&
12122 cmd->autoneg != AUTONEG_DISABLE)
12125 if (cmd->autoneg == AUTONEG_DISABLE &&
12126 cmd->duplex != DUPLEX_FULL &&
12127 cmd->duplex != DUPLEX_HALF)
12130 if (cmd->autoneg == AUTONEG_ENABLE) {
12131 u32 mask = ADVERTISED_Autoneg |
12133 ADVERTISED_Asym_Pause;
12135 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12136 mask |= ADVERTISED_1000baseT_Half |
12137 ADVERTISED_1000baseT_Full;
12139 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12140 mask |= ADVERTISED_100baseT_Half |
12141 ADVERTISED_100baseT_Full |
12142 ADVERTISED_10baseT_Half |
12143 ADVERTISED_10baseT_Full |
12146 mask |= ADVERTISED_FIBRE;
12148 if (cmd->advertising & ~mask)
12151 mask &= (ADVERTISED_1000baseT_Half |
12152 ADVERTISED_1000baseT_Full |
12153 ADVERTISED_100baseT_Half |
12154 ADVERTISED_100baseT_Full |
12155 ADVERTISED_10baseT_Half |
12156 ADVERTISED_10baseT_Full);
12158 cmd->advertising &= mask;
12160 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12161 if (speed != SPEED_1000)
12164 if (cmd->duplex != DUPLEX_FULL)
12167 if (speed != SPEED_100 &&
12173 tg3_full_lock(tp, 0);
12175 tp->link_config.autoneg = cmd->autoneg;
12176 if (cmd->autoneg == AUTONEG_ENABLE) {
12177 tp->link_config.advertising = (cmd->advertising |
12178 ADVERTISED_Autoneg);
12179 tp->link_config.speed = SPEED_UNKNOWN;
12180 tp->link_config.duplex = DUPLEX_UNKNOWN;
12182 tp->link_config.advertising = 0;
12183 tp->link_config.speed = speed;
12184 tp->link_config.duplex = cmd->duplex;
12187 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12189 tg3_warn_mgmt_link_flap(tp);
12191 if (netif_running(dev))
12192 tg3_setup_phy(tp, true);
12194 tg3_full_unlock(tp);
12199 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12201 struct tg3 *tp = netdev_priv(dev);
12203 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12204 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12205 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12206 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12209 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12211 struct tg3 *tp = netdev_priv(dev);
12213 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12214 wol->supported = WAKE_MAGIC;
12216 wol->supported = 0;
12218 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12219 wol->wolopts = WAKE_MAGIC;
12220 memset(&wol->sopass, 0, sizeof(wol->sopass));
12223 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12225 struct tg3 *tp = netdev_priv(dev);
12226 struct device *dp = &tp->pdev->dev;
12228 if (wol->wolopts & ~WAKE_MAGIC)
12230 if ((wol->wolopts & WAKE_MAGIC) &&
12231 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12234 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12236 if (device_may_wakeup(dp))
12237 tg3_flag_set(tp, WOL_ENABLE);
12239 tg3_flag_clear(tp, WOL_ENABLE);
12244 static u32 tg3_get_msglevel(struct net_device *dev)
12246 struct tg3 *tp = netdev_priv(dev);
12247 return tp->msg_enable;
12250 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12252 struct tg3 *tp = netdev_priv(dev);
12253 tp->msg_enable = value;
12256 static int tg3_nway_reset(struct net_device *dev)
12258 struct tg3 *tp = netdev_priv(dev);
12261 if (!netif_running(dev))
12264 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12267 tg3_warn_mgmt_link_flap(tp);
12269 if (tg3_flag(tp, USE_PHYLIB)) {
12270 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12272 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12276 spin_lock_bh(&tp->lock);
12278 tg3_readphy(tp, MII_BMCR, &bmcr);
12279 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12280 ((bmcr & BMCR_ANENABLE) ||
12281 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12282 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12286 spin_unlock_bh(&tp->lock);
12292 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12294 struct tg3 *tp = netdev_priv(dev);
12296 ering->rx_max_pending = tp->rx_std_ring_mask;
12297 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12298 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12300 ering->rx_jumbo_max_pending = 0;
12302 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12304 ering->rx_pending = tp->rx_pending;
12305 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12306 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12308 ering->rx_jumbo_pending = 0;
12310 ering->tx_pending = tp->napi[0].tx_pending;
12313 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12315 struct tg3 *tp = netdev_priv(dev);
12316 int i, irq_sync = 0, err = 0;
12318 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12319 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12320 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12321 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12322 (tg3_flag(tp, TSO_BUG) &&
12323 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12326 if (netif_running(dev)) {
12328 tg3_netif_stop(tp);
12332 tg3_full_lock(tp, irq_sync);
12334 tp->rx_pending = ering->rx_pending;
12336 if (tg3_flag(tp, MAX_RXPEND_64) &&
12337 tp->rx_pending > 63)
12338 tp->rx_pending = 63;
12340 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12341 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12343 for (i = 0; i < tp->irq_max; i++)
12344 tp->napi[i].tx_pending = ering->tx_pending;
12346 if (netif_running(dev)) {
12347 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12348 err = tg3_restart_hw(tp, false);
12350 tg3_netif_start(tp);
12353 tg3_full_unlock(tp);
12355 if (irq_sync && !err)
12361 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12363 struct tg3 *tp = netdev_priv(dev);
12365 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12367 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12368 epause->rx_pause = 1;
12370 epause->rx_pause = 0;
12372 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12373 epause->tx_pause = 1;
12375 epause->tx_pause = 0;
12378 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12380 struct tg3 *tp = netdev_priv(dev);
12383 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12384 tg3_warn_mgmt_link_flap(tp);
12386 if (tg3_flag(tp, USE_PHYLIB)) {
12388 struct phy_device *phydev;
12390 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12392 if (!(phydev->supported & SUPPORTED_Pause) ||
12393 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12394 (epause->rx_pause != epause->tx_pause)))
12397 tp->link_config.flowctrl = 0;
12398 if (epause->rx_pause) {
12399 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12401 if (epause->tx_pause) {
12402 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12403 newadv = ADVERTISED_Pause;
12405 newadv = ADVERTISED_Pause |
12406 ADVERTISED_Asym_Pause;
12407 } else if (epause->tx_pause) {
12408 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12409 newadv = ADVERTISED_Asym_Pause;
12413 if (epause->autoneg)
12414 tg3_flag_set(tp, PAUSE_AUTONEG);
12416 tg3_flag_clear(tp, PAUSE_AUTONEG);
12418 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12419 u32 oldadv = phydev->advertising &
12420 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12421 if (oldadv != newadv) {
12422 phydev->advertising &=
12423 ~(ADVERTISED_Pause |
12424 ADVERTISED_Asym_Pause);
12425 phydev->advertising |= newadv;
12426 if (phydev->autoneg) {
12428 * Always renegotiate the link to
12429 * inform our link partner of our
12430 * flow control settings, even if the
12431 * flow control is forced. Let
12432 * tg3_adjust_link() do the final
12433 * flow control setup.
12435 return phy_start_aneg(phydev);
12439 if (!epause->autoneg)
12440 tg3_setup_flow_control(tp, 0, 0);
12442 tp->link_config.advertising &=
12443 ~(ADVERTISED_Pause |
12444 ADVERTISED_Asym_Pause);
12445 tp->link_config.advertising |= newadv;
12450 if (netif_running(dev)) {
12451 tg3_netif_stop(tp);
12455 tg3_full_lock(tp, irq_sync);
12457 if (epause->autoneg)
12458 tg3_flag_set(tp, PAUSE_AUTONEG);
12460 tg3_flag_clear(tp, PAUSE_AUTONEG);
12461 if (epause->rx_pause)
12462 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12464 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12465 if (epause->tx_pause)
12466 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12468 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12470 if (netif_running(dev)) {
12471 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12472 err = tg3_restart_hw(tp, false);
12474 tg3_netif_start(tp);
12477 tg3_full_unlock(tp);
12480 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12485 static int tg3_get_sset_count(struct net_device *dev, int sset)
12489 return TG3_NUM_TEST;
12491 return TG3_NUM_STATS;
12493 return -EOPNOTSUPP;
12497 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12498 u32 *rules __always_unused)
12500 struct tg3 *tp = netdev_priv(dev);
12502 if (!tg3_flag(tp, SUPPORT_MSIX))
12503 return -EOPNOTSUPP;
12505 switch (info->cmd) {
12506 case ETHTOOL_GRXRINGS:
12507 if (netif_running(tp->dev))
12508 info->data = tp->rxq_cnt;
12510 info->data = num_online_cpus();
12511 if (info->data > TG3_RSS_MAX_NUM_QS)
12512 info->data = TG3_RSS_MAX_NUM_QS;
12515 /* The first interrupt vector only
12516 * handles link interrupts.
12522 return -EOPNOTSUPP;
12526 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12529 struct tg3 *tp = netdev_priv(dev);
12531 if (tg3_flag(tp, SUPPORT_MSIX))
12532 size = TG3_RSS_INDIR_TBL_SIZE;
12537 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
12539 struct tg3 *tp = netdev_priv(dev);
12542 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12543 indir[i] = tp->rss_ind_tbl[i];
12548 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key)
12550 struct tg3 *tp = netdev_priv(dev);
12553 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12554 tp->rss_ind_tbl[i] = indir[i];
12556 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12559 /* It is legal to write the indirection
12560 * table while the device is running.
12562 tg3_full_lock(tp, 0);
12563 tg3_rss_write_indir_tbl(tp);
12564 tg3_full_unlock(tp);
12569 static void tg3_get_channels(struct net_device *dev,
12570 struct ethtool_channels *channel)
12572 struct tg3 *tp = netdev_priv(dev);
12573 u32 deflt_qs = netif_get_num_default_rss_queues();
12575 channel->max_rx = tp->rxq_max;
12576 channel->max_tx = tp->txq_max;
12578 if (netif_running(dev)) {
12579 channel->rx_count = tp->rxq_cnt;
12580 channel->tx_count = tp->txq_cnt;
12583 channel->rx_count = tp->rxq_req;
12585 channel->rx_count = min(deflt_qs, tp->rxq_max);
12588 channel->tx_count = tp->txq_req;
12590 channel->tx_count = min(deflt_qs, tp->txq_max);
12594 static int tg3_set_channels(struct net_device *dev,
12595 struct ethtool_channels *channel)
12597 struct tg3 *tp = netdev_priv(dev);
12599 if (!tg3_flag(tp, SUPPORT_MSIX))
12600 return -EOPNOTSUPP;
12602 if (channel->rx_count > tp->rxq_max ||
12603 channel->tx_count > tp->txq_max)
12606 tp->rxq_req = channel->rx_count;
12607 tp->txq_req = channel->tx_count;
12609 if (!netif_running(dev))
12614 tg3_carrier_off(tp);
12616 tg3_start(tp, true, false, false);
12621 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12623 switch (stringset) {
12625 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12628 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12631 WARN_ON(1); /* we need a WARN() */
12636 static int tg3_set_phys_id(struct net_device *dev,
12637 enum ethtool_phys_id_state state)
12639 struct tg3 *tp = netdev_priv(dev);
12641 if (!netif_running(tp->dev))
12645 case ETHTOOL_ID_ACTIVE:
12646 return 1; /* cycle on/off once per second */
12648 case ETHTOOL_ID_ON:
12649 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12650 LED_CTRL_1000MBPS_ON |
12651 LED_CTRL_100MBPS_ON |
12652 LED_CTRL_10MBPS_ON |
12653 LED_CTRL_TRAFFIC_OVERRIDE |
12654 LED_CTRL_TRAFFIC_BLINK |
12655 LED_CTRL_TRAFFIC_LED);
12658 case ETHTOOL_ID_OFF:
12659 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12660 LED_CTRL_TRAFFIC_OVERRIDE);
12663 case ETHTOOL_ID_INACTIVE:
12664 tw32(MAC_LED_CTRL, tp->led_ctrl);
12671 static void tg3_get_ethtool_stats(struct net_device *dev,
12672 struct ethtool_stats *estats, u64 *tmp_stats)
12674 struct tg3 *tp = netdev_priv(dev);
12677 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12679 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12682 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12686 u32 offset = 0, len = 0;
12689 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12692 if (magic == TG3_EEPROM_MAGIC) {
12693 for (offset = TG3_NVM_DIR_START;
12694 offset < TG3_NVM_DIR_END;
12695 offset += TG3_NVM_DIRENT_SIZE) {
12696 if (tg3_nvram_read(tp, offset, &val))
12699 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12700 TG3_NVM_DIRTYPE_EXTVPD)
12704 if (offset != TG3_NVM_DIR_END) {
12705 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12706 if (tg3_nvram_read(tp, offset + 4, &offset))
12709 offset = tg3_nvram_logical_addr(tp, offset);
12713 if (!offset || !len) {
12714 offset = TG3_NVM_VPD_OFF;
12715 len = TG3_NVM_VPD_LEN;
12718 buf = kmalloc(len, GFP_KERNEL);
12722 if (magic == TG3_EEPROM_MAGIC) {
12723 for (i = 0; i < len; i += 4) {
12724 /* The data is in little-endian format in NVRAM.
12725 * Use the big-endian read routines to preserve
12726 * the byte order as it exists in NVRAM.
12728 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12734 unsigned int pos = 0;
12736 ptr = (u8 *)&buf[0];
12737 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12738 cnt = pci_read_vpd(tp->pdev, pos,
12740 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12758 #define NVRAM_TEST_SIZE 0x100
12759 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12760 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12761 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12762 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12763 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12764 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12765 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12766 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12768 static int tg3_test_nvram(struct tg3 *tp)
12770 u32 csum, magic, len;
12772 int i, j, k, err = 0, size;
12774 if (tg3_flag(tp, NO_NVRAM))
12777 if (tg3_nvram_read(tp, 0, &magic) != 0)
12780 if (magic == TG3_EEPROM_MAGIC)
12781 size = NVRAM_TEST_SIZE;
12782 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12783 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12784 TG3_EEPROM_SB_FORMAT_1) {
12785 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12786 case TG3_EEPROM_SB_REVISION_0:
12787 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12789 case TG3_EEPROM_SB_REVISION_2:
12790 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12792 case TG3_EEPROM_SB_REVISION_3:
12793 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12795 case TG3_EEPROM_SB_REVISION_4:
12796 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12798 case TG3_EEPROM_SB_REVISION_5:
12799 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12801 case TG3_EEPROM_SB_REVISION_6:
12802 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12809 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12810 size = NVRAM_SELFBOOT_HW_SIZE;
12814 buf = kmalloc(size, GFP_KERNEL);
12819 for (i = 0, j = 0; i < size; i += 4, j++) {
12820 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12827 /* Selfboot format */
12828 magic = be32_to_cpu(buf[0]);
12829 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12830 TG3_EEPROM_MAGIC_FW) {
12831 u8 *buf8 = (u8 *) buf, csum8 = 0;
12833 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12834 TG3_EEPROM_SB_REVISION_2) {
12835 /* For rev 2, the csum doesn't include the MBA. */
12836 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12838 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12841 for (i = 0; i < size; i++)
12854 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12855 TG3_EEPROM_MAGIC_HW) {
12856 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12857 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12858 u8 *buf8 = (u8 *) buf;
12860 /* Separate the parity bits and the data bytes. */
12861 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12862 if ((i == 0) || (i == 8)) {
12866 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12867 parity[k++] = buf8[i] & msk;
12869 } else if (i == 16) {
12873 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12874 parity[k++] = buf8[i] & msk;
12877 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12878 parity[k++] = buf8[i] & msk;
12881 data[j++] = buf8[i];
12885 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12886 u8 hw8 = hweight8(data[i]);
12888 if ((hw8 & 0x1) && parity[i])
12890 else if (!(hw8 & 0x1) && !parity[i])
12899 /* Bootstrap checksum at offset 0x10 */
12900 csum = calc_crc((unsigned char *) buf, 0x10);
12901 if (csum != le32_to_cpu(buf[0x10/4]))
12904 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12905 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12906 if (csum != le32_to_cpu(buf[0xfc/4]))
12911 buf = tg3_vpd_readblock(tp, &len);
12915 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12917 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12921 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12924 i += PCI_VPD_LRDT_TAG_SIZE;
12925 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12926 PCI_VPD_RO_KEYWORD_CHKSUM);
12930 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12932 for (i = 0; i <= j; i++)
12933 csum8 += ((u8 *)buf)[i];
12947 #define TG3_SERDES_TIMEOUT_SEC 2
12948 #define TG3_COPPER_TIMEOUT_SEC 6
12950 static int tg3_test_link(struct tg3 *tp)
12954 if (!netif_running(tp->dev))
12957 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12958 max = TG3_SERDES_TIMEOUT_SEC;
12960 max = TG3_COPPER_TIMEOUT_SEC;
12962 for (i = 0; i < max; i++) {
12966 if (msleep_interruptible(1000))
12973 /* Only test the commonly used registers */
12974 static int tg3_test_registers(struct tg3 *tp)
12976 int i, is_5705, is_5750;
12977 u32 offset, read_mask, write_mask, val, save_val, read_val;
12981 #define TG3_FL_5705 0x1
12982 #define TG3_FL_NOT_5705 0x2
12983 #define TG3_FL_NOT_5788 0x4
12984 #define TG3_FL_NOT_5750 0x8
12988 /* MAC Control Registers */
12989 { MAC_MODE, TG3_FL_NOT_5705,
12990 0x00000000, 0x00ef6f8c },
12991 { MAC_MODE, TG3_FL_5705,
12992 0x00000000, 0x01ef6b8c },
12993 { MAC_STATUS, TG3_FL_NOT_5705,
12994 0x03800107, 0x00000000 },
12995 { MAC_STATUS, TG3_FL_5705,
12996 0x03800100, 0x00000000 },
12997 { MAC_ADDR_0_HIGH, 0x0000,
12998 0x00000000, 0x0000ffff },
12999 { MAC_ADDR_0_LOW, 0x0000,
13000 0x00000000, 0xffffffff },
13001 { MAC_RX_MTU_SIZE, 0x0000,
13002 0x00000000, 0x0000ffff },
13003 { MAC_TX_MODE, 0x0000,
13004 0x00000000, 0x00000070 },
13005 { MAC_TX_LENGTHS, 0x0000,
13006 0x00000000, 0x00003fff },
13007 { MAC_RX_MODE, TG3_FL_NOT_5705,
13008 0x00000000, 0x000007fc },
13009 { MAC_RX_MODE, TG3_FL_5705,
13010 0x00000000, 0x000007dc },
13011 { MAC_HASH_REG_0, 0x0000,
13012 0x00000000, 0xffffffff },
13013 { MAC_HASH_REG_1, 0x0000,
13014 0x00000000, 0xffffffff },
13015 { MAC_HASH_REG_2, 0x0000,
13016 0x00000000, 0xffffffff },
13017 { MAC_HASH_REG_3, 0x0000,
13018 0x00000000, 0xffffffff },
13020 /* Receive Data and Receive BD Initiator Control Registers. */
13021 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13022 0x00000000, 0xffffffff },
13023 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13024 0x00000000, 0xffffffff },
13025 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13026 0x00000000, 0x00000003 },
13027 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13028 0x00000000, 0xffffffff },
13029 { RCVDBDI_STD_BD+0, 0x0000,
13030 0x00000000, 0xffffffff },
13031 { RCVDBDI_STD_BD+4, 0x0000,
13032 0x00000000, 0xffffffff },
13033 { RCVDBDI_STD_BD+8, 0x0000,
13034 0x00000000, 0xffff0002 },
13035 { RCVDBDI_STD_BD+0xc, 0x0000,
13036 0x00000000, 0xffffffff },
13038 /* Receive BD Initiator Control Registers. */
13039 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13040 0x00000000, 0xffffffff },
13041 { RCVBDI_STD_THRESH, TG3_FL_5705,
13042 0x00000000, 0x000003ff },
13043 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13044 0x00000000, 0xffffffff },
13046 /* Host Coalescing Control Registers. */
13047 { HOSTCC_MODE, TG3_FL_NOT_5705,
13048 0x00000000, 0x00000004 },
13049 { HOSTCC_MODE, TG3_FL_5705,
13050 0x00000000, 0x000000f6 },
13051 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13052 0x00000000, 0xffffffff },
13053 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13054 0x00000000, 0x000003ff },
13055 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13056 0x00000000, 0xffffffff },
13057 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13058 0x00000000, 0x000003ff },
13059 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13060 0x00000000, 0xffffffff },
13061 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13062 0x00000000, 0x000000ff },
13063 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13064 0x00000000, 0xffffffff },
13065 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13066 0x00000000, 0x000000ff },
13067 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13068 0x00000000, 0xffffffff },
13069 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13070 0x00000000, 0xffffffff },
13071 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13072 0x00000000, 0xffffffff },
13073 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13074 0x00000000, 0x000000ff },
13075 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13076 0x00000000, 0xffffffff },
13077 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13078 0x00000000, 0x000000ff },
13079 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13080 0x00000000, 0xffffffff },
13081 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13082 0x00000000, 0xffffffff },
13083 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13084 0x00000000, 0xffffffff },
13085 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13086 0x00000000, 0xffffffff },
13087 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13088 0x00000000, 0xffffffff },
13089 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13090 0xffffffff, 0x00000000 },
13091 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13092 0xffffffff, 0x00000000 },
13094 /* Buffer Manager Control Registers. */
13095 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13096 0x00000000, 0x007fff80 },
13097 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13098 0x00000000, 0x007fffff },
13099 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13100 0x00000000, 0x0000003f },
13101 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13102 0x00000000, 0x000001ff },
13103 { BUFMGR_MB_HIGH_WATER, 0x0000,
13104 0x00000000, 0x000001ff },
13105 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13106 0xffffffff, 0x00000000 },
13107 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13108 0xffffffff, 0x00000000 },
13110 /* Mailbox Registers */
13111 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13112 0x00000000, 0x000001ff },
13113 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13114 0x00000000, 0x000001ff },
13115 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13116 0x00000000, 0x000007ff },
13117 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13118 0x00000000, 0x000001ff },
13120 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13123 is_5705 = is_5750 = 0;
13124 if (tg3_flag(tp, 5705_PLUS)) {
13126 if (tg3_flag(tp, 5750_PLUS))
13130 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13131 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13134 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13137 if (tg3_flag(tp, IS_5788) &&
13138 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13141 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13144 offset = (u32) reg_tbl[i].offset;
13145 read_mask = reg_tbl[i].read_mask;
13146 write_mask = reg_tbl[i].write_mask;
13148 /* Save the original register content */
13149 save_val = tr32(offset);
13151 /* Determine the read-only value. */
13152 read_val = save_val & read_mask;
13154 /* Write zero to the register, then make sure the read-only bits
13155 * are not changed and the read/write bits are all zeros.
13159 val = tr32(offset);
13161 /* Test the read-only and read/write bits. */
13162 if (((val & read_mask) != read_val) || (val & write_mask))
13165 /* Write ones to all the bits defined by RdMask and WrMask, then
13166 * make sure the read-only bits are not changed and the
13167 * read/write bits are all ones.
13169 tw32(offset, read_mask | write_mask);
13171 val = tr32(offset);
13173 /* Test the read-only bits. */
13174 if ((val & read_mask) != read_val)
13177 /* Test the read/write bits. */
13178 if ((val & write_mask) != write_mask)
13181 tw32(offset, save_val);
13187 if (netif_msg_hw(tp))
13188 netdev_err(tp->dev,
13189 "Register test failed at offset %x\n", offset);
13190 tw32(offset, save_val);
13194 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13196 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13200 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13201 for (j = 0; j < len; j += 4) {
13204 tg3_write_mem(tp, offset + j, test_pattern[i]);
13205 tg3_read_mem(tp, offset + j, &val);
13206 if (val != test_pattern[i])
13213 static int tg3_test_memory(struct tg3 *tp)
13215 static struct mem_entry {
13218 } mem_tbl_570x[] = {
13219 { 0x00000000, 0x00b50},
13220 { 0x00002000, 0x1c000},
13221 { 0xffffffff, 0x00000}
13222 }, mem_tbl_5705[] = {
13223 { 0x00000100, 0x0000c},
13224 { 0x00000200, 0x00008},
13225 { 0x00004000, 0x00800},
13226 { 0x00006000, 0x01000},
13227 { 0x00008000, 0x02000},
13228 { 0x00010000, 0x0e000},
13229 { 0xffffffff, 0x00000}
13230 }, mem_tbl_5755[] = {
13231 { 0x00000200, 0x00008},
13232 { 0x00004000, 0x00800},
13233 { 0x00006000, 0x00800},
13234 { 0x00008000, 0x02000},
13235 { 0x00010000, 0x0c000},
13236 { 0xffffffff, 0x00000}
13237 }, mem_tbl_5906[] = {
13238 { 0x00000200, 0x00008},
13239 { 0x00004000, 0x00400},
13240 { 0x00006000, 0x00400},
13241 { 0x00008000, 0x01000},
13242 { 0x00010000, 0x01000},
13243 { 0xffffffff, 0x00000}
13244 }, mem_tbl_5717[] = {
13245 { 0x00000200, 0x00008},
13246 { 0x00010000, 0x0a000},
13247 { 0x00020000, 0x13c00},
13248 { 0xffffffff, 0x00000}
13249 }, mem_tbl_57765[] = {
13250 { 0x00000200, 0x00008},
13251 { 0x00004000, 0x00800},
13252 { 0x00006000, 0x09800},
13253 { 0x00010000, 0x0a000},
13254 { 0xffffffff, 0x00000}
13256 struct mem_entry *mem_tbl;
13260 if (tg3_flag(tp, 5717_PLUS))
13261 mem_tbl = mem_tbl_5717;
13262 else if (tg3_flag(tp, 57765_CLASS) ||
13263 tg3_asic_rev(tp) == ASIC_REV_5762)
13264 mem_tbl = mem_tbl_57765;
13265 else if (tg3_flag(tp, 5755_PLUS))
13266 mem_tbl = mem_tbl_5755;
13267 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13268 mem_tbl = mem_tbl_5906;
13269 else if (tg3_flag(tp, 5705_PLUS))
13270 mem_tbl = mem_tbl_5705;
13272 mem_tbl = mem_tbl_570x;
13274 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13275 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13283 #define TG3_TSO_MSS 500
13285 #define TG3_TSO_IP_HDR_LEN 20
13286 #define TG3_TSO_TCP_HDR_LEN 20
13287 #define TG3_TSO_TCP_OPT_LEN 12
13289 static const u8 tg3_tso_header[] = {
13291 0x45, 0x00, 0x00, 0x00,
13292 0x00, 0x00, 0x40, 0x00,
13293 0x40, 0x06, 0x00, 0x00,
13294 0x0a, 0x00, 0x00, 0x01,
13295 0x0a, 0x00, 0x00, 0x02,
13296 0x0d, 0x00, 0xe0, 0x00,
13297 0x00, 0x00, 0x01, 0x00,
13298 0x00, 0x00, 0x02, 0x00,
13299 0x80, 0x10, 0x10, 0x00,
13300 0x14, 0x09, 0x00, 0x00,
13301 0x01, 0x01, 0x08, 0x0a,
13302 0x11, 0x11, 0x11, 0x11,
13303 0x11, 0x11, 0x11, 0x11,
13306 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13308 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13309 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13311 struct sk_buff *skb;
13312 u8 *tx_data, *rx_data;
13314 int num_pkts, tx_len, rx_len, i, err;
13315 struct tg3_rx_buffer_desc *desc;
13316 struct tg3_napi *tnapi, *rnapi;
13317 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13319 tnapi = &tp->napi[0];
13320 rnapi = &tp->napi[0];
13321 if (tp->irq_cnt > 1) {
13322 if (tg3_flag(tp, ENABLE_RSS))
13323 rnapi = &tp->napi[1];
13324 if (tg3_flag(tp, ENABLE_TSS))
13325 tnapi = &tp->napi[1];
13327 coal_now = tnapi->coal_now | rnapi->coal_now;
13332 skb = netdev_alloc_skb(tp->dev, tx_len);
13336 tx_data = skb_put(skb, tx_len);
13337 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13338 memset(tx_data + ETH_ALEN, 0x0, 8);
13340 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13342 if (tso_loopback) {
13343 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13345 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13346 TG3_TSO_TCP_OPT_LEN;
13348 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13349 sizeof(tg3_tso_header));
13352 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13353 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13355 /* Set the total length field in the IP header */
13356 iph->tot_len = htons((u16)(mss + hdr_len));
13358 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13359 TXD_FLAG_CPU_POST_DMA);
13361 if (tg3_flag(tp, HW_TSO_1) ||
13362 tg3_flag(tp, HW_TSO_2) ||
13363 tg3_flag(tp, HW_TSO_3)) {
13365 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13366 th = (struct tcphdr *)&tx_data[val];
13369 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13371 if (tg3_flag(tp, HW_TSO_3)) {
13372 mss |= (hdr_len & 0xc) << 12;
13373 if (hdr_len & 0x10)
13374 base_flags |= 0x00000010;
13375 base_flags |= (hdr_len & 0x3e0) << 5;
13376 } else if (tg3_flag(tp, HW_TSO_2))
13377 mss |= hdr_len << 9;
13378 else if (tg3_flag(tp, HW_TSO_1) ||
13379 tg3_asic_rev(tp) == ASIC_REV_5705) {
13380 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13382 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13385 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13388 data_off = ETH_HLEN;
13390 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13391 tx_len > VLAN_ETH_FRAME_LEN)
13392 base_flags |= TXD_FLAG_JMB_PKT;
13395 for (i = data_off; i < tx_len; i++)
13396 tx_data[i] = (u8) (i & 0xff);
13398 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13399 if (pci_dma_mapping_error(tp->pdev, map)) {
13400 dev_kfree_skb(skb);
13404 val = tnapi->tx_prod;
13405 tnapi->tx_buffers[val].skb = skb;
13406 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13408 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13413 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13415 budget = tg3_tx_avail(tnapi);
13416 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13417 base_flags | TXD_FLAG_END, mss, 0)) {
13418 tnapi->tx_buffers[val].skb = NULL;
13419 dev_kfree_skb(skb);
13425 /* Sync BD data before updating mailbox */
13428 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13429 tr32_mailbox(tnapi->prodmbox);
13433 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13434 for (i = 0; i < 35; i++) {
13435 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13440 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13441 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13442 if ((tx_idx == tnapi->tx_prod) &&
13443 (rx_idx == (rx_start_idx + num_pkts)))
13447 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13448 dev_kfree_skb(skb);
13450 if (tx_idx != tnapi->tx_prod)
13453 if (rx_idx != rx_start_idx + num_pkts)
13457 while (rx_idx != rx_start_idx) {
13458 desc = &rnapi->rx_rcb[rx_start_idx++];
13459 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13460 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13462 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13463 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13466 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13469 if (!tso_loopback) {
13470 if (rx_len != tx_len)
13473 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13474 if (opaque_key != RXD_OPAQUE_RING_STD)
13477 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13480 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13481 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13482 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13486 if (opaque_key == RXD_OPAQUE_RING_STD) {
13487 rx_data = tpr->rx_std_buffers[desc_idx].data;
13488 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13490 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13491 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13492 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13497 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13498 PCI_DMA_FROMDEVICE);
13500 rx_data += TG3_RX_OFFSET(tp);
13501 for (i = data_off; i < rx_len; i++, val++) {
13502 if (*(rx_data + i) != (u8) (val & 0xff))
13509 /* tg3_free_rings will unmap and free the rx_data */
13514 #define TG3_STD_LOOPBACK_FAILED 1
13515 #define TG3_JMB_LOOPBACK_FAILED 2
13516 #define TG3_TSO_LOOPBACK_FAILED 4
13517 #define TG3_LOOPBACK_FAILED \
13518 (TG3_STD_LOOPBACK_FAILED | \
13519 TG3_JMB_LOOPBACK_FAILED | \
13520 TG3_TSO_LOOPBACK_FAILED)
13522 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13526 u32 jmb_pkt_sz = 9000;
13529 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13531 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13532 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13534 if (!netif_running(tp->dev)) {
13535 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13536 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13538 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13542 err = tg3_reset_hw(tp, true);
13544 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13545 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13547 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13551 if (tg3_flag(tp, ENABLE_RSS)) {
13554 /* Reroute all rx packets to the 1st queue */
13555 for (i = MAC_RSS_INDIR_TBL_0;
13556 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13560 /* HW errata - mac loopback fails in some cases on 5780.
13561 * Normal traffic and PHY loopback are not affected by
13562 * errata. Also, the MAC loopback test is deprecated for
13563 * all newer ASIC revisions.
13565 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13566 !tg3_flag(tp, CPMU_PRESENT)) {
13567 tg3_mac_loopback(tp, true);
13569 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13570 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13572 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13573 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13574 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13576 tg3_mac_loopback(tp, false);
13579 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13580 !tg3_flag(tp, USE_PHYLIB)) {
13583 tg3_phy_lpbk_set(tp, 0, false);
13585 /* Wait for link */
13586 for (i = 0; i < 100; i++) {
13587 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13592 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13593 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13594 if (tg3_flag(tp, TSO_CAPABLE) &&
13595 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13596 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13597 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13598 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13599 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13602 tg3_phy_lpbk_set(tp, 0, true);
13604 /* All link indications report up, but the hardware
13605 * isn't really ready for about 20 msec. Double it
13610 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13611 data[TG3_EXT_LOOPB_TEST] |=
13612 TG3_STD_LOOPBACK_FAILED;
13613 if (tg3_flag(tp, TSO_CAPABLE) &&
13614 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13615 data[TG3_EXT_LOOPB_TEST] |=
13616 TG3_TSO_LOOPBACK_FAILED;
13617 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13618 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13619 data[TG3_EXT_LOOPB_TEST] |=
13620 TG3_JMB_LOOPBACK_FAILED;
13623 /* Re-enable gphy autopowerdown. */
13624 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13625 tg3_phy_toggle_apd(tp, true);
13628 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13629 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13632 tp->phy_flags |= eee_cap;
13637 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13640 struct tg3 *tp = netdev_priv(dev);
13641 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13643 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13644 if (tg3_power_up(tp)) {
13645 etest->flags |= ETH_TEST_FL_FAILED;
13646 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13649 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13652 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13654 if (tg3_test_nvram(tp) != 0) {
13655 etest->flags |= ETH_TEST_FL_FAILED;
13656 data[TG3_NVRAM_TEST] = 1;
13658 if (!doextlpbk && tg3_test_link(tp)) {
13659 etest->flags |= ETH_TEST_FL_FAILED;
13660 data[TG3_LINK_TEST] = 1;
13662 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13663 int err, err2 = 0, irq_sync = 0;
13665 if (netif_running(dev)) {
13667 tg3_netif_stop(tp);
13671 tg3_full_lock(tp, irq_sync);
13672 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13673 err = tg3_nvram_lock(tp);
13674 tg3_halt_cpu(tp, RX_CPU_BASE);
13675 if (!tg3_flag(tp, 5705_PLUS))
13676 tg3_halt_cpu(tp, TX_CPU_BASE);
13678 tg3_nvram_unlock(tp);
13680 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13683 if (tg3_test_registers(tp) != 0) {
13684 etest->flags |= ETH_TEST_FL_FAILED;
13685 data[TG3_REGISTER_TEST] = 1;
13688 if (tg3_test_memory(tp) != 0) {
13689 etest->flags |= ETH_TEST_FL_FAILED;
13690 data[TG3_MEMORY_TEST] = 1;
13694 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13696 if (tg3_test_loopback(tp, data, doextlpbk))
13697 etest->flags |= ETH_TEST_FL_FAILED;
13699 tg3_full_unlock(tp);
13701 if (tg3_test_interrupt(tp) != 0) {
13702 etest->flags |= ETH_TEST_FL_FAILED;
13703 data[TG3_INTERRUPT_TEST] = 1;
13706 tg3_full_lock(tp, 0);
13708 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13709 if (netif_running(dev)) {
13710 tg3_flag_set(tp, INIT_COMPLETE);
13711 err2 = tg3_restart_hw(tp, true);
13713 tg3_netif_start(tp);
13716 tg3_full_unlock(tp);
13718 if (irq_sync && !err2)
13721 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13722 tg3_power_down_prepare(tp);
13726 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13728 struct tg3 *tp = netdev_priv(dev);
13729 struct hwtstamp_config stmpconf;
13731 if (!tg3_flag(tp, PTP_CAPABLE))
13732 return -EOPNOTSUPP;
13734 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13737 if (stmpconf.flags)
13740 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13741 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13744 switch (stmpconf.rx_filter) {
13745 case HWTSTAMP_FILTER_NONE:
13748 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13749 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13750 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13752 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13753 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13754 TG3_RX_PTP_CTL_SYNC_EVNT;
13756 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13757 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13758 TG3_RX_PTP_CTL_DELAY_REQ;
13760 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13761 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13762 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13764 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13765 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13766 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13768 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13769 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13770 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13772 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13773 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13774 TG3_RX_PTP_CTL_SYNC_EVNT;
13776 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13777 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13778 TG3_RX_PTP_CTL_SYNC_EVNT;
13780 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13781 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13782 TG3_RX_PTP_CTL_SYNC_EVNT;
13784 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13785 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13786 TG3_RX_PTP_CTL_DELAY_REQ;
13788 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13789 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13790 TG3_RX_PTP_CTL_DELAY_REQ;
13792 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13793 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13794 TG3_RX_PTP_CTL_DELAY_REQ;
13800 if (netif_running(dev) && tp->rxptpctl)
13801 tw32(TG3_RX_PTP_CTL,
13802 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13804 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13805 tg3_flag_set(tp, TX_TSTAMP_EN);
13807 tg3_flag_clear(tp, TX_TSTAMP_EN);
13809 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13813 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13815 struct tg3 *tp = netdev_priv(dev);
13816 struct hwtstamp_config stmpconf;
13818 if (!tg3_flag(tp, PTP_CAPABLE))
13819 return -EOPNOTSUPP;
13821 stmpconf.flags = 0;
13822 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13823 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13825 switch (tp->rxptpctl) {
13827 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13829 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13830 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13832 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13833 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13835 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13836 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13838 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13839 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13841 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13842 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13844 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13845 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13847 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13848 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13850 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13851 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13853 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13854 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13856 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13857 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13859 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13860 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13862 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13863 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13870 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13874 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13876 struct mii_ioctl_data *data = if_mii(ifr);
13877 struct tg3 *tp = netdev_priv(dev);
13880 if (tg3_flag(tp, USE_PHYLIB)) {
13881 struct phy_device *phydev;
13882 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13884 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13885 return phy_mii_ioctl(phydev, ifr, cmd);
13890 data->phy_id = tp->phy_addr;
13893 case SIOCGMIIREG: {
13896 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13897 break; /* We have no PHY */
13899 if (!netif_running(dev))
13902 spin_lock_bh(&tp->lock);
13903 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13904 data->reg_num & 0x1f, &mii_regval);
13905 spin_unlock_bh(&tp->lock);
13907 data->val_out = mii_regval;
13913 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13914 break; /* We have no PHY */
13916 if (!netif_running(dev))
13919 spin_lock_bh(&tp->lock);
13920 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13921 data->reg_num & 0x1f, data->val_in);
13922 spin_unlock_bh(&tp->lock);
13926 case SIOCSHWTSTAMP:
13927 return tg3_hwtstamp_set(dev, ifr);
13929 case SIOCGHWTSTAMP:
13930 return tg3_hwtstamp_get(dev, ifr);
13936 return -EOPNOTSUPP;
13939 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13941 struct tg3 *tp = netdev_priv(dev);
13943 memcpy(ec, &tp->coal, sizeof(*ec));
13947 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13949 struct tg3 *tp = netdev_priv(dev);
13950 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13951 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13953 if (!tg3_flag(tp, 5705_PLUS)) {
13954 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13955 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13956 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13957 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13960 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13961 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13962 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13963 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13964 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13965 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13966 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13967 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13968 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13969 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13972 /* No rx interrupts will be generated if both are zero */
13973 if ((ec->rx_coalesce_usecs == 0) &&
13974 (ec->rx_max_coalesced_frames == 0))
13977 /* No tx interrupts will be generated if both are zero */
13978 if ((ec->tx_coalesce_usecs == 0) &&
13979 (ec->tx_max_coalesced_frames == 0))
13982 /* Only copy relevant parameters, ignore all others. */
13983 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13984 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13985 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13986 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13987 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13988 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13989 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13990 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13991 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13993 if (netif_running(dev)) {
13994 tg3_full_lock(tp, 0);
13995 __tg3_set_coalesce(tp, &tp->coal);
13996 tg3_full_unlock(tp);
14001 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14003 struct tg3 *tp = netdev_priv(dev);
14005 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14006 netdev_warn(tp->dev, "Board does not support EEE!\n");
14007 return -EOPNOTSUPP;
14010 if (edata->advertised != tp->eee.advertised) {
14011 netdev_warn(tp->dev,
14012 "Direct manipulation of EEE advertisement is not supported\n");
14016 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14017 netdev_warn(tp->dev,
14018 "Maximal Tx Lpi timer supported is %#x(u)\n",
14019 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14025 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14026 tg3_warn_mgmt_link_flap(tp);
14028 if (netif_running(tp->dev)) {
14029 tg3_full_lock(tp, 0);
14032 tg3_full_unlock(tp);
14038 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14040 struct tg3 *tp = netdev_priv(dev);
14042 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14043 netdev_warn(tp->dev,
14044 "Board does not support EEE!\n");
14045 return -EOPNOTSUPP;
14052 static const struct ethtool_ops tg3_ethtool_ops = {
14053 .get_settings = tg3_get_settings,
14054 .set_settings = tg3_set_settings,
14055 .get_drvinfo = tg3_get_drvinfo,
14056 .get_regs_len = tg3_get_regs_len,
14057 .get_regs = tg3_get_regs,
14058 .get_wol = tg3_get_wol,
14059 .set_wol = tg3_set_wol,
14060 .get_msglevel = tg3_get_msglevel,
14061 .set_msglevel = tg3_set_msglevel,
14062 .nway_reset = tg3_nway_reset,
14063 .get_link = ethtool_op_get_link,
14064 .get_eeprom_len = tg3_get_eeprom_len,
14065 .get_eeprom = tg3_get_eeprom,
14066 .set_eeprom = tg3_set_eeprom,
14067 .get_ringparam = tg3_get_ringparam,
14068 .set_ringparam = tg3_set_ringparam,
14069 .get_pauseparam = tg3_get_pauseparam,
14070 .set_pauseparam = tg3_set_pauseparam,
14071 .self_test = tg3_self_test,
14072 .get_strings = tg3_get_strings,
14073 .set_phys_id = tg3_set_phys_id,
14074 .get_ethtool_stats = tg3_get_ethtool_stats,
14075 .get_coalesce = tg3_get_coalesce,
14076 .set_coalesce = tg3_set_coalesce,
14077 .get_sset_count = tg3_get_sset_count,
14078 .get_rxnfc = tg3_get_rxnfc,
14079 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14080 .get_rxfh = tg3_get_rxfh,
14081 .set_rxfh = tg3_set_rxfh,
14082 .get_channels = tg3_get_channels,
14083 .set_channels = tg3_set_channels,
14084 .get_ts_info = tg3_get_ts_info,
14085 .get_eee = tg3_get_eee,
14086 .set_eee = tg3_set_eee,
14089 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14090 struct rtnl_link_stats64 *stats)
14092 struct tg3 *tp = netdev_priv(dev);
14094 spin_lock_bh(&tp->lock);
14095 if (!tp->hw_stats) {
14096 *stats = tp->net_stats_prev;
14097 spin_unlock_bh(&tp->lock);
14101 tg3_get_nstats(tp, stats);
14102 spin_unlock_bh(&tp->lock);
14107 static void tg3_set_rx_mode(struct net_device *dev)
14109 struct tg3 *tp = netdev_priv(dev);
14111 if (!netif_running(dev))
14114 tg3_full_lock(tp, 0);
14115 __tg3_set_rx_mode(dev);
14116 tg3_full_unlock(tp);
14119 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14122 dev->mtu = new_mtu;
14124 if (new_mtu > ETH_DATA_LEN) {
14125 if (tg3_flag(tp, 5780_CLASS)) {
14126 netdev_update_features(dev);
14127 tg3_flag_clear(tp, TSO_CAPABLE);
14129 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14132 if (tg3_flag(tp, 5780_CLASS)) {
14133 tg3_flag_set(tp, TSO_CAPABLE);
14134 netdev_update_features(dev);
14136 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14140 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14142 struct tg3 *tp = netdev_priv(dev);
14144 bool reset_phy = false;
14146 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14149 if (!netif_running(dev)) {
14150 /* We'll just catch it later when the
14153 tg3_set_mtu(dev, tp, new_mtu);
14159 tg3_netif_stop(tp);
14161 tg3_set_mtu(dev, tp, new_mtu);
14163 tg3_full_lock(tp, 1);
14165 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14167 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14168 * breaks all requests to 256 bytes.
14170 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14173 err = tg3_restart_hw(tp, reset_phy);
14176 tg3_netif_start(tp);
14178 tg3_full_unlock(tp);
14186 static const struct net_device_ops tg3_netdev_ops = {
14187 .ndo_open = tg3_open,
14188 .ndo_stop = tg3_close,
14189 .ndo_start_xmit = tg3_start_xmit,
14190 .ndo_get_stats64 = tg3_get_stats64,
14191 .ndo_validate_addr = eth_validate_addr,
14192 .ndo_set_rx_mode = tg3_set_rx_mode,
14193 .ndo_set_mac_address = tg3_set_mac_addr,
14194 .ndo_do_ioctl = tg3_ioctl,
14195 .ndo_tx_timeout = tg3_tx_timeout,
14196 .ndo_change_mtu = tg3_change_mtu,
14197 .ndo_fix_features = tg3_fix_features,
14198 .ndo_set_features = tg3_set_features,
14199 #ifdef CONFIG_NET_POLL_CONTROLLER
14200 .ndo_poll_controller = tg3_poll_controller,
14204 static void tg3_get_eeprom_size(struct tg3 *tp)
14206 u32 cursize, val, magic;
14208 tp->nvram_size = EEPROM_CHIP_SIZE;
14210 if (tg3_nvram_read(tp, 0, &magic) != 0)
14213 if ((magic != TG3_EEPROM_MAGIC) &&
14214 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14215 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14219 * Size the chip by reading offsets at increasing powers of two.
14220 * When we encounter our validation signature, we know the addressing
14221 * has wrapped around, and thus have our chip size.
14225 while (cursize < tp->nvram_size) {
14226 if (tg3_nvram_read(tp, cursize, &val) != 0)
14235 tp->nvram_size = cursize;
14238 static void tg3_get_nvram_size(struct tg3 *tp)
14242 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14245 /* Selfboot format */
14246 if (val != TG3_EEPROM_MAGIC) {
14247 tg3_get_eeprom_size(tp);
14251 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14253 /* This is confusing. We want to operate on the
14254 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14255 * call will read from NVRAM and byteswap the data
14256 * according to the byteswapping settings for all
14257 * other register accesses. This ensures the data we
14258 * want will always reside in the lower 16-bits.
14259 * However, the data in NVRAM is in LE format, which
14260 * means the data from the NVRAM read will always be
14261 * opposite the endianness of the CPU. The 16-bit
14262 * byteswap then brings the data to CPU endianness.
14264 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14268 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14271 static void tg3_get_nvram_info(struct tg3 *tp)
14275 nvcfg1 = tr32(NVRAM_CFG1);
14276 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14277 tg3_flag_set(tp, FLASH);
14279 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14280 tw32(NVRAM_CFG1, nvcfg1);
14283 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14284 tg3_flag(tp, 5780_CLASS)) {
14285 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14286 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14287 tp->nvram_jedecnum = JEDEC_ATMEL;
14288 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14289 tg3_flag_set(tp, NVRAM_BUFFERED);
14291 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14292 tp->nvram_jedecnum = JEDEC_ATMEL;
14293 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14295 case FLASH_VENDOR_ATMEL_EEPROM:
14296 tp->nvram_jedecnum = JEDEC_ATMEL;
14297 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14298 tg3_flag_set(tp, NVRAM_BUFFERED);
14300 case FLASH_VENDOR_ST:
14301 tp->nvram_jedecnum = JEDEC_ST;
14302 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14303 tg3_flag_set(tp, NVRAM_BUFFERED);
14305 case FLASH_VENDOR_SAIFUN:
14306 tp->nvram_jedecnum = JEDEC_SAIFUN;
14307 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14309 case FLASH_VENDOR_SST_SMALL:
14310 case FLASH_VENDOR_SST_LARGE:
14311 tp->nvram_jedecnum = JEDEC_SST;
14312 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14316 tp->nvram_jedecnum = JEDEC_ATMEL;
14317 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14318 tg3_flag_set(tp, NVRAM_BUFFERED);
14322 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14324 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14325 case FLASH_5752PAGE_SIZE_256:
14326 tp->nvram_pagesize = 256;
14328 case FLASH_5752PAGE_SIZE_512:
14329 tp->nvram_pagesize = 512;
14331 case FLASH_5752PAGE_SIZE_1K:
14332 tp->nvram_pagesize = 1024;
14334 case FLASH_5752PAGE_SIZE_2K:
14335 tp->nvram_pagesize = 2048;
14337 case FLASH_5752PAGE_SIZE_4K:
14338 tp->nvram_pagesize = 4096;
14340 case FLASH_5752PAGE_SIZE_264:
14341 tp->nvram_pagesize = 264;
14343 case FLASH_5752PAGE_SIZE_528:
14344 tp->nvram_pagesize = 528;
14349 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14353 nvcfg1 = tr32(NVRAM_CFG1);
14355 /* NVRAM protection for TPM */
14356 if (nvcfg1 & (1 << 27))
14357 tg3_flag_set(tp, PROTECTED_NVRAM);
14359 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14360 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14361 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14362 tp->nvram_jedecnum = JEDEC_ATMEL;
14363 tg3_flag_set(tp, NVRAM_BUFFERED);
14365 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14366 tp->nvram_jedecnum = JEDEC_ATMEL;
14367 tg3_flag_set(tp, NVRAM_BUFFERED);
14368 tg3_flag_set(tp, FLASH);
14370 case FLASH_5752VENDOR_ST_M45PE10:
14371 case FLASH_5752VENDOR_ST_M45PE20:
14372 case FLASH_5752VENDOR_ST_M45PE40:
14373 tp->nvram_jedecnum = JEDEC_ST;
14374 tg3_flag_set(tp, NVRAM_BUFFERED);
14375 tg3_flag_set(tp, FLASH);
14379 if (tg3_flag(tp, FLASH)) {
14380 tg3_nvram_get_pagesize(tp, nvcfg1);
14382 /* For eeprom, set pagesize to maximum eeprom size */
14383 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14385 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14386 tw32(NVRAM_CFG1, nvcfg1);
14390 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14392 u32 nvcfg1, protect = 0;
14394 nvcfg1 = tr32(NVRAM_CFG1);
14396 /* NVRAM protection for TPM */
14397 if (nvcfg1 & (1 << 27)) {
14398 tg3_flag_set(tp, PROTECTED_NVRAM);
14402 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14404 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14405 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14406 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14407 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14408 tp->nvram_jedecnum = JEDEC_ATMEL;
14409 tg3_flag_set(tp, NVRAM_BUFFERED);
14410 tg3_flag_set(tp, FLASH);
14411 tp->nvram_pagesize = 264;
14412 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14413 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14414 tp->nvram_size = (protect ? 0x3e200 :
14415 TG3_NVRAM_SIZE_512KB);
14416 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14417 tp->nvram_size = (protect ? 0x1f200 :
14418 TG3_NVRAM_SIZE_256KB);
14420 tp->nvram_size = (protect ? 0x1f200 :
14421 TG3_NVRAM_SIZE_128KB);
14423 case FLASH_5752VENDOR_ST_M45PE10:
14424 case FLASH_5752VENDOR_ST_M45PE20:
14425 case FLASH_5752VENDOR_ST_M45PE40:
14426 tp->nvram_jedecnum = JEDEC_ST;
14427 tg3_flag_set(tp, NVRAM_BUFFERED);
14428 tg3_flag_set(tp, FLASH);
14429 tp->nvram_pagesize = 256;
14430 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14431 tp->nvram_size = (protect ?
14432 TG3_NVRAM_SIZE_64KB :
14433 TG3_NVRAM_SIZE_128KB);
14434 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14435 tp->nvram_size = (protect ?
14436 TG3_NVRAM_SIZE_64KB :
14437 TG3_NVRAM_SIZE_256KB);
14439 tp->nvram_size = (protect ?
14440 TG3_NVRAM_SIZE_128KB :
14441 TG3_NVRAM_SIZE_512KB);
14446 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14450 nvcfg1 = tr32(NVRAM_CFG1);
14452 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14453 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14454 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14455 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14456 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14457 tp->nvram_jedecnum = JEDEC_ATMEL;
14458 tg3_flag_set(tp, NVRAM_BUFFERED);
14459 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14461 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14462 tw32(NVRAM_CFG1, nvcfg1);
14464 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14465 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14466 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14467 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14468 tp->nvram_jedecnum = JEDEC_ATMEL;
14469 tg3_flag_set(tp, NVRAM_BUFFERED);
14470 tg3_flag_set(tp, FLASH);
14471 tp->nvram_pagesize = 264;
14473 case FLASH_5752VENDOR_ST_M45PE10:
14474 case FLASH_5752VENDOR_ST_M45PE20:
14475 case FLASH_5752VENDOR_ST_M45PE40:
14476 tp->nvram_jedecnum = JEDEC_ST;
14477 tg3_flag_set(tp, NVRAM_BUFFERED);
14478 tg3_flag_set(tp, FLASH);
14479 tp->nvram_pagesize = 256;
14484 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14486 u32 nvcfg1, protect = 0;
14488 nvcfg1 = tr32(NVRAM_CFG1);
14490 /* NVRAM protection for TPM */
14491 if (nvcfg1 & (1 << 27)) {
14492 tg3_flag_set(tp, PROTECTED_NVRAM);
14496 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14498 case FLASH_5761VENDOR_ATMEL_ADB021D:
14499 case FLASH_5761VENDOR_ATMEL_ADB041D:
14500 case FLASH_5761VENDOR_ATMEL_ADB081D:
14501 case FLASH_5761VENDOR_ATMEL_ADB161D:
14502 case FLASH_5761VENDOR_ATMEL_MDB021D:
14503 case FLASH_5761VENDOR_ATMEL_MDB041D:
14504 case FLASH_5761VENDOR_ATMEL_MDB081D:
14505 case FLASH_5761VENDOR_ATMEL_MDB161D:
14506 tp->nvram_jedecnum = JEDEC_ATMEL;
14507 tg3_flag_set(tp, NVRAM_BUFFERED);
14508 tg3_flag_set(tp, FLASH);
14509 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14510 tp->nvram_pagesize = 256;
14512 case FLASH_5761VENDOR_ST_A_M45PE20:
14513 case FLASH_5761VENDOR_ST_A_M45PE40:
14514 case FLASH_5761VENDOR_ST_A_M45PE80:
14515 case FLASH_5761VENDOR_ST_A_M45PE16:
14516 case FLASH_5761VENDOR_ST_M_M45PE20:
14517 case FLASH_5761VENDOR_ST_M_M45PE40:
14518 case FLASH_5761VENDOR_ST_M_M45PE80:
14519 case FLASH_5761VENDOR_ST_M_M45PE16:
14520 tp->nvram_jedecnum = JEDEC_ST;
14521 tg3_flag_set(tp, NVRAM_BUFFERED);
14522 tg3_flag_set(tp, FLASH);
14523 tp->nvram_pagesize = 256;
14528 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14531 case FLASH_5761VENDOR_ATMEL_ADB161D:
14532 case FLASH_5761VENDOR_ATMEL_MDB161D:
14533 case FLASH_5761VENDOR_ST_A_M45PE16:
14534 case FLASH_5761VENDOR_ST_M_M45PE16:
14535 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14537 case FLASH_5761VENDOR_ATMEL_ADB081D:
14538 case FLASH_5761VENDOR_ATMEL_MDB081D:
14539 case FLASH_5761VENDOR_ST_A_M45PE80:
14540 case FLASH_5761VENDOR_ST_M_M45PE80:
14541 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14543 case FLASH_5761VENDOR_ATMEL_ADB041D:
14544 case FLASH_5761VENDOR_ATMEL_MDB041D:
14545 case FLASH_5761VENDOR_ST_A_M45PE40:
14546 case FLASH_5761VENDOR_ST_M_M45PE40:
14547 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14549 case FLASH_5761VENDOR_ATMEL_ADB021D:
14550 case FLASH_5761VENDOR_ATMEL_MDB021D:
14551 case FLASH_5761VENDOR_ST_A_M45PE20:
14552 case FLASH_5761VENDOR_ST_M_M45PE20:
14553 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14559 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14561 tp->nvram_jedecnum = JEDEC_ATMEL;
14562 tg3_flag_set(tp, NVRAM_BUFFERED);
14563 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14566 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14570 nvcfg1 = tr32(NVRAM_CFG1);
14572 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14573 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14574 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14575 tp->nvram_jedecnum = JEDEC_ATMEL;
14576 tg3_flag_set(tp, NVRAM_BUFFERED);
14577 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14579 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14580 tw32(NVRAM_CFG1, nvcfg1);
14582 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14583 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14584 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14585 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14586 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14587 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14588 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14589 tp->nvram_jedecnum = JEDEC_ATMEL;
14590 tg3_flag_set(tp, NVRAM_BUFFERED);
14591 tg3_flag_set(tp, FLASH);
14593 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14594 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14595 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14596 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14597 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14599 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14600 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14601 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14603 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14604 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14605 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14609 case FLASH_5752VENDOR_ST_M45PE10:
14610 case FLASH_5752VENDOR_ST_M45PE20:
14611 case FLASH_5752VENDOR_ST_M45PE40:
14612 tp->nvram_jedecnum = JEDEC_ST;
14613 tg3_flag_set(tp, NVRAM_BUFFERED);
14614 tg3_flag_set(tp, FLASH);
14616 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14617 case FLASH_5752VENDOR_ST_M45PE10:
14618 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14620 case FLASH_5752VENDOR_ST_M45PE20:
14621 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14623 case FLASH_5752VENDOR_ST_M45PE40:
14624 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14629 tg3_flag_set(tp, NO_NVRAM);
14633 tg3_nvram_get_pagesize(tp, nvcfg1);
14634 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14635 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14639 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14643 nvcfg1 = tr32(NVRAM_CFG1);
14645 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14646 case FLASH_5717VENDOR_ATMEL_EEPROM:
14647 case FLASH_5717VENDOR_MICRO_EEPROM:
14648 tp->nvram_jedecnum = JEDEC_ATMEL;
14649 tg3_flag_set(tp, NVRAM_BUFFERED);
14650 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14652 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14653 tw32(NVRAM_CFG1, nvcfg1);
14655 case FLASH_5717VENDOR_ATMEL_MDB011D:
14656 case FLASH_5717VENDOR_ATMEL_ADB011B:
14657 case FLASH_5717VENDOR_ATMEL_ADB011D:
14658 case FLASH_5717VENDOR_ATMEL_MDB021D:
14659 case FLASH_5717VENDOR_ATMEL_ADB021B:
14660 case FLASH_5717VENDOR_ATMEL_ADB021D:
14661 case FLASH_5717VENDOR_ATMEL_45USPT:
14662 tp->nvram_jedecnum = JEDEC_ATMEL;
14663 tg3_flag_set(tp, NVRAM_BUFFERED);
14664 tg3_flag_set(tp, FLASH);
14666 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14667 case FLASH_5717VENDOR_ATMEL_MDB021D:
14668 /* Detect size with tg3_nvram_get_size() */
14670 case FLASH_5717VENDOR_ATMEL_ADB021B:
14671 case FLASH_5717VENDOR_ATMEL_ADB021D:
14672 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14675 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14679 case FLASH_5717VENDOR_ST_M_M25PE10:
14680 case FLASH_5717VENDOR_ST_A_M25PE10:
14681 case FLASH_5717VENDOR_ST_M_M45PE10:
14682 case FLASH_5717VENDOR_ST_A_M45PE10:
14683 case FLASH_5717VENDOR_ST_M_M25PE20:
14684 case FLASH_5717VENDOR_ST_A_M25PE20:
14685 case FLASH_5717VENDOR_ST_M_M45PE20:
14686 case FLASH_5717VENDOR_ST_A_M45PE20:
14687 case FLASH_5717VENDOR_ST_25USPT:
14688 case FLASH_5717VENDOR_ST_45USPT:
14689 tp->nvram_jedecnum = JEDEC_ST;
14690 tg3_flag_set(tp, NVRAM_BUFFERED);
14691 tg3_flag_set(tp, FLASH);
14693 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14694 case FLASH_5717VENDOR_ST_M_M25PE20:
14695 case FLASH_5717VENDOR_ST_M_M45PE20:
14696 /* Detect size with tg3_nvram_get_size() */
14698 case FLASH_5717VENDOR_ST_A_M25PE20:
14699 case FLASH_5717VENDOR_ST_A_M45PE20:
14700 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14703 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14708 tg3_flag_set(tp, NO_NVRAM);
14712 tg3_nvram_get_pagesize(tp, nvcfg1);
14713 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14714 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14717 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14719 u32 nvcfg1, nvmpinstrp;
14721 nvcfg1 = tr32(NVRAM_CFG1);
14722 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14724 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14725 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14726 tg3_flag_set(tp, NO_NVRAM);
14730 switch (nvmpinstrp) {
14731 case FLASH_5762_EEPROM_HD:
14732 nvmpinstrp = FLASH_5720_EEPROM_HD;
14734 case FLASH_5762_EEPROM_LD:
14735 nvmpinstrp = FLASH_5720_EEPROM_LD;
14737 case FLASH_5720VENDOR_M_ST_M45PE20:
14738 /* This pinstrap supports multiple sizes, so force it
14739 * to read the actual size from location 0xf0.
14741 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14746 switch (nvmpinstrp) {
14747 case FLASH_5720_EEPROM_HD:
14748 case FLASH_5720_EEPROM_LD:
14749 tp->nvram_jedecnum = JEDEC_ATMEL;
14750 tg3_flag_set(tp, NVRAM_BUFFERED);
14752 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14753 tw32(NVRAM_CFG1, nvcfg1);
14754 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14757 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14759 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14760 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14761 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14762 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14763 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14764 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14765 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14766 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14767 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14768 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14769 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14770 case FLASH_5720VENDOR_ATMEL_45USPT:
14771 tp->nvram_jedecnum = JEDEC_ATMEL;
14772 tg3_flag_set(tp, NVRAM_BUFFERED);
14773 tg3_flag_set(tp, FLASH);
14775 switch (nvmpinstrp) {
14776 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14777 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14778 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14779 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14781 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14782 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14783 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14784 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14786 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14787 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14788 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14791 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14792 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14796 case FLASH_5720VENDOR_M_ST_M25PE10:
14797 case FLASH_5720VENDOR_M_ST_M45PE10:
14798 case FLASH_5720VENDOR_A_ST_M25PE10:
14799 case FLASH_5720VENDOR_A_ST_M45PE10:
14800 case FLASH_5720VENDOR_M_ST_M25PE20:
14801 case FLASH_5720VENDOR_M_ST_M45PE20:
14802 case FLASH_5720VENDOR_A_ST_M25PE20:
14803 case FLASH_5720VENDOR_A_ST_M45PE20:
14804 case FLASH_5720VENDOR_M_ST_M25PE40:
14805 case FLASH_5720VENDOR_M_ST_M45PE40:
14806 case FLASH_5720VENDOR_A_ST_M25PE40:
14807 case FLASH_5720VENDOR_A_ST_M45PE40:
14808 case FLASH_5720VENDOR_M_ST_M25PE80:
14809 case FLASH_5720VENDOR_M_ST_M45PE80:
14810 case FLASH_5720VENDOR_A_ST_M25PE80:
14811 case FLASH_5720VENDOR_A_ST_M45PE80:
14812 case FLASH_5720VENDOR_ST_25USPT:
14813 case FLASH_5720VENDOR_ST_45USPT:
14814 tp->nvram_jedecnum = JEDEC_ST;
14815 tg3_flag_set(tp, NVRAM_BUFFERED);
14816 tg3_flag_set(tp, FLASH);
14818 switch (nvmpinstrp) {
14819 case FLASH_5720VENDOR_M_ST_M25PE20:
14820 case FLASH_5720VENDOR_M_ST_M45PE20:
14821 case FLASH_5720VENDOR_A_ST_M25PE20:
14822 case FLASH_5720VENDOR_A_ST_M45PE20:
14823 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14825 case FLASH_5720VENDOR_M_ST_M25PE40:
14826 case FLASH_5720VENDOR_M_ST_M45PE40:
14827 case FLASH_5720VENDOR_A_ST_M25PE40:
14828 case FLASH_5720VENDOR_A_ST_M45PE40:
14829 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14831 case FLASH_5720VENDOR_M_ST_M25PE80:
14832 case FLASH_5720VENDOR_M_ST_M45PE80:
14833 case FLASH_5720VENDOR_A_ST_M25PE80:
14834 case FLASH_5720VENDOR_A_ST_M45PE80:
14835 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14838 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14839 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14844 tg3_flag_set(tp, NO_NVRAM);
14848 tg3_nvram_get_pagesize(tp, nvcfg1);
14849 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14850 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14852 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14855 if (tg3_nvram_read(tp, 0, &val))
14858 if (val != TG3_EEPROM_MAGIC &&
14859 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14860 tg3_flag_set(tp, NO_NVRAM);
14864 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14865 static void tg3_nvram_init(struct tg3 *tp)
14867 if (tg3_flag(tp, IS_SSB_CORE)) {
14868 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14869 tg3_flag_clear(tp, NVRAM);
14870 tg3_flag_clear(tp, NVRAM_BUFFERED);
14871 tg3_flag_set(tp, NO_NVRAM);
14875 tw32_f(GRC_EEPROM_ADDR,
14876 (EEPROM_ADDR_FSM_RESET |
14877 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14878 EEPROM_ADDR_CLKPERD_SHIFT)));
14882 /* Enable seeprom accesses. */
14883 tw32_f(GRC_LOCAL_CTRL,
14884 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14887 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14888 tg3_asic_rev(tp) != ASIC_REV_5701) {
14889 tg3_flag_set(tp, NVRAM);
14891 if (tg3_nvram_lock(tp)) {
14892 netdev_warn(tp->dev,
14893 "Cannot get nvram lock, %s failed\n",
14897 tg3_enable_nvram_access(tp);
14899 tp->nvram_size = 0;
14901 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14902 tg3_get_5752_nvram_info(tp);
14903 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14904 tg3_get_5755_nvram_info(tp);
14905 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14906 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14907 tg3_asic_rev(tp) == ASIC_REV_5785)
14908 tg3_get_5787_nvram_info(tp);
14909 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14910 tg3_get_5761_nvram_info(tp);
14911 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14912 tg3_get_5906_nvram_info(tp);
14913 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14914 tg3_flag(tp, 57765_CLASS))
14915 tg3_get_57780_nvram_info(tp);
14916 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14917 tg3_asic_rev(tp) == ASIC_REV_5719)
14918 tg3_get_5717_nvram_info(tp);
14919 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14920 tg3_asic_rev(tp) == ASIC_REV_5762)
14921 tg3_get_5720_nvram_info(tp);
14923 tg3_get_nvram_info(tp);
14925 if (tp->nvram_size == 0)
14926 tg3_get_nvram_size(tp);
14928 tg3_disable_nvram_access(tp);
14929 tg3_nvram_unlock(tp);
14932 tg3_flag_clear(tp, NVRAM);
14933 tg3_flag_clear(tp, NVRAM_BUFFERED);
14935 tg3_get_eeprom_size(tp);
14939 struct subsys_tbl_ent {
14940 u16 subsys_vendor, subsys_devid;
14944 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14945 /* Broadcom boards. */
14946 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14947 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14948 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14949 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14950 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14951 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14952 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14953 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14954 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14955 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14956 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14957 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14958 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14959 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14960 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14961 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14962 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14963 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14964 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14965 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14966 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14967 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14970 { TG3PCI_SUBVENDOR_ID_3COM,
14971 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14972 { TG3PCI_SUBVENDOR_ID_3COM,
14973 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14974 { TG3PCI_SUBVENDOR_ID_3COM,
14975 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14976 { TG3PCI_SUBVENDOR_ID_3COM,
14977 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14978 { TG3PCI_SUBVENDOR_ID_3COM,
14979 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14982 { TG3PCI_SUBVENDOR_ID_DELL,
14983 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14984 { TG3PCI_SUBVENDOR_ID_DELL,
14985 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14986 { TG3PCI_SUBVENDOR_ID_DELL,
14987 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14988 { TG3PCI_SUBVENDOR_ID_DELL,
14989 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14991 /* Compaq boards. */
14992 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14993 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14994 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14995 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14996 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14997 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14998 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14999 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15000 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15001 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15004 { TG3PCI_SUBVENDOR_ID_IBM,
15005 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15008 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15012 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15013 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15014 tp->pdev->subsystem_vendor) &&
15015 (subsys_id_to_phy_id[i].subsys_devid ==
15016 tp->pdev->subsystem_device))
15017 return &subsys_id_to_phy_id[i];
15022 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15026 tp->phy_id = TG3_PHY_ID_INVALID;
15027 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15029 /* Assume an onboard device and WOL capable by default. */
15030 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15031 tg3_flag_set(tp, WOL_CAP);
15033 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15034 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15035 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15036 tg3_flag_set(tp, IS_NIC);
15038 val = tr32(VCPU_CFGSHDW);
15039 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15040 tg3_flag_set(tp, ASPM_WORKAROUND);
15041 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15042 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15043 tg3_flag_set(tp, WOL_ENABLE);
15044 device_set_wakeup_enable(&tp->pdev->dev, true);
15049 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15050 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15051 u32 nic_cfg, led_cfg;
15052 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15053 u32 nic_phy_id, ver, eeprom_phy_id;
15054 int eeprom_phy_serdes = 0;
15056 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15057 tp->nic_sram_data_cfg = nic_cfg;
15059 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15060 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15061 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15062 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15063 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15064 (ver > 0) && (ver < 0x100))
15065 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15067 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15068 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15070 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15071 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15072 tg3_asic_rev(tp) == ASIC_REV_5720)
15073 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15075 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15076 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15077 eeprom_phy_serdes = 1;
15079 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15080 if (nic_phy_id != 0) {
15081 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15082 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15084 eeprom_phy_id = (id1 >> 16) << 10;
15085 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15086 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15090 tp->phy_id = eeprom_phy_id;
15091 if (eeprom_phy_serdes) {
15092 if (!tg3_flag(tp, 5705_PLUS))
15093 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15095 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15098 if (tg3_flag(tp, 5750_PLUS))
15099 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15100 SHASTA_EXT_LED_MODE_MASK);
15102 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15106 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15107 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15110 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15111 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15114 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15115 tp->led_ctrl = LED_CTRL_MODE_MAC;
15117 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15118 * read on some older 5700/5701 bootcode.
15120 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15121 tg3_asic_rev(tp) == ASIC_REV_5701)
15122 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15126 case SHASTA_EXT_LED_SHARED:
15127 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15128 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15129 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15130 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15131 LED_CTRL_MODE_PHY_2);
15133 if (tg3_flag(tp, 5717_PLUS) ||
15134 tg3_asic_rev(tp) == ASIC_REV_5762)
15135 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15136 LED_CTRL_BLINK_RATE_MASK;
15140 case SHASTA_EXT_LED_MAC:
15141 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15144 case SHASTA_EXT_LED_COMBO:
15145 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15146 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15147 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15148 LED_CTRL_MODE_PHY_2);
15153 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15154 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15155 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15156 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15158 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15159 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15161 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15162 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15163 if ((tp->pdev->subsystem_vendor ==
15164 PCI_VENDOR_ID_ARIMA) &&
15165 (tp->pdev->subsystem_device == 0x205a ||
15166 tp->pdev->subsystem_device == 0x2063))
15167 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15169 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15170 tg3_flag_set(tp, IS_NIC);
15173 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15174 tg3_flag_set(tp, ENABLE_ASF);
15175 if (tg3_flag(tp, 5750_PLUS))
15176 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15179 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15180 tg3_flag(tp, 5750_PLUS))
15181 tg3_flag_set(tp, ENABLE_APE);
15183 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15184 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15185 tg3_flag_clear(tp, WOL_CAP);
15187 if (tg3_flag(tp, WOL_CAP) &&
15188 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15189 tg3_flag_set(tp, WOL_ENABLE);
15190 device_set_wakeup_enable(&tp->pdev->dev, true);
15193 if (cfg2 & (1 << 17))
15194 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15196 /* serdes signal pre-emphasis in register 0x590 set by */
15197 /* bootcode if bit 18 is set */
15198 if (cfg2 & (1 << 18))
15199 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15201 if ((tg3_flag(tp, 57765_PLUS) ||
15202 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15203 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15204 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15205 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15207 if (tg3_flag(tp, PCI_EXPRESS)) {
15210 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15211 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15212 !tg3_flag(tp, 57765_PLUS) &&
15213 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15214 tg3_flag_set(tp, ASPM_WORKAROUND);
15215 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15216 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15217 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15218 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15221 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15222 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15223 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15224 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15225 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15226 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15228 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15229 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15232 if (tg3_flag(tp, WOL_CAP))
15233 device_set_wakeup_enable(&tp->pdev->dev,
15234 tg3_flag(tp, WOL_ENABLE));
15236 device_set_wakeup_capable(&tp->pdev->dev, false);
15239 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15242 u32 val2, off = offset * 8;
15244 err = tg3_nvram_lock(tp);
15248 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15249 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15250 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15251 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15254 for (i = 0; i < 100; i++) {
15255 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15256 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15257 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15263 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15265 tg3_nvram_unlock(tp);
15266 if (val2 & APE_OTP_STATUS_CMD_DONE)
15272 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15277 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15278 tw32(OTP_CTRL, cmd);
15280 /* Wait for up to 1 ms for command to execute. */
15281 for (i = 0; i < 100; i++) {
15282 val = tr32(OTP_STATUS);
15283 if (val & OTP_STATUS_CMD_DONE)
15288 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15291 /* Read the gphy configuration from the OTP region of the chip. The gphy
15292 * configuration is a 32-bit value that straddles the alignment boundary.
15293 * We do two 32-bit reads and then shift and merge the results.
15295 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15297 u32 bhalf_otp, thalf_otp;
15299 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15301 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15304 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15306 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15309 thalf_otp = tr32(OTP_READ_DATA);
15311 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15313 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15316 bhalf_otp = tr32(OTP_READ_DATA);
15318 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15321 static void tg3_phy_init_link_config(struct tg3 *tp)
15323 u32 adv = ADVERTISED_Autoneg;
15325 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15326 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15327 adv |= ADVERTISED_1000baseT_Half;
15328 adv |= ADVERTISED_1000baseT_Full;
15331 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15332 adv |= ADVERTISED_100baseT_Half |
15333 ADVERTISED_100baseT_Full |
15334 ADVERTISED_10baseT_Half |
15335 ADVERTISED_10baseT_Full |
15338 adv |= ADVERTISED_FIBRE;
15340 tp->link_config.advertising = adv;
15341 tp->link_config.speed = SPEED_UNKNOWN;
15342 tp->link_config.duplex = DUPLEX_UNKNOWN;
15343 tp->link_config.autoneg = AUTONEG_ENABLE;
15344 tp->link_config.active_speed = SPEED_UNKNOWN;
15345 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15350 static int tg3_phy_probe(struct tg3 *tp)
15352 u32 hw_phy_id_1, hw_phy_id_2;
15353 u32 hw_phy_id, hw_phy_id_masked;
15356 /* flow control autonegotiation is default behavior */
15357 tg3_flag_set(tp, PAUSE_AUTONEG);
15358 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15360 if (tg3_flag(tp, ENABLE_APE)) {
15361 switch (tp->pci_fn) {
15363 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15366 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15369 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15372 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15377 if (!tg3_flag(tp, ENABLE_ASF) &&
15378 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15379 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15380 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15381 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15383 if (tg3_flag(tp, USE_PHYLIB))
15384 return tg3_phy_init(tp);
15386 /* Reading the PHY ID register can conflict with ASF
15387 * firmware access to the PHY hardware.
15390 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15391 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15393 /* Now read the physical PHY_ID from the chip and verify
15394 * that it is sane. If it doesn't look good, we fall back
15395 * to either the hard-coded table based PHY_ID and failing
15396 * that the value found in the eeprom area.
15398 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15399 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15401 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15402 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15403 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15405 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15408 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15409 tp->phy_id = hw_phy_id;
15410 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15411 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15413 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15415 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15416 /* Do nothing, phy ID already set up in
15417 * tg3_get_eeprom_hw_cfg().
15420 struct subsys_tbl_ent *p;
15422 /* No eeprom signature? Try the hardcoded
15423 * subsys device table.
15425 p = tg3_lookup_by_subsys(tp);
15427 tp->phy_id = p->phy_id;
15428 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15429 /* For now we saw the IDs 0xbc050cd0,
15430 * 0xbc050f80 and 0xbc050c30 on devices
15431 * connected to an BCM4785 and there are
15432 * probably more. Just assume that the phy is
15433 * supported when it is connected to a SSB core
15440 tp->phy_id == TG3_PHY_ID_BCM8002)
15441 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15445 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15446 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15447 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15448 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15449 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15450 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15451 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15452 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15453 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15454 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15456 tp->eee.supported = SUPPORTED_100baseT_Full |
15457 SUPPORTED_1000baseT_Full;
15458 tp->eee.advertised = ADVERTISED_100baseT_Full |
15459 ADVERTISED_1000baseT_Full;
15460 tp->eee.eee_enabled = 1;
15461 tp->eee.tx_lpi_enabled = 1;
15462 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15465 tg3_phy_init_link_config(tp);
15467 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15468 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15469 !tg3_flag(tp, ENABLE_APE) &&
15470 !tg3_flag(tp, ENABLE_ASF)) {
15473 tg3_readphy(tp, MII_BMSR, &bmsr);
15474 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15475 (bmsr & BMSR_LSTATUS))
15476 goto skip_phy_reset;
15478 err = tg3_phy_reset(tp);
15482 tg3_phy_set_wirespeed(tp);
15484 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15485 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15486 tp->link_config.flowctrl);
15488 tg3_writephy(tp, MII_BMCR,
15489 BMCR_ANENABLE | BMCR_ANRESTART);
15494 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15495 err = tg3_init_5401phy_dsp(tp);
15499 err = tg3_init_5401phy_dsp(tp);
15505 static void tg3_read_vpd(struct tg3 *tp)
15508 unsigned int block_end, rosize, len;
15512 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15516 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15518 goto out_not_found;
15520 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15521 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15522 i += PCI_VPD_LRDT_TAG_SIZE;
15524 if (block_end > vpdlen)
15525 goto out_not_found;
15527 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15528 PCI_VPD_RO_KEYWORD_MFR_ID);
15530 len = pci_vpd_info_field_size(&vpd_data[j]);
15532 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15533 if (j + len > block_end || len != 4 ||
15534 memcmp(&vpd_data[j], "1028", 4))
15537 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15538 PCI_VPD_RO_KEYWORD_VENDOR0);
15542 len = pci_vpd_info_field_size(&vpd_data[j]);
15544 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15545 if (j + len > block_end)
15548 if (len >= sizeof(tp->fw_ver))
15549 len = sizeof(tp->fw_ver) - 1;
15550 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15551 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15556 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15557 PCI_VPD_RO_KEYWORD_PARTNO);
15559 goto out_not_found;
15561 len = pci_vpd_info_field_size(&vpd_data[i]);
15563 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15564 if (len > TG3_BPN_SIZE ||
15565 (len + i) > vpdlen)
15566 goto out_not_found;
15568 memcpy(tp->board_part_number, &vpd_data[i], len);
15572 if (tp->board_part_number[0])
15576 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15577 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15579 strcpy(tp->board_part_number, "BCM5717");
15580 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15581 strcpy(tp->board_part_number, "BCM5718");
15584 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15585 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15586 strcpy(tp->board_part_number, "BCM57780");
15587 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15588 strcpy(tp->board_part_number, "BCM57760");
15589 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15590 strcpy(tp->board_part_number, "BCM57790");
15591 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15592 strcpy(tp->board_part_number, "BCM57788");
15595 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15596 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15597 strcpy(tp->board_part_number, "BCM57761");
15598 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15599 strcpy(tp->board_part_number, "BCM57765");
15600 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15601 strcpy(tp->board_part_number, "BCM57781");
15602 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15603 strcpy(tp->board_part_number, "BCM57785");
15604 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15605 strcpy(tp->board_part_number, "BCM57791");
15606 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15607 strcpy(tp->board_part_number, "BCM57795");
15610 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15611 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15612 strcpy(tp->board_part_number, "BCM57762");
15613 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15614 strcpy(tp->board_part_number, "BCM57766");
15615 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15616 strcpy(tp->board_part_number, "BCM57782");
15617 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15618 strcpy(tp->board_part_number, "BCM57786");
15621 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15622 strcpy(tp->board_part_number, "BCM95906");
15625 strcpy(tp->board_part_number, "none");
15629 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15633 if (tg3_nvram_read(tp, offset, &val) ||
15634 (val & 0xfc000000) != 0x0c000000 ||
15635 tg3_nvram_read(tp, offset + 4, &val) ||
15642 static void tg3_read_bc_ver(struct tg3 *tp)
15644 u32 val, offset, start, ver_offset;
15646 bool newver = false;
15648 if (tg3_nvram_read(tp, 0xc, &offset) ||
15649 tg3_nvram_read(tp, 0x4, &start))
15652 offset = tg3_nvram_logical_addr(tp, offset);
15654 if (tg3_nvram_read(tp, offset, &val))
15657 if ((val & 0xfc000000) == 0x0c000000) {
15658 if (tg3_nvram_read(tp, offset + 4, &val))
15665 dst_off = strlen(tp->fw_ver);
15668 if (TG3_VER_SIZE - dst_off < 16 ||
15669 tg3_nvram_read(tp, offset + 8, &ver_offset))
15672 offset = offset + ver_offset - start;
15673 for (i = 0; i < 16; i += 4) {
15675 if (tg3_nvram_read_be32(tp, offset + i, &v))
15678 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15683 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15686 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15687 TG3_NVM_BCVER_MAJSFT;
15688 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15689 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15690 "v%d.%02d", major, minor);
15694 static void tg3_read_hwsb_ver(struct tg3 *tp)
15696 u32 val, major, minor;
15698 /* Use native endian representation */
15699 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15702 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15703 TG3_NVM_HWSB_CFG1_MAJSFT;
15704 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15705 TG3_NVM_HWSB_CFG1_MINSFT;
15707 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15710 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15712 u32 offset, major, minor, build;
15714 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15716 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15719 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15720 case TG3_EEPROM_SB_REVISION_0:
15721 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15723 case TG3_EEPROM_SB_REVISION_2:
15724 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15726 case TG3_EEPROM_SB_REVISION_3:
15727 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15729 case TG3_EEPROM_SB_REVISION_4:
15730 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15732 case TG3_EEPROM_SB_REVISION_5:
15733 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15735 case TG3_EEPROM_SB_REVISION_6:
15736 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15742 if (tg3_nvram_read(tp, offset, &val))
15745 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15746 TG3_EEPROM_SB_EDH_BLD_SHFT;
15747 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15748 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15749 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15751 if (minor > 99 || build > 26)
15754 offset = strlen(tp->fw_ver);
15755 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15756 " v%d.%02d", major, minor);
15759 offset = strlen(tp->fw_ver);
15760 if (offset < TG3_VER_SIZE - 1)
15761 tp->fw_ver[offset] = 'a' + build - 1;
15765 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15767 u32 val, offset, start;
15770 for (offset = TG3_NVM_DIR_START;
15771 offset < TG3_NVM_DIR_END;
15772 offset += TG3_NVM_DIRENT_SIZE) {
15773 if (tg3_nvram_read(tp, offset, &val))
15776 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15780 if (offset == TG3_NVM_DIR_END)
15783 if (!tg3_flag(tp, 5705_PLUS))
15784 start = 0x08000000;
15785 else if (tg3_nvram_read(tp, offset - 4, &start))
15788 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15789 !tg3_fw_img_is_valid(tp, offset) ||
15790 tg3_nvram_read(tp, offset + 8, &val))
15793 offset += val - start;
15795 vlen = strlen(tp->fw_ver);
15797 tp->fw_ver[vlen++] = ',';
15798 tp->fw_ver[vlen++] = ' ';
15800 for (i = 0; i < 4; i++) {
15802 if (tg3_nvram_read_be32(tp, offset, &v))
15805 offset += sizeof(v);
15807 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15808 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15812 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15817 static void tg3_probe_ncsi(struct tg3 *tp)
15821 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15822 if (apedata != APE_SEG_SIG_MAGIC)
15825 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15826 if (!(apedata & APE_FW_STATUS_READY))
15829 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15830 tg3_flag_set(tp, APE_HAS_NCSI);
15833 static void tg3_read_dash_ver(struct tg3 *tp)
15839 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15841 if (tg3_flag(tp, APE_HAS_NCSI))
15843 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15848 vlen = strlen(tp->fw_ver);
15850 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15852 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15853 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15854 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15855 (apedata & APE_FW_VERSION_BLDMSK));
15858 static void tg3_read_otp_ver(struct tg3 *tp)
15862 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15865 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15866 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15867 TG3_OTP_MAGIC0_VALID(val)) {
15868 u64 val64 = (u64) val << 32 | val2;
15872 for (i = 0; i < 7; i++) {
15873 if ((val64 & 0xff) == 0)
15875 ver = val64 & 0xff;
15878 vlen = strlen(tp->fw_ver);
15879 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15883 static void tg3_read_fw_ver(struct tg3 *tp)
15886 bool vpd_vers = false;
15888 if (tp->fw_ver[0] != 0)
15891 if (tg3_flag(tp, NO_NVRAM)) {
15892 strcat(tp->fw_ver, "sb");
15893 tg3_read_otp_ver(tp);
15897 if (tg3_nvram_read(tp, 0, &val))
15900 if (val == TG3_EEPROM_MAGIC)
15901 tg3_read_bc_ver(tp);
15902 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15903 tg3_read_sb_ver(tp, val);
15904 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15905 tg3_read_hwsb_ver(tp);
15907 if (tg3_flag(tp, ENABLE_ASF)) {
15908 if (tg3_flag(tp, ENABLE_APE)) {
15909 tg3_probe_ncsi(tp);
15911 tg3_read_dash_ver(tp);
15912 } else if (!vpd_vers) {
15913 tg3_read_mgmtfw_ver(tp);
15917 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15920 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15922 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15923 return TG3_RX_RET_MAX_SIZE_5717;
15924 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15925 return TG3_RX_RET_MAX_SIZE_5700;
15927 return TG3_RX_RET_MAX_SIZE_5705;
15930 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15931 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15932 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15933 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15937 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15939 struct pci_dev *peer;
15940 unsigned int func, devnr = tp->pdev->devfn & ~7;
15942 for (func = 0; func < 8; func++) {
15943 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15944 if (peer && peer != tp->pdev)
15948 /* 5704 can be configured in single-port mode, set peer to
15949 * tp->pdev in that case.
15957 * We don't need to keep the refcount elevated; there's no way
15958 * to remove one half of this device without removing the other
15965 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15967 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15968 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15971 /* All devices that use the alternate
15972 * ASIC REV location have a CPMU.
15974 tg3_flag_set(tp, CPMU_PRESENT);
15976 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15977 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15978 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15979 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15980 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15981 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15982 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
15983 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15984 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15985 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15986 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
15987 reg = TG3PCI_GEN2_PRODID_ASICREV;
15988 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15989 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15990 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15991 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15992 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15993 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15994 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15995 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15997 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15998 reg = TG3PCI_GEN15_PRODID_ASICREV;
16000 reg = TG3PCI_PRODID_ASICREV;
16002 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16005 /* Wrong chip ID in 5752 A0. This code can be removed later
16006 * as A0 is not in production.
16008 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16009 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16011 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16012 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16014 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16015 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16016 tg3_asic_rev(tp) == ASIC_REV_5720)
16017 tg3_flag_set(tp, 5717_PLUS);
16019 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16020 tg3_asic_rev(tp) == ASIC_REV_57766)
16021 tg3_flag_set(tp, 57765_CLASS);
16023 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16024 tg3_asic_rev(tp) == ASIC_REV_5762)
16025 tg3_flag_set(tp, 57765_PLUS);
16027 /* Intentionally exclude ASIC_REV_5906 */
16028 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16029 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16030 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16031 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16032 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16033 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16034 tg3_flag(tp, 57765_PLUS))
16035 tg3_flag_set(tp, 5755_PLUS);
16037 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16038 tg3_asic_rev(tp) == ASIC_REV_5714)
16039 tg3_flag_set(tp, 5780_CLASS);
16041 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16042 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16043 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16044 tg3_flag(tp, 5755_PLUS) ||
16045 tg3_flag(tp, 5780_CLASS))
16046 tg3_flag_set(tp, 5750_PLUS);
16048 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16049 tg3_flag(tp, 5750_PLUS))
16050 tg3_flag_set(tp, 5705_PLUS);
16053 static bool tg3_10_100_only_device(struct tg3 *tp,
16054 const struct pci_device_id *ent)
16056 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16058 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16059 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16060 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16063 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16064 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16065 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16075 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16078 u32 pci_state_reg, grc_misc_cfg;
16083 /* Force memory write invalidate off. If we leave it on,
16084 * then on 5700_BX chips we have to enable a workaround.
16085 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16086 * to match the cacheline size. The Broadcom driver have this
16087 * workaround but turns MWI off all the times so never uses
16088 * it. This seems to suggest that the workaround is insufficient.
16090 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16091 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16092 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16094 /* Important! -- Make sure register accesses are byteswapped
16095 * correctly. Also, for those chips that require it, make
16096 * sure that indirect register accesses are enabled before
16097 * the first operation.
16099 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16101 tp->misc_host_ctrl |= (misc_ctrl_reg &
16102 MISC_HOST_CTRL_CHIPREV);
16103 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16104 tp->misc_host_ctrl);
16106 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16108 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16109 * we need to disable memory and use config. cycles
16110 * only to access all registers. The 5702/03 chips
16111 * can mistakenly decode the special cycles from the
16112 * ICH chipsets as memory write cycles, causing corruption
16113 * of register and memory space. Only certain ICH bridges
16114 * will drive special cycles with non-zero data during the
16115 * address phase which can fall within the 5703's address
16116 * range. This is not an ICH bug as the PCI spec allows
16117 * non-zero address during special cycles. However, only
16118 * these ICH bridges are known to drive non-zero addresses
16119 * during special cycles.
16121 * Since special cycles do not cross PCI bridges, we only
16122 * enable this workaround if the 5703 is on the secondary
16123 * bus of these ICH bridges.
16125 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16126 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16127 static struct tg3_dev_id {
16131 } ich_chipsets[] = {
16132 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16134 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16136 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16138 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16142 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16143 struct pci_dev *bridge = NULL;
16145 while (pci_id->vendor != 0) {
16146 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16152 if (pci_id->rev != PCI_ANY_ID) {
16153 if (bridge->revision > pci_id->rev)
16156 if (bridge->subordinate &&
16157 (bridge->subordinate->number ==
16158 tp->pdev->bus->number)) {
16159 tg3_flag_set(tp, ICH_WORKAROUND);
16160 pci_dev_put(bridge);
16166 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16167 static struct tg3_dev_id {
16170 } bridge_chipsets[] = {
16171 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16172 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16175 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16176 struct pci_dev *bridge = NULL;
16178 while (pci_id->vendor != 0) {
16179 bridge = pci_get_device(pci_id->vendor,
16186 if (bridge->subordinate &&
16187 (bridge->subordinate->number <=
16188 tp->pdev->bus->number) &&
16189 (bridge->subordinate->busn_res.end >=
16190 tp->pdev->bus->number)) {
16191 tg3_flag_set(tp, 5701_DMA_BUG);
16192 pci_dev_put(bridge);
16198 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16199 * DMA addresses > 40-bit. This bridge may have other additional
16200 * 57xx devices behind it in some 4-port NIC designs for example.
16201 * Any tg3 device found behind the bridge will also need the 40-bit
16204 if (tg3_flag(tp, 5780_CLASS)) {
16205 tg3_flag_set(tp, 40BIT_DMA_BUG);
16206 tp->msi_cap = tp->pdev->msi_cap;
16208 struct pci_dev *bridge = NULL;
16211 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16212 PCI_DEVICE_ID_SERVERWORKS_EPB,
16214 if (bridge && bridge->subordinate &&
16215 (bridge->subordinate->number <=
16216 tp->pdev->bus->number) &&
16217 (bridge->subordinate->busn_res.end >=
16218 tp->pdev->bus->number)) {
16219 tg3_flag_set(tp, 40BIT_DMA_BUG);
16220 pci_dev_put(bridge);
16226 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16227 tg3_asic_rev(tp) == ASIC_REV_5714)
16228 tp->pdev_peer = tg3_find_peer(tp);
16230 /* Determine TSO capabilities */
16231 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16232 ; /* Do nothing. HW bug. */
16233 else if (tg3_flag(tp, 57765_PLUS))
16234 tg3_flag_set(tp, HW_TSO_3);
16235 else if (tg3_flag(tp, 5755_PLUS) ||
16236 tg3_asic_rev(tp) == ASIC_REV_5906)
16237 tg3_flag_set(tp, HW_TSO_2);
16238 else if (tg3_flag(tp, 5750_PLUS)) {
16239 tg3_flag_set(tp, HW_TSO_1);
16240 tg3_flag_set(tp, TSO_BUG);
16241 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16242 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16243 tg3_flag_clear(tp, TSO_BUG);
16244 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16245 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16246 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16247 tg3_flag_set(tp, FW_TSO);
16248 tg3_flag_set(tp, TSO_BUG);
16249 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16250 tp->fw_needed = FIRMWARE_TG3TSO5;
16252 tp->fw_needed = FIRMWARE_TG3TSO;
16255 /* Selectively allow TSO based on operating conditions */
16256 if (tg3_flag(tp, HW_TSO_1) ||
16257 tg3_flag(tp, HW_TSO_2) ||
16258 tg3_flag(tp, HW_TSO_3) ||
16259 tg3_flag(tp, FW_TSO)) {
16260 /* For firmware TSO, assume ASF is disabled.
16261 * We'll disable TSO later if we discover ASF
16262 * is enabled in tg3_get_eeprom_hw_cfg().
16264 tg3_flag_set(tp, TSO_CAPABLE);
16266 tg3_flag_clear(tp, TSO_CAPABLE);
16267 tg3_flag_clear(tp, TSO_BUG);
16268 tp->fw_needed = NULL;
16271 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16272 tp->fw_needed = FIRMWARE_TG3;
16274 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16275 tp->fw_needed = FIRMWARE_TG357766;
16279 if (tg3_flag(tp, 5750_PLUS)) {
16280 tg3_flag_set(tp, SUPPORT_MSI);
16281 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16282 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16283 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16284 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16285 tp->pdev_peer == tp->pdev))
16286 tg3_flag_clear(tp, SUPPORT_MSI);
16288 if (tg3_flag(tp, 5755_PLUS) ||
16289 tg3_asic_rev(tp) == ASIC_REV_5906) {
16290 tg3_flag_set(tp, 1SHOT_MSI);
16293 if (tg3_flag(tp, 57765_PLUS)) {
16294 tg3_flag_set(tp, SUPPORT_MSIX);
16295 tp->irq_max = TG3_IRQ_MAX_VECS;
16301 if (tp->irq_max > 1) {
16302 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16303 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16305 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16306 tg3_asic_rev(tp) == ASIC_REV_5720)
16307 tp->txq_max = tp->irq_max - 1;
16310 if (tg3_flag(tp, 5755_PLUS) ||
16311 tg3_asic_rev(tp) == ASIC_REV_5906)
16312 tg3_flag_set(tp, SHORT_DMA_BUG);
16314 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16315 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16317 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16318 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16319 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16320 tg3_asic_rev(tp) == ASIC_REV_5762)
16321 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16323 if (tg3_flag(tp, 57765_PLUS) &&
16324 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16325 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16327 if (!tg3_flag(tp, 5705_PLUS) ||
16328 tg3_flag(tp, 5780_CLASS) ||
16329 tg3_flag(tp, USE_JUMBO_BDFLAG))
16330 tg3_flag_set(tp, JUMBO_CAPABLE);
16332 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16335 if (pci_is_pcie(tp->pdev)) {
16338 tg3_flag_set(tp, PCI_EXPRESS);
16340 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16341 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16342 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16343 tg3_flag_clear(tp, HW_TSO_2);
16344 tg3_flag_clear(tp, TSO_CAPABLE);
16346 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16347 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16348 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16349 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16350 tg3_flag_set(tp, CLKREQ_BUG);
16351 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16352 tg3_flag_set(tp, L1PLLPD_EN);
16354 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16355 /* BCM5785 devices are effectively PCIe devices, and should
16356 * follow PCIe codepaths, but do not have a PCIe capabilities
16359 tg3_flag_set(tp, PCI_EXPRESS);
16360 } else if (!tg3_flag(tp, 5705_PLUS) ||
16361 tg3_flag(tp, 5780_CLASS)) {
16362 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16363 if (!tp->pcix_cap) {
16364 dev_err(&tp->pdev->dev,
16365 "Cannot find PCI-X capability, aborting\n");
16369 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16370 tg3_flag_set(tp, PCIX_MODE);
16373 /* If we have an AMD 762 or VIA K8T800 chipset, write
16374 * reordering to the mailbox registers done by the host
16375 * controller can cause major troubles. We read back from
16376 * every mailbox register write to force the writes to be
16377 * posted to the chip in order.
16379 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16380 !tg3_flag(tp, PCI_EXPRESS))
16381 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16383 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16384 &tp->pci_cacheline_sz);
16385 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16386 &tp->pci_lat_timer);
16387 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16388 tp->pci_lat_timer < 64) {
16389 tp->pci_lat_timer = 64;
16390 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16391 tp->pci_lat_timer);
16394 /* Important! -- It is critical that the PCI-X hw workaround
16395 * situation is decided before the first MMIO register access.
16397 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16398 /* 5700 BX chips need to have their TX producer index
16399 * mailboxes written twice to workaround a bug.
16401 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16403 /* If we are in PCI-X mode, enable register write workaround.
16405 * The workaround is to use indirect register accesses
16406 * for all chip writes not to mailbox registers.
16408 if (tg3_flag(tp, PCIX_MODE)) {
16411 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16413 /* The chip can have it's power management PCI config
16414 * space registers clobbered due to this bug.
16415 * So explicitly force the chip into D0 here.
16417 pci_read_config_dword(tp->pdev,
16418 tp->pdev->pm_cap + PCI_PM_CTRL,
16420 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16421 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16422 pci_write_config_dword(tp->pdev,
16423 tp->pdev->pm_cap + PCI_PM_CTRL,
16426 /* Also, force SERR#/PERR# in PCI command. */
16427 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16428 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16429 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16433 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16434 tg3_flag_set(tp, PCI_HIGH_SPEED);
16435 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16436 tg3_flag_set(tp, PCI_32BIT);
16438 /* Chip-specific fixup from Broadcom driver */
16439 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16440 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16441 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16442 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16445 /* Default fast path register access methods */
16446 tp->read32 = tg3_read32;
16447 tp->write32 = tg3_write32;
16448 tp->read32_mbox = tg3_read32;
16449 tp->write32_mbox = tg3_write32;
16450 tp->write32_tx_mbox = tg3_write32;
16451 tp->write32_rx_mbox = tg3_write32;
16453 /* Various workaround register access methods */
16454 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16455 tp->write32 = tg3_write_indirect_reg32;
16456 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16457 (tg3_flag(tp, PCI_EXPRESS) &&
16458 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16460 * Back to back register writes can cause problems on these
16461 * chips, the workaround is to read back all reg writes
16462 * except those to mailbox regs.
16464 * See tg3_write_indirect_reg32().
16466 tp->write32 = tg3_write_flush_reg32;
16469 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16470 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16471 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16472 tp->write32_rx_mbox = tg3_write_flush_reg32;
16475 if (tg3_flag(tp, ICH_WORKAROUND)) {
16476 tp->read32 = tg3_read_indirect_reg32;
16477 tp->write32 = tg3_write_indirect_reg32;
16478 tp->read32_mbox = tg3_read_indirect_mbox;
16479 tp->write32_mbox = tg3_write_indirect_mbox;
16480 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16481 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16486 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16487 pci_cmd &= ~PCI_COMMAND_MEMORY;
16488 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16490 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16491 tp->read32_mbox = tg3_read32_mbox_5906;
16492 tp->write32_mbox = tg3_write32_mbox_5906;
16493 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16494 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16497 if (tp->write32 == tg3_write_indirect_reg32 ||
16498 (tg3_flag(tp, PCIX_MODE) &&
16499 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16500 tg3_asic_rev(tp) == ASIC_REV_5701)))
16501 tg3_flag_set(tp, SRAM_USE_CONFIG);
16503 /* The memory arbiter has to be enabled in order for SRAM accesses
16504 * to succeed. Normally on powerup the tg3 chip firmware will make
16505 * sure it is enabled, but other entities such as system netboot
16506 * code might disable it.
16508 val = tr32(MEMARB_MODE);
16509 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16511 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16512 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16513 tg3_flag(tp, 5780_CLASS)) {
16514 if (tg3_flag(tp, PCIX_MODE)) {
16515 pci_read_config_dword(tp->pdev,
16516 tp->pcix_cap + PCI_X_STATUS,
16518 tp->pci_fn = val & 0x7;
16520 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16521 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16522 tg3_asic_rev(tp) == ASIC_REV_5720) {
16523 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16524 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16525 val = tr32(TG3_CPMU_STATUS);
16527 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16528 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16530 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16531 TG3_CPMU_STATUS_FSHFT_5719;
16534 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16535 tp->write32_tx_mbox = tg3_write_flush_reg32;
16536 tp->write32_rx_mbox = tg3_write_flush_reg32;
16539 /* Get eeprom hw config before calling tg3_set_power_state().
16540 * In particular, the TG3_FLAG_IS_NIC flag must be
16541 * determined before calling tg3_set_power_state() so that
16542 * we know whether or not to switch out of Vaux power.
16543 * When the flag is set, it means that GPIO1 is used for eeprom
16544 * write protect and also implies that it is a LOM where GPIOs
16545 * are not used to switch power.
16547 tg3_get_eeprom_hw_cfg(tp);
16549 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16550 tg3_flag_clear(tp, TSO_CAPABLE);
16551 tg3_flag_clear(tp, TSO_BUG);
16552 tp->fw_needed = NULL;
16555 if (tg3_flag(tp, ENABLE_APE)) {
16556 /* Allow reads and writes to the
16557 * APE register and memory space.
16559 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16560 PCISTATE_ALLOW_APE_SHMEM_WR |
16561 PCISTATE_ALLOW_APE_PSPACE_WR;
16562 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16565 tg3_ape_lock_init(tp);
16568 /* Set up tp->grc_local_ctrl before calling
16569 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16570 * will bring 5700's external PHY out of reset.
16571 * It is also used as eeprom write protect on LOMs.
16573 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16574 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16575 tg3_flag(tp, EEPROM_WRITE_PROT))
16576 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16577 GRC_LCLCTRL_GPIO_OUTPUT1);
16578 /* Unused GPIO3 must be driven as output on 5752 because there
16579 * are no pull-up resistors on unused GPIO pins.
16581 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16582 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16584 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16585 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16586 tg3_flag(tp, 57765_CLASS))
16587 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16589 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16591 /* Turn off the debug UART. */
16592 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16593 if (tg3_flag(tp, IS_NIC))
16594 /* Keep VMain power. */
16595 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16596 GRC_LCLCTRL_GPIO_OUTPUT0;
16599 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16600 tp->grc_local_ctrl |=
16601 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16603 /* Switch out of Vaux if it is a NIC */
16604 tg3_pwrsrc_switch_to_vmain(tp);
16606 /* Derive initial jumbo mode from MTU assigned in
16607 * ether_setup() via the alloc_etherdev() call
16609 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16610 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16612 /* Determine WakeOnLan speed to use. */
16613 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16614 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16615 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16616 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16617 tg3_flag_clear(tp, WOL_SPEED_100MB);
16619 tg3_flag_set(tp, WOL_SPEED_100MB);
16622 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16623 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16625 /* A few boards don't want Ethernet@WireSpeed phy feature */
16626 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16627 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16628 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16629 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16630 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16631 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16632 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16634 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16635 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16636 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16637 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16638 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16640 if (tg3_flag(tp, 5705_PLUS) &&
16641 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16642 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16643 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16644 !tg3_flag(tp, 57765_PLUS)) {
16645 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16646 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16647 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16648 tg3_asic_rev(tp) == ASIC_REV_5761) {
16649 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16650 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16651 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16652 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16653 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16655 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16658 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16659 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16660 tp->phy_otp = tg3_read_otp_phycfg(tp);
16661 if (tp->phy_otp == 0)
16662 tp->phy_otp = TG3_OTP_DEFAULT;
16665 if (tg3_flag(tp, CPMU_PRESENT))
16666 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16668 tp->mi_mode = MAC_MI_MODE_BASE;
16670 tp->coalesce_mode = 0;
16671 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16672 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16673 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16675 /* Set these bits to enable statistics workaround. */
16676 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16677 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16678 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16679 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16680 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16681 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16684 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16685 tg3_asic_rev(tp) == ASIC_REV_57780)
16686 tg3_flag_set(tp, USE_PHYLIB);
16688 err = tg3_mdio_init(tp);
16692 /* Initialize data/descriptor byte/word swapping. */
16693 val = tr32(GRC_MODE);
16694 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16695 tg3_asic_rev(tp) == ASIC_REV_5762)
16696 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16697 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16698 GRC_MODE_B2HRX_ENABLE |
16699 GRC_MODE_HTX2B_ENABLE |
16700 GRC_MODE_HOST_STACKUP);
16702 val &= GRC_MODE_HOST_STACKUP;
16704 tw32(GRC_MODE, val | tp->grc_mode);
16706 tg3_switch_clocks(tp);
16708 /* Clear this out for sanity. */
16709 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16711 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16712 tw32(TG3PCI_REG_BASE_ADDR, 0);
16714 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16716 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16717 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16718 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16719 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16720 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16721 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16722 void __iomem *sram_base;
16724 /* Write some dummy words into the SRAM status block
16725 * area, see if it reads back correctly. If the return
16726 * value is bad, force enable the PCIX workaround.
16728 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16730 writel(0x00000000, sram_base);
16731 writel(0x00000000, sram_base + 4);
16732 writel(0xffffffff, sram_base + 4);
16733 if (readl(sram_base) != 0x00000000)
16734 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16739 tg3_nvram_init(tp);
16741 /* If the device has an NVRAM, no need to load patch firmware */
16742 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16743 !tg3_flag(tp, NO_NVRAM))
16744 tp->fw_needed = NULL;
16746 grc_misc_cfg = tr32(GRC_MISC_CFG);
16747 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16749 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16750 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16751 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16752 tg3_flag_set(tp, IS_5788);
16754 if (!tg3_flag(tp, IS_5788) &&
16755 tg3_asic_rev(tp) != ASIC_REV_5700)
16756 tg3_flag_set(tp, TAGGED_STATUS);
16757 if (tg3_flag(tp, TAGGED_STATUS)) {
16758 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16759 HOSTCC_MODE_CLRTICK_TXBD);
16761 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16762 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16763 tp->misc_host_ctrl);
16766 /* Preserve the APE MAC_MODE bits */
16767 if (tg3_flag(tp, ENABLE_APE))
16768 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16772 if (tg3_10_100_only_device(tp, ent))
16773 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16775 err = tg3_phy_probe(tp);
16777 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16778 /* ... but do not return immediately ... */
16783 tg3_read_fw_ver(tp);
16785 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16786 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16788 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16789 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16791 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16794 /* 5700 {AX,BX} chips have a broken status block link
16795 * change bit implementation, so we must use the
16796 * status register in those cases.
16798 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16799 tg3_flag_set(tp, USE_LINKCHG_REG);
16801 tg3_flag_clear(tp, USE_LINKCHG_REG);
16803 /* The led_ctrl is set during tg3_phy_probe, here we might
16804 * have to force the link status polling mechanism based
16805 * upon subsystem IDs.
16807 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16808 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16809 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16810 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16811 tg3_flag_set(tp, USE_LINKCHG_REG);
16814 /* For all SERDES we poll the MAC status register. */
16815 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16816 tg3_flag_set(tp, POLL_SERDES);
16818 tg3_flag_clear(tp, POLL_SERDES);
16820 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16821 tg3_flag_set(tp, POLL_CPMU_LINK);
16823 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16824 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16825 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16826 tg3_flag(tp, PCIX_MODE)) {
16827 tp->rx_offset = NET_SKB_PAD;
16828 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16829 tp->rx_copy_thresh = ~(u16)0;
16833 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16834 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16835 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16837 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16839 /* Increment the rx prod index on the rx std ring by at most
16840 * 8 for these chips to workaround hw errata.
16842 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16843 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16844 tg3_asic_rev(tp) == ASIC_REV_5755)
16845 tp->rx_std_max_post = 8;
16847 if (tg3_flag(tp, ASPM_WORKAROUND))
16848 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16849 PCIE_PWR_MGMT_L1_THRESH_MSK;
16854 #ifdef CONFIG_SPARC
16855 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16857 struct net_device *dev = tp->dev;
16858 struct pci_dev *pdev = tp->pdev;
16859 struct device_node *dp = pci_device_to_OF_node(pdev);
16860 const unsigned char *addr;
16863 addr = of_get_property(dp, "local-mac-address", &len);
16864 if (addr && len == ETH_ALEN) {
16865 memcpy(dev->dev_addr, addr, ETH_ALEN);
16871 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16873 struct net_device *dev = tp->dev;
16875 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16880 static int tg3_get_device_address(struct tg3 *tp)
16882 struct net_device *dev = tp->dev;
16883 u32 hi, lo, mac_offset;
16887 #ifdef CONFIG_SPARC
16888 if (!tg3_get_macaddr_sparc(tp))
16892 if (tg3_flag(tp, IS_SSB_CORE)) {
16893 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16894 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16899 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16900 tg3_flag(tp, 5780_CLASS)) {
16901 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16903 if (tg3_nvram_lock(tp))
16904 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16906 tg3_nvram_unlock(tp);
16907 } else if (tg3_flag(tp, 5717_PLUS)) {
16908 if (tp->pci_fn & 1)
16910 if (tp->pci_fn > 1)
16911 mac_offset += 0x18c;
16912 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16915 /* First try to get it from MAC address mailbox. */
16916 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16917 if ((hi >> 16) == 0x484b) {
16918 dev->dev_addr[0] = (hi >> 8) & 0xff;
16919 dev->dev_addr[1] = (hi >> 0) & 0xff;
16921 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16922 dev->dev_addr[2] = (lo >> 24) & 0xff;
16923 dev->dev_addr[3] = (lo >> 16) & 0xff;
16924 dev->dev_addr[4] = (lo >> 8) & 0xff;
16925 dev->dev_addr[5] = (lo >> 0) & 0xff;
16927 /* Some old bootcode may report a 0 MAC address in SRAM */
16928 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16931 /* Next, try NVRAM. */
16932 if (!tg3_flag(tp, NO_NVRAM) &&
16933 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16934 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16935 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16936 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16938 /* Finally just fetch it out of the MAC control regs. */
16940 hi = tr32(MAC_ADDR_0_HIGH);
16941 lo = tr32(MAC_ADDR_0_LOW);
16943 dev->dev_addr[5] = lo & 0xff;
16944 dev->dev_addr[4] = (lo >> 8) & 0xff;
16945 dev->dev_addr[3] = (lo >> 16) & 0xff;
16946 dev->dev_addr[2] = (lo >> 24) & 0xff;
16947 dev->dev_addr[1] = hi & 0xff;
16948 dev->dev_addr[0] = (hi >> 8) & 0xff;
16952 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16953 #ifdef CONFIG_SPARC
16954 if (!tg3_get_default_macaddr_sparc(tp))
16962 #define BOUNDARY_SINGLE_CACHELINE 1
16963 #define BOUNDARY_MULTI_CACHELINE 2
16965 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16967 int cacheline_size;
16971 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16973 cacheline_size = 1024;
16975 cacheline_size = (int) byte * 4;
16977 /* On 5703 and later chips, the boundary bits have no
16980 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16981 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16982 !tg3_flag(tp, PCI_EXPRESS))
16985 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16986 goal = BOUNDARY_MULTI_CACHELINE;
16988 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16989 goal = BOUNDARY_SINGLE_CACHELINE;
16995 if (tg3_flag(tp, 57765_PLUS)) {
16996 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17003 /* PCI controllers on most RISC systems tend to disconnect
17004 * when a device tries to burst across a cache-line boundary.
17005 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17007 * Unfortunately, for PCI-E there are only limited
17008 * write-side controls for this, and thus for reads
17009 * we will still get the disconnects. We'll also waste
17010 * these PCI cycles for both read and write for chips
17011 * other than 5700 and 5701 which do not implement the
17014 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17015 switch (cacheline_size) {
17020 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17021 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17022 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17024 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17025 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17030 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17031 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17035 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17036 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17039 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17040 switch (cacheline_size) {
17044 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17045 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17046 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17052 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17053 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17057 switch (cacheline_size) {
17059 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17060 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17061 DMA_RWCTRL_WRITE_BNDRY_16);
17066 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17067 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17068 DMA_RWCTRL_WRITE_BNDRY_32);
17073 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17074 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17075 DMA_RWCTRL_WRITE_BNDRY_64);
17080 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17081 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17082 DMA_RWCTRL_WRITE_BNDRY_128);
17087 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17088 DMA_RWCTRL_WRITE_BNDRY_256);
17091 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17092 DMA_RWCTRL_WRITE_BNDRY_512);
17096 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17097 DMA_RWCTRL_WRITE_BNDRY_1024);
17106 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17107 int size, bool to_device)
17109 struct tg3_internal_buffer_desc test_desc;
17110 u32 sram_dma_descs;
17113 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17115 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17116 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17117 tw32(RDMAC_STATUS, 0);
17118 tw32(WDMAC_STATUS, 0);
17120 tw32(BUFMGR_MODE, 0);
17121 tw32(FTQ_RESET, 0);
17123 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17124 test_desc.addr_lo = buf_dma & 0xffffffff;
17125 test_desc.nic_mbuf = 0x00002100;
17126 test_desc.len = size;
17129 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17130 * the *second* time the tg3 driver was getting loaded after an
17133 * Broadcom tells me:
17134 * ...the DMA engine is connected to the GRC block and a DMA
17135 * reset may affect the GRC block in some unpredictable way...
17136 * The behavior of resets to individual blocks has not been tested.
17138 * Broadcom noted the GRC reset will also reset all sub-components.
17141 test_desc.cqid_sqid = (13 << 8) | 2;
17143 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17146 test_desc.cqid_sqid = (16 << 8) | 7;
17148 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17151 test_desc.flags = 0x00000005;
17153 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17156 val = *(((u32 *)&test_desc) + i);
17157 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17158 sram_dma_descs + (i * sizeof(u32)));
17159 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17161 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17164 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17166 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17169 for (i = 0; i < 40; i++) {
17173 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17175 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17176 if ((val & 0xffff) == sram_dma_descs) {
17187 #define TEST_BUFFER_SIZE 0x2000
17189 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17190 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17194 static int tg3_test_dma(struct tg3 *tp)
17196 dma_addr_t buf_dma;
17197 u32 *buf, saved_dma_rwctrl;
17200 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17201 &buf_dma, GFP_KERNEL);
17207 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17208 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17210 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17212 if (tg3_flag(tp, 57765_PLUS))
17215 if (tg3_flag(tp, PCI_EXPRESS)) {
17216 /* DMA read watermark not used on PCIE */
17217 tp->dma_rwctrl |= 0x00180000;
17218 } else if (!tg3_flag(tp, PCIX_MODE)) {
17219 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17220 tg3_asic_rev(tp) == ASIC_REV_5750)
17221 tp->dma_rwctrl |= 0x003f0000;
17223 tp->dma_rwctrl |= 0x003f000f;
17225 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17226 tg3_asic_rev(tp) == ASIC_REV_5704) {
17227 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17228 u32 read_water = 0x7;
17230 /* If the 5704 is behind the EPB bridge, we can
17231 * do the less restrictive ONE_DMA workaround for
17232 * better performance.
17234 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17235 tg3_asic_rev(tp) == ASIC_REV_5704)
17236 tp->dma_rwctrl |= 0x8000;
17237 else if (ccval == 0x6 || ccval == 0x7)
17238 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17240 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17242 /* Set bit 23 to enable PCIX hw bug fix */
17244 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17245 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17247 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17248 /* 5780 always in PCIX mode */
17249 tp->dma_rwctrl |= 0x00144000;
17250 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17251 /* 5714 always in PCIX mode */
17252 tp->dma_rwctrl |= 0x00148000;
17254 tp->dma_rwctrl |= 0x001b000f;
17257 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17258 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17260 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17261 tg3_asic_rev(tp) == ASIC_REV_5704)
17262 tp->dma_rwctrl &= 0xfffffff0;
17264 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17265 tg3_asic_rev(tp) == ASIC_REV_5701) {
17266 /* Remove this if it causes problems for some boards. */
17267 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17269 /* On 5700/5701 chips, we need to set this bit.
17270 * Otherwise the chip will issue cacheline transactions
17271 * to streamable DMA memory with not all the byte
17272 * enables turned on. This is an error on several
17273 * RISC PCI controllers, in particular sparc64.
17275 * On 5703/5704 chips, this bit has been reassigned
17276 * a different meaning. In particular, it is used
17277 * on those chips to enable a PCI-X workaround.
17279 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17282 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17285 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17286 tg3_asic_rev(tp) != ASIC_REV_5701)
17289 /* It is best to perform DMA test with maximum write burst size
17290 * to expose the 5700/5701 write DMA bug.
17292 saved_dma_rwctrl = tp->dma_rwctrl;
17293 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17294 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17299 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17302 /* Send the buffer to the chip. */
17303 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17305 dev_err(&tp->pdev->dev,
17306 "%s: Buffer write failed. err = %d\n",
17311 /* Now read it back. */
17312 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17314 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17315 "err = %d\n", __func__, ret);
17320 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17324 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17325 DMA_RWCTRL_WRITE_BNDRY_16) {
17326 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17327 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17328 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17331 dev_err(&tp->pdev->dev,
17332 "%s: Buffer corrupted on read back! "
17333 "(%d != %d)\n", __func__, p[i], i);
17339 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17345 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17346 DMA_RWCTRL_WRITE_BNDRY_16) {
17347 /* DMA test passed without adjusting DMA boundary,
17348 * now look for chipsets that are known to expose the
17349 * DMA bug without failing the test.
17351 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17352 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17353 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17355 /* Safe to use the calculated DMA boundary. */
17356 tp->dma_rwctrl = saved_dma_rwctrl;
17359 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17363 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17368 static void tg3_init_bufmgr_config(struct tg3 *tp)
17370 if (tg3_flag(tp, 57765_PLUS)) {
17371 tp->bufmgr_config.mbuf_read_dma_low_water =
17372 DEFAULT_MB_RDMA_LOW_WATER_5705;
17373 tp->bufmgr_config.mbuf_mac_rx_low_water =
17374 DEFAULT_MB_MACRX_LOW_WATER_57765;
17375 tp->bufmgr_config.mbuf_high_water =
17376 DEFAULT_MB_HIGH_WATER_57765;
17378 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17379 DEFAULT_MB_RDMA_LOW_WATER_5705;
17380 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17381 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17382 tp->bufmgr_config.mbuf_high_water_jumbo =
17383 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17384 } else if (tg3_flag(tp, 5705_PLUS)) {
17385 tp->bufmgr_config.mbuf_read_dma_low_water =
17386 DEFAULT_MB_RDMA_LOW_WATER_5705;
17387 tp->bufmgr_config.mbuf_mac_rx_low_water =
17388 DEFAULT_MB_MACRX_LOW_WATER_5705;
17389 tp->bufmgr_config.mbuf_high_water =
17390 DEFAULT_MB_HIGH_WATER_5705;
17391 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17392 tp->bufmgr_config.mbuf_mac_rx_low_water =
17393 DEFAULT_MB_MACRX_LOW_WATER_5906;
17394 tp->bufmgr_config.mbuf_high_water =
17395 DEFAULT_MB_HIGH_WATER_5906;
17398 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17399 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17400 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17401 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17402 tp->bufmgr_config.mbuf_high_water_jumbo =
17403 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17405 tp->bufmgr_config.mbuf_read_dma_low_water =
17406 DEFAULT_MB_RDMA_LOW_WATER;
17407 tp->bufmgr_config.mbuf_mac_rx_low_water =
17408 DEFAULT_MB_MACRX_LOW_WATER;
17409 tp->bufmgr_config.mbuf_high_water =
17410 DEFAULT_MB_HIGH_WATER;
17412 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17413 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17414 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17415 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17416 tp->bufmgr_config.mbuf_high_water_jumbo =
17417 DEFAULT_MB_HIGH_WATER_JUMBO;
17420 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17421 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17424 static char *tg3_phy_string(struct tg3 *tp)
17426 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17427 case TG3_PHY_ID_BCM5400: return "5400";
17428 case TG3_PHY_ID_BCM5401: return "5401";
17429 case TG3_PHY_ID_BCM5411: return "5411";
17430 case TG3_PHY_ID_BCM5701: return "5701";
17431 case TG3_PHY_ID_BCM5703: return "5703";
17432 case TG3_PHY_ID_BCM5704: return "5704";
17433 case TG3_PHY_ID_BCM5705: return "5705";
17434 case TG3_PHY_ID_BCM5750: return "5750";
17435 case TG3_PHY_ID_BCM5752: return "5752";
17436 case TG3_PHY_ID_BCM5714: return "5714";
17437 case TG3_PHY_ID_BCM5780: return "5780";
17438 case TG3_PHY_ID_BCM5755: return "5755";
17439 case TG3_PHY_ID_BCM5787: return "5787";
17440 case TG3_PHY_ID_BCM5784: return "5784";
17441 case TG3_PHY_ID_BCM5756: return "5722/5756";
17442 case TG3_PHY_ID_BCM5906: return "5906";
17443 case TG3_PHY_ID_BCM5761: return "5761";
17444 case TG3_PHY_ID_BCM5718C: return "5718C";
17445 case TG3_PHY_ID_BCM5718S: return "5718S";
17446 case TG3_PHY_ID_BCM57765: return "57765";
17447 case TG3_PHY_ID_BCM5719C: return "5719C";
17448 case TG3_PHY_ID_BCM5720C: return "5720C";
17449 case TG3_PHY_ID_BCM5762: return "5762C";
17450 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17451 case 0: return "serdes";
17452 default: return "unknown";
17456 static char *tg3_bus_string(struct tg3 *tp, char *str)
17458 if (tg3_flag(tp, PCI_EXPRESS)) {
17459 strcpy(str, "PCI Express");
17461 } else if (tg3_flag(tp, PCIX_MODE)) {
17462 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17464 strcpy(str, "PCIX:");
17466 if ((clock_ctrl == 7) ||
17467 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17468 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17469 strcat(str, "133MHz");
17470 else if (clock_ctrl == 0)
17471 strcat(str, "33MHz");
17472 else if (clock_ctrl == 2)
17473 strcat(str, "50MHz");
17474 else if (clock_ctrl == 4)
17475 strcat(str, "66MHz");
17476 else if (clock_ctrl == 6)
17477 strcat(str, "100MHz");
17479 strcpy(str, "PCI:");
17480 if (tg3_flag(tp, PCI_HIGH_SPEED))
17481 strcat(str, "66MHz");
17483 strcat(str, "33MHz");
17485 if (tg3_flag(tp, PCI_32BIT))
17486 strcat(str, ":32-bit");
17488 strcat(str, ":64-bit");
17492 static void tg3_init_coal(struct tg3 *tp)
17494 struct ethtool_coalesce *ec = &tp->coal;
17496 memset(ec, 0, sizeof(*ec));
17497 ec->cmd = ETHTOOL_GCOALESCE;
17498 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17499 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17500 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17501 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17502 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17503 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17504 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17505 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17506 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17508 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17509 HOSTCC_MODE_CLRTICK_TXBD)) {
17510 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17511 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17512 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17513 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17516 if (tg3_flag(tp, 5705_PLUS)) {
17517 ec->rx_coalesce_usecs_irq = 0;
17518 ec->tx_coalesce_usecs_irq = 0;
17519 ec->stats_block_coalesce_usecs = 0;
17523 static int tg3_init_one(struct pci_dev *pdev,
17524 const struct pci_device_id *ent)
17526 struct net_device *dev;
17529 u32 sndmbx, rcvmbx, intmbx;
17531 u64 dma_mask, persist_dma_mask;
17532 netdev_features_t features = 0;
17534 printk_once(KERN_INFO "%s\n", version);
17536 err = pci_enable_device(pdev);
17538 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17542 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17544 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17545 goto err_out_disable_pdev;
17548 pci_set_master(pdev);
17550 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17553 goto err_out_free_res;
17556 SET_NETDEV_DEV(dev, &pdev->dev);
17558 tp = netdev_priv(dev);
17561 tp->rx_mode = TG3_DEF_RX_MODE;
17562 tp->tx_mode = TG3_DEF_TX_MODE;
17566 tp->msg_enable = tg3_debug;
17568 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17570 if (pdev_is_ssb_gige_core(pdev)) {
17571 tg3_flag_set(tp, IS_SSB_CORE);
17572 if (ssb_gige_must_flush_posted_writes(pdev))
17573 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17574 if (ssb_gige_one_dma_at_once(pdev))
17575 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17576 if (ssb_gige_have_roboswitch(pdev)) {
17577 tg3_flag_set(tp, USE_PHYLIB);
17578 tg3_flag_set(tp, ROBOSWITCH);
17580 if (ssb_gige_is_rgmii(pdev))
17581 tg3_flag_set(tp, RGMII_MODE);
17584 /* The word/byte swap controls here control register access byte
17585 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17588 tp->misc_host_ctrl =
17589 MISC_HOST_CTRL_MASK_PCI_INT |
17590 MISC_HOST_CTRL_WORD_SWAP |
17591 MISC_HOST_CTRL_INDIR_ACCESS |
17592 MISC_HOST_CTRL_PCISTATE_RW;
17594 /* The NONFRM (non-frame) byte/word swap controls take effect
17595 * on descriptor entries, anything which isn't packet data.
17597 * The StrongARM chips on the board (one for tx, one for rx)
17598 * are running in big-endian mode.
17600 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17601 GRC_MODE_WSWAP_NONFRM_DATA);
17602 #ifdef __BIG_ENDIAN
17603 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17605 spin_lock_init(&tp->lock);
17606 spin_lock_init(&tp->indirect_lock);
17607 INIT_WORK(&tp->reset_task, tg3_reset_task);
17609 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17611 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17613 goto err_out_free_dev;
17616 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17617 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17618 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17619 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17620 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17621 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17622 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17623 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17624 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17625 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17626 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17627 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17628 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17629 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17630 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17631 tg3_flag_set(tp, ENABLE_APE);
17632 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17633 if (!tp->aperegs) {
17634 dev_err(&pdev->dev,
17635 "Cannot map APE registers, aborting\n");
17637 goto err_out_iounmap;
17641 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17642 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17644 dev->ethtool_ops = &tg3_ethtool_ops;
17645 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17646 dev->netdev_ops = &tg3_netdev_ops;
17647 dev->irq = pdev->irq;
17649 err = tg3_get_invariants(tp, ent);
17651 dev_err(&pdev->dev,
17652 "Problem fetching invariants of chip, aborting\n");
17653 goto err_out_apeunmap;
17656 /* The EPB bridge inside 5714, 5715, and 5780 and any
17657 * device behind the EPB cannot support DMA addresses > 40-bit.
17658 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17659 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17660 * do DMA address check in tg3_start_xmit().
17662 if (tg3_flag(tp, IS_5788))
17663 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17664 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17665 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17666 #ifdef CONFIG_HIGHMEM
17667 dma_mask = DMA_BIT_MASK(64);
17670 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17672 /* Configure DMA attributes. */
17673 if (dma_mask > DMA_BIT_MASK(32)) {
17674 err = pci_set_dma_mask(pdev, dma_mask);
17676 features |= NETIF_F_HIGHDMA;
17677 err = pci_set_consistent_dma_mask(pdev,
17680 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17681 "DMA for consistent allocations\n");
17682 goto err_out_apeunmap;
17686 if (err || dma_mask == DMA_BIT_MASK(32)) {
17687 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17689 dev_err(&pdev->dev,
17690 "No usable DMA configuration, aborting\n");
17691 goto err_out_apeunmap;
17695 tg3_init_bufmgr_config(tp);
17697 /* 5700 B0 chips do not support checksumming correctly due
17698 * to hardware bugs.
17700 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17701 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17703 if (tg3_flag(tp, 5755_PLUS))
17704 features |= NETIF_F_IPV6_CSUM;
17707 /* TSO is on by default on chips that support hardware TSO.
17708 * Firmware TSO on older chips gives lower performance, so it
17709 * is off by default, but can be enabled using ethtool.
17711 if ((tg3_flag(tp, HW_TSO_1) ||
17712 tg3_flag(tp, HW_TSO_2) ||
17713 tg3_flag(tp, HW_TSO_3)) &&
17714 (features & NETIF_F_IP_CSUM))
17715 features |= NETIF_F_TSO;
17716 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17717 if (features & NETIF_F_IPV6_CSUM)
17718 features |= NETIF_F_TSO6;
17719 if (tg3_flag(tp, HW_TSO_3) ||
17720 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17721 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17722 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17723 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17724 tg3_asic_rev(tp) == ASIC_REV_57780)
17725 features |= NETIF_F_TSO_ECN;
17728 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17729 NETIF_F_HW_VLAN_CTAG_RX;
17730 dev->vlan_features |= features;
17733 * Add loopback capability only for a subset of devices that support
17734 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17735 * loopback for the remaining devices.
17737 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17738 !tg3_flag(tp, CPMU_PRESENT))
17739 /* Add the loopback capability */
17740 features |= NETIF_F_LOOPBACK;
17742 dev->hw_features |= features;
17743 dev->priv_flags |= IFF_UNICAST_FLT;
17745 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17746 !tg3_flag(tp, TSO_CAPABLE) &&
17747 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17748 tg3_flag_set(tp, MAX_RXPEND_64);
17749 tp->rx_pending = 63;
17752 err = tg3_get_device_address(tp);
17754 dev_err(&pdev->dev,
17755 "Could not obtain valid ethernet address, aborting\n");
17756 goto err_out_apeunmap;
17760 * Reset chip in case UNDI or EFI driver did not shutdown
17761 * DMA self test will enable WDMAC and we'll see (spurious)
17762 * pending DMA on the PCI bus at that point.
17764 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17765 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17766 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17767 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17770 err = tg3_test_dma(tp);
17772 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17773 goto err_out_apeunmap;
17776 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17777 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17778 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17779 for (i = 0; i < tp->irq_max; i++) {
17780 struct tg3_napi *tnapi = &tp->napi[i];
17783 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17785 tnapi->int_mbox = intmbx;
17791 tnapi->consmbox = rcvmbx;
17792 tnapi->prodmbox = sndmbx;
17795 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17797 tnapi->coal_now = HOSTCC_MODE_NOW;
17799 if (!tg3_flag(tp, SUPPORT_MSIX))
17803 * If we support MSIX, we'll be using RSS. If we're using
17804 * RSS, the first vector only handles link interrupts and the
17805 * remaining vectors handle rx and tx interrupts. Reuse the
17806 * mailbox values for the next iteration. The values we setup
17807 * above are still useful for the single vectored mode.
17822 pci_set_drvdata(pdev, dev);
17824 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17825 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17826 tg3_asic_rev(tp) == ASIC_REV_5762)
17827 tg3_flag_set(tp, PTP_CAPABLE);
17829 tg3_timer_init(tp);
17831 tg3_carrier_off(tp);
17833 err = register_netdev(dev);
17835 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17836 goto err_out_apeunmap;
17839 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17840 tp->board_part_number,
17841 tg3_chip_rev_id(tp),
17842 tg3_bus_string(tp, str),
17845 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17846 struct phy_device *phydev;
17847 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17849 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17850 phydev->drv->name, dev_name(&phydev->dev));
17854 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17855 ethtype = "10/100Base-TX";
17856 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17857 ethtype = "1000Base-SX";
17859 ethtype = "10/100/1000Base-T";
17861 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17862 "(WireSpeed[%d], EEE[%d])\n",
17863 tg3_phy_string(tp), ethtype,
17864 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17865 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17868 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17869 (dev->features & NETIF_F_RXCSUM) != 0,
17870 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17871 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17872 tg3_flag(tp, ENABLE_ASF) != 0,
17873 tg3_flag(tp, TSO_CAPABLE) != 0);
17874 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17876 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17877 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17879 pci_save_state(pdev);
17885 iounmap(tp->aperegs);
17886 tp->aperegs = NULL;
17899 pci_release_regions(pdev);
17901 err_out_disable_pdev:
17902 if (pci_is_enabled(pdev))
17903 pci_disable_device(pdev);
17907 static void tg3_remove_one(struct pci_dev *pdev)
17909 struct net_device *dev = pci_get_drvdata(pdev);
17912 struct tg3 *tp = netdev_priv(dev);
17914 release_firmware(tp->fw);
17916 tg3_reset_task_cancel(tp);
17918 if (tg3_flag(tp, USE_PHYLIB)) {
17923 unregister_netdev(dev);
17925 iounmap(tp->aperegs);
17926 tp->aperegs = NULL;
17933 pci_release_regions(pdev);
17934 pci_disable_device(pdev);
17938 #ifdef CONFIG_PM_SLEEP
17939 static int tg3_suspend(struct device *device)
17941 struct pci_dev *pdev = to_pci_dev(device);
17942 struct net_device *dev = pci_get_drvdata(pdev);
17943 struct tg3 *tp = netdev_priv(dev);
17948 if (!netif_running(dev))
17951 tg3_reset_task_cancel(tp);
17953 tg3_netif_stop(tp);
17955 tg3_timer_stop(tp);
17957 tg3_full_lock(tp, 1);
17958 tg3_disable_ints(tp);
17959 tg3_full_unlock(tp);
17961 netif_device_detach(dev);
17963 tg3_full_lock(tp, 0);
17964 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17965 tg3_flag_clear(tp, INIT_COMPLETE);
17966 tg3_full_unlock(tp);
17968 err = tg3_power_down_prepare(tp);
17972 tg3_full_lock(tp, 0);
17974 tg3_flag_set(tp, INIT_COMPLETE);
17975 err2 = tg3_restart_hw(tp, true);
17979 tg3_timer_start(tp);
17981 netif_device_attach(dev);
17982 tg3_netif_start(tp);
17985 tg3_full_unlock(tp);
17996 static int tg3_resume(struct device *device)
17998 struct pci_dev *pdev = to_pci_dev(device);
17999 struct net_device *dev = pci_get_drvdata(pdev);
18000 struct tg3 *tp = netdev_priv(dev);
18005 if (!netif_running(dev))
18008 netif_device_attach(dev);
18010 tg3_full_lock(tp, 0);
18012 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18014 tg3_flag_set(tp, INIT_COMPLETE);
18015 err = tg3_restart_hw(tp,
18016 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18020 tg3_timer_start(tp);
18022 tg3_netif_start(tp);
18025 tg3_full_unlock(tp);
18034 #endif /* CONFIG_PM_SLEEP */
18036 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18038 static void tg3_shutdown(struct pci_dev *pdev)
18040 struct net_device *dev = pci_get_drvdata(pdev);
18041 struct tg3 *tp = netdev_priv(dev);
18044 netif_device_detach(dev);
18046 if (netif_running(dev))
18049 if (system_state == SYSTEM_POWER_OFF)
18050 tg3_power_down(tp);
18056 * tg3_io_error_detected - called when PCI error is detected
18057 * @pdev: Pointer to PCI device
18058 * @state: The current pci connection state
18060 * This function is called after a PCI bus error affecting
18061 * this device has been detected.
18063 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18064 pci_channel_state_t state)
18066 struct net_device *netdev = pci_get_drvdata(pdev);
18067 struct tg3 *tp = netdev_priv(netdev);
18068 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18070 netdev_info(netdev, "PCI I/O error detected\n");
18074 /* We probably don't have netdev yet */
18075 if (!netdev || !netif_running(netdev))
18080 tg3_netif_stop(tp);
18082 tg3_timer_stop(tp);
18084 /* Want to make sure that the reset task doesn't run */
18085 tg3_reset_task_cancel(tp);
18087 netif_device_detach(netdev);
18089 /* Clean up software state, even if MMIO is blocked */
18090 tg3_full_lock(tp, 0);
18091 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18092 tg3_full_unlock(tp);
18095 if (state == pci_channel_io_perm_failure) {
18097 tg3_napi_enable(tp);
18100 err = PCI_ERS_RESULT_DISCONNECT;
18102 pci_disable_device(pdev);
18111 * tg3_io_slot_reset - called after the pci bus has been reset.
18112 * @pdev: Pointer to PCI device
18114 * Restart the card from scratch, as if from a cold-boot.
18115 * At this point, the card has exprienced a hard reset,
18116 * followed by fixups by BIOS, and has its config space
18117 * set up identically to what it was at cold boot.
18119 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18121 struct net_device *netdev = pci_get_drvdata(pdev);
18122 struct tg3 *tp = netdev_priv(netdev);
18123 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18128 if (pci_enable_device(pdev)) {
18129 dev_err(&pdev->dev,
18130 "Cannot re-enable PCI device after reset.\n");
18134 pci_set_master(pdev);
18135 pci_restore_state(pdev);
18136 pci_save_state(pdev);
18138 if (!netdev || !netif_running(netdev)) {
18139 rc = PCI_ERS_RESULT_RECOVERED;
18143 err = tg3_power_up(tp);
18147 rc = PCI_ERS_RESULT_RECOVERED;
18150 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18151 tg3_napi_enable(tp);
18160 * tg3_io_resume - called when traffic can start flowing again.
18161 * @pdev: Pointer to PCI device
18163 * This callback is called when the error recovery driver tells
18164 * us that its OK to resume normal operation.
18166 static void tg3_io_resume(struct pci_dev *pdev)
18168 struct net_device *netdev = pci_get_drvdata(pdev);
18169 struct tg3 *tp = netdev_priv(netdev);
18174 if (!netif_running(netdev))
18177 tg3_full_lock(tp, 0);
18178 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18179 tg3_flag_set(tp, INIT_COMPLETE);
18180 err = tg3_restart_hw(tp, true);
18182 tg3_full_unlock(tp);
18183 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18187 netif_device_attach(netdev);
18189 tg3_timer_start(tp);
18191 tg3_netif_start(tp);
18193 tg3_full_unlock(tp);
18201 static const struct pci_error_handlers tg3_err_handler = {
18202 .error_detected = tg3_io_error_detected,
18203 .slot_reset = tg3_io_slot_reset,
18204 .resume = tg3_io_resume
18207 static struct pci_driver tg3_driver = {
18208 .name = DRV_MODULE_NAME,
18209 .id_table = tg3_pci_tbl,
18210 .probe = tg3_init_one,
18211 .remove = tg3_remove_one,
18212 .err_handler = &tg3_err_handler,
18213 .driver.pm = &tg3_pm_ops,
18214 .shutdown = tg3_shutdown,
18217 module_pci_driver(tg3_driver);