2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 134
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "Sep 16, 2013"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
212 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
214 #define FIRMWARE_TG3 "tigon/tg3.bin"
215 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
216 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
219 static char version[] =
220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
222 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_MODULE_VERSION);
226 MODULE_FIRMWARE(FIRMWARE_TG3);
227 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
230 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231 module_param(tg3_debug, int, 0);
232 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
234 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
237 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
345 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
346 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
347 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
348 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
351 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
356 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
358 static const struct {
359 const char string[ETH_GSTRING_LEN];
360 } ethtool_stats_keys[] = {
363 { "rx_ucast_packets" },
364 { "rx_mcast_packets" },
365 { "rx_bcast_packets" },
367 { "rx_align_errors" },
368 { "rx_xon_pause_rcvd" },
369 { "rx_xoff_pause_rcvd" },
370 { "rx_mac_ctrl_rcvd" },
371 { "rx_xoff_entered" },
372 { "rx_frame_too_long_errors" },
374 { "rx_undersize_packets" },
375 { "rx_in_length_errors" },
376 { "rx_out_length_errors" },
377 { "rx_64_or_less_octet_packets" },
378 { "rx_65_to_127_octet_packets" },
379 { "rx_128_to_255_octet_packets" },
380 { "rx_256_to_511_octet_packets" },
381 { "rx_512_to_1023_octet_packets" },
382 { "rx_1024_to_1522_octet_packets" },
383 { "rx_1523_to_2047_octet_packets" },
384 { "rx_2048_to_4095_octet_packets" },
385 { "rx_4096_to_8191_octet_packets" },
386 { "rx_8192_to_9022_octet_packets" },
393 { "tx_flow_control" },
395 { "tx_single_collisions" },
396 { "tx_mult_collisions" },
398 { "tx_excessive_collisions" },
399 { "tx_late_collisions" },
400 { "tx_collide_2times" },
401 { "tx_collide_3times" },
402 { "tx_collide_4times" },
403 { "tx_collide_5times" },
404 { "tx_collide_6times" },
405 { "tx_collide_7times" },
406 { "tx_collide_8times" },
407 { "tx_collide_9times" },
408 { "tx_collide_10times" },
409 { "tx_collide_11times" },
410 { "tx_collide_12times" },
411 { "tx_collide_13times" },
412 { "tx_collide_14times" },
413 { "tx_collide_15times" },
414 { "tx_ucast_packets" },
415 { "tx_mcast_packets" },
416 { "tx_bcast_packets" },
417 { "tx_carrier_sense_errors" },
421 { "dma_writeq_full" },
422 { "dma_write_prioq_full" },
426 { "rx_threshold_hit" },
428 { "dma_readq_full" },
429 { "dma_read_prioq_full" },
430 { "tx_comp_queue_full" },
432 { "ring_set_send_prod_index" },
433 { "ring_status_update" },
435 { "nic_avoided_irqs" },
436 { "nic_tx_threshold_hit" },
438 { "mbuf_lwm_thresh_hit" },
441 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
442 #define TG3_NVRAM_TEST 0
443 #define TG3_LINK_TEST 1
444 #define TG3_REGISTER_TEST 2
445 #define TG3_MEMORY_TEST 3
446 #define TG3_MAC_LOOPB_TEST 4
447 #define TG3_PHY_LOOPB_TEST 5
448 #define TG3_EXT_LOOPB_TEST 6
449 #define TG3_INTERRUPT_TEST 7
452 static const struct {
453 const char string[ETH_GSTRING_LEN];
454 } ethtool_test_keys[] = {
455 [TG3_NVRAM_TEST] = { "nvram test (online) " },
456 [TG3_LINK_TEST] = { "link test (online) " },
457 [TG3_REGISTER_TEST] = { "register test (offline)" },
458 [TG3_MEMORY_TEST] = { "memory test (offline)" },
459 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
460 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
461 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
462 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
465 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
468 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
470 writel(val, tp->regs + off);
473 static u32 tg3_read32(struct tg3 *tp, u32 off)
475 return readl(tp->regs + off);
478 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
480 writel(val, tp->aperegs + off);
483 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
485 return readl(tp->aperegs + off);
488 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492 spin_lock_irqsave(&tp->indirect_lock, flags);
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
495 spin_unlock_irqrestore(&tp->indirect_lock, flags);
498 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
500 writel(val, tp->regs + off);
501 readl(tp->regs + off);
504 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
509 spin_lock_irqsave(&tp->indirect_lock, flags);
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
522 TG3_64BIT_REG_LOW, val);
525 if (off == TG3_RX_STD_PROD_IDX_REG) {
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
527 TG3_64BIT_REG_LOW, val);
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
536 /* In indirect mode when disabling interrupts, we also need
537 * to clear the interrupt bit in the GRC local ctrl register.
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
551 spin_lock_irqsave(&tp->indirect_lock, flags);
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 /* usec_wait specifies the wait time in usec when writing to certain registers
559 * where it is unsafe to read back the register without some delay.
560 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
561 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
563 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
566 /* Non-posted methods */
567 tp->write32(tp, off, val);
570 tg3_write32(tp, off, val);
575 /* Wait again after the read for the posted method to guarantee that
576 * the wait time is met.
582 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
584 tp->write32_mbox(tp, off, val);
585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
587 !tg3_flag(tp, ICH_WORKAROUND)))
588 tp->read32_mbox(tp, off);
591 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
593 void __iomem *mbox = tp->regs + off;
595 if (tg3_flag(tp, TXD_MBOX_HWBUG))
597 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
598 tg3_flag(tp, FLUSH_POSTED_WRITES))
602 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
604 return readl(tp->regs + off + GRCMBOX_BASE);
607 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
609 writel(val, tp->regs + off + GRCMBOX_BASE);
612 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
613 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
614 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
618 #define tw32(reg, val) tp->write32(tp, reg, val)
619 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621 #define tr32(reg) tp->read32(tp, reg)
623 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
628 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
631 spin_lock_irqsave(&tp->indirect_lock, flags);
632 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
636 /* Always leave this as zero. */
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
639 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_DATA, val);
642 /* Always leave this as zero. */
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
645 spin_unlock_irqrestore(&tp->indirect_lock, flags);
648 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
653 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
658 spin_lock_irqsave(&tp->indirect_lock, flags);
659 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
663 /* Always leave this as zero. */
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
666 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
667 *val = tr32(TG3PCI_MEM_WIN_DATA);
669 /* Always leave this as zero. */
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
672 spin_unlock_irqrestore(&tp->indirect_lock, flags);
675 static void tg3_ape_lock_init(struct tg3 *tp)
680 if (tg3_asic_rev(tp) == ASIC_REV_5761)
681 regbase = TG3_APE_LOCK_GRANT;
683 regbase = TG3_APE_PER_LOCK_GRANT;
685 /* Make sure the driver hasn't any stale locks. */
686 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
688 case TG3_APE_LOCK_PHY0:
689 case TG3_APE_LOCK_PHY1:
690 case TG3_APE_LOCK_PHY2:
691 case TG3_APE_LOCK_PHY3:
692 bit = APE_LOCK_GRANT_DRIVER;
696 bit = APE_LOCK_GRANT_DRIVER;
698 bit = 1 << tp->pci_fn;
700 tg3_ape_write32(tp, regbase + 4 * i, bit);
705 static int tg3_ape_lock(struct tg3 *tp, int locknum)
709 u32 status, req, gnt, bit;
711 if (!tg3_flag(tp, ENABLE_APE))
715 case TG3_APE_LOCK_GPIO:
716 if (tg3_asic_rev(tp) == ASIC_REV_5761)
718 case TG3_APE_LOCK_GRC:
719 case TG3_APE_LOCK_MEM:
721 bit = APE_LOCK_REQ_DRIVER;
723 bit = 1 << tp->pci_fn;
725 case TG3_APE_LOCK_PHY0:
726 case TG3_APE_LOCK_PHY1:
727 case TG3_APE_LOCK_PHY2:
728 case TG3_APE_LOCK_PHY3:
729 bit = APE_LOCK_REQ_DRIVER;
735 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
736 req = TG3_APE_LOCK_REQ;
737 gnt = TG3_APE_LOCK_GRANT;
739 req = TG3_APE_PER_LOCK_REQ;
740 gnt = TG3_APE_PER_LOCK_GRANT;
745 tg3_ape_write32(tp, req + off, bit);
747 /* Wait for up to 1 millisecond to acquire lock. */
748 for (i = 0; i < 100; i++) {
749 status = tg3_ape_read32(tp, gnt + off);
752 if (pci_channel_offline(tp->pdev))
759 /* Revoke the lock request. */
760 tg3_ape_write32(tp, gnt + off, bit);
767 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771 if (!tg3_flag(tp, ENABLE_APE))
775 case TG3_APE_LOCK_GPIO:
776 if (tg3_asic_rev(tp) == ASIC_REV_5761)
778 case TG3_APE_LOCK_GRC:
779 case TG3_APE_LOCK_MEM:
781 bit = APE_LOCK_GRANT_DRIVER;
783 bit = 1 << tp->pci_fn;
785 case TG3_APE_LOCK_PHY0:
786 case TG3_APE_LOCK_PHY1:
787 case TG3_APE_LOCK_PHY2:
788 case TG3_APE_LOCK_PHY3:
789 bit = APE_LOCK_GRANT_DRIVER;
795 if (tg3_asic_rev(tp) == ASIC_REV_5761)
796 gnt = TG3_APE_LOCK_GRANT;
798 gnt = TG3_APE_PER_LOCK_GRANT;
800 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
803 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
808 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
811 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
812 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
815 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
818 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
821 return timeout_us ? 0 : -EBUSY;
824 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828 for (i = 0; i < timeout_us / 10; i++) {
829 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
831 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
837 return i == timeout_us / 10;
840 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 i, bufoff, msgoff, maxlen, apedata;
846 if (!tg3_flag(tp, APE_HAS_NCSI))
849 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
850 if (apedata != APE_SEG_SIG_MAGIC)
853 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
854 if (!(apedata & APE_FW_STATUS_READY))
857 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
859 msgoff = bufoff + 2 * sizeof(u32);
860 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
865 /* Cap xfer sizes to scratchpad limits. */
866 length = (len > maxlen) ? maxlen : len;
869 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
870 if (!(apedata & APE_FW_STATUS_READY))
873 /* Wait for up to 1 msec for APE to service previous event. */
874 err = tg3_ape_event_lock(tp, 1000);
878 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
879 APE_EVENT_STATUS_SCRTCHPD_READ |
880 APE_EVENT_STATUS_EVENT_PENDING;
881 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
883 tg3_ape_write32(tp, bufoff, base_off);
884 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
886 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
887 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891 if (tg3_ape_wait_for_event(tp, 30000))
894 for (i = 0; length; i += 4, length -= 4) {
895 u32 val = tg3_ape_read32(tp, msgoff + i);
896 memcpy(data, &val, sizeof(u32));
904 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
909 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
910 if (apedata != APE_SEG_SIG_MAGIC)
913 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
914 if (!(apedata & APE_FW_STATUS_READY))
917 /* Wait for up to 1 millisecond for APE to service previous event. */
918 err = tg3_ape_event_lock(tp, 1000);
922 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
923 event | APE_EVENT_STATUS_EVENT_PENDING);
925 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
926 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
931 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
936 if (!tg3_flag(tp, ENABLE_APE))
940 case RESET_KIND_INIT:
941 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
942 APE_HOST_SEG_SIG_MAGIC);
943 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
944 APE_HOST_SEG_LEN_MAGIC);
945 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
946 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
947 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
948 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
949 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
950 APE_HOST_BEHAV_NO_PHYLOCK);
951 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
952 TG3_APE_HOST_DRVR_STATE_START);
954 event = APE_EVENT_STATUS_STATE_START;
956 case RESET_KIND_SHUTDOWN:
957 /* With the interface we are currently using,
958 * APE does not track driver state. Wiping
959 * out the HOST SEGMENT SIGNATURE forces
960 * the APE to assume OS absent status.
962 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
967 TG3_APE_HOST_WOL_SPEED_AUTO);
968 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
970 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
974 event = APE_EVENT_STATUS_STATE_UNLOAD;
980 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
982 tg3_ape_send_event(tp, event);
985 static void tg3_disable_ints(struct tg3 *tp)
989 tw32(TG3PCI_MISC_HOST_CTRL,
990 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
991 for (i = 0; i < tp->irq_max; i++)
992 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
995 static void tg3_enable_ints(struct tg3 *tp)
1002 tw32(TG3PCI_MISC_HOST_CTRL,
1003 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1005 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1006 for (i = 0; i < tp->irq_cnt; i++) {
1007 struct tg3_napi *tnapi = &tp->napi[i];
1009 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1010 if (tg3_flag(tp, 1SHOT_MSI))
1011 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 tp->coal_now |= tnapi->coal_now;
1016 /* Force an initial interrupt */
1017 if (!tg3_flag(tp, TAGGED_STATUS) &&
1018 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1019 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1021 tw32(HOSTCC_MODE, tp->coal_now);
1023 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1026 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1028 struct tg3 *tp = tnapi->tp;
1029 struct tg3_hw_status *sblk = tnapi->hw_status;
1030 unsigned int work_exists = 0;
1032 /* check for phy events */
1033 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1034 if (sblk->status & SD_STATUS_LINK_CHG)
1038 /* check for TX work to do */
1039 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1042 /* check for RX work to do */
1043 if (tnapi->rx_rcb_prod_idx &&
1044 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1051 * similar to tg3_enable_ints, but it accurately determines whether there
1052 * is new work pending and can return without flushing the PIO write
1053 * which reenables interrupts
1055 static void tg3_int_reenable(struct tg3_napi *tnapi)
1057 struct tg3 *tp = tnapi->tp;
1059 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1062 /* When doing tagged status, this work check is unnecessary.
1063 * The last_tag we write above tells the chip which piece of
1064 * work we've completed.
1066 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1067 tw32(HOSTCC_MODE, tp->coalesce_mode |
1068 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1071 static void tg3_switch_clocks(struct tg3 *tp)
1074 u32 orig_clock_ctrl;
1076 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1079 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1081 orig_clock_ctrl = clock_ctrl;
1082 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1083 CLOCK_CTRL_CLKRUN_OENABLE |
1085 tp->pci_clock_ctrl = clock_ctrl;
1087 if (tg3_flag(tp, 5705_PLUS)) {
1088 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1089 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1090 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1092 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1093 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1095 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1097 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1101 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1104 #define PHY_BUSY_LOOPS 5000
1106 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1113 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1115 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 tg3_ape_lock(tp, tp->phy_ape_lock);
1123 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1124 MI_COM_PHY_ADDR_MASK);
1125 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1126 MI_COM_REG_ADDR_MASK);
1127 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1129 tw32_f(MAC_MI_COM, frame_val);
1131 loops = PHY_BUSY_LOOPS;
1132 while (loops != 0) {
1134 frame_val = tr32(MAC_MI_COM);
1136 if ((frame_val & MI_COM_BUSY) == 0) {
1138 frame_val = tr32(MAC_MI_COM);
1146 *val = frame_val & MI_COM_DATA_MASK;
1150 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1151 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 tg3_ape_unlock(tp, tp->phy_ape_lock);
1160 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1162 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1165 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1172 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1173 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1176 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1178 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 tg3_ape_lock(tp, tp->phy_ape_lock);
1184 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1185 MI_COM_PHY_ADDR_MASK);
1186 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1187 MI_COM_REG_ADDR_MASK);
1188 frame_val |= (val & MI_COM_DATA_MASK);
1189 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1191 tw32_f(MAC_MI_COM, frame_val);
1193 loops = PHY_BUSY_LOOPS;
1194 while (loops != 0) {
1196 frame_val = tr32(MAC_MI_COM);
1197 if ((frame_val & MI_COM_BUSY) == 0) {
1199 frame_val = tr32(MAC_MI_COM);
1209 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1210 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 tg3_ape_unlock(tp, tp->phy_ape_lock);
1219 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1221 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1224 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1237 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1247 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1260 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1270 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1276 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1281 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1287 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1292 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1297 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1298 MII_TG3_AUXCTL_SHDWSEL_MISC);
1300 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1305 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1307 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1308 set |= MII_TG3_AUXCTL_MISC_WREN;
1310 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1313 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1318 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1324 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1326 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1329 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1334 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1336 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1337 reg | val | MII_TG3_MISC_SHDW_WREN);
1340 static int tg3_bmcr_reset(struct tg3 *tp)
1345 /* OK, reset it, and poll the BMCR_RESET bit until it
1346 * clears or we time out.
1348 phy_control = BMCR_RESET;
1349 err = tg3_writephy(tp, MII_BMCR, phy_control);
1355 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if ((phy_control & BMCR_RESET) == 0) {
1371 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1373 struct tg3 *tp = bp->priv;
1376 spin_lock_bh(&tp->lock);
1378 if (__tg3_readphy(tp, mii_id, reg, &val))
1381 spin_unlock_bh(&tp->lock);
1386 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1388 struct tg3 *tp = bp->priv;
1391 spin_lock_bh(&tp->lock);
1393 if (__tg3_writephy(tp, mii_id, reg, val))
1396 spin_unlock_bh(&tp->lock);
1401 static int tg3_mdio_reset(struct mii_bus *bp)
1406 static void tg3_mdio_config_5785(struct tg3 *tp)
1409 struct phy_device *phydev;
1411 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1412 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1413 case PHY_ID_BCM50610:
1414 case PHY_ID_BCM50610M:
1415 val = MAC_PHYCFG2_50610_LED_MODES;
1417 case PHY_ID_BCMAC131:
1418 val = MAC_PHYCFG2_AC131_LED_MODES;
1420 case PHY_ID_RTL8211C:
1421 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1423 case PHY_ID_RTL8201E:
1424 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1430 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1431 tw32(MAC_PHYCFG2, val);
1433 val = tr32(MAC_PHYCFG1);
1434 val &= ~(MAC_PHYCFG1_RGMII_INT |
1435 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1436 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1437 tw32(MAC_PHYCFG1, val);
1442 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1443 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1444 MAC_PHYCFG2_FMODE_MASK_MASK |
1445 MAC_PHYCFG2_GMODE_MASK_MASK |
1446 MAC_PHYCFG2_ACT_MASK_MASK |
1447 MAC_PHYCFG2_QUAL_MASK_MASK |
1448 MAC_PHYCFG2_INBAND_ENABLE;
1450 tw32(MAC_PHYCFG2, val);
1452 val = tr32(MAC_PHYCFG1);
1453 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1454 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1455 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1456 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1457 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1458 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1459 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1461 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1462 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1463 tw32(MAC_PHYCFG1, val);
1465 val = tr32(MAC_EXT_RGMII_MODE);
1466 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1467 MAC_RGMII_MODE_RX_QUALITY |
1468 MAC_RGMII_MODE_RX_ACTIVITY |
1469 MAC_RGMII_MODE_RX_ENG_DET |
1470 MAC_RGMII_MODE_TX_ENABLE |
1471 MAC_RGMII_MODE_TX_LOWPWR |
1472 MAC_RGMII_MODE_TX_RESET);
1473 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1474 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1475 val |= MAC_RGMII_MODE_RX_INT_B |
1476 MAC_RGMII_MODE_RX_QUALITY |
1477 MAC_RGMII_MODE_RX_ACTIVITY |
1478 MAC_RGMII_MODE_RX_ENG_DET;
1479 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1480 val |= MAC_RGMII_MODE_TX_ENABLE |
1481 MAC_RGMII_MODE_TX_LOWPWR |
1482 MAC_RGMII_MODE_TX_RESET;
1484 tw32(MAC_EXT_RGMII_MODE, val);
1487 static void tg3_mdio_start(struct tg3 *tp)
1489 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1490 tw32_f(MAC_MI_MODE, tp->mi_mode);
1493 if (tg3_flag(tp, MDIOBUS_INITED) &&
1494 tg3_asic_rev(tp) == ASIC_REV_5785)
1495 tg3_mdio_config_5785(tp);
1498 static int tg3_mdio_init(struct tg3 *tp)
1502 struct phy_device *phydev;
1504 if (tg3_flag(tp, 5717_PLUS)) {
1507 tp->phy_addr = tp->pci_fn + 1;
1509 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1510 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1512 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1513 TG3_CPMU_PHY_STRAP_IS_SERDES;
1516 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1519 addr = ssb_gige_get_phyaddr(tp->pdev);
1522 tp->phy_addr = addr;
1524 tp->phy_addr = TG3_PHY_MII_ADDR;
1528 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1531 tp->mdio_bus = mdiobus_alloc();
1532 if (tp->mdio_bus == NULL)
1535 tp->mdio_bus->name = "tg3 mdio bus";
1536 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1537 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1538 tp->mdio_bus->priv = tp;
1539 tp->mdio_bus->parent = &tp->pdev->dev;
1540 tp->mdio_bus->read = &tg3_mdio_read;
1541 tp->mdio_bus->write = &tg3_mdio_write;
1542 tp->mdio_bus->reset = &tg3_mdio_reset;
1543 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1544 tp->mdio_bus->irq = &tp->mdio_irq[0];
1546 for (i = 0; i < PHY_MAX_ADDR; i++)
1547 tp->mdio_bus->irq[i] = PHY_POLL;
1549 /* The bus registration will look for all the PHYs on the mdio bus.
1550 * Unfortunately, it does not ensure the PHY is powered up before
1551 * accessing the PHY ID registers. A chip reset is the
1552 * quickest way to bring the device back to an operational state..
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1557 i = mdiobus_register(tp->mdio_bus);
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1560 mdiobus_free(tp->mdio_bus);
1564 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1566 if (!phydev || !phydev->drv) {
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1568 mdiobus_unregister(tp->mdio_bus);
1569 mdiobus_free(tp->mdio_bus);
1573 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1574 case PHY_ID_BCM57780:
1575 phydev->interface = PHY_INTERFACE_MODE_GMII;
1576 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1578 case PHY_ID_BCM50610:
1579 case PHY_ID_BCM50610M:
1580 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1581 PHY_BRCM_RX_REFCLK_UNUSED |
1582 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1583 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1584 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1585 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1586 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1587 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1588 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1589 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1591 case PHY_ID_RTL8211C:
1592 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1594 case PHY_ID_RTL8201E:
1595 case PHY_ID_BCMAC131:
1596 phydev->interface = PHY_INTERFACE_MODE_MII;
1597 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1598 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1602 tg3_flag_set(tp, MDIOBUS_INITED);
1604 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1605 tg3_mdio_config_5785(tp);
1610 static void tg3_mdio_fini(struct tg3 *tp)
1612 if (tg3_flag(tp, MDIOBUS_INITED)) {
1613 tg3_flag_clear(tp, MDIOBUS_INITED);
1614 mdiobus_unregister(tp->mdio_bus);
1615 mdiobus_free(tp->mdio_bus);
1619 /* tp->lock is held. */
1620 static inline void tg3_generate_fw_event(struct tg3 *tp)
1624 val = tr32(GRC_RX_CPU_EVENT);
1625 val |= GRC_RX_CPU_DRIVER_EVENT;
1626 tw32_f(GRC_RX_CPU_EVENT, val);
1628 tp->last_event_jiffies = jiffies;
1631 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1633 /* tp->lock is held. */
1634 static void tg3_wait_for_event_ack(struct tg3 *tp)
1637 unsigned int delay_cnt;
1640 /* If enough time has passed, no wait is necessary. */
1641 time_remain = (long)(tp->last_event_jiffies + 1 +
1642 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1644 if (time_remain < 0)
1647 /* Check if we can shorten the wait time. */
1648 delay_cnt = jiffies_to_usecs(time_remain);
1649 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1650 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1651 delay_cnt = (delay_cnt >> 3) + 1;
1653 for (i = 0; i < delay_cnt; i++) {
1654 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1656 if (pci_channel_offline(tp->pdev))
1663 /* tp->lock is held. */
1664 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1669 if (!tg3_readphy(tp, MII_BMCR, ®))
1671 if (!tg3_readphy(tp, MII_BMSR, ®))
1672 val |= (reg & 0xffff);
1676 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1678 if (!tg3_readphy(tp, MII_LPA, ®))
1679 val |= (reg & 0xffff);
1683 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1684 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1686 if (!tg3_readphy(tp, MII_STAT1000, ®))
1687 val |= (reg & 0xffff);
1691 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1698 /* tp->lock is held. */
1699 static void tg3_ump_link_report(struct tg3 *tp)
1703 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1706 tg3_phy_gather_ump_data(tp, data);
1708 tg3_wait_for_event_ack(tp);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1717 tg3_generate_fw_event(tp);
1720 /* tp->lock is held. */
1721 static void tg3_stop_fw(struct tg3 *tp)
1723 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1724 /* Wait for RX cpu to ACK the previous event. */
1725 tg3_wait_for_event_ack(tp);
1727 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1729 tg3_generate_fw_event(tp);
1731 /* Wait for RX cpu to ACK this event. */
1732 tg3_wait_for_event_ack(tp);
1736 /* tp->lock is held. */
1737 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1739 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1740 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1742 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1744 case RESET_KIND_INIT:
1745 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 case RESET_KIND_SHUTDOWN:
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 case RESET_KIND_SUSPEND:
1755 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 /* tp->lock is held. */
1766 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1768 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1770 case RESET_KIND_INIT:
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1772 DRV_STATE_START_DONE);
1775 case RESET_KIND_SHUTDOWN:
1776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1777 DRV_STATE_UNLOAD_DONE);
1786 /* tp->lock is held. */
1787 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1789 if (tg3_flag(tp, ENABLE_ASF)) {
1791 case RESET_KIND_INIT:
1792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 case RESET_KIND_SHUTDOWN:
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1801 case RESET_KIND_SUSPEND:
1802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1812 static int tg3_poll_fw(struct tg3 *tp)
1817 if (tg3_flag(tp, NO_FWARE_REPORTED))
1820 if (tg3_flag(tp, IS_SSB_CORE)) {
1821 /* We don't use firmware. */
1825 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1826 /* Wait up to 20ms for init done. */
1827 for (i = 0; i < 200; i++) {
1828 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1830 if (pci_channel_offline(tp->pdev))
1838 /* Wait for firmware initialization to complete. */
1839 for (i = 0; i < 100000; i++) {
1840 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1841 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1843 if (pci_channel_offline(tp->pdev)) {
1844 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1845 tg3_flag_set(tp, NO_FWARE_REPORTED);
1846 netdev_info(tp->dev, "No firmware running\n");
1855 /* Chip might not be fitted with firmware. Some Sun onboard
1856 * parts are configured like that. So don't signal the timeout
1857 * of the above loop as an error, but do report the lack of
1858 * running firmware once.
1860 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1861 tg3_flag_set(tp, NO_FWARE_REPORTED);
1863 netdev_info(tp->dev, "No firmware running\n");
1866 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1867 /* The 57765 A0 needs a little more
1868 * time to do some important work.
1876 static void tg3_link_report(struct tg3 *tp)
1878 if (!netif_carrier_ok(tp->dev)) {
1879 netif_info(tp, link, tp->dev, "Link is down\n");
1880 tg3_ump_link_report(tp);
1881 } else if (netif_msg_link(tp)) {
1882 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1883 (tp->link_config.active_speed == SPEED_1000 ?
1885 (tp->link_config.active_speed == SPEED_100 ?
1887 (tp->link_config.active_duplex == DUPLEX_FULL ?
1890 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1891 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1893 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1896 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1897 netdev_info(tp->dev, "EEE is %s\n",
1898 tp->setlpicnt ? "enabled" : "disabled");
1900 tg3_ump_link_report(tp);
1903 tp->link_up = netif_carrier_ok(tp->dev);
1906 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1910 if (adv & ADVERTISE_PAUSE_CAP) {
1911 flowctrl |= FLOW_CTRL_RX;
1912 if (!(adv & ADVERTISE_PAUSE_ASYM))
1913 flowctrl |= FLOW_CTRL_TX;
1914 } else if (adv & ADVERTISE_PAUSE_ASYM)
1915 flowctrl |= FLOW_CTRL_TX;
1920 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1924 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1925 miireg = ADVERTISE_1000XPAUSE;
1926 else if (flow_ctrl & FLOW_CTRL_TX)
1927 miireg = ADVERTISE_1000XPSE_ASYM;
1928 else if (flow_ctrl & FLOW_CTRL_RX)
1929 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1936 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1940 if (adv & ADVERTISE_1000XPAUSE) {
1941 flowctrl |= FLOW_CTRL_RX;
1942 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1943 flowctrl |= FLOW_CTRL_TX;
1944 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1945 flowctrl |= FLOW_CTRL_TX;
1950 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1954 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1955 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1956 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1957 if (lcladv & ADVERTISE_1000XPAUSE)
1959 if (rmtadv & ADVERTISE_1000XPAUSE)
1966 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1970 u32 old_rx_mode = tp->rx_mode;
1971 u32 old_tx_mode = tp->tx_mode;
1973 if (tg3_flag(tp, USE_PHYLIB))
1974 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1976 autoneg = tp->link_config.autoneg;
1978 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1979 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1980 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1982 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1984 flowctrl = tp->link_config.flowctrl;
1986 tp->link_config.active_flowctrl = flowctrl;
1988 if (flowctrl & FLOW_CTRL_RX)
1989 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1991 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1993 if (old_rx_mode != tp->rx_mode)
1994 tw32_f(MAC_RX_MODE, tp->rx_mode);
1996 if (flowctrl & FLOW_CTRL_TX)
1997 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1999 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2001 if (old_tx_mode != tp->tx_mode)
2002 tw32_f(MAC_TX_MODE, tp->tx_mode);
2005 static void tg3_adjust_link(struct net_device *dev)
2007 u8 oldflowctrl, linkmesg = 0;
2008 u32 mac_mode, lcl_adv, rmt_adv;
2009 struct tg3 *tp = netdev_priv(dev);
2010 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2012 spin_lock_bh(&tp->lock);
2014 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2015 MAC_MODE_HALF_DUPLEX);
2017 oldflowctrl = tp->link_config.active_flowctrl;
2023 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2024 mac_mode |= MAC_MODE_PORT_MODE_MII;
2025 else if (phydev->speed == SPEED_1000 ||
2026 tg3_asic_rev(tp) != ASIC_REV_5785)
2027 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2029 mac_mode |= MAC_MODE_PORT_MODE_MII;
2031 if (phydev->duplex == DUPLEX_HALF)
2032 mac_mode |= MAC_MODE_HALF_DUPLEX;
2034 lcl_adv = mii_advertise_flowctrl(
2035 tp->link_config.flowctrl);
2038 rmt_adv = LPA_PAUSE_CAP;
2039 if (phydev->asym_pause)
2040 rmt_adv |= LPA_PAUSE_ASYM;
2043 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2045 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2047 if (mac_mode != tp->mac_mode) {
2048 tp->mac_mode = mac_mode;
2049 tw32_f(MAC_MODE, tp->mac_mode);
2053 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2054 if (phydev->speed == SPEED_10)
2056 MAC_MI_STAT_10MBPS_MODE |
2057 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2062 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2063 tw32(MAC_TX_LENGTHS,
2064 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2065 (6 << TX_LENGTHS_IPG_SHIFT) |
2066 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2068 tw32(MAC_TX_LENGTHS,
2069 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2070 (6 << TX_LENGTHS_IPG_SHIFT) |
2071 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2073 if (phydev->link != tp->old_link ||
2074 phydev->speed != tp->link_config.active_speed ||
2075 phydev->duplex != tp->link_config.active_duplex ||
2076 oldflowctrl != tp->link_config.active_flowctrl)
2079 tp->old_link = phydev->link;
2080 tp->link_config.active_speed = phydev->speed;
2081 tp->link_config.active_duplex = phydev->duplex;
2083 spin_unlock_bh(&tp->lock);
2086 tg3_link_report(tp);
2089 static int tg3_phy_init(struct tg3 *tp)
2091 struct phy_device *phydev;
2093 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2096 /* Bring the PHY back to a known state. */
2099 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2101 /* Attach the MAC to the PHY. */
2102 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2103 tg3_adjust_link, phydev->interface);
2104 if (IS_ERR(phydev)) {
2105 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2106 return PTR_ERR(phydev);
2109 /* Mask with MAC supported features. */
2110 switch (phydev->interface) {
2111 case PHY_INTERFACE_MODE_GMII:
2112 case PHY_INTERFACE_MODE_RGMII:
2113 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2114 phydev->supported &= (PHY_GBIT_FEATURES |
2116 SUPPORTED_Asym_Pause);
2120 case PHY_INTERFACE_MODE_MII:
2121 phydev->supported &= (PHY_BASIC_FEATURES |
2123 SUPPORTED_Asym_Pause);
2126 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2130 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2132 phydev->advertising = phydev->supported;
2137 static void tg3_phy_start(struct tg3 *tp)
2139 struct phy_device *phydev;
2141 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2144 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2146 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2147 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2148 phydev->speed = tp->link_config.speed;
2149 phydev->duplex = tp->link_config.duplex;
2150 phydev->autoneg = tp->link_config.autoneg;
2151 phydev->advertising = tp->link_config.advertising;
2156 phy_start_aneg(phydev);
2159 static void tg3_phy_stop(struct tg3 *tp)
2161 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2164 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2167 static void tg3_phy_fini(struct tg3 *tp)
2169 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2170 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2171 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2175 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2180 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2183 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2184 /* Cannot do read-modify-write on 5401 */
2185 err = tg3_phy_auxctl_write(tp,
2186 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2187 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2192 err = tg3_phy_auxctl_read(tp,
2193 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2197 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2198 err = tg3_phy_auxctl_write(tp,
2199 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2205 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2209 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2212 tg3_writephy(tp, MII_TG3_FET_TEST,
2213 phytest | MII_TG3_FET_SHADOW_EN);
2214 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2216 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2218 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2219 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2221 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2225 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2229 if (!tg3_flag(tp, 5705_PLUS) ||
2230 (tg3_flag(tp, 5717_PLUS) &&
2231 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2234 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2235 tg3_phy_fet_toggle_apd(tp, enable);
2239 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2240 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2241 MII_TG3_MISC_SHDW_SCR5_SDTL |
2242 MII_TG3_MISC_SHDW_SCR5_C125OE;
2243 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2244 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2249 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2251 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2253 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2256 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2260 if (!tg3_flag(tp, 5705_PLUS) ||
2261 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2264 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2267 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2268 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2270 tg3_writephy(tp, MII_TG3_FET_TEST,
2271 ephy | MII_TG3_FET_SHADOW_EN);
2272 if (!tg3_readphy(tp, reg, &phy)) {
2274 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2276 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2277 tg3_writephy(tp, reg, phy);
2279 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2284 ret = tg3_phy_auxctl_read(tp,
2285 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2288 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2290 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2291 tg3_phy_auxctl_write(tp,
2292 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2297 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2302 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2305 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2307 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2308 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2311 static void tg3_phy_apply_otp(struct tg3 *tp)
2320 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2323 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2324 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2325 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2327 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2328 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2331 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2332 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2333 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2335 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2338 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2339 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2341 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2342 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2343 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2345 tg3_phy_toggle_auxctl_smdsp(tp, false);
2348 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2351 struct ethtool_eee *dest = &tp->eee;
2353 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2359 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2362 /* Pull eee_active */
2363 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2364 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2365 dest->eee_active = 1;
2367 dest->eee_active = 0;
2369 /* Pull lp advertised settings */
2370 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2372 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2374 /* Pull advertised and eee_enabled settings */
2375 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2377 dest->eee_enabled = !!val;
2378 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2380 /* Pull tx_lpi_enabled */
2381 val = tr32(TG3_CPMU_EEE_MODE);
2382 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2384 /* Pull lpi timer value */
2385 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2388 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2392 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2397 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2399 tp->link_config.active_duplex == DUPLEX_FULL &&
2400 (tp->link_config.active_speed == SPEED_100 ||
2401 tp->link_config.active_speed == SPEED_1000)) {
2404 if (tp->link_config.active_speed == SPEED_1000)
2405 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2407 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2409 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2411 tg3_eee_pull_config(tp, NULL);
2412 if (tp->eee.eee_active)
2416 if (!tp->setlpicnt) {
2417 if (current_link_up &&
2418 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2419 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2420 tg3_phy_toggle_auxctl_smdsp(tp, false);
2423 val = tr32(TG3_CPMU_EEE_MODE);
2424 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2428 static void tg3_phy_eee_enable(struct tg3 *tp)
2432 if (tp->link_config.active_speed == SPEED_1000 &&
2433 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2434 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2435 tg3_flag(tp, 57765_CLASS)) &&
2436 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2437 val = MII_TG3_DSP_TAP26_ALNOKO |
2438 MII_TG3_DSP_TAP26_RMRXSTO;
2439 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2440 tg3_phy_toggle_auxctl_smdsp(tp, false);
2443 val = tr32(TG3_CPMU_EEE_MODE);
2444 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2447 static int tg3_wait_macro_done(struct tg3 *tp)
2454 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2455 if ((tmp32 & 0x1000) == 0)
2465 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2467 static const u32 test_pat[4][6] = {
2468 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2469 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2470 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2471 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2475 for (chan = 0; chan < 4; chan++) {
2478 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 (chan * 0x2000) | 0x0200);
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2482 for (i = 0; i < 6; i++)
2483 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2487 if (tg3_wait_macro_done(tp)) {
2492 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2493 (chan * 0x2000) | 0x0200);
2494 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2495 if (tg3_wait_macro_done(tp)) {
2500 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2501 if (tg3_wait_macro_done(tp)) {
2506 for (i = 0; i < 6; i += 2) {
2509 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2510 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2511 tg3_wait_macro_done(tp)) {
2517 if (low != test_pat[chan][i] ||
2518 high != test_pat[chan][i+1]) {
2519 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2520 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2521 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2531 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2535 for (chan = 0; chan < 4; chan++) {
2538 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2539 (chan * 0x2000) | 0x0200);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2541 for (i = 0; i < 6; i++)
2542 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2543 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2544 if (tg3_wait_macro_done(tp))
2551 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2553 u32 reg32, phy9_orig;
2554 int retries, do_phy_reset, err;
2560 err = tg3_bmcr_reset(tp);
2566 /* Disable transmitter and interrupt. */
2567 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2571 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2573 /* Set full-duplex, 1000 mbps. */
2574 tg3_writephy(tp, MII_BMCR,
2575 BMCR_FULLDPLX | BMCR_SPEED1000);
2577 /* Set to master mode. */
2578 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2581 tg3_writephy(tp, MII_CTRL1000,
2582 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2584 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2588 /* Block the PHY control access. */
2589 tg3_phydsp_write(tp, 0x8005, 0x0800);
2591 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2594 } while (--retries);
2596 err = tg3_phy_reset_chanpat(tp);
2600 tg3_phydsp_write(tp, 0x8005, 0x0000);
2602 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2603 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2605 tg3_phy_toggle_auxctl_smdsp(tp, false);
2607 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2609 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2618 static void tg3_carrier_off(struct tg3 *tp)
2620 netif_carrier_off(tp->dev);
2621 tp->link_up = false;
2624 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2626 if (tg3_flag(tp, ENABLE_ASF))
2627 netdev_warn(tp->dev,
2628 "Management side-band traffic will be interrupted during phy settings change\n");
2631 /* This will reset the tigon3 PHY if there is no valid
2632 * link unless the FORCE argument is non-zero.
2634 static int tg3_phy_reset(struct tg3 *tp)
2639 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2640 val = tr32(GRC_MISC_CFG);
2641 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2644 err = tg3_readphy(tp, MII_BMSR, &val);
2645 err |= tg3_readphy(tp, MII_BMSR, &val);
2649 if (netif_running(tp->dev) && tp->link_up) {
2650 netif_carrier_off(tp->dev);
2651 tg3_link_report(tp);
2654 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2655 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2656 tg3_asic_rev(tp) == ASIC_REV_5705) {
2657 err = tg3_phy_reset_5703_4_5(tp);
2664 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2665 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2666 cpmuctrl = tr32(TG3_CPMU_CTRL);
2667 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2669 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2672 err = tg3_bmcr_reset(tp);
2676 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2677 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2680 tw32(TG3_CPMU_CTRL, cpmuctrl);
2683 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2684 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2685 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2686 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2687 CPMU_LSPD_1000MB_MACCLK_12_5) {
2688 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2690 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2694 if (tg3_flag(tp, 5717_PLUS) &&
2695 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2698 tg3_phy_apply_otp(tp);
2700 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2701 tg3_phy_toggle_apd(tp, true);
2703 tg3_phy_toggle_apd(tp, false);
2706 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2707 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2708 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2709 tg3_phydsp_write(tp, 0x000a, 0x0323);
2710 tg3_phy_toggle_auxctl_smdsp(tp, false);
2713 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2714 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2715 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2718 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2720 tg3_phydsp_write(tp, 0x000a, 0x310b);
2721 tg3_phydsp_write(tp, 0x201f, 0x9506);
2722 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2723 tg3_phy_toggle_auxctl_smdsp(tp, false);
2725 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2726 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2727 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2728 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2730 tg3_writephy(tp, MII_TG3_TEST1,
2731 MII_TG3_TEST1_TRIM_EN | 0x4);
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2735 tg3_phy_toggle_auxctl_smdsp(tp, false);
2739 /* Set Extended packet length bit (bit 14) on all chips that */
2740 /* support jumbo frames */
2741 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2742 /* Cannot do read-modify-write on 5401 */
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2744 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2745 /* Set bit 14 with read-modify-write to preserve other bits */
2746 err = tg3_phy_auxctl_read(tp,
2747 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2749 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2750 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2753 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2754 * jumbo frames transmission.
2756 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2757 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2758 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2759 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2762 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2763 /* adjust output voltage */
2764 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2767 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2768 tg3_phydsp_write(tp, 0xffb, 0x4000);
2770 tg3_phy_toggle_automdix(tp, true);
2771 tg3_phy_set_wirespeed(tp);
2775 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2776 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2777 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2778 TG3_GPIO_MSG_NEED_VAUX)
2779 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2780 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2782 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2783 (TG3_GPIO_MSG_DRVR_PRES << 12))
2785 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2786 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2788 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2789 (TG3_GPIO_MSG_NEED_VAUX << 12))
2791 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2795 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2796 tg3_asic_rev(tp) == ASIC_REV_5719)
2797 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2799 status = tr32(TG3_CPMU_DRV_STATUS);
2801 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2802 status &= ~(TG3_GPIO_MSG_MASK << shift);
2803 status |= (newstat << shift);
2805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2806 tg3_asic_rev(tp) == ASIC_REV_5719)
2807 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2809 tw32(TG3_CPMU_DRV_STATUS, status);
2811 return status >> TG3_APE_GPIO_MSG_SHIFT;
2814 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2816 if (!tg3_flag(tp, IS_NIC))
2819 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2820 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2821 tg3_asic_rev(tp) == ASIC_REV_5720) {
2822 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2825 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2828 TG3_GRC_LCLCTL_PWRSW_DELAY);
2830 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2832 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2833 TG3_GRC_LCLCTL_PWRSW_DELAY);
2839 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2843 if (!tg3_flag(tp, IS_NIC) ||
2844 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2845 tg3_asic_rev(tp) == ASIC_REV_5701)
2848 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2850 tw32_wait_f(GRC_LOCAL_CTRL,
2851 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2852 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2859 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2863 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2865 if (!tg3_flag(tp, IS_NIC))
2868 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2869 tg3_asic_rev(tp) == ASIC_REV_5701) {
2870 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2871 (GRC_LCLCTRL_GPIO_OE0 |
2872 GRC_LCLCTRL_GPIO_OE1 |
2873 GRC_LCLCTRL_GPIO_OE2 |
2874 GRC_LCLCTRL_GPIO_OUTPUT0 |
2875 GRC_LCLCTRL_GPIO_OUTPUT1),
2876 TG3_GRC_LCLCTL_PWRSW_DELAY);
2877 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2878 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2879 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2880 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2881 GRC_LCLCTRL_GPIO_OE1 |
2882 GRC_LCLCTRL_GPIO_OE2 |
2883 GRC_LCLCTRL_GPIO_OUTPUT0 |
2884 GRC_LCLCTRL_GPIO_OUTPUT1 |
2886 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2887 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2893 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2898 u32 grc_local_ctrl = 0;
2900 /* Workaround to prevent overdrawing Amps. */
2901 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2902 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2903 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2905 TG3_GRC_LCLCTL_PWRSW_DELAY);
2908 /* On 5753 and variants, GPIO2 cannot be used. */
2909 no_gpio2 = tp->nic_sram_data_cfg &
2910 NIC_SRAM_DATA_CFG_NO_GPIO2;
2912 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2913 GRC_LCLCTRL_GPIO_OE1 |
2914 GRC_LCLCTRL_GPIO_OE2 |
2915 GRC_LCLCTRL_GPIO_OUTPUT1 |
2916 GRC_LCLCTRL_GPIO_OUTPUT2;
2918 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT2);
2921 tw32_wait_f(GRC_LOCAL_CTRL,
2922 tp->grc_local_ctrl | grc_local_ctrl,
2923 TG3_GRC_LCLCTL_PWRSW_DELAY);
2925 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2927 tw32_wait_f(GRC_LOCAL_CTRL,
2928 tp->grc_local_ctrl | grc_local_ctrl,
2929 TG3_GRC_LCLCTL_PWRSW_DELAY);
2932 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2933 tw32_wait_f(GRC_LOCAL_CTRL,
2934 tp->grc_local_ctrl | grc_local_ctrl,
2935 TG3_GRC_LCLCTL_PWRSW_DELAY);
2940 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2944 /* Serialize power state transitions */
2945 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2948 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2949 msg = TG3_GPIO_MSG_NEED_VAUX;
2951 msg = tg3_set_function_status(tp, msg);
2953 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2956 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2957 tg3_pwrsrc_switch_to_vaux(tp);
2959 tg3_pwrsrc_die_with_vmain(tp);
2962 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2965 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2967 bool need_vaux = false;
2969 /* The GPIOs do something completely different on 57765. */
2970 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2973 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2974 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2975 tg3_asic_rev(tp) == ASIC_REV_5720) {
2976 tg3_frob_aux_power_5717(tp, include_wol ?
2977 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2981 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2982 struct net_device *dev_peer;
2984 dev_peer = pci_get_drvdata(tp->pdev_peer);
2986 /* remove_one() may have been run on the peer. */
2988 struct tg3 *tp_peer = netdev_priv(dev_peer);
2990 if (tg3_flag(tp_peer, INIT_COMPLETE))
2993 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2994 tg3_flag(tp_peer, ENABLE_ASF))
2999 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3000 tg3_flag(tp, ENABLE_ASF))
3004 tg3_pwrsrc_switch_to_vaux(tp);
3006 tg3_pwrsrc_die_with_vmain(tp);
3009 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3011 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3013 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3014 if (speed != SPEED_10)
3016 } else if (speed == SPEED_10)
3022 static bool tg3_phy_power_bug(struct tg3 *tp)
3024 switch (tg3_asic_rev(tp)) {
3029 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3038 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3047 static bool tg3_phy_led_bug(struct tg3 *tp)
3049 switch (tg3_asic_rev(tp)) {
3052 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3061 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3065 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3069 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3070 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3071 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3074 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3075 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3076 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3081 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3083 val = tr32(GRC_MISC_CFG);
3084 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3087 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3089 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3092 tg3_writephy(tp, MII_ADVERTISE, 0);
3093 tg3_writephy(tp, MII_BMCR,
3094 BMCR_ANENABLE | BMCR_ANRESTART);
3096 tg3_writephy(tp, MII_TG3_FET_TEST,
3097 phytest | MII_TG3_FET_SHADOW_EN);
3098 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3099 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3101 MII_TG3_FET_SHDW_AUXMODE4,
3104 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3107 } else if (do_low_power) {
3108 if (!tg3_phy_led_bug(tp))
3109 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3110 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3112 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3113 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3114 MII_TG3_AUXCTL_PCTL_VREG_11V;
3115 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3118 /* The PHY should not be powered down on some chips because
3121 if (tg3_phy_power_bug(tp))
3124 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3125 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3126 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3127 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3128 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3129 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3132 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3135 /* tp->lock is held. */
3136 static int tg3_nvram_lock(struct tg3 *tp)
3138 if (tg3_flag(tp, NVRAM)) {
3141 if (tp->nvram_lock_cnt == 0) {
3142 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3143 for (i = 0; i < 8000; i++) {
3144 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3149 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3153 tp->nvram_lock_cnt++;
3158 /* tp->lock is held. */
3159 static void tg3_nvram_unlock(struct tg3 *tp)
3161 if (tg3_flag(tp, NVRAM)) {
3162 if (tp->nvram_lock_cnt > 0)
3163 tp->nvram_lock_cnt--;
3164 if (tp->nvram_lock_cnt == 0)
3165 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3169 /* tp->lock is held. */
3170 static void tg3_enable_nvram_access(struct tg3 *tp)
3172 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3173 u32 nvaccess = tr32(NVRAM_ACCESS);
3175 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3179 /* tp->lock is held. */
3180 static void tg3_disable_nvram_access(struct tg3 *tp)
3182 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3183 u32 nvaccess = tr32(NVRAM_ACCESS);
3185 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3189 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3190 u32 offset, u32 *val)
3195 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3198 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3199 EEPROM_ADDR_DEVID_MASK |
3201 tw32(GRC_EEPROM_ADDR,
3203 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3204 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3205 EEPROM_ADDR_ADDR_MASK) |
3206 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3208 for (i = 0; i < 1000; i++) {
3209 tmp = tr32(GRC_EEPROM_ADDR);
3211 if (tmp & EEPROM_ADDR_COMPLETE)
3215 if (!(tmp & EEPROM_ADDR_COMPLETE))
3218 tmp = tr32(GRC_EEPROM_DATA);
3221 * The data will always be opposite the native endian
3222 * format. Perform a blind byteswap to compensate.
3229 #define NVRAM_CMD_TIMEOUT 10000
3231 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3235 tw32(NVRAM_CMD, nvram_cmd);
3236 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3238 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3244 if (i == NVRAM_CMD_TIMEOUT)
3250 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3252 if (tg3_flag(tp, NVRAM) &&
3253 tg3_flag(tp, NVRAM_BUFFERED) &&
3254 tg3_flag(tp, FLASH) &&
3255 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3256 (tp->nvram_jedecnum == JEDEC_ATMEL))
3258 addr = ((addr / tp->nvram_pagesize) <<
3259 ATMEL_AT45DB0X1B_PAGE_POS) +
3260 (addr % tp->nvram_pagesize);
3265 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3267 if (tg3_flag(tp, NVRAM) &&
3268 tg3_flag(tp, NVRAM_BUFFERED) &&
3269 tg3_flag(tp, FLASH) &&
3270 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3271 (tp->nvram_jedecnum == JEDEC_ATMEL))
3273 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3274 tp->nvram_pagesize) +
3275 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3280 /* NOTE: Data read in from NVRAM is byteswapped according to
3281 * the byteswapping settings for all other register accesses.
3282 * tg3 devices are BE devices, so on a BE machine, the data
3283 * returned will be exactly as it is seen in NVRAM. On a LE
3284 * machine, the 32-bit value will be byteswapped.
3286 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3290 if (!tg3_flag(tp, NVRAM))
3291 return tg3_nvram_read_using_eeprom(tp, offset, val);
3293 offset = tg3_nvram_phys_addr(tp, offset);
3295 if (offset > NVRAM_ADDR_MSK)
3298 ret = tg3_nvram_lock(tp);
3302 tg3_enable_nvram_access(tp);
3304 tw32(NVRAM_ADDR, offset);
3305 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3306 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3309 *val = tr32(NVRAM_RDDATA);
3311 tg3_disable_nvram_access(tp);
3313 tg3_nvram_unlock(tp);
3318 /* Ensures NVRAM data is in bytestream format. */
3319 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3322 int res = tg3_nvram_read(tp, offset, &v);
3324 *val = cpu_to_be32(v);
3328 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3329 u32 offset, u32 len, u8 *buf)
3334 for (i = 0; i < len; i += 4) {
3340 memcpy(&data, buf + i, 4);
3343 * The SEEPROM interface expects the data to always be opposite
3344 * the native endian format. We accomplish this by reversing
3345 * all the operations that would have been performed on the
3346 * data from a call to tg3_nvram_read_be32().
3348 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3350 val = tr32(GRC_EEPROM_ADDR);
3351 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3353 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3355 tw32(GRC_EEPROM_ADDR, val |
3356 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3357 (addr & EEPROM_ADDR_ADDR_MASK) |
3361 for (j = 0; j < 1000; j++) {
3362 val = tr32(GRC_EEPROM_ADDR);
3364 if (val & EEPROM_ADDR_COMPLETE)
3368 if (!(val & EEPROM_ADDR_COMPLETE)) {
3377 /* offset and length are dword aligned */
3378 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3382 u32 pagesize = tp->nvram_pagesize;
3383 u32 pagemask = pagesize - 1;
3387 tmp = kmalloc(pagesize, GFP_KERNEL);
3393 u32 phy_addr, page_off, size;
3395 phy_addr = offset & ~pagemask;
3397 for (j = 0; j < pagesize; j += 4) {
3398 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3399 (__be32 *) (tmp + j));
3406 page_off = offset & pagemask;
3413 memcpy(tmp + page_off, buf, size);
3415 offset = offset + (pagesize - page_off);
3417 tg3_enable_nvram_access(tp);
3420 * Before we can erase the flash page, we need
3421 * to issue a special "write enable" command.
3423 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3425 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 /* Erase the target page */
3429 tw32(NVRAM_ADDR, phy_addr);
3431 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3432 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3437 /* Issue another write enable to start the write. */
3438 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3440 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3443 for (j = 0; j < pagesize; j += 4) {
3446 data = *((__be32 *) (tmp + j));
3448 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3450 tw32(NVRAM_ADDR, phy_addr + j);
3452 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3456 nvram_cmd |= NVRAM_CMD_FIRST;
3457 else if (j == (pagesize - 4))
3458 nvram_cmd |= NVRAM_CMD_LAST;
3460 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3468 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3469 tg3_nvram_exec_cmd(tp, nvram_cmd);
3476 /* offset and length are dword aligned */
3477 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 for (i = 0; i < len; i += 4, offset += 4) {
3483 u32 page_off, phy_addr, nvram_cmd;
3486 memcpy(&data, buf + i, 4);
3487 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3489 page_off = offset % tp->nvram_pagesize;
3491 phy_addr = tg3_nvram_phys_addr(tp, offset);
3493 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3495 if (page_off == 0 || i == 0)
3496 nvram_cmd |= NVRAM_CMD_FIRST;
3497 if (page_off == (tp->nvram_pagesize - 4))
3498 nvram_cmd |= NVRAM_CMD_LAST;
3501 nvram_cmd |= NVRAM_CMD_LAST;
3503 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3504 !tg3_flag(tp, FLASH) ||
3505 !tg3_flag(tp, 57765_PLUS))
3506 tw32(NVRAM_ADDR, phy_addr);
3508 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3509 !tg3_flag(tp, 5755_PLUS) &&
3510 (tp->nvram_jedecnum == JEDEC_ST) &&
3511 (nvram_cmd & NVRAM_CMD_FIRST)) {
3514 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3515 ret = tg3_nvram_exec_cmd(tp, cmd);
3519 if (!tg3_flag(tp, FLASH)) {
3520 /* We always do complete word writes to eeprom. */
3521 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3524 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3531 /* offset and length are dword aligned */
3532 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3536 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3537 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3538 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3542 if (!tg3_flag(tp, NVRAM)) {
3543 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3547 ret = tg3_nvram_lock(tp);
3551 tg3_enable_nvram_access(tp);
3552 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3553 tw32(NVRAM_WRITE1, 0x406);
3555 grc_mode = tr32(GRC_MODE);
3556 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3558 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3559 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3562 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3566 grc_mode = tr32(GRC_MODE);
3567 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3569 tg3_disable_nvram_access(tp);
3570 tg3_nvram_unlock(tp);
3573 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3574 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3581 #define RX_CPU_SCRATCH_BASE 0x30000
3582 #define RX_CPU_SCRATCH_SIZE 0x04000
3583 #define TX_CPU_SCRATCH_BASE 0x34000
3584 #define TX_CPU_SCRATCH_SIZE 0x04000
3586 /* tp->lock is held. */
3587 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3590 const int iters = 10000;
3592 for (i = 0; i < iters; i++) {
3593 tw32(cpu_base + CPU_STATE, 0xffffffff);
3594 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3595 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3597 if (pci_channel_offline(tp->pdev))
3601 return (i == iters) ? -EBUSY : 0;
3604 /* tp->lock is held. */
3605 static int tg3_rxcpu_pause(struct tg3 *tp)
3607 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3609 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3610 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3616 /* tp->lock is held. */
3617 static int tg3_txcpu_pause(struct tg3 *tp)
3619 return tg3_pause_cpu(tp, TX_CPU_BASE);
3622 /* tp->lock is held. */
3623 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3625 tw32(cpu_base + CPU_STATE, 0xffffffff);
3626 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3629 /* tp->lock is held. */
3630 static void tg3_rxcpu_resume(struct tg3 *tp)
3632 tg3_resume_cpu(tp, RX_CPU_BASE);
3635 /* tp->lock is held. */
3636 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3640 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3642 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3643 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3645 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3648 if (cpu_base == RX_CPU_BASE) {
3649 rc = tg3_rxcpu_pause(tp);
3652 * There is only an Rx CPU for the 5750 derivative in the
3655 if (tg3_flag(tp, IS_SSB_CORE))
3658 rc = tg3_txcpu_pause(tp);
3662 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3663 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3667 /* Clear firmware's nvram arbitration. */
3668 if (tg3_flag(tp, NVRAM))
3669 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3673 static int tg3_fw_data_len(struct tg3 *tp,
3674 const struct tg3_firmware_hdr *fw_hdr)
3678 /* Non fragmented firmware have one firmware header followed by a
3679 * contiguous chunk of data to be written. The length field in that
3680 * header is not the length of data to be written but the complete
3681 * length of the bss. The data length is determined based on
3682 * tp->fw->size minus headers.
3684 * Fragmented firmware have a main header followed by multiple
3685 * fragments. Each fragment is identical to non fragmented firmware
3686 * with a firmware header followed by a contiguous chunk of data. In
3687 * the main header, the length field is unused and set to 0xffffffff.
3688 * In each fragment header the length is the entire size of that
3689 * fragment i.e. fragment data + header length. Data length is
3690 * therefore length field in the header minus TG3_FW_HDR_LEN.
3692 if (tp->fw_len == 0xffffffff)
3693 fw_len = be32_to_cpu(fw_hdr->len);
3695 fw_len = tp->fw->size;
3697 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3700 /* tp->lock is held. */
3701 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3702 u32 cpu_scratch_base, int cpu_scratch_size,
3703 const struct tg3_firmware_hdr *fw_hdr)
3706 void (*write_op)(struct tg3 *, u32, u32);
3707 int total_len = tp->fw->size;
3709 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3711 "%s: Trying to load TX cpu firmware which is 5705\n",
3716 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3717 write_op = tg3_write_mem;
3719 write_op = tg3_write_indirect_reg32;
3721 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3722 /* It is possible that bootcode is still loading at this point.
3723 * Get the nvram lock first before halting the cpu.
3725 int lock_err = tg3_nvram_lock(tp);
3726 err = tg3_halt_cpu(tp, cpu_base);
3728 tg3_nvram_unlock(tp);
3732 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3733 write_op(tp, cpu_scratch_base + i, 0);
3734 tw32(cpu_base + CPU_STATE, 0xffffffff);
3735 tw32(cpu_base + CPU_MODE,
3736 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3738 /* Subtract additional main header for fragmented firmware and
3739 * advance to the first fragment
3741 total_len -= TG3_FW_HDR_LEN;
3746 u32 *fw_data = (u32 *)(fw_hdr + 1);
3747 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3748 write_op(tp, cpu_scratch_base +
3749 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3751 be32_to_cpu(fw_data[i]));
3753 total_len -= be32_to_cpu(fw_hdr->len);
3755 /* Advance to next fragment */
3756 fw_hdr = (struct tg3_firmware_hdr *)
3757 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3758 } while (total_len > 0);
3766 /* tp->lock is held. */
3767 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3770 const int iters = 5;
3772 tw32(cpu_base + CPU_STATE, 0xffffffff);
3773 tw32_f(cpu_base + CPU_PC, pc);
3775 for (i = 0; i < iters; i++) {
3776 if (tr32(cpu_base + CPU_PC) == pc)
3778 tw32(cpu_base + CPU_STATE, 0xffffffff);
3779 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3780 tw32_f(cpu_base + CPU_PC, pc);
3784 return (i == iters) ? -EBUSY : 0;
3787 /* tp->lock is held. */
3788 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3790 const struct tg3_firmware_hdr *fw_hdr;
3793 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3795 /* Firmware blob starts with version numbers, followed by
3796 start address and length. We are setting complete length.
3797 length = end_address_of_bss - start_address_of_text.
3798 Remainder is the blob to be loaded contiguously
3799 from start address. */
3801 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3802 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3807 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3808 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3813 /* Now startup only the RX cpu. */
3814 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3815 be32_to_cpu(fw_hdr->base_addr));
3817 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3818 "should be %08x\n", __func__,
3819 tr32(RX_CPU_BASE + CPU_PC),
3820 be32_to_cpu(fw_hdr->base_addr));
3824 tg3_rxcpu_resume(tp);
3829 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3831 const int iters = 1000;
3835 /* Wait for boot code to complete initialization and enter service
3836 * loop. It is then safe to download service patches
3838 for (i = 0; i < iters; i++) {
3839 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3846 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3850 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3852 netdev_warn(tp->dev,
3853 "Other patches exist. Not downloading EEE patch\n");
3860 /* tp->lock is held. */
3861 static void tg3_load_57766_firmware(struct tg3 *tp)
3863 struct tg3_firmware_hdr *fw_hdr;
3865 if (!tg3_flag(tp, NO_NVRAM))
3868 if (tg3_validate_rxcpu_state(tp))
3874 /* This firmware blob has a different format than older firmware
3875 * releases as given below. The main difference is we have fragmented
3876 * data to be written to non-contiguous locations.
3878 * In the beginning we have a firmware header identical to other
3879 * firmware which consists of version, base addr and length. The length
3880 * here is unused and set to 0xffffffff.
3882 * This is followed by a series of firmware fragments which are
3883 * individually identical to previous firmware. i.e. they have the
3884 * firmware header and followed by data for that fragment. The version
3885 * field of the individual fragment header is unused.
3888 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3889 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3892 if (tg3_rxcpu_pause(tp))
3895 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3896 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3898 tg3_rxcpu_resume(tp);
3901 /* tp->lock is held. */
3902 static int tg3_load_tso_firmware(struct tg3 *tp)
3904 const struct tg3_firmware_hdr *fw_hdr;
3905 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3908 if (!tg3_flag(tp, FW_TSO))
3911 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3913 /* Firmware blob starts with version numbers, followed by
3914 start address and length. We are setting complete length.
3915 length = end_address_of_bss - start_address_of_text.
3916 Remainder is the blob to be loaded contiguously
3917 from start address. */
3919 cpu_scratch_size = tp->fw_len;
3921 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3922 cpu_base = RX_CPU_BASE;
3923 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3925 cpu_base = TX_CPU_BASE;
3926 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3927 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3930 err = tg3_load_firmware_cpu(tp, cpu_base,
3931 cpu_scratch_base, cpu_scratch_size,
3936 /* Now startup the cpu. */
3937 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3938 be32_to_cpu(fw_hdr->base_addr));
3941 "%s fails to set CPU PC, is %08x should be %08x\n",
3942 __func__, tr32(cpu_base + CPU_PC),
3943 be32_to_cpu(fw_hdr->base_addr));
3947 tg3_resume_cpu(tp, cpu_base);
3952 /* tp->lock is held. */
3953 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3955 u32 addr_high, addr_low;
3958 addr_high = ((tp->dev->dev_addr[0] << 8) |
3959 tp->dev->dev_addr[1]);
3960 addr_low = ((tp->dev->dev_addr[2] << 24) |
3961 (tp->dev->dev_addr[3] << 16) |
3962 (tp->dev->dev_addr[4] << 8) |
3963 (tp->dev->dev_addr[5] << 0));
3964 for (i = 0; i < 4; i++) {
3965 if (i == 1 && skip_mac_1)
3967 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3968 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3971 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3972 tg3_asic_rev(tp) == ASIC_REV_5704) {
3973 for (i = 0; i < 12; i++) {
3974 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3975 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3979 addr_high = (tp->dev->dev_addr[0] +
3980 tp->dev->dev_addr[1] +
3981 tp->dev->dev_addr[2] +
3982 tp->dev->dev_addr[3] +
3983 tp->dev->dev_addr[4] +
3984 tp->dev->dev_addr[5]) &
3985 TX_BACKOFF_SEED_MASK;
3986 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3989 static void tg3_enable_register_access(struct tg3 *tp)
3992 * Make sure register accesses (indirect or otherwise) will function
3995 pci_write_config_dword(tp->pdev,
3996 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3999 static int tg3_power_up(struct tg3 *tp)
4003 tg3_enable_register_access(tp);
4005 err = pci_set_power_state(tp->pdev, PCI_D0);
4007 /* Switch out of Vaux if it is a NIC */
4008 tg3_pwrsrc_switch_to_vmain(tp);
4010 netdev_err(tp->dev, "Transition to D0 failed\n");
4016 static int tg3_setup_phy(struct tg3 *, bool);
4018 static int tg3_power_down_prepare(struct tg3 *tp)
4021 bool device_should_wake, do_low_power;
4023 tg3_enable_register_access(tp);
4025 /* Restore the CLKREQ setting. */
4026 if (tg3_flag(tp, CLKREQ_BUG))
4027 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4028 PCI_EXP_LNKCTL_CLKREQ_EN);
4030 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4031 tw32(TG3PCI_MISC_HOST_CTRL,
4032 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4034 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4035 tg3_flag(tp, WOL_ENABLE);
4037 if (tg3_flag(tp, USE_PHYLIB)) {
4038 do_low_power = false;
4039 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4040 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4041 struct phy_device *phydev;
4042 u32 phyid, advertising;
4044 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4046 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4048 tp->link_config.speed = phydev->speed;
4049 tp->link_config.duplex = phydev->duplex;
4050 tp->link_config.autoneg = phydev->autoneg;
4051 tp->link_config.advertising = phydev->advertising;
4053 advertising = ADVERTISED_TP |
4055 ADVERTISED_Autoneg |
4056 ADVERTISED_10baseT_Half;
4058 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4059 if (tg3_flag(tp, WOL_SPEED_100MB))
4061 ADVERTISED_100baseT_Half |
4062 ADVERTISED_100baseT_Full |
4063 ADVERTISED_10baseT_Full;
4065 advertising |= ADVERTISED_10baseT_Full;
4068 phydev->advertising = advertising;
4070 phy_start_aneg(phydev);
4072 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4073 if (phyid != PHY_ID_BCMAC131) {
4074 phyid &= PHY_BCM_OUI_MASK;
4075 if (phyid == PHY_BCM_OUI_1 ||
4076 phyid == PHY_BCM_OUI_2 ||
4077 phyid == PHY_BCM_OUI_3)
4078 do_low_power = true;
4082 do_low_power = true;
4084 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4085 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4087 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4088 tg3_setup_phy(tp, false);
4091 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4094 val = tr32(GRC_VCPU_EXT_CTRL);
4095 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4096 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4100 for (i = 0; i < 200; i++) {
4101 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4102 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4107 if (tg3_flag(tp, WOL_CAP))
4108 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4109 WOL_DRV_STATE_SHUTDOWN |
4113 if (device_should_wake) {
4116 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4118 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4119 tg3_phy_auxctl_write(tp,
4120 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4121 MII_TG3_AUXCTL_PCTL_WOL_EN |
4122 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4123 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4127 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4128 mac_mode = MAC_MODE_PORT_MODE_GMII;
4129 else if (tp->phy_flags &
4130 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4131 if (tp->link_config.active_speed == SPEED_1000)
4132 mac_mode = MAC_MODE_PORT_MODE_GMII;
4134 mac_mode = MAC_MODE_PORT_MODE_MII;
4136 mac_mode = MAC_MODE_PORT_MODE_MII;
4138 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4139 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4140 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4141 SPEED_100 : SPEED_10;
4142 if (tg3_5700_link_polarity(tp, speed))
4143 mac_mode |= MAC_MODE_LINK_POLARITY;
4145 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4148 mac_mode = MAC_MODE_PORT_MODE_TBI;
4151 if (!tg3_flag(tp, 5750_PLUS))
4152 tw32(MAC_LED_CTRL, tp->led_ctrl);
4154 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4155 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4156 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4157 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4159 if (tg3_flag(tp, ENABLE_APE))
4160 mac_mode |= MAC_MODE_APE_TX_EN |
4161 MAC_MODE_APE_RX_EN |
4162 MAC_MODE_TDE_ENABLE;
4164 tw32_f(MAC_MODE, mac_mode);
4167 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4171 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4172 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4173 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4176 base_val = tp->pci_clock_ctrl;
4177 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4178 CLOCK_CTRL_TXCLK_DISABLE);
4180 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4181 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4182 } else if (tg3_flag(tp, 5780_CLASS) ||
4183 tg3_flag(tp, CPMU_PRESENT) ||
4184 tg3_asic_rev(tp) == ASIC_REV_5906) {
4186 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4187 u32 newbits1, newbits2;
4189 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4190 tg3_asic_rev(tp) == ASIC_REV_5701) {
4191 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4192 CLOCK_CTRL_TXCLK_DISABLE |
4194 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4195 } else if (tg3_flag(tp, 5705_PLUS)) {
4196 newbits1 = CLOCK_CTRL_625_CORE;
4197 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4199 newbits1 = CLOCK_CTRL_ALTCLK;
4200 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4203 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4206 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4209 if (!tg3_flag(tp, 5705_PLUS)) {
4212 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4213 tg3_asic_rev(tp) == ASIC_REV_5701) {
4214 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4215 CLOCK_CTRL_TXCLK_DISABLE |
4216 CLOCK_CTRL_44MHZ_CORE);
4218 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4221 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4222 tp->pci_clock_ctrl | newbits3, 40);
4226 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4227 tg3_power_down_phy(tp, do_low_power);
4229 tg3_frob_aux_power(tp, true);
4231 /* Workaround for unstable PLL clock */
4232 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4233 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4234 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4235 u32 val = tr32(0x7d00);
4237 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4239 if (!tg3_flag(tp, ENABLE_ASF)) {
4242 err = tg3_nvram_lock(tp);
4243 tg3_halt_cpu(tp, RX_CPU_BASE);
4245 tg3_nvram_unlock(tp);
4249 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4251 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4256 static void tg3_power_down(struct tg3 *tp)
4258 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4259 pci_set_power_state(tp->pdev, PCI_D3hot);
4262 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4264 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4265 case MII_TG3_AUX_STAT_10HALF:
4267 *duplex = DUPLEX_HALF;
4270 case MII_TG3_AUX_STAT_10FULL:
4272 *duplex = DUPLEX_FULL;
4275 case MII_TG3_AUX_STAT_100HALF:
4277 *duplex = DUPLEX_HALF;
4280 case MII_TG3_AUX_STAT_100FULL:
4282 *duplex = DUPLEX_FULL;
4285 case MII_TG3_AUX_STAT_1000HALF:
4286 *speed = SPEED_1000;
4287 *duplex = DUPLEX_HALF;
4290 case MII_TG3_AUX_STAT_1000FULL:
4291 *speed = SPEED_1000;
4292 *duplex = DUPLEX_FULL;
4296 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4297 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4299 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4303 *speed = SPEED_UNKNOWN;
4304 *duplex = DUPLEX_UNKNOWN;
4309 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4314 new_adv = ADVERTISE_CSMA;
4315 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4316 new_adv |= mii_advertise_flowctrl(flowctrl);
4318 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4322 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4323 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4325 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4326 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4327 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4329 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4334 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4337 tw32(TG3_CPMU_EEE_MODE,
4338 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4340 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4345 /* Advertise 100-BaseTX EEE ability */
4346 if (advertise & ADVERTISED_100baseT_Full)
4347 val |= MDIO_AN_EEE_ADV_100TX;
4348 /* Advertise 1000-BaseT EEE ability */
4349 if (advertise & ADVERTISED_1000baseT_Full)
4350 val |= MDIO_AN_EEE_ADV_1000T;
4352 if (!tp->eee.eee_enabled) {
4354 tp->eee.advertised = 0;
4356 tp->eee.advertised = advertise &
4357 (ADVERTISED_100baseT_Full |
4358 ADVERTISED_1000baseT_Full);
4361 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4365 switch (tg3_asic_rev(tp)) {
4367 case ASIC_REV_57765:
4368 case ASIC_REV_57766:
4370 /* If we advertised any eee advertisements above... */
4372 val = MII_TG3_DSP_TAP26_ALNOKO |
4373 MII_TG3_DSP_TAP26_RMRXSTO |
4374 MII_TG3_DSP_TAP26_OPCSINPT;
4375 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4379 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4380 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4381 MII_TG3_DSP_CH34TP2_HIBW01);
4384 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4393 static void tg3_phy_copper_begin(struct tg3 *tp)
4395 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4396 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4399 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4400 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4401 adv = ADVERTISED_10baseT_Half |
4402 ADVERTISED_10baseT_Full;
4403 if (tg3_flag(tp, WOL_SPEED_100MB))
4404 adv |= ADVERTISED_100baseT_Half |
4405 ADVERTISED_100baseT_Full;
4406 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4407 adv |= ADVERTISED_1000baseT_Half |
4408 ADVERTISED_1000baseT_Full;
4410 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4412 adv = tp->link_config.advertising;
4413 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4414 adv &= ~(ADVERTISED_1000baseT_Half |
4415 ADVERTISED_1000baseT_Full);
4417 fc = tp->link_config.flowctrl;
4420 tg3_phy_autoneg_cfg(tp, adv, fc);
4422 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4423 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4424 /* Normally during power down we want to autonegotiate
4425 * the lowest possible speed for WOL. However, to avoid
4426 * link flap, we leave it untouched.
4431 tg3_writephy(tp, MII_BMCR,
4432 BMCR_ANENABLE | BMCR_ANRESTART);
4435 u32 bmcr, orig_bmcr;
4437 tp->link_config.active_speed = tp->link_config.speed;
4438 tp->link_config.active_duplex = tp->link_config.duplex;
4440 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4441 /* With autoneg disabled, 5715 only links up when the
4442 * advertisement register has the configured speed
4445 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4449 switch (tp->link_config.speed) {
4455 bmcr |= BMCR_SPEED100;
4459 bmcr |= BMCR_SPEED1000;
4463 if (tp->link_config.duplex == DUPLEX_FULL)
4464 bmcr |= BMCR_FULLDPLX;
4466 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4467 (bmcr != orig_bmcr)) {
4468 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4469 for (i = 0; i < 1500; i++) {
4473 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4474 tg3_readphy(tp, MII_BMSR, &tmp))
4476 if (!(tmp & BMSR_LSTATUS)) {
4481 tg3_writephy(tp, MII_BMCR, bmcr);
4487 static int tg3_phy_pull_config(struct tg3 *tp)
4492 err = tg3_readphy(tp, MII_BMCR, &val);
4496 if (!(val & BMCR_ANENABLE)) {
4497 tp->link_config.autoneg = AUTONEG_DISABLE;
4498 tp->link_config.advertising = 0;
4499 tg3_flag_clear(tp, PAUSE_AUTONEG);
4503 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4505 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4508 tp->link_config.speed = SPEED_10;
4511 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4514 tp->link_config.speed = SPEED_100;
4516 case BMCR_SPEED1000:
4517 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4518 tp->link_config.speed = SPEED_1000;
4526 if (val & BMCR_FULLDPLX)
4527 tp->link_config.duplex = DUPLEX_FULL;
4529 tp->link_config.duplex = DUPLEX_HALF;
4531 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4537 tp->link_config.autoneg = AUTONEG_ENABLE;
4538 tp->link_config.advertising = ADVERTISED_Autoneg;
4539 tg3_flag_set(tp, PAUSE_AUTONEG);
4541 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4544 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4548 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4549 tp->link_config.advertising |= adv | ADVERTISED_TP;
4551 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4553 tp->link_config.advertising |= ADVERTISED_FIBRE;
4556 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4559 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4560 err = tg3_readphy(tp, MII_CTRL1000, &val);
4564 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4566 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4570 adv = tg3_decode_flowctrl_1000X(val);
4571 tp->link_config.flowctrl = adv;
4573 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4574 adv = mii_adv_to_ethtool_adv_x(val);
4577 tp->link_config.advertising |= adv;
4584 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4588 /* Turn off tap power management. */
4589 /* Set Extended packet length bit */
4590 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4592 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4593 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4594 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4595 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4596 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4603 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4605 struct ethtool_eee eee;
4607 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4610 tg3_eee_pull_config(tp, &eee);
4612 if (tp->eee.eee_enabled) {
4613 if (tp->eee.advertised != eee.advertised ||
4614 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4615 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4618 /* EEE is disabled but we're advertising */
4626 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4628 u32 advmsk, tgtadv, advertising;
4630 advertising = tp->link_config.advertising;
4631 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4633 advmsk = ADVERTISE_ALL;
4634 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4635 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4636 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4639 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4642 if ((*lcladv & advmsk) != tgtadv)
4645 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4648 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4650 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4654 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4655 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4656 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4657 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4658 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4660 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4663 if (tg3_ctrl != tgtadv)
4670 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4674 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4677 if (tg3_readphy(tp, MII_STAT1000, &val))
4680 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4683 if (tg3_readphy(tp, MII_LPA, rmtadv))
4686 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4687 tp->link_config.rmt_adv = lpeth;
4692 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4694 if (curr_link_up != tp->link_up) {
4696 netif_carrier_on(tp->dev);
4698 netif_carrier_off(tp->dev);
4699 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4700 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4703 tg3_link_report(tp);
4710 static void tg3_clear_mac_status(struct tg3 *tp)
4715 MAC_STATUS_SYNC_CHANGED |
4716 MAC_STATUS_CFG_CHANGED |
4717 MAC_STATUS_MI_COMPLETION |
4718 MAC_STATUS_LNKSTATE_CHANGED);
4722 static void tg3_setup_eee(struct tg3 *tp)
4726 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4727 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4728 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4729 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4731 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4733 tw32_f(TG3_CPMU_EEE_CTRL,
4734 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4736 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4737 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4738 TG3_CPMU_EEEMD_LPI_IN_RX |
4739 TG3_CPMU_EEEMD_EEE_ENABLE;
4741 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4742 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4744 if (tg3_flag(tp, ENABLE_APE))
4745 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4747 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4749 tw32_f(TG3_CPMU_EEE_DBTMR1,
4750 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4751 (tp->eee.tx_lpi_timer & 0xffff));
4753 tw32_f(TG3_CPMU_EEE_DBTMR2,
4754 TG3_CPMU_DBTMR2_APE_TX_2047US |
4755 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4758 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4760 bool current_link_up;
4762 u32 lcl_adv, rmt_adv;
4767 tg3_clear_mac_status(tp);
4769 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4771 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4775 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4777 /* Some third-party PHYs need to be reset on link going
4780 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4781 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4782 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4784 tg3_readphy(tp, MII_BMSR, &bmsr);
4785 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4786 !(bmsr & BMSR_LSTATUS))
4792 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4793 tg3_readphy(tp, MII_BMSR, &bmsr);
4794 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4795 !tg3_flag(tp, INIT_COMPLETE))
4798 if (!(bmsr & BMSR_LSTATUS)) {
4799 err = tg3_init_5401phy_dsp(tp);
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 for (i = 0; i < 1000; i++) {
4806 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4807 (bmsr & BMSR_LSTATUS)) {
4813 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4814 TG3_PHY_REV_BCM5401_B0 &&
4815 !(bmsr & BMSR_LSTATUS) &&
4816 tp->link_config.active_speed == SPEED_1000) {
4817 err = tg3_phy_reset(tp);
4819 err = tg3_init_5401phy_dsp(tp);
4824 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4825 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4826 /* 5701 {A0,B0} CRC bug workaround */
4827 tg3_writephy(tp, 0x15, 0x0a75);
4828 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4829 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4830 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4833 /* Clear pending interrupts... */
4834 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4835 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4837 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4838 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4839 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4840 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4842 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4843 tg3_asic_rev(tp) == ASIC_REV_5701) {
4844 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4845 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4846 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4848 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4851 current_link_up = false;
4852 current_speed = SPEED_UNKNOWN;
4853 current_duplex = DUPLEX_UNKNOWN;
4854 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4855 tp->link_config.rmt_adv = 0;
4857 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4858 err = tg3_phy_auxctl_read(tp,
4859 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4861 if (!err && !(val & (1 << 10))) {
4862 tg3_phy_auxctl_write(tp,
4863 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 for (i = 0; i < 100; i++) {
4871 tg3_readphy(tp, MII_BMSR, &bmsr);
4872 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4873 (bmsr & BMSR_LSTATUS))
4878 if (bmsr & BMSR_LSTATUS) {
4881 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4882 for (i = 0; i < 2000; i++) {
4884 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4889 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4894 for (i = 0; i < 200; i++) {
4895 tg3_readphy(tp, MII_BMCR, &bmcr);
4896 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4898 if (bmcr && bmcr != 0x7fff)
4906 tp->link_config.active_speed = current_speed;
4907 tp->link_config.active_duplex = current_duplex;
4909 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4910 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4912 if ((bmcr & BMCR_ANENABLE) &&
4914 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4915 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4916 current_link_up = true;
4918 /* EEE settings changes take effect only after a phy
4919 * reset. If we have skipped a reset due to Link Flap
4920 * Avoidance being enabled, do it now.
4922 if (!eee_config_ok &&
4923 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4929 if (!(bmcr & BMCR_ANENABLE) &&
4930 tp->link_config.speed == current_speed &&
4931 tp->link_config.duplex == current_duplex) {
4932 current_link_up = true;
4936 if (current_link_up &&
4937 tp->link_config.active_duplex == DUPLEX_FULL) {
4940 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4941 reg = MII_TG3_FET_GEN_STAT;
4942 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4944 reg = MII_TG3_EXT_STAT;
4945 bit = MII_TG3_EXT_STAT_MDIX;
4948 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4949 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4951 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4956 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4957 tg3_phy_copper_begin(tp);
4959 if (tg3_flag(tp, ROBOSWITCH)) {
4960 current_link_up = true;
4961 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4962 current_speed = SPEED_1000;
4963 current_duplex = DUPLEX_FULL;
4964 tp->link_config.active_speed = current_speed;
4965 tp->link_config.active_duplex = current_duplex;
4968 tg3_readphy(tp, MII_BMSR, &bmsr);
4969 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4970 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4971 current_link_up = true;
4974 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4975 if (current_link_up) {
4976 if (tp->link_config.active_speed == SPEED_100 ||
4977 tp->link_config.active_speed == SPEED_10)
4978 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4980 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4981 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4982 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4984 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4986 /* In order for the 5750 core in BCM4785 chip to work properly
4987 * in RGMII mode, the Led Control Register must be set up.
4989 if (tg3_flag(tp, RGMII_MODE)) {
4990 u32 led_ctrl = tr32(MAC_LED_CTRL);
4991 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4993 if (tp->link_config.active_speed == SPEED_10)
4994 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4995 else if (tp->link_config.active_speed == SPEED_100)
4996 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4997 LED_CTRL_100MBPS_ON);
4998 else if (tp->link_config.active_speed == SPEED_1000)
4999 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5000 LED_CTRL_1000MBPS_ON);
5002 tw32(MAC_LED_CTRL, led_ctrl);
5006 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5007 if (tp->link_config.active_duplex == DUPLEX_HALF)
5008 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5010 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5011 if (current_link_up &&
5012 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5013 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5015 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5018 /* ??? Without this setting Netgear GA302T PHY does not
5019 * ??? send/receive packets...
5021 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5022 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5023 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5024 tw32_f(MAC_MI_MODE, tp->mi_mode);
5028 tw32_f(MAC_MODE, tp->mac_mode);
5031 tg3_phy_eee_adjust(tp, current_link_up);
5033 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5034 /* Polled via timer. */
5035 tw32_f(MAC_EVENT, 0);
5037 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5041 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5043 tp->link_config.active_speed == SPEED_1000 &&
5044 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5047 (MAC_STATUS_SYNC_CHANGED |
5048 MAC_STATUS_CFG_CHANGED));
5051 NIC_SRAM_FIRMWARE_MBOX,
5052 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5055 /* Prevent send BD corruption. */
5056 if (tg3_flag(tp, CLKREQ_BUG)) {
5057 if (tp->link_config.active_speed == SPEED_100 ||
5058 tp->link_config.active_speed == SPEED_10)
5059 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5060 PCI_EXP_LNKCTL_CLKREQ_EN);
5062 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5063 PCI_EXP_LNKCTL_CLKREQ_EN);
5066 tg3_test_and_report_link_chg(tp, current_link_up);
5071 struct tg3_fiber_aneginfo {
5073 #define ANEG_STATE_UNKNOWN 0
5074 #define ANEG_STATE_AN_ENABLE 1
5075 #define ANEG_STATE_RESTART_INIT 2
5076 #define ANEG_STATE_RESTART 3
5077 #define ANEG_STATE_DISABLE_LINK_OK 4
5078 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5079 #define ANEG_STATE_ABILITY_DETECT 6
5080 #define ANEG_STATE_ACK_DETECT_INIT 7
5081 #define ANEG_STATE_ACK_DETECT 8
5082 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5083 #define ANEG_STATE_COMPLETE_ACK 10
5084 #define ANEG_STATE_IDLE_DETECT_INIT 11
5085 #define ANEG_STATE_IDLE_DETECT 12
5086 #define ANEG_STATE_LINK_OK 13
5087 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5088 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5091 #define MR_AN_ENABLE 0x00000001
5092 #define MR_RESTART_AN 0x00000002
5093 #define MR_AN_COMPLETE 0x00000004
5094 #define MR_PAGE_RX 0x00000008
5095 #define MR_NP_LOADED 0x00000010
5096 #define MR_TOGGLE_TX 0x00000020
5097 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5098 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5099 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5100 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5101 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5102 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5103 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5104 #define MR_TOGGLE_RX 0x00002000
5105 #define MR_NP_RX 0x00004000
5107 #define MR_LINK_OK 0x80000000
5109 unsigned long link_time, cur_time;
5111 u32 ability_match_cfg;
5112 int ability_match_count;
5114 char ability_match, idle_match, ack_match;
5116 u32 txconfig, rxconfig;
5117 #define ANEG_CFG_NP 0x00000080
5118 #define ANEG_CFG_ACK 0x00000040
5119 #define ANEG_CFG_RF2 0x00000020
5120 #define ANEG_CFG_RF1 0x00000010
5121 #define ANEG_CFG_PS2 0x00000001
5122 #define ANEG_CFG_PS1 0x00008000
5123 #define ANEG_CFG_HD 0x00004000
5124 #define ANEG_CFG_FD 0x00002000
5125 #define ANEG_CFG_INVAL 0x00001f06
5130 #define ANEG_TIMER_ENAB 2
5131 #define ANEG_FAILED -1
5133 #define ANEG_STATE_SETTLE_TIME 10000
5135 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5136 struct tg3_fiber_aneginfo *ap)
5139 unsigned long delta;
5143 if (ap->state == ANEG_STATE_UNKNOWN) {
5147 ap->ability_match_cfg = 0;
5148 ap->ability_match_count = 0;
5149 ap->ability_match = 0;
5155 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5156 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5158 if (rx_cfg_reg != ap->ability_match_cfg) {
5159 ap->ability_match_cfg = rx_cfg_reg;
5160 ap->ability_match = 0;
5161 ap->ability_match_count = 0;
5163 if (++ap->ability_match_count > 1) {
5164 ap->ability_match = 1;
5165 ap->ability_match_cfg = rx_cfg_reg;
5168 if (rx_cfg_reg & ANEG_CFG_ACK)
5176 ap->ability_match_cfg = 0;
5177 ap->ability_match_count = 0;
5178 ap->ability_match = 0;
5184 ap->rxconfig = rx_cfg_reg;
5187 switch (ap->state) {
5188 case ANEG_STATE_UNKNOWN:
5189 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5190 ap->state = ANEG_STATE_AN_ENABLE;
5193 case ANEG_STATE_AN_ENABLE:
5194 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5195 if (ap->flags & MR_AN_ENABLE) {
5198 ap->ability_match_cfg = 0;
5199 ap->ability_match_count = 0;
5200 ap->ability_match = 0;
5204 ap->state = ANEG_STATE_RESTART_INIT;
5206 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5210 case ANEG_STATE_RESTART_INIT:
5211 ap->link_time = ap->cur_time;
5212 ap->flags &= ~(MR_NP_LOADED);
5214 tw32(MAC_TX_AUTO_NEG, 0);
5215 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5216 tw32_f(MAC_MODE, tp->mac_mode);
5219 ret = ANEG_TIMER_ENAB;
5220 ap->state = ANEG_STATE_RESTART;
5223 case ANEG_STATE_RESTART:
5224 delta = ap->cur_time - ap->link_time;
5225 if (delta > ANEG_STATE_SETTLE_TIME)
5226 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5228 ret = ANEG_TIMER_ENAB;
5231 case ANEG_STATE_DISABLE_LINK_OK:
5235 case ANEG_STATE_ABILITY_DETECT_INIT:
5236 ap->flags &= ~(MR_TOGGLE_TX);
5237 ap->txconfig = ANEG_CFG_FD;
5238 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5239 if (flowctrl & ADVERTISE_1000XPAUSE)
5240 ap->txconfig |= ANEG_CFG_PS1;
5241 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5242 ap->txconfig |= ANEG_CFG_PS2;
5243 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5244 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5245 tw32_f(MAC_MODE, tp->mac_mode);
5248 ap->state = ANEG_STATE_ABILITY_DETECT;
5251 case ANEG_STATE_ABILITY_DETECT:
5252 if (ap->ability_match != 0 && ap->rxconfig != 0)
5253 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5256 case ANEG_STATE_ACK_DETECT_INIT:
5257 ap->txconfig |= ANEG_CFG_ACK;
5258 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5259 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5260 tw32_f(MAC_MODE, tp->mac_mode);
5263 ap->state = ANEG_STATE_ACK_DETECT;
5266 case ANEG_STATE_ACK_DETECT:
5267 if (ap->ack_match != 0) {
5268 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5269 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5270 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5272 ap->state = ANEG_STATE_AN_ENABLE;
5274 } else if (ap->ability_match != 0 &&
5275 ap->rxconfig == 0) {
5276 ap->state = ANEG_STATE_AN_ENABLE;
5280 case ANEG_STATE_COMPLETE_ACK_INIT:
5281 if (ap->rxconfig & ANEG_CFG_INVAL) {
5285 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5286 MR_LP_ADV_HALF_DUPLEX |
5287 MR_LP_ADV_SYM_PAUSE |
5288 MR_LP_ADV_ASYM_PAUSE |
5289 MR_LP_ADV_REMOTE_FAULT1 |
5290 MR_LP_ADV_REMOTE_FAULT2 |
5291 MR_LP_ADV_NEXT_PAGE |
5294 if (ap->rxconfig & ANEG_CFG_FD)
5295 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5296 if (ap->rxconfig & ANEG_CFG_HD)
5297 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5298 if (ap->rxconfig & ANEG_CFG_PS1)
5299 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5300 if (ap->rxconfig & ANEG_CFG_PS2)
5301 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5302 if (ap->rxconfig & ANEG_CFG_RF1)
5303 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5304 if (ap->rxconfig & ANEG_CFG_RF2)
5305 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5306 if (ap->rxconfig & ANEG_CFG_NP)
5307 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5309 ap->link_time = ap->cur_time;
5311 ap->flags ^= (MR_TOGGLE_TX);
5312 if (ap->rxconfig & 0x0008)
5313 ap->flags |= MR_TOGGLE_RX;
5314 if (ap->rxconfig & ANEG_CFG_NP)
5315 ap->flags |= MR_NP_RX;
5316 ap->flags |= MR_PAGE_RX;
5318 ap->state = ANEG_STATE_COMPLETE_ACK;
5319 ret = ANEG_TIMER_ENAB;
5322 case ANEG_STATE_COMPLETE_ACK:
5323 if (ap->ability_match != 0 &&
5324 ap->rxconfig == 0) {
5325 ap->state = ANEG_STATE_AN_ENABLE;
5328 delta = ap->cur_time - ap->link_time;
5329 if (delta > ANEG_STATE_SETTLE_TIME) {
5330 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5331 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5333 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5334 !(ap->flags & MR_NP_RX)) {
5335 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 case ANEG_STATE_IDLE_DETECT_INIT:
5344 ap->link_time = ap->cur_time;
5345 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5346 tw32_f(MAC_MODE, tp->mac_mode);
5349 ap->state = ANEG_STATE_IDLE_DETECT;
5350 ret = ANEG_TIMER_ENAB;
5353 case ANEG_STATE_IDLE_DETECT:
5354 if (ap->ability_match != 0 &&
5355 ap->rxconfig == 0) {
5356 ap->state = ANEG_STATE_AN_ENABLE;
5359 delta = ap->cur_time - ap->link_time;
5360 if (delta > ANEG_STATE_SETTLE_TIME) {
5361 /* XXX another gem from the Broadcom driver :( */
5362 ap->state = ANEG_STATE_LINK_OK;
5366 case ANEG_STATE_LINK_OK:
5367 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5371 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5372 /* ??? unimplemented */
5375 case ANEG_STATE_NEXT_PAGE_WAIT:
5376 /* ??? unimplemented */
5387 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5390 struct tg3_fiber_aneginfo aninfo;
5391 int status = ANEG_FAILED;
5395 tw32_f(MAC_TX_AUTO_NEG, 0);
5397 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5398 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5401 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5404 memset(&aninfo, 0, sizeof(aninfo));
5405 aninfo.flags |= MR_AN_ENABLE;
5406 aninfo.state = ANEG_STATE_UNKNOWN;
5407 aninfo.cur_time = 0;
5409 while (++tick < 195000) {
5410 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5411 if (status == ANEG_DONE || status == ANEG_FAILED)
5417 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5418 tw32_f(MAC_MODE, tp->mac_mode);
5421 *txflags = aninfo.txconfig;
5422 *rxflags = aninfo.flags;
5424 if (status == ANEG_DONE &&
5425 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5426 MR_LP_ADV_FULL_DUPLEX)))
5432 static void tg3_init_bcm8002(struct tg3 *tp)
5434 u32 mac_status = tr32(MAC_STATUS);
5437 /* Reset when initting first time or we have a link. */
5438 if (tg3_flag(tp, INIT_COMPLETE) &&
5439 !(mac_status & MAC_STATUS_PCS_SYNCED))
5442 /* Set PLL lock range. */
5443 tg3_writephy(tp, 0x16, 0x8007);
5446 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5448 /* Wait for reset to complete. */
5449 /* XXX schedule_timeout() ... */
5450 for (i = 0; i < 500; i++)
5453 /* Config mode; select PMA/Ch 1 regs. */
5454 tg3_writephy(tp, 0x10, 0x8411);
5456 /* Enable auto-lock and comdet, select txclk for tx. */
5457 tg3_writephy(tp, 0x11, 0x0a10);
5459 tg3_writephy(tp, 0x18, 0x00a0);
5460 tg3_writephy(tp, 0x16, 0x41ff);
5462 /* Assert and deassert POR. */
5463 tg3_writephy(tp, 0x13, 0x0400);
5465 tg3_writephy(tp, 0x13, 0x0000);
5467 tg3_writephy(tp, 0x11, 0x0a50);
5469 tg3_writephy(tp, 0x11, 0x0a10);
5471 /* Wait for signal to stabilize */
5472 /* XXX schedule_timeout() ... */
5473 for (i = 0; i < 15000; i++)
5476 /* Deselect the channel register so we can read the PHYID
5479 tg3_writephy(tp, 0x10, 0x8011);
5482 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5485 bool current_link_up;
5486 u32 sg_dig_ctrl, sg_dig_status;
5487 u32 serdes_cfg, expected_sg_dig_ctrl;
5488 int workaround, port_a;
5491 expected_sg_dig_ctrl = 0;
5494 current_link_up = false;
5496 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5497 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5499 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5502 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5503 /* preserve bits 20-23 for voltage regulator */
5504 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5507 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5509 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5510 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5512 u32 val = serdes_cfg;
5518 tw32_f(MAC_SERDES_CFG, val);
5521 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5523 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5524 tg3_setup_flow_control(tp, 0, 0);
5525 current_link_up = true;
5530 /* Want auto-negotiation. */
5531 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5533 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5534 if (flowctrl & ADVERTISE_1000XPAUSE)
5535 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5536 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5537 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5539 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5540 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5541 tp->serdes_counter &&
5542 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5543 MAC_STATUS_RCVD_CFG)) ==
5544 MAC_STATUS_PCS_SYNCED)) {
5545 tp->serdes_counter--;
5546 current_link_up = true;
5551 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5552 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5554 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5556 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5557 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5558 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_SIGNAL_DET)) {
5560 sg_dig_status = tr32(SG_DIG_STATUS);
5561 mac_status = tr32(MAC_STATUS);
5563 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5564 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5565 u32 local_adv = 0, remote_adv = 0;
5567 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5568 local_adv |= ADVERTISE_1000XPAUSE;
5569 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5570 local_adv |= ADVERTISE_1000XPSE_ASYM;
5572 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5573 remote_adv |= LPA_1000XPAUSE;
5574 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5575 remote_adv |= LPA_1000XPAUSE_ASYM;
5577 tp->link_config.rmt_adv =
5578 mii_adv_to_ethtool_adv_x(remote_adv);
5580 tg3_setup_flow_control(tp, local_adv, remote_adv);
5581 current_link_up = true;
5582 tp->serdes_counter = 0;
5583 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5584 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5585 if (tp->serdes_counter)
5586 tp->serdes_counter--;
5589 u32 val = serdes_cfg;
5596 tw32_f(MAC_SERDES_CFG, val);
5599 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5602 /* Link parallel detection - link is up */
5603 /* only if we have PCS_SYNC and not */
5604 /* receiving config code words */
5605 mac_status = tr32(MAC_STATUS);
5606 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5607 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5608 tg3_setup_flow_control(tp, 0, 0);
5609 current_link_up = true;
5611 TG3_PHYFLG_PARALLEL_DETECT;
5612 tp->serdes_counter =
5613 SERDES_PARALLEL_DET_TIMEOUT;
5615 goto restart_autoneg;
5619 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5620 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5624 return current_link_up;
5627 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5629 bool current_link_up = false;
5631 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5634 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5635 u32 txflags, rxflags;
5638 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5639 u32 local_adv = 0, remote_adv = 0;
5641 if (txflags & ANEG_CFG_PS1)
5642 local_adv |= ADVERTISE_1000XPAUSE;
5643 if (txflags & ANEG_CFG_PS2)
5644 local_adv |= ADVERTISE_1000XPSE_ASYM;
5646 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5647 remote_adv |= LPA_1000XPAUSE;
5648 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5649 remote_adv |= LPA_1000XPAUSE_ASYM;
5651 tp->link_config.rmt_adv =
5652 mii_adv_to_ethtool_adv_x(remote_adv);
5654 tg3_setup_flow_control(tp, local_adv, remote_adv);
5656 current_link_up = true;
5658 for (i = 0; i < 30; i++) {
5661 (MAC_STATUS_SYNC_CHANGED |
5662 MAC_STATUS_CFG_CHANGED));
5664 if ((tr32(MAC_STATUS) &
5665 (MAC_STATUS_SYNC_CHANGED |
5666 MAC_STATUS_CFG_CHANGED)) == 0)
5670 mac_status = tr32(MAC_STATUS);
5671 if (!current_link_up &&
5672 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5673 !(mac_status & MAC_STATUS_RCVD_CFG))
5674 current_link_up = true;
5676 tg3_setup_flow_control(tp, 0, 0);
5678 /* Forcing 1000FD link up. */
5679 current_link_up = true;
5681 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5684 tw32_f(MAC_MODE, tp->mac_mode);
5689 return current_link_up;
5692 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5695 u16 orig_active_speed;
5696 u8 orig_active_duplex;
5698 bool current_link_up;
5701 orig_pause_cfg = tp->link_config.active_flowctrl;
5702 orig_active_speed = tp->link_config.active_speed;
5703 orig_active_duplex = tp->link_config.active_duplex;
5705 if (!tg3_flag(tp, HW_AUTONEG) &&
5707 tg3_flag(tp, INIT_COMPLETE)) {
5708 mac_status = tr32(MAC_STATUS);
5709 mac_status &= (MAC_STATUS_PCS_SYNCED |
5710 MAC_STATUS_SIGNAL_DET |
5711 MAC_STATUS_CFG_CHANGED |
5712 MAC_STATUS_RCVD_CFG);
5713 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5714 MAC_STATUS_SIGNAL_DET)) {
5715 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5716 MAC_STATUS_CFG_CHANGED));
5721 tw32_f(MAC_TX_AUTO_NEG, 0);
5723 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5724 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5725 tw32_f(MAC_MODE, tp->mac_mode);
5728 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5729 tg3_init_bcm8002(tp);
5731 /* Enable link change event even when serdes polling. */
5732 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5735 current_link_up = false;
5736 tp->link_config.rmt_adv = 0;
5737 mac_status = tr32(MAC_STATUS);
5739 if (tg3_flag(tp, HW_AUTONEG))
5740 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5742 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5744 tp->napi[0].hw_status->status =
5745 (SD_STATUS_UPDATED |
5746 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5748 for (i = 0; i < 100; i++) {
5749 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5750 MAC_STATUS_CFG_CHANGED));
5752 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5753 MAC_STATUS_CFG_CHANGED |
5754 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5758 mac_status = tr32(MAC_STATUS);
5759 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5760 current_link_up = false;
5761 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5762 tp->serdes_counter == 0) {
5763 tw32_f(MAC_MODE, (tp->mac_mode |
5764 MAC_MODE_SEND_CONFIGS));
5766 tw32_f(MAC_MODE, tp->mac_mode);
5770 if (current_link_up) {
5771 tp->link_config.active_speed = SPEED_1000;
5772 tp->link_config.active_duplex = DUPLEX_FULL;
5773 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5774 LED_CTRL_LNKLED_OVERRIDE |
5775 LED_CTRL_1000MBPS_ON));
5777 tp->link_config.active_speed = SPEED_UNKNOWN;
5778 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5779 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5780 LED_CTRL_LNKLED_OVERRIDE |
5781 LED_CTRL_TRAFFIC_OVERRIDE));
5784 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5785 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5786 if (orig_pause_cfg != now_pause_cfg ||
5787 orig_active_speed != tp->link_config.active_speed ||
5788 orig_active_duplex != tp->link_config.active_duplex)
5789 tg3_link_report(tp);
5795 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5799 u16 current_speed = SPEED_UNKNOWN;
5800 u8 current_duplex = DUPLEX_UNKNOWN;
5801 bool current_link_up = false;
5802 u32 local_adv, remote_adv, sgsr;
5804 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5805 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5806 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5807 (sgsr & SERDES_TG3_SGMII_MODE)) {
5812 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5814 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5815 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5817 current_link_up = true;
5818 if (sgsr & SERDES_TG3_SPEED_1000) {
5819 current_speed = SPEED_1000;
5820 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5821 } else if (sgsr & SERDES_TG3_SPEED_100) {
5822 current_speed = SPEED_100;
5823 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5825 current_speed = SPEED_10;
5826 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5829 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5830 current_duplex = DUPLEX_FULL;
5832 current_duplex = DUPLEX_HALF;
5835 tw32_f(MAC_MODE, tp->mac_mode);
5838 tg3_clear_mac_status(tp);
5840 goto fiber_setup_done;
5843 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5844 tw32_f(MAC_MODE, tp->mac_mode);
5847 tg3_clear_mac_status(tp);
5852 tp->link_config.rmt_adv = 0;
5854 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5855 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5856 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5857 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5858 bmsr |= BMSR_LSTATUS;
5860 bmsr &= ~BMSR_LSTATUS;
5863 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5865 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5866 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5867 /* do nothing, just check for link up at the end */
5868 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5871 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5872 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5873 ADVERTISE_1000XPAUSE |
5874 ADVERTISE_1000XPSE_ASYM |
5877 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5878 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5880 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5881 tg3_writephy(tp, MII_ADVERTISE, newadv);
5882 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5883 tg3_writephy(tp, MII_BMCR, bmcr);
5885 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5886 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5887 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5894 bmcr &= ~BMCR_SPEED1000;
5895 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5897 if (tp->link_config.duplex == DUPLEX_FULL)
5898 new_bmcr |= BMCR_FULLDPLX;
5900 if (new_bmcr != bmcr) {
5901 /* BMCR_SPEED1000 is a reserved bit that needs
5902 * to be set on write.
5904 new_bmcr |= BMCR_SPEED1000;
5906 /* Force a linkdown */
5910 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5911 adv &= ~(ADVERTISE_1000XFULL |
5912 ADVERTISE_1000XHALF |
5914 tg3_writephy(tp, MII_ADVERTISE, adv);
5915 tg3_writephy(tp, MII_BMCR, bmcr |
5919 tg3_carrier_off(tp);
5921 tg3_writephy(tp, MII_BMCR, new_bmcr);
5923 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5924 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5925 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5926 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5927 bmsr |= BMSR_LSTATUS;
5929 bmsr &= ~BMSR_LSTATUS;
5931 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5935 if (bmsr & BMSR_LSTATUS) {
5936 current_speed = SPEED_1000;
5937 current_link_up = true;
5938 if (bmcr & BMCR_FULLDPLX)
5939 current_duplex = DUPLEX_FULL;
5941 current_duplex = DUPLEX_HALF;
5946 if (bmcr & BMCR_ANENABLE) {
5949 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5950 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5951 common = local_adv & remote_adv;
5952 if (common & (ADVERTISE_1000XHALF |
5953 ADVERTISE_1000XFULL)) {
5954 if (common & ADVERTISE_1000XFULL)
5955 current_duplex = DUPLEX_FULL;
5957 current_duplex = DUPLEX_HALF;
5959 tp->link_config.rmt_adv =
5960 mii_adv_to_ethtool_adv_x(remote_adv);
5961 } else if (!tg3_flag(tp, 5780_CLASS)) {
5962 /* Link is up via parallel detect */
5964 current_link_up = false;
5970 if (current_link_up && current_duplex == DUPLEX_FULL)
5971 tg3_setup_flow_control(tp, local_adv, remote_adv);
5973 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5974 if (tp->link_config.active_duplex == DUPLEX_HALF)
5975 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5977 tw32_f(MAC_MODE, tp->mac_mode);
5980 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5982 tp->link_config.active_speed = current_speed;
5983 tp->link_config.active_duplex = current_duplex;
5985 tg3_test_and_report_link_chg(tp, current_link_up);
5989 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5991 if (tp->serdes_counter) {
5992 /* Give autoneg time to complete. */
5993 tp->serdes_counter--;
5998 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6001 tg3_readphy(tp, MII_BMCR, &bmcr);
6002 if (bmcr & BMCR_ANENABLE) {
6005 /* Select shadow register 0x1f */
6006 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6007 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6009 /* Select expansion interrupt status register */
6010 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6011 MII_TG3_DSP_EXP1_INT_STAT);
6012 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6013 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6015 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6016 /* We have signal detect and not receiving
6017 * config code words, link is up by parallel
6021 bmcr &= ~BMCR_ANENABLE;
6022 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6023 tg3_writephy(tp, MII_BMCR, bmcr);
6024 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6027 } else if (tp->link_up &&
6028 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6029 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6032 /* Select expansion interrupt status register */
6033 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6034 MII_TG3_DSP_EXP1_INT_STAT);
6035 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6039 /* Config code words received, turn on autoneg. */
6040 tg3_readphy(tp, MII_BMCR, &bmcr);
6041 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6043 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6049 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6054 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6055 err = tg3_setup_fiber_phy(tp, force_reset);
6056 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6057 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6059 err = tg3_setup_copper_phy(tp, force_reset);
6061 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6064 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6065 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6067 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6072 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6073 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6074 tw32(GRC_MISC_CFG, val);
6077 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6078 (6 << TX_LENGTHS_IPG_SHIFT);
6079 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6080 tg3_asic_rev(tp) == ASIC_REV_5762)
6081 val |= tr32(MAC_TX_LENGTHS) &
6082 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6083 TX_LENGTHS_CNT_DWN_VAL_MSK);
6085 if (tp->link_config.active_speed == SPEED_1000 &&
6086 tp->link_config.active_duplex == DUPLEX_HALF)
6087 tw32(MAC_TX_LENGTHS, val |
6088 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6090 tw32(MAC_TX_LENGTHS, val |
6091 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6093 if (!tg3_flag(tp, 5705_PLUS)) {
6095 tw32(HOSTCC_STAT_COAL_TICKS,
6096 tp->coal.stats_block_coalesce_usecs);
6098 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6102 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6103 val = tr32(PCIE_PWR_MGMT_THRESH);
6105 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6108 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6109 tw32(PCIE_PWR_MGMT_THRESH, val);
6115 /* tp->lock must be held */
6116 static u64 tg3_refclk_read(struct tg3 *tp)
6118 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6119 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6122 /* tp->lock must be held */
6123 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6125 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6127 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6128 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6129 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6130 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6133 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6134 static inline void tg3_full_unlock(struct tg3 *tp);
6135 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6137 struct tg3 *tp = netdev_priv(dev);
6139 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6140 SOF_TIMESTAMPING_RX_SOFTWARE |
6141 SOF_TIMESTAMPING_SOFTWARE;
6143 if (tg3_flag(tp, PTP_CAPABLE)) {
6144 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6145 SOF_TIMESTAMPING_RX_HARDWARE |
6146 SOF_TIMESTAMPING_RAW_HARDWARE;
6150 info->phc_index = ptp_clock_index(tp->ptp_clock);
6152 info->phc_index = -1;
6154 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6156 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6157 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6158 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6159 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6163 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6165 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6166 bool neg_adj = false;
6174 /* Frequency adjustment is performed using hardware with a 24 bit
6175 * accumulator and a programmable correction value. On each clk, the
6176 * correction value gets added to the accumulator and when it
6177 * overflows, the time counter is incremented/decremented.
6179 * So conversion from ppb to correction value is
6180 * ppb * (1 << 24) / 1000000000
6182 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6183 TG3_EAV_REF_CLK_CORRECT_MASK;
6185 tg3_full_lock(tp, 0);
6188 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6189 TG3_EAV_REF_CLK_CORRECT_EN |
6190 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6192 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6194 tg3_full_unlock(tp);
6199 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6201 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6203 tg3_full_lock(tp, 0);
6204 tp->ptp_adjust += delta;
6205 tg3_full_unlock(tp);
6210 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6214 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6216 tg3_full_lock(tp, 0);
6217 ns = tg3_refclk_read(tp);
6218 ns += tp->ptp_adjust;
6219 tg3_full_unlock(tp);
6221 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6222 ts->tv_nsec = remainder;
6227 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6228 const struct timespec *ts)
6231 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6233 ns = timespec_to_ns(ts);
6235 tg3_full_lock(tp, 0);
6236 tg3_refclk_write(tp, ns);
6238 tg3_full_unlock(tp);
6243 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6244 struct ptp_clock_request *rq, int on)
6246 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6251 case PTP_CLK_REQ_PEROUT:
6252 if (rq->perout.index != 0)
6255 tg3_full_lock(tp, 0);
6256 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6257 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6262 nsec = rq->perout.start.sec * 1000000000ULL +
6263 rq->perout.start.nsec;
6265 if (rq->perout.period.sec || rq->perout.period.nsec) {
6266 netdev_warn(tp->dev,
6267 "Device supports only a one-shot timesync output, period must be 0\n");
6272 if (nsec & (1ULL << 63)) {
6273 netdev_warn(tp->dev,
6274 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6279 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6280 tw32(TG3_EAV_WATCHDOG0_MSB,
6281 TG3_EAV_WATCHDOG0_EN |
6282 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6284 tw32(TG3_EAV_REF_CLCK_CTL,
6285 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6287 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6288 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6292 tg3_full_unlock(tp);
6302 static const struct ptp_clock_info tg3_ptp_caps = {
6303 .owner = THIS_MODULE,
6304 .name = "tg3 clock",
6305 .max_adj = 250000000,
6310 .adjfreq = tg3_ptp_adjfreq,
6311 .adjtime = tg3_ptp_adjtime,
6312 .gettime = tg3_ptp_gettime,
6313 .settime = tg3_ptp_settime,
6314 .enable = tg3_ptp_enable,
6317 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6318 struct skb_shared_hwtstamps *timestamp)
6320 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6321 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6325 /* tp->lock must be held */
6326 static void tg3_ptp_init(struct tg3 *tp)
6328 if (!tg3_flag(tp, PTP_CAPABLE))
6331 /* Initialize the hardware clock to the system time. */
6332 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6334 tp->ptp_info = tg3_ptp_caps;
6337 /* tp->lock must be held */
6338 static void tg3_ptp_resume(struct tg3 *tp)
6340 if (!tg3_flag(tp, PTP_CAPABLE))
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6347 static void tg3_ptp_fini(struct tg3 *tp)
6349 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6352 ptp_clock_unregister(tp->ptp_clock);
6353 tp->ptp_clock = NULL;
6357 static inline int tg3_irq_sync(struct tg3 *tp)
6359 return tp->irq_sync;
6362 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6366 dst = (u32 *)((u8 *)dst + off);
6367 for (i = 0; i < len; i += sizeof(u32))
6368 *dst++ = tr32(off + i);
6371 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6373 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6374 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6375 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6376 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6377 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6378 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6379 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6380 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6381 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6382 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6383 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6384 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6385 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6386 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6387 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6388 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6389 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6390 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6391 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6393 if (tg3_flag(tp, SUPPORT_MSIX))
6394 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6396 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6397 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6398 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6399 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6400 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6401 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6402 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6403 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6405 if (!tg3_flag(tp, 5705_PLUS)) {
6406 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6407 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6408 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6411 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6412 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6413 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6414 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6415 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6417 if (tg3_flag(tp, NVRAM))
6418 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6421 static void tg3_dump_state(struct tg3 *tp)
6426 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6430 if (tg3_flag(tp, PCI_EXPRESS)) {
6431 /* Read up to but not including private PCI registers */
6432 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6433 regs[i / sizeof(u32)] = tr32(i);
6435 tg3_dump_legacy_regs(tp, regs);
6437 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6438 if (!regs[i + 0] && !regs[i + 1] &&
6439 !regs[i + 2] && !regs[i + 3])
6442 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6444 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6449 for (i = 0; i < tp->irq_cnt; i++) {
6450 struct tg3_napi *tnapi = &tp->napi[i];
6452 /* SW status block */
6454 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6456 tnapi->hw_status->status,
6457 tnapi->hw_status->status_tag,
6458 tnapi->hw_status->rx_jumbo_consumer,
6459 tnapi->hw_status->rx_consumer,
6460 tnapi->hw_status->rx_mini_consumer,
6461 tnapi->hw_status->idx[0].rx_producer,
6462 tnapi->hw_status->idx[0].tx_consumer);
6465 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6467 tnapi->last_tag, tnapi->last_irq_tag,
6468 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6470 tnapi->prodring.rx_std_prod_idx,
6471 tnapi->prodring.rx_std_cons_idx,
6472 tnapi->prodring.rx_jmb_prod_idx,
6473 tnapi->prodring.rx_jmb_cons_idx);
6477 /* This is called whenever we suspect that the system chipset is re-
6478 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6479 * is bogus tx completions. We try to recover by setting the
6480 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6483 static void tg3_tx_recover(struct tg3 *tp)
6485 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6486 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6488 netdev_warn(tp->dev,
6489 "The system may be re-ordering memory-mapped I/O "
6490 "cycles to the network device, attempting to recover. "
6491 "Please report the problem to the driver maintainer "
6492 "and include system chipset information.\n");
6494 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6497 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6499 /* Tell compiler to fetch tx indices from memory. */
6501 return tnapi->tx_pending -
6502 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6505 /* Tigon3 never reports partial packet sends. So we do not
6506 * need special logic to handle SKBs that have not had all
6507 * of their frags sent yet, like SunGEM does.
6509 static void tg3_tx(struct tg3_napi *tnapi)
6511 struct tg3 *tp = tnapi->tp;
6512 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6513 u32 sw_idx = tnapi->tx_cons;
6514 struct netdev_queue *txq;
6515 int index = tnapi - tp->napi;
6516 unsigned int pkts_compl = 0, bytes_compl = 0;
6518 if (tg3_flag(tp, ENABLE_TSS))
6521 txq = netdev_get_tx_queue(tp->dev, index);
6523 while (sw_idx != hw_idx) {
6524 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6525 struct sk_buff *skb = ri->skb;
6528 if (unlikely(skb == NULL)) {
6533 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6534 struct skb_shared_hwtstamps timestamp;
6535 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6536 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6538 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6540 skb_tstamp_tx(skb, ×tamp);
6543 pci_unmap_single(tp->pdev,
6544 dma_unmap_addr(ri, mapping),
6550 while (ri->fragmented) {
6551 ri->fragmented = false;
6552 sw_idx = NEXT_TX(sw_idx);
6553 ri = &tnapi->tx_buffers[sw_idx];
6556 sw_idx = NEXT_TX(sw_idx);
6558 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6559 ri = &tnapi->tx_buffers[sw_idx];
6560 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6563 pci_unmap_page(tp->pdev,
6564 dma_unmap_addr(ri, mapping),
6565 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6568 while (ri->fragmented) {
6569 ri->fragmented = false;
6570 sw_idx = NEXT_TX(sw_idx);
6571 ri = &tnapi->tx_buffers[sw_idx];
6574 sw_idx = NEXT_TX(sw_idx);
6578 bytes_compl += skb->len;
6582 if (unlikely(tx_bug)) {
6588 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6590 tnapi->tx_cons = sw_idx;
6592 /* Need to make the tx_cons update visible to tg3_start_xmit()
6593 * before checking for netif_queue_stopped(). Without the
6594 * memory barrier, there is a small possibility that tg3_start_xmit()
6595 * will miss it and cause the queue to be stopped forever.
6599 if (unlikely(netif_tx_queue_stopped(txq) &&
6600 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6601 __netif_tx_lock(txq, smp_processor_id());
6602 if (netif_tx_queue_stopped(txq) &&
6603 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6604 netif_tx_wake_queue(txq);
6605 __netif_tx_unlock(txq);
6609 static void tg3_frag_free(bool is_frag, void *data)
6612 put_page(virt_to_head_page(data));
6617 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6619 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6620 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6625 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6626 map_sz, PCI_DMA_FROMDEVICE);
6627 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6632 /* Returns size of skb allocated or < 0 on error.
6634 * We only need to fill in the address because the other members
6635 * of the RX descriptor are invariant, see tg3_init_rings.
6637 * Note the purposeful assymetry of cpu vs. chip accesses. For
6638 * posting buffers we only dirty the first cache line of the RX
6639 * descriptor (containing the address). Whereas for the RX status
6640 * buffers the cpu only reads the last cacheline of the RX descriptor
6641 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6643 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6644 u32 opaque_key, u32 dest_idx_unmasked,
6645 unsigned int *frag_size)
6647 struct tg3_rx_buffer_desc *desc;
6648 struct ring_info *map;
6651 int skb_size, data_size, dest_idx;
6653 switch (opaque_key) {
6654 case RXD_OPAQUE_RING_STD:
6655 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6656 desc = &tpr->rx_std[dest_idx];
6657 map = &tpr->rx_std_buffers[dest_idx];
6658 data_size = tp->rx_pkt_map_sz;
6661 case RXD_OPAQUE_RING_JUMBO:
6662 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6663 desc = &tpr->rx_jmb[dest_idx].std;
6664 map = &tpr->rx_jmb_buffers[dest_idx];
6665 data_size = TG3_RX_JMB_MAP_SZ;
6672 /* Do not overwrite any of the map or rp information
6673 * until we are sure we can commit to a new buffer.
6675 * Callers depend upon this behavior and assume that
6676 * we leave everything unchanged if we fail.
6678 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6679 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6680 if (skb_size <= PAGE_SIZE) {
6681 data = netdev_alloc_frag(skb_size);
6682 *frag_size = skb_size;
6684 data = kmalloc(skb_size, GFP_ATOMIC);
6690 mapping = pci_map_single(tp->pdev,
6691 data + TG3_RX_OFFSET(tp),
6693 PCI_DMA_FROMDEVICE);
6694 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6695 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6700 dma_unmap_addr_set(map, mapping, mapping);
6702 desc->addr_hi = ((u64)mapping >> 32);
6703 desc->addr_lo = ((u64)mapping & 0xffffffff);
6708 /* We only need to move over in the address because the other
6709 * members of the RX descriptor are invariant. See notes above
6710 * tg3_alloc_rx_data for full details.
6712 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6713 struct tg3_rx_prodring_set *dpr,
6714 u32 opaque_key, int src_idx,
6715 u32 dest_idx_unmasked)
6717 struct tg3 *tp = tnapi->tp;
6718 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6719 struct ring_info *src_map, *dest_map;
6720 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6723 switch (opaque_key) {
6724 case RXD_OPAQUE_RING_STD:
6725 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6726 dest_desc = &dpr->rx_std[dest_idx];
6727 dest_map = &dpr->rx_std_buffers[dest_idx];
6728 src_desc = &spr->rx_std[src_idx];
6729 src_map = &spr->rx_std_buffers[src_idx];
6732 case RXD_OPAQUE_RING_JUMBO:
6733 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6734 dest_desc = &dpr->rx_jmb[dest_idx].std;
6735 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6736 src_desc = &spr->rx_jmb[src_idx].std;
6737 src_map = &spr->rx_jmb_buffers[src_idx];
6744 dest_map->data = src_map->data;
6745 dma_unmap_addr_set(dest_map, mapping,
6746 dma_unmap_addr(src_map, mapping));
6747 dest_desc->addr_hi = src_desc->addr_hi;
6748 dest_desc->addr_lo = src_desc->addr_lo;
6750 /* Ensure that the update to the skb happens after the physical
6751 * addresses have been transferred to the new BD location.
6755 src_map->data = NULL;
6758 /* The RX ring scheme is composed of multiple rings which post fresh
6759 * buffers to the chip, and one special ring the chip uses to report
6760 * status back to the host.
6762 * The special ring reports the status of received packets to the
6763 * host. The chip does not write into the original descriptor the
6764 * RX buffer was obtained from. The chip simply takes the original
6765 * descriptor as provided by the host, updates the status and length
6766 * field, then writes this into the next status ring entry.
6768 * Each ring the host uses to post buffers to the chip is described
6769 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6770 * it is first placed into the on-chip ram. When the packet's length
6771 * is known, it walks down the TG3_BDINFO entries to select the ring.
6772 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6773 * which is within the range of the new packet's length is chosen.
6775 * The "separate ring for rx status" scheme may sound queer, but it makes
6776 * sense from a cache coherency perspective. If only the host writes
6777 * to the buffer post rings, and only the chip writes to the rx status
6778 * rings, then cache lines never move beyond shared-modified state.
6779 * If both the host and chip were to write into the same ring, cache line
6780 * eviction could occur since both entities want it in an exclusive state.
6782 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6784 struct tg3 *tp = tnapi->tp;
6785 u32 work_mask, rx_std_posted = 0;
6786 u32 std_prod_idx, jmb_prod_idx;
6787 u32 sw_idx = tnapi->rx_rcb_ptr;
6790 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6792 hw_idx = *(tnapi->rx_rcb_prod_idx);
6794 * We need to order the read of hw_idx and the read of
6795 * the opaque cookie.
6800 std_prod_idx = tpr->rx_std_prod_idx;
6801 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6802 while (sw_idx != hw_idx && budget > 0) {
6803 struct ring_info *ri;
6804 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6806 struct sk_buff *skb;
6807 dma_addr_t dma_addr;
6808 u32 opaque_key, desc_idx, *post_ptr;
6812 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6813 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6814 if (opaque_key == RXD_OPAQUE_RING_STD) {
6815 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6816 dma_addr = dma_unmap_addr(ri, mapping);
6818 post_ptr = &std_prod_idx;
6820 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6821 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6822 dma_addr = dma_unmap_addr(ri, mapping);
6824 post_ptr = &jmb_prod_idx;
6826 goto next_pkt_nopost;
6828 work_mask |= opaque_key;
6830 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6831 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6833 tg3_recycle_rx(tnapi, tpr, opaque_key,
6834 desc_idx, *post_ptr);
6836 /* Other statistics kept track of by card. */
6841 prefetch(data + TG3_RX_OFFSET(tp));
6842 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6845 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6846 RXD_FLAG_PTPSTAT_PTPV1 ||
6847 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6848 RXD_FLAG_PTPSTAT_PTPV2) {
6849 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6850 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6853 if (len > TG3_RX_COPY_THRESH(tp)) {
6855 unsigned int frag_size;
6857 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6858 *post_ptr, &frag_size);
6862 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6863 PCI_DMA_FROMDEVICE);
6865 skb = build_skb(data, frag_size);
6867 tg3_frag_free(frag_size != 0, data);
6868 goto drop_it_no_recycle;
6870 skb_reserve(skb, TG3_RX_OFFSET(tp));
6871 /* Ensure that the update to the data happens
6872 * after the usage of the old DMA mapping.
6879 tg3_recycle_rx(tnapi, tpr, opaque_key,
6880 desc_idx, *post_ptr);
6882 skb = netdev_alloc_skb(tp->dev,
6883 len + TG3_RAW_IP_ALIGN);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6888 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6890 data + TG3_RX_OFFSET(tp),
6892 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6897 tg3_hwclock_to_timestamp(tp, tstamp,
6898 skb_hwtstamps(skb));
6900 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6901 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6902 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6903 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6904 skb->ip_summed = CHECKSUM_UNNECESSARY;
6906 skb_checksum_none_assert(skb);
6908 skb->protocol = eth_type_trans(skb, tp->dev);
6910 if (len > (tp->dev->mtu + ETH_HLEN) &&
6911 skb->protocol != htons(ETH_P_8021Q)) {
6913 goto drop_it_no_recycle;
6916 if (desc->type_flags & RXD_FLAG_VLAN &&
6917 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6918 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6919 desc->err_vlan & RXD_VLAN_MASK);
6921 napi_gro_receive(&tnapi->napi, skb);
6929 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6930 tpr->rx_std_prod_idx = std_prod_idx &
6931 tp->rx_std_ring_mask;
6932 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6933 tpr->rx_std_prod_idx);
6934 work_mask &= ~RXD_OPAQUE_RING_STD;
6939 sw_idx &= tp->rx_ret_ring_mask;
6941 /* Refresh hw_idx to see if there is new work */
6942 if (sw_idx == hw_idx) {
6943 hw_idx = *(tnapi->rx_rcb_prod_idx);
6948 /* ACK the status ring. */
6949 tnapi->rx_rcb_ptr = sw_idx;
6950 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6952 /* Refill RX ring(s). */
6953 if (!tg3_flag(tp, ENABLE_RSS)) {
6954 /* Sync BD data before updating mailbox */
6957 if (work_mask & RXD_OPAQUE_RING_STD) {
6958 tpr->rx_std_prod_idx = std_prod_idx &
6959 tp->rx_std_ring_mask;
6960 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6961 tpr->rx_std_prod_idx);
6963 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6964 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6965 tp->rx_jmb_ring_mask;
6966 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6967 tpr->rx_jmb_prod_idx);
6970 } else if (work_mask) {
6971 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6972 * updated before the producer indices can be updated.
6976 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6977 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6979 if (tnapi != &tp->napi[1]) {
6980 tp->rx_refill = true;
6981 napi_schedule(&tp->napi[1].napi);
6988 static void tg3_poll_link(struct tg3 *tp)
6990 /* handle link change and other phy events */
6991 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6992 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6994 if (sblk->status & SD_STATUS_LINK_CHG) {
6995 sblk->status = SD_STATUS_UPDATED |
6996 (sblk->status & ~SD_STATUS_LINK_CHG);
6997 spin_lock(&tp->lock);
6998 if (tg3_flag(tp, USE_PHYLIB)) {
7000 (MAC_STATUS_SYNC_CHANGED |
7001 MAC_STATUS_CFG_CHANGED |
7002 MAC_STATUS_MI_COMPLETION |
7003 MAC_STATUS_LNKSTATE_CHANGED));
7006 tg3_setup_phy(tp, false);
7007 spin_unlock(&tp->lock);
7012 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7013 struct tg3_rx_prodring_set *dpr,
7014 struct tg3_rx_prodring_set *spr)
7016 u32 si, di, cpycnt, src_prod_idx;
7020 src_prod_idx = spr->rx_std_prod_idx;
7022 /* Make sure updates to the rx_std_buffers[] entries and the
7023 * standard producer index are seen in the correct order.
7027 if (spr->rx_std_cons_idx == src_prod_idx)
7030 if (spr->rx_std_cons_idx < src_prod_idx)
7031 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7033 cpycnt = tp->rx_std_ring_mask + 1 -
7034 spr->rx_std_cons_idx;
7036 cpycnt = min(cpycnt,
7037 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7039 si = spr->rx_std_cons_idx;
7040 di = dpr->rx_std_prod_idx;
7042 for (i = di; i < di + cpycnt; i++) {
7043 if (dpr->rx_std_buffers[i].data) {
7053 /* Ensure that updates to the rx_std_buffers ring and the
7054 * shadowed hardware producer ring from tg3_recycle_skb() are
7055 * ordered correctly WRT the skb check above.
7059 memcpy(&dpr->rx_std_buffers[di],
7060 &spr->rx_std_buffers[si],
7061 cpycnt * sizeof(struct ring_info));
7063 for (i = 0; i < cpycnt; i++, di++, si++) {
7064 struct tg3_rx_buffer_desc *sbd, *dbd;
7065 sbd = &spr->rx_std[si];
7066 dbd = &dpr->rx_std[di];
7067 dbd->addr_hi = sbd->addr_hi;
7068 dbd->addr_lo = sbd->addr_lo;
7071 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7072 tp->rx_std_ring_mask;
7073 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7074 tp->rx_std_ring_mask;
7078 src_prod_idx = spr->rx_jmb_prod_idx;
7080 /* Make sure updates to the rx_jmb_buffers[] entries and
7081 * the jumbo producer index are seen in the correct order.
7085 if (spr->rx_jmb_cons_idx == src_prod_idx)
7088 if (spr->rx_jmb_cons_idx < src_prod_idx)
7089 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7091 cpycnt = tp->rx_jmb_ring_mask + 1 -
7092 spr->rx_jmb_cons_idx;
7094 cpycnt = min(cpycnt,
7095 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7097 si = spr->rx_jmb_cons_idx;
7098 di = dpr->rx_jmb_prod_idx;
7100 for (i = di; i < di + cpycnt; i++) {
7101 if (dpr->rx_jmb_buffers[i].data) {
7111 /* Ensure that updates to the rx_jmb_buffers ring and the
7112 * shadowed hardware producer ring from tg3_recycle_skb() are
7113 * ordered correctly WRT the skb check above.
7117 memcpy(&dpr->rx_jmb_buffers[di],
7118 &spr->rx_jmb_buffers[si],
7119 cpycnt * sizeof(struct ring_info));
7121 for (i = 0; i < cpycnt; i++, di++, si++) {
7122 struct tg3_rx_buffer_desc *sbd, *dbd;
7123 sbd = &spr->rx_jmb[si].std;
7124 dbd = &dpr->rx_jmb[di].std;
7125 dbd->addr_hi = sbd->addr_hi;
7126 dbd->addr_lo = sbd->addr_lo;
7129 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7130 tp->rx_jmb_ring_mask;
7131 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7132 tp->rx_jmb_ring_mask;
7138 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7140 struct tg3 *tp = tnapi->tp;
7142 /* run TX completion thread */
7143 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7145 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7149 if (!tnapi->rx_rcb_prod_idx)
7152 /* run RX thread, within the bounds set by NAPI.
7153 * All RX "locking" is done by ensuring outside
7154 * code synchronizes with tg3->napi.poll()
7156 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7157 work_done += tg3_rx(tnapi, budget - work_done);
7159 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7160 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7162 u32 std_prod_idx = dpr->rx_std_prod_idx;
7163 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7165 tp->rx_refill = false;
7166 for (i = 1; i <= tp->rxq_cnt; i++)
7167 err |= tg3_rx_prodring_xfer(tp, dpr,
7168 &tp->napi[i].prodring);
7172 if (std_prod_idx != dpr->rx_std_prod_idx)
7173 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7174 dpr->rx_std_prod_idx);
7176 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7177 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7178 dpr->rx_jmb_prod_idx);
7183 tw32_f(HOSTCC_MODE, tp->coal_now);
7189 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7191 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7192 schedule_work(&tp->reset_task);
7195 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7197 cancel_work_sync(&tp->reset_task);
7198 tg3_flag_clear(tp, RESET_TASK_PENDING);
7199 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7202 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7204 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7205 struct tg3 *tp = tnapi->tp;
7207 struct tg3_hw_status *sblk = tnapi->hw_status;
7210 work_done = tg3_poll_work(tnapi, work_done, budget);
7212 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7215 if (unlikely(work_done >= budget))
7218 /* tp->last_tag is used in tg3_int_reenable() below
7219 * to tell the hw how much work has been processed,
7220 * so we must read it before checking for more work.
7222 tnapi->last_tag = sblk->status_tag;
7223 tnapi->last_irq_tag = tnapi->last_tag;
7226 /* check for RX/TX work to do */
7227 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7228 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7230 /* This test here is not race free, but will reduce
7231 * the number of interrupts by looping again.
7233 if (tnapi == &tp->napi[1] && tp->rx_refill)
7236 napi_complete(napi);
7237 /* Reenable interrupts. */
7238 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7240 /* This test here is synchronized by napi_schedule()
7241 * and napi_complete() to close the race condition.
7243 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7244 tw32(HOSTCC_MODE, tp->coalesce_mode |
7245 HOSTCC_MODE_ENABLE |
7256 /* work_done is guaranteed to be less than budget. */
7257 napi_complete(napi);
7258 tg3_reset_task_schedule(tp);
7262 static void tg3_process_error(struct tg3 *tp)
7265 bool real_error = false;
7267 if (tg3_flag(tp, ERROR_PROCESSED))
7270 /* Check Flow Attention register */
7271 val = tr32(HOSTCC_FLOW_ATTN);
7272 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7273 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7277 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7278 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7282 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7283 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7292 tg3_flag_set(tp, ERROR_PROCESSED);
7293 tg3_reset_task_schedule(tp);
7296 static int tg3_poll(struct napi_struct *napi, int budget)
7298 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7299 struct tg3 *tp = tnapi->tp;
7301 struct tg3_hw_status *sblk = tnapi->hw_status;
7304 if (sblk->status & SD_STATUS_ERROR)
7305 tg3_process_error(tp);
7309 work_done = tg3_poll_work(tnapi, work_done, budget);
7311 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7314 if (unlikely(work_done >= budget))
7317 if (tg3_flag(tp, TAGGED_STATUS)) {
7318 /* tp->last_tag is used in tg3_int_reenable() below
7319 * to tell the hw how much work has been processed,
7320 * so we must read it before checking for more work.
7322 tnapi->last_tag = sblk->status_tag;
7323 tnapi->last_irq_tag = tnapi->last_tag;
7326 sblk->status &= ~SD_STATUS_UPDATED;
7328 if (likely(!tg3_has_work(tnapi))) {
7329 napi_complete(napi);
7330 tg3_int_reenable(tnapi);
7338 /* work_done is guaranteed to be less than budget. */
7339 napi_complete(napi);
7340 tg3_reset_task_schedule(tp);
7344 static void tg3_napi_disable(struct tg3 *tp)
7348 for (i = tp->irq_cnt - 1; i >= 0; i--)
7349 napi_disable(&tp->napi[i].napi);
7352 static void tg3_napi_enable(struct tg3 *tp)
7356 for (i = 0; i < tp->irq_cnt; i++)
7357 napi_enable(&tp->napi[i].napi);
7360 static void tg3_napi_init(struct tg3 *tp)
7364 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7365 for (i = 1; i < tp->irq_cnt; i++)
7366 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7369 static void tg3_napi_fini(struct tg3 *tp)
7373 for (i = 0; i < tp->irq_cnt; i++)
7374 netif_napi_del(&tp->napi[i].napi);
7377 static inline void tg3_netif_stop(struct tg3 *tp)
7379 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7380 tg3_napi_disable(tp);
7381 netif_carrier_off(tp->dev);
7382 netif_tx_disable(tp->dev);
7385 /* tp->lock must be held */
7386 static inline void tg3_netif_start(struct tg3 *tp)
7390 /* NOTE: unconditional netif_tx_wake_all_queues is only
7391 * appropriate so long as all callers are assured to
7392 * have free tx slots (such as after tg3_init_hw)
7394 netif_tx_wake_all_queues(tp->dev);
7397 netif_carrier_on(tp->dev);
7399 tg3_napi_enable(tp);
7400 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7401 tg3_enable_ints(tp);
7404 static void tg3_irq_quiesce(struct tg3 *tp)
7408 BUG_ON(tp->irq_sync);
7413 for (i = 0; i < tp->irq_cnt; i++)
7414 synchronize_irq(tp->napi[i].irq_vec);
7417 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7418 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7419 * with as well. Most of the time, this is not necessary except when
7420 * shutting down the device.
7422 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7424 spin_lock_bh(&tp->lock);
7426 tg3_irq_quiesce(tp);
7429 static inline void tg3_full_unlock(struct tg3 *tp)
7431 spin_unlock_bh(&tp->lock);
7434 /* One-shot MSI handler - Chip automatically disables interrupt
7435 * after sending MSI so driver doesn't have to do it.
7437 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7439 struct tg3_napi *tnapi = dev_id;
7440 struct tg3 *tp = tnapi->tp;
7442 prefetch(tnapi->hw_status);
7444 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7446 if (likely(!tg3_irq_sync(tp)))
7447 napi_schedule(&tnapi->napi);
7452 /* MSI ISR - No need to check for interrupt sharing and no need to
7453 * flush status block and interrupt mailbox. PCI ordering rules
7454 * guarantee that MSI will arrive after the status block.
7456 static irqreturn_t tg3_msi(int irq, void *dev_id)
7458 struct tg3_napi *tnapi = dev_id;
7459 struct tg3 *tp = tnapi->tp;
7461 prefetch(tnapi->hw_status);
7463 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7465 * Writing any value to intr-mbox-0 clears PCI INTA# and
7466 * chip-internal interrupt pending events.
7467 * Writing non-zero to intr-mbox-0 additional tells the
7468 * NIC to stop sending us irqs, engaging "in-intr-handler"
7471 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7472 if (likely(!tg3_irq_sync(tp)))
7473 napi_schedule(&tnapi->napi);
7475 return IRQ_RETVAL(1);
7478 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7480 struct tg3_napi *tnapi = dev_id;
7481 struct tg3 *tp = tnapi->tp;
7482 struct tg3_hw_status *sblk = tnapi->hw_status;
7483 unsigned int handled = 1;
7485 /* In INTx mode, it is possible for the interrupt to arrive at
7486 * the CPU before the status block posted prior to the interrupt.
7487 * Reading the PCI State register will confirm whether the
7488 * interrupt is ours and will flush the status block.
7490 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7491 if (tg3_flag(tp, CHIP_RESETTING) ||
7492 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7499 * Writing any value to intr-mbox-0 clears PCI INTA# and
7500 * chip-internal interrupt pending events.
7501 * Writing non-zero to intr-mbox-0 additional tells the
7502 * NIC to stop sending us irqs, engaging "in-intr-handler"
7505 * Flush the mailbox to de-assert the IRQ immediately to prevent
7506 * spurious interrupts. The flush impacts performance but
7507 * excessive spurious interrupts can be worse in some cases.
7509 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7510 if (tg3_irq_sync(tp))
7512 sblk->status &= ~SD_STATUS_UPDATED;
7513 if (likely(tg3_has_work(tnapi))) {
7514 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7515 napi_schedule(&tnapi->napi);
7517 /* No work, shared interrupt perhaps? re-enable
7518 * interrupts, and flush that PCI write
7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7524 return IRQ_RETVAL(handled);
7527 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7529 struct tg3_napi *tnapi = dev_id;
7530 struct tg3 *tp = tnapi->tp;
7531 struct tg3_hw_status *sblk = tnapi->hw_status;
7532 unsigned int handled = 1;
7534 /* In INTx mode, it is possible for the interrupt to arrive at
7535 * the CPU before the status block posted prior to the interrupt.
7536 * Reading the PCI State register will confirm whether the
7537 * interrupt is ours and will flush the status block.
7539 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7540 if (tg3_flag(tp, CHIP_RESETTING) ||
7541 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7548 * writing any value to intr-mbox-0 clears PCI INTA# and
7549 * chip-internal interrupt pending events.
7550 * writing non-zero to intr-mbox-0 additional tells the
7551 * NIC to stop sending us irqs, engaging "in-intr-handler"
7554 * Flush the mailbox to de-assert the IRQ immediately to prevent
7555 * spurious interrupts. The flush impacts performance but
7556 * excessive spurious interrupts can be worse in some cases.
7558 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7561 * In a shared interrupt configuration, sometimes other devices'
7562 * interrupts will scream. We record the current status tag here
7563 * so that the above check can report that the screaming interrupts
7564 * are unhandled. Eventually they will be silenced.
7566 tnapi->last_irq_tag = sblk->status_tag;
7568 if (tg3_irq_sync(tp))
7571 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7573 napi_schedule(&tnapi->napi);
7576 return IRQ_RETVAL(handled);
7579 /* ISR for interrupt test */
7580 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7582 struct tg3_napi *tnapi = dev_id;
7583 struct tg3 *tp = tnapi->tp;
7584 struct tg3_hw_status *sblk = tnapi->hw_status;
7586 if ((sblk->status & SD_STATUS_UPDATED) ||
7587 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7588 tg3_disable_ints(tp);
7589 return IRQ_RETVAL(1);
7591 return IRQ_RETVAL(0);
7594 #ifdef CONFIG_NET_POLL_CONTROLLER
7595 static void tg3_poll_controller(struct net_device *dev)
7598 struct tg3 *tp = netdev_priv(dev);
7600 if (tg3_irq_sync(tp))
7603 for (i = 0; i < tp->irq_cnt; i++)
7604 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7608 static void tg3_tx_timeout(struct net_device *dev)
7610 struct tg3 *tp = netdev_priv(dev);
7612 if (netif_msg_tx_err(tp)) {
7613 netdev_err(dev, "transmit timed out, resetting\n");
7617 tg3_reset_task_schedule(tp);
7620 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7621 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7623 u32 base = (u32) mapping & 0xffffffff;
7625 return (base > 0xffffdcc0) && (base + len + 8 < base);
7628 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7629 * of any 4GB boundaries: 4G, 8G, etc
7631 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7634 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7635 u32 base = (u32) mapping & 0xffffffff;
7637 return ((base + len + (mss & 0x3fff)) < base);
7642 /* Test for DMA addresses > 40-bit */
7643 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7646 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7647 if (tg3_flag(tp, 40BIT_DMA_BUG))
7648 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7655 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7656 dma_addr_t mapping, u32 len, u32 flags,
7659 txbd->addr_hi = ((u64) mapping >> 32);
7660 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7661 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7662 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7665 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7666 dma_addr_t map, u32 len, u32 flags,
7669 struct tg3 *tp = tnapi->tp;
7672 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7675 if (tg3_4g_overflow_test(map, len))
7678 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7681 if (tg3_40bit_overflow_test(tp, map, len))
7684 if (tp->dma_limit) {
7685 u32 prvidx = *entry;
7686 u32 tmp_flag = flags & ~TXD_FLAG_END;
7687 while (len > tp->dma_limit && *budget) {
7688 u32 frag_len = tp->dma_limit;
7689 len -= tp->dma_limit;
7691 /* Avoid the 8byte DMA problem */
7693 len += tp->dma_limit / 2;
7694 frag_len = tp->dma_limit / 2;
7697 tnapi->tx_buffers[*entry].fragmented = true;
7699 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7700 frag_len, tmp_flag, mss, vlan);
7703 *entry = NEXT_TX(*entry);
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 len, flags, mss, vlan);
7713 *entry = NEXT_TX(*entry);
7716 tnapi->tx_buffers[prvidx].fragmented = false;
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
7722 *entry = NEXT_TX(*entry);
7728 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7731 struct sk_buff *skb;
7732 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7737 pci_unmap_single(tnapi->tp->pdev,
7738 dma_unmap_addr(txb, mapping),
7742 while (txb->fragmented) {
7743 txb->fragmented = false;
7744 entry = NEXT_TX(entry);
7745 txb = &tnapi->tx_buffers[entry];
7748 for (i = 0; i <= last; i++) {
7749 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7751 entry = NEXT_TX(entry);
7752 txb = &tnapi->tx_buffers[entry];
7754 pci_unmap_page(tnapi->tp->pdev,
7755 dma_unmap_addr(txb, mapping),
7756 skb_frag_size(frag), PCI_DMA_TODEVICE);
7758 while (txb->fragmented) {
7759 txb->fragmented = false;
7760 entry = NEXT_TX(entry);
7761 txb = &tnapi->tx_buffers[entry];
7766 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7767 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7768 struct sk_buff **pskb,
7769 u32 *entry, u32 *budget,
7770 u32 base_flags, u32 mss, u32 vlan)
7772 struct tg3 *tp = tnapi->tp;
7773 struct sk_buff *new_skb, *skb = *pskb;
7774 dma_addr_t new_addr = 0;
7777 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7778 new_skb = skb_copy(skb, GFP_ATOMIC);
7780 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7782 new_skb = skb_copy_expand(skb,
7783 skb_headroom(skb) + more_headroom,
7784 skb_tailroom(skb), GFP_ATOMIC);
7790 /* New SKB is guaranteed to be linear. */
7791 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7793 /* Make sure the mapping succeeded */
7794 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7795 dev_kfree_skb(new_skb);
7798 u32 save_entry = *entry;
7800 base_flags |= TXD_FLAG_END;
7802 tnapi->tx_buffers[*entry].skb = new_skb;
7803 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7806 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7807 new_skb->len, base_flags,
7809 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7810 dev_kfree_skb(new_skb);
7821 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7823 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7824 * TSO header is greater than 80 bytes.
7826 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7828 struct sk_buff *segs, *nskb;
7829 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7831 /* Estimate the number of fragments in the worst case */
7832 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
7833 netif_stop_queue(tp->dev);
7835 /* netif_tx_stop_queue() must be done before checking
7836 * checking tx index in tg3_tx_avail() below, because in
7837 * tg3_tx(), we update tx index before checking for
7838 * netif_tx_queue_stopped().
7841 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7842 return NETDEV_TX_BUSY;
7844 netif_wake_queue(tp->dev);
7847 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
7849 goto tg3_tso_bug_end;
7855 tg3_start_xmit(nskb, tp->dev);
7861 return NETDEV_TX_OK;
7864 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7865 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7867 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7869 struct tg3 *tp = netdev_priv(dev);
7870 u32 len, entry, base_flags, mss, vlan = 0;
7872 int i = -1, would_hit_hwbug;
7874 struct tg3_napi *tnapi;
7875 struct netdev_queue *txq;
7878 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7879 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7880 if (tg3_flag(tp, ENABLE_TSS))
7883 budget = tg3_tx_avail(tnapi);
7885 /* We are running in BH disabled context with netif_tx_lock
7886 * and TX reclaim runs via tp->napi.poll inside of a software
7887 * interrupt. Furthermore, IRQ processing runs lockless so we have
7888 * no IRQ context deadlocks to worry about either. Rejoice!
7890 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7891 if (!netif_tx_queue_stopped(txq)) {
7892 netif_tx_stop_queue(txq);
7894 /* This is a hard error, log it. */
7896 "BUG! Tx Ring full when queue awake!\n");
7898 return NETDEV_TX_BUSY;
7901 entry = tnapi->tx_prod;
7903 if (skb->ip_summed == CHECKSUM_PARTIAL)
7904 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7906 mss = skb_shinfo(skb)->gso_size;
7909 u32 tcp_opt_len, hdr_len;
7911 if (skb_header_cloned(skb) &&
7912 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7916 tcp_opt_len = tcp_optlen(skb);
7918 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7920 if (!skb_is_gso_v6(skb)) {
7922 iph->tot_len = htons(mss + hdr_len);
7925 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7926 tg3_flag(tp, TSO_BUG))
7927 return tg3_tso_bug(tp, skb);
7929 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7930 TXD_FLAG_CPU_POST_DMA);
7932 if (tg3_flag(tp, HW_TSO_1) ||
7933 tg3_flag(tp, HW_TSO_2) ||
7934 tg3_flag(tp, HW_TSO_3)) {
7935 tcp_hdr(skb)->check = 0;
7936 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7938 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7943 if (tg3_flag(tp, HW_TSO_3)) {
7944 mss |= (hdr_len & 0xc) << 12;
7946 base_flags |= 0x00000010;
7947 base_flags |= (hdr_len & 0x3e0) << 5;
7948 } else if (tg3_flag(tp, HW_TSO_2))
7949 mss |= hdr_len << 9;
7950 else if (tg3_flag(tp, HW_TSO_1) ||
7951 tg3_asic_rev(tp) == ASIC_REV_5705) {
7952 if (tcp_opt_len || iph->ihl > 5) {
7955 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7956 mss |= (tsflags << 11);
7959 if (tcp_opt_len || iph->ihl > 5) {
7962 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7963 base_flags |= tsflags << 12;
7968 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7969 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7970 base_flags |= TXD_FLAG_JMB_PKT;
7972 if (vlan_tx_tag_present(skb)) {
7973 base_flags |= TXD_FLAG_VLAN;
7974 vlan = vlan_tx_tag_get(skb);
7977 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7978 tg3_flag(tp, TX_TSTAMP_EN)) {
7979 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7980 base_flags |= TXD_FLAG_HWTSTAMP;
7983 len = skb_headlen(skb);
7985 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7986 if (pci_dma_mapping_error(tp->pdev, mapping))
7990 tnapi->tx_buffers[entry].skb = skb;
7991 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
7993 would_hit_hwbug = 0;
7995 if (tg3_flag(tp, 5701_DMA_BUG))
7996 would_hit_hwbug = 1;
7998 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
7999 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8001 would_hit_hwbug = 1;
8002 } else if (skb_shinfo(skb)->nr_frags > 0) {
8005 if (!tg3_flag(tp, HW_TSO_1) &&
8006 !tg3_flag(tp, HW_TSO_2) &&
8007 !tg3_flag(tp, HW_TSO_3))
8010 /* Now loop through additional data
8011 * fragments, and queue them.
8013 last = skb_shinfo(skb)->nr_frags - 1;
8014 for (i = 0; i <= last; i++) {
8015 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8017 len = skb_frag_size(frag);
8018 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8019 len, DMA_TO_DEVICE);
8021 tnapi->tx_buffers[entry].skb = NULL;
8022 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8024 if (dma_mapping_error(&tp->pdev->dev, mapping))
8028 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8030 ((i == last) ? TXD_FLAG_END : 0),
8032 would_hit_hwbug = 1;
8038 if (would_hit_hwbug) {
8039 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8041 /* If the workaround fails due to memory/mapping
8042 * failure, silently drop this packet.
8044 entry = tnapi->tx_prod;
8045 budget = tg3_tx_avail(tnapi);
8046 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8047 base_flags, mss, vlan))
8051 skb_tx_timestamp(skb);
8052 netdev_tx_sent_queue(txq, skb->len);
8054 /* Sync BD data before updating mailbox */
8057 /* Packets are ready, update Tx producer idx local and on card. */
8058 tw32_tx_mbox(tnapi->prodmbox, entry);
8060 tnapi->tx_prod = entry;
8061 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8062 netif_tx_stop_queue(txq);
8064 /* netif_tx_stop_queue() must be done before checking
8065 * checking tx index in tg3_tx_avail() below, because in
8066 * tg3_tx(), we update tx index before checking for
8067 * netif_tx_queue_stopped().
8070 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8071 netif_tx_wake_queue(txq);
8075 return NETDEV_TX_OK;
8078 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8079 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8084 return NETDEV_TX_OK;
8087 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8090 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8091 MAC_MODE_PORT_MODE_MASK);
8093 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8095 if (!tg3_flag(tp, 5705_PLUS))
8096 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8098 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8099 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8101 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8103 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8105 if (tg3_flag(tp, 5705_PLUS) ||
8106 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8107 tg3_asic_rev(tp) == ASIC_REV_5700)
8108 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8111 tw32(MAC_MODE, tp->mac_mode);
8115 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8117 u32 val, bmcr, mac_mode, ptest = 0;
8119 tg3_phy_toggle_apd(tp, false);
8120 tg3_phy_toggle_automdix(tp, false);
8122 if (extlpbk && tg3_phy_set_extloopbk(tp))
8125 bmcr = BMCR_FULLDPLX;
8130 bmcr |= BMCR_SPEED100;
8134 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8136 bmcr |= BMCR_SPEED100;
8139 bmcr |= BMCR_SPEED1000;
8144 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8145 tg3_readphy(tp, MII_CTRL1000, &val);
8146 val |= CTL1000_AS_MASTER |
8147 CTL1000_ENABLE_MASTER;
8148 tg3_writephy(tp, MII_CTRL1000, val);
8150 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8151 MII_TG3_FET_PTEST_TRIM_2;
8152 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8155 bmcr |= BMCR_LOOPBACK;
8157 tg3_writephy(tp, MII_BMCR, bmcr);
8159 /* The write needs to be flushed for the FETs */
8160 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8161 tg3_readphy(tp, MII_BMCR, &bmcr);
8165 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8166 tg3_asic_rev(tp) == ASIC_REV_5785) {
8167 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8168 MII_TG3_FET_PTEST_FRC_TX_LINK |
8169 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8171 /* The write needs to be flushed for the AC131 */
8172 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8175 /* Reset to prevent losing 1st rx packet intermittently */
8176 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8177 tg3_flag(tp, 5780_CLASS)) {
8178 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8180 tw32_f(MAC_RX_MODE, tp->rx_mode);
8183 mac_mode = tp->mac_mode &
8184 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8185 if (speed == SPEED_1000)
8186 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8188 mac_mode |= MAC_MODE_PORT_MODE_MII;
8190 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8191 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8193 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8194 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8195 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8196 mac_mode |= MAC_MODE_LINK_POLARITY;
8198 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8199 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8202 tw32(MAC_MODE, mac_mode);
8208 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8210 struct tg3 *tp = netdev_priv(dev);
8212 if (features & NETIF_F_LOOPBACK) {
8213 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8216 spin_lock_bh(&tp->lock);
8217 tg3_mac_loopback(tp, true);
8218 netif_carrier_on(tp->dev);
8219 spin_unlock_bh(&tp->lock);
8220 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8222 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8225 spin_lock_bh(&tp->lock);
8226 tg3_mac_loopback(tp, false);
8227 /* Force link status check */
8228 tg3_setup_phy(tp, true);
8229 spin_unlock_bh(&tp->lock);
8230 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8234 static netdev_features_t tg3_fix_features(struct net_device *dev,
8235 netdev_features_t features)
8237 struct tg3 *tp = netdev_priv(dev);
8239 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8240 features &= ~NETIF_F_ALL_TSO;
8245 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8247 netdev_features_t changed = dev->features ^ features;
8249 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8250 tg3_set_loopback(dev, features);
8255 static void tg3_rx_prodring_free(struct tg3 *tp,
8256 struct tg3_rx_prodring_set *tpr)
8260 if (tpr != &tp->napi[0].prodring) {
8261 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8262 i = (i + 1) & tp->rx_std_ring_mask)
8263 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8266 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8267 for (i = tpr->rx_jmb_cons_idx;
8268 i != tpr->rx_jmb_prod_idx;
8269 i = (i + 1) & tp->rx_jmb_ring_mask) {
8270 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8278 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8279 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8282 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8283 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8284 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8289 /* Initialize rx rings for packet processing.
8291 * The chip has been shut down and the driver detached from
8292 * the networking, so no interrupts or new tx packets will
8293 * end up in the driver. tp->{tx,}lock are held and thus
8296 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8297 struct tg3_rx_prodring_set *tpr)
8299 u32 i, rx_pkt_dma_sz;
8301 tpr->rx_std_cons_idx = 0;
8302 tpr->rx_std_prod_idx = 0;
8303 tpr->rx_jmb_cons_idx = 0;
8304 tpr->rx_jmb_prod_idx = 0;
8306 if (tpr != &tp->napi[0].prodring) {
8307 memset(&tpr->rx_std_buffers[0], 0,
8308 TG3_RX_STD_BUFF_RING_SIZE(tp));
8309 if (tpr->rx_jmb_buffers)
8310 memset(&tpr->rx_jmb_buffers[0], 0,
8311 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8315 /* Zero out all descriptors. */
8316 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8318 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8319 if (tg3_flag(tp, 5780_CLASS) &&
8320 tp->dev->mtu > ETH_DATA_LEN)
8321 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8322 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8324 /* Initialize invariants of the rings, we only set this
8325 * stuff once. This works because the card does not
8326 * write into the rx buffer posting rings.
8328 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8329 struct tg3_rx_buffer_desc *rxd;
8331 rxd = &tpr->rx_std[i];
8332 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8333 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8334 rxd->opaque = (RXD_OPAQUE_RING_STD |
8335 (i << RXD_OPAQUE_INDEX_SHIFT));
8338 /* Now allocate fresh SKBs for each rx ring. */
8339 for (i = 0; i < tp->rx_pending; i++) {
8340 unsigned int frag_size;
8342 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8344 netdev_warn(tp->dev,
8345 "Using a smaller RX standard ring. Only "
8346 "%d out of %d buffers were allocated "
8347 "successfully\n", i, tp->rx_pending);
8355 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8358 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8360 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8363 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8364 struct tg3_rx_buffer_desc *rxd;
8366 rxd = &tpr->rx_jmb[i].std;
8367 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8368 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8370 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8371 (i << RXD_OPAQUE_INDEX_SHIFT));
8374 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8375 unsigned int frag_size;
8377 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8379 netdev_warn(tp->dev,
8380 "Using a smaller RX jumbo ring. Only %d "
8381 "out of %d buffers were allocated "
8382 "successfully\n", i, tp->rx_jumbo_pending);
8385 tp->rx_jumbo_pending = i;
8394 tg3_rx_prodring_free(tp, tpr);
8398 static void tg3_rx_prodring_fini(struct tg3 *tp,
8399 struct tg3_rx_prodring_set *tpr)
8401 kfree(tpr->rx_std_buffers);
8402 tpr->rx_std_buffers = NULL;
8403 kfree(tpr->rx_jmb_buffers);
8404 tpr->rx_jmb_buffers = NULL;
8406 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8407 tpr->rx_std, tpr->rx_std_mapping);
8411 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8412 tpr->rx_jmb, tpr->rx_jmb_mapping);
8417 static int tg3_rx_prodring_init(struct tg3 *tp,
8418 struct tg3_rx_prodring_set *tpr)
8420 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8422 if (!tpr->rx_std_buffers)
8425 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8426 TG3_RX_STD_RING_BYTES(tp),
8427 &tpr->rx_std_mapping,
8432 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8433 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8435 if (!tpr->rx_jmb_buffers)
8438 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8439 TG3_RX_JMB_RING_BYTES(tp),
8440 &tpr->rx_jmb_mapping,
8449 tg3_rx_prodring_fini(tp, tpr);
8453 /* Free up pending packets in all rx/tx rings.
8455 * The chip has been shut down and the driver detached from
8456 * the networking, so no interrupts or new tx packets will
8457 * end up in the driver. tp->{tx,}lock is not held and we are not
8458 * in an interrupt context and thus may sleep.
8460 static void tg3_free_rings(struct tg3 *tp)
8464 for (j = 0; j < tp->irq_cnt; j++) {
8465 struct tg3_napi *tnapi = &tp->napi[j];
8467 tg3_rx_prodring_free(tp, &tnapi->prodring);
8469 if (!tnapi->tx_buffers)
8472 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8473 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8478 tg3_tx_skb_unmap(tnapi, i,
8479 skb_shinfo(skb)->nr_frags - 1);
8481 dev_kfree_skb_any(skb);
8483 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8487 /* Initialize tx/rx rings for packet processing.
8489 * The chip has been shut down and the driver detached from
8490 * the networking, so no interrupts or new tx packets will
8491 * end up in the driver. tp->{tx,}lock are held and thus
8494 static int tg3_init_rings(struct tg3 *tp)
8498 /* Free up all the SKBs. */
8501 for (i = 0; i < tp->irq_cnt; i++) {
8502 struct tg3_napi *tnapi = &tp->napi[i];
8504 tnapi->last_tag = 0;
8505 tnapi->last_irq_tag = 0;
8506 tnapi->hw_status->status = 0;
8507 tnapi->hw_status->status_tag = 0;
8508 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8513 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8515 tnapi->rx_rcb_ptr = 0;
8517 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8519 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8528 static void tg3_mem_tx_release(struct tg3 *tp)
8532 for (i = 0; i < tp->irq_max; i++) {
8533 struct tg3_napi *tnapi = &tp->napi[i];
8535 if (tnapi->tx_ring) {
8536 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8537 tnapi->tx_ring, tnapi->tx_desc_mapping);
8538 tnapi->tx_ring = NULL;
8541 kfree(tnapi->tx_buffers);
8542 tnapi->tx_buffers = NULL;
8546 static int tg3_mem_tx_acquire(struct tg3 *tp)
8549 struct tg3_napi *tnapi = &tp->napi[0];
8551 /* If multivector TSS is enabled, vector 0 does not handle
8552 * tx interrupts. Don't allocate any resources for it.
8554 if (tg3_flag(tp, ENABLE_TSS))
8557 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8558 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8559 TG3_TX_RING_SIZE, GFP_KERNEL);
8560 if (!tnapi->tx_buffers)
8563 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8565 &tnapi->tx_desc_mapping,
8567 if (!tnapi->tx_ring)
8574 tg3_mem_tx_release(tp);
8578 static void tg3_mem_rx_release(struct tg3 *tp)
8582 for (i = 0; i < tp->irq_max; i++) {
8583 struct tg3_napi *tnapi = &tp->napi[i];
8585 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8590 dma_free_coherent(&tp->pdev->dev,
8591 TG3_RX_RCB_RING_BYTES(tp),
8593 tnapi->rx_rcb_mapping);
8594 tnapi->rx_rcb = NULL;
8598 static int tg3_mem_rx_acquire(struct tg3 *tp)
8600 unsigned int i, limit;
8602 limit = tp->rxq_cnt;
8604 /* If RSS is enabled, we need a (dummy) producer ring
8605 * set on vector zero. This is the true hw prodring.
8607 if (tg3_flag(tp, ENABLE_RSS))
8610 for (i = 0; i < limit; i++) {
8611 struct tg3_napi *tnapi = &tp->napi[i];
8613 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8616 /* If multivector RSS is enabled, vector 0
8617 * does not handle rx or tx interrupts.
8618 * Don't allocate any resources for it.
8620 if (!i && tg3_flag(tp, ENABLE_RSS))
8623 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8624 TG3_RX_RCB_RING_BYTES(tp),
8625 &tnapi->rx_rcb_mapping,
8634 tg3_mem_rx_release(tp);
8639 * Must not be invoked with interrupt sources disabled and
8640 * the hardware shutdown down.
8642 static void tg3_free_consistent(struct tg3 *tp)
8646 for (i = 0; i < tp->irq_cnt; i++) {
8647 struct tg3_napi *tnapi = &tp->napi[i];
8649 if (tnapi->hw_status) {
8650 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8652 tnapi->status_mapping);
8653 tnapi->hw_status = NULL;
8657 tg3_mem_rx_release(tp);
8658 tg3_mem_tx_release(tp);
8661 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8662 tp->hw_stats, tp->stats_mapping);
8663 tp->hw_stats = NULL;
8668 * Must not be invoked with interrupt sources disabled and
8669 * the hardware shutdown down. Can sleep.
8671 static int tg3_alloc_consistent(struct tg3 *tp)
8675 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8676 sizeof(struct tg3_hw_stats),
8677 &tp->stats_mapping, GFP_KERNEL);
8681 for (i = 0; i < tp->irq_cnt; i++) {
8682 struct tg3_napi *tnapi = &tp->napi[i];
8683 struct tg3_hw_status *sblk;
8685 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8687 &tnapi->status_mapping,
8689 if (!tnapi->hw_status)
8692 sblk = tnapi->hw_status;
8694 if (tg3_flag(tp, ENABLE_RSS)) {
8695 u16 *prodptr = NULL;
8698 * When RSS is enabled, the status block format changes
8699 * slightly. The "rx_jumbo_consumer", "reserved",
8700 * and "rx_mini_consumer" members get mapped to the
8701 * other three rx return ring producer indexes.
8705 prodptr = &sblk->idx[0].rx_producer;
8708 prodptr = &sblk->rx_jumbo_consumer;
8711 prodptr = &sblk->reserved;
8714 prodptr = &sblk->rx_mini_consumer;
8717 tnapi->rx_rcb_prod_idx = prodptr;
8719 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8723 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8729 tg3_free_consistent(tp);
8733 #define MAX_WAIT_CNT 1000
8735 /* To stop a block, clear the enable bit and poll till it
8736 * clears. tp->lock is held.
8738 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8743 if (tg3_flag(tp, 5705_PLUS)) {
8750 /* We can't enable/disable these bits of the
8751 * 5705/5750, just say success.
8764 for (i = 0; i < MAX_WAIT_CNT; i++) {
8765 if (pci_channel_offline(tp->pdev)) {
8766 dev_err(&tp->pdev->dev,
8767 "tg3_stop_block device offline, "
8768 "ofs=%lx enable_bit=%x\n",
8775 if ((val & enable_bit) == 0)
8779 if (i == MAX_WAIT_CNT && !silent) {
8780 dev_err(&tp->pdev->dev,
8781 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8789 /* tp->lock is held. */
8790 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8794 tg3_disable_ints(tp);
8796 if (pci_channel_offline(tp->pdev)) {
8797 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8798 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8803 tp->rx_mode &= ~RX_MODE_ENABLE;
8804 tw32_f(MAC_RX_MODE, tp->rx_mode);
8807 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8808 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8809 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8810 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8811 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8812 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8814 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8815 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8816 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8817 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8818 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8819 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8820 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8822 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8823 tw32_f(MAC_MODE, tp->mac_mode);
8826 tp->tx_mode &= ~TX_MODE_ENABLE;
8827 tw32_f(MAC_TX_MODE, tp->tx_mode);
8829 for (i = 0; i < MAX_WAIT_CNT; i++) {
8831 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8834 if (i >= MAX_WAIT_CNT) {
8835 dev_err(&tp->pdev->dev,
8836 "%s timed out, TX_MODE_ENABLE will not clear "
8837 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8841 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8843 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8845 tw32(FTQ_RESET, 0xffffffff);
8846 tw32(FTQ_RESET, 0x00000000);
8848 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8849 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8852 for (i = 0; i < tp->irq_cnt; i++) {
8853 struct tg3_napi *tnapi = &tp->napi[i];
8854 if (tnapi->hw_status)
8855 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8861 /* Save PCI command register before chip reset */
8862 static void tg3_save_pci_state(struct tg3 *tp)
8864 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8867 /* Restore PCI state after chip reset */
8868 static void tg3_restore_pci_state(struct tg3 *tp)
8872 /* Re-enable indirect register accesses. */
8873 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8874 tp->misc_host_ctrl);
8876 /* Set MAX PCI retry to zero. */
8877 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8878 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8879 tg3_flag(tp, PCIX_MODE))
8880 val |= PCISTATE_RETRY_SAME_DMA;
8881 /* Allow reads and writes to the APE register and memory space. */
8882 if (tg3_flag(tp, ENABLE_APE))
8883 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8884 PCISTATE_ALLOW_APE_SHMEM_WR |
8885 PCISTATE_ALLOW_APE_PSPACE_WR;
8886 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8888 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8890 if (!tg3_flag(tp, PCI_EXPRESS)) {
8891 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8892 tp->pci_cacheline_sz);
8893 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8897 /* Make sure PCI-X relaxed ordering bit is clear. */
8898 if (tg3_flag(tp, PCIX_MODE)) {
8901 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8903 pcix_cmd &= ~PCI_X_CMD_ERO;
8904 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8908 if (tg3_flag(tp, 5780_CLASS)) {
8910 /* Chip reset on 5780 will reset MSI enable bit,
8911 * so need to restore it.
8913 if (tg3_flag(tp, USING_MSI)) {
8916 pci_read_config_word(tp->pdev,
8917 tp->msi_cap + PCI_MSI_FLAGS,
8919 pci_write_config_word(tp->pdev,
8920 tp->msi_cap + PCI_MSI_FLAGS,
8921 ctrl | PCI_MSI_FLAGS_ENABLE);
8922 val = tr32(MSGINT_MODE);
8923 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8928 /* tp->lock is held. */
8929 static int tg3_chip_reset(struct tg3 *tp)
8932 void (*write_op)(struct tg3 *, u32, u32);
8937 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8939 /* No matching tg3_nvram_unlock() after this because
8940 * chip reset below will undo the nvram lock.
8942 tp->nvram_lock_cnt = 0;
8944 /* GRC_MISC_CFG core clock reset will clear the memory
8945 * enable bit in PCI register 4 and the MSI enable bit
8946 * on some chips, so we save relevant registers here.
8948 tg3_save_pci_state(tp);
8950 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
8951 tg3_flag(tp, 5755_PLUS))
8952 tw32(GRC_FASTBOOT_PC, 0);
8955 * We must avoid the readl() that normally takes place.
8956 * It locks machines, causes machine checks, and other
8957 * fun things. So, temporarily disable the 5701
8958 * hardware workaround, while we do the reset.
8960 write_op = tp->write32;
8961 if (write_op == tg3_write_flush_reg32)
8962 tp->write32 = tg3_write32;
8964 /* Prevent the irq handler from reading or writing PCI registers
8965 * during chip reset when the memory enable bit in the PCI command
8966 * register may be cleared. The chip does not generate interrupt
8967 * at this time, but the irq handler may still be called due to irq
8968 * sharing or irqpoll.
8970 tg3_flag_set(tp, CHIP_RESETTING);
8971 for (i = 0; i < tp->irq_cnt; i++) {
8972 struct tg3_napi *tnapi = &tp->napi[i];
8973 if (tnapi->hw_status) {
8974 tnapi->hw_status->status = 0;
8975 tnapi->hw_status->status_tag = 0;
8977 tnapi->last_tag = 0;
8978 tnapi->last_irq_tag = 0;
8982 for (i = 0; i < tp->irq_cnt; i++)
8983 synchronize_irq(tp->napi[i].irq_vec);
8985 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
8986 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8987 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8991 val = GRC_MISC_CFG_CORECLK_RESET;
8993 if (tg3_flag(tp, PCI_EXPRESS)) {
8994 /* Force PCIe 1.0a mode */
8995 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
8996 !tg3_flag(tp, 57765_PLUS) &&
8997 tr32(TG3_PCIE_PHY_TSTCTL) ==
8998 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8999 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9001 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9002 tw32(GRC_MISC_CFG, (1 << 29));
9007 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9008 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9009 tw32(GRC_VCPU_EXT_CTRL,
9010 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9013 /* Manage gphy power for all CPMU absent PCIe devices. */
9014 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9015 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9017 tw32(GRC_MISC_CFG, val);
9019 /* restore 5701 hardware bug workaround write method */
9020 tp->write32 = write_op;
9022 /* Unfortunately, we have to delay before the PCI read back.
9023 * Some 575X chips even will not respond to a PCI cfg access
9024 * when the reset command is given to the chip.
9026 * How do these hardware designers expect things to work
9027 * properly if the PCI write is posted for a long period
9028 * of time? It is always necessary to have some method by
9029 * which a register read back can occur to push the write
9030 * out which does the reset.
9032 * For most tg3 variants the trick below was working.
9037 /* Flush PCI posted writes. The normal MMIO registers
9038 * are inaccessible at this time so this is the only
9039 * way to make this reliably (actually, this is no longer
9040 * the case, see above). I tried to use indirect
9041 * register read/write but this upset some 5701 variants.
9043 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9047 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9050 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9054 /* Wait for link training to complete. */
9055 for (j = 0; j < 5000; j++)
9058 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9059 pci_write_config_dword(tp->pdev, 0xc4,
9060 cfg_val | (1 << 15));
9063 /* Clear the "no snoop" and "relaxed ordering" bits. */
9064 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9066 * Older PCIe devices only support the 128 byte
9067 * MPS setting. Enforce the restriction.
9069 if (!tg3_flag(tp, CPMU_PRESENT))
9070 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9071 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9073 /* Clear error status */
9074 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9075 PCI_EXP_DEVSTA_CED |
9076 PCI_EXP_DEVSTA_NFED |
9077 PCI_EXP_DEVSTA_FED |
9078 PCI_EXP_DEVSTA_URD);
9081 tg3_restore_pci_state(tp);
9083 tg3_flag_clear(tp, CHIP_RESETTING);
9084 tg3_flag_clear(tp, ERROR_PROCESSED);
9087 if (tg3_flag(tp, 5780_CLASS))
9088 val = tr32(MEMARB_MODE);
9089 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9091 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9093 tw32(0x5000, 0x400);
9096 if (tg3_flag(tp, IS_SSB_CORE)) {
9098 * BCM4785: In order to avoid repercussions from using
9099 * potentially defective internal ROM, stop the Rx RISC CPU,
9100 * which is not required.
9103 tg3_halt_cpu(tp, RX_CPU_BASE);
9106 err = tg3_poll_fw(tp);
9110 tw32(GRC_MODE, tp->grc_mode);
9112 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9115 tw32(0xc4, val | (1 << 15));
9118 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9119 tg3_asic_rev(tp) == ASIC_REV_5705) {
9120 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9121 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9122 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9123 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9126 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9127 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9129 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9130 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9135 tw32_f(MAC_MODE, val);
9138 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9142 if (tg3_flag(tp, PCI_EXPRESS) &&
9143 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9144 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9145 !tg3_flag(tp, 57765_PLUS)) {
9148 tw32(0x7c00, val | (1 << 25));
9151 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
9152 val = tr32(TG3_CPMU_CLCK_ORIDE);
9153 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9156 /* Reprobe ASF enable state. */
9157 tg3_flag_clear(tp, ENABLE_ASF);
9158 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9159 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9161 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9162 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9163 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9166 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9167 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9168 tg3_flag_set(tp, ENABLE_ASF);
9169 tp->last_event_jiffies = jiffies;
9170 if (tg3_flag(tp, 5750_PLUS))
9171 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9173 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9174 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9175 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9176 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9177 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9184 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9185 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9187 /* tp->lock is held. */
9188 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9194 tg3_write_sig_pre_reset(tp, kind);
9196 tg3_abort_hw(tp, silent);
9197 err = tg3_chip_reset(tp);
9199 __tg3_set_mac_addr(tp, false);
9201 tg3_write_sig_legacy(tp, kind);
9202 tg3_write_sig_post_reset(tp, kind);
9205 /* Save the stats across chip resets... */
9206 tg3_get_nstats(tp, &tp->net_stats_prev);
9207 tg3_get_estats(tp, &tp->estats_prev);
9209 /* And make sure the next sample is new data */
9210 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9216 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9218 struct tg3 *tp = netdev_priv(dev);
9219 struct sockaddr *addr = p;
9221 bool skip_mac_1 = false;
9223 if (!is_valid_ether_addr(addr->sa_data))
9224 return -EADDRNOTAVAIL;
9226 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9228 if (!netif_running(dev))
9231 if (tg3_flag(tp, ENABLE_ASF)) {
9232 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9234 addr0_high = tr32(MAC_ADDR_0_HIGH);
9235 addr0_low = tr32(MAC_ADDR_0_LOW);
9236 addr1_high = tr32(MAC_ADDR_1_HIGH);
9237 addr1_low = tr32(MAC_ADDR_1_LOW);
9239 /* Skip MAC addr 1 if ASF is using it. */
9240 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9241 !(addr1_high == 0 && addr1_low == 0))
9244 spin_lock_bh(&tp->lock);
9245 __tg3_set_mac_addr(tp, skip_mac_1);
9246 spin_unlock_bh(&tp->lock);
9251 /* tp->lock is held. */
9252 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9253 dma_addr_t mapping, u32 maxlen_flags,
9257 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9258 ((u64) mapping >> 32));
9260 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9261 ((u64) mapping & 0xffffffff));
9263 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9266 if (!tg3_flag(tp, 5705_PLUS))
9268 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9273 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9277 if (!tg3_flag(tp, ENABLE_TSS)) {
9278 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9279 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9280 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9282 tw32(HOSTCC_TXCOL_TICKS, 0);
9283 tw32(HOSTCC_TXMAX_FRAMES, 0);
9284 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9286 for (; i < tp->txq_cnt; i++) {
9289 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9290 tw32(reg, ec->tx_coalesce_usecs);
9291 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9292 tw32(reg, ec->tx_max_coalesced_frames);
9293 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9294 tw32(reg, ec->tx_max_coalesced_frames_irq);
9298 for (; i < tp->irq_max - 1; i++) {
9299 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9300 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9301 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9305 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9308 u32 limit = tp->rxq_cnt;
9310 if (!tg3_flag(tp, ENABLE_RSS)) {
9311 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9312 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9313 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9316 tw32(HOSTCC_RXCOL_TICKS, 0);
9317 tw32(HOSTCC_RXMAX_FRAMES, 0);
9318 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9321 for (; i < limit; i++) {
9324 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9325 tw32(reg, ec->rx_coalesce_usecs);
9326 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9327 tw32(reg, ec->rx_max_coalesced_frames);
9328 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9329 tw32(reg, ec->rx_max_coalesced_frames_irq);
9332 for (; i < tp->irq_max - 1; i++) {
9333 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9334 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9335 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9339 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9341 tg3_coal_tx_init(tp, ec);
9342 tg3_coal_rx_init(tp, ec);
9344 if (!tg3_flag(tp, 5705_PLUS)) {
9345 u32 val = ec->stats_block_coalesce_usecs;
9347 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9348 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9353 tw32(HOSTCC_STAT_COAL_TICKS, val);
9357 /* tp->lock is held. */
9358 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9362 /* Disable all transmit rings but the first. */
9363 if (!tg3_flag(tp, 5705_PLUS))
9364 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9365 else if (tg3_flag(tp, 5717_PLUS))
9366 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9367 else if (tg3_flag(tp, 57765_CLASS) ||
9368 tg3_asic_rev(tp) == ASIC_REV_5762)
9369 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9371 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9373 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9374 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9375 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9376 BDINFO_FLAGS_DISABLED);
9379 /* tp->lock is held. */
9380 static void tg3_tx_rcbs_init(struct tg3 *tp)
9383 u32 txrcb = NIC_SRAM_SEND_RCB;
9385 if (tg3_flag(tp, ENABLE_TSS))
9388 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9389 struct tg3_napi *tnapi = &tp->napi[i];
9391 if (!tnapi->tx_ring)
9394 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9395 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9396 NIC_SRAM_TX_BUFFER_DESC);
9400 /* tp->lock is held. */
9401 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9405 /* Disable all receive return rings but the first. */
9406 if (tg3_flag(tp, 5717_PLUS))
9407 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9408 else if (!tg3_flag(tp, 5705_PLUS))
9409 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9410 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9411 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9412 tg3_flag(tp, 57765_CLASS))
9413 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9415 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9417 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9418 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9419 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9420 BDINFO_FLAGS_DISABLED);
9423 /* tp->lock is held. */
9424 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9427 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9429 if (tg3_flag(tp, ENABLE_RSS))
9432 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9433 struct tg3_napi *tnapi = &tp->napi[i];
9438 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9439 (tp->rx_ret_ring_mask + 1) <<
9440 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9444 /* tp->lock is held. */
9445 static void tg3_rings_reset(struct tg3 *tp)
9449 struct tg3_napi *tnapi = &tp->napi[0];
9451 tg3_tx_rcbs_disable(tp);
9453 tg3_rx_ret_rcbs_disable(tp);
9455 /* Disable interrupts */
9456 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9457 tp->napi[0].chk_msi_cnt = 0;
9458 tp->napi[0].last_rx_cons = 0;
9459 tp->napi[0].last_tx_cons = 0;
9461 /* Zero mailbox registers. */
9462 if (tg3_flag(tp, SUPPORT_MSIX)) {
9463 for (i = 1; i < tp->irq_max; i++) {
9464 tp->napi[i].tx_prod = 0;
9465 tp->napi[i].tx_cons = 0;
9466 if (tg3_flag(tp, ENABLE_TSS))
9467 tw32_mailbox(tp->napi[i].prodmbox, 0);
9468 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9469 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9470 tp->napi[i].chk_msi_cnt = 0;
9471 tp->napi[i].last_rx_cons = 0;
9472 tp->napi[i].last_tx_cons = 0;
9474 if (!tg3_flag(tp, ENABLE_TSS))
9475 tw32_mailbox(tp->napi[0].prodmbox, 0);
9477 tp->napi[0].tx_prod = 0;
9478 tp->napi[0].tx_cons = 0;
9479 tw32_mailbox(tp->napi[0].prodmbox, 0);
9480 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9483 /* Make sure the NIC-based send BD rings are disabled. */
9484 if (!tg3_flag(tp, 5705_PLUS)) {
9485 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9486 for (i = 0; i < 16; i++)
9487 tw32_tx_mbox(mbox + i * 8, 0);
9490 /* Clear status block in ram. */
9491 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9493 /* Set status block DMA address */
9494 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9495 ((u64) tnapi->status_mapping >> 32));
9496 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9497 ((u64) tnapi->status_mapping & 0xffffffff));
9499 stblk = HOSTCC_STATBLCK_RING1;
9501 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9502 u64 mapping = (u64)tnapi->status_mapping;
9503 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9504 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9507 /* Clear status block in ram. */
9508 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9511 tg3_tx_rcbs_init(tp);
9512 tg3_rx_ret_rcbs_init(tp);
9515 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9517 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9519 if (!tg3_flag(tp, 5750_PLUS) ||
9520 tg3_flag(tp, 5780_CLASS) ||
9521 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9522 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9523 tg3_flag(tp, 57765_PLUS))
9524 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9525 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9526 tg3_asic_rev(tp) == ASIC_REV_5787)
9527 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9529 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9531 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9532 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9534 val = min(nic_rep_thresh, host_rep_thresh);
9535 tw32(RCVBDI_STD_THRESH, val);
9537 if (tg3_flag(tp, 57765_PLUS))
9538 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9540 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9543 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9545 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9547 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9548 tw32(RCVBDI_JUMBO_THRESH, val);
9550 if (tg3_flag(tp, 57765_PLUS))
9551 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9554 static inline u32 calc_crc(unsigned char *buf, int len)
9562 for (j = 0; j < len; j++) {
9565 for (k = 0; k < 8; k++) {
9578 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9580 /* accept or reject all multicast frames */
9581 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9582 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9583 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9584 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9587 static void __tg3_set_rx_mode(struct net_device *dev)
9589 struct tg3 *tp = netdev_priv(dev);
9592 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9593 RX_MODE_KEEP_VLAN_TAG);
9595 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9596 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9599 if (!tg3_flag(tp, ENABLE_ASF))
9600 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9603 if (dev->flags & IFF_PROMISC) {
9604 /* Promiscuous mode. */
9605 rx_mode |= RX_MODE_PROMISC;
9606 } else if (dev->flags & IFF_ALLMULTI) {
9607 /* Accept all multicast. */
9608 tg3_set_multi(tp, 1);
9609 } else if (netdev_mc_empty(dev)) {
9610 /* Reject all multicast. */
9611 tg3_set_multi(tp, 0);
9613 /* Accept one or more multicast(s). */
9614 struct netdev_hw_addr *ha;
9615 u32 mc_filter[4] = { 0, };
9620 netdev_for_each_mc_addr(ha, dev) {
9621 crc = calc_crc(ha->addr, ETH_ALEN);
9623 regidx = (bit & 0x60) >> 5;
9625 mc_filter[regidx] |= (1 << bit);
9628 tw32(MAC_HASH_REG_0, mc_filter[0]);
9629 tw32(MAC_HASH_REG_1, mc_filter[1]);
9630 tw32(MAC_HASH_REG_2, mc_filter[2]);
9631 tw32(MAC_HASH_REG_3, mc_filter[3]);
9634 if (rx_mode != tp->rx_mode) {
9635 tp->rx_mode = rx_mode;
9636 tw32_f(MAC_RX_MODE, rx_mode);
9641 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9645 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9646 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9649 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9653 if (!tg3_flag(tp, SUPPORT_MSIX))
9656 if (tp->rxq_cnt == 1) {
9657 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9661 /* Validate table against current IRQ count */
9662 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9663 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9667 if (i != TG3_RSS_INDIR_TBL_SIZE)
9668 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9671 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9674 u32 reg = MAC_RSS_INDIR_TBL_0;
9676 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9677 u32 val = tp->rss_ind_tbl[i];
9679 for (; i % 8; i++) {
9681 val |= tp->rss_ind_tbl[i];
9688 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9690 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9691 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9693 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9696 /* tp->lock is held. */
9697 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9699 u32 val, rdmac_mode;
9701 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9703 tg3_disable_ints(tp);
9707 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9709 if (tg3_flag(tp, INIT_COMPLETE))
9710 tg3_abort_hw(tp, 1);
9712 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9713 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9714 tg3_phy_pull_config(tp);
9715 tg3_eee_pull_config(tp, NULL);
9716 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9719 /* Enable MAC control of LPI */
9720 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9726 err = tg3_chip_reset(tp);
9730 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9732 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9733 val = tr32(TG3_CPMU_CTRL);
9734 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9735 tw32(TG3_CPMU_CTRL, val);
9737 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9738 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9739 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9740 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9742 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9743 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9744 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9745 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9747 val = tr32(TG3_CPMU_HST_ACC);
9748 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9749 val |= CPMU_HST_ACC_MACCLK_6_25;
9750 tw32(TG3_CPMU_HST_ACC, val);
9753 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9754 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9755 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9756 PCIE_PWR_MGMT_L1_THRESH_4MS;
9757 tw32(PCIE_PWR_MGMT_THRESH, val);
9759 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9760 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9762 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9764 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9765 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9768 if (tg3_flag(tp, L1PLLPD_EN)) {
9769 u32 grc_mode = tr32(GRC_MODE);
9771 /* Access the lower 1K of PL PCIE block registers. */
9772 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9773 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9775 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9776 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9777 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9779 tw32(GRC_MODE, grc_mode);
9782 if (tg3_flag(tp, 57765_CLASS)) {
9783 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9784 u32 grc_mode = tr32(GRC_MODE);
9786 /* Access the lower 1K of PL PCIE block registers. */
9787 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9788 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9790 val = tr32(TG3_PCIE_TLDLPL_PORT +
9791 TG3_PCIE_PL_LO_PHYCTL5);
9792 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9793 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9795 tw32(GRC_MODE, grc_mode);
9798 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9801 /* Fix transmit hangs */
9802 val = tr32(TG3_CPMU_PADRNG_CTL);
9803 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9804 tw32(TG3_CPMU_PADRNG_CTL, val);
9806 grc_mode = tr32(GRC_MODE);
9808 /* Access the lower 1K of DL PCIE block registers. */
9809 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9810 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9812 val = tr32(TG3_PCIE_TLDLPL_PORT +
9813 TG3_PCIE_DL_LO_FTSMAX);
9814 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9815 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9816 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9818 tw32(GRC_MODE, grc_mode);
9821 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9822 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9823 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9824 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9827 /* This works around an issue with Athlon chipsets on
9828 * B3 tigon3 silicon. This bit has no effect on any
9829 * other revision. But do not set this on PCI Express
9830 * chips and don't even touch the clocks if the CPMU is present.
9832 if (!tg3_flag(tp, CPMU_PRESENT)) {
9833 if (!tg3_flag(tp, PCI_EXPRESS))
9834 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9835 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9838 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9839 tg3_flag(tp, PCIX_MODE)) {
9840 val = tr32(TG3PCI_PCISTATE);
9841 val |= PCISTATE_RETRY_SAME_DMA;
9842 tw32(TG3PCI_PCISTATE, val);
9845 if (tg3_flag(tp, ENABLE_APE)) {
9846 /* Allow reads and writes to the
9847 * APE register and memory space.
9849 val = tr32(TG3PCI_PCISTATE);
9850 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9851 PCISTATE_ALLOW_APE_SHMEM_WR |
9852 PCISTATE_ALLOW_APE_PSPACE_WR;
9853 tw32(TG3PCI_PCISTATE, val);
9856 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9857 /* Enable some hw fixes. */
9858 val = tr32(TG3PCI_MSI_DATA);
9859 val |= (1 << 26) | (1 << 28) | (1 << 29);
9860 tw32(TG3PCI_MSI_DATA, val);
9863 /* Descriptor ring init may make accesses to the
9864 * NIC SRAM area to setup the TX descriptors, so we
9865 * can only do this after the hardware has been
9866 * successfully reset.
9868 err = tg3_init_rings(tp);
9872 if (tg3_flag(tp, 57765_PLUS)) {
9873 val = tr32(TG3PCI_DMA_RW_CTRL) &
9874 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9875 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9876 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9877 if (!tg3_flag(tp, 57765_CLASS) &&
9878 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9879 tg3_asic_rev(tp) != ASIC_REV_5762)
9880 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9881 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9882 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9883 tg3_asic_rev(tp) != ASIC_REV_5761) {
9884 /* This value is determined during the probe time DMA
9885 * engine test, tg3_test_dma.
9887 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9890 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9891 GRC_MODE_4X_NIC_SEND_RINGS |
9892 GRC_MODE_NO_TX_PHDR_CSUM |
9893 GRC_MODE_NO_RX_PHDR_CSUM);
9894 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9896 /* Pseudo-header checksum is done by hardware logic and not
9897 * the offload processers, so make the chip do the pseudo-
9898 * header checksums on receive. For transmit it is more
9899 * convenient to do the pseudo-header checksum in software
9900 * as Linux does that on transmit for us in all cases.
9902 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9904 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9906 tw32(TG3_RX_PTP_CTL,
9907 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9909 if (tg3_flag(tp, PTP_CAPABLE))
9910 val |= GRC_MODE_TIME_SYNC_ENABLE;
9912 tw32(GRC_MODE, tp->grc_mode | val);
9914 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9915 val = tr32(GRC_MISC_CFG);
9917 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9918 tw32(GRC_MISC_CFG, val);
9920 /* Initialize MBUF/DESC pool. */
9921 if (tg3_flag(tp, 5750_PLUS)) {
9923 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
9924 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
9925 if (tg3_asic_rev(tp) == ASIC_REV_5704)
9926 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9928 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9929 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9930 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
9931 } else if (tg3_flag(tp, TSO_CAPABLE)) {
9934 fw_len = tp->fw_len;
9935 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9936 tw32(BUFMGR_MB_POOL_ADDR,
9937 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9938 tw32(BUFMGR_MB_POOL_SIZE,
9939 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9942 if (tp->dev->mtu <= ETH_DATA_LEN) {
9943 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9944 tp->bufmgr_config.mbuf_read_dma_low_water);
9945 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9946 tp->bufmgr_config.mbuf_mac_rx_low_water);
9947 tw32(BUFMGR_MB_HIGH_WATER,
9948 tp->bufmgr_config.mbuf_high_water);
9950 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9951 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9952 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9953 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9954 tw32(BUFMGR_MB_HIGH_WATER,
9955 tp->bufmgr_config.mbuf_high_water_jumbo);
9957 tw32(BUFMGR_DMA_LOW_WATER,
9958 tp->bufmgr_config.dma_low_water);
9959 tw32(BUFMGR_DMA_HIGH_WATER,
9960 tp->bufmgr_config.dma_high_water);
9962 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
9963 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9964 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
9965 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9966 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9967 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
9968 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
9969 tw32(BUFMGR_MODE, val);
9970 for (i = 0; i < 2000; i++) {
9971 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9976 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
9980 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
9981 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
9983 tg3_setup_rxbd_thresholds(tp);
9985 /* Initialize TG3_BDINFO's at:
9986 * RCVDBDI_STD_BD: standard eth size rx ring
9987 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9988 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9991 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9992 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9993 * ring attribute flags
9994 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9996 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9997 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9999 * The size of each ring is fixed in the firmware, but the location is
10002 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10003 ((u64) tpr->rx_std_mapping >> 32));
10004 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10005 ((u64) tpr->rx_std_mapping & 0xffffffff));
10006 if (!tg3_flag(tp, 5717_PLUS))
10007 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10008 NIC_SRAM_RX_BUFFER_DESC);
10010 /* Disable the mini ring */
10011 if (!tg3_flag(tp, 5705_PLUS))
10012 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10013 BDINFO_FLAGS_DISABLED);
10015 /* Program the jumbo buffer descriptor ring control
10016 * blocks on those devices that have them.
10018 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10019 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10021 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10022 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10023 ((u64) tpr->rx_jmb_mapping >> 32));
10024 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10025 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10026 val = TG3_RX_JMB_RING_SIZE(tp) <<
10027 BDINFO_FLAGS_MAXLEN_SHIFT;
10028 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10029 val | BDINFO_FLAGS_USE_EXT_RECV);
10030 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10031 tg3_flag(tp, 57765_CLASS) ||
10032 tg3_asic_rev(tp) == ASIC_REV_5762)
10033 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10034 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10036 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10037 BDINFO_FLAGS_DISABLED);
10040 if (tg3_flag(tp, 57765_PLUS)) {
10041 val = TG3_RX_STD_RING_SIZE(tp);
10042 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10043 val |= (TG3_RX_STD_DMA_SZ << 2);
10045 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10047 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10049 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10051 tpr->rx_std_prod_idx = tp->rx_pending;
10052 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10054 tpr->rx_jmb_prod_idx =
10055 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10056 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10058 tg3_rings_reset(tp);
10060 /* Initialize MAC address and backoff seed. */
10061 __tg3_set_mac_addr(tp, false);
10063 /* MTU + ethernet header + FCS + optional VLAN tag */
10064 tw32(MAC_RX_MTU_SIZE,
10065 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10067 /* The slot time is changed by tg3_setup_phy if we
10068 * run at gigabit with half duplex.
10070 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10071 (6 << TX_LENGTHS_IPG_SHIFT) |
10072 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10074 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10075 tg3_asic_rev(tp) == ASIC_REV_5762)
10076 val |= tr32(MAC_TX_LENGTHS) &
10077 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10078 TX_LENGTHS_CNT_DWN_VAL_MSK);
10080 tw32(MAC_TX_LENGTHS, val);
10082 /* Receive rules. */
10083 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10084 tw32(RCVLPC_CONFIG, 0x0181);
10086 /* Calculate RDMAC_MODE setting early, we need it to determine
10087 * the RCVLPC_STATE_ENABLE mask.
10089 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10090 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10091 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10092 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10093 RDMAC_MODE_LNGREAD_ENAB);
10095 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10096 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10098 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10099 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10100 tg3_asic_rev(tp) == ASIC_REV_57780)
10101 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10102 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10103 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10105 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10106 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10107 if (tg3_flag(tp, TSO_CAPABLE) &&
10108 tg3_asic_rev(tp) == ASIC_REV_5705) {
10109 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10110 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10111 !tg3_flag(tp, IS_5788)) {
10112 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10116 if (tg3_flag(tp, PCI_EXPRESS))
10117 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10119 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10121 if (tp->dev->mtu <= ETH_DATA_LEN) {
10122 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10123 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10127 if (tg3_flag(tp, HW_TSO_1) ||
10128 tg3_flag(tp, HW_TSO_2) ||
10129 tg3_flag(tp, HW_TSO_3))
10130 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10132 if (tg3_flag(tp, 57765_PLUS) ||
10133 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10134 tg3_asic_rev(tp) == ASIC_REV_57780)
10135 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10137 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10138 tg3_asic_rev(tp) == ASIC_REV_5762)
10139 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10141 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10142 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10143 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10144 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10145 tg3_flag(tp, 57765_PLUS)) {
10148 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10149 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10151 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10153 val = tr32(tgtreg);
10154 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10155 tg3_asic_rev(tp) == ASIC_REV_5762) {
10156 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10157 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10158 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10159 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10160 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10161 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10163 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10166 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10167 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10168 tg3_asic_rev(tp) == ASIC_REV_5762) {
10171 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10172 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10174 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10176 val = tr32(tgtreg);
10178 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10179 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10182 /* Receive/send statistics. */
10183 if (tg3_flag(tp, 5750_PLUS)) {
10184 val = tr32(RCVLPC_STATS_ENABLE);
10185 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10186 tw32(RCVLPC_STATS_ENABLE, val);
10187 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10188 tg3_flag(tp, TSO_CAPABLE)) {
10189 val = tr32(RCVLPC_STATS_ENABLE);
10190 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10191 tw32(RCVLPC_STATS_ENABLE, val);
10193 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10195 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10196 tw32(SNDDATAI_STATSENAB, 0xffffff);
10197 tw32(SNDDATAI_STATSCTRL,
10198 (SNDDATAI_SCTRL_ENABLE |
10199 SNDDATAI_SCTRL_FASTUPD));
10201 /* Setup host coalescing engine. */
10202 tw32(HOSTCC_MODE, 0);
10203 for (i = 0; i < 2000; i++) {
10204 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10209 __tg3_set_coalesce(tp, &tp->coal);
10211 if (!tg3_flag(tp, 5705_PLUS)) {
10212 /* Status/statistics block address. See tg3_timer,
10213 * the tg3_periodic_fetch_stats call there, and
10214 * tg3_get_stats to see how this works for 5705/5750 chips.
10216 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10217 ((u64) tp->stats_mapping >> 32));
10218 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10219 ((u64) tp->stats_mapping & 0xffffffff));
10220 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10222 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10224 /* Clear statistics and status block memory areas */
10225 for (i = NIC_SRAM_STATS_BLK;
10226 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10227 i += sizeof(u32)) {
10228 tg3_write_mem(tp, i, 0);
10233 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10235 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10236 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10237 if (!tg3_flag(tp, 5705_PLUS))
10238 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10240 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10241 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10242 /* reset to prevent losing 1st rx packet intermittently */
10243 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10247 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10248 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10249 MAC_MODE_FHDE_ENABLE;
10250 if (tg3_flag(tp, ENABLE_APE))
10251 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10252 if (!tg3_flag(tp, 5705_PLUS) &&
10253 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10254 tg3_asic_rev(tp) != ASIC_REV_5700)
10255 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10256 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10259 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10260 * If TG3_FLAG_IS_NIC is zero, we should read the
10261 * register to preserve the GPIO settings for LOMs. The GPIOs,
10262 * whether used as inputs or outputs, are set by boot code after
10265 if (!tg3_flag(tp, IS_NIC)) {
10268 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10269 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10270 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10272 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10273 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10274 GRC_LCLCTRL_GPIO_OUTPUT3;
10276 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10277 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10279 tp->grc_local_ctrl &= ~gpio_mask;
10280 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10282 /* GPIO1 must be driven high for eeprom write protect */
10283 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10284 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10285 GRC_LCLCTRL_GPIO_OUTPUT1);
10287 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10290 if (tg3_flag(tp, USING_MSIX)) {
10291 val = tr32(MSGINT_MODE);
10292 val |= MSGINT_MODE_ENABLE;
10293 if (tp->irq_cnt > 1)
10294 val |= MSGINT_MODE_MULTIVEC_EN;
10295 if (!tg3_flag(tp, 1SHOT_MSI))
10296 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10297 tw32(MSGINT_MODE, val);
10300 if (!tg3_flag(tp, 5705_PLUS)) {
10301 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10305 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10306 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10307 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10308 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10309 WDMAC_MODE_LNGREAD_ENAB);
10311 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10312 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10313 if (tg3_flag(tp, TSO_CAPABLE) &&
10314 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10315 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10317 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10318 !tg3_flag(tp, IS_5788)) {
10319 val |= WDMAC_MODE_RX_ACCEL;
10323 /* Enable host coalescing bug fix */
10324 if (tg3_flag(tp, 5755_PLUS))
10325 val |= WDMAC_MODE_STATUS_TAG_FIX;
10327 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10328 val |= WDMAC_MODE_BURST_ALL_DATA;
10330 tw32_f(WDMAC_MODE, val);
10333 if (tg3_flag(tp, PCIX_MODE)) {
10336 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10338 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10339 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10340 pcix_cmd |= PCI_X_CMD_READ_2K;
10341 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10342 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10343 pcix_cmd |= PCI_X_CMD_READ_2K;
10345 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10349 tw32_f(RDMAC_MODE, rdmac_mode);
10352 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10353 tg3_asic_rev(tp) == ASIC_REV_5720) {
10354 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10355 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10358 if (i < TG3_NUM_RDMA_CHANNELS) {
10359 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10360 val |= tg3_lso_rd_dma_workaround_bit(tp);
10361 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10362 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10366 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10367 if (!tg3_flag(tp, 5705_PLUS))
10368 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10370 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10371 tw32(SNDDATAC_MODE,
10372 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10374 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10376 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10377 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10378 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10379 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10380 val |= RCVDBDI_MODE_LRG_RING_SZ;
10381 tw32(RCVDBDI_MODE, val);
10382 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10383 if (tg3_flag(tp, HW_TSO_1) ||
10384 tg3_flag(tp, HW_TSO_2) ||
10385 tg3_flag(tp, HW_TSO_3))
10386 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10387 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10388 if (tg3_flag(tp, ENABLE_TSS))
10389 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10390 tw32(SNDBDI_MODE, val);
10391 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10393 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10394 err = tg3_load_5701_a0_firmware_fix(tp);
10399 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10400 /* Ignore any errors for the firmware download. If download
10401 * fails, the device will operate with EEE disabled
10403 tg3_load_57766_firmware(tp);
10406 if (tg3_flag(tp, TSO_CAPABLE)) {
10407 err = tg3_load_tso_firmware(tp);
10412 tp->tx_mode = TX_MODE_ENABLE;
10414 if (tg3_flag(tp, 5755_PLUS) ||
10415 tg3_asic_rev(tp) == ASIC_REV_5906)
10416 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10418 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10419 tg3_asic_rev(tp) == ASIC_REV_5762) {
10420 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10421 tp->tx_mode &= ~val;
10422 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10425 tw32_f(MAC_TX_MODE, tp->tx_mode);
10428 if (tg3_flag(tp, ENABLE_RSS)) {
10429 tg3_rss_write_indir_tbl(tp);
10431 /* Setup the "secret" hash key. */
10432 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10433 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10434 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10435 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10436 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10437 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10438 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10439 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10440 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10441 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10444 tp->rx_mode = RX_MODE_ENABLE;
10445 if (tg3_flag(tp, 5755_PLUS))
10446 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10448 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10449 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10451 if (tg3_flag(tp, ENABLE_RSS))
10452 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10453 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10454 RX_MODE_RSS_IPV6_HASH_EN |
10455 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10456 RX_MODE_RSS_IPV4_HASH_EN |
10457 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10459 tw32_f(MAC_RX_MODE, tp->rx_mode);
10462 tw32(MAC_LED_CTRL, tp->led_ctrl);
10464 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10465 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10466 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10469 tw32_f(MAC_RX_MODE, tp->rx_mode);
10472 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10473 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10474 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10475 /* Set drive transmission level to 1.2V */
10476 /* only if the signal pre-emphasis bit is not set */
10477 val = tr32(MAC_SERDES_CFG);
10480 tw32(MAC_SERDES_CFG, val);
10482 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10483 tw32(MAC_SERDES_CFG, 0x616000);
10486 /* Prevent chip from dropping frames when flow control
10489 if (tg3_flag(tp, 57765_CLASS))
10493 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10495 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10496 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10497 /* Use hardware link auto-negotiation */
10498 tg3_flag_set(tp, HW_AUTONEG);
10501 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10502 tg3_asic_rev(tp) == ASIC_REV_5714) {
10505 tmp = tr32(SERDES_RX_CTRL);
10506 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10507 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10508 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10509 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10512 if (!tg3_flag(tp, USE_PHYLIB)) {
10513 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10514 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10516 err = tg3_setup_phy(tp, false);
10520 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10521 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10524 /* Clear CRC stats. */
10525 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10526 tg3_writephy(tp, MII_TG3_TEST1,
10527 tmp | MII_TG3_TEST1_CRC_EN);
10528 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10533 __tg3_set_rx_mode(tp->dev);
10535 /* Initialize receive rules. */
10536 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10537 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10538 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10539 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10541 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10545 if (tg3_flag(tp, ENABLE_ASF))
10549 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10551 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10553 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10555 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10557 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10559 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10561 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10563 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10565 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10567 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10569 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10571 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10573 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10575 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10583 if (tg3_flag(tp, ENABLE_APE))
10584 /* Write our heartbeat update interval to APE. */
10585 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10586 APE_HOST_HEARTBEAT_INT_DISABLE);
10588 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10593 /* Called at device open time to get the chip ready for
10594 * packet processing. Invoked with tp->lock held.
10596 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10598 /* Chip may have been just powered on. If so, the boot code may still
10599 * be running initialization. Wait for it to finish to avoid races in
10600 * accessing the hardware.
10602 tg3_enable_register_access(tp);
10605 tg3_switch_clocks(tp);
10607 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10609 return tg3_reset_hw(tp, reset_phy);
10612 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10616 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10617 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10619 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10622 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10623 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10624 memset(ocir, 0, TG3_OCIR_LEN);
10628 /* sysfs attributes for hwmon */
10629 static ssize_t tg3_show_temp(struct device *dev,
10630 struct device_attribute *devattr, char *buf)
10632 struct pci_dev *pdev = to_pci_dev(dev);
10633 struct net_device *netdev = pci_get_drvdata(pdev);
10634 struct tg3 *tp = netdev_priv(netdev);
10635 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10638 spin_lock_bh(&tp->lock);
10639 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10640 sizeof(temperature));
10641 spin_unlock_bh(&tp->lock);
10642 return sprintf(buf, "%u\n", temperature);
10646 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10647 TG3_TEMP_SENSOR_OFFSET);
10648 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10649 TG3_TEMP_CAUTION_OFFSET);
10650 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10651 TG3_TEMP_MAX_OFFSET);
10653 static struct attribute *tg3_attributes[] = {
10654 &sensor_dev_attr_temp1_input.dev_attr.attr,
10655 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10656 &sensor_dev_attr_temp1_max.dev_attr.attr,
10660 static const struct attribute_group tg3_group = {
10661 .attrs = tg3_attributes,
10664 static void tg3_hwmon_close(struct tg3 *tp)
10666 if (tp->hwmon_dev) {
10667 hwmon_device_unregister(tp->hwmon_dev);
10668 tp->hwmon_dev = NULL;
10669 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10673 static void tg3_hwmon_open(struct tg3 *tp)
10677 struct pci_dev *pdev = tp->pdev;
10678 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10680 tg3_sd_scan_scratchpad(tp, ocirs);
10682 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10683 if (!ocirs[i].src_data_length)
10686 size += ocirs[i].src_hdr_length;
10687 size += ocirs[i].src_data_length;
10693 /* Register hwmon sysfs hooks */
10694 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10696 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10700 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10701 if (IS_ERR(tp->hwmon_dev)) {
10702 tp->hwmon_dev = NULL;
10703 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10704 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10709 #define TG3_STAT_ADD32(PSTAT, REG) \
10710 do { u32 __val = tr32(REG); \
10711 (PSTAT)->low += __val; \
10712 if ((PSTAT)->low < __val) \
10713 (PSTAT)->high += 1; \
10716 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10718 struct tg3_hw_stats *sp = tp->hw_stats;
10723 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10724 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10725 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10726 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10727 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10728 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10729 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10730 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10731 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10732 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10733 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10734 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10735 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10736 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10737 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10738 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10741 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10742 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10743 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10744 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10747 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10748 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10749 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10750 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10751 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10752 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10753 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10754 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10755 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10756 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10757 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10758 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10759 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10760 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10762 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10763 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10764 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10765 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10766 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10768 u32 val = tr32(HOSTCC_FLOW_ATTN);
10769 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10771 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10772 sp->rx_discards.low += val;
10773 if (sp->rx_discards.low < val)
10774 sp->rx_discards.high += 1;
10776 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10778 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10781 static void tg3_chk_missed_msi(struct tg3 *tp)
10785 for (i = 0; i < tp->irq_cnt; i++) {
10786 struct tg3_napi *tnapi = &tp->napi[i];
10788 if (tg3_has_work(tnapi)) {
10789 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10790 tnapi->last_tx_cons == tnapi->tx_cons) {
10791 if (tnapi->chk_msi_cnt < 1) {
10792 tnapi->chk_msi_cnt++;
10798 tnapi->chk_msi_cnt = 0;
10799 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10800 tnapi->last_tx_cons = tnapi->tx_cons;
10804 static void tg3_timer(unsigned long __opaque)
10806 struct tg3 *tp = (struct tg3 *) __opaque;
10808 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10809 goto restart_timer;
10811 spin_lock(&tp->lock);
10813 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10814 tg3_flag(tp, 57765_CLASS))
10815 tg3_chk_missed_msi(tp);
10817 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10818 /* BCM4785: Flush posted writes from GbE to host memory. */
10822 if (!tg3_flag(tp, TAGGED_STATUS)) {
10823 /* All of this garbage is because when using non-tagged
10824 * IRQ status the mailbox/status_block protocol the chip
10825 * uses with the cpu is race prone.
10827 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10828 tw32(GRC_LOCAL_CTRL,
10829 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10831 tw32(HOSTCC_MODE, tp->coalesce_mode |
10832 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10835 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10836 spin_unlock(&tp->lock);
10837 tg3_reset_task_schedule(tp);
10838 goto restart_timer;
10842 /* This part only runs once per second. */
10843 if (!--tp->timer_counter) {
10844 if (tg3_flag(tp, 5705_PLUS))
10845 tg3_periodic_fetch_stats(tp);
10847 if (tp->setlpicnt && !--tp->setlpicnt)
10848 tg3_phy_eee_enable(tp);
10850 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10854 mac_stat = tr32(MAC_STATUS);
10857 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10858 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10860 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10864 tg3_setup_phy(tp, false);
10865 } else if (tg3_flag(tp, POLL_SERDES)) {
10866 u32 mac_stat = tr32(MAC_STATUS);
10867 int need_setup = 0;
10870 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10873 if (!tp->link_up &&
10874 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10875 MAC_STATUS_SIGNAL_DET))) {
10879 if (!tp->serdes_counter) {
10882 ~MAC_MODE_PORT_MODE_MASK));
10884 tw32_f(MAC_MODE, tp->mac_mode);
10887 tg3_setup_phy(tp, false);
10889 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10890 tg3_flag(tp, 5780_CLASS)) {
10891 tg3_serdes_parallel_detect(tp);
10894 tp->timer_counter = tp->timer_multiplier;
10897 /* Heartbeat is only sent once every 2 seconds.
10899 * The heartbeat is to tell the ASF firmware that the host
10900 * driver is still alive. In the event that the OS crashes,
10901 * ASF needs to reset the hardware to free up the FIFO space
10902 * that may be filled with rx packets destined for the host.
10903 * If the FIFO is full, ASF will no longer function properly.
10905 * Unintended resets have been reported on real time kernels
10906 * where the timer doesn't run on time. Netpoll will also have
10909 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10910 * to check the ring condition when the heartbeat is expiring
10911 * before doing the reset. This will prevent most unintended
10914 if (!--tp->asf_counter) {
10915 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
10916 tg3_wait_for_event_ack(tp);
10918 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
10919 FWCMD_NICDRV_ALIVE3);
10920 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
10921 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10922 TG3_FW_UPDATE_TIMEOUT_SEC);
10924 tg3_generate_fw_event(tp);
10926 tp->asf_counter = tp->asf_multiplier;
10929 spin_unlock(&tp->lock);
10932 tp->timer.expires = jiffies + tp->timer_offset;
10933 add_timer(&tp->timer);
10936 static void tg3_timer_init(struct tg3 *tp)
10938 if (tg3_flag(tp, TAGGED_STATUS) &&
10939 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10940 !tg3_flag(tp, 57765_CLASS))
10941 tp->timer_offset = HZ;
10943 tp->timer_offset = HZ / 10;
10945 BUG_ON(tp->timer_offset > HZ);
10947 tp->timer_multiplier = (HZ / tp->timer_offset);
10948 tp->asf_multiplier = (HZ / tp->timer_offset) *
10949 TG3_FW_UPDATE_FREQ_SEC;
10951 init_timer(&tp->timer);
10952 tp->timer.data = (unsigned long) tp;
10953 tp->timer.function = tg3_timer;
10956 static void tg3_timer_start(struct tg3 *tp)
10958 tp->asf_counter = tp->asf_multiplier;
10959 tp->timer_counter = tp->timer_multiplier;
10961 tp->timer.expires = jiffies + tp->timer_offset;
10962 add_timer(&tp->timer);
10965 static void tg3_timer_stop(struct tg3 *tp)
10967 del_timer_sync(&tp->timer);
10970 /* Restart hardware after configuration changes, self-test, etc.
10971 * Invoked with tp->lock held.
10973 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
10974 __releases(tp->lock)
10975 __acquires(tp->lock)
10979 err = tg3_init_hw(tp, reset_phy);
10981 netdev_err(tp->dev,
10982 "Failed to re-initialize device, aborting\n");
10983 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10984 tg3_full_unlock(tp);
10985 tg3_timer_stop(tp);
10987 tg3_napi_enable(tp);
10988 dev_close(tp->dev);
10989 tg3_full_lock(tp, 0);
10994 static void tg3_reset_task(struct work_struct *work)
10996 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10999 tg3_full_lock(tp, 0);
11001 if (!netif_running(tp->dev)) {
11002 tg3_flag_clear(tp, RESET_TASK_PENDING);
11003 tg3_full_unlock(tp);
11007 tg3_full_unlock(tp);
11011 tg3_netif_stop(tp);
11013 tg3_full_lock(tp, 1);
11015 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11016 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11017 tp->write32_rx_mbox = tg3_write_flush_reg32;
11018 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11019 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11022 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11023 err = tg3_init_hw(tp, true);
11027 tg3_netif_start(tp);
11030 tg3_full_unlock(tp);
11035 tg3_flag_clear(tp, RESET_TASK_PENDING);
11038 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11041 unsigned long flags;
11043 struct tg3_napi *tnapi = &tp->napi[irq_num];
11045 if (tp->irq_cnt == 1)
11046 name = tp->dev->name;
11048 name = &tnapi->irq_lbl[0];
11049 if (tnapi->tx_buffers && tnapi->rx_rcb)
11050 snprintf(name, IFNAMSIZ,
11051 "%s-txrx-%d", tp->dev->name, irq_num);
11052 else if (tnapi->tx_buffers)
11053 snprintf(name, IFNAMSIZ,
11054 "%s-tx-%d", tp->dev->name, irq_num);
11055 else if (tnapi->rx_rcb)
11056 snprintf(name, IFNAMSIZ,
11057 "%s-rx-%d", tp->dev->name, irq_num);
11059 snprintf(name, IFNAMSIZ,
11060 "%s-%d", tp->dev->name, irq_num);
11061 name[IFNAMSIZ-1] = 0;
11064 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11066 if (tg3_flag(tp, 1SHOT_MSI))
11067 fn = tg3_msi_1shot;
11070 fn = tg3_interrupt;
11071 if (tg3_flag(tp, TAGGED_STATUS))
11072 fn = tg3_interrupt_tagged;
11073 flags = IRQF_SHARED;
11076 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11079 static int tg3_test_interrupt(struct tg3 *tp)
11081 struct tg3_napi *tnapi = &tp->napi[0];
11082 struct net_device *dev = tp->dev;
11083 int err, i, intr_ok = 0;
11086 if (!netif_running(dev))
11089 tg3_disable_ints(tp);
11091 free_irq(tnapi->irq_vec, tnapi);
11094 * Turn off MSI one shot mode. Otherwise this test has no
11095 * observable way to know whether the interrupt was delivered.
11097 if (tg3_flag(tp, 57765_PLUS)) {
11098 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11099 tw32(MSGINT_MODE, val);
11102 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11103 IRQF_SHARED, dev->name, tnapi);
11107 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11108 tg3_enable_ints(tp);
11110 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11113 for (i = 0; i < 5; i++) {
11114 u32 int_mbox, misc_host_ctrl;
11116 int_mbox = tr32_mailbox(tnapi->int_mbox);
11117 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11119 if ((int_mbox != 0) ||
11120 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11125 if (tg3_flag(tp, 57765_PLUS) &&
11126 tnapi->hw_status->status_tag != tnapi->last_tag)
11127 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11132 tg3_disable_ints(tp);
11134 free_irq(tnapi->irq_vec, tnapi);
11136 err = tg3_request_irq(tp, 0);
11142 /* Reenable MSI one shot mode. */
11143 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11144 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11145 tw32(MSGINT_MODE, val);
11153 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11154 * successfully restored
11156 static int tg3_test_msi(struct tg3 *tp)
11161 if (!tg3_flag(tp, USING_MSI))
11164 /* Turn off SERR reporting in case MSI terminates with Master
11167 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11168 pci_write_config_word(tp->pdev, PCI_COMMAND,
11169 pci_cmd & ~PCI_COMMAND_SERR);
11171 err = tg3_test_interrupt(tp);
11173 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11178 /* other failures */
11182 /* MSI test failed, go back to INTx mode */
11183 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11184 "to INTx mode. Please report this failure to the PCI "
11185 "maintainer and include system chipset information\n");
11187 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11189 pci_disable_msi(tp->pdev);
11191 tg3_flag_clear(tp, USING_MSI);
11192 tp->napi[0].irq_vec = tp->pdev->irq;
11194 err = tg3_request_irq(tp, 0);
11198 /* Need to reset the chip because the MSI cycle may have terminated
11199 * with Master Abort.
11201 tg3_full_lock(tp, 1);
11203 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11204 err = tg3_init_hw(tp, true);
11206 tg3_full_unlock(tp);
11209 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11214 static int tg3_request_firmware(struct tg3 *tp)
11216 const struct tg3_firmware_hdr *fw_hdr;
11218 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11219 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11224 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11226 /* Firmware blob starts with version numbers, followed by
11227 * start address and _full_ length including BSS sections
11228 * (which must be longer than the actual data, of course
11231 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11232 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11233 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11234 tp->fw_len, tp->fw_needed);
11235 release_firmware(tp->fw);
11240 /* We no longer need firmware; we have it. */
11241 tp->fw_needed = NULL;
11245 static u32 tg3_irq_count(struct tg3 *tp)
11247 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11250 /* We want as many rx rings enabled as there are cpus.
11251 * In multiqueue MSI-X mode, the first MSI-X vector
11252 * only deals with link interrupts, etc, so we add
11253 * one to the number of vectors we are requesting.
11255 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11261 static bool tg3_enable_msix(struct tg3 *tp)
11264 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11266 tp->txq_cnt = tp->txq_req;
11267 tp->rxq_cnt = tp->rxq_req;
11269 tp->rxq_cnt = netif_get_num_default_rss_queues();
11270 if (tp->rxq_cnt > tp->rxq_max)
11271 tp->rxq_cnt = tp->rxq_max;
11273 /* Disable multiple TX rings by default. Simple round-robin hardware
11274 * scheduling of the TX rings can cause starvation of rings with
11275 * small packets when other rings have TSO or jumbo packets.
11280 tp->irq_cnt = tg3_irq_count(tp);
11282 for (i = 0; i < tp->irq_max; i++) {
11283 msix_ent[i].entry = i;
11284 msix_ent[i].vector = 0;
11287 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
11290 } else if (rc != 0) {
11291 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11293 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11296 tp->rxq_cnt = max(rc - 1, 1);
11298 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11301 for (i = 0; i < tp->irq_max; i++)
11302 tp->napi[i].irq_vec = msix_ent[i].vector;
11304 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11305 pci_disable_msix(tp->pdev);
11309 if (tp->irq_cnt == 1)
11312 tg3_flag_set(tp, ENABLE_RSS);
11314 if (tp->txq_cnt > 1)
11315 tg3_flag_set(tp, ENABLE_TSS);
11317 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11322 static void tg3_ints_init(struct tg3 *tp)
11324 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11325 !tg3_flag(tp, TAGGED_STATUS)) {
11326 /* All MSI supporting chips should support tagged
11327 * status. Assert that this is the case.
11329 netdev_warn(tp->dev,
11330 "MSI without TAGGED_STATUS? Not using MSI\n");
11334 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11335 tg3_flag_set(tp, USING_MSIX);
11336 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11337 tg3_flag_set(tp, USING_MSI);
11339 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11340 u32 msi_mode = tr32(MSGINT_MODE);
11341 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11342 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11343 if (!tg3_flag(tp, 1SHOT_MSI))
11344 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11345 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11348 if (!tg3_flag(tp, USING_MSIX)) {
11350 tp->napi[0].irq_vec = tp->pdev->irq;
11353 if (tp->irq_cnt == 1) {
11356 netif_set_real_num_tx_queues(tp->dev, 1);
11357 netif_set_real_num_rx_queues(tp->dev, 1);
11361 static void tg3_ints_fini(struct tg3 *tp)
11363 if (tg3_flag(tp, USING_MSIX))
11364 pci_disable_msix(tp->pdev);
11365 else if (tg3_flag(tp, USING_MSI))
11366 pci_disable_msi(tp->pdev);
11367 tg3_flag_clear(tp, USING_MSI);
11368 tg3_flag_clear(tp, USING_MSIX);
11369 tg3_flag_clear(tp, ENABLE_RSS);
11370 tg3_flag_clear(tp, ENABLE_TSS);
11373 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11376 struct net_device *dev = tp->dev;
11380 * Setup interrupts first so we know how
11381 * many NAPI resources to allocate
11385 tg3_rss_check_indir_tbl(tp);
11387 /* The placement of this call is tied
11388 * to the setup and use of Host TX descriptors.
11390 err = tg3_alloc_consistent(tp);
11392 goto out_ints_fini;
11396 tg3_napi_enable(tp);
11398 for (i = 0; i < tp->irq_cnt; i++) {
11399 struct tg3_napi *tnapi = &tp->napi[i];
11400 err = tg3_request_irq(tp, i);
11402 for (i--; i >= 0; i--) {
11403 tnapi = &tp->napi[i];
11404 free_irq(tnapi->irq_vec, tnapi);
11406 goto out_napi_fini;
11410 tg3_full_lock(tp, 0);
11413 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11415 err = tg3_init_hw(tp, reset_phy);
11417 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11418 tg3_free_rings(tp);
11421 tg3_full_unlock(tp);
11426 if (test_irq && tg3_flag(tp, USING_MSI)) {
11427 err = tg3_test_msi(tp);
11430 tg3_full_lock(tp, 0);
11431 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11432 tg3_free_rings(tp);
11433 tg3_full_unlock(tp);
11435 goto out_napi_fini;
11438 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11439 u32 val = tr32(PCIE_TRANSACTION_CFG);
11441 tw32(PCIE_TRANSACTION_CFG,
11442 val | PCIE_TRANS_CFG_1SHOT_MSI);
11448 tg3_hwmon_open(tp);
11450 tg3_full_lock(tp, 0);
11452 tg3_timer_start(tp);
11453 tg3_flag_set(tp, INIT_COMPLETE);
11454 tg3_enable_ints(tp);
11459 tg3_ptp_resume(tp);
11462 tg3_full_unlock(tp);
11464 netif_tx_start_all_queues(dev);
11467 * Reset loopback feature if it was turned on while the device was down
11468 * make sure that it's installed properly now.
11470 if (dev->features & NETIF_F_LOOPBACK)
11471 tg3_set_loopback(dev, dev->features);
11476 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11477 struct tg3_napi *tnapi = &tp->napi[i];
11478 free_irq(tnapi->irq_vec, tnapi);
11482 tg3_napi_disable(tp);
11484 tg3_free_consistent(tp);
11492 static void tg3_stop(struct tg3 *tp)
11496 tg3_reset_task_cancel(tp);
11497 tg3_netif_stop(tp);
11499 tg3_timer_stop(tp);
11501 tg3_hwmon_close(tp);
11505 tg3_full_lock(tp, 1);
11507 tg3_disable_ints(tp);
11509 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11510 tg3_free_rings(tp);
11511 tg3_flag_clear(tp, INIT_COMPLETE);
11513 tg3_full_unlock(tp);
11515 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11516 struct tg3_napi *tnapi = &tp->napi[i];
11517 free_irq(tnapi->irq_vec, tnapi);
11524 tg3_free_consistent(tp);
11527 static int tg3_open(struct net_device *dev)
11529 struct tg3 *tp = netdev_priv(dev);
11532 if (tp->fw_needed) {
11533 err = tg3_request_firmware(tp);
11534 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11536 netdev_warn(tp->dev, "EEE capability disabled\n");
11537 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11538 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11539 netdev_warn(tp->dev, "EEE capability restored\n");
11540 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11542 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11546 netdev_warn(tp->dev, "TSO capability disabled\n");
11547 tg3_flag_clear(tp, TSO_CAPABLE);
11548 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11549 netdev_notice(tp->dev, "TSO capability restored\n");
11550 tg3_flag_set(tp, TSO_CAPABLE);
11554 tg3_carrier_off(tp);
11556 err = tg3_power_up(tp);
11560 tg3_full_lock(tp, 0);
11562 tg3_disable_ints(tp);
11563 tg3_flag_clear(tp, INIT_COMPLETE);
11565 tg3_full_unlock(tp);
11567 err = tg3_start(tp,
11568 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11571 tg3_frob_aux_power(tp, false);
11572 pci_set_power_state(tp->pdev, PCI_D3hot);
11575 if (tg3_flag(tp, PTP_CAPABLE)) {
11576 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11578 if (IS_ERR(tp->ptp_clock))
11579 tp->ptp_clock = NULL;
11585 static int tg3_close(struct net_device *dev)
11587 struct tg3 *tp = netdev_priv(dev);
11593 /* Clear stats across close / open calls */
11594 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11595 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11597 tg3_power_down_prepare(tp);
11599 tg3_carrier_off(tp);
11604 static inline u64 get_stat64(tg3_stat64_t *val)
11606 return ((u64)val->high << 32) | ((u64)val->low);
11609 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11611 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11613 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11614 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11615 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11618 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11619 tg3_writephy(tp, MII_TG3_TEST1,
11620 val | MII_TG3_TEST1_CRC_EN);
11621 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11625 tp->phy_crc_errors += val;
11627 return tp->phy_crc_errors;
11630 return get_stat64(&hw_stats->rx_fcs_errors);
11633 #define ESTAT_ADD(member) \
11634 estats->member = old_estats->member + \
11635 get_stat64(&hw_stats->member)
11637 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11639 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11640 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11642 ESTAT_ADD(rx_octets);
11643 ESTAT_ADD(rx_fragments);
11644 ESTAT_ADD(rx_ucast_packets);
11645 ESTAT_ADD(rx_mcast_packets);
11646 ESTAT_ADD(rx_bcast_packets);
11647 ESTAT_ADD(rx_fcs_errors);
11648 ESTAT_ADD(rx_align_errors);
11649 ESTAT_ADD(rx_xon_pause_rcvd);
11650 ESTAT_ADD(rx_xoff_pause_rcvd);
11651 ESTAT_ADD(rx_mac_ctrl_rcvd);
11652 ESTAT_ADD(rx_xoff_entered);
11653 ESTAT_ADD(rx_frame_too_long_errors);
11654 ESTAT_ADD(rx_jabbers);
11655 ESTAT_ADD(rx_undersize_packets);
11656 ESTAT_ADD(rx_in_length_errors);
11657 ESTAT_ADD(rx_out_length_errors);
11658 ESTAT_ADD(rx_64_or_less_octet_packets);
11659 ESTAT_ADD(rx_65_to_127_octet_packets);
11660 ESTAT_ADD(rx_128_to_255_octet_packets);
11661 ESTAT_ADD(rx_256_to_511_octet_packets);
11662 ESTAT_ADD(rx_512_to_1023_octet_packets);
11663 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11664 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11665 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11666 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11667 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11669 ESTAT_ADD(tx_octets);
11670 ESTAT_ADD(tx_collisions);
11671 ESTAT_ADD(tx_xon_sent);
11672 ESTAT_ADD(tx_xoff_sent);
11673 ESTAT_ADD(tx_flow_control);
11674 ESTAT_ADD(tx_mac_errors);
11675 ESTAT_ADD(tx_single_collisions);
11676 ESTAT_ADD(tx_mult_collisions);
11677 ESTAT_ADD(tx_deferred);
11678 ESTAT_ADD(tx_excessive_collisions);
11679 ESTAT_ADD(tx_late_collisions);
11680 ESTAT_ADD(tx_collide_2times);
11681 ESTAT_ADD(tx_collide_3times);
11682 ESTAT_ADD(tx_collide_4times);
11683 ESTAT_ADD(tx_collide_5times);
11684 ESTAT_ADD(tx_collide_6times);
11685 ESTAT_ADD(tx_collide_7times);
11686 ESTAT_ADD(tx_collide_8times);
11687 ESTAT_ADD(tx_collide_9times);
11688 ESTAT_ADD(tx_collide_10times);
11689 ESTAT_ADD(tx_collide_11times);
11690 ESTAT_ADD(tx_collide_12times);
11691 ESTAT_ADD(tx_collide_13times);
11692 ESTAT_ADD(tx_collide_14times);
11693 ESTAT_ADD(tx_collide_15times);
11694 ESTAT_ADD(tx_ucast_packets);
11695 ESTAT_ADD(tx_mcast_packets);
11696 ESTAT_ADD(tx_bcast_packets);
11697 ESTAT_ADD(tx_carrier_sense_errors);
11698 ESTAT_ADD(tx_discards);
11699 ESTAT_ADD(tx_errors);
11701 ESTAT_ADD(dma_writeq_full);
11702 ESTAT_ADD(dma_write_prioq_full);
11703 ESTAT_ADD(rxbds_empty);
11704 ESTAT_ADD(rx_discards);
11705 ESTAT_ADD(rx_errors);
11706 ESTAT_ADD(rx_threshold_hit);
11708 ESTAT_ADD(dma_readq_full);
11709 ESTAT_ADD(dma_read_prioq_full);
11710 ESTAT_ADD(tx_comp_queue_full);
11712 ESTAT_ADD(ring_set_send_prod_index);
11713 ESTAT_ADD(ring_status_update);
11714 ESTAT_ADD(nic_irqs);
11715 ESTAT_ADD(nic_avoided_irqs);
11716 ESTAT_ADD(nic_tx_threshold_hit);
11718 ESTAT_ADD(mbuf_lwm_thresh_hit);
11721 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11723 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11724 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11726 stats->rx_packets = old_stats->rx_packets +
11727 get_stat64(&hw_stats->rx_ucast_packets) +
11728 get_stat64(&hw_stats->rx_mcast_packets) +
11729 get_stat64(&hw_stats->rx_bcast_packets);
11731 stats->tx_packets = old_stats->tx_packets +
11732 get_stat64(&hw_stats->tx_ucast_packets) +
11733 get_stat64(&hw_stats->tx_mcast_packets) +
11734 get_stat64(&hw_stats->tx_bcast_packets);
11736 stats->rx_bytes = old_stats->rx_bytes +
11737 get_stat64(&hw_stats->rx_octets);
11738 stats->tx_bytes = old_stats->tx_bytes +
11739 get_stat64(&hw_stats->tx_octets);
11741 stats->rx_errors = old_stats->rx_errors +
11742 get_stat64(&hw_stats->rx_errors);
11743 stats->tx_errors = old_stats->tx_errors +
11744 get_stat64(&hw_stats->tx_errors) +
11745 get_stat64(&hw_stats->tx_mac_errors) +
11746 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11747 get_stat64(&hw_stats->tx_discards);
11749 stats->multicast = old_stats->multicast +
11750 get_stat64(&hw_stats->rx_mcast_packets);
11751 stats->collisions = old_stats->collisions +
11752 get_stat64(&hw_stats->tx_collisions);
11754 stats->rx_length_errors = old_stats->rx_length_errors +
11755 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11756 get_stat64(&hw_stats->rx_undersize_packets);
11758 stats->rx_over_errors = old_stats->rx_over_errors +
11759 get_stat64(&hw_stats->rxbds_empty);
11760 stats->rx_frame_errors = old_stats->rx_frame_errors +
11761 get_stat64(&hw_stats->rx_align_errors);
11762 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11763 get_stat64(&hw_stats->tx_discards);
11764 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11765 get_stat64(&hw_stats->tx_carrier_sense_errors);
11767 stats->rx_crc_errors = old_stats->rx_crc_errors +
11768 tg3_calc_crc_errors(tp);
11770 stats->rx_missed_errors = old_stats->rx_missed_errors +
11771 get_stat64(&hw_stats->rx_discards);
11773 stats->rx_dropped = tp->rx_dropped;
11774 stats->tx_dropped = tp->tx_dropped;
11777 static int tg3_get_regs_len(struct net_device *dev)
11779 return TG3_REG_BLK_SIZE;
11782 static void tg3_get_regs(struct net_device *dev,
11783 struct ethtool_regs *regs, void *_p)
11785 struct tg3 *tp = netdev_priv(dev);
11789 memset(_p, 0, TG3_REG_BLK_SIZE);
11791 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11794 tg3_full_lock(tp, 0);
11796 tg3_dump_legacy_regs(tp, (u32 *)_p);
11798 tg3_full_unlock(tp);
11801 static int tg3_get_eeprom_len(struct net_device *dev)
11803 struct tg3 *tp = netdev_priv(dev);
11805 return tp->nvram_size;
11808 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11810 struct tg3 *tp = netdev_priv(dev);
11813 u32 i, offset, len, b_offset, b_count;
11816 if (tg3_flag(tp, NO_NVRAM))
11819 offset = eeprom->offset;
11823 eeprom->magic = TG3_EEPROM_MAGIC;
11826 /* adjustments to start on required 4 byte boundary */
11827 b_offset = offset & 3;
11828 b_count = 4 - b_offset;
11829 if (b_count > len) {
11830 /* i.e. offset=1 len=2 */
11833 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11836 memcpy(data, ((char *)&val) + b_offset, b_count);
11839 eeprom->len += b_count;
11842 /* read bytes up to the last 4 byte boundary */
11843 pd = &data[eeprom->len];
11844 for (i = 0; i < (len - (len & 3)); i += 4) {
11845 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11850 memcpy(pd + i, &val, 4);
11855 /* read last bytes not ending on 4 byte boundary */
11856 pd = &data[eeprom->len];
11858 b_offset = offset + len - b_count;
11859 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11862 memcpy(pd, &val, b_count);
11863 eeprom->len += b_count;
11868 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11870 struct tg3 *tp = netdev_priv(dev);
11872 u32 offset, len, b_offset, odd_len;
11876 if (tg3_flag(tp, NO_NVRAM) ||
11877 eeprom->magic != TG3_EEPROM_MAGIC)
11880 offset = eeprom->offset;
11883 if ((b_offset = (offset & 3))) {
11884 /* adjustments to start on required 4 byte boundary */
11885 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
11896 /* adjustments to end on required 4 byte boundary */
11898 len = (len + 3) & ~3;
11899 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
11905 if (b_offset || odd_len) {
11906 buf = kmalloc(len, GFP_KERNEL);
11910 memcpy(buf, &start, 4);
11912 memcpy(buf+len-4, &end, 4);
11913 memcpy(buf + b_offset, data, eeprom->len);
11916 ret = tg3_nvram_write_block(tp, offset, len, buf);
11924 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11926 struct tg3 *tp = netdev_priv(dev);
11928 if (tg3_flag(tp, USE_PHYLIB)) {
11929 struct phy_device *phydev;
11930 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11932 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
11933 return phy_ethtool_gset(phydev, cmd);
11936 cmd->supported = (SUPPORTED_Autoneg);
11938 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
11939 cmd->supported |= (SUPPORTED_1000baseT_Half |
11940 SUPPORTED_1000baseT_Full);
11942 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11943 cmd->supported |= (SUPPORTED_100baseT_Half |
11944 SUPPORTED_100baseT_Full |
11945 SUPPORTED_10baseT_Half |
11946 SUPPORTED_10baseT_Full |
11948 cmd->port = PORT_TP;
11950 cmd->supported |= SUPPORTED_FIBRE;
11951 cmd->port = PORT_FIBRE;
11954 cmd->advertising = tp->link_config.advertising;
11955 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11956 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11957 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11958 cmd->advertising |= ADVERTISED_Pause;
11960 cmd->advertising |= ADVERTISED_Pause |
11961 ADVERTISED_Asym_Pause;
11963 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11964 cmd->advertising |= ADVERTISED_Asym_Pause;
11967 if (netif_running(dev) && tp->link_up) {
11968 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
11969 cmd->duplex = tp->link_config.active_duplex;
11970 cmd->lp_advertising = tp->link_config.rmt_adv;
11971 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11972 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11973 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11975 cmd->eth_tp_mdix = ETH_TP_MDI;
11978 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11979 cmd->duplex = DUPLEX_UNKNOWN;
11980 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
11982 cmd->phy_address = tp->phy_addr;
11983 cmd->transceiver = XCVR_INTERNAL;
11984 cmd->autoneg = tp->link_config.autoneg;
11990 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11992 struct tg3 *tp = netdev_priv(dev);
11993 u32 speed = ethtool_cmd_speed(cmd);
11995 if (tg3_flag(tp, USE_PHYLIB)) {
11996 struct phy_device *phydev;
11997 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11999 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12000 return phy_ethtool_sset(phydev, cmd);
12003 if (cmd->autoneg != AUTONEG_ENABLE &&
12004 cmd->autoneg != AUTONEG_DISABLE)
12007 if (cmd->autoneg == AUTONEG_DISABLE &&
12008 cmd->duplex != DUPLEX_FULL &&
12009 cmd->duplex != DUPLEX_HALF)
12012 if (cmd->autoneg == AUTONEG_ENABLE) {
12013 u32 mask = ADVERTISED_Autoneg |
12015 ADVERTISED_Asym_Pause;
12017 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12018 mask |= ADVERTISED_1000baseT_Half |
12019 ADVERTISED_1000baseT_Full;
12021 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12022 mask |= ADVERTISED_100baseT_Half |
12023 ADVERTISED_100baseT_Full |
12024 ADVERTISED_10baseT_Half |
12025 ADVERTISED_10baseT_Full |
12028 mask |= ADVERTISED_FIBRE;
12030 if (cmd->advertising & ~mask)
12033 mask &= (ADVERTISED_1000baseT_Half |
12034 ADVERTISED_1000baseT_Full |
12035 ADVERTISED_100baseT_Half |
12036 ADVERTISED_100baseT_Full |
12037 ADVERTISED_10baseT_Half |
12038 ADVERTISED_10baseT_Full);
12040 cmd->advertising &= mask;
12042 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12043 if (speed != SPEED_1000)
12046 if (cmd->duplex != DUPLEX_FULL)
12049 if (speed != SPEED_100 &&
12055 tg3_full_lock(tp, 0);
12057 tp->link_config.autoneg = cmd->autoneg;
12058 if (cmd->autoneg == AUTONEG_ENABLE) {
12059 tp->link_config.advertising = (cmd->advertising |
12060 ADVERTISED_Autoneg);
12061 tp->link_config.speed = SPEED_UNKNOWN;
12062 tp->link_config.duplex = DUPLEX_UNKNOWN;
12064 tp->link_config.advertising = 0;
12065 tp->link_config.speed = speed;
12066 tp->link_config.duplex = cmd->duplex;
12069 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12071 tg3_warn_mgmt_link_flap(tp);
12073 if (netif_running(dev))
12074 tg3_setup_phy(tp, true);
12076 tg3_full_unlock(tp);
12081 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12083 struct tg3 *tp = netdev_priv(dev);
12085 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12086 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12087 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12088 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12091 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12093 struct tg3 *tp = netdev_priv(dev);
12095 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12096 wol->supported = WAKE_MAGIC;
12098 wol->supported = 0;
12100 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12101 wol->wolopts = WAKE_MAGIC;
12102 memset(&wol->sopass, 0, sizeof(wol->sopass));
12105 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12107 struct tg3 *tp = netdev_priv(dev);
12108 struct device *dp = &tp->pdev->dev;
12110 if (wol->wolopts & ~WAKE_MAGIC)
12112 if ((wol->wolopts & WAKE_MAGIC) &&
12113 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12116 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12118 if (device_may_wakeup(dp))
12119 tg3_flag_set(tp, WOL_ENABLE);
12121 tg3_flag_clear(tp, WOL_ENABLE);
12126 static u32 tg3_get_msglevel(struct net_device *dev)
12128 struct tg3 *tp = netdev_priv(dev);
12129 return tp->msg_enable;
12132 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12134 struct tg3 *tp = netdev_priv(dev);
12135 tp->msg_enable = value;
12138 static int tg3_nway_reset(struct net_device *dev)
12140 struct tg3 *tp = netdev_priv(dev);
12143 if (!netif_running(dev))
12146 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12149 tg3_warn_mgmt_link_flap(tp);
12151 if (tg3_flag(tp, USE_PHYLIB)) {
12152 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12154 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12158 spin_lock_bh(&tp->lock);
12160 tg3_readphy(tp, MII_BMCR, &bmcr);
12161 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12162 ((bmcr & BMCR_ANENABLE) ||
12163 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12164 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12168 spin_unlock_bh(&tp->lock);
12174 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12176 struct tg3 *tp = netdev_priv(dev);
12178 ering->rx_max_pending = tp->rx_std_ring_mask;
12179 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12180 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12182 ering->rx_jumbo_max_pending = 0;
12184 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12186 ering->rx_pending = tp->rx_pending;
12187 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12188 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12190 ering->rx_jumbo_pending = 0;
12192 ering->tx_pending = tp->napi[0].tx_pending;
12195 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12197 struct tg3 *tp = netdev_priv(dev);
12198 int i, irq_sync = 0, err = 0;
12200 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12201 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12202 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12203 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12204 (tg3_flag(tp, TSO_BUG) &&
12205 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12208 if (netif_running(dev)) {
12210 tg3_netif_stop(tp);
12214 tg3_full_lock(tp, irq_sync);
12216 tp->rx_pending = ering->rx_pending;
12218 if (tg3_flag(tp, MAX_RXPEND_64) &&
12219 tp->rx_pending > 63)
12220 tp->rx_pending = 63;
12221 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12223 for (i = 0; i < tp->irq_max; i++)
12224 tp->napi[i].tx_pending = ering->tx_pending;
12226 if (netif_running(dev)) {
12227 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12228 err = tg3_restart_hw(tp, false);
12230 tg3_netif_start(tp);
12233 tg3_full_unlock(tp);
12235 if (irq_sync && !err)
12241 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12243 struct tg3 *tp = netdev_priv(dev);
12245 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12247 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12248 epause->rx_pause = 1;
12250 epause->rx_pause = 0;
12252 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12253 epause->tx_pause = 1;
12255 epause->tx_pause = 0;
12258 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12260 struct tg3 *tp = netdev_priv(dev);
12263 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12264 tg3_warn_mgmt_link_flap(tp);
12266 if (tg3_flag(tp, USE_PHYLIB)) {
12268 struct phy_device *phydev;
12270 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12272 if (!(phydev->supported & SUPPORTED_Pause) ||
12273 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12274 (epause->rx_pause != epause->tx_pause)))
12277 tp->link_config.flowctrl = 0;
12278 if (epause->rx_pause) {
12279 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12281 if (epause->tx_pause) {
12282 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12283 newadv = ADVERTISED_Pause;
12285 newadv = ADVERTISED_Pause |
12286 ADVERTISED_Asym_Pause;
12287 } else if (epause->tx_pause) {
12288 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12289 newadv = ADVERTISED_Asym_Pause;
12293 if (epause->autoneg)
12294 tg3_flag_set(tp, PAUSE_AUTONEG);
12296 tg3_flag_clear(tp, PAUSE_AUTONEG);
12298 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12299 u32 oldadv = phydev->advertising &
12300 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12301 if (oldadv != newadv) {
12302 phydev->advertising &=
12303 ~(ADVERTISED_Pause |
12304 ADVERTISED_Asym_Pause);
12305 phydev->advertising |= newadv;
12306 if (phydev->autoneg) {
12308 * Always renegotiate the link to
12309 * inform our link partner of our
12310 * flow control settings, even if the
12311 * flow control is forced. Let
12312 * tg3_adjust_link() do the final
12313 * flow control setup.
12315 return phy_start_aneg(phydev);
12319 if (!epause->autoneg)
12320 tg3_setup_flow_control(tp, 0, 0);
12322 tp->link_config.advertising &=
12323 ~(ADVERTISED_Pause |
12324 ADVERTISED_Asym_Pause);
12325 tp->link_config.advertising |= newadv;
12330 if (netif_running(dev)) {
12331 tg3_netif_stop(tp);
12335 tg3_full_lock(tp, irq_sync);
12337 if (epause->autoneg)
12338 tg3_flag_set(tp, PAUSE_AUTONEG);
12340 tg3_flag_clear(tp, PAUSE_AUTONEG);
12341 if (epause->rx_pause)
12342 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12344 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12345 if (epause->tx_pause)
12346 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12348 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12350 if (netif_running(dev)) {
12351 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12352 err = tg3_restart_hw(tp, false);
12354 tg3_netif_start(tp);
12357 tg3_full_unlock(tp);
12360 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12365 static int tg3_get_sset_count(struct net_device *dev, int sset)
12369 return TG3_NUM_TEST;
12371 return TG3_NUM_STATS;
12373 return -EOPNOTSUPP;
12377 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12378 u32 *rules __always_unused)
12380 struct tg3 *tp = netdev_priv(dev);
12382 if (!tg3_flag(tp, SUPPORT_MSIX))
12383 return -EOPNOTSUPP;
12385 switch (info->cmd) {
12386 case ETHTOOL_GRXRINGS:
12387 if (netif_running(tp->dev))
12388 info->data = tp->rxq_cnt;
12390 info->data = num_online_cpus();
12391 if (info->data > TG3_RSS_MAX_NUM_QS)
12392 info->data = TG3_RSS_MAX_NUM_QS;
12395 /* The first interrupt vector only
12396 * handles link interrupts.
12402 return -EOPNOTSUPP;
12406 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12409 struct tg3 *tp = netdev_priv(dev);
12411 if (tg3_flag(tp, SUPPORT_MSIX))
12412 size = TG3_RSS_INDIR_TBL_SIZE;
12417 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12419 struct tg3 *tp = netdev_priv(dev);
12422 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12423 indir[i] = tp->rss_ind_tbl[i];
12428 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12430 struct tg3 *tp = netdev_priv(dev);
12433 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12434 tp->rss_ind_tbl[i] = indir[i];
12436 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12439 /* It is legal to write the indirection
12440 * table while the device is running.
12442 tg3_full_lock(tp, 0);
12443 tg3_rss_write_indir_tbl(tp);
12444 tg3_full_unlock(tp);
12449 static void tg3_get_channels(struct net_device *dev,
12450 struct ethtool_channels *channel)
12452 struct tg3 *tp = netdev_priv(dev);
12453 u32 deflt_qs = netif_get_num_default_rss_queues();
12455 channel->max_rx = tp->rxq_max;
12456 channel->max_tx = tp->txq_max;
12458 if (netif_running(dev)) {
12459 channel->rx_count = tp->rxq_cnt;
12460 channel->tx_count = tp->txq_cnt;
12463 channel->rx_count = tp->rxq_req;
12465 channel->rx_count = min(deflt_qs, tp->rxq_max);
12468 channel->tx_count = tp->txq_req;
12470 channel->tx_count = min(deflt_qs, tp->txq_max);
12474 static int tg3_set_channels(struct net_device *dev,
12475 struct ethtool_channels *channel)
12477 struct tg3 *tp = netdev_priv(dev);
12479 if (!tg3_flag(tp, SUPPORT_MSIX))
12480 return -EOPNOTSUPP;
12482 if (channel->rx_count > tp->rxq_max ||
12483 channel->tx_count > tp->txq_max)
12486 tp->rxq_req = channel->rx_count;
12487 tp->txq_req = channel->tx_count;
12489 if (!netif_running(dev))
12494 tg3_carrier_off(tp);
12496 tg3_start(tp, true, false, false);
12501 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12503 switch (stringset) {
12505 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12508 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12511 WARN_ON(1); /* we need a WARN() */
12516 static int tg3_set_phys_id(struct net_device *dev,
12517 enum ethtool_phys_id_state state)
12519 struct tg3 *tp = netdev_priv(dev);
12521 if (!netif_running(tp->dev))
12525 case ETHTOOL_ID_ACTIVE:
12526 return 1; /* cycle on/off once per second */
12528 case ETHTOOL_ID_ON:
12529 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12530 LED_CTRL_1000MBPS_ON |
12531 LED_CTRL_100MBPS_ON |
12532 LED_CTRL_10MBPS_ON |
12533 LED_CTRL_TRAFFIC_OVERRIDE |
12534 LED_CTRL_TRAFFIC_BLINK |
12535 LED_CTRL_TRAFFIC_LED);
12538 case ETHTOOL_ID_OFF:
12539 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12540 LED_CTRL_TRAFFIC_OVERRIDE);
12543 case ETHTOOL_ID_INACTIVE:
12544 tw32(MAC_LED_CTRL, tp->led_ctrl);
12551 static void tg3_get_ethtool_stats(struct net_device *dev,
12552 struct ethtool_stats *estats, u64 *tmp_stats)
12554 struct tg3 *tp = netdev_priv(dev);
12557 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12559 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12562 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12566 u32 offset = 0, len = 0;
12569 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12572 if (magic == TG3_EEPROM_MAGIC) {
12573 for (offset = TG3_NVM_DIR_START;
12574 offset < TG3_NVM_DIR_END;
12575 offset += TG3_NVM_DIRENT_SIZE) {
12576 if (tg3_nvram_read(tp, offset, &val))
12579 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12580 TG3_NVM_DIRTYPE_EXTVPD)
12584 if (offset != TG3_NVM_DIR_END) {
12585 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12586 if (tg3_nvram_read(tp, offset + 4, &offset))
12589 offset = tg3_nvram_logical_addr(tp, offset);
12593 if (!offset || !len) {
12594 offset = TG3_NVM_VPD_OFF;
12595 len = TG3_NVM_VPD_LEN;
12598 buf = kmalloc(len, GFP_KERNEL);
12602 if (magic == TG3_EEPROM_MAGIC) {
12603 for (i = 0; i < len; i += 4) {
12604 /* The data is in little-endian format in NVRAM.
12605 * Use the big-endian read routines to preserve
12606 * the byte order as it exists in NVRAM.
12608 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12614 unsigned int pos = 0;
12616 ptr = (u8 *)&buf[0];
12617 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12618 cnt = pci_read_vpd(tp->pdev, pos,
12620 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12638 #define NVRAM_TEST_SIZE 0x100
12639 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12640 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12641 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12642 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12643 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12644 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12645 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12646 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12648 static int tg3_test_nvram(struct tg3 *tp)
12650 u32 csum, magic, len;
12652 int i, j, k, err = 0, size;
12654 if (tg3_flag(tp, NO_NVRAM))
12657 if (tg3_nvram_read(tp, 0, &magic) != 0)
12660 if (magic == TG3_EEPROM_MAGIC)
12661 size = NVRAM_TEST_SIZE;
12662 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12663 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12664 TG3_EEPROM_SB_FORMAT_1) {
12665 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12666 case TG3_EEPROM_SB_REVISION_0:
12667 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12669 case TG3_EEPROM_SB_REVISION_2:
12670 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12672 case TG3_EEPROM_SB_REVISION_3:
12673 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12675 case TG3_EEPROM_SB_REVISION_4:
12676 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12678 case TG3_EEPROM_SB_REVISION_5:
12679 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12681 case TG3_EEPROM_SB_REVISION_6:
12682 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12689 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12690 size = NVRAM_SELFBOOT_HW_SIZE;
12694 buf = kmalloc(size, GFP_KERNEL);
12699 for (i = 0, j = 0; i < size; i += 4, j++) {
12700 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12707 /* Selfboot format */
12708 magic = be32_to_cpu(buf[0]);
12709 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12710 TG3_EEPROM_MAGIC_FW) {
12711 u8 *buf8 = (u8 *) buf, csum8 = 0;
12713 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12714 TG3_EEPROM_SB_REVISION_2) {
12715 /* For rev 2, the csum doesn't include the MBA. */
12716 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12718 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12721 for (i = 0; i < size; i++)
12734 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12735 TG3_EEPROM_MAGIC_HW) {
12736 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12737 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12738 u8 *buf8 = (u8 *) buf;
12740 /* Separate the parity bits and the data bytes. */
12741 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12742 if ((i == 0) || (i == 8)) {
12746 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12747 parity[k++] = buf8[i] & msk;
12749 } else if (i == 16) {
12753 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12754 parity[k++] = buf8[i] & msk;
12757 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12758 parity[k++] = buf8[i] & msk;
12761 data[j++] = buf8[i];
12765 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12766 u8 hw8 = hweight8(data[i]);
12768 if ((hw8 & 0x1) && parity[i])
12770 else if (!(hw8 & 0x1) && !parity[i])
12779 /* Bootstrap checksum at offset 0x10 */
12780 csum = calc_crc((unsigned char *) buf, 0x10);
12781 if (csum != le32_to_cpu(buf[0x10/4]))
12784 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12785 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12786 if (csum != le32_to_cpu(buf[0xfc/4]))
12791 buf = tg3_vpd_readblock(tp, &len);
12795 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12797 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12801 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12804 i += PCI_VPD_LRDT_TAG_SIZE;
12805 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12806 PCI_VPD_RO_KEYWORD_CHKSUM);
12810 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12812 for (i = 0; i <= j; i++)
12813 csum8 += ((u8 *)buf)[i];
12827 #define TG3_SERDES_TIMEOUT_SEC 2
12828 #define TG3_COPPER_TIMEOUT_SEC 6
12830 static int tg3_test_link(struct tg3 *tp)
12834 if (!netif_running(tp->dev))
12837 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12838 max = TG3_SERDES_TIMEOUT_SEC;
12840 max = TG3_COPPER_TIMEOUT_SEC;
12842 for (i = 0; i < max; i++) {
12846 if (msleep_interruptible(1000))
12853 /* Only test the commonly used registers */
12854 static int tg3_test_registers(struct tg3 *tp)
12856 int i, is_5705, is_5750;
12857 u32 offset, read_mask, write_mask, val, save_val, read_val;
12861 #define TG3_FL_5705 0x1
12862 #define TG3_FL_NOT_5705 0x2
12863 #define TG3_FL_NOT_5788 0x4
12864 #define TG3_FL_NOT_5750 0x8
12868 /* MAC Control Registers */
12869 { MAC_MODE, TG3_FL_NOT_5705,
12870 0x00000000, 0x00ef6f8c },
12871 { MAC_MODE, TG3_FL_5705,
12872 0x00000000, 0x01ef6b8c },
12873 { MAC_STATUS, TG3_FL_NOT_5705,
12874 0x03800107, 0x00000000 },
12875 { MAC_STATUS, TG3_FL_5705,
12876 0x03800100, 0x00000000 },
12877 { MAC_ADDR_0_HIGH, 0x0000,
12878 0x00000000, 0x0000ffff },
12879 { MAC_ADDR_0_LOW, 0x0000,
12880 0x00000000, 0xffffffff },
12881 { MAC_RX_MTU_SIZE, 0x0000,
12882 0x00000000, 0x0000ffff },
12883 { MAC_TX_MODE, 0x0000,
12884 0x00000000, 0x00000070 },
12885 { MAC_TX_LENGTHS, 0x0000,
12886 0x00000000, 0x00003fff },
12887 { MAC_RX_MODE, TG3_FL_NOT_5705,
12888 0x00000000, 0x000007fc },
12889 { MAC_RX_MODE, TG3_FL_5705,
12890 0x00000000, 0x000007dc },
12891 { MAC_HASH_REG_0, 0x0000,
12892 0x00000000, 0xffffffff },
12893 { MAC_HASH_REG_1, 0x0000,
12894 0x00000000, 0xffffffff },
12895 { MAC_HASH_REG_2, 0x0000,
12896 0x00000000, 0xffffffff },
12897 { MAC_HASH_REG_3, 0x0000,
12898 0x00000000, 0xffffffff },
12900 /* Receive Data and Receive BD Initiator Control Registers. */
12901 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12902 0x00000000, 0xffffffff },
12903 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12904 0x00000000, 0xffffffff },
12905 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12906 0x00000000, 0x00000003 },
12907 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12908 0x00000000, 0xffffffff },
12909 { RCVDBDI_STD_BD+0, 0x0000,
12910 0x00000000, 0xffffffff },
12911 { RCVDBDI_STD_BD+4, 0x0000,
12912 0x00000000, 0xffffffff },
12913 { RCVDBDI_STD_BD+8, 0x0000,
12914 0x00000000, 0xffff0002 },
12915 { RCVDBDI_STD_BD+0xc, 0x0000,
12916 0x00000000, 0xffffffff },
12918 /* Receive BD Initiator Control Registers. */
12919 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12920 0x00000000, 0xffffffff },
12921 { RCVBDI_STD_THRESH, TG3_FL_5705,
12922 0x00000000, 0x000003ff },
12923 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12924 0x00000000, 0xffffffff },
12926 /* Host Coalescing Control Registers. */
12927 { HOSTCC_MODE, TG3_FL_NOT_5705,
12928 0x00000000, 0x00000004 },
12929 { HOSTCC_MODE, TG3_FL_5705,
12930 0x00000000, 0x000000f6 },
12931 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12932 0x00000000, 0xffffffff },
12933 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12934 0x00000000, 0x000003ff },
12935 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12936 0x00000000, 0xffffffff },
12937 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12938 0x00000000, 0x000003ff },
12939 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12940 0x00000000, 0xffffffff },
12941 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12942 0x00000000, 0x000000ff },
12943 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12944 0x00000000, 0xffffffff },
12945 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12946 0x00000000, 0x000000ff },
12947 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12948 0x00000000, 0xffffffff },
12949 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12950 0x00000000, 0xffffffff },
12951 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12952 0x00000000, 0xffffffff },
12953 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12954 0x00000000, 0x000000ff },
12955 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12956 0x00000000, 0xffffffff },
12957 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12958 0x00000000, 0x000000ff },
12959 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12960 0x00000000, 0xffffffff },
12961 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12962 0x00000000, 0xffffffff },
12963 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12964 0x00000000, 0xffffffff },
12965 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12966 0x00000000, 0xffffffff },
12967 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12968 0x00000000, 0xffffffff },
12969 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12970 0xffffffff, 0x00000000 },
12971 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12972 0xffffffff, 0x00000000 },
12974 /* Buffer Manager Control Registers. */
12975 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
12976 0x00000000, 0x007fff80 },
12977 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
12978 0x00000000, 0x007fffff },
12979 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12980 0x00000000, 0x0000003f },
12981 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12982 0x00000000, 0x000001ff },
12983 { BUFMGR_MB_HIGH_WATER, 0x0000,
12984 0x00000000, 0x000001ff },
12985 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12986 0xffffffff, 0x00000000 },
12987 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12988 0xffffffff, 0x00000000 },
12990 /* Mailbox Registers */
12991 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12992 0x00000000, 0x000001ff },
12993 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12994 0x00000000, 0x000001ff },
12995 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12996 0x00000000, 0x000007ff },
12997 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12998 0x00000000, 0x000001ff },
13000 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13003 is_5705 = is_5750 = 0;
13004 if (tg3_flag(tp, 5705_PLUS)) {
13006 if (tg3_flag(tp, 5750_PLUS))
13010 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13011 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13014 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13017 if (tg3_flag(tp, IS_5788) &&
13018 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13021 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13024 offset = (u32) reg_tbl[i].offset;
13025 read_mask = reg_tbl[i].read_mask;
13026 write_mask = reg_tbl[i].write_mask;
13028 /* Save the original register content */
13029 save_val = tr32(offset);
13031 /* Determine the read-only value. */
13032 read_val = save_val & read_mask;
13034 /* Write zero to the register, then make sure the read-only bits
13035 * are not changed and the read/write bits are all zeros.
13039 val = tr32(offset);
13041 /* Test the read-only and read/write bits. */
13042 if (((val & read_mask) != read_val) || (val & write_mask))
13045 /* Write ones to all the bits defined by RdMask and WrMask, then
13046 * make sure the read-only bits are not changed and the
13047 * read/write bits are all ones.
13049 tw32(offset, read_mask | write_mask);
13051 val = tr32(offset);
13053 /* Test the read-only bits. */
13054 if ((val & read_mask) != read_val)
13057 /* Test the read/write bits. */
13058 if ((val & write_mask) != write_mask)
13061 tw32(offset, save_val);
13067 if (netif_msg_hw(tp))
13068 netdev_err(tp->dev,
13069 "Register test failed at offset %x\n", offset);
13070 tw32(offset, save_val);
13074 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13076 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13080 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13081 for (j = 0; j < len; j += 4) {
13084 tg3_write_mem(tp, offset + j, test_pattern[i]);
13085 tg3_read_mem(tp, offset + j, &val);
13086 if (val != test_pattern[i])
13093 static int tg3_test_memory(struct tg3 *tp)
13095 static struct mem_entry {
13098 } mem_tbl_570x[] = {
13099 { 0x00000000, 0x00b50},
13100 { 0x00002000, 0x1c000},
13101 { 0xffffffff, 0x00000}
13102 }, mem_tbl_5705[] = {
13103 { 0x00000100, 0x0000c},
13104 { 0x00000200, 0x00008},
13105 { 0x00004000, 0x00800},
13106 { 0x00006000, 0x01000},
13107 { 0x00008000, 0x02000},
13108 { 0x00010000, 0x0e000},
13109 { 0xffffffff, 0x00000}
13110 }, mem_tbl_5755[] = {
13111 { 0x00000200, 0x00008},
13112 { 0x00004000, 0x00800},
13113 { 0x00006000, 0x00800},
13114 { 0x00008000, 0x02000},
13115 { 0x00010000, 0x0c000},
13116 { 0xffffffff, 0x00000}
13117 }, mem_tbl_5906[] = {
13118 { 0x00000200, 0x00008},
13119 { 0x00004000, 0x00400},
13120 { 0x00006000, 0x00400},
13121 { 0x00008000, 0x01000},
13122 { 0x00010000, 0x01000},
13123 { 0xffffffff, 0x00000}
13124 }, mem_tbl_5717[] = {
13125 { 0x00000200, 0x00008},
13126 { 0x00010000, 0x0a000},
13127 { 0x00020000, 0x13c00},
13128 { 0xffffffff, 0x00000}
13129 }, mem_tbl_57765[] = {
13130 { 0x00000200, 0x00008},
13131 { 0x00004000, 0x00800},
13132 { 0x00006000, 0x09800},
13133 { 0x00010000, 0x0a000},
13134 { 0xffffffff, 0x00000}
13136 struct mem_entry *mem_tbl;
13140 if (tg3_flag(tp, 5717_PLUS))
13141 mem_tbl = mem_tbl_5717;
13142 else if (tg3_flag(tp, 57765_CLASS) ||
13143 tg3_asic_rev(tp) == ASIC_REV_5762)
13144 mem_tbl = mem_tbl_57765;
13145 else if (tg3_flag(tp, 5755_PLUS))
13146 mem_tbl = mem_tbl_5755;
13147 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13148 mem_tbl = mem_tbl_5906;
13149 else if (tg3_flag(tp, 5705_PLUS))
13150 mem_tbl = mem_tbl_5705;
13152 mem_tbl = mem_tbl_570x;
13154 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13155 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13163 #define TG3_TSO_MSS 500
13165 #define TG3_TSO_IP_HDR_LEN 20
13166 #define TG3_TSO_TCP_HDR_LEN 20
13167 #define TG3_TSO_TCP_OPT_LEN 12
13169 static const u8 tg3_tso_header[] = {
13171 0x45, 0x00, 0x00, 0x00,
13172 0x00, 0x00, 0x40, 0x00,
13173 0x40, 0x06, 0x00, 0x00,
13174 0x0a, 0x00, 0x00, 0x01,
13175 0x0a, 0x00, 0x00, 0x02,
13176 0x0d, 0x00, 0xe0, 0x00,
13177 0x00, 0x00, 0x01, 0x00,
13178 0x00, 0x00, 0x02, 0x00,
13179 0x80, 0x10, 0x10, 0x00,
13180 0x14, 0x09, 0x00, 0x00,
13181 0x01, 0x01, 0x08, 0x0a,
13182 0x11, 0x11, 0x11, 0x11,
13183 0x11, 0x11, 0x11, 0x11,
13186 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13188 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13189 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13191 struct sk_buff *skb;
13192 u8 *tx_data, *rx_data;
13194 int num_pkts, tx_len, rx_len, i, err;
13195 struct tg3_rx_buffer_desc *desc;
13196 struct tg3_napi *tnapi, *rnapi;
13197 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13199 tnapi = &tp->napi[0];
13200 rnapi = &tp->napi[0];
13201 if (tp->irq_cnt > 1) {
13202 if (tg3_flag(tp, ENABLE_RSS))
13203 rnapi = &tp->napi[1];
13204 if (tg3_flag(tp, ENABLE_TSS))
13205 tnapi = &tp->napi[1];
13207 coal_now = tnapi->coal_now | rnapi->coal_now;
13212 skb = netdev_alloc_skb(tp->dev, tx_len);
13216 tx_data = skb_put(skb, tx_len);
13217 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13218 memset(tx_data + ETH_ALEN, 0x0, 8);
13220 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13222 if (tso_loopback) {
13223 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13225 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13226 TG3_TSO_TCP_OPT_LEN;
13228 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13229 sizeof(tg3_tso_header));
13232 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13233 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13235 /* Set the total length field in the IP header */
13236 iph->tot_len = htons((u16)(mss + hdr_len));
13238 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13239 TXD_FLAG_CPU_POST_DMA);
13241 if (tg3_flag(tp, HW_TSO_1) ||
13242 tg3_flag(tp, HW_TSO_2) ||
13243 tg3_flag(tp, HW_TSO_3)) {
13245 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13246 th = (struct tcphdr *)&tx_data[val];
13249 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13251 if (tg3_flag(tp, HW_TSO_3)) {
13252 mss |= (hdr_len & 0xc) << 12;
13253 if (hdr_len & 0x10)
13254 base_flags |= 0x00000010;
13255 base_flags |= (hdr_len & 0x3e0) << 5;
13256 } else if (tg3_flag(tp, HW_TSO_2))
13257 mss |= hdr_len << 9;
13258 else if (tg3_flag(tp, HW_TSO_1) ||
13259 tg3_asic_rev(tp) == ASIC_REV_5705) {
13260 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13262 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13265 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13268 data_off = ETH_HLEN;
13270 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13271 tx_len > VLAN_ETH_FRAME_LEN)
13272 base_flags |= TXD_FLAG_JMB_PKT;
13275 for (i = data_off; i < tx_len; i++)
13276 tx_data[i] = (u8) (i & 0xff);
13278 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13279 if (pci_dma_mapping_error(tp->pdev, map)) {
13280 dev_kfree_skb(skb);
13284 val = tnapi->tx_prod;
13285 tnapi->tx_buffers[val].skb = skb;
13286 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13288 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13293 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13295 budget = tg3_tx_avail(tnapi);
13296 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13297 base_flags | TXD_FLAG_END, mss, 0)) {
13298 tnapi->tx_buffers[val].skb = NULL;
13299 dev_kfree_skb(skb);
13305 /* Sync BD data before updating mailbox */
13308 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13309 tr32_mailbox(tnapi->prodmbox);
13313 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13314 for (i = 0; i < 35; i++) {
13315 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13320 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13321 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13322 if ((tx_idx == tnapi->tx_prod) &&
13323 (rx_idx == (rx_start_idx + num_pkts)))
13327 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13328 dev_kfree_skb(skb);
13330 if (tx_idx != tnapi->tx_prod)
13333 if (rx_idx != rx_start_idx + num_pkts)
13337 while (rx_idx != rx_start_idx) {
13338 desc = &rnapi->rx_rcb[rx_start_idx++];
13339 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13340 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13342 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13343 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13346 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13349 if (!tso_loopback) {
13350 if (rx_len != tx_len)
13353 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13354 if (opaque_key != RXD_OPAQUE_RING_STD)
13357 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13360 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13361 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13362 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13366 if (opaque_key == RXD_OPAQUE_RING_STD) {
13367 rx_data = tpr->rx_std_buffers[desc_idx].data;
13368 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13370 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13371 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13372 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13377 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13378 PCI_DMA_FROMDEVICE);
13380 rx_data += TG3_RX_OFFSET(tp);
13381 for (i = data_off; i < rx_len; i++, val++) {
13382 if (*(rx_data + i) != (u8) (val & 0xff))
13389 /* tg3_free_rings will unmap and free the rx_data */
13394 #define TG3_STD_LOOPBACK_FAILED 1
13395 #define TG3_JMB_LOOPBACK_FAILED 2
13396 #define TG3_TSO_LOOPBACK_FAILED 4
13397 #define TG3_LOOPBACK_FAILED \
13398 (TG3_STD_LOOPBACK_FAILED | \
13399 TG3_JMB_LOOPBACK_FAILED | \
13400 TG3_TSO_LOOPBACK_FAILED)
13402 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13406 u32 jmb_pkt_sz = 9000;
13409 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13411 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13412 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13414 if (!netif_running(tp->dev)) {
13415 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13416 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13418 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13422 err = tg3_reset_hw(tp, true);
13424 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13425 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13427 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13431 if (tg3_flag(tp, ENABLE_RSS)) {
13434 /* Reroute all rx packets to the 1st queue */
13435 for (i = MAC_RSS_INDIR_TBL_0;
13436 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13440 /* HW errata - mac loopback fails in some cases on 5780.
13441 * Normal traffic and PHY loopback are not affected by
13442 * errata. Also, the MAC loopback test is deprecated for
13443 * all newer ASIC revisions.
13445 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13446 !tg3_flag(tp, CPMU_PRESENT)) {
13447 tg3_mac_loopback(tp, true);
13449 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13450 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13452 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13453 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13454 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13456 tg3_mac_loopback(tp, false);
13459 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13460 !tg3_flag(tp, USE_PHYLIB)) {
13463 tg3_phy_lpbk_set(tp, 0, false);
13465 /* Wait for link */
13466 for (i = 0; i < 100; i++) {
13467 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13472 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13473 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13474 if (tg3_flag(tp, TSO_CAPABLE) &&
13475 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13476 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13477 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13478 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13479 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13482 tg3_phy_lpbk_set(tp, 0, true);
13484 /* All link indications report up, but the hardware
13485 * isn't really ready for about 20 msec. Double it
13490 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13491 data[TG3_EXT_LOOPB_TEST] |=
13492 TG3_STD_LOOPBACK_FAILED;
13493 if (tg3_flag(tp, TSO_CAPABLE) &&
13494 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13495 data[TG3_EXT_LOOPB_TEST] |=
13496 TG3_TSO_LOOPBACK_FAILED;
13497 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13498 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13499 data[TG3_EXT_LOOPB_TEST] |=
13500 TG3_JMB_LOOPBACK_FAILED;
13503 /* Re-enable gphy autopowerdown. */
13504 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13505 tg3_phy_toggle_apd(tp, true);
13508 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13509 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13512 tp->phy_flags |= eee_cap;
13517 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13520 struct tg3 *tp = netdev_priv(dev);
13521 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13523 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13524 if (tg3_power_up(tp)) {
13525 etest->flags |= ETH_TEST_FL_FAILED;
13526 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13529 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13532 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13534 if (tg3_test_nvram(tp) != 0) {
13535 etest->flags |= ETH_TEST_FL_FAILED;
13536 data[TG3_NVRAM_TEST] = 1;
13538 if (!doextlpbk && tg3_test_link(tp)) {
13539 etest->flags |= ETH_TEST_FL_FAILED;
13540 data[TG3_LINK_TEST] = 1;
13542 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13543 int err, err2 = 0, irq_sync = 0;
13545 if (netif_running(dev)) {
13547 tg3_netif_stop(tp);
13551 tg3_full_lock(tp, irq_sync);
13552 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13553 err = tg3_nvram_lock(tp);
13554 tg3_halt_cpu(tp, RX_CPU_BASE);
13555 if (!tg3_flag(tp, 5705_PLUS))
13556 tg3_halt_cpu(tp, TX_CPU_BASE);
13558 tg3_nvram_unlock(tp);
13560 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13563 if (tg3_test_registers(tp) != 0) {
13564 etest->flags |= ETH_TEST_FL_FAILED;
13565 data[TG3_REGISTER_TEST] = 1;
13568 if (tg3_test_memory(tp) != 0) {
13569 etest->flags |= ETH_TEST_FL_FAILED;
13570 data[TG3_MEMORY_TEST] = 1;
13574 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13576 if (tg3_test_loopback(tp, data, doextlpbk))
13577 etest->flags |= ETH_TEST_FL_FAILED;
13579 tg3_full_unlock(tp);
13581 if (tg3_test_interrupt(tp) != 0) {
13582 etest->flags |= ETH_TEST_FL_FAILED;
13583 data[TG3_INTERRUPT_TEST] = 1;
13586 tg3_full_lock(tp, 0);
13588 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13589 if (netif_running(dev)) {
13590 tg3_flag_set(tp, INIT_COMPLETE);
13591 err2 = tg3_restart_hw(tp, true);
13593 tg3_netif_start(tp);
13596 tg3_full_unlock(tp);
13598 if (irq_sync && !err2)
13601 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13602 tg3_power_down_prepare(tp);
13606 static int tg3_hwtstamp_ioctl(struct net_device *dev,
13607 struct ifreq *ifr, int cmd)
13609 struct tg3 *tp = netdev_priv(dev);
13610 struct hwtstamp_config stmpconf;
13612 if (!tg3_flag(tp, PTP_CAPABLE))
13615 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13618 if (stmpconf.flags)
13621 switch (stmpconf.tx_type) {
13622 case HWTSTAMP_TX_ON:
13623 tg3_flag_set(tp, TX_TSTAMP_EN);
13625 case HWTSTAMP_TX_OFF:
13626 tg3_flag_clear(tp, TX_TSTAMP_EN);
13632 switch (stmpconf.rx_filter) {
13633 case HWTSTAMP_FILTER_NONE:
13636 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13637 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13638 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13640 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13641 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13642 TG3_RX_PTP_CTL_SYNC_EVNT;
13644 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13645 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13646 TG3_RX_PTP_CTL_DELAY_REQ;
13648 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13649 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13650 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13652 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13653 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13654 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13656 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13657 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13658 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13660 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13661 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13662 TG3_RX_PTP_CTL_SYNC_EVNT;
13664 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13665 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13666 TG3_RX_PTP_CTL_SYNC_EVNT;
13668 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13669 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13670 TG3_RX_PTP_CTL_SYNC_EVNT;
13672 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13673 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13674 TG3_RX_PTP_CTL_DELAY_REQ;
13676 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13677 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13678 TG3_RX_PTP_CTL_DELAY_REQ;
13680 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13681 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13682 TG3_RX_PTP_CTL_DELAY_REQ;
13688 if (netif_running(dev) && tp->rxptpctl)
13689 tw32(TG3_RX_PTP_CTL,
13690 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13692 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13696 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13698 struct mii_ioctl_data *data = if_mii(ifr);
13699 struct tg3 *tp = netdev_priv(dev);
13702 if (tg3_flag(tp, USE_PHYLIB)) {
13703 struct phy_device *phydev;
13704 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13706 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13707 return phy_mii_ioctl(phydev, ifr, cmd);
13712 data->phy_id = tp->phy_addr;
13715 case SIOCGMIIREG: {
13718 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13719 break; /* We have no PHY */
13721 if (!netif_running(dev))
13724 spin_lock_bh(&tp->lock);
13725 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13726 data->reg_num & 0x1f, &mii_regval);
13727 spin_unlock_bh(&tp->lock);
13729 data->val_out = mii_regval;
13735 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13736 break; /* We have no PHY */
13738 if (!netif_running(dev))
13741 spin_lock_bh(&tp->lock);
13742 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13743 data->reg_num & 0x1f, data->val_in);
13744 spin_unlock_bh(&tp->lock);
13748 case SIOCSHWTSTAMP:
13749 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13755 return -EOPNOTSUPP;
13758 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13760 struct tg3 *tp = netdev_priv(dev);
13762 memcpy(ec, &tp->coal, sizeof(*ec));
13766 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13768 struct tg3 *tp = netdev_priv(dev);
13769 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13770 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13772 if (!tg3_flag(tp, 5705_PLUS)) {
13773 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13774 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13775 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13776 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13779 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13780 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13781 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13782 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13783 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13784 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13785 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13786 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13787 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13788 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13791 /* No rx interrupts will be generated if both are zero */
13792 if ((ec->rx_coalesce_usecs == 0) &&
13793 (ec->rx_max_coalesced_frames == 0))
13796 /* No tx interrupts will be generated if both are zero */
13797 if ((ec->tx_coalesce_usecs == 0) &&
13798 (ec->tx_max_coalesced_frames == 0))
13801 /* Only copy relevant parameters, ignore all others. */
13802 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13803 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13804 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13805 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13806 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13807 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13808 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13809 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13810 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13812 if (netif_running(dev)) {
13813 tg3_full_lock(tp, 0);
13814 __tg3_set_coalesce(tp, &tp->coal);
13815 tg3_full_unlock(tp);
13820 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13822 struct tg3 *tp = netdev_priv(dev);
13824 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13825 netdev_warn(tp->dev, "Board does not support EEE!\n");
13826 return -EOPNOTSUPP;
13829 if (edata->advertised != tp->eee.advertised) {
13830 netdev_warn(tp->dev,
13831 "Direct manipulation of EEE advertisement is not supported\n");
13835 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13836 netdev_warn(tp->dev,
13837 "Maximal Tx Lpi timer supported is %#x(u)\n",
13838 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13844 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13845 tg3_warn_mgmt_link_flap(tp);
13847 if (netif_running(tp->dev)) {
13848 tg3_full_lock(tp, 0);
13851 tg3_full_unlock(tp);
13857 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13859 struct tg3 *tp = netdev_priv(dev);
13861 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13862 netdev_warn(tp->dev,
13863 "Board does not support EEE!\n");
13864 return -EOPNOTSUPP;
13871 static const struct ethtool_ops tg3_ethtool_ops = {
13872 .get_settings = tg3_get_settings,
13873 .set_settings = tg3_set_settings,
13874 .get_drvinfo = tg3_get_drvinfo,
13875 .get_regs_len = tg3_get_regs_len,
13876 .get_regs = tg3_get_regs,
13877 .get_wol = tg3_get_wol,
13878 .set_wol = tg3_set_wol,
13879 .get_msglevel = tg3_get_msglevel,
13880 .set_msglevel = tg3_set_msglevel,
13881 .nway_reset = tg3_nway_reset,
13882 .get_link = ethtool_op_get_link,
13883 .get_eeprom_len = tg3_get_eeprom_len,
13884 .get_eeprom = tg3_get_eeprom,
13885 .set_eeprom = tg3_set_eeprom,
13886 .get_ringparam = tg3_get_ringparam,
13887 .set_ringparam = tg3_set_ringparam,
13888 .get_pauseparam = tg3_get_pauseparam,
13889 .set_pauseparam = tg3_set_pauseparam,
13890 .self_test = tg3_self_test,
13891 .get_strings = tg3_get_strings,
13892 .set_phys_id = tg3_set_phys_id,
13893 .get_ethtool_stats = tg3_get_ethtool_stats,
13894 .get_coalesce = tg3_get_coalesce,
13895 .set_coalesce = tg3_set_coalesce,
13896 .get_sset_count = tg3_get_sset_count,
13897 .get_rxnfc = tg3_get_rxnfc,
13898 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13899 .get_rxfh_indir = tg3_get_rxfh_indir,
13900 .set_rxfh_indir = tg3_set_rxfh_indir,
13901 .get_channels = tg3_get_channels,
13902 .set_channels = tg3_set_channels,
13903 .get_ts_info = tg3_get_ts_info,
13904 .get_eee = tg3_get_eee,
13905 .set_eee = tg3_set_eee,
13908 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13909 struct rtnl_link_stats64 *stats)
13911 struct tg3 *tp = netdev_priv(dev);
13913 spin_lock_bh(&tp->lock);
13914 if (!tp->hw_stats) {
13915 spin_unlock_bh(&tp->lock);
13916 return &tp->net_stats_prev;
13919 tg3_get_nstats(tp, stats);
13920 spin_unlock_bh(&tp->lock);
13925 static void tg3_set_rx_mode(struct net_device *dev)
13927 struct tg3 *tp = netdev_priv(dev);
13929 if (!netif_running(dev))
13932 tg3_full_lock(tp, 0);
13933 __tg3_set_rx_mode(dev);
13934 tg3_full_unlock(tp);
13937 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13940 dev->mtu = new_mtu;
13942 if (new_mtu > ETH_DATA_LEN) {
13943 if (tg3_flag(tp, 5780_CLASS)) {
13944 netdev_update_features(dev);
13945 tg3_flag_clear(tp, TSO_CAPABLE);
13947 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13950 if (tg3_flag(tp, 5780_CLASS)) {
13951 tg3_flag_set(tp, TSO_CAPABLE);
13952 netdev_update_features(dev);
13954 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13958 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13960 struct tg3 *tp = netdev_priv(dev);
13962 bool reset_phy = false;
13964 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13967 if (!netif_running(dev)) {
13968 /* We'll just catch it later when the
13971 tg3_set_mtu(dev, tp, new_mtu);
13977 tg3_netif_stop(tp);
13979 tg3_full_lock(tp, 1);
13981 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13983 tg3_set_mtu(dev, tp, new_mtu);
13985 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13986 * breaks all requests to 256 bytes.
13988 if (tg3_asic_rev(tp) == ASIC_REV_57766)
13991 err = tg3_restart_hw(tp, reset_phy);
13994 tg3_netif_start(tp);
13996 tg3_full_unlock(tp);
14004 static const struct net_device_ops tg3_netdev_ops = {
14005 .ndo_open = tg3_open,
14006 .ndo_stop = tg3_close,
14007 .ndo_start_xmit = tg3_start_xmit,
14008 .ndo_get_stats64 = tg3_get_stats64,
14009 .ndo_validate_addr = eth_validate_addr,
14010 .ndo_set_rx_mode = tg3_set_rx_mode,
14011 .ndo_set_mac_address = tg3_set_mac_addr,
14012 .ndo_do_ioctl = tg3_ioctl,
14013 .ndo_tx_timeout = tg3_tx_timeout,
14014 .ndo_change_mtu = tg3_change_mtu,
14015 .ndo_fix_features = tg3_fix_features,
14016 .ndo_set_features = tg3_set_features,
14017 #ifdef CONFIG_NET_POLL_CONTROLLER
14018 .ndo_poll_controller = tg3_poll_controller,
14022 static void tg3_get_eeprom_size(struct tg3 *tp)
14024 u32 cursize, val, magic;
14026 tp->nvram_size = EEPROM_CHIP_SIZE;
14028 if (tg3_nvram_read(tp, 0, &magic) != 0)
14031 if ((magic != TG3_EEPROM_MAGIC) &&
14032 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14033 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14037 * Size the chip by reading offsets at increasing powers of two.
14038 * When we encounter our validation signature, we know the addressing
14039 * has wrapped around, and thus have our chip size.
14043 while (cursize < tp->nvram_size) {
14044 if (tg3_nvram_read(tp, cursize, &val) != 0)
14053 tp->nvram_size = cursize;
14056 static void tg3_get_nvram_size(struct tg3 *tp)
14060 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14063 /* Selfboot format */
14064 if (val != TG3_EEPROM_MAGIC) {
14065 tg3_get_eeprom_size(tp);
14069 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14071 /* This is confusing. We want to operate on the
14072 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14073 * call will read from NVRAM and byteswap the data
14074 * according to the byteswapping settings for all
14075 * other register accesses. This ensures the data we
14076 * want will always reside in the lower 16-bits.
14077 * However, the data in NVRAM is in LE format, which
14078 * means the data from the NVRAM read will always be
14079 * opposite the endianness of the CPU. The 16-bit
14080 * byteswap then brings the data to CPU endianness.
14082 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14086 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14089 static void tg3_get_nvram_info(struct tg3 *tp)
14093 nvcfg1 = tr32(NVRAM_CFG1);
14094 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14095 tg3_flag_set(tp, FLASH);
14097 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14098 tw32(NVRAM_CFG1, nvcfg1);
14101 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14102 tg3_flag(tp, 5780_CLASS)) {
14103 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14104 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14105 tp->nvram_jedecnum = JEDEC_ATMEL;
14106 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14107 tg3_flag_set(tp, NVRAM_BUFFERED);
14109 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14110 tp->nvram_jedecnum = JEDEC_ATMEL;
14111 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14113 case FLASH_VENDOR_ATMEL_EEPROM:
14114 tp->nvram_jedecnum = JEDEC_ATMEL;
14115 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14116 tg3_flag_set(tp, NVRAM_BUFFERED);
14118 case FLASH_VENDOR_ST:
14119 tp->nvram_jedecnum = JEDEC_ST;
14120 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14121 tg3_flag_set(tp, NVRAM_BUFFERED);
14123 case FLASH_VENDOR_SAIFUN:
14124 tp->nvram_jedecnum = JEDEC_SAIFUN;
14125 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14127 case FLASH_VENDOR_SST_SMALL:
14128 case FLASH_VENDOR_SST_LARGE:
14129 tp->nvram_jedecnum = JEDEC_SST;
14130 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14134 tp->nvram_jedecnum = JEDEC_ATMEL;
14135 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14136 tg3_flag_set(tp, NVRAM_BUFFERED);
14140 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14142 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14143 case FLASH_5752PAGE_SIZE_256:
14144 tp->nvram_pagesize = 256;
14146 case FLASH_5752PAGE_SIZE_512:
14147 tp->nvram_pagesize = 512;
14149 case FLASH_5752PAGE_SIZE_1K:
14150 tp->nvram_pagesize = 1024;
14152 case FLASH_5752PAGE_SIZE_2K:
14153 tp->nvram_pagesize = 2048;
14155 case FLASH_5752PAGE_SIZE_4K:
14156 tp->nvram_pagesize = 4096;
14158 case FLASH_5752PAGE_SIZE_264:
14159 tp->nvram_pagesize = 264;
14161 case FLASH_5752PAGE_SIZE_528:
14162 tp->nvram_pagesize = 528;
14167 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14171 nvcfg1 = tr32(NVRAM_CFG1);
14173 /* NVRAM protection for TPM */
14174 if (nvcfg1 & (1 << 27))
14175 tg3_flag_set(tp, PROTECTED_NVRAM);
14177 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14178 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14179 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14180 tp->nvram_jedecnum = JEDEC_ATMEL;
14181 tg3_flag_set(tp, NVRAM_BUFFERED);
14183 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14184 tp->nvram_jedecnum = JEDEC_ATMEL;
14185 tg3_flag_set(tp, NVRAM_BUFFERED);
14186 tg3_flag_set(tp, FLASH);
14188 case FLASH_5752VENDOR_ST_M45PE10:
14189 case FLASH_5752VENDOR_ST_M45PE20:
14190 case FLASH_5752VENDOR_ST_M45PE40:
14191 tp->nvram_jedecnum = JEDEC_ST;
14192 tg3_flag_set(tp, NVRAM_BUFFERED);
14193 tg3_flag_set(tp, FLASH);
14197 if (tg3_flag(tp, FLASH)) {
14198 tg3_nvram_get_pagesize(tp, nvcfg1);
14200 /* For eeprom, set pagesize to maximum eeprom size */
14201 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14203 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14204 tw32(NVRAM_CFG1, nvcfg1);
14208 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14210 u32 nvcfg1, protect = 0;
14212 nvcfg1 = tr32(NVRAM_CFG1);
14214 /* NVRAM protection for TPM */
14215 if (nvcfg1 & (1 << 27)) {
14216 tg3_flag_set(tp, PROTECTED_NVRAM);
14220 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14222 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14223 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14224 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14225 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14226 tp->nvram_jedecnum = JEDEC_ATMEL;
14227 tg3_flag_set(tp, NVRAM_BUFFERED);
14228 tg3_flag_set(tp, FLASH);
14229 tp->nvram_pagesize = 264;
14230 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14231 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14232 tp->nvram_size = (protect ? 0x3e200 :
14233 TG3_NVRAM_SIZE_512KB);
14234 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14235 tp->nvram_size = (protect ? 0x1f200 :
14236 TG3_NVRAM_SIZE_256KB);
14238 tp->nvram_size = (protect ? 0x1f200 :
14239 TG3_NVRAM_SIZE_128KB);
14241 case FLASH_5752VENDOR_ST_M45PE10:
14242 case FLASH_5752VENDOR_ST_M45PE20:
14243 case FLASH_5752VENDOR_ST_M45PE40:
14244 tp->nvram_jedecnum = JEDEC_ST;
14245 tg3_flag_set(tp, NVRAM_BUFFERED);
14246 tg3_flag_set(tp, FLASH);
14247 tp->nvram_pagesize = 256;
14248 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14249 tp->nvram_size = (protect ?
14250 TG3_NVRAM_SIZE_64KB :
14251 TG3_NVRAM_SIZE_128KB);
14252 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14253 tp->nvram_size = (protect ?
14254 TG3_NVRAM_SIZE_64KB :
14255 TG3_NVRAM_SIZE_256KB);
14257 tp->nvram_size = (protect ?
14258 TG3_NVRAM_SIZE_128KB :
14259 TG3_NVRAM_SIZE_512KB);
14264 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14268 nvcfg1 = tr32(NVRAM_CFG1);
14270 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14271 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14272 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14273 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14274 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14275 tp->nvram_jedecnum = JEDEC_ATMEL;
14276 tg3_flag_set(tp, NVRAM_BUFFERED);
14277 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14279 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14280 tw32(NVRAM_CFG1, nvcfg1);
14282 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14283 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14284 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14285 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14286 tp->nvram_jedecnum = JEDEC_ATMEL;
14287 tg3_flag_set(tp, NVRAM_BUFFERED);
14288 tg3_flag_set(tp, FLASH);
14289 tp->nvram_pagesize = 264;
14291 case FLASH_5752VENDOR_ST_M45PE10:
14292 case FLASH_5752VENDOR_ST_M45PE20:
14293 case FLASH_5752VENDOR_ST_M45PE40:
14294 tp->nvram_jedecnum = JEDEC_ST;
14295 tg3_flag_set(tp, NVRAM_BUFFERED);
14296 tg3_flag_set(tp, FLASH);
14297 tp->nvram_pagesize = 256;
14302 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14304 u32 nvcfg1, protect = 0;
14306 nvcfg1 = tr32(NVRAM_CFG1);
14308 /* NVRAM protection for TPM */
14309 if (nvcfg1 & (1 << 27)) {
14310 tg3_flag_set(tp, PROTECTED_NVRAM);
14314 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14316 case FLASH_5761VENDOR_ATMEL_ADB021D:
14317 case FLASH_5761VENDOR_ATMEL_ADB041D:
14318 case FLASH_5761VENDOR_ATMEL_ADB081D:
14319 case FLASH_5761VENDOR_ATMEL_ADB161D:
14320 case FLASH_5761VENDOR_ATMEL_MDB021D:
14321 case FLASH_5761VENDOR_ATMEL_MDB041D:
14322 case FLASH_5761VENDOR_ATMEL_MDB081D:
14323 case FLASH_5761VENDOR_ATMEL_MDB161D:
14324 tp->nvram_jedecnum = JEDEC_ATMEL;
14325 tg3_flag_set(tp, NVRAM_BUFFERED);
14326 tg3_flag_set(tp, FLASH);
14327 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14328 tp->nvram_pagesize = 256;
14330 case FLASH_5761VENDOR_ST_A_M45PE20:
14331 case FLASH_5761VENDOR_ST_A_M45PE40:
14332 case FLASH_5761VENDOR_ST_A_M45PE80:
14333 case FLASH_5761VENDOR_ST_A_M45PE16:
14334 case FLASH_5761VENDOR_ST_M_M45PE20:
14335 case FLASH_5761VENDOR_ST_M_M45PE40:
14336 case FLASH_5761VENDOR_ST_M_M45PE80:
14337 case FLASH_5761VENDOR_ST_M_M45PE16:
14338 tp->nvram_jedecnum = JEDEC_ST;
14339 tg3_flag_set(tp, NVRAM_BUFFERED);
14340 tg3_flag_set(tp, FLASH);
14341 tp->nvram_pagesize = 256;
14346 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14349 case FLASH_5761VENDOR_ATMEL_ADB161D:
14350 case FLASH_5761VENDOR_ATMEL_MDB161D:
14351 case FLASH_5761VENDOR_ST_A_M45PE16:
14352 case FLASH_5761VENDOR_ST_M_M45PE16:
14353 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14355 case FLASH_5761VENDOR_ATMEL_ADB081D:
14356 case FLASH_5761VENDOR_ATMEL_MDB081D:
14357 case FLASH_5761VENDOR_ST_A_M45PE80:
14358 case FLASH_5761VENDOR_ST_M_M45PE80:
14359 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14361 case FLASH_5761VENDOR_ATMEL_ADB041D:
14362 case FLASH_5761VENDOR_ATMEL_MDB041D:
14363 case FLASH_5761VENDOR_ST_A_M45PE40:
14364 case FLASH_5761VENDOR_ST_M_M45PE40:
14365 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14367 case FLASH_5761VENDOR_ATMEL_ADB021D:
14368 case FLASH_5761VENDOR_ATMEL_MDB021D:
14369 case FLASH_5761VENDOR_ST_A_M45PE20:
14370 case FLASH_5761VENDOR_ST_M_M45PE20:
14371 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14377 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14379 tp->nvram_jedecnum = JEDEC_ATMEL;
14380 tg3_flag_set(tp, NVRAM_BUFFERED);
14381 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14384 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14388 nvcfg1 = tr32(NVRAM_CFG1);
14390 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14391 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14392 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14393 tp->nvram_jedecnum = JEDEC_ATMEL;
14394 tg3_flag_set(tp, NVRAM_BUFFERED);
14395 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14397 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14398 tw32(NVRAM_CFG1, nvcfg1);
14400 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14401 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14402 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14403 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14404 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14405 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14406 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14407 tp->nvram_jedecnum = JEDEC_ATMEL;
14408 tg3_flag_set(tp, NVRAM_BUFFERED);
14409 tg3_flag_set(tp, FLASH);
14411 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14412 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14413 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14414 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14415 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14417 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14418 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14419 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14421 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14422 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14423 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14427 case FLASH_5752VENDOR_ST_M45PE10:
14428 case FLASH_5752VENDOR_ST_M45PE20:
14429 case FLASH_5752VENDOR_ST_M45PE40:
14430 tp->nvram_jedecnum = JEDEC_ST;
14431 tg3_flag_set(tp, NVRAM_BUFFERED);
14432 tg3_flag_set(tp, FLASH);
14434 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14435 case FLASH_5752VENDOR_ST_M45PE10:
14436 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14438 case FLASH_5752VENDOR_ST_M45PE20:
14439 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14441 case FLASH_5752VENDOR_ST_M45PE40:
14442 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14447 tg3_flag_set(tp, NO_NVRAM);
14451 tg3_nvram_get_pagesize(tp, nvcfg1);
14452 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14453 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14457 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14461 nvcfg1 = tr32(NVRAM_CFG1);
14463 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14464 case FLASH_5717VENDOR_ATMEL_EEPROM:
14465 case FLASH_5717VENDOR_MICRO_EEPROM:
14466 tp->nvram_jedecnum = JEDEC_ATMEL;
14467 tg3_flag_set(tp, NVRAM_BUFFERED);
14468 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14470 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14471 tw32(NVRAM_CFG1, nvcfg1);
14473 case FLASH_5717VENDOR_ATMEL_MDB011D:
14474 case FLASH_5717VENDOR_ATMEL_ADB011B:
14475 case FLASH_5717VENDOR_ATMEL_ADB011D:
14476 case FLASH_5717VENDOR_ATMEL_MDB021D:
14477 case FLASH_5717VENDOR_ATMEL_ADB021B:
14478 case FLASH_5717VENDOR_ATMEL_ADB021D:
14479 case FLASH_5717VENDOR_ATMEL_45USPT:
14480 tp->nvram_jedecnum = JEDEC_ATMEL;
14481 tg3_flag_set(tp, NVRAM_BUFFERED);
14482 tg3_flag_set(tp, FLASH);
14484 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14485 case FLASH_5717VENDOR_ATMEL_MDB021D:
14486 /* Detect size with tg3_nvram_get_size() */
14488 case FLASH_5717VENDOR_ATMEL_ADB021B:
14489 case FLASH_5717VENDOR_ATMEL_ADB021D:
14490 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14493 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14497 case FLASH_5717VENDOR_ST_M_M25PE10:
14498 case FLASH_5717VENDOR_ST_A_M25PE10:
14499 case FLASH_5717VENDOR_ST_M_M45PE10:
14500 case FLASH_5717VENDOR_ST_A_M45PE10:
14501 case FLASH_5717VENDOR_ST_M_M25PE20:
14502 case FLASH_5717VENDOR_ST_A_M25PE20:
14503 case FLASH_5717VENDOR_ST_M_M45PE20:
14504 case FLASH_5717VENDOR_ST_A_M45PE20:
14505 case FLASH_5717VENDOR_ST_25USPT:
14506 case FLASH_5717VENDOR_ST_45USPT:
14507 tp->nvram_jedecnum = JEDEC_ST;
14508 tg3_flag_set(tp, NVRAM_BUFFERED);
14509 tg3_flag_set(tp, FLASH);
14511 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14512 case FLASH_5717VENDOR_ST_M_M25PE20:
14513 case FLASH_5717VENDOR_ST_M_M45PE20:
14514 /* Detect size with tg3_nvram_get_size() */
14516 case FLASH_5717VENDOR_ST_A_M25PE20:
14517 case FLASH_5717VENDOR_ST_A_M45PE20:
14518 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14521 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14526 tg3_flag_set(tp, NO_NVRAM);
14530 tg3_nvram_get_pagesize(tp, nvcfg1);
14531 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14532 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14535 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14537 u32 nvcfg1, nvmpinstrp;
14539 nvcfg1 = tr32(NVRAM_CFG1);
14540 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14542 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14543 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14544 tg3_flag_set(tp, NO_NVRAM);
14548 switch (nvmpinstrp) {
14549 case FLASH_5762_EEPROM_HD:
14550 nvmpinstrp = FLASH_5720_EEPROM_HD;
14552 case FLASH_5762_EEPROM_LD:
14553 nvmpinstrp = FLASH_5720_EEPROM_LD;
14555 case FLASH_5720VENDOR_M_ST_M45PE20:
14556 /* This pinstrap supports multiple sizes, so force it
14557 * to read the actual size from location 0xf0.
14559 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14564 switch (nvmpinstrp) {
14565 case FLASH_5720_EEPROM_HD:
14566 case FLASH_5720_EEPROM_LD:
14567 tp->nvram_jedecnum = JEDEC_ATMEL;
14568 tg3_flag_set(tp, NVRAM_BUFFERED);
14570 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14571 tw32(NVRAM_CFG1, nvcfg1);
14572 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14573 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14575 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14577 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14578 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14579 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14580 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14581 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14582 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14583 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14584 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14585 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14586 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14587 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14588 case FLASH_5720VENDOR_ATMEL_45USPT:
14589 tp->nvram_jedecnum = JEDEC_ATMEL;
14590 tg3_flag_set(tp, NVRAM_BUFFERED);
14591 tg3_flag_set(tp, FLASH);
14593 switch (nvmpinstrp) {
14594 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14595 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14596 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14597 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14599 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14600 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14601 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14602 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14604 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14605 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14606 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14609 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14610 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14614 case FLASH_5720VENDOR_M_ST_M25PE10:
14615 case FLASH_5720VENDOR_M_ST_M45PE10:
14616 case FLASH_5720VENDOR_A_ST_M25PE10:
14617 case FLASH_5720VENDOR_A_ST_M45PE10:
14618 case FLASH_5720VENDOR_M_ST_M25PE20:
14619 case FLASH_5720VENDOR_M_ST_M45PE20:
14620 case FLASH_5720VENDOR_A_ST_M25PE20:
14621 case FLASH_5720VENDOR_A_ST_M45PE20:
14622 case FLASH_5720VENDOR_M_ST_M25PE40:
14623 case FLASH_5720VENDOR_M_ST_M45PE40:
14624 case FLASH_5720VENDOR_A_ST_M25PE40:
14625 case FLASH_5720VENDOR_A_ST_M45PE40:
14626 case FLASH_5720VENDOR_M_ST_M25PE80:
14627 case FLASH_5720VENDOR_M_ST_M45PE80:
14628 case FLASH_5720VENDOR_A_ST_M25PE80:
14629 case FLASH_5720VENDOR_A_ST_M45PE80:
14630 case FLASH_5720VENDOR_ST_25USPT:
14631 case FLASH_5720VENDOR_ST_45USPT:
14632 tp->nvram_jedecnum = JEDEC_ST;
14633 tg3_flag_set(tp, NVRAM_BUFFERED);
14634 tg3_flag_set(tp, FLASH);
14636 switch (nvmpinstrp) {
14637 case FLASH_5720VENDOR_M_ST_M25PE20:
14638 case FLASH_5720VENDOR_M_ST_M45PE20:
14639 case FLASH_5720VENDOR_A_ST_M25PE20:
14640 case FLASH_5720VENDOR_A_ST_M45PE20:
14641 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14643 case FLASH_5720VENDOR_M_ST_M25PE40:
14644 case FLASH_5720VENDOR_M_ST_M45PE40:
14645 case FLASH_5720VENDOR_A_ST_M25PE40:
14646 case FLASH_5720VENDOR_A_ST_M45PE40:
14647 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14649 case FLASH_5720VENDOR_M_ST_M25PE80:
14650 case FLASH_5720VENDOR_M_ST_M45PE80:
14651 case FLASH_5720VENDOR_A_ST_M25PE80:
14652 case FLASH_5720VENDOR_A_ST_M45PE80:
14653 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14656 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14657 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14662 tg3_flag_set(tp, NO_NVRAM);
14666 tg3_nvram_get_pagesize(tp, nvcfg1);
14667 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14668 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14670 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14673 if (tg3_nvram_read(tp, 0, &val))
14676 if (val != TG3_EEPROM_MAGIC &&
14677 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14678 tg3_flag_set(tp, NO_NVRAM);
14682 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14683 static void tg3_nvram_init(struct tg3 *tp)
14685 if (tg3_flag(tp, IS_SSB_CORE)) {
14686 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14687 tg3_flag_clear(tp, NVRAM);
14688 tg3_flag_clear(tp, NVRAM_BUFFERED);
14689 tg3_flag_set(tp, NO_NVRAM);
14693 tw32_f(GRC_EEPROM_ADDR,
14694 (EEPROM_ADDR_FSM_RESET |
14695 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14696 EEPROM_ADDR_CLKPERD_SHIFT)));
14700 /* Enable seeprom accesses. */
14701 tw32_f(GRC_LOCAL_CTRL,
14702 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14705 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14706 tg3_asic_rev(tp) != ASIC_REV_5701) {
14707 tg3_flag_set(tp, NVRAM);
14709 if (tg3_nvram_lock(tp)) {
14710 netdev_warn(tp->dev,
14711 "Cannot get nvram lock, %s failed\n",
14715 tg3_enable_nvram_access(tp);
14717 tp->nvram_size = 0;
14719 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14720 tg3_get_5752_nvram_info(tp);
14721 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14722 tg3_get_5755_nvram_info(tp);
14723 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14724 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14725 tg3_asic_rev(tp) == ASIC_REV_5785)
14726 tg3_get_5787_nvram_info(tp);
14727 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14728 tg3_get_5761_nvram_info(tp);
14729 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14730 tg3_get_5906_nvram_info(tp);
14731 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14732 tg3_flag(tp, 57765_CLASS))
14733 tg3_get_57780_nvram_info(tp);
14734 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14735 tg3_asic_rev(tp) == ASIC_REV_5719)
14736 tg3_get_5717_nvram_info(tp);
14737 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14738 tg3_asic_rev(tp) == ASIC_REV_5762)
14739 tg3_get_5720_nvram_info(tp);
14741 tg3_get_nvram_info(tp);
14743 if (tp->nvram_size == 0)
14744 tg3_get_nvram_size(tp);
14746 tg3_disable_nvram_access(tp);
14747 tg3_nvram_unlock(tp);
14750 tg3_flag_clear(tp, NVRAM);
14751 tg3_flag_clear(tp, NVRAM_BUFFERED);
14753 tg3_get_eeprom_size(tp);
14757 struct subsys_tbl_ent {
14758 u16 subsys_vendor, subsys_devid;
14762 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14763 /* Broadcom boards. */
14764 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14765 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14766 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14767 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14768 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14769 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14770 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14771 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14772 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14773 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14774 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14775 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14776 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14777 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14778 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14779 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14780 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14781 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14782 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14783 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14784 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14785 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14788 { TG3PCI_SUBVENDOR_ID_3COM,
14789 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14790 { TG3PCI_SUBVENDOR_ID_3COM,
14791 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14792 { TG3PCI_SUBVENDOR_ID_3COM,
14793 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14794 { TG3PCI_SUBVENDOR_ID_3COM,
14795 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14796 { TG3PCI_SUBVENDOR_ID_3COM,
14797 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14800 { TG3PCI_SUBVENDOR_ID_DELL,
14801 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14802 { TG3PCI_SUBVENDOR_ID_DELL,
14803 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14804 { TG3PCI_SUBVENDOR_ID_DELL,
14805 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14806 { TG3PCI_SUBVENDOR_ID_DELL,
14807 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14809 /* Compaq boards. */
14810 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14811 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14812 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14813 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14814 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14815 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14816 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14817 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
14818 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14819 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
14822 { TG3PCI_SUBVENDOR_ID_IBM,
14823 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
14826 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
14830 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14831 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14832 tp->pdev->subsystem_vendor) &&
14833 (subsys_id_to_phy_id[i].subsys_devid ==
14834 tp->pdev->subsystem_device))
14835 return &subsys_id_to_phy_id[i];
14840 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
14844 tp->phy_id = TG3_PHY_ID_INVALID;
14845 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14847 /* Assume an onboard device and WOL capable by default. */
14848 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14849 tg3_flag_set(tp, WOL_CAP);
14851 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
14852 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
14853 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14854 tg3_flag_set(tp, IS_NIC);
14856 val = tr32(VCPU_CFGSHDW);
14857 if (val & VCPU_CFGSHDW_ASPM_DBNC)
14858 tg3_flag_set(tp, ASPM_WORKAROUND);
14859 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
14860 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
14861 tg3_flag_set(tp, WOL_ENABLE);
14862 device_set_wakeup_enable(&tp->pdev->dev, true);
14867 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14868 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14869 u32 nic_cfg, led_cfg;
14870 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
14871 int eeprom_phy_serdes = 0;
14873 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14874 tp->nic_sram_data_cfg = nic_cfg;
14876 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14877 ver >>= NIC_SRAM_DATA_VER_SHIFT;
14878 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14879 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14880 tg3_asic_rev(tp) != ASIC_REV_5703 &&
14881 (ver > 0) && (ver < 0x100))
14882 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14884 if (tg3_asic_rev(tp) == ASIC_REV_5785)
14885 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14887 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14888 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14889 eeprom_phy_serdes = 1;
14891 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14892 if (nic_phy_id != 0) {
14893 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14894 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14896 eeprom_phy_id = (id1 >> 16) << 10;
14897 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14898 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14902 tp->phy_id = eeprom_phy_id;
14903 if (eeprom_phy_serdes) {
14904 if (!tg3_flag(tp, 5705_PLUS))
14905 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
14907 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
14910 if (tg3_flag(tp, 5750_PLUS))
14911 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14912 SHASTA_EXT_LED_MODE_MASK);
14914 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14918 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14919 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14922 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14923 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14926 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14927 tp->led_ctrl = LED_CTRL_MODE_MAC;
14929 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14930 * read on some older 5700/5701 bootcode.
14932 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14933 tg3_asic_rev(tp) == ASIC_REV_5701)
14934 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14938 case SHASTA_EXT_LED_SHARED:
14939 tp->led_ctrl = LED_CTRL_MODE_SHARED;
14940 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14941 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
14942 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14943 LED_CTRL_MODE_PHY_2);
14945 if (tg3_flag(tp, 5717_PLUS) ||
14946 tg3_asic_rev(tp) == ASIC_REV_5762)
14947 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
14948 LED_CTRL_BLINK_RATE_MASK;
14952 case SHASTA_EXT_LED_MAC:
14953 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14956 case SHASTA_EXT_LED_COMBO:
14957 tp->led_ctrl = LED_CTRL_MODE_COMBO;
14958 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
14959 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14960 LED_CTRL_MODE_PHY_2);
14965 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14966 tg3_asic_rev(tp) == ASIC_REV_5701) &&
14967 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14968 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14970 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
14971 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14973 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
14974 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14975 if ((tp->pdev->subsystem_vendor ==
14976 PCI_VENDOR_ID_ARIMA) &&
14977 (tp->pdev->subsystem_device == 0x205a ||
14978 tp->pdev->subsystem_device == 0x2063))
14979 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14981 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14982 tg3_flag_set(tp, IS_NIC);
14985 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
14986 tg3_flag_set(tp, ENABLE_ASF);
14987 if (tg3_flag(tp, 5750_PLUS))
14988 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
14991 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
14992 tg3_flag(tp, 5750_PLUS))
14993 tg3_flag_set(tp, ENABLE_APE);
14995 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
14996 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
14997 tg3_flag_clear(tp, WOL_CAP);
14999 if (tg3_flag(tp, WOL_CAP) &&
15000 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15001 tg3_flag_set(tp, WOL_ENABLE);
15002 device_set_wakeup_enable(&tp->pdev->dev, true);
15005 if (cfg2 & (1 << 17))
15006 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15008 /* serdes signal pre-emphasis in register 0x590 set by */
15009 /* bootcode if bit 18 is set */
15010 if (cfg2 & (1 << 18))
15011 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15013 if ((tg3_flag(tp, 57765_PLUS) ||
15014 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15015 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15016 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15017 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15019 if (tg3_flag(tp, PCI_EXPRESS)) {
15022 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15023 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15024 !tg3_flag(tp, 57765_PLUS) &&
15025 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15026 tg3_flag_set(tp, ASPM_WORKAROUND);
15027 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15028 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15029 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15030 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15033 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15034 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15035 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15036 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15037 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15038 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15041 if (tg3_flag(tp, WOL_CAP))
15042 device_set_wakeup_enable(&tp->pdev->dev,
15043 tg3_flag(tp, WOL_ENABLE));
15045 device_set_wakeup_capable(&tp->pdev->dev, false);
15048 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15051 u32 val2, off = offset * 8;
15053 err = tg3_nvram_lock(tp);
15057 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15058 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15059 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15060 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15063 for (i = 0; i < 100; i++) {
15064 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15065 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15066 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15072 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15074 tg3_nvram_unlock(tp);
15075 if (val2 & APE_OTP_STATUS_CMD_DONE)
15081 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15086 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15087 tw32(OTP_CTRL, cmd);
15089 /* Wait for up to 1 ms for command to execute. */
15090 for (i = 0; i < 100; i++) {
15091 val = tr32(OTP_STATUS);
15092 if (val & OTP_STATUS_CMD_DONE)
15097 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15100 /* Read the gphy configuration from the OTP region of the chip. The gphy
15101 * configuration is a 32-bit value that straddles the alignment boundary.
15102 * We do two 32-bit reads and then shift and merge the results.
15104 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15106 u32 bhalf_otp, thalf_otp;
15108 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15110 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15113 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15115 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15118 thalf_otp = tr32(OTP_READ_DATA);
15120 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15122 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15125 bhalf_otp = tr32(OTP_READ_DATA);
15127 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15130 static void tg3_phy_init_link_config(struct tg3 *tp)
15132 u32 adv = ADVERTISED_Autoneg;
15134 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15135 adv |= ADVERTISED_1000baseT_Half |
15136 ADVERTISED_1000baseT_Full;
15138 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15139 adv |= ADVERTISED_100baseT_Half |
15140 ADVERTISED_100baseT_Full |
15141 ADVERTISED_10baseT_Half |
15142 ADVERTISED_10baseT_Full |
15145 adv |= ADVERTISED_FIBRE;
15147 tp->link_config.advertising = adv;
15148 tp->link_config.speed = SPEED_UNKNOWN;
15149 tp->link_config.duplex = DUPLEX_UNKNOWN;
15150 tp->link_config.autoneg = AUTONEG_ENABLE;
15151 tp->link_config.active_speed = SPEED_UNKNOWN;
15152 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15157 static int tg3_phy_probe(struct tg3 *tp)
15159 u32 hw_phy_id_1, hw_phy_id_2;
15160 u32 hw_phy_id, hw_phy_id_masked;
15163 /* flow control autonegotiation is default behavior */
15164 tg3_flag_set(tp, PAUSE_AUTONEG);
15165 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15167 if (tg3_flag(tp, ENABLE_APE)) {
15168 switch (tp->pci_fn) {
15170 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15173 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15176 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15179 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15184 if (!tg3_flag(tp, ENABLE_ASF) &&
15185 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15186 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15187 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15188 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15190 if (tg3_flag(tp, USE_PHYLIB))
15191 return tg3_phy_init(tp);
15193 /* Reading the PHY ID register can conflict with ASF
15194 * firmware access to the PHY hardware.
15197 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15198 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15200 /* Now read the physical PHY_ID from the chip and verify
15201 * that it is sane. If it doesn't look good, we fall back
15202 * to either the hard-coded table based PHY_ID and failing
15203 * that the value found in the eeprom area.
15205 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15206 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15208 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15209 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15210 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15212 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15215 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15216 tp->phy_id = hw_phy_id;
15217 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15218 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15220 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15222 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15223 /* Do nothing, phy ID already set up in
15224 * tg3_get_eeprom_hw_cfg().
15227 struct subsys_tbl_ent *p;
15229 /* No eeprom signature? Try the hardcoded
15230 * subsys device table.
15232 p = tg3_lookup_by_subsys(tp);
15234 tp->phy_id = p->phy_id;
15235 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15236 /* For now we saw the IDs 0xbc050cd0,
15237 * 0xbc050f80 and 0xbc050c30 on devices
15238 * connected to an BCM4785 and there are
15239 * probably more. Just assume that the phy is
15240 * supported when it is connected to a SSB core
15247 tp->phy_id == TG3_PHY_ID_BCM8002)
15248 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15252 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15253 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15254 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15255 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15256 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15257 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15258 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15259 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15260 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15261 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15263 tp->eee.supported = SUPPORTED_100baseT_Full |
15264 SUPPORTED_1000baseT_Full;
15265 tp->eee.advertised = ADVERTISED_100baseT_Full |
15266 ADVERTISED_1000baseT_Full;
15267 tp->eee.eee_enabled = 1;
15268 tp->eee.tx_lpi_enabled = 1;
15269 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15272 tg3_phy_init_link_config(tp);
15274 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15275 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15276 !tg3_flag(tp, ENABLE_APE) &&
15277 !tg3_flag(tp, ENABLE_ASF)) {
15280 tg3_readphy(tp, MII_BMSR, &bmsr);
15281 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15282 (bmsr & BMSR_LSTATUS))
15283 goto skip_phy_reset;
15285 err = tg3_phy_reset(tp);
15289 tg3_phy_set_wirespeed(tp);
15291 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15292 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15293 tp->link_config.flowctrl);
15295 tg3_writephy(tp, MII_BMCR,
15296 BMCR_ANENABLE | BMCR_ANRESTART);
15301 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15302 err = tg3_init_5401phy_dsp(tp);
15306 err = tg3_init_5401phy_dsp(tp);
15312 static void tg3_read_vpd(struct tg3 *tp)
15315 unsigned int block_end, rosize, len;
15319 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15323 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15325 goto out_not_found;
15327 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15328 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15329 i += PCI_VPD_LRDT_TAG_SIZE;
15331 if (block_end > vpdlen)
15332 goto out_not_found;
15334 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15335 PCI_VPD_RO_KEYWORD_MFR_ID);
15337 len = pci_vpd_info_field_size(&vpd_data[j]);
15339 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15340 if (j + len > block_end || len != 4 ||
15341 memcmp(&vpd_data[j], "1028", 4))
15344 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15345 PCI_VPD_RO_KEYWORD_VENDOR0);
15349 len = pci_vpd_info_field_size(&vpd_data[j]);
15351 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15352 if (j + len > block_end)
15355 if (len >= sizeof(tp->fw_ver))
15356 len = sizeof(tp->fw_ver) - 1;
15357 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15358 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15363 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15364 PCI_VPD_RO_KEYWORD_PARTNO);
15366 goto out_not_found;
15368 len = pci_vpd_info_field_size(&vpd_data[i]);
15370 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15371 if (len > TG3_BPN_SIZE ||
15372 (len + i) > vpdlen)
15373 goto out_not_found;
15375 memcpy(tp->board_part_number, &vpd_data[i], len);
15379 if (tp->board_part_number[0])
15383 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15384 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15385 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15386 strcpy(tp->board_part_number, "BCM5717");
15387 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15388 strcpy(tp->board_part_number, "BCM5718");
15391 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15392 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15393 strcpy(tp->board_part_number, "BCM57780");
15394 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15395 strcpy(tp->board_part_number, "BCM57760");
15396 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15397 strcpy(tp->board_part_number, "BCM57790");
15398 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15399 strcpy(tp->board_part_number, "BCM57788");
15402 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15403 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15404 strcpy(tp->board_part_number, "BCM57761");
15405 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15406 strcpy(tp->board_part_number, "BCM57765");
15407 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15408 strcpy(tp->board_part_number, "BCM57781");
15409 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15410 strcpy(tp->board_part_number, "BCM57785");
15411 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15412 strcpy(tp->board_part_number, "BCM57791");
15413 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15414 strcpy(tp->board_part_number, "BCM57795");
15417 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15418 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15419 strcpy(tp->board_part_number, "BCM57762");
15420 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15421 strcpy(tp->board_part_number, "BCM57766");
15422 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15423 strcpy(tp->board_part_number, "BCM57782");
15424 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15425 strcpy(tp->board_part_number, "BCM57786");
15428 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15429 strcpy(tp->board_part_number, "BCM95906");
15432 strcpy(tp->board_part_number, "none");
15436 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15440 if (tg3_nvram_read(tp, offset, &val) ||
15441 (val & 0xfc000000) != 0x0c000000 ||
15442 tg3_nvram_read(tp, offset + 4, &val) ||
15449 static void tg3_read_bc_ver(struct tg3 *tp)
15451 u32 val, offset, start, ver_offset;
15453 bool newver = false;
15455 if (tg3_nvram_read(tp, 0xc, &offset) ||
15456 tg3_nvram_read(tp, 0x4, &start))
15459 offset = tg3_nvram_logical_addr(tp, offset);
15461 if (tg3_nvram_read(tp, offset, &val))
15464 if ((val & 0xfc000000) == 0x0c000000) {
15465 if (tg3_nvram_read(tp, offset + 4, &val))
15472 dst_off = strlen(tp->fw_ver);
15475 if (TG3_VER_SIZE - dst_off < 16 ||
15476 tg3_nvram_read(tp, offset + 8, &ver_offset))
15479 offset = offset + ver_offset - start;
15480 for (i = 0; i < 16; i += 4) {
15482 if (tg3_nvram_read_be32(tp, offset + i, &v))
15485 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15490 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15493 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15494 TG3_NVM_BCVER_MAJSFT;
15495 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15496 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15497 "v%d.%02d", major, minor);
15501 static void tg3_read_hwsb_ver(struct tg3 *tp)
15503 u32 val, major, minor;
15505 /* Use native endian representation */
15506 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15509 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15510 TG3_NVM_HWSB_CFG1_MAJSFT;
15511 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15512 TG3_NVM_HWSB_CFG1_MINSFT;
15514 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15517 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15519 u32 offset, major, minor, build;
15521 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15523 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15526 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15527 case TG3_EEPROM_SB_REVISION_0:
15528 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15530 case TG3_EEPROM_SB_REVISION_2:
15531 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15533 case TG3_EEPROM_SB_REVISION_3:
15534 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15536 case TG3_EEPROM_SB_REVISION_4:
15537 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15539 case TG3_EEPROM_SB_REVISION_5:
15540 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15542 case TG3_EEPROM_SB_REVISION_6:
15543 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15549 if (tg3_nvram_read(tp, offset, &val))
15552 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15553 TG3_EEPROM_SB_EDH_BLD_SHFT;
15554 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15555 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15556 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15558 if (minor > 99 || build > 26)
15561 offset = strlen(tp->fw_ver);
15562 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15563 " v%d.%02d", major, minor);
15566 offset = strlen(tp->fw_ver);
15567 if (offset < TG3_VER_SIZE - 1)
15568 tp->fw_ver[offset] = 'a' + build - 1;
15572 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15574 u32 val, offset, start;
15577 for (offset = TG3_NVM_DIR_START;
15578 offset < TG3_NVM_DIR_END;
15579 offset += TG3_NVM_DIRENT_SIZE) {
15580 if (tg3_nvram_read(tp, offset, &val))
15583 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15587 if (offset == TG3_NVM_DIR_END)
15590 if (!tg3_flag(tp, 5705_PLUS))
15591 start = 0x08000000;
15592 else if (tg3_nvram_read(tp, offset - 4, &start))
15595 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15596 !tg3_fw_img_is_valid(tp, offset) ||
15597 tg3_nvram_read(tp, offset + 8, &val))
15600 offset += val - start;
15602 vlen = strlen(tp->fw_ver);
15604 tp->fw_ver[vlen++] = ',';
15605 tp->fw_ver[vlen++] = ' ';
15607 for (i = 0; i < 4; i++) {
15609 if (tg3_nvram_read_be32(tp, offset, &v))
15612 offset += sizeof(v);
15614 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15615 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15619 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15624 static void tg3_probe_ncsi(struct tg3 *tp)
15628 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15629 if (apedata != APE_SEG_SIG_MAGIC)
15632 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15633 if (!(apedata & APE_FW_STATUS_READY))
15636 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15637 tg3_flag_set(tp, APE_HAS_NCSI);
15640 static void tg3_read_dash_ver(struct tg3 *tp)
15646 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15648 if (tg3_flag(tp, APE_HAS_NCSI))
15650 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15655 vlen = strlen(tp->fw_ver);
15657 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15659 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15660 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15661 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15662 (apedata & APE_FW_VERSION_BLDMSK));
15665 static void tg3_read_otp_ver(struct tg3 *tp)
15669 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15672 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15673 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15674 TG3_OTP_MAGIC0_VALID(val)) {
15675 u64 val64 = (u64) val << 32 | val2;
15679 for (i = 0; i < 7; i++) {
15680 if ((val64 & 0xff) == 0)
15682 ver = val64 & 0xff;
15685 vlen = strlen(tp->fw_ver);
15686 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15690 static void tg3_read_fw_ver(struct tg3 *tp)
15693 bool vpd_vers = false;
15695 if (tp->fw_ver[0] != 0)
15698 if (tg3_flag(tp, NO_NVRAM)) {
15699 strcat(tp->fw_ver, "sb");
15700 tg3_read_otp_ver(tp);
15704 if (tg3_nvram_read(tp, 0, &val))
15707 if (val == TG3_EEPROM_MAGIC)
15708 tg3_read_bc_ver(tp);
15709 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15710 tg3_read_sb_ver(tp, val);
15711 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15712 tg3_read_hwsb_ver(tp);
15714 if (tg3_flag(tp, ENABLE_ASF)) {
15715 if (tg3_flag(tp, ENABLE_APE)) {
15716 tg3_probe_ncsi(tp);
15718 tg3_read_dash_ver(tp);
15719 } else if (!vpd_vers) {
15720 tg3_read_mgmtfw_ver(tp);
15724 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15727 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15729 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15730 return TG3_RX_RET_MAX_SIZE_5717;
15731 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15732 return TG3_RX_RET_MAX_SIZE_5700;
15734 return TG3_RX_RET_MAX_SIZE_5705;
15737 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
15738 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15739 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15740 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15744 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15746 struct pci_dev *peer;
15747 unsigned int func, devnr = tp->pdev->devfn & ~7;
15749 for (func = 0; func < 8; func++) {
15750 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15751 if (peer && peer != tp->pdev)
15755 /* 5704 can be configured in single-port mode, set peer to
15756 * tp->pdev in that case.
15764 * We don't need to keep the refcount elevated; there's no way
15765 * to remove one half of this device without removing the other
15772 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15774 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15775 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15778 /* All devices that use the alternate
15779 * ASIC REV location have a CPMU.
15781 tg3_flag_set(tp, CPMU_PRESENT);
15783 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15786 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15787 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15788 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15789 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
15790 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
15794 reg = TG3PCI_GEN2_PRODID_ASICREV;
15795 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15796 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15797 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15800 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15801 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15802 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15803 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15804 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15805 reg = TG3PCI_GEN15_PRODID_ASICREV;
15807 reg = TG3PCI_PRODID_ASICREV;
15809 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15812 /* Wrong chip ID in 5752 A0. This code can be removed later
15813 * as A0 is not in production.
15815 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
15816 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15818 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
15819 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15821 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15822 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15823 tg3_asic_rev(tp) == ASIC_REV_5720)
15824 tg3_flag_set(tp, 5717_PLUS);
15826 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15827 tg3_asic_rev(tp) == ASIC_REV_57766)
15828 tg3_flag_set(tp, 57765_CLASS);
15830 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
15831 tg3_asic_rev(tp) == ASIC_REV_5762)
15832 tg3_flag_set(tp, 57765_PLUS);
15834 /* Intentionally exclude ASIC_REV_5906 */
15835 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15836 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15837 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15838 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15839 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15840 tg3_asic_rev(tp) == ASIC_REV_57780 ||
15841 tg3_flag(tp, 57765_PLUS))
15842 tg3_flag_set(tp, 5755_PLUS);
15844 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15845 tg3_asic_rev(tp) == ASIC_REV_5714)
15846 tg3_flag_set(tp, 5780_CLASS);
15848 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15849 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15850 tg3_asic_rev(tp) == ASIC_REV_5906 ||
15851 tg3_flag(tp, 5755_PLUS) ||
15852 tg3_flag(tp, 5780_CLASS))
15853 tg3_flag_set(tp, 5750_PLUS);
15855 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
15856 tg3_flag(tp, 5750_PLUS))
15857 tg3_flag_set(tp, 5705_PLUS);
15860 static bool tg3_10_100_only_device(struct tg3 *tp,
15861 const struct pci_device_id *ent)
15863 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15865 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15866 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15867 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15870 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
15871 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
15872 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15882 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
15885 u32 pci_state_reg, grc_misc_cfg;
15890 /* Force memory write invalidate off. If we leave it on,
15891 * then on 5700_BX chips we have to enable a workaround.
15892 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15893 * to match the cacheline size. The Broadcom driver have this
15894 * workaround but turns MWI off all the times so never uses
15895 * it. This seems to suggest that the workaround is insufficient.
15897 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15898 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15899 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15901 /* Important! -- Make sure register accesses are byteswapped
15902 * correctly. Also, for those chips that require it, make
15903 * sure that indirect register accesses are enabled before
15904 * the first operation.
15906 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15908 tp->misc_host_ctrl |= (misc_ctrl_reg &
15909 MISC_HOST_CTRL_CHIPREV);
15910 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15911 tp->misc_host_ctrl);
15913 tg3_detect_asic_rev(tp, misc_ctrl_reg);
15915 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15916 * we need to disable memory and use config. cycles
15917 * only to access all registers. The 5702/03 chips
15918 * can mistakenly decode the special cycles from the
15919 * ICH chipsets as memory write cycles, causing corruption
15920 * of register and memory space. Only certain ICH bridges
15921 * will drive special cycles with non-zero data during the
15922 * address phase which can fall within the 5703's address
15923 * range. This is not an ICH bug as the PCI spec allows
15924 * non-zero address during special cycles. However, only
15925 * these ICH bridges are known to drive non-zero addresses
15926 * during special cycles.
15928 * Since special cycles do not cross PCI bridges, we only
15929 * enable this workaround if the 5703 is on the secondary
15930 * bus of these ICH bridges.
15932 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15933 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
15934 static struct tg3_dev_id {
15938 } ich_chipsets[] = {
15939 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15941 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15943 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15945 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15949 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15950 struct pci_dev *bridge = NULL;
15952 while (pci_id->vendor != 0) {
15953 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15959 if (pci_id->rev != PCI_ANY_ID) {
15960 if (bridge->revision > pci_id->rev)
15963 if (bridge->subordinate &&
15964 (bridge->subordinate->number ==
15965 tp->pdev->bus->number)) {
15966 tg3_flag_set(tp, ICH_WORKAROUND);
15967 pci_dev_put(bridge);
15973 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
15974 static struct tg3_dev_id {
15977 } bridge_chipsets[] = {
15978 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15979 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15982 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15983 struct pci_dev *bridge = NULL;
15985 while (pci_id->vendor != 0) {
15986 bridge = pci_get_device(pci_id->vendor,
15993 if (bridge->subordinate &&
15994 (bridge->subordinate->number <=
15995 tp->pdev->bus->number) &&
15996 (bridge->subordinate->busn_res.end >=
15997 tp->pdev->bus->number)) {
15998 tg3_flag_set(tp, 5701_DMA_BUG);
15999 pci_dev_put(bridge);
16005 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16006 * DMA addresses > 40-bit. This bridge may have other additional
16007 * 57xx devices behind it in some 4-port NIC designs for example.
16008 * Any tg3 device found behind the bridge will also need the 40-bit
16011 if (tg3_flag(tp, 5780_CLASS)) {
16012 tg3_flag_set(tp, 40BIT_DMA_BUG);
16013 tp->msi_cap = tp->pdev->msi_cap;
16015 struct pci_dev *bridge = NULL;
16018 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16019 PCI_DEVICE_ID_SERVERWORKS_EPB,
16021 if (bridge && bridge->subordinate &&
16022 (bridge->subordinate->number <=
16023 tp->pdev->bus->number) &&
16024 (bridge->subordinate->busn_res.end >=
16025 tp->pdev->bus->number)) {
16026 tg3_flag_set(tp, 40BIT_DMA_BUG);
16027 pci_dev_put(bridge);
16033 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16034 tg3_asic_rev(tp) == ASIC_REV_5714)
16035 tp->pdev_peer = tg3_find_peer(tp);
16037 /* Determine TSO capabilities */
16038 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16039 ; /* Do nothing. HW bug. */
16040 else if (tg3_flag(tp, 57765_PLUS))
16041 tg3_flag_set(tp, HW_TSO_3);
16042 else if (tg3_flag(tp, 5755_PLUS) ||
16043 tg3_asic_rev(tp) == ASIC_REV_5906)
16044 tg3_flag_set(tp, HW_TSO_2);
16045 else if (tg3_flag(tp, 5750_PLUS)) {
16046 tg3_flag_set(tp, HW_TSO_1);
16047 tg3_flag_set(tp, TSO_BUG);
16048 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16049 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16050 tg3_flag_clear(tp, TSO_BUG);
16051 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16052 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16053 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16054 tg3_flag_set(tp, FW_TSO);
16055 tg3_flag_set(tp, TSO_BUG);
16056 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16057 tp->fw_needed = FIRMWARE_TG3TSO5;
16059 tp->fw_needed = FIRMWARE_TG3TSO;
16062 /* Selectively allow TSO based on operating conditions */
16063 if (tg3_flag(tp, HW_TSO_1) ||
16064 tg3_flag(tp, HW_TSO_2) ||
16065 tg3_flag(tp, HW_TSO_3) ||
16066 tg3_flag(tp, FW_TSO)) {
16067 /* For firmware TSO, assume ASF is disabled.
16068 * We'll disable TSO later if we discover ASF
16069 * is enabled in tg3_get_eeprom_hw_cfg().
16071 tg3_flag_set(tp, TSO_CAPABLE);
16073 tg3_flag_clear(tp, TSO_CAPABLE);
16074 tg3_flag_clear(tp, TSO_BUG);
16075 tp->fw_needed = NULL;
16078 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16079 tp->fw_needed = FIRMWARE_TG3;
16081 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16082 tp->fw_needed = FIRMWARE_TG357766;
16086 if (tg3_flag(tp, 5750_PLUS)) {
16087 tg3_flag_set(tp, SUPPORT_MSI);
16088 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16089 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16090 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16091 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16092 tp->pdev_peer == tp->pdev))
16093 tg3_flag_clear(tp, SUPPORT_MSI);
16095 if (tg3_flag(tp, 5755_PLUS) ||
16096 tg3_asic_rev(tp) == ASIC_REV_5906) {
16097 tg3_flag_set(tp, 1SHOT_MSI);
16100 if (tg3_flag(tp, 57765_PLUS)) {
16101 tg3_flag_set(tp, SUPPORT_MSIX);
16102 tp->irq_max = TG3_IRQ_MAX_VECS;
16108 if (tp->irq_max > 1) {
16109 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16110 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16112 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16113 tg3_asic_rev(tp) == ASIC_REV_5720)
16114 tp->txq_max = tp->irq_max - 1;
16117 if (tg3_flag(tp, 5755_PLUS) ||
16118 tg3_asic_rev(tp) == ASIC_REV_5906)
16119 tg3_flag_set(tp, SHORT_DMA_BUG);
16121 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16122 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16124 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16125 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16126 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16127 tg3_asic_rev(tp) == ASIC_REV_5762)
16128 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16130 if (tg3_flag(tp, 57765_PLUS) &&
16131 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16132 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16134 if (!tg3_flag(tp, 5705_PLUS) ||
16135 tg3_flag(tp, 5780_CLASS) ||
16136 tg3_flag(tp, USE_JUMBO_BDFLAG))
16137 tg3_flag_set(tp, JUMBO_CAPABLE);
16139 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16142 if (pci_is_pcie(tp->pdev)) {
16145 tg3_flag_set(tp, PCI_EXPRESS);
16147 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16148 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16149 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16150 tg3_flag_clear(tp, HW_TSO_2);
16151 tg3_flag_clear(tp, TSO_CAPABLE);
16153 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16154 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16155 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16156 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16157 tg3_flag_set(tp, CLKREQ_BUG);
16158 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16159 tg3_flag_set(tp, L1PLLPD_EN);
16161 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16162 /* BCM5785 devices are effectively PCIe devices, and should
16163 * follow PCIe codepaths, but do not have a PCIe capabilities
16166 tg3_flag_set(tp, PCI_EXPRESS);
16167 } else if (!tg3_flag(tp, 5705_PLUS) ||
16168 tg3_flag(tp, 5780_CLASS)) {
16169 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16170 if (!tp->pcix_cap) {
16171 dev_err(&tp->pdev->dev,
16172 "Cannot find PCI-X capability, aborting\n");
16176 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16177 tg3_flag_set(tp, PCIX_MODE);
16180 /* If we have an AMD 762 or VIA K8T800 chipset, write
16181 * reordering to the mailbox registers done by the host
16182 * controller can cause major troubles. We read back from
16183 * every mailbox register write to force the writes to be
16184 * posted to the chip in order.
16186 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16187 !tg3_flag(tp, PCI_EXPRESS))
16188 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16190 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16191 &tp->pci_cacheline_sz);
16192 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16193 &tp->pci_lat_timer);
16194 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16195 tp->pci_lat_timer < 64) {
16196 tp->pci_lat_timer = 64;
16197 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16198 tp->pci_lat_timer);
16201 /* Important! -- It is critical that the PCI-X hw workaround
16202 * situation is decided before the first MMIO register access.
16204 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16205 /* 5700 BX chips need to have their TX producer index
16206 * mailboxes written twice to workaround a bug.
16208 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16210 /* If we are in PCI-X mode, enable register write workaround.
16212 * The workaround is to use indirect register accesses
16213 * for all chip writes not to mailbox registers.
16215 if (tg3_flag(tp, PCIX_MODE)) {
16218 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16220 /* The chip can have it's power management PCI config
16221 * space registers clobbered due to this bug.
16222 * So explicitly force the chip into D0 here.
16224 pci_read_config_dword(tp->pdev,
16225 tp->pdev->pm_cap + PCI_PM_CTRL,
16227 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16228 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16229 pci_write_config_dword(tp->pdev,
16230 tp->pdev->pm_cap + PCI_PM_CTRL,
16233 /* Also, force SERR#/PERR# in PCI command. */
16234 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16235 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16236 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16240 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16241 tg3_flag_set(tp, PCI_HIGH_SPEED);
16242 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16243 tg3_flag_set(tp, PCI_32BIT);
16245 /* Chip-specific fixup from Broadcom driver */
16246 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16247 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16248 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16249 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16252 /* Default fast path register access methods */
16253 tp->read32 = tg3_read32;
16254 tp->write32 = tg3_write32;
16255 tp->read32_mbox = tg3_read32;
16256 tp->write32_mbox = tg3_write32;
16257 tp->write32_tx_mbox = tg3_write32;
16258 tp->write32_rx_mbox = tg3_write32;
16260 /* Various workaround register access methods */
16261 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16262 tp->write32 = tg3_write_indirect_reg32;
16263 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16264 (tg3_flag(tp, PCI_EXPRESS) &&
16265 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16267 * Back to back register writes can cause problems on these
16268 * chips, the workaround is to read back all reg writes
16269 * except those to mailbox regs.
16271 * See tg3_write_indirect_reg32().
16273 tp->write32 = tg3_write_flush_reg32;
16276 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16277 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16278 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16279 tp->write32_rx_mbox = tg3_write_flush_reg32;
16282 if (tg3_flag(tp, ICH_WORKAROUND)) {
16283 tp->read32 = tg3_read_indirect_reg32;
16284 tp->write32 = tg3_write_indirect_reg32;
16285 tp->read32_mbox = tg3_read_indirect_mbox;
16286 tp->write32_mbox = tg3_write_indirect_mbox;
16287 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16288 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16293 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16294 pci_cmd &= ~PCI_COMMAND_MEMORY;
16295 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16297 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16298 tp->read32_mbox = tg3_read32_mbox_5906;
16299 tp->write32_mbox = tg3_write32_mbox_5906;
16300 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16301 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16304 if (tp->write32 == tg3_write_indirect_reg32 ||
16305 (tg3_flag(tp, PCIX_MODE) &&
16306 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16307 tg3_asic_rev(tp) == ASIC_REV_5701)))
16308 tg3_flag_set(tp, SRAM_USE_CONFIG);
16310 /* The memory arbiter has to be enabled in order for SRAM accesses
16311 * to succeed. Normally on powerup the tg3 chip firmware will make
16312 * sure it is enabled, but other entities such as system netboot
16313 * code might disable it.
16315 val = tr32(MEMARB_MODE);
16316 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16318 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16319 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16320 tg3_flag(tp, 5780_CLASS)) {
16321 if (tg3_flag(tp, PCIX_MODE)) {
16322 pci_read_config_dword(tp->pdev,
16323 tp->pcix_cap + PCI_X_STATUS,
16325 tp->pci_fn = val & 0x7;
16327 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16328 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16329 tg3_asic_rev(tp) == ASIC_REV_5720) {
16330 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16331 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16332 val = tr32(TG3_CPMU_STATUS);
16334 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16335 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16337 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16338 TG3_CPMU_STATUS_FSHFT_5719;
16341 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16342 tp->write32_tx_mbox = tg3_write_flush_reg32;
16343 tp->write32_rx_mbox = tg3_write_flush_reg32;
16346 /* Get eeprom hw config before calling tg3_set_power_state().
16347 * In particular, the TG3_FLAG_IS_NIC flag must be
16348 * determined before calling tg3_set_power_state() so that
16349 * we know whether or not to switch out of Vaux power.
16350 * When the flag is set, it means that GPIO1 is used for eeprom
16351 * write protect and also implies that it is a LOM where GPIOs
16352 * are not used to switch power.
16354 tg3_get_eeprom_hw_cfg(tp);
16356 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16357 tg3_flag_clear(tp, TSO_CAPABLE);
16358 tg3_flag_clear(tp, TSO_BUG);
16359 tp->fw_needed = NULL;
16362 if (tg3_flag(tp, ENABLE_APE)) {
16363 /* Allow reads and writes to the
16364 * APE register and memory space.
16366 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16367 PCISTATE_ALLOW_APE_SHMEM_WR |
16368 PCISTATE_ALLOW_APE_PSPACE_WR;
16369 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16372 tg3_ape_lock_init(tp);
16375 /* Set up tp->grc_local_ctrl before calling
16376 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16377 * will bring 5700's external PHY out of reset.
16378 * It is also used as eeprom write protect on LOMs.
16380 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16381 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16382 tg3_flag(tp, EEPROM_WRITE_PROT))
16383 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16384 GRC_LCLCTRL_GPIO_OUTPUT1);
16385 /* Unused GPIO3 must be driven as output on 5752 because there
16386 * are no pull-up resistors on unused GPIO pins.
16388 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16389 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16391 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16392 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16393 tg3_flag(tp, 57765_CLASS))
16394 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16396 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16397 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16398 /* Turn off the debug UART. */
16399 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16400 if (tg3_flag(tp, IS_NIC))
16401 /* Keep VMain power. */
16402 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16403 GRC_LCLCTRL_GPIO_OUTPUT0;
16406 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16407 tp->grc_local_ctrl |=
16408 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16410 /* Switch out of Vaux if it is a NIC */
16411 tg3_pwrsrc_switch_to_vmain(tp);
16413 /* Derive initial jumbo mode from MTU assigned in
16414 * ether_setup() via the alloc_etherdev() call
16416 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16417 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16419 /* Determine WakeOnLan speed to use. */
16420 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16421 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16422 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16423 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16424 tg3_flag_clear(tp, WOL_SPEED_100MB);
16426 tg3_flag_set(tp, WOL_SPEED_100MB);
16429 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16430 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16432 /* A few boards don't want Ethernet@WireSpeed phy feature */
16433 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16434 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16435 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16436 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16437 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16438 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16439 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16441 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16442 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16443 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16444 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16445 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16447 if (tg3_flag(tp, 5705_PLUS) &&
16448 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16449 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16450 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16451 !tg3_flag(tp, 57765_PLUS)) {
16452 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16453 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16454 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16455 tg3_asic_rev(tp) == ASIC_REV_5761) {
16456 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16457 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16458 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16459 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16460 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16462 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16465 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16466 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16467 tp->phy_otp = tg3_read_otp_phycfg(tp);
16468 if (tp->phy_otp == 0)
16469 tp->phy_otp = TG3_OTP_DEFAULT;
16472 if (tg3_flag(tp, CPMU_PRESENT))
16473 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16475 tp->mi_mode = MAC_MI_MODE_BASE;
16477 tp->coalesce_mode = 0;
16478 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16479 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16480 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16482 /* Set these bits to enable statistics workaround. */
16483 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16484 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16485 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16486 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16487 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16490 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16491 tg3_asic_rev(tp) == ASIC_REV_57780)
16492 tg3_flag_set(tp, USE_PHYLIB);
16494 err = tg3_mdio_init(tp);
16498 /* Initialize data/descriptor byte/word swapping. */
16499 val = tr32(GRC_MODE);
16500 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16501 tg3_asic_rev(tp) == ASIC_REV_5762)
16502 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16503 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16504 GRC_MODE_B2HRX_ENABLE |
16505 GRC_MODE_HTX2B_ENABLE |
16506 GRC_MODE_HOST_STACKUP);
16508 val &= GRC_MODE_HOST_STACKUP;
16510 tw32(GRC_MODE, val | tp->grc_mode);
16512 tg3_switch_clocks(tp);
16514 /* Clear this out for sanity. */
16515 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16517 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16519 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16520 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16521 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16522 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16523 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16524 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16525 void __iomem *sram_base;
16527 /* Write some dummy words into the SRAM status block
16528 * area, see if it reads back correctly. If the return
16529 * value is bad, force enable the PCIX workaround.
16531 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16533 writel(0x00000000, sram_base);
16534 writel(0x00000000, sram_base + 4);
16535 writel(0xffffffff, sram_base + 4);
16536 if (readl(sram_base) != 0x00000000)
16537 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16542 tg3_nvram_init(tp);
16544 /* If the device has an NVRAM, no need to load patch firmware */
16545 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16546 !tg3_flag(tp, NO_NVRAM))
16547 tp->fw_needed = NULL;
16549 grc_misc_cfg = tr32(GRC_MISC_CFG);
16550 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16552 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16553 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16554 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16555 tg3_flag_set(tp, IS_5788);
16557 if (!tg3_flag(tp, IS_5788) &&
16558 tg3_asic_rev(tp) != ASIC_REV_5700)
16559 tg3_flag_set(tp, TAGGED_STATUS);
16560 if (tg3_flag(tp, TAGGED_STATUS)) {
16561 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16562 HOSTCC_MODE_CLRTICK_TXBD);
16564 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16565 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16566 tp->misc_host_ctrl);
16569 /* Preserve the APE MAC_MODE bits */
16570 if (tg3_flag(tp, ENABLE_APE))
16571 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16575 if (tg3_10_100_only_device(tp, ent))
16576 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16578 err = tg3_phy_probe(tp);
16580 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16581 /* ... but do not return immediately ... */
16586 tg3_read_fw_ver(tp);
16588 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16589 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16591 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16592 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16594 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16597 /* 5700 {AX,BX} chips have a broken status block link
16598 * change bit implementation, so we must use the
16599 * status register in those cases.
16601 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16602 tg3_flag_set(tp, USE_LINKCHG_REG);
16604 tg3_flag_clear(tp, USE_LINKCHG_REG);
16606 /* The led_ctrl is set during tg3_phy_probe, here we might
16607 * have to force the link status polling mechanism based
16608 * upon subsystem IDs.
16610 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16611 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16612 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16613 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16614 tg3_flag_set(tp, USE_LINKCHG_REG);
16617 /* For all SERDES we poll the MAC status register. */
16618 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16619 tg3_flag_set(tp, POLL_SERDES);
16621 tg3_flag_clear(tp, POLL_SERDES);
16623 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16624 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16625 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16626 tg3_flag(tp, PCIX_MODE)) {
16627 tp->rx_offset = NET_SKB_PAD;
16628 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16629 tp->rx_copy_thresh = ~(u16)0;
16633 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16634 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16635 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16637 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16639 /* Increment the rx prod index on the rx std ring by at most
16640 * 8 for these chips to workaround hw errata.
16642 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16643 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16644 tg3_asic_rev(tp) == ASIC_REV_5755)
16645 tp->rx_std_max_post = 8;
16647 if (tg3_flag(tp, ASPM_WORKAROUND))
16648 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16649 PCIE_PWR_MGMT_L1_THRESH_MSK;
16654 #ifdef CONFIG_SPARC
16655 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16657 struct net_device *dev = tp->dev;
16658 struct pci_dev *pdev = tp->pdev;
16659 struct device_node *dp = pci_device_to_OF_node(pdev);
16660 const unsigned char *addr;
16663 addr = of_get_property(dp, "local-mac-address", &len);
16664 if (addr && len == ETH_ALEN) {
16665 memcpy(dev->dev_addr, addr, ETH_ALEN);
16671 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16673 struct net_device *dev = tp->dev;
16675 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16680 static int tg3_get_device_address(struct tg3 *tp)
16682 struct net_device *dev = tp->dev;
16683 u32 hi, lo, mac_offset;
16687 #ifdef CONFIG_SPARC
16688 if (!tg3_get_macaddr_sparc(tp))
16692 if (tg3_flag(tp, IS_SSB_CORE)) {
16693 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16694 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16699 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16700 tg3_flag(tp, 5780_CLASS)) {
16701 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16703 if (tg3_nvram_lock(tp))
16704 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16706 tg3_nvram_unlock(tp);
16707 } else if (tg3_flag(tp, 5717_PLUS)) {
16708 if (tp->pci_fn & 1)
16710 if (tp->pci_fn > 1)
16711 mac_offset += 0x18c;
16712 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16715 /* First try to get it from MAC address mailbox. */
16716 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16717 if ((hi >> 16) == 0x484b) {
16718 dev->dev_addr[0] = (hi >> 8) & 0xff;
16719 dev->dev_addr[1] = (hi >> 0) & 0xff;
16721 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16722 dev->dev_addr[2] = (lo >> 24) & 0xff;
16723 dev->dev_addr[3] = (lo >> 16) & 0xff;
16724 dev->dev_addr[4] = (lo >> 8) & 0xff;
16725 dev->dev_addr[5] = (lo >> 0) & 0xff;
16727 /* Some old bootcode may report a 0 MAC address in SRAM */
16728 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16731 /* Next, try NVRAM. */
16732 if (!tg3_flag(tp, NO_NVRAM) &&
16733 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16734 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16735 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16736 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16738 /* Finally just fetch it out of the MAC control regs. */
16740 hi = tr32(MAC_ADDR_0_HIGH);
16741 lo = tr32(MAC_ADDR_0_LOW);
16743 dev->dev_addr[5] = lo & 0xff;
16744 dev->dev_addr[4] = (lo >> 8) & 0xff;
16745 dev->dev_addr[3] = (lo >> 16) & 0xff;
16746 dev->dev_addr[2] = (lo >> 24) & 0xff;
16747 dev->dev_addr[1] = hi & 0xff;
16748 dev->dev_addr[0] = (hi >> 8) & 0xff;
16752 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16753 #ifdef CONFIG_SPARC
16754 if (!tg3_get_default_macaddr_sparc(tp))
16762 #define BOUNDARY_SINGLE_CACHELINE 1
16763 #define BOUNDARY_MULTI_CACHELINE 2
16765 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16767 int cacheline_size;
16771 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16773 cacheline_size = 1024;
16775 cacheline_size = (int) byte * 4;
16777 /* On 5703 and later chips, the boundary bits have no
16780 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16781 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16782 !tg3_flag(tp, PCI_EXPRESS))
16785 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16786 goal = BOUNDARY_MULTI_CACHELINE;
16788 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16789 goal = BOUNDARY_SINGLE_CACHELINE;
16795 if (tg3_flag(tp, 57765_PLUS)) {
16796 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16803 /* PCI controllers on most RISC systems tend to disconnect
16804 * when a device tries to burst across a cache-line boundary.
16805 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16807 * Unfortunately, for PCI-E there are only limited
16808 * write-side controls for this, and thus for reads
16809 * we will still get the disconnects. We'll also waste
16810 * these PCI cycles for both read and write for chips
16811 * other than 5700 and 5701 which do not implement the
16814 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
16815 switch (cacheline_size) {
16820 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16821 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16822 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16824 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16825 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16830 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16831 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16835 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16836 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16839 } else if (tg3_flag(tp, PCI_EXPRESS)) {
16840 switch (cacheline_size) {
16844 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16845 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16846 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16852 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16853 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16857 switch (cacheline_size) {
16859 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16860 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16861 DMA_RWCTRL_WRITE_BNDRY_16);
16866 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16867 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16868 DMA_RWCTRL_WRITE_BNDRY_32);
16873 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16874 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16875 DMA_RWCTRL_WRITE_BNDRY_64);
16880 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16881 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16882 DMA_RWCTRL_WRITE_BNDRY_128);
16887 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16888 DMA_RWCTRL_WRITE_BNDRY_256);
16891 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16892 DMA_RWCTRL_WRITE_BNDRY_512);
16896 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16897 DMA_RWCTRL_WRITE_BNDRY_1024);
16906 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
16907 int size, bool to_device)
16909 struct tg3_internal_buffer_desc test_desc;
16910 u32 sram_dma_descs;
16913 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16915 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16916 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16917 tw32(RDMAC_STATUS, 0);
16918 tw32(WDMAC_STATUS, 0);
16920 tw32(BUFMGR_MODE, 0);
16921 tw32(FTQ_RESET, 0);
16923 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16924 test_desc.addr_lo = buf_dma & 0xffffffff;
16925 test_desc.nic_mbuf = 0x00002100;
16926 test_desc.len = size;
16929 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16930 * the *second* time the tg3 driver was getting loaded after an
16933 * Broadcom tells me:
16934 * ...the DMA engine is connected to the GRC block and a DMA
16935 * reset may affect the GRC block in some unpredictable way...
16936 * The behavior of resets to individual blocks has not been tested.
16938 * Broadcom noted the GRC reset will also reset all sub-components.
16941 test_desc.cqid_sqid = (13 << 8) | 2;
16943 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16946 test_desc.cqid_sqid = (16 << 8) | 7;
16948 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16951 test_desc.flags = 0x00000005;
16953 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16956 val = *(((u32 *)&test_desc) + i);
16957 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16958 sram_dma_descs + (i * sizeof(u32)));
16959 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16961 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16964 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
16966 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
16969 for (i = 0; i < 40; i++) {
16973 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16975 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16976 if ((val & 0xffff) == sram_dma_descs) {
16987 #define TEST_BUFFER_SIZE 0x2000
16989 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
16990 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16994 static int tg3_test_dma(struct tg3 *tp)
16996 dma_addr_t buf_dma;
16997 u32 *buf, saved_dma_rwctrl;
17000 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17001 &buf_dma, GFP_KERNEL);
17007 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17008 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17010 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17012 if (tg3_flag(tp, 57765_PLUS))
17015 if (tg3_flag(tp, PCI_EXPRESS)) {
17016 /* DMA read watermark not used on PCIE */
17017 tp->dma_rwctrl |= 0x00180000;
17018 } else if (!tg3_flag(tp, PCIX_MODE)) {
17019 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17020 tg3_asic_rev(tp) == ASIC_REV_5750)
17021 tp->dma_rwctrl |= 0x003f0000;
17023 tp->dma_rwctrl |= 0x003f000f;
17025 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17026 tg3_asic_rev(tp) == ASIC_REV_5704) {
17027 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17028 u32 read_water = 0x7;
17030 /* If the 5704 is behind the EPB bridge, we can
17031 * do the less restrictive ONE_DMA workaround for
17032 * better performance.
17034 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17035 tg3_asic_rev(tp) == ASIC_REV_5704)
17036 tp->dma_rwctrl |= 0x8000;
17037 else if (ccval == 0x6 || ccval == 0x7)
17038 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17040 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17042 /* Set bit 23 to enable PCIX hw bug fix */
17044 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17045 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17047 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17048 /* 5780 always in PCIX mode */
17049 tp->dma_rwctrl |= 0x00144000;
17050 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17051 /* 5714 always in PCIX mode */
17052 tp->dma_rwctrl |= 0x00148000;
17054 tp->dma_rwctrl |= 0x001b000f;
17057 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17058 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17060 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17061 tg3_asic_rev(tp) == ASIC_REV_5704)
17062 tp->dma_rwctrl &= 0xfffffff0;
17064 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17065 tg3_asic_rev(tp) == ASIC_REV_5701) {
17066 /* Remove this if it causes problems for some boards. */
17067 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17069 /* On 5700/5701 chips, we need to set this bit.
17070 * Otherwise the chip will issue cacheline transactions
17071 * to streamable DMA memory with not all the byte
17072 * enables turned on. This is an error on several
17073 * RISC PCI controllers, in particular sparc64.
17075 * On 5703/5704 chips, this bit has been reassigned
17076 * a different meaning. In particular, it is used
17077 * on those chips to enable a PCI-X workaround.
17079 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17082 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17085 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17086 tg3_asic_rev(tp) != ASIC_REV_5701)
17089 /* It is best to perform DMA test with maximum write burst size
17090 * to expose the 5700/5701 write DMA bug.
17092 saved_dma_rwctrl = tp->dma_rwctrl;
17093 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17094 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17099 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17102 /* Send the buffer to the chip. */
17103 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17105 dev_err(&tp->pdev->dev,
17106 "%s: Buffer write failed. err = %d\n",
17111 /* Now read it back. */
17112 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17114 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17115 "err = %d\n", __func__, ret);
17120 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17124 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17125 DMA_RWCTRL_WRITE_BNDRY_16) {
17126 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17127 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17128 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17131 dev_err(&tp->pdev->dev,
17132 "%s: Buffer corrupted on read back! "
17133 "(%d != %d)\n", __func__, p[i], i);
17139 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17145 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17146 DMA_RWCTRL_WRITE_BNDRY_16) {
17147 /* DMA test passed without adjusting DMA boundary,
17148 * now look for chipsets that are known to expose the
17149 * DMA bug without failing the test.
17151 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17152 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17153 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17155 /* Safe to use the calculated DMA boundary. */
17156 tp->dma_rwctrl = saved_dma_rwctrl;
17159 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17163 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17168 static void tg3_init_bufmgr_config(struct tg3 *tp)
17170 if (tg3_flag(tp, 57765_PLUS)) {
17171 tp->bufmgr_config.mbuf_read_dma_low_water =
17172 DEFAULT_MB_RDMA_LOW_WATER_5705;
17173 tp->bufmgr_config.mbuf_mac_rx_low_water =
17174 DEFAULT_MB_MACRX_LOW_WATER_57765;
17175 tp->bufmgr_config.mbuf_high_water =
17176 DEFAULT_MB_HIGH_WATER_57765;
17178 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17179 DEFAULT_MB_RDMA_LOW_WATER_5705;
17180 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17181 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17182 tp->bufmgr_config.mbuf_high_water_jumbo =
17183 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17184 } else if (tg3_flag(tp, 5705_PLUS)) {
17185 tp->bufmgr_config.mbuf_read_dma_low_water =
17186 DEFAULT_MB_RDMA_LOW_WATER_5705;
17187 tp->bufmgr_config.mbuf_mac_rx_low_water =
17188 DEFAULT_MB_MACRX_LOW_WATER_5705;
17189 tp->bufmgr_config.mbuf_high_water =
17190 DEFAULT_MB_HIGH_WATER_5705;
17191 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17192 tp->bufmgr_config.mbuf_mac_rx_low_water =
17193 DEFAULT_MB_MACRX_LOW_WATER_5906;
17194 tp->bufmgr_config.mbuf_high_water =
17195 DEFAULT_MB_HIGH_WATER_5906;
17198 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17199 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17200 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17201 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17202 tp->bufmgr_config.mbuf_high_water_jumbo =
17203 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17205 tp->bufmgr_config.mbuf_read_dma_low_water =
17206 DEFAULT_MB_RDMA_LOW_WATER;
17207 tp->bufmgr_config.mbuf_mac_rx_low_water =
17208 DEFAULT_MB_MACRX_LOW_WATER;
17209 tp->bufmgr_config.mbuf_high_water =
17210 DEFAULT_MB_HIGH_WATER;
17212 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17213 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17214 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17215 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17216 tp->bufmgr_config.mbuf_high_water_jumbo =
17217 DEFAULT_MB_HIGH_WATER_JUMBO;
17220 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17221 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17224 static char *tg3_phy_string(struct tg3 *tp)
17226 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17227 case TG3_PHY_ID_BCM5400: return "5400";
17228 case TG3_PHY_ID_BCM5401: return "5401";
17229 case TG3_PHY_ID_BCM5411: return "5411";
17230 case TG3_PHY_ID_BCM5701: return "5701";
17231 case TG3_PHY_ID_BCM5703: return "5703";
17232 case TG3_PHY_ID_BCM5704: return "5704";
17233 case TG3_PHY_ID_BCM5705: return "5705";
17234 case TG3_PHY_ID_BCM5750: return "5750";
17235 case TG3_PHY_ID_BCM5752: return "5752";
17236 case TG3_PHY_ID_BCM5714: return "5714";
17237 case TG3_PHY_ID_BCM5780: return "5780";
17238 case TG3_PHY_ID_BCM5755: return "5755";
17239 case TG3_PHY_ID_BCM5787: return "5787";
17240 case TG3_PHY_ID_BCM5784: return "5784";
17241 case TG3_PHY_ID_BCM5756: return "5722/5756";
17242 case TG3_PHY_ID_BCM5906: return "5906";
17243 case TG3_PHY_ID_BCM5761: return "5761";
17244 case TG3_PHY_ID_BCM5718C: return "5718C";
17245 case TG3_PHY_ID_BCM5718S: return "5718S";
17246 case TG3_PHY_ID_BCM57765: return "57765";
17247 case TG3_PHY_ID_BCM5719C: return "5719C";
17248 case TG3_PHY_ID_BCM5720C: return "5720C";
17249 case TG3_PHY_ID_BCM5762: return "5762C";
17250 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17251 case 0: return "serdes";
17252 default: return "unknown";
17256 static char *tg3_bus_string(struct tg3 *tp, char *str)
17258 if (tg3_flag(tp, PCI_EXPRESS)) {
17259 strcpy(str, "PCI Express");
17261 } else if (tg3_flag(tp, PCIX_MODE)) {
17262 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17264 strcpy(str, "PCIX:");
17266 if ((clock_ctrl == 7) ||
17267 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17268 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17269 strcat(str, "133MHz");
17270 else if (clock_ctrl == 0)
17271 strcat(str, "33MHz");
17272 else if (clock_ctrl == 2)
17273 strcat(str, "50MHz");
17274 else if (clock_ctrl == 4)
17275 strcat(str, "66MHz");
17276 else if (clock_ctrl == 6)
17277 strcat(str, "100MHz");
17279 strcpy(str, "PCI:");
17280 if (tg3_flag(tp, PCI_HIGH_SPEED))
17281 strcat(str, "66MHz");
17283 strcat(str, "33MHz");
17285 if (tg3_flag(tp, PCI_32BIT))
17286 strcat(str, ":32-bit");
17288 strcat(str, ":64-bit");
17292 static void tg3_init_coal(struct tg3 *tp)
17294 struct ethtool_coalesce *ec = &tp->coal;
17296 memset(ec, 0, sizeof(*ec));
17297 ec->cmd = ETHTOOL_GCOALESCE;
17298 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17299 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17300 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17301 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17302 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17303 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17304 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17305 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17306 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17308 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17309 HOSTCC_MODE_CLRTICK_TXBD)) {
17310 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17311 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17312 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17313 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17316 if (tg3_flag(tp, 5705_PLUS)) {
17317 ec->rx_coalesce_usecs_irq = 0;
17318 ec->tx_coalesce_usecs_irq = 0;
17319 ec->stats_block_coalesce_usecs = 0;
17323 static int tg3_init_one(struct pci_dev *pdev,
17324 const struct pci_device_id *ent)
17326 struct net_device *dev;
17329 u32 sndmbx, rcvmbx, intmbx;
17331 u64 dma_mask, persist_dma_mask;
17332 netdev_features_t features = 0;
17334 printk_once(KERN_INFO "%s\n", version);
17336 err = pci_enable_device(pdev);
17338 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17342 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17344 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17345 goto err_out_disable_pdev;
17348 pci_set_master(pdev);
17350 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17353 goto err_out_free_res;
17356 SET_NETDEV_DEV(dev, &pdev->dev);
17358 tp = netdev_priv(dev);
17361 tp->rx_mode = TG3_DEF_RX_MODE;
17362 tp->tx_mode = TG3_DEF_TX_MODE;
17366 tp->msg_enable = tg3_debug;
17368 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17370 if (pdev_is_ssb_gige_core(pdev)) {
17371 tg3_flag_set(tp, IS_SSB_CORE);
17372 if (ssb_gige_must_flush_posted_writes(pdev))
17373 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17374 if (ssb_gige_one_dma_at_once(pdev))
17375 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17376 if (ssb_gige_have_roboswitch(pdev)) {
17377 tg3_flag_set(tp, USE_PHYLIB);
17378 tg3_flag_set(tp, ROBOSWITCH);
17380 if (ssb_gige_is_rgmii(pdev))
17381 tg3_flag_set(tp, RGMII_MODE);
17384 /* The word/byte swap controls here control register access byte
17385 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17388 tp->misc_host_ctrl =
17389 MISC_HOST_CTRL_MASK_PCI_INT |
17390 MISC_HOST_CTRL_WORD_SWAP |
17391 MISC_HOST_CTRL_INDIR_ACCESS |
17392 MISC_HOST_CTRL_PCISTATE_RW;
17394 /* The NONFRM (non-frame) byte/word swap controls take effect
17395 * on descriptor entries, anything which isn't packet data.
17397 * The StrongARM chips on the board (one for tx, one for rx)
17398 * are running in big-endian mode.
17400 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17401 GRC_MODE_WSWAP_NONFRM_DATA);
17402 #ifdef __BIG_ENDIAN
17403 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17405 spin_lock_init(&tp->lock);
17406 spin_lock_init(&tp->indirect_lock);
17407 INIT_WORK(&tp->reset_task, tg3_reset_task);
17409 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17411 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17413 goto err_out_free_dev;
17416 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17417 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17418 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17419 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17420 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17421 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17422 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17423 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17424 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17425 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17426 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17427 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17428 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17429 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17430 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17431 tg3_flag_set(tp, ENABLE_APE);
17432 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17433 if (!tp->aperegs) {
17434 dev_err(&pdev->dev,
17435 "Cannot map APE registers, aborting\n");
17437 goto err_out_iounmap;
17441 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17442 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17444 dev->ethtool_ops = &tg3_ethtool_ops;
17445 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17446 dev->netdev_ops = &tg3_netdev_ops;
17447 dev->irq = pdev->irq;
17449 err = tg3_get_invariants(tp, ent);
17451 dev_err(&pdev->dev,
17452 "Problem fetching invariants of chip, aborting\n");
17453 goto err_out_apeunmap;
17456 /* The EPB bridge inside 5714, 5715, and 5780 and any
17457 * device behind the EPB cannot support DMA addresses > 40-bit.
17458 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17459 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17460 * do DMA address check in tg3_start_xmit().
17462 if (tg3_flag(tp, IS_5788))
17463 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17464 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17465 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17466 #ifdef CONFIG_HIGHMEM
17467 dma_mask = DMA_BIT_MASK(64);
17470 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17472 /* Configure DMA attributes. */
17473 if (dma_mask > DMA_BIT_MASK(32)) {
17474 err = pci_set_dma_mask(pdev, dma_mask);
17476 features |= NETIF_F_HIGHDMA;
17477 err = pci_set_consistent_dma_mask(pdev,
17480 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17481 "DMA for consistent allocations\n");
17482 goto err_out_apeunmap;
17486 if (err || dma_mask == DMA_BIT_MASK(32)) {
17487 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17489 dev_err(&pdev->dev,
17490 "No usable DMA configuration, aborting\n");
17491 goto err_out_apeunmap;
17495 tg3_init_bufmgr_config(tp);
17497 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
17499 /* 5700 B0 chips do not support checksumming correctly due
17500 * to hardware bugs.
17502 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17503 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17505 if (tg3_flag(tp, 5755_PLUS))
17506 features |= NETIF_F_IPV6_CSUM;
17509 /* TSO is on by default on chips that support hardware TSO.
17510 * Firmware TSO on older chips gives lower performance, so it
17511 * is off by default, but can be enabled using ethtool.
17513 if ((tg3_flag(tp, HW_TSO_1) ||
17514 tg3_flag(tp, HW_TSO_2) ||
17515 tg3_flag(tp, HW_TSO_3)) &&
17516 (features & NETIF_F_IP_CSUM))
17517 features |= NETIF_F_TSO;
17518 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17519 if (features & NETIF_F_IPV6_CSUM)
17520 features |= NETIF_F_TSO6;
17521 if (tg3_flag(tp, HW_TSO_3) ||
17522 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17523 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17524 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17525 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17526 tg3_asic_rev(tp) == ASIC_REV_57780)
17527 features |= NETIF_F_TSO_ECN;
17530 dev->features |= features;
17531 dev->vlan_features |= features;
17534 * Add loopback capability only for a subset of devices that support
17535 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17536 * loopback for the remaining devices.
17538 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17539 !tg3_flag(tp, CPMU_PRESENT))
17540 /* Add the loopback capability */
17541 features |= NETIF_F_LOOPBACK;
17543 dev->hw_features |= features;
17545 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17546 !tg3_flag(tp, TSO_CAPABLE) &&
17547 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17548 tg3_flag_set(tp, MAX_RXPEND_64);
17549 tp->rx_pending = 63;
17552 err = tg3_get_device_address(tp);
17554 dev_err(&pdev->dev,
17555 "Could not obtain valid ethernet address, aborting\n");
17556 goto err_out_apeunmap;
17560 * Reset chip in case UNDI or EFI driver did not shutdown
17561 * DMA self test will enable WDMAC and we'll see (spurious)
17562 * pending DMA on the PCI bus at that point.
17564 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17565 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17566 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17567 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17570 err = tg3_test_dma(tp);
17572 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17573 goto err_out_apeunmap;
17576 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17577 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17578 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17579 for (i = 0; i < tp->irq_max; i++) {
17580 struct tg3_napi *tnapi = &tp->napi[i];
17583 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17585 tnapi->int_mbox = intmbx;
17591 tnapi->consmbox = rcvmbx;
17592 tnapi->prodmbox = sndmbx;
17595 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17597 tnapi->coal_now = HOSTCC_MODE_NOW;
17599 if (!tg3_flag(tp, SUPPORT_MSIX))
17603 * If we support MSIX, we'll be using RSS. If we're using
17604 * RSS, the first vector only handles link interrupts and the
17605 * remaining vectors handle rx and tx interrupts. Reuse the
17606 * mailbox values for the next iteration. The values we setup
17607 * above are still useful for the single vectored mode.
17622 pci_set_drvdata(pdev, dev);
17624 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17625 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17626 tg3_asic_rev(tp) == ASIC_REV_5762)
17627 tg3_flag_set(tp, PTP_CAPABLE);
17629 tg3_timer_init(tp);
17631 tg3_carrier_off(tp);
17633 err = register_netdev(dev);
17635 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17636 goto err_out_apeunmap;
17639 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17640 tp->board_part_number,
17641 tg3_chip_rev_id(tp),
17642 tg3_bus_string(tp, str),
17645 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17646 struct phy_device *phydev;
17647 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17649 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17650 phydev->drv->name, dev_name(&phydev->dev));
17654 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17655 ethtype = "10/100Base-TX";
17656 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17657 ethtype = "1000Base-SX";
17659 ethtype = "10/100/1000Base-T";
17661 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17662 "(WireSpeed[%d], EEE[%d])\n",
17663 tg3_phy_string(tp), ethtype,
17664 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17665 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17668 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17669 (dev->features & NETIF_F_RXCSUM) != 0,
17670 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17671 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17672 tg3_flag(tp, ENABLE_ASF) != 0,
17673 tg3_flag(tp, TSO_CAPABLE) != 0);
17674 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17676 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17677 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17679 pci_save_state(pdev);
17685 iounmap(tp->aperegs);
17686 tp->aperegs = NULL;
17699 pci_release_regions(pdev);
17701 err_out_disable_pdev:
17702 if (pci_is_enabled(pdev))
17703 pci_disable_device(pdev);
17707 static void tg3_remove_one(struct pci_dev *pdev)
17709 struct net_device *dev = pci_get_drvdata(pdev);
17712 struct tg3 *tp = netdev_priv(dev);
17714 release_firmware(tp->fw);
17716 tg3_reset_task_cancel(tp);
17718 if (tg3_flag(tp, USE_PHYLIB)) {
17723 unregister_netdev(dev);
17725 iounmap(tp->aperegs);
17726 tp->aperegs = NULL;
17733 pci_release_regions(pdev);
17734 pci_disable_device(pdev);
17738 #ifdef CONFIG_PM_SLEEP
17739 static int tg3_suspend(struct device *device)
17741 struct pci_dev *pdev = to_pci_dev(device);
17742 struct net_device *dev = pci_get_drvdata(pdev);
17743 struct tg3 *tp = netdev_priv(dev);
17746 if (!netif_running(dev))
17749 tg3_reset_task_cancel(tp);
17751 tg3_netif_stop(tp);
17753 tg3_timer_stop(tp);
17755 tg3_full_lock(tp, 1);
17756 tg3_disable_ints(tp);
17757 tg3_full_unlock(tp);
17759 netif_device_detach(dev);
17761 tg3_full_lock(tp, 0);
17762 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17763 tg3_flag_clear(tp, INIT_COMPLETE);
17764 tg3_full_unlock(tp);
17766 err = tg3_power_down_prepare(tp);
17770 tg3_full_lock(tp, 0);
17772 tg3_flag_set(tp, INIT_COMPLETE);
17773 err2 = tg3_restart_hw(tp, true);
17777 tg3_timer_start(tp);
17779 netif_device_attach(dev);
17780 tg3_netif_start(tp);
17783 tg3_full_unlock(tp);
17792 static int tg3_resume(struct device *device)
17794 struct pci_dev *pdev = to_pci_dev(device);
17795 struct net_device *dev = pci_get_drvdata(pdev);
17796 struct tg3 *tp = netdev_priv(dev);
17799 if (!netif_running(dev))
17802 netif_device_attach(dev);
17804 tg3_full_lock(tp, 0);
17806 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17808 tg3_flag_set(tp, INIT_COMPLETE);
17809 err = tg3_restart_hw(tp,
17810 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
17814 tg3_timer_start(tp);
17816 tg3_netif_start(tp);
17819 tg3_full_unlock(tp);
17826 #endif /* CONFIG_PM_SLEEP */
17828 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17830 static void tg3_shutdown(struct pci_dev *pdev)
17832 struct net_device *dev = pci_get_drvdata(pdev);
17833 struct tg3 *tp = netdev_priv(dev);
17836 netif_device_detach(dev);
17838 if (netif_running(dev))
17841 if (system_state == SYSTEM_POWER_OFF)
17842 tg3_power_down(tp);
17848 * tg3_io_error_detected - called when PCI error is detected
17849 * @pdev: Pointer to PCI device
17850 * @state: The current pci connection state
17852 * This function is called after a PCI bus error affecting
17853 * this device has been detected.
17855 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17856 pci_channel_state_t state)
17858 struct net_device *netdev = pci_get_drvdata(pdev);
17859 struct tg3 *tp = netdev_priv(netdev);
17860 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17862 netdev_info(netdev, "PCI I/O error detected\n");
17866 /* We probably don't have netdev yet */
17867 if (!netdev || !netif_running(netdev))
17872 tg3_netif_stop(tp);
17874 tg3_timer_stop(tp);
17876 /* Want to make sure that the reset task doesn't run */
17877 tg3_reset_task_cancel(tp);
17879 netif_device_detach(netdev);
17881 /* Clean up software state, even if MMIO is blocked */
17882 tg3_full_lock(tp, 0);
17883 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17884 tg3_full_unlock(tp);
17887 if (state == pci_channel_io_perm_failure) {
17889 tg3_napi_enable(tp);
17892 err = PCI_ERS_RESULT_DISCONNECT;
17894 pci_disable_device(pdev);
17903 * tg3_io_slot_reset - called after the pci bus has been reset.
17904 * @pdev: Pointer to PCI device
17906 * Restart the card from scratch, as if from a cold-boot.
17907 * At this point, the card has exprienced a hard reset,
17908 * followed by fixups by BIOS, and has its config space
17909 * set up identically to what it was at cold boot.
17911 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17913 struct net_device *netdev = pci_get_drvdata(pdev);
17914 struct tg3 *tp = netdev_priv(netdev);
17915 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17920 if (pci_enable_device(pdev)) {
17921 dev_err(&pdev->dev,
17922 "Cannot re-enable PCI device after reset.\n");
17926 pci_set_master(pdev);
17927 pci_restore_state(pdev);
17928 pci_save_state(pdev);
17930 if (!netdev || !netif_running(netdev)) {
17931 rc = PCI_ERS_RESULT_RECOVERED;
17935 err = tg3_power_up(tp);
17939 rc = PCI_ERS_RESULT_RECOVERED;
17942 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
17943 tg3_napi_enable(tp);
17952 * tg3_io_resume - called when traffic can start flowing again.
17953 * @pdev: Pointer to PCI device
17955 * This callback is called when the error recovery driver tells
17956 * us that its OK to resume normal operation.
17958 static void tg3_io_resume(struct pci_dev *pdev)
17960 struct net_device *netdev = pci_get_drvdata(pdev);
17961 struct tg3 *tp = netdev_priv(netdev);
17966 if (!netif_running(netdev))
17969 tg3_full_lock(tp, 0);
17970 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17971 tg3_flag_set(tp, INIT_COMPLETE);
17972 err = tg3_restart_hw(tp, true);
17974 tg3_full_unlock(tp);
17975 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17979 netif_device_attach(netdev);
17981 tg3_timer_start(tp);
17983 tg3_netif_start(tp);
17985 tg3_full_unlock(tp);
17993 static const struct pci_error_handlers tg3_err_handler = {
17994 .error_detected = tg3_io_error_detected,
17995 .slot_reset = tg3_io_slot_reset,
17996 .resume = tg3_io_resume
17999 static struct pci_driver tg3_driver = {
18000 .name = DRV_MODULE_NAME,
18001 .id_table = tg3_pci_tbl,
18002 .probe = tg3_init_one,
18003 .remove = tg3_remove_one,
18004 .err_handler = &tg3_err_handler,
18005 .driver.pm = &tg3_pm_ops,
18006 .shutdown = tg3_shutdown,
18009 module_pci_driver(tg3_driver);