2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU ETH_ZLEN
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1542 /* The bus registration will look for all the PHYs on the mdio bus.
1543 * Unfortunately, it does not ensure the PHY is powered up before
1544 * accessing the PHY ID registers. A chip reset is the
1545 * quickest way to bring the device back to an operational state..
1547 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1550 i = mdiobus_register(tp->mdio_bus);
1552 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1553 mdiobus_free(tp->mdio_bus);
1557 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1559 if (!phydev || !phydev->drv) {
1560 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1561 mdiobus_unregister(tp->mdio_bus);
1562 mdiobus_free(tp->mdio_bus);
1566 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1567 case PHY_ID_BCM57780:
1568 phydev->interface = PHY_INTERFACE_MODE_GMII;
1569 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1571 case PHY_ID_BCM50610:
1572 case PHY_ID_BCM50610M:
1573 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1574 PHY_BRCM_RX_REFCLK_UNUSED |
1575 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1576 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1577 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1578 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1579 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1580 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1581 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1582 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1584 case PHY_ID_RTL8211C:
1585 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1587 case PHY_ID_RTL8201E:
1588 case PHY_ID_BCMAC131:
1589 phydev->interface = PHY_INTERFACE_MODE_MII;
1590 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1591 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1595 tg3_flag_set(tp, MDIOBUS_INITED);
1597 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1598 tg3_mdio_config_5785(tp);
1603 static void tg3_mdio_fini(struct tg3 *tp)
1605 if (tg3_flag(tp, MDIOBUS_INITED)) {
1606 tg3_flag_clear(tp, MDIOBUS_INITED);
1607 mdiobus_unregister(tp->mdio_bus);
1608 mdiobus_free(tp->mdio_bus);
1612 /* tp->lock is held. */
1613 static inline void tg3_generate_fw_event(struct tg3 *tp)
1617 val = tr32(GRC_RX_CPU_EVENT);
1618 val |= GRC_RX_CPU_DRIVER_EVENT;
1619 tw32_f(GRC_RX_CPU_EVENT, val);
1621 tp->last_event_jiffies = jiffies;
1624 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1626 /* tp->lock is held. */
1627 static void tg3_wait_for_event_ack(struct tg3 *tp)
1630 unsigned int delay_cnt;
1633 /* If enough time has passed, no wait is necessary. */
1634 time_remain = (long)(tp->last_event_jiffies + 1 +
1635 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1637 if (time_remain < 0)
1640 /* Check if we can shorten the wait time. */
1641 delay_cnt = jiffies_to_usecs(time_remain);
1642 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1643 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1644 delay_cnt = (delay_cnt >> 3) + 1;
1646 for (i = 0; i < delay_cnt; i++) {
1647 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1649 if (pci_channel_offline(tp->pdev))
1656 /* tp->lock is held. */
1657 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1662 if (!tg3_readphy(tp, MII_BMCR, ®))
1664 if (!tg3_readphy(tp, MII_BMSR, ®))
1665 val |= (reg & 0xffff);
1669 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1671 if (!tg3_readphy(tp, MII_LPA, ®))
1672 val |= (reg & 0xffff);
1676 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1677 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1679 if (!tg3_readphy(tp, MII_STAT1000, ®))
1680 val |= (reg & 0xffff);
1684 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1691 /* tp->lock is held. */
1692 static void tg3_ump_link_report(struct tg3 *tp)
1696 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1699 tg3_phy_gather_ump_data(tp, data);
1701 tg3_wait_for_event_ack(tp);
1703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1710 tg3_generate_fw_event(tp);
1713 /* tp->lock is held. */
1714 static void tg3_stop_fw(struct tg3 *tp)
1716 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1717 /* Wait for RX cpu to ACK the previous event. */
1718 tg3_wait_for_event_ack(tp);
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1722 tg3_generate_fw_event(tp);
1724 /* Wait for RX cpu to ACK this event. */
1725 tg3_wait_for_event_ack(tp);
1729 /* tp->lock is held. */
1730 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1732 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1733 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1735 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1737 case RESET_KIND_INIT:
1738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1742 case RESET_KIND_SHUTDOWN:
1743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1747 case RESET_KIND_SUSPEND:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1758 /* tp->lock is held. */
1759 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1761 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1763 case RESET_KIND_INIT:
1764 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 DRV_STATE_START_DONE);
1768 case RESET_KIND_SHUTDOWN:
1769 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770 DRV_STATE_UNLOAD_DONE);
1779 /* tp->lock is held. */
1780 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1782 if (tg3_flag(tp, ENABLE_ASF)) {
1784 case RESET_KIND_INIT:
1785 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1789 case RESET_KIND_SHUTDOWN:
1790 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1794 case RESET_KIND_SUSPEND:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1805 static int tg3_poll_fw(struct tg3 *tp)
1810 if (tg3_flag(tp, NO_FWARE_REPORTED))
1813 if (tg3_flag(tp, IS_SSB_CORE)) {
1814 /* We don't use firmware. */
1818 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1819 /* Wait up to 20ms for init done. */
1820 for (i = 0; i < 200; i++) {
1821 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1823 if (pci_channel_offline(tp->pdev))
1831 /* Wait for firmware initialization to complete. */
1832 for (i = 0; i < 100000; i++) {
1833 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1834 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1836 if (pci_channel_offline(tp->pdev)) {
1837 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1838 tg3_flag_set(tp, NO_FWARE_REPORTED);
1839 netdev_info(tp->dev, "No firmware running\n");
1848 /* Chip might not be fitted with firmware. Some Sun onboard
1849 * parts are configured like that. So don't signal the timeout
1850 * of the above loop as an error, but do report the lack of
1851 * running firmware once.
1853 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1854 tg3_flag_set(tp, NO_FWARE_REPORTED);
1856 netdev_info(tp->dev, "No firmware running\n");
1859 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1860 /* The 57765 A0 needs a little more
1861 * time to do some important work.
1869 static void tg3_link_report(struct tg3 *tp)
1871 if (!netif_carrier_ok(tp->dev)) {
1872 netif_info(tp, link, tp->dev, "Link is down\n");
1873 tg3_ump_link_report(tp);
1874 } else if (netif_msg_link(tp)) {
1875 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1876 (tp->link_config.active_speed == SPEED_1000 ?
1878 (tp->link_config.active_speed == SPEED_100 ?
1880 (tp->link_config.active_duplex == DUPLEX_FULL ?
1883 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1884 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1890 netdev_info(tp->dev, "EEE is %s\n",
1891 tp->setlpicnt ? "enabled" : "disabled");
1893 tg3_ump_link_report(tp);
1896 tp->link_up = netif_carrier_ok(tp->dev);
1899 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1903 if (adv & ADVERTISE_PAUSE_CAP) {
1904 flowctrl |= FLOW_CTRL_RX;
1905 if (!(adv & ADVERTISE_PAUSE_ASYM))
1906 flowctrl |= FLOW_CTRL_TX;
1907 } else if (adv & ADVERTISE_PAUSE_ASYM)
1908 flowctrl |= FLOW_CTRL_TX;
1913 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1917 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1918 miireg = ADVERTISE_1000XPAUSE;
1919 else if (flow_ctrl & FLOW_CTRL_TX)
1920 miireg = ADVERTISE_1000XPSE_ASYM;
1921 else if (flow_ctrl & FLOW_CTRL_RX)
1922 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1929 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1933 if (adv & ADVERTISE_1000XPAUSE) {
1934 flowctrl |= FLOW_CTRL_RX;
1935 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1936 flowctrl |= FLOW_CTRL_TX;
1937 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1938 flowctrl |= FLOW_CTRL_TX;
1943 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1947 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1948 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1949 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1950 if (lcladv & ADVERTISE_1000XPAUSE)
1952 if (rmtadv & ADVERTISE_1000XPAUSE)
1959 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1963 u32 old_rx_mode = tp->rx_mode;
1964 u32 old_tx_mode = tp->tx_mode;
1966 if (tg3_flag(tp, USE_PHYLIB))
1967 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1969 autoneg = tp->link_config.autoneg;
1971 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1972 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1973 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1975 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1977 flowctrl = tp->link_config.flowctrl;
1979 tp->link_config.active_flowctrl = flowctrl;
1981 if (flowctrl & FLOW_CTRL_RX)
1982 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1984 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1986 if (old_rx_mode != tp->rx_mode)
1987 tw32_f(MAC_RX_MODE, tp->rx_mode);
1989 if (flowctrl & FLOW_CTRL_TX)
1990 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1992 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1994 if (old_tx_mode != tp->tx_mode)
1995 tw32_f(MAC_TX_MODE, tp->tx_mode);
1998 static void tg3_adjust_link(struct net_device *dev)
2000 u8 oldflowctrl, linkmesg = 0;
2001 u32 mac_mode, lcl_adv, rmt_adv;
2002 struct tg3 *tp = netdev_priv(dev);
2003 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2005 spin_lock_bh(&tp->lock);
2007 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2008 MAC_MODE_HALF_DUPLEX);
2010 oldflowctrl = tp->link_config.active_flowctrl;
2016 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2017 mac_mode |= MAC_MODE_PORT_MODE_MII;
2018 else if (phydev->speed == SPEED_1000 ||
2019 tg3_asic_rev(tp) != ASIC_REV_5785)
2020 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2022 mac_mode |= MAC_MODE_PORT_MODE_MII;
2024 if (phydev->duplex == DUPLEX_HALF)
2025 mac_mode |= MAC_MODE_HALF_DUPLEX;
2027 lcl_adv = mii_advertise_flowctrl(
2028 tp->link_config.flowctrl);
2031 rmt_adv = LPA_PAUSE_CAP;
2032 if (phydev->asym_pause)
2033 rmt_adv |= LPA_PAUSE_ASYM;
2036 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2038 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2040 if (mac_mode != tp->mac_mode) {
2041 tp->mac_mode = mac_mode;
2042 tw32_f(MAC_MODE, tp->mac_mode);
2046 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2047 if (phydev->speed == SPEED_10)
2049 MAC_MI_STAT_10MBPS_MODE |
2050 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2052 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2055 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2056 tw32(MAC_TX_LENGTHS,
2057 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2058 (6 << TX_LENGTHS_IPG_SHIFT) |
2059 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2061 tw32(MAC_TX_LENGTHS,
2062 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2063 (6 << TX_LENGTHS_IPG_SHIFT) |
2064 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2066 if (phydev->link != tp->old_link ||
2067 phydev->speed != tp->link_config.active_speed ||
2068 phydev->duplex != tp->link_config.active_duplex ||
2069 oldflowctrl != tp->link_config.active_flowctrl)
2072 tp->old_link = phydev->link;
2073 tp->link_config.active_speed = phydev->speed;
2074 tp->link_config.active_duplex = phydev->duplex;
2076 spin_unlock_bh(&tp->lock);
2079 tg3_link_report(tp);
2082 static int tg3_phy_init(struct tg3 *tp)
2084 struct phy_device *phydev;
2086 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2089 /* Bring the PHY back to a known state. */
2092 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2094 /* Attach the MAC to the PHY. */
2095 phydev = phy_connect(tp->dev, phydev_name(phydev),
2096 tg3_adjust_link, phydev->interface);
2097 if (IS_ERR(phydev)) {
2098 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2099 return PTR_ERR(phydev);
2102 /* Mask with MAC supported features. */
2103 switch (phydev->interface) {
2104 case PHY_INTERFACE_MODE_GMII:
2105 case PHY_INTERFACE_MODE_RGMII:
2106 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2107 phydev->supported &= (PHY_GBIT_FEATURES |
2109 SUPPORTED_Asym_Pause);
2113 case PHY_INTERFACE_MODE_MII:
2114 phydev->supported &= (PHY_BASIC_FEATURES |
2116 SUPPORTED_Asym_Pause);
2119 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2125 phydev->advertising = phydev->supported;
2127 phy_attached_info(phydev);
2132 static void tg3_phy_start(struct tg3 *tp)
2134 struct phy_device *phydev;
2136 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2139 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2141 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2142 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2143 phydev->speed = tp->link_config.speed;
2144 phydev->duplex = tp->link_config.duplex;
2145 phydev->autoneg = tp->link_config.autoneg;
2146 phydev->advertising = tp->link_config.advertising;
2151 phy_start_aneg(phydev);
2154 static void tg3_phy_stop(struct tg3 *tp)
2156 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2159 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2162 static void tg3_phy_fini(struct tg3 *tp)
2164 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2165 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2166 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2170 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2175 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2178 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2179 /* Cannot do read-modify-write on 5401 */
2180 err = tg3_phy_auxctl_write(tp,
2181 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2182 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2187 err = tg3_phy_auxctl_read(tp,
2188 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2192 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2193 err = tg3_phy_auxctl_write(tp,
2194 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2200 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2204 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2207 tg3_writephy(tp, MII_TG3_FET_TEST,
2208 phytest | MII_TG3_FET_SHADOW_EN);
2209 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2211 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2213 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2214 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2216 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2220 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2224 if (!tg3_flag(tp, 5705_PLUS) ||
2225 (tg3_flag(tp, 5717_PLUS) &&
2226 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2229 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2230 tg3_phy_fet_toggle_apd(tp, enable);
2234 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2235 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2236 MII_TG3_MISC_SHDW_SCR5_SDTL |
2237 MII_TG3_MISC_SHDW_SCR5_C125OE;
2238 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2239 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2241 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2244 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2246 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2248 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2251 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2255 if (!tg3_flag(tp, 5705_PLUS) ||
2256 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2259 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2262 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2263 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2265 tg3_writephy(tp, MII_TG3_FET_TEST,
2266 ephy | MII_TG3_FET_SHADOW_EN);
2267 if (!tg3_readphy(tp, reg, &phy)) {
2269 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2271 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2272 tg3_writephy(tp, reg, phy);
2274 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2279 ret = tg3_phy_auxctl_read(tp,
2280 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2283 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2285 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2286 tg3_phy_auxctl_write(tp,
2287 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2292 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2297 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2300 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2302 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2303 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2306 static void tg3_phy_apply_otp(struct tg3 *tp)
2315 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2318 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2319 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2320 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2322 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2323 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2324 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2326 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2327 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2328 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2330 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2331 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2333 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2334 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2336 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2337 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2338 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2340 tg3_phy_toggle_auxctl_smdsp(tp, false);
2343 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2346 struct ethtool_eee *dest = &tp->eee;
2348 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2354 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2357 /* Pull eee_active */
2358 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2359 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2360 dest->eee_active = 1;
2362 dest->eee_active = 0;
2364 /* Pull lp advertised settings */
2365 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2367 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2369 /* Pull advertised and eee_enabled settings */
2370 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2372 dest->eee_enabled = !!val;
2373 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2375 /* Pull tx_lpi_enabled */
2376 val = tr32(TG3_CPMU_EEE_MODE);
2377 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2379 /* Pull lpi timer value */
2380 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2383 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2387 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2392 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2394 tp->link_config.active_duplex == DUPLEX_FULL &&
2395 (tp->link_config.active_speed == SPEED_100 ||
2396 tp->link_config.active_speed == SPEED_1000)) {
2399 if (tp->link_config.active_speed == SPEED_1000)
2400 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2404 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2406 tg3_eee_pull_config(tp, NULL);
2407 if (tp->eee.eee_active)
2411 if (!tp->setlpicnt) {
2412 if (current_link_up &&
2413 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2414 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2415 tg3_phy_toggle_auxctl_smdsp(tp, false);
2418 val = tr32(TG3_CPMU_EEE_MODE);
2419 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2423 static void tg3_phy_eee_enable(struct tg3 *tp)
2427 if (tp->link_config.active_speed == SPEED_1000 &&
2428 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2429 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2430 tg3_flag(tp, 57765_CLASS)) &&
2431 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2432 val = MII_TG3_DSP_TAP26_ALNOKO |
2433 MII_TG3_DSP_TAP26_RMRXSTO;
2434 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2435 tg3_phy_toggle_auxctl_smdsp(tp, false);
2438 val = tr32(TG3_CPMU_EEE_MODE);
2439 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2442 static int tg3_wait_macro_done(struct tg3 *tp)
2449 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2450 if ((tmp32 & 0x1000) == 0)
2460 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2462 static const u32 test_pat[4][6] = {
2463 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2464 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2465 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2466 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2470 for (chan = 0; chan < 4; chan++) {
2473 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2474 (chan * 0x2000) | 0x0200);
2475 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2477 for (i = 0; i < 6; i++)
2478 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2481 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2482 if (tg3_wait_macro_done(tp)) {
2487 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2488 (chan * 0x2000) | 0x0200);
2489 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2490 if (tg3_wait_macro_done(tp)) {
2495 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2496 if (tg3_wait_macro_done(tp)) {
2501 for (i = 0; i < 6; i += 2) {
2504 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2505 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2506 tg3_wait_macro_done(tp)) {
2512 if (low != test_pat[chan][i] ||
2513 high != test_pat[chan][i+1]) {
2514 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2515 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2516 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2526 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2530 for (chan = 0; chan < 4; chan++) {
2533 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2534 (chan * 0x2000) | 0x0200);
2535 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2536 for (i = 0; i < 6; i++)
2537 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2538 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2539 if (tg3_wait_macro_done(tp))
2546 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2548 u32 reg32, phy9_orig;
2549 int retries, do_phy_reset, err;
2555 err = tg3_bmcr_reset(tp);
2561 /* Disable transmitter and interrupt. */
2562 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2566 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2568 /* Set full-duplex, 1000 mbps. */
2569 tg3_writephy(tp, MII_BMCR,
2570 BMCR_FULLDPLX | BMCR_SPEED1000);
2572 /* Set to master mode. */
2573 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2576 tg3_writephy(tp, MII_CTRL1000,
2577 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2579 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2583 /* Block the PHY control access. */
2584 tg3_phydsp_write(tp, 0x8005, 0x0800);
2586 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 } while (--retries);
2591 err = tg3_phy_reset_chanpat(tp);
2595 tg3_phydsp_write(tp, 0x8005, 0x0000);
2597 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2598 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2600 tg3_phy_toggle_auxctl_smdsp(tp, false);
2602 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2604 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2609 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2614 static void tg3_carrier_off(struct tg3 *tp)
2616 netif_carrier_off(tp->dev);
2617 tp->link_up = false;
2620 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2622 if (tg3_flag(tp, ENABLE_ASF))
2623 netdev_warn(tp->dev,
2624 "Management side-band traffic will be interrupted during phy settings change\n");
2627 /* This will reset the tigon3 PHY if there is no valid
2628 * link unless the FORCE argument is non-zero.
2630 static int tg3_phy_reset(struct tg3 *tp)
2635 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2636 val = tr32(GRC_MISC_CFG);
2637 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2640 err = tg3_readphy(tp, MII_BMSR, &val);
2641 err |= tg3_readphy(tp, MII_BMSR, &val);
2645 if (netif_running(tp->dev) && tp->link_up) {
2646 netif_carrier_off(tp->dev);
2647 tg3_link_report(tp);
2650 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2651 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2652 tg3_asic_rev(tp) == ASIC_REV_5705) {
2653 err = tg3_phy_reset_5703_4_5(tp);
2660 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2661 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2662 cpmuctrl = tr32(TG3_CPMU_CTRL);
2663 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2665 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2668 err = tg3_bmcr_reset(tp);
2672 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2673 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2674 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2676 tw32(TG3_CPMU_CTRL, cpmuctrl);
2679 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2680 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2681 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2682 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2683 CPMU_LSPD_1000MB_MACCLK_12_5) {
2684 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2686 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2690 if (tg3_flag(tp, 5717_PLUS) &&
2691 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2694 tg3_phy_apply_otp(tp);
2696 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2697 tg3_phy_toggle_apd(tp, true);
2699 tg3_phy_toggle_apd(tp, false);
2702 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2703 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2704 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2705 tg3_phydsp_write(tp, 0x000a, 0x0323);
2706 tg3_phy_toggle_auxctl_smdsp(tp, false);
2709 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2710 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2711 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2714 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2715 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2716 tg3_phydsp_write(tp, 0x000a, 0x310b);
2717 tg3_phydsp_write(tp, 0x201f, 0x9506);
2718 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2719 tg3_phy_toggle_auxctl_smdsp(tp, false);
2721 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2722 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2723 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2724 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2725 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2726 tg3_writephy(tp, MII_TG3_TEST1,
2727 MII_TG3_TEST1_TRIM_EN | 0x4);
2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2731 tg3_phy_toggle_auxctl_smdsp(tp, false);
2735 /* Set Extended packet length bit (bit 14) on all chips that */
2736 /* support jumbo frames */
2737 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2738 /* Cannot do read-modify-write on 5401 */
2739 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2740 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2741 /* Set bit 14 with read-modify-write to preserve other bits */
2742 err = tg3_phy_auxctl_read(tp,
2743 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2745 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2746 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2749 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2750 * jumbo frames transmission.
2752 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2753 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2754 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2755 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2758 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2759 /* adjust output voltage */
2760 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2763 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2764 tg3_phydsp_write(tp, 0xffb, 0x4000);
2766 tg3_phy_toggle_automdix(tp, true);
2767 tg3_phy_set_wirespeed(tp);
2771 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2772 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2773 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2774 TG3_GPIO_MSG_NEED_VAUX)
2775 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2776 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2777 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2778 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 12))
2781 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2782 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2783 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2784 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 12))
2787 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2791 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2792 tg3_asic_rev(tp) == ASIC_REV_5719)
2793 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2795 status = tr32(TG3_CPMU_DRV_STATUS);
2797 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2798 status &= ~(TG3_GPIO_MSG_MASK << shift);
2799 status |= (newstat << shift);
2801 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2802 tg3_asic_rev(tp) == ASIC_REV_5719)
2803 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2805 tw32(TG3_CPMU_DRV_STATUS, status);
2807 return status >> TG3_APE_GPIO_MSG_SHIFT;
2810 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2812 if (!tg3_flag(tp, IS_NIC))
2815 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2816 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2817 tg3_asic_rev(tp) == ASIC_REV_5720) {
2818 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2821 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2823 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2824 TG3_GRC_LCLCTL_PWRSW_DELAY);
2826 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2828 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2829 TG3_GRC_LCLCTL_PWRSW_DELAY);
2835 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2839 if (!tg3_flag(tp, IS_NIC) ||
2840 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2841 tg3_asic_rev(tp) == ASIC_REV_5701)
2844 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2846 tw32_wait_f(GRC_LOCAL_CTRL,
2847 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2848 TG3_GRC_LCLCTL_PWRSW_DELAY);
2850 tw32_wait_f(GRC_LOCAL_CTRL,
2852 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2855 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2859 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2861 if (!tg3_flag(tp, IS_NIC))
2864 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2865 tg3_asic_rev(tp) == ASIC_REV_5701) {
2866 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2867 (GRC_LCLCTRL_GPIO_OE0 |
2868 GRC_LCLCTRL_GPIO_OE1 |
2869 GRC_LCLCTRL_GPIO_OE2 |
2870 GRC_LCLCTRL_GPIO_OUTPUT0 |
2871 GRC_LCLCTRL_GPIO_OUTPUT1),
2872 TG3_GRC_LCLCTL_PWRSW_DELAY);
2873 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2874 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2875 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2876 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2877 GRC_LCLCTRL_GPIO_OE1 |
2878 GRC_LCLCTRL_GPIO_OE2 |
2879 GRC_LCLCTRL_GPIO_OUTPUT0 |
2880 GRC_LCLCTRL_GPIO_OUTPUT1 |
2882 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2883 TG3_GRC_LCLCTL_PWRSW_DELAY);
2885 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2886 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2887 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 u32 grc_local_ctrl = 0;
2896 /* Workaround to prevent overdrawing Amps. */
2897 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2898 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2899 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2901 TG3_GRC_LCLCTL_PWRSW_DELAY);
2904 /* On 5753 and variants, GPIO2 cannot be used. */
2905 no_gpio2 = tp->nic_sram_data_cfg &
2906 NIC_SRAM_DATA_CFG_NO_GPIO2;
2908 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2909 GRC_LCLCTRL_GPIO_OE1 |
2910 GRC_LCLCTRL_GPIO_OE2 |
2911 GRC_LCLCTRL_GPIO_OUTPUT1 |
2912 GRC_LCLCTRL_GPIO_OUTPUT2;
2914 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2915 GRC_LCLCTRL_GPIO_OUTPUT2);
2917 tw32_wait_f(GRC_LOCAL_CTRL,
2918 tp->grc_local_ctrl | grc_local_ctrl,
2919 TG3_GRC_LCLCTL_PWRSW_DELAY);
2921 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2923 tw32_wait_f(GRC_LOCAL_CTRL,
2924 tp->grc_local_ctrl | grc_local_ctrl,
2925 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2929 tw32_wait_f(GRC_LOCAL_CTRL,
2930 tp->grc_local_ctrl | grc_local_ctrl,
2931 TG3_GRC_LCLCTL_PWRSW_DELAY);
2936 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2940 /* Serialize power state transitions */
2941 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2944 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2945 msg = TG3_GPIO_MSG_NEED_VAUX;
2947 msg = tg3_set_function_status(tp, msg);
2949 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2952 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2953 tg3_pwrsrc_switch_to_vaux(tp);
2955 tg3_pwrsrc_die_with_vmain(tp);
2958 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2961 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2963 bool need_vaux = false;
2965 /* The GPIOs do something completely different on 57765. */
2966 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2969 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2970 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2971 tg3_asic_rev(tp) == ASIC_REV_5720) {
2972 tg3_frob_aux_power_5717(tp, include_wol ?
2973 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2977 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2978 struct net_device *dev_peer;
2980 dev_peer = pci_get_drvdata(tp->pdev_peer);
2982 /* remove_one() may have been run on the peer. */
2984 struct tg3 *tp_peer = netdev_priv(dev_peer);
2986 if (tg3_flag(tp_peer, INIT_COMPLETE))
2989 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2990 tg3_flag(tp_peer, ENABLE_ASF))
2995 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2996 tg3_flag(tp, ENABLE_ASF))
3000 tg3_pwrsrc_switch_to_vaux(tp);
3002 tg3_pwrsrc_die_with_vmain(tp);
3005 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3007 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3009 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3010 if (speed != SPEED_10)
3012 } else if (speed == SPEED_10)
3018 static bool tg3_phy_power_bug(struct tg3 *tp)
3020 switch (tg3_asic_rev(tp)) {
3025 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3034 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3043 static bool tg3_phy_led_bug(struct tg3 *tp)
3045 switch (tg3_asic_rev(tp)) {
3048 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3057 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3061 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3065 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3066 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3067 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3070 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3071 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3072 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3077 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3079 val = tr32(GRC_MISC_CFG);
3080 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3083 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3085 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3088 tg3_writephy(tp, MII_ADVERTISE, 0);
3089 tg3_writephy(tp, MII_BMCR,
3090 BMCR_ANENABLE | BMCR_ANRESTART);
3092 tg3_writephy(tp, MII_TG3_FET_TEST,
3093 phytest | MII_TG3_FET_SHADOW_EN);
3094 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3095 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3097 MII_TG3_FET_SHDW_AUXMODE4,
3100 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 } else if (do_low_power) {
3104 if (!tg3_phy_led_bug(tp))
3105 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3106 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3108 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3109 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3110 MII_TG3_AUXCTL_PCTL_VREG_11V;
3111 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3114 /* The PHY should not be powered down on some chips because
3117 if (tg3_phy_power_bug(tp))
3120 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3121 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3122 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3123 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3124 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3125 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3128 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3131 /* tp->lock is held. */
3132 static int tg3_nvram_lock(struct tg3 *tp)
3134 if (tg3_flag(tp, NVRAM)) {
3137 if (tp->nvram_lock_cnt == 0) {
3138 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3139 for (i = 0; i < 8000; i++) {
3140 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3145 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3149 tp->nvram_lock_cnt++;
3154 /* tp->lock is held. */
3155 static void tg3_nvram_unlock(struct tg3 *tp)
3157 if (tg3_flag(tp, NVRAM)) {
3158 if (tp->nvram_lock_cnt > 0)
3159 tp->nvram_lock_cnt--;
3160 if (tp->nvram_lock_cnt == 0)
3161 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3165 /* tp->lock is held. */
3166 static void tg3_enable_nvram_access(struct tg3 *tp)
3168 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3169 u32 nvaccess = tr32(NVRAM_ACCESS);
3171 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3175 /* tp->lock is held. */
3176 static void tg3_disable_nvram_access(struct tg3 *tp)
3178 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3179 u32 nvaccess = tr32(NVRAM_ACCESS);
3181 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3185 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3186 u32 offset, u32 *val)
3191 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3194 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3195 EEPROM_ADDR_DEVID_MASK |
3197 tw32(GRC_EEPROM_ADDR,
3199 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3200 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3201 EEPROM_ADDR_ADDR_MASK) |
3202 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3204 for (i = 0; i < 1000; i++) {
3205 tmp = tr32(GRC_EEPROM_ADDR);
3207 if (tmp & EEPROM_ADDR_COMPLETE)
3211 if (!(tmp & EEPROM_ADDR_COMPLETE))
3214 tmp = tr32(GRC_EEPROM_DATA);
3217 * The data will always be opposite the native endian
3218 * format. Perform a blind byteswap to compensate.
3225 #define NVRAM_CMD_TIMEOUT 5000
3227 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3231 tw32(NVRAM_CMD, nvram_cmd);
3232 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3233 usleep_range(10, 40);
3234 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3240 if (i == NVRAM_CMD_TIMEOUT)
3246 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3248 if (tg3_flag(tp, NVRAM) &&
3249 tg3_flag(tp, NVRAM_BUFFERED) &&
3250 tg3_flag(tp, FLASH) &&
3251 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3252 (tp->nvram_jedecnum == JEDEC_ATMEL))
3254 addr = ((addr / tp->nvram_pagesize) <<
3255 ATMEL_AT45DB0X1B_PAGE_POS) +
3256 (addr % tp->nvram_pagesize);
3261 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3263 if (tg3_flag(tp, NVRAM) &&
3264 tg3_flag(tp, NVRAM_BUFFERED) &&
3265 tg3_flag(tp, FLASH) &&
3266 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3267 (tp->nvram_jedecnum == JEDEC_ATMEL))
3269 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3270 tp->nvram_pagesize) +
3271 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3276 /* NOTE: Data read in from NVRAM is byteswapped according to
3277 * the byteswapping settings for all other register accesses.
3278 * tg3 devices are BE devices, so on a BE machine, the data
3279 * returned will be exactly as it is seen in NVRAM. On a LE
3280 * machine, the 32-bit value will be byteswapped.
3282 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3286 if (!tg3_flag(tp, NVRAM))
3287 return tg3_nvram_read_using_eeprom(tp, offset, val);
3289 offset = tg3_nvram_phys_addr(tp, offset);
3291 if (offset > NVRAM_ADDR_MSK)
3294 ret = tg3_nvram_lock(tp);
3298 tg3_enable_nvram_access(tp);
3300 tw32(NVRAM_ADDR, offset);
3301 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3302 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3305 *val = tr32(NVRAM_RDDATA);
3307 tg3_disable_nvram_access(tp);
3309 tg3_nvram_unlock(tp);
3314 /* Ensures NVRAM data is in bytestream format. */
3315 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3318 int res = tg3_nvram_read(tp, offset, &v);
3320 *val = cpu_to_be32(v);
3324 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3325 u32 offset, u32 len, u8 *buf)
3330 for (i = 0; i < len; i += 4) {
3336 memcpy(&data, buf + i, 4);
3339 * The SEEPROM interface expects the data to always be opposite
3340 * the native endian format. We accomplish this by reversing
3341 * all the operations that would have been performed on the
3342 * data from a call to tg3_nvram_read_be32().
3344 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3346 val = tr32(GRC_EEPROM_ADDR);
3347 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3349 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3351 tw32(GRC_EEPROM_ADDR, val |
3352 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3353 (addr & EEPROM_ADDR_ADDR_MASK) |
3357 for (j = 0; j < 1000; j++) {
3358 val = tr32(GRC_EEPROM_ADDR);
3360 if (val & EEPROM_ADDR_COMPLETE)
3364 if (!(val & EEPROM_ADDR_COMPLETE)) {
3373 /* offset and length are dword aligned */
3374 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3378 u32 pagesize = tp->nvram_pagesize;
3379 u32 pagemask = pagesize - 1;
3383 tmp = kmalloc(pagesize, GFP_KERNEL);
3389 u32 phy_addr, page_off, size;
3391 phy_addr = offset & ~pagemask;
3393 for (j = 0; j < pagesize; j += 4) {
3394 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3395 (__be32 *) (tmp + j));
3402 page_off = offset & pagemask;
3409 memcpy(tmp + page_off, buf, size);
3411 offset = offset + (pagesize - page_off);
3413 tg3_enable_nvram_access(tp);
3416 * Before we can erase the flash page, we need
3417 * to issue a special "write enable" command.
3419 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3421 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 /* Erase the target page */
3425 tw32(NVRAM_ADDR, phy_addr);
3427 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3428 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3430 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3433 /* Issue another write enable to start the write. */
3434 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3436 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 for (j = 0; j < pagesize; j += 4) {
3442 data = *((__be32 *) (tmp + j));
3444 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3446 tw32(NVRAM_ADDR, phy_addr + j);
3448 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3452 nvram_cmd |= NVRAM_CMD_FIRST;
3453 else if (j == (pagesize - 4))
3454 nvram_cmd |= NVRAM_CMD_LAST;
3456 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3464 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3465 tg3_nvram_exec_cmd(tp, nvram_cmd);
3472 /* offset and length are dword aligned */
3473 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3478 for (i = 0; i < len; i += 4, offset += 4) {
3479 u32 page_off, phy_addr, nvram_cmd;
3482 memcpy(&data, buf + i, 4);
3483 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3485 page_off = offset % tp->nvram_pagesize;
3487 phy_addr = tg3_nvram_phys_addr(tp, offset);
3489 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3491 if (page_off == 0 || i == 0)
3492 nvram_cmd |= NVRAM_CMD_FIRST;
3493 if (page_off == (tp->nvram_pagesize - 4))
3494 nvram_cmd |= NVRAM_CMD_LAST;
3497 nvram_cmd |= NVRAM_CMD_LAST;
3499 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3500 !tg3_flag(tp, FLASH) ||
3501 !tg3_flag(tp, 57765_PLUS))
3502 tw32(NVRAM_ADDR, phy_addr);
3504 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3505 !tg3_flag(tp, 5755_PLUS) &&
3506 (tp->nvram_jedecnum == JEDEC_ST) &&
3507 (nvram_cmd & NVRAM_CMD_FIRST)) {
3510 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3511 ret = tg3_nvram_exec_cmd(tp, cmd);
3515 if (!tg3_flag(tp, FLASH)) {
3516 /* We always do complete word writes to eeprom. */
3517 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3520 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3527 /* offset and length are dword aligned */
3528 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3532 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3533 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3534 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3538 if (!tg3_flag(tp, NVRAM)) {
3539 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3543 ret = tg3_nvram_lock(tp);
3547 tg3_enable_nvram_access(tp);
3548 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3549 tw32(NVRAM_WRITE1, 0x406);
3551 grc_mode = tr32(GRC_MODE);
3552 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3554 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3555 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3558 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3562 grc_mode = tr32(GRC_MODE);
3563 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3565 tg3_disable_nvram_access(tp);
3566 tg3_nvram_unlock(tp);
3569 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3570 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3577 #define RX_CPU_SCRATCH_BASE 0x30000
3578 #define RX_CPU_SCRATCH_SIZE 0x04000
3579 #define TX_CPU_SCRATCH_BASE 0x34000
3580 #define TX_CPU_SCRATCH_SIZE 0x04000
3582 /* tp->lock is held. */
3583 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3586 const int iters = 10000;
3588 for (i = 0; i < iters; i++) {
3589 tw32(cpu_base + CPU_STATE, 0xffffffff);
3590 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3591 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3593 if (pci_channel_offline(tp->pdev))
3597 return (i == iters) ? -EBUSY : 0;
3600 /* tp->lock is held. */
3601 static int tg3_rxcpu_pause(struct tg3 *tp)
3603 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3605 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3606 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3612 /* tp->lock is held. */
3613 static int tg3_txcpu_pause(struct tg3 *tp)
3615 return tg3_pause_cpu(tp, TX_CPU_BASE);
3618 /* tp->lock is held. */
3619 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3621 tw32(cpu_base + CPU_STATE, 0xffffffff);
3622 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3625 /* tp->lock is held. */
3626 static void tg3_rxcpu_resume(struct tg3 *tp)
3628 tg3_resume_cpu(tp, RX_CPU_BASE);
3631 /* tp->lock is held. */
3632 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3636 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3638 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3639 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3641 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3644 if (cpu_base == RX_CPU_BASE) {
3645 rc = tg3_rxcpu_pause(tp);
3648 * There is only an Rx CPU for the 5750 derivative in the
3651 if (tg3_flag(tp, IS_SSB_CORE))
3654 rc = tg3_txcpu_pause(tp);
3658 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3659 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3663 /* Clear firmware's nvram arbitration. */
3664 if (tg3_flag(tp, NVRAM))
3665 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3669 static int tg3_fw_data_len(struct tg3 *tp,
3670 const struct tg3_firmware_hdr *fw_hdr)
3674 /* Non fragmented firmware have one firmware header followed by a
3675 * contiguous chunk of data to be written. The length field in that
3676 * header is not the length of data to be written but the complete
3677 * length of the bss. The data length is determined based on
3678 * tp->fw->size minus headers.
3680 * Fragmented firmware have a main header followed by multiple
3681 * fragments. Each fragment is identical to non fragmented firmware
3682 * with a firmware header followed by a contiguous chunk of data. In
3683 * the main header, the length field is unused and set to 0xffffffff.
3684 * In each fragment header the length is the entire size of that
3685 * fragment i.e. fragment data + header length. Data length is
3686 * therefore length field in the header minus TG3_FW_HDR_LEN.
3688 if (tp->fw_len == 0xffffffff)
3689 fw_len = be32_to_cpu(fw_hdr->len);
3691 fw_len = tp->fw->size;
3693 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3696 /* tp->lock is held. */
3697 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3698 u32 cpu_scratch_base, int cpu_scratch_size,
3699 const struct tg3_firmware_hdr *fw_hdr)
3702 void (*write_op)(struct tg3 *, u32, u32);
3703 int total_len = tp->fw->size;
3705 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3707 "%s: Trying to load TX cpu firmware which is 5705\n",
3712 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3713 write_op = tg3_write_mem;
3715 write_op = tg3_write_indirect_reg32;
3717 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3718 /* It is possible that bootcode is still loading at this point.
3719 * Get the nvram lock first before halting the cpu.
3721 int lock_err = tg3_nvram_lock(tp);
3722 err = tg3_halt_cpu(tp, cpu_base);
3724 tg3_nvram_unlock(tp);
3728 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3729 write_op(tp, cpu_scratch_base + i, 0);
3730 tw32(cpu_base + CPU_STATE, 0xffffffff);
3731 tw32(cpu_base + CPU_MODE,
3732 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3734 /* Subtract additional main header for fragmented firmware and
3735 * advance to the first fragment
3737 total_len -= TG3_FW_HDR_LEN;
3742 u32 *fw_data = (u32 *)(fw_hdr + 1);
3743 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3744 write_op(tp, cpu_scratch_base +
3745 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3747 be32_to_cpu(fw_data[i]));
3749 total_len -= be32_to_cpu(fw_hdr->len);
3751 /* Advance to next fragment */
3752 fw_hdr = (struct tg3_firmware_hdr *)
3753 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3754 } while (total_len > 0);
3762 /* tp->lock is held. */
3763 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3766 const int iters = 5;
3768 tw32(cpu_base + CPU_STATE, 0xffffffff);
3769 tw32_f(cpu_base + CPU_PC, pc);
3771 for (i = 0; i < iters; i++) {
3772 if (tr32(cpu_base + CPU_PC) == pc)
3774 tw32(cpu_base + CPU_STATE, 0xffffffff);
3775 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3776 tw32_f(cpu_base + CPU_PC, pc);
3780 return (i == iters) ? -EBUSY : 0;
3783 /* tp->lock is held. */
3784 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3786 const struct tg3_firmware_hdr *fw_hdr;
3789 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3791 /* Firmware blob starts with version numbers, followed by
3792 start address and length. We are setting complete length.
3793 length = end_address_of_bss - start_address_of_text.
3794 Remainder is the blob to be loaded contiguously
3795 from start address. */
3797 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3798 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3803 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3804 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3809 /* Now startup only the RX cpu. */
3810 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3811 be32_to_cpu(fw_hdr->base_addr));
3813 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3814 "should be %08x\n", __func__,
3815 tr32(RX_CPU_BASE + CPU_PC),
3816 be32_to_cpu(fw_hdr->base_addr));
3820 tg3_rxcpu_resume(tp);
3825 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3827 const int iters = 1000;
3831 /* Wait for boot code to complete initialization and enter service
3832 * loop. It is then safe to download service patches
3834 for (i = 0; i < iters; i++) {
3835 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3842 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3846 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3848 netdev_warn(tp->dev,
3849 "Other patches exist. Not downloading EEE patch\n");
3856 /* tp->lock is held. */
3857 static void tg3_load_57766_firmware(struct tg3 *tp)
3859 struct tg3_firmware_hdr *fw_hdr;
3861 if (!tg3_flag(tp, NO_NVRAM))
3864 if (tg3_validate_rxcpu_state(tp))
3870 /* This firmware blob has a different format than older firmware
3871 * releases as given below. The main difference is we have fragmented
3872 * data to be written to non-contiguous locations.
3874 * In the beginning we have a firmware header identical to other
3875 * firmware which consists of version, base addr and length. The length
3876 * here is unused and set to 0xffffffff.
3878 * This is followed by a series of firmware fragments which are
3879 * individually identical to previous firmware. i.e. they have the
3880 * firmware header and followed by data for that fragment. The version
3881 * field of the individual fragment header is unused.
3884 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3885 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3888 if (tg3_rxcpu_pause(tp))
3891 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3892 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3894 tg3_rxcpu_resume(tp);
3897 /* tp->lock is held. */
3898 static int tg3_load_tso_firmware(struct tg3 *tp)
3900 const struct tg3_firmware_hdr *fw_hdr;
3901 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3904 if (!tg3_flag(tp, FW_TSO))
3907 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3909 /* Firmware blob starts with version numbers, followed by
3910 start address and length. We are setting complete length.
3911 length = end_address_of_bss - start_address_of_text.
3912 Remainder is the blob to be loaded contiguously
3913 from start address. */
3915 cpu_scratch_size = tp->fw_len;
3917 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3918 cpu_base = RX_CPU_BASE;
3919 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3921 cpu_base = TX_CPU_BASE;
3922 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3923 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3926 err = tg3_load_firmware_cpu(tp, cpu_base,
3927 cpu_scratch_base, cpu_scratch_size,
3932 /* Now startup the cpu. */
3933 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3934 be32_to_cpu(fw_hdr->base_addr));
3937 "%s fails to set CPU PC, is %08x should be %08x\n",
3938 __func__, tr32(cpu_base + CPU_PC),
3939 be32_to_cpu(fw_hdr->base_addr));
3943 tg3_resume_cpu(tp, cpu_base);
3947 /* tp->lock is held. */
3948 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3950 u32 addr_high, addr_low;
3952 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3953 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3954 (mac_addr[4] << 8) | mac_addr[5]);
3957 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3958 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3962 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3966 /* tp->lock is held. */
3967 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3972 for (i = 0; i < 4; i++) {
3973 if (i == 1 && skip_mac_1)
3975 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3978 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3979 tg3_asic_rev(tp) == ASIC_REV_5704) {
3980 for (i = 4; i < 16; i++)
3981 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3984 addr_high = (tp->dev->dev_addr[0] +
3985 tp->dev->dev_addr[1] +
3986 tp->dev->dev_addr[2] +
3987 tp->dev->dev_addr[3] +
3988 tp->dev->dev_addr[4] +
3989 tp->dev->dev_addr[5]) &
3990 TX_BACKOFF_SEED_MASK;
3991 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994 static void tg3_enable_register_access(struct tg3 *tp)
3997 * Make sure register accesses (indirect or otherwise) will function
4000 pci_write_config_dword(tp->pdev,
4001 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004 static int tg3_power_up(struct tg3 *tp)
4008 tg3_enable_register_access(tp);
4010 err = pci_set_power_state(tp->pdev, PCI_D0);
4012 /* Switch out of Vaux if it is a NIC */
4013 tg3_pwrsrc_switch_to_vmain(tp);
4015 netdev_err(tp->dev, "Transition to D0 failed\n");
4021 static int tg3_setup_phy(struct tg3 *, bool);
4023 static int tg3_power_down_prepare(struct tg3 *tp)
4026 bool device_should_wake, do_low_power;
4028 tg3_enable_register_access(tp);
4030 /* Restore the CLKREQ setting. */
4031 if (tg3_flag(tp, CLKREQ_BUG))
4032 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4033 PCI_EXP_LNKCTL_CLKREQ_EN);
4035 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4036 tw32(TG3PCI_MISC_HOST_CTRL,
4037 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4039 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4040 tg3_flag(tp, WOL_ENABLE);
4042 if (tg3_flag(tp, USE_PHYLIB)) {
4043 do_low_power = false;
4044 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4045 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4046 struct phy_device *phydev;
4047 u32 phyid, advertising;
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4053 tp->link_config.speed = phydev->speed;
4054 tp->link_config.duplex = phydev->duplex;
4055 tp->link_config.autoneg = phydev->autoneg;
4056 tp->link_config.advertising = phydev->advertising;
4058 advertising = ADVERTISED_TP |
4060 ADVERTISED_Autoneg |
4061 ADVERTISED_10baseT_Half;
4063 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4064 if (tg3_flag(tp, WOL_SPEED_100MB))
4066 ADVERTISED_100baseT_Half |
4067 ADVERTISED_100baseT_Full |
4068 ADVERTISED_10baseT_Full;
4070 advertising |= ADVERTISED_10baseT_Full;
4073 phydev->advertising = advertising;
4075 phy_start_aneg(phydev);
4077 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4078 if (phyid != PHY_ID_BCMAC131) {
4079 phyid &= PHY_BCM_OUI_MASK;
4080 if (phyid == PHY_BCM_OUI_1 ||
4081 phyid == PHY_BCM_OUI_2 ||
4082 phyid == PHY_BCM_OUI_3)
4083 do_low_power = true;
4087 do_low_power = true;
4089 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4090 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4092 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4093 tg3_setup_phy(tp, false);
4096 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4099 val = tr32(GRC_VCPU_EXT_CTRL);
4100 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4101 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4105 for (i = 0; i < 200; i++) {
4106 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4107 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4112 if (tg3_flag(tp, WOL_CAP))
4113 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4114 WOL_DRV_STATE_SHUTDOWN |
4118 if (device_should_wake) {
4121 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4123 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4124 tg3_phy_auxctl_write(tp,
4125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4126 MII_TG3_AUXCTL_PCTL_WOL_EN |
4127 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4128 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4132 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4133 mac_mode = MAC_MODE_PORT_MODE_GMII;
4134 else if (tp->phy_flags &
4135 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4136 if (tp->link_config.active_speed == SPEED_1000)
4137 mac_mode = MAC_MODE_PORT_MODE_GMII;
4139 mac_mode = MAC_MODE_PORT_MODE_MII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4144 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4145 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4146 SPEED_100 : SPEED_10;
4147 if (tg3_5700_link_polarity(tp, speed))
4148 mac_mode |= MAC_MODE_LINK_POLARITY;
4150 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 if (!tg3_flag(tp, 5750_PLUS))
4157 tw32(MAC_LED_CTRL, tp->led_ctrl);
4159 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4160 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4161 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4162 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4164 if (tg3_flag(tp, ENABLE_APE))
4165 mac_mode |= MAC_MODE_APE_TX_EN |
4166 MAC_MODE_APE_RX_EN |
4167 MAC_MODE_TDE_ENABLE;
4169 tw32_f(MAC_MODE, mac_mode);
4172 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4176 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4177 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4178 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4181 base_val = tp->pci_clock_ctrl;
4182 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4183 CLOCK_CTRL_TXCLK_DISABLE);
4185 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4186 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4187 } else if (tg3_flag(tp, 5780_CLASS) ||
4188 tg3_flag(tp, CPMU_PRESENT) ||
4189 tg3_asic_rev(tp) == ASIC_REV_5906) {
4191 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4192 u32 newbits1, newbits2;
4194 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4195 tg3_asic_rev(tp) == ASIC_REV_5701) {
4196 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4197 CLOCK_CTRL_TXCLK_DISABLE |
4199 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4200 } else if (tg3_flag(tp, 5705_PLUS)) {
4201 newbits1 = CLOCK_CTRL_625_CORE;
4202 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4204 newbits1 = CLOCK_CTRL_ALTCLK;
4205 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 if (!tg3_flag(tp, 5705_PLUS)) {
4217 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4218 tg3_asic_rev(tp) == ASIC_REV_5701) {
4219 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4220 CLOCK_CTRL_TXCLK_DISABLE |
4221 CLOCK_CTRL_44MHZ_CORE);
4223 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4227 tp->pci_clock_ctrl | newbits3, 40);
4231 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4232 tg3_power_down_phy(tp, do_low_power);
4234 tg3_frob_aux_power(tp, true);
4236 /* Workaround for unstable PLL clock */
4237 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4238 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4239 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4240 u32 val = tr32(0x7d00);
4242 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4244 if (!tg3_flag(tp, ENABLE_ASF)) {
4247 err = tg3_nvram_lock(tp);
4248 tg3_halt_cpu(tp, RX_CPU_BASE);
4250 tg3_nvram_unlock(tp);
4254 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4256 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4261 static void tg3_power_down(struct tg3 *tp)
4263 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4264 pci_set_power_state(tp->pdev, PCI_D3hot);
4267 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4269 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4270 case MII_TG3_AUX_STAT_10HALF:
4272 *duplex = DUPLEX_HALF;
4275 case MII_TG3_AUX_STAT_10FULL:
4277 *duplex = DUPLEX_FULL;
4280 case MII_TG3_AUX_STAT_100HALF:
4282 *duplex = DUPLEX_HALF;
4285 case MII_TG3_AUX_STAT_100FULL:
4287 *duplex = DUPLEX_FULL;
4290 case MII_TG3_AUX_STAT_1000HALF:
4291 *speed = SPEED_1000;
4292 *duplex = DUPLEX_HALF;
4295 case MII_TG3_AUX_STAT_1000FULL:
4296 *speed = SPEED_1000;
4297 *duplex = DUPLEX_FULL;
4301 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4302 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4304 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4308 *speed = SPEED_UNKNOWN;
4309 *duplex = DUPLEX_UNKNOWN;
4314 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4319 new_adv = ADVERTISE_CSMA;
4320 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4321 new_adv |= mii_advertise_flowctrl(flowctrl);
4323 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4327 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4328 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4330 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4331 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4332 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4334 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4339 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 tw32(TG3_CPMU_EEE_MODE,
4343 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4345 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4350 /* Advertise 100-BaseTX EEE ability */
4351 if (advertise & ADVERTISED_100baseT_Full)
4352 val |= MDIO_AN_EEE_ADV_100TX;
4353 /* Advertise 1000-BaseT EEE ability */
4354 if (advertise & ADVERTISED_1000baseT_Full)
4355 val |= MDIO_AN_EEE_ADV_1000T;
4357 if (!tp->eee.eee_enabled) {
4359 tp->eee.advertised = 0;
4361 tp->eee.advertised = advertise &
4362 (ADVERTISED_100baseT_Full |
4363 ADVERTISED_1000baseT_Full);
4366 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4370 switch (tg3_asic_rev(tp)) {
4372 case ASIC_REV_57765:
4373 case ASIC_REV_57766:
4375 /* If we advertised any eee advertisements above... */
4377 val = MII_TG3_DSP_TAP26_ALNOKO |
4378 MII_TG3_DSP_TAP26_RMRXSTO |
4379 MII_TG3_DSP_TAP26_OPCSINPT;
4380 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4384 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4385 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4386 MII_TG3_DSP_CH34TP2_HIBW01);
4389 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4398 static void tg3_phy_copper_begin(struct tg3 *tp)
4400 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4401 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4405 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4406 adv = ADVERTISED_10baseT_Half |
4407 ADVERTISED_10baseT_Full;
4408 if (tg3_flag(tp, WOL_SPEED_100MB))
4409 adv |= ADVERTISED_100baseT_Half |
4410 ADVERTISED_100baseT_Full;
4411 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4412 if (!(tp->phy_flags &
4413 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4414 adv |= ADVERTISED_1000baseT_Half;
4415 adv |= ADVERTISED_1000baseT_Full;
4418 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4420 adv = tp->link_config.advertising;
4421 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4422 adv &= ~(ADVERTISED_1000baseT_Half |
4423 ADVERTISED_1000baseT_Full);
4425 fc = tp->link_config.flowctrl;
4428 tg3_phy_autoneg_cfg(tp, adv, fc);
4430 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4431 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4432 /* Normally during power down we want to autonegotiate
4433 * the lowest possible speed for WOL. However, to avoid
4434 * link flap, we leave it untouched.
4439 tg3_writephy(tp, MII_BMCR,
4440 BMCR_ANENABLE | BMCR_ANRESTART);
4443 u32 bmcr, orig_bmcr;
4445 tp->link_config.active_speed = tp->link_config.speed;
4446 tp->link_config.active_duplex = tp->link_config.duplex;
4448 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4449 /* With autoneg disabled, 5715 only links up when the
4450 * advertisement register has the configured speed
4453 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4457 switch (tp->link_config.speed) {
4463 bmcr |= BMCR_SPEED100;
4467 bmcr |= BMCR_SPEED1000;
4471 if (tp->link_config.duplex == DUPLEX_FULL)
4472 bmcr |= BMCR_FULLDPLX;
4474 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4475 (bmcr != orig_bmcr)) {
4476 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4477 for (i = 0; i < 1500; i++) {
4481 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4482 tg3_readphy(tp, MII_BMSR, &tmp))
4484 if (!(tmp & BMSR_LSTATUS)) {
4489 tg3_writephy(tp, MII_BMCR, bmcr);
4495 static int tg3_phy_pull_config(struct tg3 *tp)
4500 err = tg3_readphy(tp, MII_BMCR, &val);
4504 if (!(val & BMCR_ANENABLE)) {
4505 tp->link_config.autoneg = AUTONEG_DISABLE;
4506 tp->link_config.advertising = 0;
4507 tg3_flag_clear(tp, PAUSE_AUTONEG);
4511 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4513 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 tp->link_config.speed = SPEED_10;
4519 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 tp->link_config.speed = SPEED_100;
4524 case BMCR_SPEED1000:
4525 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4526 tp->link_config.speed = SPEED_1000;
4534 if (val & BMCR_FULLDPLX)
4535 tp->link_config.duplex = DUPLEX_FULL;
4537 tp->link_config.duplex = DUPLEX_HALF;
4539 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4545 tp->link_config.autoneg = AUTONEG_ENABLE;
4546 tp->link_config.advertising = ADVERTISED_Autoneg;
4547 tg3_flag_set(tp, PAUSE_AUTONEG);
4549 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4556 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4557 tp->link_config.advertising |= adv | ADVERTISED_TP;
4559 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4561 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4568 err = tg3_readphy(tp, MII_CTRL1000, &val);
4572 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4574 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4578 adv = tg3_decode_flowctrl_1000X(val);
4579 tp->link_config.flowctrl = adv;
4581 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4582 adv = mii_adv_to_ethtool_adv_x(val);
4585 tp->link_config.advertising |= adv;
4592 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4596 /* Turn off tap power management. */
4597 /* Set Extended packet length bit */
4598 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4600 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4601 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4602 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4603 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4604 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4611 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4613 struct ethtool_eee eee;
4615 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 tg3_eee_pull_config(tp, &eee);
4620 if (tp->eee.eee_enabled) {
4621 if (tp->eee.advertised != eee.advertised ||
4622 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4623 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 /* EEE is disabled but we're advertising */
4634 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4636 u32 advmsk, tgtadv, advertising;
4638 advertising = tp->link_config.advertising;
4639 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4641 advmsk = ADVERTISE_ALL;
4642 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4643 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4644 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 if ((*lcladv & advmsk) != tgtadv)
4653 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4656 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4658 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4662 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4663 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4664 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4665 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4666 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4668 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 if (tg3_ctrl != tgtadv)
4678 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4682 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4695 tp->link_config.rmt_adv = lpeth;
4700 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4702 if (curr_link_up != tp->link_up) {
4704 netif_carrier_on(tp->dev);
4706 netif_carrier_off(tp->dev);
4707 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4708 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 tg3_link_report(tp);
4718 static void tg3_clear_mac_status(struct tg3 *tp)
4723 MAC_STATUS_SYNC_CHANGED |
4724 MAC_STATUS_CFG_CHANGED |
4725 MAC_STATUS_MI_COMPLETION |
4726 MAC_STATUS_LNKSTATE_CHANGED);
4730 static void tg3_setup_eee(struct tg3 *tp)
4734 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4735 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4736 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4737 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4739 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4741 tw32_f(TG3_CPMU_EEE_CTRL,
4742 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4744 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4745 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4746 TG3_CPMU_EEEMD_LPI_IN_RX |
4747 TG3_CPMU_EEEMD_EEE_ENABLE;
4749 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4750 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4752 if (tg3_flag(tp, ENABLE_APE))
4753 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4755 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4757 tw32_f(TG3_CPMU_EEE_DBTMR1,
4758 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4759 (tp->eee.tx_lpi_timer & 0xffff));
4761 tw32_f(TG3_CPMU_EEE_DBTMR2,
4762 TG3_CPMU_DBTMR2_APE_TX_2047US |
4763 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4768 bool current_link_up;
4770 u32 lcl_adv, rmt_adv;
4775 tg3_clear_mac_status(tp);
4777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4783 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4785 /* Some third-party PHYs need to be reset on link going
4788 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4789 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4790 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4792 tg3_readphy(tp, MII_BMSR, &bmsr);
4793 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4794 !(bmsr & BMSR_LSTATUS))
4800 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4801 tg3_readphy(tp, MII_BMSR, &bmsr);
4802 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4803 !tg3_flag(tp, INIT_COMPLETE))
4806 if (!(bmsr & BMSR_LSTATUS)) {
4807 err = tg3_init_5401phy_dsp(tp);
4811 tg3_readphy(tp, MII_BMSR, &bmsr);
4812 for (i = 0; i < 1000; i++) {
4814 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4815 (bmsr & BMSR_LSTATUS)) {
4821 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4822 TG3_PHY_REV_BCM5401_B0 &&
4823 !(bmsr & BMSR_LSTATUS) &&
4824 tp->link_config.active_speed == SPEED_1000) {
4825 err = tg3_phy_reset(tp);
4827 err = tg3_init_5401phy_dsp(tp);
4832 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4833 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4834 /* 5701 {A0,B0} CRC bug workaround */
4835 tg3_writephy(tp, 0x15, 0x0a75);
4836 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4837 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4841 /* Clear pending interrupts... */
4842 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4843 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4846 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4847 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4848 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4850 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4851 tg3_asic_rev(tp) == ASIC_REV_5701) {
4852 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4853 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4854 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4856 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 current_link_up = false;
4860 current_speed = SPEED_UNKNOWN;
4861 current_duplex = DUPLEX_UNKNOWN;
4862 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4863 tp->link_config.rmt_adv = 0;
4865 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4866 err = tg3_phy_auxctl_read(tp,
4867 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4869 if (!err && !(val & (1 << 10))) {
4870 tg3_phy_auxctl_write(tp,
4871 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4878 for (i = 0; i < 100; i++) {
4879 tg3_readphy(tp, MII_BMSR, &bmsr);
4880 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4881 (bmsr & BMSR_LSTATUS))
4886 if (bmsr & BMSR_LSTATUS) {
4889 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4890 for (i = 0; i < 2000; i++) {
4892 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4897 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4902 for (i = 0; i < 200; i++) {
4903 tg3_readphy(tp, MII_BMCR, &bmcr);
4904 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4906 if (bmcr && bmcr != 0x7fff)
4914 tp->link_config.active_speed = current_speed;
4915 tp->link_config.active_duplex = current_duplex;
4917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4918 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4920 if ((bmcr & BMCR_ANENABLE) &&
4922 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4923 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4924 current_link_up = true;
4926 /* EEE settings changes take effect only after a phy
4927 * reset. If we have skipped a reset due to Link Flap
4928 * Avoidance being enabled, do it now.
4930 if (!eee_config_ok &&
4931 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4937 if (!(bmcr & BMCR_ANENABLE) &&
4938 tp->link_config.speed == current_speed &&
4939 tp->link_config.duplex == current_duplex) {
4940 current_link_up = true;
4944 if (current_link_up &&
4945 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4949 reg = MII_TG3_FET_GEN_STAT;
4950 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4952 reg = MII_TG3_EXT_STAT;
4953 bit = MII_TG3_EXT_STAT_MDIX;
4956 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4957 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4959 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4964 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4965 tg3_phy_copper_begin(tp);
4967 if (tg3_flag(tp, ROBOSWITCH)) {
4968 current_link_up = true;
4969 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4970 current_speed = SPEED_1000;
4971 current_duplex = DUPLEX_FULL;
4972 tp->link_config.active_speed = current_speed;
4973 tp->link_config.active_duplex = current_duplex;
4976 tg3_readphy(tp, MII_BMSR, &bmsr);
4977 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4978 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4979 current_link_up = true;
4982 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4983 if (current_link_up) {
4984 if (tp->link_config.active_speed == SPEED_100 ||
4985 tp->link_config.active_speed == SPEED_10)
4986 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4989 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4994 /* In order for the 5750 core in BCM4785 chip to work properly
4995 * in RGMII mode, the Led Control Register must be set up.
4997 if (tg3_flag(tp, RGMII_MODE)) {
4998 u32 led_ctrl = tr32(MAC_LED_CTRL);
4999 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5001 if (tp->link_config.active_speed == SPEED_10)
5002 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5003 else if (tp->link_config.active_speed == SPEED_100)
5004 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5005 LED_CTRL_100MBPS_ON);
5006 else if (tp->link_config.active_speed == SPEED_1000)
5007 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5008 LED_CTRL_1000MBPS_ON);
5010 tw32(MAC_LED_CTRL, led_ctrl);
5014 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5015 if (tp->link_config.active_duplex == DUPLEX_HALF)
5016 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5018 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5019 if (current_link_up &&
5020 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5021 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5023 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5026 /* ??? Without this setting Netgear GA302T PHY does not
5027 * ??? send/receive packets...
5029 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5030 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5031 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5032 tw32_f(MAC_MI_MODE, tp->mi_mode);
5036 tw32_f(MAC_MODE, tp->mac_mode);
5039 tg3_phy_eee_adjust(tp, current_link_up);
5041 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5042 /* Polled via timer. */
5043 tw32_f(MAC_EVENT, 0);
5045 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5049 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5051 tp->link_config.active_speed == SPEED_1000 &&
5052 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5055 (MAC_STATUS_SYNC_CHANGED |
5056 MAC_STATUS_CFG_CHANGED));
5059 NIC_SRAM_FIRMWARE_MBOX,
5060 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 /* Prevent send BD corruption. */
5064 if (tg3_flag(tp, CLKREQ_BUG)) {
5065 if (tp->link_config.active_speed == SPEED_100 ||
5066 tp->link_config.active_speed == SPEED_10)
5067 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5068 PCI_EXP_LNKCTL_CLKREQ_EN);
5070 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5071 PCI_EXP_LNKCTL_CLKREQ_EN);
5074 tg3_test_and_report_link_chg(tp, current_link_up);
5079 struct tg3_fiber_aneginfo {
5081 #define ANEG_STATE_UNKNOWN 0
5082 #define ANEG_STATE_AN_ENABLE 1
5083 #define ANEG_STATE_RESTART_INIT 2
5084 #define ANEG_STATE_RESTART 3
5085 #define ANEG_STATE_DISABLE_LINK_OK 4
5086 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5087 #define ANEG_STATE_ABILITY_DETECT 6
5088 #define ANEG_STATE_ACK_DETECT_INIT 7
5089 #define ANEG_STATE_ACK_DETECT 8
5090 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5091 #define ANEG_STATE_COMPLETE_ACK 10
5092 #define ANEG_STATE_IDLE_DETECT_INIT 11
5093 #define ANEG_STATE_IDLE_DETECT 12
5094 #define ANEG_STATE_LINK_OK 13
5095 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5096 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5099 #define MR_AN_ENABLE 0x00000001
5100 #define MR_RESTART_AN 0x00000002
5101 #define MR_AN_COMPLETE 0x00000004
5102 #define MR_PAGE_RX 0x00000008
5103 #define MR_NP_LOADED 0x00000010
5104 #define MR_TOGGLE_TX 0x00000020
5105 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5106 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5107 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5108 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5109 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5110 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5111 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5112 #define MR_TOGGLE_RX 0x00002000
5113 #define MR_NP_RX 0x00004000
5115 #define MR_LINK_OK 0x80000000
5117 unsigned long link_time, cur_time;
5119 u32 ability_match_cfg;
5120 int ability_match_count;
5122 char ability_match, idle_match, ack_match;
5124 u32 txconfig, rxconfig;
5125 #define ANEG_CFG_NP 0x00000080
5126 #define ANEG_CFG_ACK 0x00000040
5127 #define ANEG_CFG_RF2 0x00000020
5128 #define ANEG_CFG_RF1 0x00000010
5129 #define ANEG_CFG_PS2 0x00000001
5130 #define ANEG_CFG_PS1 0x00008000
5131 #define ANEG_CFG_HD 0x00004000
5132 #define ANEG_CFG_FD 0x00002000
5133 #define ANEG_CFG_INVAL 0x00001f06
5138 #define ANEG_TIMER_ENAB 2
5139 #define ANEG_FAILED -1
5141 #define ANEG_STATE_SETTLE_TIME 10000
5143 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5144 struct tg3_fiber_aneginfo *ap)
5147 unsigned long delta;
5151 if (ap->state == ANEG_STATE_UNKNOWN) {
5155 ap->ability_match_cfg = 0;
5156 ap->ability_match_count = 0;
5157 ap->ability_match = 0;
5163 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5164 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5166 if (rx_cfg_reg != ap->ability_match_cfg) {
5167 ap->ability_match_cfg = rx_cfg_reg;
5168 ap->ability_match = 0;
5169 ap->ability_match_count = 0;
5171 if (++ap->ability_match_count > 1) {
5172 ap->ability_match = 1;
5173 ap->ability_match_cfg = rx_cfg_reg;
5176 if (rx_cfg_reg & ANEG_CFG_ACK)
5184 ap->ability_match_cfg = 0;
5185 ap->ability_match_count = 0;
5186 ap->ability_match = 0;
5192 ap->rxconfig = rx_cfg_reg;
5195 switch (ap->state) {
5196 case ANEG_STATE_UNKNOWN:
5197 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5198 ap->state = ANEG_STATE_AN_ENABLE;
5201 case ANEG_STATE_AN_ENABLE:
5202 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5203 if (ap->flags & MR_AN_ENABLE) {
5206 ap->ability_match_cfg = 0;
5207 ap->ability_match_count = 0;
5208 ap->ability_match = 0;
5212 ap->state = ANEG_STATE_RESTART_INIT;
5214 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5218 case ANEG_STATE_RESTART_INIT:
5219 ap->link_time = ap->cur_time;
5220 ap->flags &= ~(MR_NP_LOADED);
5222 tw32(MAC_TX_AUTO_NEG, 0);
5223 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5224 tw32_f(MAC_MODE, tp->mac_mode);
5227 ret = ANEG_TIMER_ENAB;
5228 ap->state = ANEG_STATE_RESTART;
5231 case ANEG_STATE_RESTART:
5232 delta = ap->cur_time - ap->link_time;
5233 if (delta > ANEG_STATE_SETTLE_TIME)
5234 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5236 ret = ANEG_TIMER_ENAB;
5239 case ANEG_STATE_DISABLE_LINK_OK:
5243 case ANEG_STATE_ABILITY_DETECT_INIT:
5244 ap->flags &= ~(MR_TOGGLE_TX);
5245 ap->txconfig = ANEG_CFG_FD;
5246 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5247 if (flowctrl & ADVERTISE_1000XPAUSE)
5248 ap->txconfig |= ANEG_CFG_PS1;
5249 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5250 ap->txconfig |= ANEG_CFG_PS2;
5251 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5252 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5253 tw32_f(MAC_MODE, tp->mac_mode);
5256 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 case ANEG_STATE_ABILITY_DETECT:
5260 if (ap->ability_match != 0 && ap->rxconfig != 0)
5261 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5264 case ANEG_STATE_ACK_DETECT_INIT:
5265 ap->txconfig |= ANEG_CFG_ACK;
5266 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5267 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5268 tw32_f(MAC_MODE, tp->mac_mode);
5271 ap->state = ANEG_STATE_ACK_DETECT;
5274 case ANEG_STATE_ACK_DETECT:
5275 if (ap->ack_match != 0) {
5276 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5277 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5278 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5280 ap->state = ANEG_STATE_AN_ENABLE;
5282 } else if (ap->ability_match != 0 &&
5283 ap->rxconfig == 0) {
5284 ap->state = ANEG_STATE_AN_ENABLE;
5288 case ANEG_STATE_COMPLETE_ACK_INIT:
5289 if (ap->rxconfig & ANEG_CFG_INVAL) {
5293 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5294 MR_LP_ADV_HALF_DUPLEX |
5295 MR_LP_ADV_SYM_PAUSE |
5296 MR_LP_ADV_ASYM_PAUSE |
5297 MR_LP_ADV_REMOTE_FAULT1 |
5298 MR_LP_ADV_REMOTE_FAULT2 |
5299 MR_LP_ADV_NEXT_PAGE |
5302 if (ap->rxconfig & ANEG_CFG_FD)
5303 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5304 if (ap->rxconfig & ANEG_CFG_HD)
5305 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_PS1)
5307 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5308 if (ap->rxconfig & ANEG_CFG_PS2)
5309 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_RF1)
5311 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5312 if (ap->rxconfig & ANEG_CFG_RF2)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5314 if (ap->rxconfig & ANEG_CFG_NP)
5315 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5317 ap->link_time = ap->cur_time;
5319 ap->flags ^= (MR_TOGGLE_TX);
5320 if (ap->rxconfig & 0x0008)
5321 ap->flags |= MR_TOGGLE_RX;
5322 if (ap->rxconfig & ANEG_CFG_NP)
5323 ap->flags |= MR_NP_RX;
5324 ap->flags |= MR_PAGE_RX;
5326 ap->state = ANEG_STATE_COMPLETE_ACK;
5327 ret = ANEG_TIMER_ENAB;
5330 case ANEG_STATE_COMPLETE_ACK:
5331 if (ap->ability_match != 0 &&
5332 ap->rxconfig == 0) {
5333 ap->state = ANEG_STATE_AN_ENABLE;
5336 delta = ap->cur_time - ap->link_time;
5337 if (delta > ANEG_STATE_SETTLE_TIME) {
5338 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5339 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5341 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5342 !(ap->flags & MR_NP_RX)) {
5343 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5351 case ANEG_STATE_IDLE_DETECT_INIT:
5352 ap->link_time = ap->cur_time;
5353 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5354 tw32_f(MAC_MODE, tp->mac_mode);
5357 ap->state = ANEG_STATE_IDLE_DETECT;
5358 ret = ANEG_TIMER_ENAB;
5361 case ANEG_STATE_IDLE_DETECT:
5362 if (ap->ability_match != 0 &&
5363 ap->rxconfig == 0) {
5364 ap->state = ANEG_STATE_AN_ENABLE;
5367 delta = ap->cur_time - ap->link_time;
5368 if (delta > ANEG_STATE_SETTLE_TIME) {
5369 /* XXX another gem from the Broadcom driver :( */
5370 ap->state = ANEG_STATE_LINK_OK;
5374 case ANEG_STATE_LINK_OK:
5375 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5379 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5380 /* ??? unimplemented */
5383 case ANEG_STATE_NEXT_PAGE_WAIT:
5384 /* ??? unimplemented */
5395 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5398 struct tg3_fiber_aneginfo aninfo;
5399 int status = ANEG_FAILED;
5403 tw32_f(MAC_TX_AUTO_NEG, 0);
5405 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5406 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 memset(&aninfo, 0, sizeof(aninfo));
5413 aninfo.flags |= MR_AN_ENABLE;
5414 aninfo.state = ANEG_STATE_UNKNOWN;
5415 aninfo.cur_time = 0;
5417 while (++tick < 195000) {
5418 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5419 if (status == ANEG_DONE || status == ANEG_FAILED)
5425 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5426 tw32_f(MAC_MODE, tp->mac_mode);
5429 *txflags = aninfo.txconfig;
5430 *rxflags = aninfo.flags;
5432 if (status == ANEG_DONE &&
5433 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5434 MR_LP_ADV_FULL_DUPLEX)))
5440 static void tg3_init_bcm8002(struct tg3 *tp)
5442 u32 mac_status = tr32(MAC_STATUS);
5445 /* Reset when initting first time or we have a link. */
5446 if (tg3_flag(tp, INIT_COMPLETE) &&
5447 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 /* Set PLL lock range. */
5451 tg3_writephy(tp, 0x16, 0x8007);
5454 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5456 /* Wait for reset to complete. */
5457 /* XXX schedule_timeout() ... */
5458 for (i = 0; i < 500; i++)
5461 /* Config mode; select PMA/Ch 1 regs. */
5462 tg3_writephy(tp, 0x10, 0x8411);
5464 /* Enable auto-lock and comdet, select txclk for tx. */
5465 tg3_writephy(tp, 0x11, 0x0a10);
5467 tg3_writephy(tp, 0x18, 0x00a0);
5468 tg3_writephy(tp, 0x16, 0x41ff);
5470 /* Assert and deassert POR. */
5471 tg3_writephy(tp, 0x13, 0x0400);
5473 tg3_writephy(tp, 0x13, 0x0000);
5475 tg3_writephy(tp, 0x11, 0x0a50);
5477 tg3_writephy(tp, 0x11, 0x0a10);
5479 /* Wait for signal to stabilize */
5480 /* XXX schedule_timeout() ... */
5481 for (i = 0; i < 15000; i++)
5484 /* Deselect the channel register so we can read the PHYID
5487 tg3_writephy(tp, 0x10, 0x8011);
5490 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5493 bool current_link_up;
5494 u32 sg_dig_ctrl, sg_dig_status;
5495 u32 serdes_cfg, expected_sg_dig_ctrl;
5496 int workaround, port_a;
5499 expected_sg_dig_ctrl = 0;
5502 current_link_up = false;
5504 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5505 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5507 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5511 /* preserve bits 20-23 for voltage regulator */
5512 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5517 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5518 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5520 u32 val = serdes_cfg;
5526 tw32_f(MAC_SERDES_CFG, val);
5529 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5531 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5532 tg3_setup_flow_control(tp, 0, 0);
5533 current_link_up = true;
5538 /* Want auto-negotiation. */
5539 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5541 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5542 if (flowctrl & ADVERTISE_1000XPAUSE)
5543 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5544 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5545 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5547 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5548 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5549 tp->serdes_counter &&
5550 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5551 MAC_STATUS_RCVD_CFG)) ==
5552 MAC_STATUS_PCS_SYNCED)) {
5553 tp->serdes_counter--;
5554 current_link_up = true;
5559 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5560 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5564 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5565 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5566 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5567 MAC_STATUS_SIGNAL_DET)) {
5568 sg_dig_status = tr32(SG_DIG_STATUS);
5569 mac_status = tr32(MAC_STATUS);
5571 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5572 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5573 u32 local_adv = 0, remote_adv = 0;
5575 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5576 local_adv |= ADVERTISE_1000XPAUSE;
5577 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5578 local_adv |= ADVERTISE_1000XPSE_ASYM;
5580 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5581 remote_adv |= LPA_1000XPAUSE;
5582 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5583 remote_adv |= LPA_1000XPAUSE_ASYM;
5585 tp->link_config.rmt_adv =
5586 mii_adv_to_ethtool_adv_x(remote_adv);
5588 tg3_setup_flow_control(tp, local_adv, remote_adv);
5589 current_link_up = true;
5590 tp->serdes_counter = 0;
5591 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5592 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5593 if (tp->serdes_counter)
5594 tp->serdes_counter--;
5597 u32 val = serdes_cfg;
5604 tw32_f(MAC_SERDES_CFG, val);
5607 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5610 /* Link parallel detection - link is up */
5611 /* only if we have PCS_SYNC and not */
5612 /* receiving config code words */
5613 mac_status = tr32(MAC_STATUS);
5614 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5615 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5616 tg3_setup_flow_control(tp, 0, 0);
5617 current_link_up = true;
5619 TG3_PHYFLG_PARALLEL_DETECT;
5620 tp->serdes_counter =
5621 SERDES_PARALLEL_DET_TIMEOUT;
5623 goto restart_autoneg;
5627 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5628 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5632 return current_link_up;
5635 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5637 bool current_link_up = false;
5639 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5642 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5643 u32 txflags, rxflags;
5646 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5647 u32 local_adv = 0, remote_adv = 0;
5649 if (txflags & ANEG_CFG_PS1)
5650 local_adv |= ADVERTISE_1000XPAUSE;
5651 if (txflags & ANEG_CFG_PS2)
5652 local_adv |= ADVERTISE_1000XPSE_ASYM;
5654 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5655 remote_adv |= LPA_1000XPAUSE;
5656 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE_ASYM;
5659 tp->link_config.rmt_adv =
5660 mii_adv_to_ethtool_adv_x(remote_adv);
5662 tg3_setup_flow_control(tp, local_adv, remote_adv);
5664 current_link_up = true;
5666 for (i = 0; i < 30; i++) {
5669 (MAC_STATUS_SYNC_CHANGED |
5670 MAC_STATUS_CFG_CHANGED));
5672 if ((tr32(MAC_STATUS) &
5673 (MAC_STATUS_SYNC_CHANGED |
5674 MAC_STATUS_CFG_CHANGED)) == 0)
5678 mac_status = tr32(MAC_STATUS);
5679 if (!current_link_up &&
5680 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5681 !(mac_status & MAC_STATUS_RCVD_CFG))
5682 current_link_up = true;
5684 tg3_setup_flow_control(tp, 0, 0);
5686 /* Forcing 1000FD link up. */
5687 current_link_up = true;
5689 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 tw32_f(MAC_MODE, tp->mac_mode);
5697 return current_link_up;
5700 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5703 u16 orig_active_speed;
5704 u8 orig_active_duplex;
5706 bool current_link_up;
5709 orig_pause_cfg = tp->link_config.active_flowctrl;
5710 orig_active_speed = tp->link_config.active_speed;
5711 orig_active_duplex = tp->link_config.active_duplex;
5713 if (!tg3_flag(tp, HW_AUTONEG) &&
5715 tg3_flag(tp, INIT_COMPLETE)) {
5716 mac_status = tr32(MAC_STATUS);
5717 mac_status &= (MAC_STATUS_PCS_SYNCED |
5718 MAC_STATUS_SIGNAL_DET |
5719 MAC_STATUS_CFG_CHANGED |
5720 MAC_STATUS_RCVD_CFG);
5721 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5722 MAC_STATUS_SIGNAL_DET)) {
5723 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5724 MAC_STATUS_CFG_CHANGED));
5729 tw32_f(MAC_TX_AUTO_NEG, 0);
5731 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5732 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5733 tw32_f(MAC_MODE, tp->mac_mode);
5736 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5737 tg3_init_bcm8002(tp);
5739 /* Enable link change event even when serdes polling. */
5740 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 current_link_up = false;
5744 tp->link_config.rmt_adv = 0;
5745 mac_status = tr32(MAC_STATUS);
5747 if (tg3_flag(tp, HW_AUTONEG))
5748 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5750 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5752 tp->napi[0].hw_status->status =
5753 (SD_STATUS_UPDATED |
5754 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5756 for (i = 0; i < 100; i++) {
5757 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5758 MAC_STATUS_CFG_CHANGED));
5760 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5761 MAC_STATUS_CFG_CHANGED |
5762 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5766 mac_status = tr32(MAC_STATUS);
5767 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5768 current_link_up = false;
5769 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5770 tp->serdes_counter == 0) {
5771 tw32_f(MAC_MODE, (tp->mac_mode |
5772 MAC_MODE_SEND_CONFIGS));
5774 tw32_f(MAC_MODE, tp->mac_mode);
5778 if (current_link_up) {
5779 tp->link_config.active_speed = SPEED_1000;
5780 tp->link_config.active_duplex = DUPLEX_FULL;
5781 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5782 LED_CTRL_LNKLED_OVERRIDE |
5783 LED_CTRL_1000MBPS_ON));
5785 tp->link_config.active_speed = SPEED_UNKNOWN;
5786 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5788 LED_CTRL_LNKLED_OVERRIDE |
5789 LED_CTRL_TRAFFIC_OVERRIDE));
5792 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5793 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5794 if (orig_pause_cfg != now_pause_cfg ||
5795 orig_active_speed != tp->link_config.active_speed ||
5796 orig_active_duplex != tp->link_config.active_duplex)
5797 tg3_link_report(tp);
5803 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5807 u16 current_speed = SPEED_UNKNOWN;
5808 u8 current_duplex = DUPLEX_UNKNOWN;
5809 bool current_link_up = false;
5810 u32 local_adv, remote_adv, sgsr;
5812 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5813 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5814 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5815 (sgsr & SERDES_TG3_SGMII_MODE)) {
5820 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5822 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5823 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5825 current_link_up = true;
5826 if (sgsr & SERDES_TG3_SPEED_1000) {
5827 current_speed = SPEED_1000;
5828 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5829 } else if (sgsr & SERDES_TG3_SPEED_100) {
5830 current_speed = SPEED_100;
5831 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5833 current_speed = SPEED_10;
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5838 current_duplex = DUPLEX_FULL;
5840 current_duplex = DUPLEX_HALF;
5843 tw32_f(MAC_MODE, tp->mac_mode);
5846 tg3_clear_mac_status(tp);
5848 goto fiber_setup_done;
5851 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5852 tw32_f(MAC_MODE, tp->mac_mode);
5855 tg3_clear_mac_status(tp);
5860 tp->link_config.rmt_adv = 0;
5862 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5863 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5864 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5865 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5866 bmsr |= BMSR_LSTATUS;
5868 bmsr &= ~BMSR_LSTATUS;
5871 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5873 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5874 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5875 /* do nothing, just check for link up at the end */
5876 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5879 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5880 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5881 ADVERTISE_1000XPAUSE |
5882 ADVERTISE_1000XPSE_ASYM |
5885 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5886 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5888 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5889 tg3_writephy(tp, MII_ADVERTISE, newadv);
5890 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5891 tg3_writephy(tp, MII_BMCR, bmcr);
5893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5894 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5895 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5902 bmcr &= ~BMCR_SPEED1000;
5903 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5905 if (tp->link_config.duplex == DUPLEX_FULL)
5906 new_bmcr |= BMCR_FULLDPLX;
5908 if (new_bmcr != bmcr) {
5909 /* BMCR_SPEED1000 is a reserved bit that needs
5910 * to be set on write.
5912 new_bmcr |= BMCR_SPEED1000;
5914 /* Force a linkdown */
5918 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5919 adv &= ~(ADVERTISE_1000XFULL |
5920 ADVERTISE_1000XHALF |
5922 tg3_writephy(tp, MII_ADVERTISE, adv);
5923 tg3_writephy(tp, MII_BMCR, bmcr |
5927 tg3_carrier_off(tp);
5929 tg3_writephy(tp, MII_BMCR, new_bmcr);
5931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5932 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5933 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5934 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5935 bmsr |= BMSR_LSTATUS;
5937 bmsr &= ~BMSR_LSTATUS;
5939 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5943 if (bmsr & BMSR_LSTATUS) {
5944 current_speed = SPEED_1000;
5945 current_link_up = true;
5946 if (bmcr & BMCR_FULLDPLX)
5947 current_duplex = DUPLEX_FULL;
5949 current_duplex = DUPLEX_HALF;
5954 if (bmcr & BMCR_ANENABLE) {
5957 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5958 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5959 common = local_adv & remote_adv;
5960 if (common & (ADVERTISE_1000XHALF |
5961 ADVERTISE_1000XFULL)) {
5962 if (common & ADVERTISE_1000XFULL)
5963 current_duplex = DUPLEX_FULL;
5965 current_duplex = DUPLEX_HALF;
5967 tp->link_config.rmt_adv =
5968 mii_adv_to_ethtool_adv_x(remote_adv);
5969 } else if (!tg3_flag(tp, 5780_CLASS)) {
5970 /* Link is up via parallel detect */
5972 current_link_up = false;
5978 if (current_link_up && current_duplex == DUPLEX_FULL)
5979 tg3_setup_flow_control(tp, local_adv, remote_adv);
5981 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5982 if (tp->link_config.active_duplex == DUPLEX_HALF)
5983 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5985 tw32_f(MAC_MODE, tp->mac_mode);
5988 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5990 tp->link_config.active_speed = current_speed;
5991 tp->link_config.active_duplex = current_duplex;
5993 tg3_test_and_report_link_chg(tp, current_link_up);
5997 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5999 if (tp->serdes_counter) {
6000 /* Give autoneg time to complete. */
6001 tp->serdes_counter--;
6006 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 tg3_readphy(tp, MII_BMCR, &bmcr);
6010 if (bmcr & BMCR_ANENABLE) {
6013 /* Select shadow register 0x1f */
6014 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6015 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6017 /* Select expansion interrupt status register */
6018 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6019 MII_TG3_DSP_EXP1_INT_STAT);
6020 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6021 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6024 /* We have signal detect and not receiving
6025 * config code words, link is up by parallel
6029 bmcr &= ~BMCR_ANENABLE;
6030 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6031 tg3_writephy(tp, MII_BMCR, bmcr);
6032 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6035 } else if (tp->link_up &&
6036 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6037 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6040 /* Select expansion interrupt status register */
6041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6042 MII_TG3_DSP_EXP1_INT_STAT);
6043 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6047 /* Config code words received, turn on autoneg. */
6048 tg3_readphy(tp, MII_BMCR, &bmcr);
6049 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6051 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6057 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6063 err = tg3_setup_fiber_phy(tp, force_reset);
6064 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6065 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6067 err = tg3_setup_copper_phy(tp, force_reset);
6069 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6072 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6073 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6075 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6080 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6081 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6082 tw32(GRC_MISC_CFG, val);
6085 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6086 (6 << TX_LENGTHS_IPG_SHIFT);
6087 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6088 tg3_asic_rev(tp) == ASIC_REV_5762)
6089 val |= tr32(MAC_TX_LENGTHS) &
6090 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6091 TX_LENGTHS_CNT_DWN_VAL_MSK);
6093 if (tp->link_config.active_speed == SPEED_1000 &&
6094 tp->link_config.active_duplex == DUPLEX_HALF)
6095 tw32(MAC_TX_LENGTHS, val |
6096 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6098 tw32(MAC_TX_LENGTHS, val |
6099 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6101 if (!tg3_flag(tp, 5705_PLUS)) {
6103 tw32(HOSTCC_STAT_COAL_TICKS,
6104 tp->coal.stats_block_coalesce_usecs);
6106 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6110 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6111 val = tr32(PCIE_PWR_MGMT_THRESH);
6113 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6117 tw32(PCIE_PWR_MGMT_THRESH, val);
6123 /* tp->lock must be held */
6124 static u64 tg3_refclk_read(struct tg3 *tp)
6126 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6127 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6130 /* tp->lock must be held */
6131 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6133 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6135 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6136 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6137 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6138 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6141 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6142 static inline void tg3_full_unlock(struct tg3 *tp);
6143 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6145 struct tg3 *tp = netdev_priv(dev);
6147 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6148 SOF_TIMESTAMPING_RX_SOFTWARE |
6149 SOF_TIMESTAMPING_SOFTWARE;
6151 if (tg3_flag(tp, PTP_CAPABLE)) {
6152 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6153 SOF_TIMESTAMPING_RX_HARDWARE |
6154 SOF_TIMESTAMPING_RAW_HARDWARE;
6158 info->phc_index = ptp_clock_index(tp->ptp_clock);
6160 info->phc_index = -1;
6162 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6164 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6165 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6166 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6167 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6171 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6173 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6174 bool neg_adj = false;
6182 /* Frequency adjustment is performed using hardware with a 24 bit
6183 * accumulator and a programmable correction value. On each clk, the
6184 * correction value gets added to the accumulator and when it
6185 * overflows, the time counter is incremented/decremented.
6187 * So conversion from ppb to correction value is
6188 * ppb * (1 << 24) / 1000000000
6190 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6191 TG3_EAV_REF_CLK_CORRECT_MASK;
6193 tg3_full_lock(tp, 0);
6196 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6197 TG3_EAV_REF_CLK_CORRECT_EN |
6198 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6200 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6202 tg3_full_unlock(tp);
6207 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6209 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6211 tg3_full_lock(tp, 0);
6212 tp->ptp_adjust += delta;
6213 tg3_full_unlock(tp);
6218 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
6221 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6223 tg3_full_lock(tp, 0);
6224 ns = tg3_refclk_read(tp);
6225 ns += tp->ptp_adjust;
6226 tg3_full_unlock(tp);
6228 *ts = ns_to_timespec64(ns);
6233 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6234 const struct timespec64 *ts)
6237 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6239 ns = timespec64_to_ns(ts);
6241 tg3_full_lock(tp, 0);
6242 tg3_refclk_write(tp, ns);
6244 tg3_full_unlock(tp);
6249 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6250 struct ptp_clock_request *rq, int on)
6252 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6257 case PTP_CLK_REQ_PEROUT:
6258 if (rq->perout.index != 0)
6261 tg3_full_lock(tp, 0);
6262 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6263 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6268 nsec = rq->perout.start.sec * 1000000000ULL +
6269 rq->perout.start.nsec;
6271 if (rq->perout.period.sec || rq->perout.period.nsec) {
6272 netdev_warn(tp->dev,
6273 "Device supports only a one-shot timesync output, period must be 0\n");
6278 if (nsec & (1ULL << 63)) {
6279 netdev_warn(tp->dev,
6280 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6285 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6286 tw32(TG3_EAV_WATCHDOG0_MSB,
6287 TG3_EAV_WATCHDOG0_EN |
6288 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6290 tw32(TG3_EAV_REF_CLCK_CTL,
6291 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6293 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6294 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6298 tg3_full_unlock(tp);
6308 static const struct ptp_clock_info tg3_ptp_caps = {
6309 .owner = THIS_MODULE,
6310 .name = "tg3 clock",
6311 .max_adj = 250000000,
6317 .adjfreq = tg3_ptp_adjfreq,
6318 .adjtime = tg3_ptp_adjtime,
6319 .gettime64 = tg3_ptp_gettime,
6320 .settime64 = tg3_ptp_settime,
6321 .enable = tg3_ptp_enable,
6324 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6325 struct skb_shared_hwtstamps *timestamp)
6327 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6328 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6332 /* tp->lock must be held */
6333 static void tg3_ptp_init(struct tg3 *tp)
6335 if (!tg3_flag(tp, PTP_CAPABLE))
6338 /* Initialize the hardware clock to the system time. */
6339 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6341 tp->ptp_info = tg3_ptp_caps;
6344 /* tp->lock must be held */
6345 static void tg3_ptp_resume(struct tg3 *tp)
6347 if (!tg3_flag(tp, PTP_CAPABLE))
6350 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6354 static void tg3_ptp_fini(struct tg3 *tp)
6356 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6359 ptp_clock_unregister(tp->ptp_clock);
6360 tp->ptp_clock = NULL;
6364 static inline int tg3_irq_sync(struct tg3 *tp)
6366 return tp->irq_sync;
6369 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6373 dst = (u32 *)((u8 *)dst + off);
6374 for (i = 0; i < len; i += sizeof(u32))
6375 *dst++ = tr32(off + i);
6378 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6380 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6381 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6382 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6383 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6384 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6385 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6386 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6387 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6388 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6389 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6390 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6391 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6392 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6393 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6394 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6395 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6396 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6397 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6398 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6400 if (tg3_flag(tp, SUPPORT_MSIX))
6401 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6403 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6404 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6405 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6406 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6408 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6409 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6410 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6412 if (!tg3_flag(tp, 5705_PLUS)) {
6413 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6414 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6415 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6418 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6419 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6420 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6421 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6422 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6424 if (tg3_flag(tp, NVRAM))
6425 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6428 static void tg3_dump_state(struct tg3 *tp)
6433 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6437 if (tg3_flag(tp, PCI_EXPRESS)) {
6438 /* Read up to but not including private PCI registers */
6439 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6440 regs[i / sizeof(u32)] = tr32(i);
6442 tg3_dump_legacy_regs(tp, regs);
6444 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6445 if (!regs[i + 0] && !regs[i + 1] &&
6446 !regs[i + 2] && !regs[i + 3])
6449 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6451 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6456 for (i = 0; i < tp->irq_cnt; i++) {
6457 struct tg3_napi *tnapi = &tp->napi[i];
6459 /* SW status block */
6461 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6463 tnapi->hw_status->status,
6464 tnapi->hw_status->status_tag,
6465 tnapi->hw_status->rx_jumbo_consumer,
6466 tnapi->hw_status->rx_consumer,
6467 tnapi->hw_status->rx_mini_consumer,
6468 tnapi->hw_status->idx[0].rx_producer,
6469 tnapi->hw_status->idx[0].tx_consumer);
6472 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6474 tnapi->last_tag, tnapi->last_irq_tag,
6475 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6477 tnapi->prodring.rx_std_prod_idx,
6478 tnapi->prodring.rx_std_cons_idx,
6479 tnapi->prodring.rx_jmb_prod_idx,
6480 tnapi->prodring.rx_jmb_cons_idx);
6484 /* This is called whenever we suspect that the system chipset is re-
6485 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6486 * is bogus tx completions. We try to recover by setting the
6487 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6490 static void tg3_tx_recover(struct tg3 *tp)
6492 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6493 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6495 netdev_warn(tp->dev,
6496 "The system may be re-ordering memory-mapped I/O "
6497 "cycles to the network device, attempting to recover. "
6498 "Please report the problem to the driver maintainer "
6499 "and include system chipset information.\n");
6501 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6504 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6506 /* Tell compiler to fetch tx indices from memory. */
6508 return tnapi->tx_pending -
6509 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6512 /* Tigon3 never reports partial packet sends. So we do not
6513 * need special logic to handle SKBs that have not had all
6514 * of their frags sent yet, like SunGEM does.
6516 static void tg3_tx(struct tg3_napi *tnapi)
6518 struct tg3 *tp = tnapi->tp;
6519 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6520 u32 sw_idx = tnapi->tx_cons;
6521 struct netdev_queue *txq;
6522 int index = tnapi - tp->napi;
6523 unsigned int pkts_compl = 0, bytes_compl = 0;
6525 if (tg3_flag(tp, ENABLE_TSS))
6528 txq = netdev_get_tx_queue(tp->dev, index);
6530 while (sw_idx != hw_idx) {
6531 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6532 struct sk_buff *skb = ri->skb;
6535 if (unlikely(skb == NULL)) {
6540 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6541 struct skb_shared_hwtstamps timestamp;
6542 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6543 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6545 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6547 skb_tstamp_tx(skb, ×tamp);
6550 pci_unmap_single(tp->pdev,
6551 dma_unmap_addr(ri, mapping),
6557 while (ri->fragmented) {
6558 ri->fragmented = false;
6559 sw_idx = NEXT_TX(sw_idx);
6560 ri = &tnapi->tx_buffers[sw_idx];
6563 sw_idx = NEXT_TX(sw_idx);
6565 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6566 ri = &tnapi->tx_buffers[sw_idx];
6567 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6570 pci_unmap_page(tp->pdev,
6571 dma_unmap_addr(ri, mapping),
6572 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6575 while (ri->fragmented) {
6576 ri->fragmented = false;
6577 sw_idx = NEXT_TX(sw_idx);
6578 ri = &tnapi->tx_buffers[sw_idx];
6581 sw_idx = NEXT_TX(sw_idx);
6585 bytes_compl += skb->len;
6587 dev_kfree_skb_any(skb);
6589 if (unlikely(tx_bug)) {
6595 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6597 tnapi->tx_cons = sw_idx;
6599 /* Need to make the tx_cons update visible to tg3_start_xmit()
6600 * before checking for netif_queue_stopped(). Without the
6601 * memory barrier, there is a small possibility that tg3_start_xmit()
6602 * will miss it and cause the queue to be stopped forever.
6606 if (unlikely(netif_tx_queue_stopped(txq) &&
6607 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6608 __netif_tx_lock(txq, smp_processor_id());
6609 if (netif_tx_queue_stopped(txq) &&
6610 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6611 netif_tx_wake_queue(txq);
6612 __netif_tx_unlock(txq);
6616 static void tg3_frag_free(bool is_frag, void *data)
6619 skb_free_frag(data);
6624 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6626 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6627 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6632 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6633 map_sz, PCI_DMA_FROMDEVICE);
6634 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6639 /* Returns size of skb allocated or < 0 on error.
6641 * We only need to fill in the address because the other members
6642 * of the RX descriptor are invariant, see tg3_init_rings.
6644 * Note the purposeful assymetry of cpu vs. chip accesses. For
6645 * posting buffers we only dirty the first cache line of the RX
6646 * descriptor (containing the address). Whereas for the RX status
6647 * buffers the cpu only reads the last cacheline of the RX descriptor
6648 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6650 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6651 u32 opaque_key, u32 dest_idx_unmasked,
6652 unsigned int *frag_size)
6654 struct tg3_rx_buffer_desc *desc;
6655 struct ring_info *map;
6658 int skb_size, data_size, dest_idx;
6660 switch (opaque_key) {
6661 case RXD_OPAQUE_RING_STD:
6662 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6663 desc = &tpr->rx_std[dest_idx];
6664 map = &tpr->rx_std_buffers[dest_idx];
6665 data_size = tp->rx_pkt_map_sz;
6668 case RXD_OPAQUE_RING_JUMBO:
6669 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6670 desc = &tpr->rx_jmb[dest_idx].std;
6671 map = &tpr->rx_jmb_buffers[dest_idx];
6672 data_size = TG3_RX_JMB_MAP_SZ;
6679 /* Do not overwrite any of the map or rp information
6680 * until we are sure we can commit to a new buffer.
6682 * Callers depend upon this behavior and assume that
6683 * we leave everything unchanged if we fail.
6685 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6686 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6687 if (skb_size <= PAGE_SIZE) {
6688 data = netdev_alloc_frag(skb_size);
6689 *frag_size = skb_size;
6691 data = kmalloc(skb_size, GFP_ATOMIC);
6697 mapping = pci_map_single(tp->pdev,
6698 data + TG3_RX_OFFSET(tp),
6700 PCI_DMA_FROMDEVICE);
6701 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6702 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6707 dma_unmap_addr_set(map, mapping, mapping);
6709 desc->addr_hi = ((u64)mapping >> 32);
6710 desc->addr_lo = ((u64)mapping & 0xffffffff);
6715 /* We only need to move over in the address because the other
6716 * members of the RX descriptor are invariant. See notes above
6717 * tg3_alloc_rx_data for full details.
6719 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6720 struct tg3_rx_prodring_set *dpr,
6721 u32 opaque_key, int src_idx,
6722 u32 dest_idx_unmasked)
6724 struct tg3 *tp = tnapi->tp;
6725 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6726 struct ring_info *src_map, *dest_map;
6727 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6730 switch (opaque_key) {
6731 case RXD_OPAQUE_RING_STD:
6732 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6733 dest_desc = &dpr->rx_std[dest_idx];
6734 dest_map = &dpr->rx_std_buffers[dest_idx];
6735 src_desc = &spr->rx_std[src_idx];
6736 src_map = &spr->rx_std_buffers[src_idx];
6739 case RXD_OPAQUE_RING_JUMBO:
6740 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6741 dest_desc = &dpr->rx_jmb[dest_idx].std;
6742 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6743 src_desc = &spr->rx_jmb[src_idx].std;
6744 src_map = &spr->rx_jmb_buffers[src_idx];
6751 dest_map->data = src_map->data;
6752 dma_unmap_addr_set(dest_map, mapping,
6753 dma_unmap_addr(src_map, mapping));
6754 dest_desc->addr_hi = src_desc->addr_hi;
6755 dest_desc->addr_lo = src_desc->addr_lo;
6757 /* Ensure that the update to the skb happens after the physical
6758 * addresses have been transferred to the new BD location.
6762 src_map->data = NULL;
6765 /* The RX ring scheme is composed of multiple rings which post fresh
6766 * buffers to the chip, and one special ring the chip uses to report
6767 * status back to the host.
6769 * The special ring reports the status of received packets to the
6770 * host. The chip does not write into the original descriptor the
6771 * RX buffer was obtained from. The chip simply takes the original
6772 * descriptor as provided by the host, updates the status and length
6773 * field, then writes this into the next status ring entry.
6775 * Each ring the host uses to post buffers to the chip is described
6776 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6777 * it is first placed into the on-chip ram. When the packet's length
6778 * is known, it walks down the TG3_BDINFO entries to select the ring.
6779 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6780 * which is within the range of the new packet's length is chosen.
6782 * The "separate ring for rx status" scheme may sound queer, but it makes
6783 * sense from a cache coherency perspective. If only the host writes
6784 * to the buffer post rings, and only the chip writes to the rx status
6785 * rings, then cache lines never move beyond shared-modified state.
6786 * If both the host and chip were to write into the same ring, cache line
6787 * eviction could occur since both entities want it in an exclusive state.
6789 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6791 struct tg3 *tp = tnapi->tp;
6792 u32 work_mask, rx_std_posted = 0;
6793 u32 std_prod_idx, jmb_prod_idx;
6794 u32 sw_idx = tnapi->rx_rcb_ptr;
6797 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6799 hw_idx = *(tnapi->rx_rcb_prod_idx);
6801 * We need to order the read of hw_idx and the read of
6802 * the opaque cookie.
6807 std_prod_idx = tpr->rx_std_prod_idx;
6808 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6809 while (sw_idx != hw_idx && budget > 0) {
6810 struct ring_info *ri;
6811 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6813 struct sk_buff *skb;
6814 dma_addr_t dma_addr;
6815 u32 opaque_key, desc_idx, *post_ptr;
6819 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6820 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6821 if (opaque_key == RXD_OPAQUE_RING_STD) {
6822 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6823 dma_addr = dma_unmap_addr(ri, mapping);
6825 post_ptr = &std_prod_idx;
6827 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6828 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6829 dma_addr = dma_unmap_addr(ri, mapping);
6831 post_ptr = &jmb_prod_idx;
6833 goto next_pkt_nopost;
6835 work_mask |= opaque_key;
6837 if (desc->err_vlan & RXD_ERR_MASK) {
6839 tg3_recycle_rx(tnapi, tpr, opaque_key,
6840 desc_idx, *post_ptr);
6842 /* Other statistics kept track of by card. */
6847 prefetch(data + TG3_RX_OFFSET(tp));
6848 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6851 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6852 RXD_FLAG_PTPSTAT_PTPV1 ||
6853 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6854 RXD_FLAG_PTPSTAT_PTPV2) {
6855 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6856 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6859 if (len > TG3_RX_COPY_THRESH(tp)) {
6861 unsigned int frag_size;
6863 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6864 *post_ptr, &frag_size);
6868 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6869 PCI_DMA_FROMDEVICE);
6871 /* Ensure that the update to the data happens
6872 * after the usage of the old DMA mapping.
6878 skb = build_skb(data, frag_size);
6880 tg3_frag_free(frag_size != 0, data);
6881 goto drop_it_no_recycle;
6883 skb_reserve(skb, TG3_RX_OFFSET(tp));
6885 tg3_recycle_rx(tnapi, tpr, opaque_key,
6886 desc_idx, *post_ptr);
6888 skb = netdev_alloc_skb(tp->dev,
6889 len + TG3_RAW_IP_ALIGN);
6891 goto drop_it_no_recycle;
6893 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6894 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6896 data + TG3_RX_OFFSET(tp),
6898 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6903 tg3_hwclock_to_timestamp(tp, tstamp,
6904 skb_hwtstamps(skb));
6906 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6907 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6908 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6909 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6910 skb->ip_summed = CHECKSUM_UNNECESSARY;
6912 skb_checksum_none_assert(skb);
6914 skb->protocol = eth_type_trans(skb, tp->dev);
6916 if (len > (tp->dev->mtu + ETH_HLEN) &&
6917 skb->protocol != htons(ETH_P_8021Q) &&
6918 skb->protocol != htons(ETH_P_8021AD)) {
6919 dev_kfree_skb_any(skb);
6920 goto drop_it_no_recycle;
6923 if (desc->type_flags & RXD_FLAG_VLAN &&
6924 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6925 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6926 desc->err_vlan & RXD_VLAN_MASK);
6928 napi_gro_receive(&tnapi->napi, skb);
6936 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6937 tpr->rx_std_prod_idx = std_prod_idx &
6938 tp->rx_std_ring_mask;
6939 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6940 tpr->rx_std_prod_idx);
6941 work_mask &= ~RXD_OPAQUE_RING_STD;
6946 sw_idx &= tp->rx_ret_ring_mask;
6948 /* Refresh hw_idx to see if there is new work */
6949 if (sw_idx == hw_idx) {
6950 hw_idx = *(tnapi->rx_rcb_prod_idx);
6955 /* ACK the status ring. */
6956 tnapi->rx_rcb_ptr = sw_idx;
6957 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6959 /* Refill RX ring(s). */
6960 if (!tg3_flag(tp, ENABLE_RSS)) {
6961 /* Sync BD data before updating mailbox */
6964 if (work_mask & RXD_OPAQUE_RING_STD) {
6965 tpr->rx_std_prod_idx = std_prod_idx &
6966 tp->rx_std_ring_mask;
6967 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6968 tpr->rx_std_prod_idx);
6970 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6971 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6972 tp->rx_jmb_ring_mask;
6973 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6974 tpr->rx_jmb_prod_idx);
6977 } else if (work_mask) {
6978 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6979 * updated before the producer indices can be updated.
6983 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6984 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6986 if (tnapi != &tp->napi[1]) {
6987 tp->rx_refill = true;
6988 napi_schedule(&tp->napi[1].napi);
6995 static void tg3_poll_link(struct tg3 *tp)
6997 /* handle link change and other phy events */
6998 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6999 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7001 if (sblk->status & SD_STATUS_LINK_CHG) {
7002 sblk->status = SD_STATUS_UPDATED |
7003 (sblk->status & ~SD_STATUS_LINK_CHG);
7004 spin_lock(&tp->lock);
7005 if (tg3_flag(tp, USE_PHYLIB)) {
7007 (MAC_STATUS_SYNC_CHANGED |
7008 MAC_STATUS_CFG_CHANGED |
7009 MAC_STATUS_MI_COMPLETION |
7010 MAC_STATUS_LNKSTATE_CHANGED));
7013 tg3_setup_phy(tp, false);
7014 spin_unlock(&tp->lock);
7019 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7020 struct tg3_rx_prodring_set *dpr,
7021 struct tg3_rx_prodring_set *spr)
7023 u32 si, di, cpycnt, src_prod_idx;
7027 src_prod_idx = spr->rx_std_prod_idx;
7029 /* Make sure updates to the rx_std_buffers[] entries and the
7030 * standard producer index are seen in the correct order.
7034 if (spr->rx_std_cons_idx == src_prod_idx)
7037 if (spr->rx_std_cons_idx < src_prod_idx)
7038 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7040 cpycnt = tp->rx_std_ring_mask + 1 -
7041 spr->rx_std_cons_idx;
7043 cpycnt = min(cpycnt,
7044 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7046 si = spr->rx_std_cons_idx;
7047 di = dpr->rx_std_prod_idx;
7049 for (i = di; i < di + cpycnt; i++) {
7050 if (dpr->rx_std_buffers[i].data) {
7060 /* Ensure that updates to the rx_std_buffers ring and the
7061 * shadowed hardware producer ring from tg3_recycle_skb() are
7062 * ordered correctly WRT the skb check above.
7066 memcpy(&dpr->rx_std_buffers[di],
7067 &spr->rx_std_buffers[si],
7068 cpycnt * sizeof(struct ring_info));
7070 for (i = 0; i < cpycnt; i++, di++, si++) {
7071 struct tg3_rx_buffer_desc *sbd, *dbd;
7072 sbd = &spr->rx_std[si];
7073 dbd = &dpr->rx_std[di];
7074 dbd->addr_hi = sbd->addr_hi;
7075 dbd->addr_lo = sbd->addr_lo;
7078 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7079 tp->rx_std_ring_mask;
7080 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7081 tp->rx_std_ring_mask;
7085 src_prod_idx = spr->rx_jmb_prod_idx;
7087 /* Make sure updates to the rx_jmb_buffers[] entries and
7088 * the jumbo producer index are seen in the correct order.
7092 if (spr->rx_jmb_cons_idx == src_prod_idx)
7095 if (spr->rx_jmb_cons_idx < src_prod_idx)
7096 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7098 cpycnt = tp->rx_jmb_ring_mask + 1 -
7099 spr->rx_jmb_cons_idx;
7101 cpycnt = min(cpycnt,
7102 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7104 si = spr->rx_jmb_cons_idx;
7105 di = dpr->rx_jmb_prod_idx;
7107 for (i = di; i < di + cpycnt; i++) {
7108 if (dpr->rx_jmb_buffers[i].data) {
7118 /* Ensure that updates to the rx_jmb_buffers ring and the
7119 * shadowed hardware producer ring from tg3_recycle_skb() are
7120 * ordered correctly WRT the skb check above.
7124 memcpy(&dpr->rx_jmb_buffers[di],
7125 &spr->rx_jmb_buffers[si],
7126 cpycnt * sizeof(struct ring_info));
7128 for (i = 0; i < cpycnt; i++, di++, si++) {
7129 struct tg3_rx_buffer_desc *sbd, *dbd;
7130 sbd = &spr->rx_jmb[si].std;
7131 dbd = &dpr->rx_jmb[di].std;
7132 dbd->addr_hi = sbd->addr_hi;
7133 dbd->addr_lo = sbd->addr_lo;
7136 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7137 tp->rx_jmb_ring_mask;
7138 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7139 tp->rx_jmb_ring_mask;
7145 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7147 struct tg3 *tp = tnapi->tp;
7149 /* run TX completion thread */
7150 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7152 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7156 if (!tnapi->rx_rcb_prod_idx)
7159 /* run RX thread, within the bounds set by NAPI.
7160 * All RX "locking" is done by ensuring outside
7161 * code synchronizes with tg3->napi.poll()
7163 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7164 work_done += tg3_rx(tnapi, budget - work_done);
7166 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7167 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7169 u32 std_prod_idx = dpr->rx_std_prod_idx;
7170 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7172 tp->rx_refill = false;
7173 for (i = 1; i <= tp->rxq_cnt; i++)
7174 err |= tg3_rx_prodring_xfer(tp, dpr,
7175 &tp->napi[i].prodring);
7179 if (std_prod_idx != dpr->rx_std_prod_idx)
7180 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7181 dpr->rx_std_prod_idx);
7183 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7184 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7185 dpr->rx_jmb_prod_idx);
7190 tw32_f(HOSTCC_MODE, tp->coal_now);
7196 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7198 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7199 schedule_work(&tp->reset_task);
7202 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7204 cancel_work_sync(&tp->reset_task);
7205 tg3_flag_clear(tp, RESET_TASK_PENDING);
7206 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7209 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7211 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7212 struct tg3 *tp = tnapi->tp;
7214 struct tg3_hw_status *sblk = tnapi->hw_status;
7217 work_done = tg3_poll_work(tnapi, work_done, budget);
7219 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7222 if (unlikely(work_done >= budget))
7225 /* tp->last_tag is used in tg3_int_reenable() below
7226 * to tell the hw how much work has been processed,
7227 * so we must read it before checking for more work.
7229 tnapi->last_tag = sblk->status_tag;
7230 tnapi->last_irq_tag = tnapi->last_tag;
7233 /* check for RX/TX work to do */
7234 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7235 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7237 /* This test here is not race free, but will reduce
7238 * the number of interrupts by looping again.
7240 if (tnapi == &tp->napi[1] && tp->rx_refill)
7243 napi_complete_done(napi, work_done);
7244 /* Reenable interrupts. */
7245 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7247 /* This test here is synchronized by napi_schedule()
7248 * and napi_complete() to close the race condition.
7250 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7251 tw32(HOSTCC_MODE, tp->coalesce_mode |
7252 HOSTCC_MODE_ENABLE |
7263 /* work_done is guaranteed to be less than budget. */
7264 napi_complete(napi);
7265 tg3_reset_task_schedule(tp);
7269 static void tg3_process_error(struct tg3 *tp)
7272 bool real_error = false;
7274 if (tg3_flag(tp, ERROR_PROCESSED))
7277 /* Check Flow Attention register */
7278 val = tr32(HOSTCC_FLOW_ATTN);
7279 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7280 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7284 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7285 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7289 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7290 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7299 tg3_flag_set(tp, ERROR_PROCESSED);
7300 tg3_reset_task_schedule(tp);
7303 static int tg3_poll(struct napi_struct *napi, int budget)
7305 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7306 struct tg3 *tp = tnapi->tp;
7308 struct tg3_hw_status *sblk = tnapi->hw_status;
7311 if (sblk->status & SD_STATUS_ERROR)
7312 tg3_process_error(tp);
7316 work_done = tg3_poll_work(tnapi, work_done, budget);
7318 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7321 if (unlikely(work_done >= budget))
7324 if (tg3_flag(tp, TAGGED_STATUS)) {
7325 /* tp->last_tag is used in tg3_int_reenable() below
7326 * to tell the hw how much work has been processed,
7327 * so we must read it before checking for more work.
7329 tnapi->last_tag = sblk->status_tag;
7330 tnapi->last_irq_tag = tnapi->last_tag;
7333 sblk->status &= ~SD_STATUS_UPDATED;
7335 if (likely(!tg3_has_work(tnapi))) {
7336 napi_complete_done(napi, work_done);
7337 tg3_int_reenable(tnapi);
7345 /* work_done is guaranteed to be less than budget. */
7346 napi_complete(napi);
7347 tg3_reset_task_schedule(tp);
7351 static void tg3_napi_disable(struct tg3 *tp)
7355 for (i = tp->irq_cnt - 1; i >= 0; i--)
7356 napi_disable(&tp->napi[i].napi);
7359 static void tg3_napi_enable(struct tg3 *tp)
7363 for (i = 0; i < tp->irq_cnt; i++)
7364 napi_enable(&tp->napi[i].napi);
7367 static void tg3_napi_init(struct tg3 *tp)
7371 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7372 for (i = 1; i < tp->irq_cnt; i++)
7373 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7376 static void tg3_napi_fini(struct tg3 *tp)
7380 for (i = 0; i < tp->irq_cnt; i++)
7381 netif_napi_del(&tp->napi[i].napi);
7384 static inline void tg3_netif_stop(struct tg3 *tp)
7386 netif_trans_update(tp->dev); /* prevent tx timeout */
7387 tg3_napi_disable(tp);
7388 netif_carrier_off(tp->dev);
7389 netif_tx_disable(tp->dev);
7392 /* tp->lock must be held */
7393 static inline void tg3_netif_start(struct tg3 *tp)
7397 /* NOTE: unconditional netif_tx_wake_all_queues is only
7398 * appropriate so long as all callers are assured to
7399 * have free tx slots (such as after tg3_init_hw)
7401 netif_tx_wake_all_queues(tp->dev);
7404 netif_carrier_on(tp->dev);
7406 tg3_napi_enable(tp);
7407 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7408 tg3_enable_ints(tp);
7411 static void tg3_irq_quiesce(struct tg3 *tp)
7412 __releases(tp->lock)
7413 __acquires(tp->lock)
7417 BUG_ON(tp->irq_sync);
7422 spin_unlock_bh(&tp->lock);
7424 for (i = 0; i < tp->irq_cnt; i++)
7425 synchronize_irq(tp->napi[i].irq_vec);
7427 spin_lock_bh(&tp->lock);
7430 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7431 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7432 * with as well. Most of the time, this is not necessary except when
7433 * shutting down the device.
7435 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7437 spin_lock_bh(&tp->lock);
7439 tg3_irq_quiesce(tp);
7442 static inline void tg3_full_unlock(struct tg3 *tp)
7444 spin_unlock_bh(&tp->lock);
7447 /* One-shot MSI handler - Chip automatically disables interrupt
7448 * after sending MSI so driver doesn't have to do it.
7450 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7452 struct tg3_napi *tnapi = dev_id;
7453 struct tg3 *tp = tnapi->tp;
7455 prefetch(tnapi->hw_status);
7457 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7459 if (likely(!tg3_irq_sync(tp)))
7460 napi_schedule(&tnapi->napi);
7465 /* MSI ISR - No need to check for interrupt sharing and no need to
7466 * flush status block and interrupt mailbox. PCI ordering rules
7467 * guarantee that MSI will arrive after the status block.
7469 static irqreturn_t tg3_msi(int irq, void *dev_id)
7471 struct tg3_napi *tnapi = dev_id;
7472 struct tg3 *tp = tnapi->tp;
7474 prefetch(tnapi->hw_status);
7476 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7478 * Writing any value to intr-mbox-0 clears PCI INTA# and
7479 * chip-internal interrupt pending events.
7480 * Writing non-zero to intr-mbox-0 additional tells the
7481 * NIC to stop sending us irqs, engaging "in-intr-handler"
7484 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7485 if (likely(!tg3_irq_sync(tp)))
7486 napi_schedule(&tnapi->napi);
7488 return IRQ_RETVAL(1);
7491 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7493 struct tg3_napi *tnapi = dev_id;
7494 struct tg3 *tp = tnapi->tp;
7495 struct tg3_hw_status *sblk = tnapi->hw_status;
7496 unsigned int handled = 1;
7498 /* In INTx mode, it is possible for the interrupt to arrive at
7499 * the CPU before the status block posted prior to the interrupt.
7500 * Reading the PCI State register will confirm whether the
7501 * interrupt is ours and will flush the status block.
7503 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7504 if (tg3_flag(tp, CHIP_RESETTING) ||
7505 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7512 * Writing any value to intr-mbox-0 clears PCI INTA# and
7513 * chip-internal interrupt pending events.
7514 * Writing non-zero to intr-mbox-0 additional tells the
7515 * NIC to stop sending us irqs, engaging "in-intr-handler"
7518 * Flush the mailbox to de-assert the IRQ immediately to prevent
7519 * spurious interrupts. The flush impacts performance but
7520 * excessive spurious interrupts can be worse in some cases.
7522 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7523 if (tg3_irq_sync(tp))
7525 sblk->status &= ~SD_STATUS_UPDATED;
7526 if (likely(tg3_has_work(tnapi))) {
7527 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7528 napi_schedule(&tnapi->napi);
7530 /* No work, shared interrupt perhaps? re-enable
7531 * interrupts, and flush that PCI write
7533 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7537 return IRQ_RETVAL(handled);
7540 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7542 struct tg3_napi *tnapi = dev_id;
7543 struct tg3 *tp = tnapi->tp;
7544 struct tg3_hw_status *sblk = tnapi->hw_status;
7545 unsigned int handled = 1;
7547 /* In INTx mode, it is possible for the interrupt to arrive at
7548 * the CPU before the status block posted prior to the interrupt.
7549 * Reading the PCI State register will confirm whether the
7550 * interrupt is ours and will flush the status block.
7552 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7553 if (tg3_flag(tp, CHIP_RESETTING) ||
7554 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7561 * writing any value to intr-mbox-0 clears PCI INTA# and
7562 * chip-internal interrupt pending events.
7563 * writing non-zero to intr-mbox-0 additional tells the
7564 * NIC to stop sending us irqs, engaging "in-intr-handler"
7567 * Flush the mailbox to de-assert the IRQ immediately to prevent
7568 * spurious interrupts. The flush impacts performance but
7569 * excessive spurious interrupts can be worse in some cases.
7571 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7574 * In a shared interrupt configuration, sometimes other devices'
7575 * interrupts will scream. We record the current status tag here
7576 * so that the above check can report that the screaming interrupts
7577 * are unhandled. Eventually they will be silenced.
7579 tnapi->last_irq_tag = sblk->status_tag;
7581 if (tg3_irq_sync(tp))
7584 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7586 napi_schedule(&tnapi->napi);
7589 return IRQ_RETVAL(handled);
7592 /* ISR for interrupt test */
7593 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7595 struct tg3_napi *tnapi = dev_id;
7596 struct tg3 *tp = tnapi->tp;
7597 struct tg3_hw_status *sblk = tnapi->hw_status;
7599 if ((sblk->status & SD_STATUS_UPDATED) ||
7600 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7601 tg3_disable_ints(tp);
7602 return IRQ_RETVAL(1);
7604 return IRQ_RETVAL(0);
7607 #ifdef CONFIG_NET_POLL_CONTROLLER
7608 static void tg3_poll_controller(struct net_device *dev)
7611 struct tg3 *tp = netdev_priv(dev);
7613 if (tg3_irq_sync(tp))
7616 for (i = 0; i < tp->irq_cnt; i++)
7617 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7621 static void tg3_tx_timeout(struct net_device *dev)
7623 struct tg3 *tp = netdev_priv(dev);
7625 if (netif_msg_tx_err(tp)) {
7626 netdev_err(dev, "transmit timed out, resetting\n");
7630 tg3_reset_task_schedule(tp);
7633 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7634 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7636 u32 base = (u32) mapping & 0xffffffff;
7638 return base + len + 8 < base;
7641 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7642 * of any 4GB boundaries: 4G, 8G, etc
7644 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7647 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7648 u32 base = (u32) mapping & 0xffffffff;
7650 return ((base + len + (mss & 0x3fff)) < base);
7655 /* Test for DMA addresses > 40-bit */
7656 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7659 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7660 if (tg3_flag(tp, 40BIT_DMA_BUG))
7661 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7668 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7669 dma_addr_t mapping, u32 len, u32 flags,
7672 txbd->addr_hi = ((u64) mapping >> 32);
7673 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7674 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7675 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7678 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7679 dma_addr_t map, u32 len, u32 flags,
7682 struct tg3 *tp = tnapi->tp;
7685 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7688 if (tg3_4g_overflow_test(map, len))
7691 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7694 if (tg3_40bit_overflow_test(tp, map, len))
7697 if (tp->dma_limit) {
7698 u32 prvidx = *entry;
7699 u32 tmp_flag = flags & ~TXD_FLAG_END;
7700 while (len > tp->dma_limit && *budget) {
7701 u32 frag_len = tp->dma_limit;
7702 len -= tp->dma_limit;
7704 /* Avoid the 8byte DMA problem */
7706 len += tp->dma_limit / 2;
7707 frag_len = tp->dma_limit / 2;
7710 tnapi->tx_buffers[*entry].fragmented = true;
7712 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7713 frag_len, tmp_flag, mss, vlan);
7716 *entry = NEXT_TX(*entry);
7723 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7724 len, flags, mss, vlan);
7726 *entry = NEXT_TX(*entry);
7729 tnapi->tx_buffers[prvidx].fragmented = false;
7733 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7734 len, flags, mss, vlan);
7735 *entry = NEXT_TX(*entry);
7741 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7744 struct sk_buff *skb;
7745 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7750 pci_unmap_single(tnapi->tp->pdev,
7751 dma_unmap_addr(txb, mapping),
7755 while (txb->fragmented) {
7756 txb->fragmented = false;
7757 entry = NEXT_TX(entry);
7758 txb = &tnapi->tx_buffers[entry];
7761 for (i = 0; i <= last; i++) {
7762 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7764 entry = NEXT_TX(entry);
7765 txb = &tnapi->tx_buffers[entry];
7767 pci_unmap_page(tnapi->tp->pdev,
7768 dma_unmap_addr(txb, mapping),
7769 skb_frag_size(frag), PCI_DMA_TODEVICE);
7771 while (txb->fragmented) {
7772 txb->fragmented = false;
7773 entry = NEXT_TX(entry);
7774 txb = &tnapi->tx_buffers[entry];
7779 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7780 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7781 struct sk_buff **pskb,
7782 u32 *entry, u32 *budget,
7783 u32 base_flags, u32 mss, u32 vlan)
7785 struct tg3 *tp = tnapi->tp;
7786 struct sk_buff *new_skb, *skb = *pskb;
7787 dma_addr_t new_addr = 0;
7790 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7791 new_skb = skb_copy(skb, GFP_ATOMIC);
7793 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7795 new_skb = skb_copy_expand(skb,
7796 skb_headroom(skb) + more_headroom,
7797 skb_tailroom(skb), GFP_ATOMIC);
7803 /* New SKB is guaranteed to be linear. */
7804 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7806 /* Make sure the mapping succeeded */
7807 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7808 dev_kfree_skb_any(new_skb);
7811 u32 save_entry = *entry;
7813 base_flags |= TXD_FLAG_END;
7815 tnapi->tx_buffers[*entry].skb = new_skb;
7816 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7819 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7820 new_skb->len, base_flags,
7822 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7823 dev_kfree_skb_any(new_skb);
7829 dev_kfree_skb_any(skb);
7834 static bool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb)
7836 /* Check if we will never have enough descriptors,
7837 * as gso_segs can be more than current ring size
7839 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3;
7842 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7844 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7845 * indicated in tg3_tx_frag_set()
7847 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7848 struct netdev_queue *txq, struct sk_buff *skb)
7850 struct sk_buff *segs, *nskb;
7851 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7853 /* Estimate the number of fragments in the worst case */
7854 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7855 netif_tx_stop_queue(txq);
7857 /* netif_tx_stop_queue() must be done before checking
7858 * checking tx index in tg3_tx_avail() below, because in
7859 * tg3_tx(), we update tx index before checking for
7860 * netif_tx_queue_stopped().
7863 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7864 return NETDEV_TX_BUSY;
7866 netif_tx_wake_queue(txq);
7869 segs = skb_gso_segment(skb, tp->dev->features &
7870 ~(NETIF_F_TSO | NETIF_F_TSO6));
7871 if (IS_ERR(segs) || !segs)
7872 goto tg3_tso_bug_end;
7878 tg3_start_xmit(nskb, tp->dev);
7882 dev_kfree_skb_any(skb);
7884 return NETDEV_TX_OK;
7887 /* hard_start_xmit for all devices */
7888 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7890 struct tg3 *tp = netdev_priv(dev);
7891 u32 len, entry, base_flags, mss, vlan = 0;
7893 int i = -1, would_hit_hwbug;
7895 struct tg3_napi *tnapi;
7896 struct netdev_queue *txq;
7898 struct iphdr *iph = NULL;
7899 struct tcphdr *tcph = NULL;
7900 __sum16 tcp_csum = 0, ip_csum = 0;
7901 __be16 ip_tot_len = 0;
7903 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7904 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7905 if (tg3_flag(tp, ENABLE_TSS))
7908 budget = tg3_tx_avail(tnapi);
7910 /* We are running in BH disabled context with netif_tx_lock
7911 * and TX reclaim runs via tp->napi.poll inside of a software
7912 * interrupt. Furthermore, IRQ processing runs lockless so we have
7913 * no IRQ context deadlocks to worry about either. Rejoice!
7915 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7916 if (!netif_tx_queue_stopped(txq)) {
7917 netif_tx_stop_queue(txq);
7919 /* This is a hard error, log it. */
7921 "BUG! Tx Ring full when queue awake!\n");
7923 return NETDEV_TX_BUSY;
7926 entry = tnapi->tx_prod;
7929 mss = skb_shinfo(skb)->gso_size;
7931 u32 tcp_opt_len, hdr_len;
7933 if (skb_cow_head(skb, 0))
7937 tcp_opt_len = tcp_optlen(skb);
7939 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7941 /* HW/FW can not correctly segment packets that have been
7942 * vlan encapsulated.
7944 if (skb->protocol == htons(ETH_P_8021Q) ||
7945 skb->protocol == htons(ETH_P_8021AD)) {
7946 if (tg3_tso_bug_gso_check(tnapi, skb))
7947 return tg3_tso_bug(tp, tnapi, txq, skb);
7951 if (!skb_is_gso_v6(skb)) {
7952 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7953 tg3_flag(tp, TSO_BUG)) {
7954 if (tg3_tso_bug_gso_check(tnapi, skb))
7955 return tg3_tso_bug(tp, tnapi, txq, skb);
7958 ip_csum = iph->check;
7959 ip_tot_len = iph->tot_len;
7961 iph->tot_len = htons(mss + hdr_len);
7964 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7965 TXD_FLAG_CPU_POST_DMA);
7967 tcph = tcp_hdr(skb);
7968 tcp_csum = tcph->check;
7970 if (tg3_flag(tp, HW_TSO_1) ||
7971 tg3_flag(tp, HW_TSO_2) ||
7972 tg3_flag(tp, HW_TSO_3)) {
7974 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7976 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7980 if (tg3_flag(tp, HW_TSO_3)) {
7981 mss |= (hdr_len & 0xc) << 12;
7983 base_flags |= 0x00000010;
7984 base_flags |= (hdr_len & 0x3e0) << 5;
7985 } else if (tg3_flag(tp, HW_TSO_2))
7986 mss |= hdr_len << 9;
7987 else if (tg3_flag(tp, HW_TSO_1) ||
7988 tg3_asic_rev(tp) == ASIC_REV_5705) {
7989 if (tcp_opt_len || iph->ihl > 5) {
7992 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7993 mss |= (tsflags << 11);
7996 if (tcp_opt_len || iph->ihl > 5) {
7999 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8000 base_flags |= tsflags << 12;
8003 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
8004 /* HW/FW can not correctly checksum packets that have been
8005 * vlan encapsulated.
8007 if (skb->protocol == htons(ETH_P_8021Q) ||
8008 skb->protocol == htons(ETH_P_8021AD)) {
8009 if (skb_checksum_help(skb))
8012 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8016 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8017 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8018 base_flags |= TXD_FLAG_JMB_PKT;
8020 if (skb_vlan_tag_present(skb)) {
8021 base_flags |= TXD_FLAG_VLAN;
8022 vlan = skb_vlan_tag_get(skb);
8025 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8026 tg3_flag(tp, TX_TSTAMP_EN)) {
8027 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8028 base_flags |= TXD_FLAG_HWTSTAMP;
8031 len = skb_headlen(skb);
8033 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8034 if (pci_dma_mapping_error(tp->pdev, mapping))
8038 tnapi->tx_buffers[entry].skb = skb;
8039 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8041 would_hit_hwbug = 0;
8043 if (tg3_flag(tp, 5701_DMA_BUG))
8044 would_hit_hwbug = 1;
8046 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8047 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8049 would_hit_hwbug = 1;
8050 } else if (skb_shinfo(skb)->nr_frags > 0) {
8053 if (!tg3_flag(tp, HW_TSO_1) &&
8054 !tg3_flag(tp, HW_TSO_2) &&
8055 !tg3_flag(tp, HW_TSO_3))
8058 /* Now loop through additional data
8059 * fragments, and queue them.
8061 last = skb_shinfo(skb)->nr_frags - 1;
8062 for (i = 0; i <= last; i++) {
8063 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8065 len = skb_frag_size(frag);
8066 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8067 len, DMA_TO_DEVICE);
8069 tnapi->tx_buffers[entry].skb = NULL;
8070 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8072 if (dma_mapping_error(&tp->pdev->dev, mapping))
8076 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8078 ((i == last) ? TXD_FLAG_END : 0),
8080 would_hit_hwbug = 1;
8086 if (would_hit_hwbug) {
8087 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8089 if (mss && tg3_tso_bug_gso_check(tnapi, skb)) {
8090 /* If it's a TSO packet, do GSO instead of
8091 * allocating and copying to a large linear SKB
8094 iph->check = ip_csum;
8095 iph->tot_len = ip_tot_len;
8097 tcph->check = tcp_csum;
8098 return tg3_tso_bug(tp, tnapi, txq, skb);
8101 /* If the workaround fails due to memory/mapping
8102 * failure, silently drop this packet.
8104 entry = tnapi->tx_prod;
8105 budget = tg3_tx_avail(tnapi);
8106 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8107 base_flags, mss, vlan))
8111 skb_tx_timestamp(skb);
8112 netdev_tx_sent_queue(txq, skb->len);
8114 /* Sync BD data before updating mailbox */
8117 tnapi->tx_prod = entry;
8118 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8119 netif_tx_stop_queue(txq);
8121 /* netif_tx_stop_queue() must be done before checking
8122 * checking tx index in tg3_tx_avail() below, because in
8123 * tg3_tx(), we update tx index before checking for
8124 * netif_tx_queue_stopped().
8127 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8128 netif_tx_wake_queue(txq);
8131 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8132 /* Packets are ready, update Tx producer idx on card. */
8133 tw32_tx_mbox(tnapi->prodmbox, entry);
8137 return NETDEV_TX_OK;
8140 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8141 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8143 dev_kfree_skb_any(skb);
8146 return NETDEV_TX_OK;
8149 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8152 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8153 MAC_MODE_PORT_MODE_MASK);
8155 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8157 if (!tg3_flag(tp, 5705_PLUS))
8158 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8160 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8161 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8163 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8165 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8167 if (tg3_flag(tp, 5705_PLUS) ||
8168 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8169 tg3_asic_rev(tp) == ASIC_REV_5700)
8170 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8173 tw32(MAC_MODE, tp->mac_mode);
8177 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8179 u32 val, bmcr, mac_mode, ptest = 0;
8181 tg3_phy_toggle_apd(tp, false);
8182 tg3_phy_toggle_automdix(tp, false);
8184 if (extlpbk && tg3_phy_set_extloopbk(tp))
8187 bmcr = BMCR_FULLDPLX;
8192 bmcr |= BMCR_SPEED100;
8196 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8198 bmcr |= BMCR_SPEED100;
8201 bmcr |= BMCR_SPEED1000;
8206 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8207 tg3_readphy(tp, MII_CTRL1000, &val);
8208 val |= CTL1000_AS_MASTER |
8209 CTL1000_ENABLE_MASTER;
8210 tg3_writephy(tp, MII_CTRL1000, val);
8212 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8213 MII_TG3_FET_PTEST_TRIM_2;
8214 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8217 bmcr |= BMCR_LOOPBACK;
8219 tg3_writephy(tp, MII_BMCR, bmcr);
8221 /* The write needs to be flushed for the FETs */
8222 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8223 tg3_readphy(tp, MII_BMCR, &bmcr);
8227 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8228 tg3_asic_rev(tp) == ASIC_REV_5785) {
8229 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8230 MII_TG3_FET_PTEST_FRC_TX_LINK |
8231 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8233 /* The write needs to be flushed for the AC131 */
8234 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8237 /* Reset to prevent losing 1st rx packet intermittently */
8238 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8239 tg3_flag(tp, 5780_CLASS)) {
8240 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8242 tw32_f(MAC_RX_MODE, tp->rx_mode);
8245 mac_mode = tp->mac_mode &
8246 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8247 if (speed == SPEED_1000)
8248 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8250 mac_mode |= MAC_MODE_PORT_MODE_MII;
8252 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8253 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8255 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8256 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8257 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8258 mac_mode |= MAC_MODE_LINK_POLARITY;
8260 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8261 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8264 tw32(MAC_MODE, mac_mode);
8270 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8272 struct tg3 *tp = netdev_priv(dev);
8274 if (features & NETIF_F_LOOPBACK) {
8275 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8278 spin_lock_bh(&tp->lock);
8279 tg3_mac_loopback(tp, true);
8280 netif_carrier_on(tp->dev);
8281 spin_unlock_bh(&tp->lock);
8282 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8284 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8287 spin_lock_bh(&tp->lock);
8288 tg3_mac_loopback(tp, false);
8289 /* Force link status check */
8290 tg3_setup_phy(tp, true);
8291 spin_unlock_bh(&tp->lock);
8292 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8296 static netdev_features_t tg3_fix_features(struct net_device *dev,
8297 netdev_features_t features)
8299 struct tg3 *tp = netdev_priv(dev);
8301 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8302 features &= ~NETIF_F_ALL_TSO;
8307 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8309 netdev_features_t changed = dev->features ^ features;
8311 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8312 tg3_set_loopback(dev, features);
8317 static void tg3_rx_prodring_free(struct tg3 *tp,
8318 struct tg3_rx_prodring_set *tpr)
8322 if (tpr != &tp->napi[0].prodring) {
8323 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8324 i = (i + 1) & tp->rx_std_ring_mask)
8325 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8328 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8329 for (i = tpr->rx_jmb_cons_idx;
8330 i != tpr->rx_jmb_prod_idx;
8331 i = (i + 1) & tp->rx_jmb_ring_mask) {
8332 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8340 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8341 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8344 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8345 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8346 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8351 /* Initialize rx rings for packet processing.
8353 * The chip has been shut down and the driver detached from
8354 * the networking, so no interrupts or new tx packets will
8355 * end up in the driver. tp->{tx,}lock are held and thus
8358 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8359 struct tg3_rx_prodring_set *tpr)
8361 u32 i, rx_pkt_dma_sz;
8363 tpr->rx_std_cons_idx = 0;
8364 tpr->rx_std_prod_idx = 0;
8365 tpr->rx_jmb_cons_idx = 0;
8366 tpr->rx_jmb_prod_idx = 0;
8368 if (tpr != &tp->napi[0].prodring) {
8369 memset(&tpr->rx_std_buffers[0], 0,
8370 TG3_RX_STD_BUFF_RING_SIZE(tp));
8371 if (tpr->rx_jmb_buffers)
8372 memset(&tpr->rx_jmb_buffers[0], 0,
8373 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8377 /* Zero out all descriptors. */
8378 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8380 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8381 if (tg3_flag(tp, 5780_CLASS) &&
8382 tp->dev->mtu > ETH_DATA_LEN)
8383 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8384 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8386 /* Initialize invariants of the rings, we only set this
8387 * stuff once. This works because the card does not
8388 * write into the rx buffer posting rings.
8390 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8391 struct tg3_rx_buffer_desc *rxd;
8393 rxd = &tpr->rx_std[i];
8394 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8395 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8396 rxd->opaque = (RXD_OPAQUE_RING_STD |
8397 (i << RXD_OPAQUE_INDEX_SHIFT));
8400 /* Now allocate fresh SKBs for each rx ring. */
8401 for (i = 0; i < tp->rx_pending; i++) {
8402 unsigned int frag_size;
8404 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8406 netdev_warn(tp->dev,
8407 "Using a smaller RX standard ring. Only "
8408 "%d out of %d buffers were allocated "
8409 "successfully\n", i, tp->rx_pending);
8417 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8420 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8422 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8425 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8426 struct tg3_rx_buffer_desc *rxd;
8428 rxd = &tpr->rx_jmb[i].std;
8429 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8430 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8432 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8433 (i << RXD_OPAQUE_INDEX_SHIFT));
8436 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8437 unsigned int frag_size;
8439 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8441 netdev_warn(tp->dev,
8442 "Using a smaller RX jumbo ring. Only %d "
8443 "out of %d buffers were allocated "
8444 "successfully\n", i, tp->rx_jumbo_pending);
8447 tp->rx_jumbo_pending = i;
8456 tg3_rx_prodring_free(tp, tpr);
8460 static void tg3_rx_prodring_fini(struct tg3 *tp,
8461 struct tg3_rx_prodring_set *tpr)
8463 kfree(tpr->rx_std_buffers);
8464 tpr->rx_std_buffers = NULL;
8465 kfree(tpr->rx_jmb_buffers);
8466 tpr->rx_jmb_buffers = NULL;
8468 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8469 tpr->rx_std, tpr->rx_std_mapping);
8473 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8474 tpr->rx_jmb, tpr->rx_jmb_mapping);
8479 static int tg3_rx_prodring_init(struct tg3 *tp,
8480 struct tg3_rx_prodring_set *tpr)
8482 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8484 if (!tpr->rx_std_buffers)
8487 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8488 TG3_RX_STD_RING_BYTES(tp),
8489 &tpr->rx_std_mapping,
8494 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8495 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8497 if (!tpr->rx_jmb_buffers)
8500 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8501 TG3_RX_JMB_RING_BYTES(tp),
8502 &tpr->rx_jmb_mapping,
8511 tg3_rx_prodring_fini(tp, tpr);
8515 /* Free up pending packets in all rx/tx rings.
8517 * The chip has been shut down and the driver detached from
8518 * the networking, so no interrupts or new tx packets will
8519 * end up in the driver. tp->{tx,}lock is not held and we are not
8520 * in an interrupt context and thus may sleep.
8522 static void tg3_free_rings(struct tg3 *tp)
8526 for (j = 0; j < tp->irq_cnt; j++) {
8527 struct tg3_napi *tnapi = &tp->napi[j];
8529 tg3_rx_prodring_free(tp, &tnapi->prodring);
8531 if (!tnapi->tx_buffers)
8534 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8535 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8540 tg3_tx_skb_unmap(tnapi, i,
8541 skb_shinfo(skb)->nr_frags - 1);
8543 dev_kfree_skb_any(skb);
8545 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8549 /* Initialize tx/rx rings for packet processing.
8551 * The chip has been shut down and the driver detached from
8552 * the networking, so no interrupts or new tx packets will
8553 * end up in the driver. tp->{tx,}lock are held and thus
8556 static int tg3_init_rings(struct tg3 *tp)
8560 /* Free up all the SKBs. */
8563 for (i = 0; i < tp->irq_cnt; i++) {
8564 struct tg3_napi *tnapi = &tp->napi[i];
8566 tnapi->last_tag = 0;
8567 tnapi->last_irq_tag = 0;
8568 tnapi->hw_status->status = 0;
8569 tnapi->hw_status->status_tag = 0;
8570 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8575 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8577 tnapi->rx_rcb_ptr = 0;
8579 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8581 if (tnapi->prodring.rx_std &&
8582 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8591 static void tg3_mem_tx_release(struct tg3 *tp)
8595 for (i = 0; i < tp->irq_max; i++) {
8596 struct tg3_napi *tnapi = &tp->napi[i];
8598 if (tnapi->tx_ring) {
8599 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8600 tnapi->tx_ring, tnapi->tx_desc_mapping);
8601 tnapi->tx_ring = NULL;
8604 kfree(tnapi->tx_buffers);
8605 tnapi->tx_buffers = NULL;
8609 static int tg3_mem_tx_acquire(struct tg3 *tp)
8612 struct tg3_napi *tnapi = &tp->napi[0];
8614 /* If multivector TSS is enabled, vector 0 does not handle
8615 * tx interrupts. Don't allocate any resources for it.
8617 if (tg3_flag(tp, ENABLE_TSS))
8620 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8621 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8622 TG3_TX_RING_SIZE, GFP_KERNEL);
8623 if (!tnapi->tx_buffers)
8626 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8628 &tnapi->tx_desc_mapping,
8630 if (!tnapi->tx_ring)
8637 tg3_mem_tx_release(tp);
8641 static void tg3_mem_rx_release(struct tg3 *tp)
8645 for (i = 0; i < tp->irq_max; i++) {
8646 struct tg3_napi *tnapi = &tp->napi[i];
8648 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8653 dma_free_coherent(&tp->pdev->dev,
8654 TG3_RX_RCB_RING_BYTES(tp),
8656 tnapi->rx_rcb_mapping);
8657 tnapi->rx_rcb = NULL;
8661 static int tg3_mem_rx_acquire(struct tg3 *tp)
8663 unsigned int i, limit;
8665 limit = tp->rxq_cnt;
8667 /* If RSS is enabled, we need a (dummy) producer ring
8668 * set on vector zero. This is the true hw prodring.
8670 if (tg3_flag(tp, ENABLE_RSS))
8673 for (i = 0; i < limit; i++) {
8674 struct tg3_napi *tnapi = &tp->napi[i];
8676 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8679 /* If multivector RSS is enabled, vector 0
8680 * does not handle rx or tx interrupts.
8681 * Don't allocate any resources for it.
8683 if (!i && tg3_flag(tp, ENABLE_RSS))
8686 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8687 TG3_RX_RCB_RING_BYTES(tp),
8688 &tnapi->rx_rcb_mapping,
8697 tg3_mem_rx_release(tp);
8702 * Must not be invoked with interrupt sources disabled and
8703 * the hardware shutdown down.
8705 static void tg3_free_consistent(struct tg3 *tp)
8709 for (i = 0; i < tp->irq_cnt; i++) {
8710 struct tg3_napi *tnapi = &tp->napi[i];
8712 if (tnapi->hw_status) {
8713 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8715 tnapi->status_mapping);
8716 tnapi->hw_status = NULL;
8720 tg3_mem_rx_release(tp);
8721 tg3_mem_tx_release(tp);
8723 /* Protect tg3_get_stats64() from reading freed tp->hw_stats. */
8724 tg3_full_lock(tp, 0);
8726 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8727 tp->hw_stats, tp->stats_mapping);
8728 tp->hw_stats = NULL;
8730 tg3_full_unlock(tp);
8734 * Must not be invoked with interrupt sources disabled and
8735 * the hardware shutdown down. Can sleep.
8737 static int tg3_alloc_consistent(struct tg3 *tp)
8741 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8742 sizeof(struct tg3_hw_stats),
8743 &tp->stats_mapping, GFP_KERNEL);
8747 for (i = 0; i < tp->irq_cnt; i++) {
8748 struct tg3_napi *tnapi = &tp->napi[i];
8749 struct tg3_hw_status *sblk;
8751 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8753 &tnapi->status_mapping,
8755 if (!tnapi->hw_status)
8758 sblk = tnapi->hw_status;
8760 if (tg3_flag(tp, ENABLE_RSS)) {
8761 u16 *prodptr = NULL;
8764 * When RSS is enabled, the status block format changes
8765 * slightly. The "rx_jumbo_consumer", "reserved",
8766 * and "rx_mini_consumer" members get mapped to the
8767 * other three rx return ring producer indexes.
8771 prodptr = &sblk->idx[0].rx_producer;
8774 prodptr = &sblk->rx_jumbo_consumer;
8777 prodptr = &sblk->reserved;
8780 prodptr = &sblk->rx_mini_consumer;
8783 tnapi->rx_rcb_prod_idx = prodptr;
8785 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8789 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8795 tg3_free_consistent(tp);
8799 #define MAX_WAIT_CNT 1000
8801 /* To stop a block, clear the enable bit and poll till it
8802 * clears. tp->lock is held.
8804 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8809 if (tg3_flag(tp, 5705_PLUS)) {
8816 /* We can't enable/disable these bits of the
8817 * 5705/5750, just say success.
8830 for (i = 0; i < MAX_WAIT_CNT; i++) {
8831 if (pci_channel_offline(tp->pdev)) {
8832 dev_err(&tp->pdev->dev,
8833 "tg3_stop_block device offline, "
8834 "ofs=%lx enable_bit=%x\n",
8841 if ((val & enable_bit) == 0)
8845 if (i == MAX_WAIT_CNT && !silent) {
8846 dev_err(&tp->pdev->dev,
8847 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8855 /* tp->lock is held. */
8856 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8860 tg3_disable_ints(tp);
8862 if (pci_channel_offline(tp->pdev)) {
8863 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8864 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8869 tp->rx_mode &= ~RX_MODE_ENABLE;
8870 tw32_f(MAC_RX_MODE, tp->rx_mode);
8873 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8874 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8875 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8876 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8877 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8878 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8880 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8881 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8882 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8883 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8884 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8885 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8886 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8888 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8889 tw32_f(MAC_MODE, tp->mac_mode);
8892 tp->tx_mode &= ~TX_MODE_ENABLE;
8893 tw32_f(MAC_TX_MODE, tp->tx_mode);
8895 for (i = 0; i < MAX_WAIT_CNT; i++) {
8897 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8900 if (i >= MAX_WAIT_CNT) {
8901 dev_err(&tp->pdev->dev,
8902 "%s timed out, TX_MODE_ENABLE will not clear "
8903 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8907 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8908 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8909 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8911 tw32(FTQ_RESET, 0xffffffff);
8912 tw32(FTQ_RESET, 0x00000000);
8914 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8915 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8918 for (i = 0; i < tp->irq_cnt; i++) {
8919 struct tg3_napi *tnapi = &tp->napi[i];
8920 if (tnapi->hw_status)
8921 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8927 /* Save PCI command register before chip reset */
8928 static void tg3_save_pci_state(struct tg3 *tp)
8930 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8933 /* Restore PCI state after chip reset */
8934 static void tg3_restore_pci_state(struct tg3 *tp)
8938 /* Re-enable indirect register accesses. */
8939 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8940 tp->misc_host_ctrl);
8942 /* Set MAX PCI retry to zero. */
8943 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8944 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8945 tg3_flag(tp, PCIX_MODE))
8946 val |= PCISTATE_RETRY_SAME_DMA;
8947 /* Allow reads and writes to the APE register and memory space. */
8948 if (tg3_flag(tp, ENABLE_APE))
8949 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8950 PCISTATE_ALLOW_APE_SHMEM_WR |
8951 PCISTATE_ALLOW_APE_PSPACE_WR;
8952 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8954 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8956 if (!tg3_flag(tp, PCI_EXPRESS)) {
8957 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8958 tp->pci_cacheline_sz);
8959 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8963 /* Make sure PCI-X relaxed ordering bit is clear. */
8964 if (tg3_flag(tp, PCIX_MODE)) {
8967 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8969 pcix_cmd &= ~PCI_X_CMD_ERO;
8970 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8974 if (tg3_flag(tp, 5780_CLASS)) {
8976 /* Chip reset on 5780 will reset MSI enable bit,
8977 * so need to restore it.
8979 if (tg3_flag(tp, USING_MSI)) {
8982 pci_read_config_word(tp->pdev,
8983 tp->msi_cap + PCI_MSI_FLAGS,
8985 pci_write_config_word(tp->pdev,
8986 tp->msi_cap + PCI_MSI_FLAGS,
8987 ctrl | PCI_MSI_FLAGS_ENABLE);
8988 val = tr32(MSGINT_MODE);
8989 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8994 static void tg3_override_clk(struct tg3 *tp)
8998 switch (tg3_asic_rev(tp)) {
9000 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9001 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9002 TG3_CPMU_MAC_ORIDE_ENABLE);
9007 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9015 static void tg3_restore_clk(struct tg3 *tp)
9019 switch (tg3_asic_rev(tp)) {
9021 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9022 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9023 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9028 val = tr32(TG3_CPMU_CLCK_ORIDE);
9029 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9037 /* tp->lock is held. */
9038 static int tg3_chip_reset(struct tg3 *tp)
9039 __releases(tp->lock)
9040 __acquires(tp->lock)
9043 void (*write_op)(struct tg3 *, u32, u32);
9046 if (!pci_device_is_present(tp->pdev))
9051 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9053 /* No matching tg3_nvram_unlock() after this because
9054 * chip reset below will undo the nvram lock.
9056 tp->nvram_lock_cnt = 0;
9058 /* GRC_MISC_CFG core clock reset will clear the memory
9059 * enable bit in PCI register 4 and the MSI enable bit
9060 * on some chips, so we save relevant registers here.
9062 tg3_save_pci_state(tp);
9064 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9065 tg3_flag(tp, 5755_PLUS))
9066 tw32(GRC_FASTBOOT_PC, 0);
9069 * We must avoid the readl() that normally takes place.
9070 * It locks machines, causes machine checks, and other
9071 * fun things. So, temporarily disable the 5701
9072 * hardware workaround, while we do the reset.
9074 write_op = tp->write32;
9075 if (write_op == tg3_write_flush_reg32)
9076 tp->write32 = tg3_write32;
9078 /* Prevent the irq handler from reading or writing PCI registers
9079 * during chip reset when the memory enable bit in the PCI command
9080 * register may be cleared. The chip does not generate interrupt
9081 * at this time, but the irq handler may still be called due to irq
9082 * sharing or irqpoll.
9084 tg3_flag_set(tp, CHIP_RESETTING);
9085 for (i = 0; i < tp->irq_cnt; i++) {
9086 struct tg3_napi *tnapi = &tp->napi[i];
9087 if (tnapi->hw_status) {
9088 tnapi->hw_status->status = 0;
9089 tnapi->hw_status->status_tag = 0;
9091 tnapi->last_tag = 0;
9092 tnapi->last_irq_tag = 0;
9096 tg3_full_unlock(tp);
9098 for (i = 0; i < tp->irq_cnt; i++)
9099 synchronize_irq(tp->napi[i].irq_vec);
9101 tg3_full_lock(tp, 0);
9103 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9104 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9105 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9109 val = GRC_MISC_CFG_CORECLK_RESET;
9111 if (tg3_flag(tp, PCI_EXPRESS)) {
9112 /* Force PCIe 1.0a mode */
9113 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9114 !tg3_flag(tp, 57765_PLUS) &&
9115 tr32(TG3_PCIE_PHY_TSTCTL) ==
9116 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9117 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9119 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9120 tw32(GRC_MISC_CFG, (1 << 29));
9125 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9126 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9127 tw32(GRC_VCPU_EXT_CTRL,
9128 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9131 /* Set the clock to the highest frequency to avoid timeouts. With link
9132 * aware mode, the clock speed could be slow and bootcode does not
9133 * complete within the expected time. Override the clock to allow the
9134 * bootcode to finish sooner and then restore it.
9136 tg3_override_clk(tp);
9138 /* Manage gphy power for all CPMU absent PCIe devices. */
9139 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9140 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9142 tw32(GRC_MISC_CFG, val);
9144 /* restore 5701 hardware bug workaround write method */
9145 tp->write32 = write_op;
9147 /* Unfortunately, we have to delay before the PCI read back.
9148 * Some 575X chips even will not respond to a PCI cfg access
9149 * when the reset command is given to the chip.
9151 * How do these hardware designers expect things to work
9152 * properly if the PCI write is posted for a long period
9153 * of time? It is always necessary to have some method by
9154 * which a register read back can occur to push the write
9155 * out which does the reset.
9157 * For most tg3 variants the trick below was working.
9162 /* Flush PCI posted writes. The normal MMIO registers
9163 * are inaccessible at this time so this is the only
9164 * way to make this reliably (actually, this is no longer
9165 * the case, see above). I tried to use indirect
9166 * register read/write but this upset some 5701 variants.
9168 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9172 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9175 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9179 /* Wait for link training to complete. */
9180 for (j = 0; j < 5000; j++)
9183 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9184 pci_write_config_dword(tp->pdev, 0xc4,
9185 cfg_val | (1 << 15));
9188 /* Clear the "no snoop" and "relaxed ordering" bits. */
9189 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9191 * Older PCIe devices only support the 128 byte
9192 * MPS setting. Enforce the restriction.
9194 if (!tg3_flag(tp, CPMU_PRESENT))
9195 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9196 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9198 /* Clear error status */
9199 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9200 PCI_EXP_DEVSTA_CED |
9201 PCI_EXP_DEVSTA_NFED |
9202 PCI_EXP_DEVSTA_FED |
9203 PCI_EXP_DEVSTA_URD);
9206 tg3_restore_pci_state(tp);
9208 tg3_flag_clear(tp, CHIP_RESETTING);
9209 tg3_flag_clear(tp, ERROR_PROCESSED);
9212 if (tg3_flag(tp, 5780_CLASS))
9213 val = tr32(MEMARB_MODE);
9214 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9216 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9218 tw32(0x5000, 0x400);
9221 if (tg3_flag(tp, IS_SSB_CORE)) {
9223 * BCM4785: In order to avoid repercussions from using
9224 * potentially defective internal ROM, stop the Rx RISC CPU,
9225 * which is not required.
9228 tg3_halt_cpu(tp, RX_CPU_BASE);
9231 err = tg3_poll_fw(tp);
9235 tw32(GRC_MODE, tp->grc_mode);
9237 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9240 tw32(0xc4, val | (1 << 15));
9243 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9244 tg3_asic_rev(tp) == ASIC_REV_5705) {
9245 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9246 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9247 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9248 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9251 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9252 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9254 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9255 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9260 tw32_f(MAC_MODE, val);
9263 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9267 if (tg3_flag(tp, PCI_EXPRESS) &&
9268 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9269 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9270 !tg3_flag(tp, 57765_PLUS)) {
9273 tw32(0x7c00, val | (1 << 25));
9276 tg3_restore_clk(tp);
9278 /* Reprobe ASF enable state. */
9279 tg3_flag_clear(tp, ENABLE_ASF);
9280 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9281 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9283 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9284 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9285 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9288 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9289 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9290 tg3_flag_set(tp, ENABLE_ASF);
9291 tp->last_event_jiffies = jiffies;
9292 if (tg3_flag(tp, 5750_PLUS))
9293 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9295 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9296 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9297 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9298 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9299 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9306 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9307 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9308 static void __tg3_set_rx_mode(struct net_device *);
9310 /* tp->lock is held. */
9311 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9317 tg3_write_sig_pre_reset(tp, kind);
9319 tg3_abort_hw(tp, silent);
9320 err = tg3_chip_reset(tp);
9322 __tg3_set_mac_addr(tp, false);
9324 tg3_write_sig_legacy(tp, kind);
9325 tg3_write_sig_post_reset(tp, kind);
9328 /* Save the stats across chip resets... */
9329 tg3_get_nstats(tp, &tp->net_stats_prev);
9330 tg3_get_estats(tp, &tp->estats_prev);
9332 /* And make sure the next sample is new data */
9333 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9339 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9341 struct tg3 *tp = netdev_priv(dev);
9342 struct sockaddr *addr = p;
9344 bool skip_mac_1 = false;
9346 if (!is_valid_ether_addr(addr->sa_data))
9347 return -EADDRNOTAVAIL;
9349 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9351 if (!netif_running(dev))
9354 if (tg3_flag(tp, ENABLE_ASF)) {
9355 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9357 addr0_high = tr32(MAC_ADDR_0_HIGH);
9358 addr0_low = tr32(MAC_ADDR_0_LOW);
9359 addr1_high = tr32(MAC_ADDR_1_HIGH);
9360 addr1_low = tr32(MAC_ADDR_1_LOW);
9362 /* Skip MAC addr 1 if ASF is using it. */
9363 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9364 !(addr1_high == 0 && addr1_low == 0))
9367 spin_lock_bh(&tp->lock);
9368 __tg3_set_mac_addr(tp, skip_mac_1);
9369 __tg3_set_rx_mode(dev);
9370 spin_unlock_bh(&tp->lock);
9375 /* tp->lock is held. */
9376 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9377 dma_addr_t mapping, u32 maxlen_flags,
9381 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9382 ((u64) mapping >> 32));
9384 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9385 ((u64) mapping & 0xffffffff));
9387 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9390 if (!tg3_flag(tp, 5705_PLUS))
9392 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9397 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9401 if (!tg3_flag(tp, ENABLE_TSS)) {
9402 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9403 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9404 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9406 tw32(HOSTCC_TXCOL_TICKS, 0);
9407 tw32(HOSTCC_TXMAX_FRAMES, 0);
9408 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9410 for (; i < tp->txq_cnt; i++) {
9413 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9414 tw32(reg, ec->tx_coalesce_usecs);
9415 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9416 tw32(reg, ec->tx_max_coalesced_frames);
9417 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9418 tw32(reg, ec->tx_max_coalesced_frames_irq);
9422 for (; i < tp->irq_max - 1; i++) {
9423 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9424 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9425 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9429 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9432 u32 limit = tp->rxq_cnt;
9434 if (!tg3_flag(tp, ENABLE_RSS)) {
9435 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9436 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9437 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9440 tw32(HOSTCC_RXCOL_TICKS, 0);
9441 tw32(HOSTCC_RXMAX_FRAMES, 0);
9442 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9445 for (; i < limit; i++) {
9448 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9449 tw32(reg, ec->rx_coalesce_usecs);
9450 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9451 tw32(reg, ec->rx_max_coalesced_frames);
9452 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9453 tw32(reg, ec->rx_max_coalesced_frames_irq);
9456 for (; i < tp->irq_max - 1; i++) {
9457 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9458 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9459 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9463 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9465 tg3_coal_tx_init(tp, ec);
9466 tg3_coal_rx_init(tp, ec);
9468 if (!tg3_flag(tp, 5705_PLUS)) {
9469 u32 val = ec->stats_block_coalesce_usecs;
9471 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9472 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9477 tw32(HOSTCC_STAT_COAL_TICKS, val);
9481 /* tp->lock is held. */
9482 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9486 /* Disable all transmit rings but the first. */
9487 if (!tg3_flag(tp, 5705_PLUS))
9488 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9489 else if (tg3_flag(tp, 5717_PLUS))
9490 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9491 else if (tg3_flag(tp, 57765_CLASS) ||
9492 tg3_asic_rev(tp) == ASIC_REV_5762)
9493 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9495 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9497 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9498 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9499 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9500 BDINFO_FLAGS_DISABLED);
9503 /* tp->lock is held. */
9504 static void tg3_tx_rcbs_init(struct tg3 *tp)
9507 u32 txrcb = NIC_SRAM_SEND_RCB;
9509 if (tg3_flag(tp, ENABLE_TSS))
9512 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9513 struct tg3_napi *tnapi = &tp->napi[i];
9515 if (!tnapi->tx_ring)
9518 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9519 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9520 NIC_SRAM_TX_BUFFER_DESC);
9524 /* tp->lock is held. */
9525 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9529 /* Disable all receive return rings but the first. */
9530 if (tg3_flag(tp, 5717_PLUS))
9531 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9532 else if (!tg3_flag(tp, 5705_PLUS))
9533 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9534 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9535 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9536 tg3_flag(tp, 57765_CLASS))
9537 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9539 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9541 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9542 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9543 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9544 BDINFO_FLAGS_DISABLED);
9547 /* tp->lock is held. */
9548 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9551 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9553 if (tg3_flag(tp, ENABLE_RSS))
9556 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9557 struct tg3_napi *tnapi = &tp->napi[i];
9562 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9563 (tp->rx_ret_ring_mask + 1) <<
9564 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9568 /* tp->lock is held. */
9569 static void tg3_rings_reset(struct tg3 *tp)
9573 struct tg3_napi *tnapi = &tp->napi[0];
9575 tg3_tx_rcbs_disable(tp);
9577 tg3_rx_ret_rcbs_disable(tp);
9579 /* Disable interrupts */
9580 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9581 tp->napi[0].chk_msi_cnt = 0;
9582 tp->napi[0].last_rx_cons = 0;
9583 tp->napi[0].last_tx_cons = 0;
9585 /* Zero mailbox registers. */
9586 if (tg3_flag(tp, SUPPORT_MSIX)) {
9587 for (i = 1; i < tp->irq_max; i++) {
9588 tp->napi[i].tx_prod = 0;
9589 tp->napi[i].tx_cons = 0;
9590 if (tg3_flag(tp, ENABLE_TSS))
9591 tw32_mailbox(tp->napi[i].prodmbox, 0);
9592 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9593 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9594 tp->napi[i].chk_msi_cnt = 0;
9595 tp->napi[i].last_rx_cons = 0;
9596 tp->napi[i].last_tx_cons = 0;
9598 if (!tg3_flag(tp, ENABLE_TSS))
9599 tw32_mailbox(tp->napi[0].prodmbox, 0);
9601 tp->napi[0].tx_prod = 0;
9602 tp->napi[0].tx_cons = 0;
9603 tw32_mailbox(tp->napi[0].prodmbox, 0);
9604 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9607 /* Make sure the NIC-based send BD rings are disabled. */
9608 if (!tg3_flag(tp, 5705_PLUS)) {
9609 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9610 for (i = 0; i < 16; i++)
9611 tw32_tx_mbox(mbox + i * 8, 0);
9614 /* Clear status block in ram. */
9615 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9617 /* Set status block DMA address */
9618 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9619 ((u64) tnapi->status_mapping >> 32));
9620 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9621 ((u64) tnapi->status_mapping & 0xffffffff));
9623 stblk = HOSTCC_STATBLCK_RING1;
9625 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9626 u64 mapping = (u64)tnapi->status_mapping;
9627 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9628 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9631 /* Clear status block in ram. */
9632 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9635 tg3_tx_rcbs_init(tp);
9636 tg3_rx_ret_rcbs_init(tp);
9639 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9641 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9643 if (!tg3_flag(tp, 5750_PLUS) ||
9644 tg3_flag(tp, 5780_CLASS) ||
9645 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9646 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9647 tg3_flag(tp, 57765_PLUS))
9648 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9649 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9650 tg3_asic_rev(tp) == ASIC_REV_5787)
9651 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9653 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9655 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9656 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9658 val = min(nic_rep_thresh, host_rep_thresh);
9659 tw32(RCVBDI_STD_THRESH, val);
9661 if (tg3_flag(tp, 57765_PLUS))
9662 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9664 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9667 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9669 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9671 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9672 tw32(RCVBDI_JUMBO_THRESH, val);
9674 if (tg3_flag(tp, 57765_PLUS))
9675 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9678 static inline u32 calc_crc(unsigned char *buf, int len)
9686 for (j = 0; j < len; j++) {
9689 for (k = 0; k < 8; k++) {
9702 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9704 /* accept or reject all multicast frames */
9705 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9706 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9707 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9708 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9711 static void __tg3_set_rx_mode(struct net_device *dev)
9713 struct tg3 *tp = netdev_priv(dev);
9716 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9717 RX_MODE_KEEP_VLAN_TAG);
9719 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9720 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9723 if (!tg3_flag(tp, ENABLE_ASF))
9724 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9727 if (dev->flags & IFF_PROMISC) {
9728 /* Promiscuous mode. */
9729 rx_mode |= RX_MODE_PROMISC;
9730 } else if (dev->flags & IFF_ALLMULTI) {
9731 /* Accept all multicast. */
9732 tg3_set_multi(tp, 1);
9733 } else if (netdev_mc_empty(dev)) {
9734 /* Reject all multicast. */
9735 tg3_set_multi(tp, 0);
9737 /* Accept one or more multicast(s). */
9738 struct netdev_hw_addr *ha;
9739 u32 mc_filter[4] = { 0, };
9744 netdev_for_each_mc_addr(ha, dev) {
9745 crc = calc_crc(ha->addr, ETH_ALEN);
9747 regidx = (bit & 0x60) >> 5;
9749 mc_filter[regidx] |= (1 << bit);
9752 tw32(MAC_HASH_REG_0, mc_filter[0]);
9753 tw32(MAC_HASH_REG_1, mc_filter[1]);
9754 tw32(MAC_HASH_REG_2, mc_filter[2]);
9755 tw32(MAC_HASH_REG_3, mc_filter[3]);
9758 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9759 rx_mode |= RX_MODE_PROMISC;
9760 } else if (!(dev->flags & IFF_PROMISC)) {
9761 /* Add all entries into to the mac addr filter list */
9763 struct netdev_hw_addr *ha;
9765 netdev_for_each_uc_addr(ha, dev) {
9766 __tg3_set_one_mac_addr(tp, ha->addr,
9767 i + TG3_UCAST_ADDR_IDX(tp));
9772 if (rx_mode != tp->rx_mode) {
9773 tp->rx_mode = rx_mode;
9774 tw32_f(MAC_RX_MODE, rx_mode);
9779 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9783 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9784 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9787 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9791 if (!tg3_flag(tp, SUPPORT_MSIX))
9794 if (tp->rxq_cnt == 1) {
9795 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9799 /* Validate table against current IRQ count */
9800 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9801 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9805 if (i != TG3_RSS_INDIR_TBL_SIZE)
9806 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9809 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9812 u32 reg = MAC_RSS_INDIR_TBL_0;
9814 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9815 u32 val = tp->rss_ind_tbl[i];
9817 for (; i % 8; i++) {
9819 val |= tp->rss_ind_tbl[i];
9826 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9828 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9829 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9831 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9834 /* tp->lock is held. */
9835 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9837 u32 val, rdmac_mode;
9839 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9841 tg3_disable_ints(tp);
9845 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9847 if (tg3_flag(tp, INIT_COMPLETE))
9848 tg3_abort_hw(tp, 1);
9850 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9851 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9852 tg3_phy_pull_config(tp);
9853 tg3_eee_pull_config(tp, NULL);
9854 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9857 /* Enable MAC control of LPI */
9858 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9864 err = tg3_chip_reset(tp);
9868 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9870 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9871 val = tr32(TG3_CPMU_CTRL);
9872 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9873 tw32(TG3_CPMU_CTRL, val);
9875 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9876 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9877 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9878 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9880 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9881 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9882 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9883 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9885 val = tr32(TG3_CPMU_HST_ACC);
9886 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9887 val |= CPMU_HST_ACC_MACCLK_6_25;
9888 tw32(TG3_CPMU_HST_ACC, val);
9891 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9892 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9893 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9894 PCIE_PWR_MGMT_L1_THRESH_4MS;
9895 tw32(PCIE_PWR_MGMT_THRESH, val);
9897 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9898 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9900 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9902 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9903 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9906 if (tg3_flag(tp, L1PLLPD_EN)) {
9907 u32 grc_mode = tr32(GRC_MODE);
9909 /* Access the lower 1K of PL PCIE block registers. */
9910 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9911 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9913 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9914 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9915 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9917 tw32(GRC_MODE, grc_mode);
9920 if (tg3_flag(tp, 57765_CLASS)) {
9921 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9922 u32 grc_mode = tr32(GRC_MODE);
9924 /* Access the lower 1K of PL PCIE block registers. */
9925 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9926 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9928 val = tr32(TG3_PCIE_TLDLPL_PORT +
9929 TG3_PCIE_PL_LO_PHYCTL5);
9930 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9931 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9933 tw32(GRC_MODE, grc_mode);
9936 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9939 /* Fix transmit hangs */
9940 val = tr32(TG3_CPMU_PADRNG_CTL);
9941 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9942 tw32(TG3_CPMU_PADRNG_CTL, val);
9944 grc_mode = tr32(GRC_MODE);
9946 /* Access the lower 1K of DL PCIE block registers. */
9947 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9948 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9950 val = tr32(TG3_PCIE_TLDLPL_PORT +
9951 TG3_PCIE_DL_LO_FTSMAX);
9952 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9953 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9954 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9956 tw32(GRC_MODE, grc_mode);
9959 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9960 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9961 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9962 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9965 /* This works around an issue with Athlon chipsets on
9966 * B3 tigon3 silicon. This bit has no effect on any
9967 * other revision. But do not set this on PCI Express
9968 * chips and don't even touch the clocks if the CPMU is present.
9970 if (!tg3_flag(tp, CPMU_PRESENT)) {
9971 if (!tg3_flag(tp, PCI_EXPRESS))
9972 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9973 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9976 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9977 tg3_flag(tp, PCIX_MODE)) {
9978 val = tr32(TG3PCI_PCISTATE);
9979 val |= PCISTATE_RETRY_SAME_DMA;
9980 tw32(TG3PCI_PCISTATE, val);
9983 if (tg3_flag(tp, ENABLE_APE)) {
9984 /* Allow reads and writes to the
9985 * APE register and memory space.
9987 val = tr32(TG3PCI_PCISTATE);
9988 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9989 PCISTATE_ALLOW_APE_SHMEM_WR |
9990 PCISTATE_ALLOW_APE_PSPACE_WR;
9991 tw32(TG3PCI_PCISTATE, val);
9994 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9995 /* Enable some hw fixes. */
9996 val = tr32(TG3PCI_MSI_DATA);
9997 val |= (1 << 26) | (1 << 28) | (1 << 29);
9998 tw32(TG3PCI_MSI_DATA, val);
10001 /* Descriptor ring init may make accesses to the
10002 * NIC SRAM area to setup the TX descriptors, so we
10003 * can only do this after the hardware has been
10004 * successfully reset.
10006 err = tg3_init_rings(tp);
10010 if (tg3_flag(tp, 57765_PLUS)) {
10011 val = tr32(TG3PCI_DMA_RW_CTRL) &
10012 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
10013 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10014 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10015 if (!tg3_flag(tp, 57765_CLASS) &&
10016 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10017 tg3_asic_rev(tp) != ASIC_REV_5762)
10018 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10019 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10020 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10021 tg3_asic_rev(tp) != ASIC_REV_5761) {
10022 /* This value is determined during the probe time DMA
10023 * engine test, tg3_test_dma.
10025 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10028 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10029 GRC_MODE_4X_NIC_SEND_RINGS |
10030 GRC_MODE_NO_TX_PHDR_CSUM |
10031 GRC_MODE_NO_RX_PHDR_CSUM);
10032 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10034 /* Pseudo-header checksum is done by hardware logic and not
10035 * the offload processers, so make the chip do the pseudo-
10036 * header checksums on receive. For transmit it is more
10037 * convenient to do the pseudo-header checksum in software
10038 * as Linux does that on transmit for us in all cases.
10040 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10042 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10044 tw32(TG3_RX_PTP_CTL,
10045 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10047 if (tg3_flag(tp, PTP_CAPABLE))
10048 val |= GRC_MODE_TIME_SYNC_ENABLE;
10050 tw32(GRC_MODE, tp->grc_mode | val);
10052 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10053 val = tr32(GRC_MISC_CFG);
10055 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10056 tw32(GRC_MISC_CFG, val);
10058 /* Initialize MBUF/DESC pool. */
10059 if (tg3_flag(tp, 5750_PLUS)) {
10061 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10062 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10063 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10064 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10066 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10067 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10068 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10069 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10072 fw_len = tp->fw_len;
10073 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10074 tw32(BUFMGR_MB_POOL_ADDR,
10075 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10076 tw32(BUFMGR_MB_POOL_SIZE,
10077 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10080 if (tp->dev->mtu <= ETH_DATA_LEN) {
10081 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10082 tp->bufmgr_config.mbuf_read_dma_low_water);
10083 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10084 tp->bufmgr_config.mbuf_mac_rx_low_water);
10085 tw32(BUFMGR_MB_HIGH_WATER,
10086 tp->bufmgr_config.mbuf_high_water);
10088 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10089 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10090 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10091 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10092 tw32(BUFMGR_MB_HIGH_WATER,
10093 tp->bufmgr_config.mbuf_high_water_jumbo);
10095 tw32(BUFMGR_DMA_LOW_WATER,
10096 tp->bufmgr_config.dma_low_water);
10097 tw32(BUFMGR_DMA_HIGH_WATER,
10098 tp->bufmgr_config.dma_high_water);
10100 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10101 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10102 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10103 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10104 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10105 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10106 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10107 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10108 tw32(BUFMGR_MODE, val);
10109 for (i = 0; i < 2000; i++) {
10110 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10115 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10119 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10120 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10122 tg3_setup_rxbd_thresholds(tp);
10124 /* Initialize TG3_BDINFO's at:
10125 * RCVDBDI_STD_BD: standard eth size rx ring
10126 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10127 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10130 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10131 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10132 * ring attribute flags
10133 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10135 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10136 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10138 * The size of each ring is fixed in the firmware, but the location is
10141 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10142 ((u64) tpr->rx_std_mapping >> 32));
10143 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10144 ((u64) tpr->rx_std_mapping & 0xffffffff));
10145 if (!tg3_flag(tp, 5717_PLUS))
10146 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10147 NIC_SRAM_RX_BUFFER_DESC);
10149 /* Disable the mini ring */
10150 if (!tg3_flag(tp, 5705_PLUS))
10151 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10152 BDINFO_FLAGS_DISABLED);
10154 /* Program the jumbo buffer descriptor ring control
10155 * blocks on those devices that have them.
10157 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10158 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10160 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10161 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10162 ((u64) tpr->rx_jmb_mapping >> 32));
10163 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10164 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10165 val = TG3_RX_JMB_RING_SIZE(tp) <<
10166 BDINFO_FLAGS_MAXLEN_SHIFT;
10167 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10168 val | BDINFO_FLAGS_USE_EXT_RECV);
10169 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10170 tg3_flag(tp, 57765_CLASS) ||
10171 tg3_asic_rev(tp) == ASIC_REV_5762)
10172 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10173 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10175 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10176 BDINFO_FLAGS_DISABLED);
10179 if (tg3_flag(tp, 57765_PLUS)) {
10180 val = TG3_RX_STD_RING_SIZE(tp);
10181 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10182 val |= (TG3_RX_STD_DMA_SZ << 2);
10184 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10186 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10188 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10190 tpr->rx_std_prod_idx = tp->rx_pending;
10191 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10193 tpr->rx_jmb_prod_idx =
10194 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10195 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10197 tg3_rings_reset(tp);
10199 /* Initialize MAC address and backoff seed. */
10200 __tg3_set_mac_addr(tp, false);
10202 /* MTU + ethernet header + FCS + optional VLAN tag */
10203 tw32(MAC_RX_MTU_SIZE,
10204 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10206 /* The slot time is changed by tg3_setup_phy if we
10207 * run at gigabit with half duplex.
10209 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10210 (6 << TX_LENGTHS_IPG_SHIFT) |
10211 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10213 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10214 tg3_asic_rev(tp) == ASIC_REV_5762)
10215 val |= tr32(MAC_TX_LENGTHS) &
10216 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10217 TX_LENGTHS_CNT_DWN_VAL_MSK);
10219 tw32(MAC_TX_LENGTHS, val);
10221 /* Receive rules. */
10222 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10223 tw32(RCVLPC_CONFIG, 0x0181);
10225 /* Calculate RDMAC_MODE setting early, we need it to determine
10226 * the RCVLPC_STATE_ENABLE mask.
10228 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10229 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10230 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10231 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10232 RDMAC_MODE_LNGREAD_ENAB);
10234 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10235 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10237 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10238 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10239 tg3_asic_rev(tp) == ASIC_REV_57780)
10240 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10241 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10242 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10244 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10245 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10246 if (tg3_flag(tp, TSO_CAPABLE) &&
10247 tg3_asic_rev(tp) == ASIC_REV_5705) {
10248 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10249 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10250 !tg3_flag(tp, IS_5788)) {
10251 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10255 if (tg3_flag(tp, PCI_EXPRESS))
10256 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10258 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10260 if (tp->dev->mtu <= ETH_DATA_LEN) {
10261 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10262 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10266 if (tg3_flag(tp, HW_TSO_1) ||
10267 tg3_flag(tp, HW_TSO_2) ||
10268 tg3_flag(tp, HW_TSO_3))
10269 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10271 if (tg3_flag(tp, 57765_PLUS) ||
10272 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10273 tg3_asic_rev(tp) == ASIC_REV_57780)
10274 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10276 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10277 tg3_asic_rev(tp) == ASIC_REV_5762)
10278 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10280 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10281 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10282 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10283 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10284 tg3_flag(tp, 57765_PLUS)) {
10287 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10288 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10290 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10292 val = tr32(tgtreg);
10293 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10294 tg3_asic_rev(tp) == ASIC_REV_5762) {
10295 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10296 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10297 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10298 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10299 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10300 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10302 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10305 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10306 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10307 tg3_asic_rev(tp) == ASIC_REV_5762) {
10310 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10311 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10313 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10315 val = tr32(tgtreg);
10317 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10318 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10321 /* Receive/send statistics. */
10322 if (tg3_flag(tp, 5750_PLUS)) {
10323 val = tr32(RCVLPC_STATS_ENABLE);
10324 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10325 tw32(RCVLPC_STATS_ENABLE, val);
10326 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10327 tg3_flag(tp, TSO_CAPABLE)) {
10328 val = tr32(RCVLPC_STATS_ENABLE);
10329 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10330 tw32(RCVLPC_STATS_ENABLE, val);
10332 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10334 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10335 tw32(SNDDATAI_STATSENAB, 0xffffff);
10336 tw32(SNDDATAI_STATSCTRL,
10337 (SNDDATAI_SCTRL_ENABLE |
10338 SNDDATAI_SCTRL_FASTUPD));
10340 /* Setup host coalescing engine. */
10341 tw32(HOSTCC_MODE, 0);
10342 for (i = 0; i < 2000; i++) {
10343 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10348 __tg3_set_coalesce(tp, &tp->coal);
10350 if (!tg3_flag(tp, 5705_PLUS)) {
10351 /* Status/statistics block address. See tg3_timer,
10352 * the tg3_periodic_fetch_stats call there, and
10353 * tg3_get_stats to see how this works for 5705/5750 chips.
10355 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10356 ((u64) tp->stats_mapping >> 32));
10357 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10358 ((u64) tp->stats_mapping & 0xffffffff));
10359 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10361 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10363 /* Clear statistics and status block memory areas */
10364 for (i = NIC_SRAM_STATS_BLK;
10365 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10366 i += sizeof(u32)) {
10367 tg3_write_mem(tp, i, 0);
10372 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10374 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10375 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10376 if (!tg3_flag(tp, 5705_PLUS))
10377 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10379 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10380 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10381 /* reset to prevent losing 1st rx packet intermittently */
10382 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10386 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10387 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10388 MAC_MODE_FHDE_ENABLE;
10389 if (tg3_flag(tp, ENABLE_APE))
10390 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10391 if (!tg3_flag(tp, 5705_PLUS) &&
10392 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10393 tg3_asic_rev(tp) != ASIC_REV_5700)
10394 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10395 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10398 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10399 * If TG3_FLAG_IS_NIC is zero, we should read the
10400 * register to preserve the GPIO settings for LOMs. The GPIOs,
10401 * whether used as inputs or outputs, are set by boot code after
10404 if (!tg3_flag(tp, IS_NIC)) {
10407 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10408 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10409 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10411 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10412 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10413 GRC_LCLCTRL_GPIO_OUTPUT3;
10415 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10416 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10418 tp->grc_local_ctrl &= ~gpio_mask;
10419 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10421 /* GPIO1 must be driven high for eeprom write protect */
10422 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10423 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10424 GRC_LCLCTRL_GPIO_OUTPUT1);
10426 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10429 if (tg3_flag(tp, USING_MSIX)) {
10430 val = tr32(MSGINT_MODE);
10431 val |= MSGINT_MODE_ENABLE;
10432 if (tp->irq_cnt > 1)
10433 val |= MSGINT_MODE_MULTIVEC_EN;
10434 if (!tg3_flag(tp, 1SHOT_MSI))
10435 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10436 tw32(MSGINT_MODE, val);
10439 if (!tg3_flag(tp, 5705_PLUS)) {
10440 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10444 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10445 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10446 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10447 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10448 WDMAC_MODE_LNGREAD_ENAB);
10450 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10451 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10452 if (tg3_flag(tp, TSO_CAPABLE) &&
10453 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10454 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10456 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10457 !tg3_flag(tp, IS_5788)) {
10458 val |= WDMAC_MODE_RX_ACCEL;
10462 /* Enable host coalescing bug fix */
10463 if (tg3_flag(tp, 5755_PLUS))
10464 val |= WDMAC_MODE_STATUS_TAG_FIX;
10466 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10467 val |= WDMAC_MODE_BURST_ALL_DATA;
10469 tw32_f(WDMAC_MODE, val);
10472 if (tg3_flag(tp, PCIX_MODE)) {
10475 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10477 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10478 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10479 pcix_cmd |= PCI_X_CMD_READ_2K;
10480 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10481 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10482 pcix_cmd |= PCI_X_CMD_READ_2K;
10484 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10488 tw32_f(RDMAC_MODE, rdmac_mode);
10491 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10492 tg3_asic_rev(tp) == ASIC_REV_5720) {
10493 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10494 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10497 if (i < TG3_NUM_RDMA_CHANNELS) {
10498 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10499 val |= tg3_lso_rd_dma_workaround_bit(tp);
10500 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10501 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10505 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10506 if (!tg3_flag(tp, 5705_PLUS))
10507 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10509 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10510 tw32(SNDDATAC_MODE,
10511 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10513 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10515 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10516 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10517 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10518 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10519 val |= RCVDBDI_MODE_LRG_RING_SZ;
10520 tw32(RCVDBDI_MODE, val);
10521 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10522 if (tg3_flag(tp, HW_TSO_1) ||
10523 tg3_flag(tp, HW_TSO_2) ||
10524 tg3_flag(tp, HW_TSO_3))
10525 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10526 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10527 if (tg3_flag(tp, ENABLE_TSS))
10528 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10529 tw32(SNDBDI_MODE, val);
10530 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10532 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10533 err = tg3_load_5701_a0_firmware_fix(tp);
10538 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10539 /* Ignore any errors for the firmware download. If download
10540 * fails, the device will operate with EEE disabled
10542 tg3_load_57766_firmware(tp);
10545 if (tg3_flag(tp, TSO_CAPABLE)) {
10546 err = tg3_load_tso_firmware(tp);
10551 tp->tx_mode = TX_MODE_ENABLE;
10553 if (tg3_flag(tp, 5755_PLUS) ||
10554 tg3_asic_rev(tp) == ASIC_REV_5906)
10555 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10557 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10558 tg3_asic_rev(tp) == ASIC_REV_5762) {
10559 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10560 tp->tx_mode &= ~val;
10561 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10564 tw32_f(MAC_TX_MODE, tp->tx_mode);
10567 if (tg3_flag(tp, ENABLE_RSS)) {
10570 tg3_rss_write_indir_tbl(tp);
10572 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10574 for (i = 0; i < 10 ; i++)
10575 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10578 tp->rx_mode = RX_MODE_ENABLE;
10579 if (tg3_flag(tp, 5755_PLUS))
10580 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10582 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10583 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10585 if (tg3_flag(tp, ENABLE_RSS))
10586 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10587 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10588 RX_MODE_RSS_IPV6_HASH_EN |
10589 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10590 RX_MODE_RSS_IPV4_HASH_EN |
10591 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10593 tw32_f(MAC_RX_MODE, tp->rx_mode);
10596 tw32(MAC_LED_CTRL, tp->led_ctrl);
10598 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10599 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10600 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10603 tw32_f(MAC_RX_MODE, tp->rx_mode);
10606 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10607 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10608 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10609 /* Set drive transmission level to 1.2V */
10610 /* only if the signal pre-emphasis bit is not set */
10611 val = tr32(MAC_SERDES_CFG);
10614 tw32(MAC_SERDES_CFG, val);
10616 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10617 tw32(MAC_SERDES_CFG, 0x616000);
10620 /* Prevent chip from dropping frames when flow control
10623 if (tg3_flag(tp, 57765_CLASS))
10627 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10629 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10630 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10631 /* Use hardware link auto-negotiation */
10632 tg3_flag_set(tp, HW_AUTONEG);
10635 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10636 tg3_asic_rev(tp) == ASIC_REV_5714) {
10639 tmp = tr32(SERDES_RX_CTRL);
10640 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10641 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10642 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10643 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10646 if (!tg3_flag(tp, USE_PHYLIB)) {
10647 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10648 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10650 err = tg3_setup_phy(tp, false);
10654 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10655 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10658 /* Clear CRC stats. */
10659 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10660 tg3_writephy(tp, MII_TG3_TEST1,
10661 tmp | MII_TG3_TEST1_CRC_EN);
10662 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10667 __tg3_set_rx_mode(tp->dev);
10669 /* Initialize receive rules. */
10670 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10671 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10672 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10673 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10675 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10679 if (tg3_flag(tp, ENABLE_ASF))
10683 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10685 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10687 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10689 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10691 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10693 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10695 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10697 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10699 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10701 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10703 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10705 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10707 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10709 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10717 if (tg3_flag(tp, ENABLE_APE))
10718 /* Write our heartbeat update interval to APE. */
10719 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10720 APE_HOST_HEARTBEAT_INT_DISABLE);
10722 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10727 /* Called at device open time to get the chip ready for
10728 * packet processing. Invoked with tp->lock held.
10730 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10732 /* Chip may have been just powered on. If so, the boot code may still
10733 * be running initialization. Wait for it to finish to avoid races in
10734 * accessing the hardware.
10736 tg3_enable_register_access(tp);
10739 tg3_switch_clocks(tp);
10741 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10743 return tg3_reset_hw(tp, reset_phy);
10746 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10750 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10751 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10753 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10756 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10757 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10758 memset(ocir, 0, TG3_OCIR_LEN);
10762 /* sysfs attributes for hwmon */
10763 static ssize_t tg3_show_temp(struct device *dev,
10764 struct device_attribute *devattr, char *buf)
10766 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10767 struct tg3 *tp = dev_get_drvdata(dev);
10770 spin_lock_bh(&tp->lock);
10771 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10772 sizeof(temperature));
10773 spin_unlock_bh(&tp->lock);
10774 return sprintf(buf, "%u\n", temperature * 1000);
10778 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10779 TG3_TEMP_SENSOR_OFFSET);
10780 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10781 TG3_TEMP_CAUTION_OFFSET);
10782 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10783 TG3_TEMP_MAX_OFFSET);
10785 static struct attribute *tg3_attrs[] = {
10786 &sensor_dev_attr_temp1_input.dev_attr.attr,
10787 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10788 &sensor_dev_attr_temp1_max.dev_attr.attr,
10791 ATTRIBUTE_GROUPS(tg3);
10793 static void tg3_hwmon_close(struct tg3 *tp)
10795 if (tp->hwmon_dev) {
10796 hwmon_device_unregister(tp->hwmon_dev);
10797 tp->hwmon_dev = NULL;
10801 static void tg3_hwmon_open(struct tg3 *tp)
10805 struct pci_dev *pdev = tp->pdev;
10806 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10808 tg3_sd_scan_scratchpad(tp, ocirs);
10810 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10811 if (!ocirs[i].src_data_length)
10814 size += ocirs[i].src_hdr_length;
10815 size += ocirs[i].src_data_length;
10821 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10823 if (IS_ERR(tp->hwmon_dev)) {
10824 tp->hwmon_dev = NULL;
10825 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10830 #define TG3_STAT_ADD32(PSTAT, REG) \
10831 do { u32 __val = tr32(REG); \
10832 (PSTAT)->low += __val; \
10833 if ((PSTAT)->low < __val) \
10834 (PSTAT)->high += 1; \
10837 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10839 struct tg3_hw_stats *sp = tp->hw_stats;
10844 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10845 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10846 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10847 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10848 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10849 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10850 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10851 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10852 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10853 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10854 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10855 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10856 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10857 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10858 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10859 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10862 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10863 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10864 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10865 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10868 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10869 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10870 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10871 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10872 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10873 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10874 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10875 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10876 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10877 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10878 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10879 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10880 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10881 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10883 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10884 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10885 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10886 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10887 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10888 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10890 u32 val = tr32(HOSTCC_FLOW_ATTN);
10891 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10893 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10894 sp->rx_discards.low += val;
10895 if (sp->rx_discards.low < val)
10896 sp->rx_discards.high += 1;
10898 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10900 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10903 static void tg3_chk_missed_msi(struct tg3 *tp)
10907 for (i = 0; i < tp->irq_cnt; i++) {
10908 struct tg3_napi *tnapi = &tp->napi[i];
10910 if (tg3_has_work(tnapi)) {
10911 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10912 tnapi->last_tx_cons == tnapi->tx_cons) {
10913 if (tnapi->chk_msi_cnt < 1) {
10914 tnapi->chk_msi_cnt++;
10920 tnapi->chk_msi_cnt = 0;
10921 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10922 tnapi->last_tx_cons = tnapi->tx_cons;
10926 static void tg3_timer(unsigned long __opaque)
10928 struct tg3 *tp = (struct tg3 *) __opaque;
10930 spin_lock(&tp->lock);
10932 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10933 spin_unlock(&tp->lock);
10934 goto restart_timer;
10937 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10938 tg3_flag(tp, 57765_CLASS))
10939 tg3_chk_missed_msi(tp);
10941 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10942 /* BCM4785: Flush posted writes from GbE to host memory. */
10946 if (!tg3_flag(tp, TAGGED_STATUS)) {
10947 /* All of this garbage is because when using non-tagged
10948 * IRQ status the mailbox/status_block protocol the chip
10949 * uses with the cpu is race prone.
10951 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10952 tw32(GRC_LOCAL_CTRL,
10953 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10955 tw32(HOSTCC_MODE, tp->coalesce_mode |
10956 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10959 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10960 spin_unlock(&tp->lock);
10961 tg3_reset_task_schedule(tp);
10962 goto restart_timer;
10966 /* This part only runs once per second. */
10967 if (!--tp->timer_counter) {
10968 if (tg3_flag(tp, 5705_PLUS))
10969 tg3_periodic_fetch_stats(tp);
10971 if (tp->setlpicnt && !--tp->setlpicnt)
10972 tg3_phy_eee_enable(tp);
10974 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10978 mac_stat = tr32(MAC_STATUS);
10981 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10982 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10984 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10988 tg3_setup_phy(tp, false);
10989 } else if (tg3_flag(tp, POLL_SERDES)) {
10990 u32 mac_stat = tr32(MAC_STATUS);
10991 int need_setup = 0;
10994 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10997 if (!tp->link_up &&
10998 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10999 MAC_STATUS_SIGNAL_DET))) {
11003 if (!tp->serdes_counter) {
11006 ~MAC_MODE_PORT_MODE_MASK));
11008 tw32_f(MAC_MODE, tp->mac_mode);
11011 tg3_setup_phy(tp, false);
11013 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11014 tg3_flag(tp, 5780_CLASS)) {
11015 tg3_serdes_parallel_detect(tp);
11016 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11017 u32 cpmu = tr32(TG3_CPMU_STATUS);
11018 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11019 TG3_CPMU_STATUS_LINK_MASK);
11021 if (link_up != tp->link_up)
11022 tg3_setup_phy(tp, false);
11025 tp->timer_counter = tp->timer_multiplier;
11028 /* Heartbeat is only sent once every 2 seconds.
11030 * The heartbeat is to tell the ASF firmware that the host
11031 * driver is still alive. In the event that the OS crashes,
11032 * ASF needs to reset the hardware to free up the FIFO space
11033 * that may be filled with rx packets destined for the host.
11034 * If the FIFO is full, ASF will no longer function properly.
11036 * Unintended resets have been reported on real time kernels
11037 * where the timer doesn't run on time. Netpoll will also have
11040 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11041 * to check the ring condition when the heartbeat is expiring
11042 * before doing the reset. This will prevent most unintended
11045 if (!--tp->asf_counter) {
11046 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11047 tg3_wait_for_event_ack(tp);
11049 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11050 FWCMD_NICDRV_ALIVE3);
11051 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11052 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11053 TG3_FW_UPDATE_TIMEOUT_SEC);
11055 tg3_generate_fw_event(tp);
11057 tp->asf_counter = tp->asf_multiplier;
11060 spin_unlock(&tp->lock);
11063 tp->timer.expires = jiffies + tp->timer_offset;
11064 add_timer(&tp->timer);
11067 static void tg3_timer_init(struct tg3 *tp)
11069 if (tg3_flag(tp, TAGGED_STATUS) &&
11070 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11071 !tg3_flag(tp, 57765_CLASS))
11072 tp->timer_offset = HZ;
11074 tp->timer_offset = HZ / 10;
11076 BUG_ON(tp->timer_offset > HZ);
11078 tp->timer_multiplier = (HZ / tp->timer_offset);
11079 tp->asf_multiplier = (HZ / tp->timer_offset) *
11080 TG3_FW_UPDATE_FREQ_SEC;
11082 init_timer(&tp->timer);
11083 tp->timer.data = (unsigned long) tp;
11084 tp->timer.function = tg3_timer;
11087 static void tg3_timer_start(struct tg3 *tp)
11089 tp->asf_counter = tp->asf_multiplier;
11090 tp->timer_counter = tp->timer_multiplier;
11092 tp->timer.expires = jiffies + tp->timer_offset;
11093 add_timer(&tp->timer);
11096 static void tg3_timer_stop(struct tg3 *tp)
11098 del_timer_sync(&tp->timer);
11101 /* Restart hardware after configuration changes, self-test, etc.
11102 * Invoked with tp->lock held.
11104 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11105 __releases(tp->lock)
11106 __acquires(tp->lock)
11110 err = tg3_init_hw(tp, reset_phy);
11112 netdev_err(tp->dev,
11113 "Failed to re-initialize device, aborting\n");
11114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11115 tg3_full_unlock(tp);
11116 tg3_timer_stop(tp);
11118 tg3_napi_enable(tp);
11119 dev_close(tp->dev);
11120 tg3_full_lock(tp, 0);
11125 static void tg3_reset_task(struct work_struct *work)
11127 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11131 tg3_full_lock(tp, 0);
11133 if (!netif_running(tp->dev)) {
11134 tg3_flag_clear(tp, RESET_TASK_PENDING);
11135 tg3_full_unlock(tp);
11140 tg3_full_unlock(tp);
11144 tg3_netif_stop(tp);
11146 tg3_full_lock(tp, 1);
11148 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11149 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11150 tp->write32_rx_mbox = tg3_write_flush_reg32;
11151 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11152 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11155 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11156 err = tg3_init_hw(tp, true);
11160 tg3_netif_start(tp);
11163 tg3_full_unlock(tp);
11168 tg3_flag_clear(tp, RESET_TASK_PENDING);
11172 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11175 unsigned long flags;
11177 struct tg3_napi *tnapi = &tp->napi[irq_num];
11179 if (tp->irq_cnt == 1)
11180 name = tp->dev->name;
11182 name = &tnapi->irq_lbl[0];
11183 if (tnapi->tx_buffers && tnapi->rx_rcb)
11184 snprintf(name, IFNAMSIZ,
11185 "%s-txrx-%d", tp->dev->name, irq_num);
11186 else if (tnapi->tx_buffers)
11187 snprintf(name, IFNAMSIZ,
11188 "%s-tx-%d", tp->dev->name, irq_num);
11189 else if (tnapi->rx_rcb)
11190 snprintf(name, IFNAMSIZ,
11191 "%s-rx-%d", tp->dev->name, irq_num);
11193 snprintf(name, IFNAMSIZ,
11194 "%s-%d", tp->dev->name, irq_num);
11195 name[IFNAMSIZ-1] = 0;
11198 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11200 if (tg3_flag(tp, 1SHOT_MSI))
11201 fn = tg3_msi_1shot;
11204 fn = tg3_interrupt;
11205 if (tg3_flag(tp, TAGGED_STATUS))
11206 fn = tg3_interrupt_tagged;
11207 flags = IRQF_SHARED;
11210 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11213 static int tg3_test_interrupt(struct tg3 *tp)
11215 struct tg3_napi *tnapi = &tp->napi[0];
11216 struct net_device *dev = tp->dev;
11217 int err, i, intr_ok = 0;
11220 if (!netif_running(dev))
11223 tg3_disable_ints(tp);
11225 free_irq(tnapi->irq_vec, tnapi);
11228 * Turn off MSI one shot mode. Otherwise this test has no
11229 * observable way to know whether the interrupt was delivered.
11231 if (tg3_flag(tp, 57765_PLUS)) {
11232 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11233 tw32(MSGINT_MODE, val);
11236 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11237 IRQF_SHARED, dev->name, tnapi);
11241 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11242 tg3_enable_ints(tp);
11244 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11247 for (i = 0; i < 5; i++) {
11248 u32 int_mbox, misc_host_ctrl;
11250 int_mbox = tr32_mailbox(tnapi->int_mbox);
11251 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11253 if ((int_mbox != 0) ||
11254 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11259 if (tg3_flag(tp, 57765_PLUS) &&
11260 tnapi->hw_status->status_tag != tnapi->last_tag)
11261 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11266 tg3_disable_ints(tp);
11268 free_irq(tnapi->irq_vec, tnapi);
11270 err = tg3_request_irq(tp, 0);
11276 /* Reenable MSI one shot mode. */
11277 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11278 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11279 tw32(MSGINT_MODE, val);
11287 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11288 * successfully restored
11290 static int tg3_test_msi(struct tg3 *tp)
11295 if (!tg3_flag(tp, USING_MSI))
11298 /* Turn off SERR reporting in case MSI terminates with Master
11301 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11302 pci_write_config_word(tp->pdev, PCI_COMMAND,
11303 pci_cmd & ~PCI_COMMAND_SERR);
11305 err = tg3_test_interrupt(tp);
11307 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11312 /* other failures */
11316 /* MSI test failed, go back to INTx mode */
11317 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11318 "to INTx mode. Please report this failure to the PCI "
11319 "maintainer and include system chipset information\n");
11321 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11323 pci_disable_msi(tp->pdev);
11325 tg3_flag_clear(tp, USING_MSI);
11326 tp->napi[0].irq_vec = tp->pdev->irq;
11328 err = tg3_request_irq(tp, 0);
11332 /* Need to reset the chip because the MSI cycle may have terminated
11333 * with Master Abort.
11335 tg3_full_lock(tp, 1);
11337 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11338 err = tg3_init_hw(tp, true);
11340 tg3_full_unlock(tp);
11343 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11348 static int tg3_request_firmware(struct tg3 *tp)
11350 const struct tg3_firmware_hdr *fw_hdr;
11352 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11353 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11358 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11360 /* Firmware blob starts with version numbers, followed by
11361 * start address and _full_ length including BSS sections
11362 * (which must be longer than the actual data, of course
11365 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11366 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11367 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11368 tp->fw_len, tp->fw_needed);
11369 release_firmware(tp->fw);
11374 /* We no longer need firmware; we have it. */
11375 tp->fw_needed = NULL;
11379 static u32 tg3_irq_count(struct tg3 *tp)
11381 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11384 /* We want as many rx rings enabled as there are cpus.
11385 * In multiqueue MSI-X mode, the first MSI-X vector
11386 * only deals with link interrupts, etc, so we add
11387 * one to the number of vectors we are requesting.
11389 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11395 static bool tg3_enable_msix(struct tg3 *tp)
11398 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11400 tp->txq_cnt = tp->txq_req;
11401 tp->rxq_cnt = tp->rxq_req;
11403 tp->rxq_cnt = netif_get_num_default_rss_queues();
11404 if (tp->rxq_cnt > tp->rxq_max)
11405 tp->rxq_cnt = tp->rxq_max;
11407 /* Disable multiple TX rings by default. Simple round-robin hardware
11408 * scheduling of the TX rings can cause starvation of rings with
11409 * small packets when other rings have TSO or jumbo packets.
11414 tp->irq_cnt = tg3_irq_count(tp);
11416 for (i = 0; i < tp->irq_max; i++) {
11417 msix_ent[i].entry = i;
11418 msix_ent[i].vector = 0;
11421 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11424 } else if (rc < tp->irq_cnt) {
11425 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11428 tp->rxq_cnt = max(rc - 1, 1);
11430 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11433 for (i = 0; i < tp->irq_max; i++)
11434 tp->napi[i].irq_vec = msix_ent[i].vector;
11436 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11437 pci_disable_msix(tp->pdev);
11441 if (tp->irq_cnt == 1)
11444 tg3_flag_set(tp, ENABLE_RSS);
11446 if (tp->txq_cnt > 1)
11447 tg3_flag_set(tp, ENABLE_TSS);
11449 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11454 static void tg3_ints_init(struct tg3 *tp)
11456 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11457 !tg3_flag(tp, TAGGED_STATUS)) {
11458 /* All MSI supporting chips should support tagged
11459 * status. Assert that this is the case.
11461 netdev_warn(tp->dev,
11462 "MSI without TAGGED_STATUS? Not using MSI\n");
11466 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11467 tg3_flag_set(tp, USING_MSIX);
11468 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11469 tg3_flag_set(tp, USING_MSI);
11471 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11472 u32 msi_mode = tr32(MSGINT_MODE);
11473 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11474 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11475 if (!tg3_flag(tp, 1SHOT_MSI))
11476 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11477 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11480 if (!tg3_flag(tp, USING_MSIX)) {
11482 tp->napi[0].irq_vec = tp->pdev->irq;
11485 if (tp->irq_cnt == 1) {
11488 netif_set_real_num_tx_queues(tp->dev, 1);
11489 netif_set_real_num_rx_queues(tp->dev, 1);
11493 static void tg3_ints_fini(struct tg3 *tp)
11495 if (tg3_flag(tp, USING_MSIX))
11496 pci_disable_msix(tp->pdev);
11497 else if (tg3_flag(tp, USING_MSI))
11498 pci_disable_msi(tp->pdev);
11499 tg3_flag_clear(tp, USING_MSI);
11500 tg3_flag_clear(tp, USING_MSIX);
11501 tg3_flag_clear(tp, ENABLE_RSS);
11502 tg3_flag_clear(tp, ENABLE_TSS);
11505 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11508 struct net_device *dev = tp->dev;
11512 * Setup interrupts first so we know how
11513 * many NAPI resources to allocate
11517 tg3_rss_check_indir_tbl(tp);
11519 /* The placement of this call is tied
11520 * to the setup and use of Host TX descriptors.
11522 err = tg3_alloc_consistent(tp);
11524 goto out_ints_fini;
11528 tg3_napi_enable(tp);
11530 for (i = 0; i < tp->irq_cnt; i++) {
11531 struct tg3_napi *tnapi = &tp->napi[i];
11532 err = tg3_request_irq(tp, i);
11534 for (i--; i >= 0; i--) {
11535 tnapi = &tp->napi[i];
11536 free_irq(tnapi->irq_vec, tnapi);
11538 goto out_napi_fini;
11542 tg3_full_lock(tp, 0);
11545 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11547 err = tg3_init_hw(tp, reset_phy);
11549 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11550 tg3_free_rings(tp);
11553 tg3_full_unlock(tp);
11558 if (test_irq && tg3_flag(tp, USING_MSI)) {
11559 err = tg3_test_msi(tp);
11562 tg3_full_lock(tp, 0);
11563 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11564 tg3_free_rings(tp);
11565 tg3_full_unlock(tp);
11567 goto out_napi_fini;
11570 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11571 u32 val = tr32(PCIE_TRANSACTION_CFG);
11573 tw32(PCIE_TRANSACTION_CFG,
11574 val | PCIE_TRANS_CFG_1SHOT_MSI);
11580 tg3_hwmon_open(tp);
11582 tg3_full_lock(tp, 0);
11584 tg3_timer_start(tp);
11585 tg3_flag_set(tp, INIT_COMPLETE);
11586 tg3_enable_ints(tp);
11588 tg3_ptp_resume(tp);
11590 tg3_full_unlock(tp);
11592 netif_tx_start_all_queues(dev);
11595 * Reset loopback feature if it was turned on while the device was down
11596 * make sure that it's installed properly now.
11598 if (dev->features & NETIF_F_LOOPBACK)
11599 tg3_set_loopback(dev, dev->features);
11604 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11605 struct tg3_napi *tnapi = &tp->napi[i];
11606 free_irq(tnapi->irq_vec, tnapi);
11610 tg3_napi_disable(tp);
11612 tg3_free_consistent(tp);
11620 static void tg3_stop(struct tg3 *tp)
11624 tg3_reset_task_cancel(tp);
11625 tg3_netif_stop(tp);
11627 tg3_timer_stop(tp);
11629 tg3_hwmon_close(tp);
11633 tg3_full_lock(tp, 1);
11635 tg3_disable_ints(tp);
11637 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11638 tg3_free_rings(tp);
11639 tg3_flag_clear(tp, INIT_COMPLETE);
11641 tg3_full_unlock(tp);
11643 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11644 struct tg3_napi *tnapi = &tp->napi[i];
11645 free_irq(tnapi->irq_vec, tnapi);
11652 tg3_free_consistent(tp);
11655 static int tg3_open(struct net_device *dev)
11657 struct tg3 *tp = netdev_priv(dev);
11660 if (tp->pcierr_recovery) {
11661 netdev_err(dev, "Failed to open device. PCI error recovery "
11666 if (tp->fw_needed) {
11667 err = tg3_request_firmware(tp);
11668 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11670 netdev_warn(tp->dev, "EEE capability disabled\n");
11671 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11672 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11673 netdev_warn(tp->dev, "EEE capability restored\n");
11674 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11676 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11680 netdev_warn(tp->dev, "TSO capability disabled\n");
11681 tg3_flag_clear(tp, TSO_CAPABLE);
11682 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11683 netdev_notice(tp->dev, "TSO capability restored\n");
11684 tg3_flag_set(tp, TSO_CAPABLE);
11688 tg3_carrier_off(tp);
11690 err = tg3_power_up(tp);
11694 tg3_full_lock(tp, 0);
11696 tg3_disable_ints(tp);
11697 tg3_flag_clear(tp, INIT_COMPLETE);
11699 tg3_full_unlock(tp);
11701 err = tg3_start(tp,
11702 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11705 tg3_frob_aux_power(tp, false);
11706 pci_set_power_state(tp->pdev, PCI_D3hot);
11712 static int tg3_close(struct net_device *dev)
11714 struct tg3 *tp = netdev_priv(dev);
11716 if (tp->pcierr_recovery) {
11717 netdev_err(dev, "Failed to close device. PCI error recovery "
11724 /* Clear stats across close / open calls */
11725 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11726 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11728 if (pci_device_is_present(tp->pdev)) {
11729 tg3_power_down_prepare(tp);
11731 tg3_carrier_off(tp);
11736 static inline u64 get_stat64(tg3_stat64_t *val)
11738 return ((u64)val->high << 32) | ((u64)val->low);
11741 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11743 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11745 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11746 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11747 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11750 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11751 tg3_writephy(tp, MII_TG3_TEST1,
11752 val | MII_TG3_TEST1_CRC_EN);
11753 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11757 tp->phy_crc_errors += val;
11759 return tp->phy_crc_errors;
11762 return get_stat64(&hw_stats->rx_fcs_errors);
11765 #define ESTAT_ADD(member) \
11766 estats->member = old_estats->member + \
11767 get_stat64(&hw_stats->member)
11769 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11771 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11772 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11774 ESTAT_ADD(rx_octets);
11775 ESTAT_ADD(rx_fragments);
11776 ESTAT_ADD(rx_ucast_packets);
11777 ESTAT_ADD(rx_mcast_packets);
11778 ESTAT_ADD(rx_bcast_packets);
11779 ESTAT_ADD(rx_fcs_errors);
11780 ESTAT_ADD(rx_align_errors);
11781 ESTAT_ADD(rx_xon_pause_rcvd);
11782 ESTAT_ADD(rx_xoff_pause_rcvd);
11783 ESTAT_ADD(rx_mac_ctrl_rcvd);
11784 ESTAT_ADD(rx_xoff_entered);
11785 ESTAT_ADD(rx_frame_too_long_errors);
11786 ESTAT_ADD(rx_jabbers);
11787 ESTAT_ADD(rx_undersize_packets);
11788 ESTAT_ADD(rx_in_length_errors);
11789 ESTAT_ADD(rx_out_length_errors);
11790 ESTAT_ADD(rx_64_or_less_octet_packets);
11791 ESTAT_ADD(rx_65_to_127_octet_packets);
11792 ESTAT_ADD(rx_128_to_255_octet_packets);
11793 ESTAT_ADD(rx_256_to_511_octet_packets);
11794 ESTAT_ADD(rx_512_to_1023_octet_packets);
11795 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11796 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11797 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11798 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11799 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11801 ESTAT_ADD(tx_octets);
11802 ESTAT_ADD(tx_collisions);
11803 ESTAT_ADD(tx_xon_sent);
11804 ESTAT_ADD(tx_xoff_sent);
11805 ESTAT_ADD(tx_flow_control);
11806 ESTAT_ADD(tx_mac_errors);
11807 ESTAT_ADD(tx_single_collisions);
11808 ESTAT_ADD(tx_mult_collisions);
11809 ESTAT_ADD(tx_deferred);
11810 ESTAT_ADD(tx_excessive_collisions);
11811 ESTAT_ADD(tx_late_collisions);
11812 ESTAT_ADD(tx_collide_2times);
11813 ESTAT_ADD(tx_collide_3times);
11814 ESTAT_ADD(tx_collide_4times);
11815 ESTAT_ADD(tx_collide_5times);
11816 ESTAT_ADD(tx_collide_6times);
11817 ESTAT_ADD(tx_collide_7times);
11818 ESTAT_ADD(tx_collide_8times);
11819 ESTAT_ADD(tx_collide_9times);
11820 ESTAT_ADD(tx_collide_10times);
11821 ESTAT_ADD(tx_collide_11times);
11822 ESTAT_ADD(tx_collide_12times);
11823 ESTAT_ADD(tx_collide_13times);
11824 ESTAT_ADD(tx_collide_14times);
11825 ESTAT_ADD(tx_collide_15times);
11826 ESTAT_ADD(tx_ucast_packets);
11827 ESTAT_ADD(tx_mcast_packets);
11828 ESTAT_ADD(tx_bcast_packets);
11829 ESTAT_ADD(tx_carrier_sense_errors);
11830 ESTAT_ADD(tx_discards);
11831 ESTAT_ADD(tx_errors);
11833 ESTAT_ADD(dma_writeq_full);
11834 ESTAT_ADD(dma_write_prioq_full);
11835 ESTAT_ADD(rxbds_empty);
11836 ESTAT_ADD(rx_discards);
11837 ESTAT_ADD(rx_errors);
11838 ESTAT_ADD(rx_threshold_hit);
11840 ESTAT_ADD(dma_readq_full);
11841 ESTAT_ADD(dma_read_prioq_full);
11842 ESTAT_ADD(tx_comp_queue_full);
11844 ESTAT_ADD(ring_set_send_prod_index);
11845 ESTAT_ADD(ring_status_update);
11846 ESTAT_ADD(nic_irqs);
11847 ESTAT_ADD(nic_avoided_irqs);
11848 ESTAT_ADD(nic_tx_threshold_hit);
11850 ESTAT_ADD(mbuf_lwm_thresh_hit);
11853 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11855 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11856 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11858 stats->rx_packets = old_stats->rx_packets +
11859 get_stat64(&hw_stats->rx_ucast_packets) +
11860 get_stat64(&hw_stats->rx_mcast_packets) +
11861 get_stat64(&hw_stats->rx_bcast_packets);
11863 stats->tx_packets = old_stats->tx_packets +
11864 get_stat64(&hw_stats->tx_ucast_packets) +
11865 get_stat64(&hw_stats->tx_mcast_packets) +
11866 get_stat64(&hw_stats->tx_bcast_packets);
11868 stats->rx_bytes = old_stats->rx_bytes +
11869 get_stat64(&hw_stats->rx_octets);
11870 stats->tx_bytes = old_stats->tx_bytes +
11871 get_stat64(&hw_stats->tx_octets);
11873 stats->rx_errors = old_stats->rx_errors +
11874 get_stat64(&hw_stats->rx_errors);
11875 stats->tx_errors = old_stats->tx_errors +
11876 get_stat64(&hw_stats->tx_errors) +
11877 get_stat64(&hw_stats->tx_mac_errors) +
11878 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11879 get_stat64(&hw_stats->tx_discards);
11881 stats->multicast = old_stats->multicast +
11882 get_stat64(&hw_stats->rx_mcast_packets);
11883 stats->collisions = old_stats->collisions +
11884 get_stat64(&hw_stats->tx_collisions);
11886 stats->rx_length_errors = old_stats->rx_length_errors +
11887 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11888 get_stat64(&hw_stats->rx_undersize_packets);
11890 stats->rx_frame_errors = old_stats->rx_frame_errors +
11891 get_stat64(&hw_stats->rx_align_errors);
11892 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11893 get_stat64(&hw_stats->tx_discards);
11894 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11895 get_stat64(&hw_stats->tx_carrier_sense_errors);
11897 stats->rx_crc_errors = old_stats->rx_crc_errors +
11898 tg3_calc_crc_errors(tp);
11900 stats->rx_missed_errors = old_stats->rx_missed_errors +
11901 get_stat64(&hw_stats->rx_discards);
11903 stats->rx_dropped = tp->rx_dropped;
11904 stats->tx_dropped = tp->tx_dropped;
11907 static int tg3_get_regs_len(struct net_device *dev)
11909 return TG3_REG_BLK_SIZE;
11912 static void tg3_get_regs(struct net_device *dev,
11913 struct ethtool_regs *regs, void *_p)
11915 struct tg3 *tp = netdev_priv(dev);
11919 memset(_p, 0, TG3_REG_BLK_SIZE);
11921 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11924 tg3_full_lock(tp, 0);
11926 tg3_dump_legacy_regs(tp, (u32 *)_p);
11928 tg3_full_unlock(tp);
11931 static int tg3_get_eeprom_len(struct net_device *dev)
11933 struct tg3 *tp = netdev_priv(dev);
11935 return tp->nvram_size;
11938 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11940 struct tg3 *tp = netdev_priv(dev);
11941 int ret, cpmu_restore = 0;
11943 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11946 if (tg3_flag(tp, NO_NVRAM))
11949 offset = eeprom->offset;
11953 eeprom->magic = TG3_EEPROM_MAGIC;
11955 /* Override clock, link aware and link idle modes */
11956 if (tg3_flag(tp, CPMU_PRESENT)) {
11957 cpmu_val = tr32(TG3_CPMU_CTRL);
11958 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11959 CPMU_CTRL_LINK_IDLE_MODE)) {
11960 tw32(TG3_CPMU_CTRL, cpmu_val &
11961 ~(CPMU_CTRL_LINK_AWARE_MODE |
11962 CPMU_CTRL_LINK_IDLE_MODE));
11966 tg3_override_clk(tp);
11969 /* adjustments to start on required 4 byte boundary */
11970 b_offset = offset & 3;
11971 b_count = 4 - b_offset;
11972 if (b_count > len) {
11973 /* i.e. offset=1 len=2 */
11976 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11979 memcpy(data, ((char *)&val) + b_offset, b_count);
11982 eeprom->len += b_count;
11985 /* read bytes up to the last 4 byte boundary */
11986 pd = &data[eeprom->len];
11987 for (i = 0; i < (len - (len & 3)); i += 4) {
11988 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11995 memcpy(pd + i, &val, 4);
11996 if (need_resched()) {
11997 if (signal_pending(current)) {
12008 /* read last bytes not ending on 4 byte boundary */
12009 pd = &data[eeprom->len];
12011 b_offset = offset + len - b_count;
12012 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12015 memcpy(pd, &val, b_count);
12016 eeprom->len += b_count;
12021 /* Restore clock, link aware and link idle modes */
12022 tg3_restore_clk(tp);
12024 tw32(TG3_CPMU_CTRL, cpmu_val);
12029 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12031 struct tg3 *tp = netdev_priv(dev);
12033 u32 offset, len, b_offset, odd_len;
12035 __be32 start = 0, end;
12037 if (tg3_flag(tp, NO_NVRAM) ||
12038 eeprom->magic != TG3_EEPROM_MAGIC)
12041 offset = eeprom->offset;
12044 if ((b_offset = (offset & 3))) {
12045 /* adjustments to start on required 4 byte boundary */
12046 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12057 /* adjustments to end on required 4 byte boundary */
12059 len = (len + 3) & ~3;
12060 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12066 if (b_offset || odd_len) {
12067 buf = kmalloc(len, GFP_KERNEL);
12071 memcpy(buf, &start, 4);
12073 memcpy(buf+len-4, &end, 4);
12074 memcpy(buf + b_offset, data, eeprom->len);
12077 ret = tg3_nvram_write_block(tp, offset, len, buf);
12085 static int tg3_get_link_ksettings(struct net_device *dev,
12086 struct ethtool_link_ksettings *cmd)
12088 struct tg3 *tp = netdev_priv(dev);
12089 u32 supported, advertising;
12091 if (tg3_flag(tp, USE_PHYLIB)) {
12092 struct phy_device *phydev;
12093 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12095 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12096 return phy_ethtool_ksettings_get(phydev, cmd);
12099 supported = (SUPPORTED_Autoneg);
12101 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12102 supported |= (SUPPORTED_1000baseT_Half |
12103 SUPPORTED_1000baseT_Full);
12105 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12106 supported |= (SUPPORTED_100baseT_Half |
12107 SUPPORTED_100baseT_Full |
12108 SUPPORTED_10baseT_Half |
12109 SUPPORTED_10baseT_Full |
12111 cmd->base.port = PORT_TP;
12113 supported |= SUPPORTED_FIBRE;
12114 cmd->base.port = PORT_FIBRE;
12116 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
12119 advertising = tp->link_config.advertising;
12120 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12121 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12122 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12123 advertising |= ADVERTISED_Pause;
12125 advertising |= ADVERTISED_Pause |
12126 ADVERTISED_Asym_Pause;
12128 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12129 advertising |= ADVERTISED_Asym_Pause;
12132 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
12135 if (netif_running(dev) && tp->link_up) {
12136 cmd->base.speed = tp->link_config.active_speed;
12137 cmd->base.duplex = tp->link_config.active_duplex;
12138 ethtool_convert_legacy_u32_to_link_mode(
12139 cmd->link_modes.lp_advertising,
12140 tp->link_config.rmt_adv);
12142 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12143 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12144 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
12146 cmd->base.eth_tp_mdix = ETH_TP_MDI;
12149 cmd->base.speed = SPEED_UNKNOWN;
12150 cmd->base.duplex = DUPLEX_UNKNOWN;
12151 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
12153 cmd->base.phy_address = tp->phy_addr;
12154 cmd->base.autoneg = tp->link_config.autoneg;
12158 static int tg3_set_link_ksettings(struct net_device *dev,
12159 const struct ethtool_link_ksettings *cmd)
12161 struct tg3 *tp = netdev_priv(dev);
12162 u32 speed = cmd->base.speed;
12165 if (tg3_flag(tp, USE_PHYLIB)) {
12166 struct phy_device *phydev;
12167 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12169 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12170 return phy_ethtool_ksettings_set(phydev, cmd);
12173 if (cmd->base.autoneg != AUTONEG_ENABLE &&
12174 cmd->base.autoneg != AUTONEG_DISABLE)
12177 if (cmd->base.autoneg == AUTONEG_DISABLE &&
12178 cmd->base.duplex != DUPLEX_FULL &&
12179 cmd->base.duplex != DUPLEX_HALF)
12182 ethtool_convert_link_mode_to_legacy_u32(&advertising,
12183 cmd->link_modes.advertising);
12185 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12186 u32 mask = ADVERTISED_Autoneg |
12188 ADVERTISED_Asym_Pause;
12190 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12191 mask |= ADVERTISED_1000baseT_Half |
12192 ADVERTISED_1000baseT_Full;
12194 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12195 mask |= ADVERTISED_100baseT_Half |
12196 ADVERTISED_100baseT_Full |
12197 ADVERTISED_10baseT_Half |
12198 ADVERTISED_10baseT_Full |
12201 mask |= ADVERTISED_FIBRE;
12203 if (advertising & ~mask)
12206 mask &= (ADVERTISED_1000baseT_Half |
12207 ADVERTISED_1000baseT_Full |
12208 ADVERTISED_100baseT_Half |
12209 ADVERTISED_100baseT_Full |
12210 ADVERTISED_10baseT_Half |
12211 ADVERTISED_10baseT_Full);
12213 advertising &= mask;
12215 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12216 if (speed != SPEED_1000)
12219 if (cmd->base.duplex != DUPLEX_FULL)
12222 if (speed != SPEED_100 &&
12228 tg3_full_lock(tp, 0);
12230 tp->link_config.autoneg = cmd->base.autoneg;
12231 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12232 tp->link_config.advertising = (advertising |
12233 ADVERTISED_Autoneg);
12234 tp->link_config.speed = SPEED_UNKNOWN;
12235 tp->link_config.duplex = DUPLEX_UNKNOWN;
12237 tp->link_config.advertising = 0;
12238 tp->link_config.speed = speed;
12239 tp->link_config.duplex = cmd->base.duplex;
12242 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12244 tg3_warn_mgmt_link_flap(tp);
12246 if (netif_running(dev))
12247 tg3_setup_phy(tp, true);
12249 tg3_full_unlock(tp);
12254 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12256 struct tg3 *tp = netdev_priv(dev);
12258 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12259 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12260 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12261 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12264 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12266 struct tg3 *tp = netdev_priv(dev);
12268 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12269 wol->supported = WAKE_MAGIC;
12271 wol->supported = 0;
12273 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12274 wol->wolopts = WAKE_MAGIC;
12275 memset(&wol->sopass, 0, sizeof(wol->sopass));
12278 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12280 struct tg3 *tp = netdev_priv(dev);
12281 struct device *dp = &tp->pdev->dev;
12283 if (wol->wolopts & ~WAKE_MAGIC)
12285 if ((wol->wolopts & WAKE_MAGIC) &&
12286 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12289 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12291 if (device_may_wakeup(dp))
12292 tg3_flag_set(tp, WOL_ENABLE);
12294 tg3_flag_clear(tp, WOL_ENABLE);
12299 static u32 tg3_get_msglevel(struct net_device *dev)
12301 struct tg3 *tp = netdev_priv(dev);
12302 return tp->msg_enable;
12305 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12307 struct tg3 *tp = netdev_priv(dev);
12308 tp->msg_enable = value;
12311 static int tg3_nway_reset(struct net_device *dev)
12313 struct tg3 *tp = netdev_priv(dev);
12316 if (!netif_running(dev))
12319 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12322 tg3_warn_mgmt_link_flap(tp);
12324 if (tg3_flag(tp, USE_PHYLIB)) {
12325 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12327 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12331 spin_lock_bh(&tp->lock);
12333 tg3_readphy(tp, MII_BMCR, &bmcr);
12334 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12335 ((bmcr & BMCR_ANENABLE) ||
12336 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12337 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12341 spin_unlock_bh(&tp->lock);
12347 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12349 struct tg3 *tp = netdev_priv(dev);
12351 ering->rx_max_pending = tp->rx_std_ring_mask;
12352 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12353 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12355 ering->rx_jumbo_max_pending = 0;
12357 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12359 ering->rx_pending = tp->rx_pending;
12360 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12361 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12363 ering->rx_jumbo_pending = 0;
12365 ering->tx_pending = tp->napi[0].tx_pending;
12368 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12370 struct tg3 *tp = netdev_priv(dev);
12371 int i, irq_sync = 0, err = 0;
12373 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12374 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12375 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12376 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12377 (tg3_flag(tp, TSO_BUG) &&
12378 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12381 if (netif_running(dev)) {
12383 tg3_netif_stop(tp);
12387 tg3_full_lock(tp, irq_sync);
12389 tp->rx_pending = ering->rx_pending;
12391 if (tg3_flag(tp, MAX_RXPEND_64) &&
12392 tp->rx_pending > 63)
12393 tp->rx_pending = 63;
12395 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12396 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12398 for (i = 0; i < tp->irq_max; i++)
12399 tp->napi[i].tx_pending = ering->tx_pending;
12401 if (netif_running(dev)) {
12402 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12403 err = tg3_restart_hw(tp, false);
12405 tg3_netif_start(tp);
12408 tg3_full_unlock(tp);
12410 if (irq_sync && !err)
12416 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12418 struct tg3 *tp = netdev_priv(dev);
12420 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12422 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12423 epause->rx_pause = 1;
12425 epause->rx_pause = 0;
12427 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12428 epause->tx_pause = 1;
12430 epause->tx_pause = 0;
12433 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12435 struct tg3 *tp = netdev_priv(dev);
12438 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12439 tg3_warn_mgmt_link_flap(tp);
12441 if (tg3_flag(tp, USE_PHYLIB)) {
12443 struct phy_device *phydev;
12445 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12447 if (!(phydev->supported & SUPPORTED_Pause) ||
12448 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12449 (epause->rx_pause != epause->tx_pause)))
12452 tp->link_config.flowctrl = 0;
12453 if (epause->rx_pause) {
12454 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12456 if (epause->tx_pause) {
12457 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12458 newadv = ADVERTISED_Pause;
12460 newadv = ADVERTISED_Pause |
12461 ADVERTISED_Asym_Pause;
12462 } else if (epause->tx_pause) {
12463 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12464 newadv = ADVERTISED_Asym_Pause;
12468 if (epause->autoneg)
12469 tg3_flag_set(tp, PAUSE_AUTONEG);
12471 tg3_flag_clear(tp, PAUSE_AUTONEG);
12473 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12474 u32 oldadv = phydev->advertising &
12475 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12476 if (oldadv != newadv) {
12477 phydev->advertising &=
12478 ~(ADVERTISED_Pause |
12479 ADVERTISED_Asym_Pause);
12480 phydev->advertising |= newadv;
12481 if (phydev->autoneg) {
12483 * Always renegotiate the link to
12484 * inform our link partner of our
12485 * flow control settings, even if the
12486 * flow control is forced. Let
12487 * tg3_adjust_link() do the final
12488 * flow control setup.
12490 return phy_start_aneg(phydev);
12494 if (!epause->autoneg)
12495 tg3_setup_flow_control(tp, 0, 0);
12497 tp->link_config.advertising &=
12498 ~(ADVERTISED_Pause |
12499 ADVERTISED_Asym_Pause);
12500 tp->link_config.advertising |= newadv;
12505 if (netif_running(dev)) {
12506 tg3_netif_stop(tp);
12510 tg3_full_lock(tp, irq_sync);
12512 if (epause->autoneg)
12513 tg3_flag_set(tp, PAUSE_AUTONEG);
12515 tg3_flag_clear(tp, PAUSE_AUTONEG);
12516 if (epause->rx_pause)
12517 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12519 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12520 if (epause->tx_pause)
12521 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12523 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12525 if (netif_running(dev)) {
12526 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12527 err = tg3_restart_hw(tp, false);
12529 tg3_netif_start(tp);
12532 tg3_full_unlock(tp);
12535 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12540 static int tg3_get_sset_count(struct net_device *dev, int sset)
12544 return TG3_NUM_TEST;
12546 return TG3_NUM_STATS;
12548 return -EOPNOTSUPP;
12552 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12553 u32 *rules __always_unused)
12555 struct tg3 *tp = netdev_priv(dev);
12557 if (!tg3_flag(tp, SUPPORT_MSIX))
12558 return -EOPNOTSUPP;
12560 switch (info->cmd) {
12561 case ETHTOOL_GRXRINGS:
12562 if (netif_running(tp->dev))
12563 info->data = tp->rxq_cnt;
12565 info->data = num_online_cpus();
12566 if (info->data > TG3_RSS_MAX_NUM_QS)
12567 info->data = TG3_RSS_MAX_NUM_QS;
12573 return -EOPNOTSUPP;
12577 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12580 struct tg3 *tp = netdev_priv(dev);
12582 if (tg3_flag(tp, SUPPORT_MSIX))
12583 size = TG3_RSS_INDIR_TBL_SIZE;
12588 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12590 struct tg3 *tp = netdev_priv(dev);
12594 *hfunc = ETH_RSS_HASH_TOP;
12598 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12599 indir[i] = tp->rss_ind_tbl[i];
12604 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12607 struct tg3 *tp = netdev_priv(dev);
12610 /* We require at least one supported parameter to be changed and no
12611 * change in any of the unsupported parameters
12614 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12615 return -EOPNOTSUPP;
12620 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12621 tp->rss_ind_tbl[i] = indir[i];
12623 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12626 /* It is legal to write the indirection
12627 * table while the device is running.
12629 tg3_full_lock(tp, 0);
12630 tg3_rss_write_indir_tbl(tp);
12631 tg3_full_unlock(tp);
12636 static void tg3_get_channels(struct net_device *dev,
12637 struct ethtool_channels *channel)
12639 struct tg3 *tp = netdev_priv(dev);
12640 u32 deflt_qs = netif_get_num_default_rss_queues();
12642 channel->max_rx = tp->rxq_max;
12643 channel->max_tx = tp->txq_max;
12645 if (netif_running(dev)) {
12646 channel->rx_count = tp->rxq_cnt;
12647 channel->tx_count = tp->txq_cnt;
12650 channel->rx_count = tp->rxq_req;
12652 channel->rx_count = min(deflt_qs, tp->rxq_max);
12655 channel->tx_count = tp->txq_req;
12657 channel->tx_count = min(deflt_qs, tp->txq_max);
12661 static int tg3_set_channels(struct net_device *dev,
12662 struct ethtool_channels *channel)
12664 struct tg3 *tp = netdev_priv(dev);
12666 if (!tg3_flag(tp, SUPPORT_MSIX))
12667 return -EOPNOTSUPP;
12669 if (channel->rx_count > tp->rxq_max ||
12670 channel->tx_count > tp->txq_max)
12673 tp->rxq_req = channel->rx_count;
12674 tp->txq_req = channel->tx_count;
12676 if (!netif_running(dev))
12681 tg3_carrier_off(tp);
12683 tg3_start(tp, true, false, false);
12688 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12690 switch (stringset) {
12692 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12695 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12698 WARN_ON(1); /* we need a WARN() */
12703 static int tg3_set_phys_id(struct net_device *dev,
12704 enum ethtool_phys_id_state state)
12706 struct tg3 *tp = netdev_priv(dev);
12708 if (!netif_running(tp->dev))
12712 case ETHTOOL_ID_ACTIVE:
12713 return 1; /* cycle on/off once per second */
12715 case ETHTOOL_ID_ON:
12716 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12717 LED_CTRL_1000MBPS_ON |
12718 LED_CTRL_100MBPS_ON |
12719 LED_CTRL_10MBPS_ON |
12720 LED_CTRL_TRAFFIC_OVERRIDE |
12721 LED_CTRL_TRAFFIC_BLINK |
12722 LED_CTRL_TRAFFIC_LED);
12725 case ETHTOOL_ID_OFF:
12726 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12727 LED_CTRL_TRAFFIC_OVERRIDE);
12730 case ETHTOOL_ID_INACTIVE:
12731 tw32(MAC_LED_CTRL, tp->led_ctrl);
12738 static void tg3_get_ethtool_stats(struct net_device *dev,
12739 struct ethtool_stats *estats, u64 *tmp_stats)
12741 struct tg3 *tp = netdev_priv(dev);
12744 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12746 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12749 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12753 u32 offset = 0, len = 0;
12756 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12759 if (magic == TG3_EEPROM_MAGIC) {
12760 for (offset = TG3_NVM_DIR_START;
12761 offset < TG3_NVM_DIR_END;
12762 offset += TG3_NVM_DIRENT_SIZE) {
12763 if (tg3_nvram_read(tp, offset, &val))
12766 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12767 TG3_NVM_DIRTYPE_EXTVPD)
12771 if (offset != TG3_NVM_DIR_END) {
12772 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12773 if (tg3_nvram_read(tp, offset + 4, &offset))
12776 offset = tg3_nvram_logical_addr(tp, offset);
12780 if (!offset || !len) {
12781 offset = TG3_NVM_VPD_OFF;
12782 len = TG3_NVM_VPD_LEN;
12785 buf = kmalloc(len, GFP_KERNEL);
12789 if (magic == TG3_EEPROM_MAGIC) {
12790 for (i = 0; i < len; i += 4) {
12791 /* The data is in little-endian format in NVRAM.
12792 * Use the big-endian read routines to preserve
12793 * the byte order as it exists in NVRAM.
12795 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12801 unsigned int pos = 0;
12803 ptr = (u8 *)&buf[0];
12804 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12805 cnt = pci_read_vpd(tp->pdev, pos,
12807 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12825 #define NVRAM_TEST_SIZE 0x100
12826 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12827 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12828 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12829 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12830 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12831 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12832 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12833 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12835 static int tg3_test_nvram(struct tg3 *tp)
12837 u32 csum, magic, len;
12839 int i, j, k, err = 0, size;
12841 if (tg3_flag(tp, NO_NVRAM))
12844 if (tg3_nvram_read(tp, 0, &magic) != 0)
12847 if (magic == TG3_EEPROM_MAGIC)
12848 size = NVRAM_TEST_SIZE;
12849 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12850 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12851 TG3_EEPROM_SB_FORMAT_1) {
12852 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12853 case TG3_EEPROM_SB_REVISION_0:
12854 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12856 case TG3_EEPROM_SB_REVISION_2:
12857 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12859 case TG3_EEPROM_SB_REVISION_3:
12860 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12862 case TG3_EEPROM_SB_REVISION_4:
12863 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12865 case TG3_EEPROM_SB_REVISION_5:
12866 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12868 case TG3_EEPROM_SB_REVISION_6:
12869 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12876 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12877 size = NVRAM_SELFBOOT_HW_SIZE;
12881 buf = kmalloc(size, GFP_KERNEL);
12886 for (i = 0, j = 0; i < size; i += 4, j++) {
12887 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12894 /* Selfboot format */
12895 magic = be32_to_cpu(buf[0]);
12896 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12897 TG3_EEPROM_MAGIC_FW) {
12898 u8 *buf8 = (u8 *) buf, csum8 = 0;
12900 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12901 TG3_EEPROM_SB_REVISION_2) {
12902 /* For rev 2, the csum doesn't include the MBA. */
12903 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12905 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12908 for (i = 0; i < size; i++)
12921 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12922 TG3_EEPROM_MAGIC_HW) {
12923 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12924 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12925 u8 *buf8 = (u8 *) buf;
12927 /* Separate the parity bits and the data bytes. */
12928 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12929 if ((i == 0) || (i == 8)) {
12933 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12934 parity[k++] = buf8[i] & msk;
12936 } else if (i == 16) {
12940 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12941 parity[k++] = buf8[i] & msk;
12944 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12945 parity[k++] = buf8[i] & msk;
12948 data[j++] = buf8[i];
12952 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12953 u8 hw8 = hweight8(data[i]);
12955 if ((hw8 & 0x1) && parity[i])
12957 else if (!(hw8 & 0x1) && !parity[i])
12966 /* Bootstrap checksum at offset 0x10 */
12967 csum = calc_crc((unsigned char *) buf, 0x10);
12968 if (csum != le32_to_cpu(buf[0x10/4]))
12971 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12972 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12973 if (csum != le32_to_cpu(buf[0xfc/4]))
12978 buf = tg3_vpd_readblock(tp, &len);
12982 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12984 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12988 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12991 i += PCI_VPD_LRDT_TAG_SIZE;
12992 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12993 PCI_VPD_RO_KEYWORD_CHKSUM);
12997 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12999 for (i = 0; i <= j; i++)
13000 csum8 += ((u8 *)buf)[i];
13014 #define TG3_SERDES_TIMEOUT_SEC 2
13015 #define TG3_COPPER_TIMEOUT_SEC 6
13017 static int tg3_test_link(struct tg3 *tp)
13021 if (!netif_running(tp->dev))
13024 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13025 max = TG3_SERDES_TIMEOUT_SEC;
13027 max = TG3_COPPER_TIMEOUT_SEC;
13029 for (i = 0; i < max; i++) {
13033 if (msleep_interruptible(1000))
13040 /* Only test the commonly used registers */
13041 static int tg3_test_registers(struct tg3 *tp)
13043 int i, is_5705, is_5750;
13044 u32 offset, read_mask, write_mask, val, save_val, read_val;
13048 #define TG3_FL_5705 0x1
13049 #define TG3_FL_NOT_5705 0x2
13050 #define TG3_FL_NOT_5788 0x4
13051 #define TG3_FL_NOT_5750 0x8
13055 /* MAC Control Registers */
13056 { MAC_MODE, TG3_FL_NOT_5705,
13057 0x00000000, 0x00ef6f8c },
13058 { MAC_MODE, TG3_FL_5705,
13059 0x00000000, 0x01ef6b8c },
13060 { MAC_STATUS, TG3_FL_NOT_5705,
13061 0x03800107, 0x00000000 },
13062 { MAC_STATUS, TG3_FL_5705,
13063 0x03800100, 0x00000000 },
13064 { MAC_ADDR_0_HIGH, 0x0000,
13065 0x00000000, 0x0000ffff },
13066 { MAC_ADDR_0_LOW, 0x0000,
13067 0x00000000, 0xffffffff },
13068 { MAC_RX_MTU_SIZE, 0x0000,
13069 0x00000000, 0x0000ffff },
13070 { MAC_TX_MODE, 0x0000,
13071 0x00000000, 0x00000070 },
13072 { MAC_TX_LENGTHS, 0x0000,
13073 0x00000000, 0x00003fff },
13074 { MAC_RX_MODE, TG3_FL_NOT_5705,
13075 0x00000000, 0x000007fc },
13076 { MAC_RX_MODE, TG3_FL_5705,
13077 0x00000000, 0x000007dc },
13078 { MAC_HASH_REG_0, 0x0000,
13079 0x00000000, 0xffffffff },
13080 { MAC_HASH_REG_1, 0x0000,
13081 0x00000000, 0xffffffff },
13082 { MAC_HASH_REG_2, 0x0000,
13083 0x00000000, 0xffffffff },
13084 { MAC_HASH_REG_3, 0x0000,
13085 0x00000000, 0xffffffff },
13087 /* Receive Data and Receive BD Initiator Control Registers. */
13088 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13089 0x00000000, 0xffffffff },
13090 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13091 0x00000000, 0xffffffff },
13092 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13093 0x00000000, 0x00000003 },
13094 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13095 0x00000000, 0xffffffff },
13096 { RCVDBDI_STD_BD+0, 0x0000,
13097 0x00000000, 0xffffffff },
13098 { RCVDBDI_STD_BD+4, 0x0000,
13099 0x00000000, 0xffffffff },
13100 { RCVDBDI_STD_BD+8, 0x0000,
13101 0x00000000, 0xffff0002 },
13102 { RCVDBDI_STD_BD+0xc, 0x0000,
13103 0x00000000, 0xffffffff },
13105 /* Receive BD Initiator Control Registers. */
13106 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13107 0x00000000, 0xffffffff },
13108 { RCVBDI_STD_THRESH, TG3_FL_5705,
13109 0x00000000, 0x000003ff },
13110 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13111 0x00000000, 0xffffffff },
13113 /* Host Coalescing Control Registers. */
13114 { HOSTCC_MODE, TG3_FL_NOT_5705,
13115 0x00000000, 0x00000004 },
13116 { HOSTCC_MODE, TG3_FL_5705,
13117 0x00000000, 0x000000f6 },
13118 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13119 0x00000000, 0xffffffff },
13120 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13121 0x00000000, 0x000003ff },
13122 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13123 0x00000000, 0xffffffff },
13124 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13125 0x00000000, 0x000003ff },
13126 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13127 0x00000000, 0xffffffff },
13128 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13129 0x00000000, 0x000000ff },
13130 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13131 0x00000000, 0xffffffff },
13132 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13133 0x00000000, 0x000000ff },
13134 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13135 0x00000000, 0xffffffff },
13136 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13137 0x00000000, 0xffffffff },
13138 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13139 0x00000000, 0xffffffff },
13140 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13141 0x00000000, 0x000000ff },
13142 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13143 0x00000000, 0xffffffff },
13144 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13145 0x00000000, 0x000000ff },
13146 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13147 0x00000000, 0xffffffff },
13148 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13149 0x00000000, 0xffffffff },
13150 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13151 0x00000000, 0xffffffff },
13152 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13153 0x00000000, 0xffffffff },
13154 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13155 0x00000000, 0xffffffff },
13156 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13157 0xffffffff, 0x00000000 },
13158 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13159 0xffffffff, 0x00000000 },
13161 /* Buffer Manager Control Registers. */
13162 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13163 0x00000000, 0x007fff80 },
13164 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13165 0x00000000, 0x007fffff },
13166 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13167 0x00000000, 0x0000003f },
13168 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13169 0x00000000, 0x000001ff },
13170 { BUFMGR_MB_HIGH_WATER, 0x0000,
13171 0x00000000, 0x000001ff },
13172 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13173 0xffffffff, 0x00000000 },
13174 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13175 0xffffffff, 0x00000000 },
13177 /* Mailbox Registers */
13178 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13179 0x00000000, 0x000001ff },
13180 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13181 0x00000000, 0x000001ff },
13182 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13183 0x00000000, 0x000007ff },
13184 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13185 0x00000000, 0x000001ff },
13187 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13190 is_5705 = is_5750 = 0;
13191 if (tg3_flag(tp, 5705_PLUS)) {
13193 if (tg3_flag(tp, 5750_PLUS))
13197 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13198 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13201 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13204 if (tg3_flag(tp, IS_5788) &&
13205 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13208 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13211 offset = (u32) reg_tbl[i].offset;
13212 read_mask = reg_tbl[i].read_mask;
13213 write_mask = reg_tbl[i].write_mask;
13215 /* Save the original register content */
13216 save_val = tr32(offset);
13218 /* Determine the read-only value. */
13219 read_val = save_val & read_mask;
13221 /* Write zero to the register, then make sure the read-only bits
13222 * are not changed and the read/write bits are all zeros.
13226 val = tr32(offset);
13228 /* Test the read-only and read/write bits. */
13229 if (((val & read_mask) != read_val) || (val & write_mask))
13232 /* Write ones to all the bits defined by RdMask and WrMask, then
13233 * make sure the read-only bits are not changed and the
13234 * read/write bits are all ones.
13236 tw32(offset, read_mask | write_mask);
13238 val = tr32(offset);
13240 /* Test the read-only bits. */
13241 if ((val & read_mask) != read_val)
13244 /* Test the read/write bits. */
13245 if ((val & write_mask) != write_mask)
13248 tw32(offset, save_val);
13254 if (netif_msg_hw(tp))
13255 netdev_err(tp->dev,
13256 "Register test failed at offset %x\n", offset);
13257 tw32(offset, save_val);
13261 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13263 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13267 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13268 for (j = 0; j < len; j += 4) {
13271 tg3_write_mem(tp, offset + j, test_pattern[i]);
13272 tg3_read_mem(tp, offset + j, &val);
13273 if (val != test_pattern[i])
13280 static int tg3_test_memory(struct tg3 *tp)
13282 static struct mem_entry {
13285 } mem_tbl_570x[] = {
13286 { 0x00000000, 0x00b50},
13287 { 0x00002000, 0x1c000},
13288 { 0xffffffff, 0x00000}
13289 }, mem_tbl_5705[] = {
13290 { 0x00000100, 0x0000c},
13291 { 0x00000200, 0x00008},
13292 { 0x00004000, 0x00800},
13293 { 0x00006000, 0x01000},
13294 { 0x00008000, 0x02000},
13295 { 0x00010000, 0x0e000},
13296 { 0xffffffff, 0x00000}
13297 }, mem_tbl_5755[] = {
13298 { 0x00000200, 0x00008},
13299 { 0x00004000, 0x00800},
13300 { 0x00006000, 0x00800},
13301 { 0x00008000, 0x02000},
13302 { 0x00010000, 0x0c000},
13303 { 0xffffffff, 0x00000}
13304 }, mem_tbl_5906[] = {
13305 { 0x00000200, 0x00008},
13306 { 0x00004000, 0x00400},
13307 { 0x00006000, 0x00400},
13308 { 0x00008000, 0x01000},
13309 { 0x00010000, 0x01000},
13310 { 0xffffffff, 0x00000}
13311 }, mem_tbl_5717[] = {
13312 { 0x00000200, 0x00008},
13313 { 0x00010000, 0x0a000},
13314 { 0x00020000, 0x13c00},
13315 { 0xffffffff, 0x00000}
13316 }, mem_tbl_57765[] = {
13317 { 0x00000200, 0x00008},
13318 { 0x00004000, 0x00800},
13319 { 0x00006000, 0x09800},
13320 { 0x00010000, 0x0a000},
13321 { 0xffffffff, 0x00000}
13323 struct mem_entry *mem_tbl;
13327 if (tg3_flag(tp, 5717_PLUS))
13328 mem_tbl = mem_tbl_5717;
13329 else if (tg3_flag(tp, 57765_CLASS) ||
13330 tg3_asic_rev(tp) == ASIC_REV_5762)
13331 mem_tbl = mem_tbl_57765;
13332 else if (tg3_flag(tp, 5755_PLUS))
13333 mem_tbl = mem_tbl_5755;
13334 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13335 mem_tbl = mem_tbl_5906;
13336 else if (tg3_flag(tp, 5705_PLUS))
13337 mem_tbl = mem_tbl_5705;
13339 mem_tbl = mem_tbl_570x;
13341 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13342 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13350 #define TG3_TSO_MSS 500
13352 #define TG3_TSO_IP_HDR_LEN 20
13353 #define TG3_TSO_TCP_HDR_LEN 20
13354 #define TG3_TSO_TCP_OPT_LEN 12
13356 static const u8 tg3_tso_header[] = {
13358 0x45, 0x00, 0x00, 0x00,
13359 0x00, 0x00, 0x40, 0x00,
13360 0x40, 0x06, 0x00, 0x00,
13361 0x0a, 0x00, 0x00, 0x01,
13362 0x0a, 0x00, 0x00, 0x02,
13363 0x0d, 0x00, 0xe0, 0x00,
13364 0x00, 0x00, 0x01, 0x00,
13365 0x00, 0x00, 0x02, 0x00,
13366 0x80, 0x10, 0x10, 0x00,
13367 0x14, 0x09, 0x00, 0x00,
13368 0x01, 0x01, 0x08, 0x0a,
13369 0x11, 0x11, 0x11, 0x11,
13370 0x11, 0x11, 0x11, 0x11,
13373 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13375 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13376 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13378 struct sk_buff *skb;
13379 u8 *tx_data, *rx_data;
13381 int num_pkts, tx_len, rx_len, i, err;
13382 struct tg3_rx_buffer_desc *desc;
13383 struct tg3_napi *tnapi, *rnapi;
13384 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13386 tnapi = &tp->napi[0];
13387 rnapi = &tp->napi[0];
13388 if (tp->irq_cnt > 1) {
13389 if (tg3_flag(tp, ENABLE_RSS))
13390 rnapi = &tp->napi[1];
13391 if (tg3_flag(tp, ENABLE_TSS))
13392 tnapi = &tp->napi[1];
13394 coal_now = tnapi->coal_now | rnapi->coal_now;
13399 skb = netdev_alloc_skb(tp->dev, tx_len);
13403 tx_data = skb_put(skb, tx_len);
13404 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13405 memset(tx_data + ETH_ALEN, 0x0, 8);
13407 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13409 if (tso_loopback) {
13410 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13412 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13413 TG3_TSO_TCP_OPT_LEN;
13415 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13416 sizeof(tg3_tso_header));
13419 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13420 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13422 /* Set the total length field in the IP header */
13423 iph->tot_len = htons((u16)(mss + hdr_len));
13425 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13426 TXD_FLAG_CPU_POST_DMA);
13428 if (tg3_flag(tp, HW_TSO_1) ||
13429 tg3_flag(tp, HW_TSO_2) ||
13430 tg3_flag(tp, HW_TSO_3)) {
13432 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13433 th = (struct tcphdr *)&tx_data[val];
13436 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13438 if (tg3_flag(tp, HW_TSO_3)) {
13439 mss |= (hdr_len & 0xc) << 12;
13440 if (hdr_len & 0x10)
13441 base_flags |= 0x00000010;
13442 base_flags |= (hdr_len & 0x3e0) << 5;
13443 } else if (tg3_flag(tp, HW_TSO_2))
13444 mss |= hdr_len << 9;
13445 else if (tg3_flag(tp, HW_TSO_1) ||
13446 tg3_asic_rev(tp) == ASIC_REV_5705) {
13447 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13449 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13452 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13455 data_off = ETH_HLEN;
13457 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13458 tx_len > VLAN_ETH_FRAME_LEN)
13459 base_flags |= TXD_FLAG_JMB_PKT;
13462 for (i = data_off; i < tx_len; i++)
13463 tx_data[i] = (u8) (i & 0xff);
13465 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13466 if (pci_dma_mapping_error(tp->pdev, map)) {
13467 dev_kfree_skb(skb);
13471 val = tnapi->tx_prod;
13472 tnapi->tx_buffers[val].skb = skb;
13473 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13475 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13480 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13482 budget = tg3_tx_avail(tnapi);
13483 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13484 base_flags | TXD_FLAG_END, mss, 0)) {
13485 tnapi->tx_buffers[val].skb = NULL;
13486 dev_kfree_skb(skb);
13492 /* Sync BD data before updating mailbox */
13495 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13496 tr32_mailbox(tnapi->prodmbox);
13500 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13501 for (i = 0; i < 35; i++) {
13502 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13507 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13508 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13509 if ((tx_idx == tnapi->tx_prod) &&
13510 (rx_idx == (rx_start_idx + num_pkts)))
13514 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13515 dev_kfree_skb(skb);
13517 if (tx_idx != tnapi->tx_prod)
13520 if (rx_idx != rx_start_idx + num_pkts)
13524 while (rx_idx != rx_start_idx) {
13525 desc = &rnapi->rx_rcb[rx_start_idx++];
13526 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13527 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13529 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13530 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13533 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13536 if (!tso_loopback) {
13537 if (rx_len != tx_len)
13540 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13541 if (opaque_key != RXD_OPAQUE_RING_STD)
13544 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13547 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13548 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13549 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13553 if (opaque_key == RXD_OPAQUE_RING_STD) {
13554 rx_data = tpr->rx_std_buffers[desc_idx].data;
13555 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13557 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13558 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13559 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13564 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13565 PCI_DMA_FROMDEVICE);
13567 rx_data += TG3_RX_OFFSET(tp);
13568 for (i = data_off; i < rx_len; i++, val++) {
13569 if (*(rx_data + i) != (u8) (val & 0xff))
13576 /* tg3_free_rings will unmap and free the rx_data */
13581 #define TG3_STD_LOOPBACK_FAILED 1
13582 #define TG3_JMB_LOOPBACK_FAILED 2
13583 #define TG3_TSO_LOOPBACK_FAILED 4
13584 #define TG3_LOOPBACK_FAILED \
13585 (TG3_STD_LOOPBACK_FAILED | \
13586 TG3_JMB_LOOPBACK_FAILED | \
13587 TG3_TSO_LOOPBACK_FAILED)
13589 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13593 u32 jmb_pkt_sz = 9000;
13596 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13598 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13599 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13601 if (!netif_running(tp->dev)) {
13602 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13603 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13605 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13609 err = tg3_reset_hw(tp, true);
13611 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13612 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13614 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13618 if (tg3_flag(tp, ENABLE_RSS)) {
13621 /* Reroute all rx packets to the 1st queue */
13622 for (i = MAC_RSS_INDIR_TBL_0;
13623 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13627 /* HW errata - mac loopback fails in some cases on 5780.
13628 * Normal traffic and PHY loopback are not affected by
13629 * errata. Also, the MAC loopback test is deprecated for
13630 * all newer ASIC revisions.
13632 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13633 !tg3_flag(tp, CPMU_PRESENT)) {
13634 tg3_mac_loopback(tp, true);
13636 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13637 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13639 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13640 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13641 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13643 tg3_mac_loopback(tp, false);
13646 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13647 !tg3_flag(tp, USE_PHYLIB)) {
13650 tg3_phy_lpbk_set(tp, 0, false);
13652 /* Wait for link */
13653 for (i = 0; i < 100; i++) {
13654 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13659 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13660 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13661 if (tg3_flag(tp, TSO_CAPABLE) &&
13662 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13663 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13664 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13665 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13666 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13669 tg3_phy_lpbk_set(tp, 0, true);
13671 /* All link indications report up, but the hardware
13672 * isn't really ready for about 20 msec. Double it
13677 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13678 data[TG3_EXT_LOOPB_TEST] |=
13679 TG3_STD_LOOPBACK_FAILED;
13680 if (tg3_flag(tp, TSO_CAPABLE) &&
13681 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13682 data[TG3_EXT_LOOPB_TEST] |=
13683 TG3_TSO_LOOPBACK_FAILED;
13684 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13685 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13686 data[TG3_EXT_LOOPB_TEST] |=
13687 TG3_JMB_LOOPBACK_FAILED;
13690 /* Re-enable gphy autopowerdown. */
13691 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13692 tg3_phy_toggle_apd(tp, true);
13695 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13696 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13699 tp->phy_flags |= eee_cap;
13704 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13707 struct tg3 *tp = netdev_priv(dev);
13708 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13710 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13711 if (tg3_power_up(tp)) {
13712 etest->flags |= ETH_TEST_FL_FAILED;
13713 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13716 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13719 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13721 if (tg3_test_nvram(tp) != 0) {
13722 etest->flags |= ETH_TEST_FL_FAILED;
13723 data[TG3_NVRAM_TEST] = 1;
13725 if (!doextlpbk && tg3_test_link(tp)) {
13726 etest->flags |= ETH_TEST_FL_FAILED;
13727 data[TG3_LINK_TEST] = 1;
13729 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13730 int err, err2 = 0, irq_sync = 0;
13732 if (netif_running(dev)) {
13734 tg3_netif_stop(tp);
13738 tg3_full_lock(tp, irq_sync);
13739 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13740 err = tg3_nvram_lock(tp);
13741 tg3_halt_cpu(tp, RX_CPU_BASE);
13742 if (!tg3_flag(tp, 5705_PLUS))
13743 tg3_halt_cpu(tp, TX_CPU_BASE);
13745 tg3_nvram_unlock(tp);
13747 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13750 if (tg3_test_registers(tp) != 0) {
13751 etest->flags |= ETH_TEST_FL_FAILED;
13752 data[TG3_REGISTER_TEST] = 1;
13755 if (tg3_test_memory(tp) != 0) {
13756 etest->flags |= ETH_TEST_FL_FAILED;
13757 data[TG3_MEMORY_TEST] = 1;
13761 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13763 if (tg3_test_loopback(tp, data, doextlpbk))
13764 etest->flags |= ETH_TEST_FL_FAILED;
13766 tg3_full_unlock(tp);
13768 if (tg3_test_interrupt(tp) != 0) {
13769 etest->flags |= ETH_TEST_FL_FAILED;
13770 data[TG3_INTERRUPT_TEST] = 1;
13773 tg3_full_lock(tp, 0);
13775 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13776 if (netif_running(dev)) {
13777 tg3_flag_set(tp, INIT_COMPLETE);
13778 err2 = tg3_restart_hw(tp, true);
13780 tg3_netif_start(tp);
13783 tg3_full_unlock(tp);
13785 if (irq_sync && !err2)
13788 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13789 tg3_power_down_prepare(tp);
13793 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13795 struct tg3 *tp = netdev_priv(dev);
13796 struct hwtstamp_config stmpconf;
13798 if (!tg3_flag(tp, PTP_CAPABLE))
13799 return -EOPNOTSUPP;
13801 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13804 if (stmpconf.flags)
13807 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13808 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13811 switch (stmpconf.rx_filter) {
13812 case HWTSTAMP_FILTER_NONE:
13815 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13816 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13817 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13819 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13820 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13821 TG3_RX_PTP_CTL_SYNC_EVNT;
13823 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13824 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13825 TG3_RX_PTP_CTL_DELAY_REQ;
13827 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13828 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13829 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13831 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13832 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13833 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13835 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13836 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13837 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13839 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13840 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13841 TG3_RX_PTP_CTL_SYNC_EVNT;
13843 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13844 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13845 TG3_RX_PTP_CTL_SYNC_EVNT;
13847 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13848 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13849 TG3_RX_PTP_CTL_SYNC_EVNT;
13851 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13852 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13853 TG3_RX_PTP_CTL_DELAY_REQ;
13855 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13856 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13857 TG3_RX_PTP_CTL_DELAY_REQ;
13859 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13860 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13861 TG3_RX_PTP_CTL_DELAY_REQ;
13867 if (netif_running(dev) && tp->rxptpctl)
13868 tw32(TG3_RX_PTP_CTL,
13869 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13871 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13872 tg3_flag_set(tp, TX_TSTAMP_EN);
13874 tg3_flag_clear(tp, TX_TSTAMP_EN);
13876 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13880 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13882 struct tg3 *tp = netdev_priv(dev);
13883 struct hwtstamp_config stmpconf;
13885 if (!tg3_flag(tp, PTP_CAPABLE))
13886 return -EOPNOTSUPP;
13888 stmpconf.flags = 0;
13889 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13890 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13892 switch (tp->rxptpctl) {
13894 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13896 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13897 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13899 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13900 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13902 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13903 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13905 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13906 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13908 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13909 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13911 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13912 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13914 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13915 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13917 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13918 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13920 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13921 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13923 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13924 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13926 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13927 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13929 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13930 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13937 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13941 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13943 struct mii_ioctl_data *data = if_mii(ifr);
13944 struct tg3 *tp = netdev_priv(dev);
13947 if (tg3_flag(tp, USE_PHYLIB)) {
13948 struct phy_device *phydev;
13949 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13951 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
13952 return phy_mii_ioctl(phydev, ifr, cmd);
13957 data->phy_id = tp->phy_addr;
13960 case SIOCGMIIREG: {
13963 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13964 break; /* We have no PHY */
13966 if (!netif_running(dev))
13969 spin_lock_bh(&tp->lock);
13970 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13971 data->reg_num & 0x1f, &mii_regval);
13972 spin_unlock_bh(&tp->lock);
13974 data->val_out = mii_regval;
13980 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13981 break; /* We have no PHY */
13983 if (!netif_running(dev))
13986 spin_lock_bh(&tp->lock);
13987 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13988 data->reg_num & 0x1f, data->val_in);
13989 spin_unlock_bh(&tp->lock);
13993 case SIOCSHWTSTAMP:
13994 return tg3_hwtstamp_set(dev, ifr);
13996 case SIOCGHWTSTAMP:
13997 return tg3_hwtstamp_get(dev, ifr);
14003 return -EOPNOTSUPP;
14006 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14008 struct tg3 *tp = netdev_priv(dev);
14010 memcpy(ec, &tp->coal, sizeof(*ec));
14014 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14016 struct tg3 *tp = netdev_priv(dev);
14017 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
14018 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14020 if (!tg3_flag(tp, 5705_PLUS)) {
14021 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14022 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14023 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14024 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14027 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14028 (!ec->rx_coalesce_usecs) ||
14029 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14030 (!ec->tx_coalesce_usecs) ||
14031 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14032 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14033 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14034 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14035 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14036 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14037 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14038 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14041 /* Only copy relevant parameters, ignore all others. */
14042 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14043 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14044 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14045 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14046 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14047 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14048 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14049 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14050 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14052 if (netif_running(dev)) {
14053 tg3_full_lock(tp, 0);
14054 __tg3_set_coalesce(tp, &tp->coal);
14055 tg3_full_unlock(tp);
14060 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14062 struct tg3 *tp = netdev_priv(dev);
14064 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14065 netdev_warn(tp->dev, "Board does not support EEE!\n");
14066 return -EOPNOTSUPP;
14069 if (edata->advertised != tp->eee.advertised) {
14070 netdev_warn(tp->dev,
14071 "Direct manipulation of EEE advertisement is not supported\n");
14075 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14076 netdev_warn(tp->dev,
14077 "Maximal Tx Lpi timer supported is %#x(u)\n",
14078 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14084 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14085 tg3_warn_mgmt_link_flap(tp);
14087 if (netif_running(tp->dev)) {
14088 tg3_full_lock(tp, 0);
14091 tg3_full_unlock(tp);
14097 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14099 struct tg3 *tp = netdev_priv(dev);
14101 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14102 netdev_warn(tp->dev,
14103 "Board does not support EEE!\n");
14104 return -EOPNOTSUPP;
14111 static const struct ethtool_ops tg3_ethtool_ops = {
14112 .get_drvinfo = tg3_get_drvinfo,
14113 .get_regs_len = tg3_get_regs_len,
14114 .get_regs = tg3_get_regs,
14115 .get_wol = tg3_get_wol,
14116 .set_wol = tg3_set_wol,
14117 .get_msglevel = tg3_get_msglevel,
14118 .set_msglevel = tg3_set_msglevel,
14119 .nway_reset = tg3_nway_reset,
14120 .get_link = ethtool_op_get_link,
14121 .get_eeprom_len = tg3_get_eeprom_len,
14122 .get_eeprom = tg3_get_eeprom,
14123 .set_eeprom = tg3_set_eeprom,
14124 .get_ringparam = tg3_get_ringparam,
14125 .set_ringparam = tg3_set_ringparam,
14126 .get_pauseparam = tg3_get_pauseparam,
14127 .set_pauseparam = tg3_set_pauseparam,
14128 .self_test = tg3_self_test,
14129 .get_strings = tg3_get_strings,
14130 .set_phys_id = tg3_set_phys_id,
14131 .get_ethtool_stats = tg3_get_ethtool_stats,
14132 .get_coalesce = tg3_get_coalesce,
14133 .set_coalesce = tg3_set_coalesce,
14134 .get_sset_count = tg3_get_sset_count,
14135 .get_rxnfc = tg3_get_rxnfc,
14136 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14137 .get_rxfh = tg3_get_rxfh,
14138 .set_rxfh = tg3_set_rxfh,
14139 .get_channels = tg3_get_channels,
14140 .set_channels = tg3_set_channels,
14141 .get_ts_info = tg3_get_ts_info,
14142 .get_eee = tg3_get_eee,
14143 .set_eee = tg3_set_eee,
14144 .get_link_ksettings = tg3_get_link_ksettings,
14145 .set_link_ksettings = tg3_set_link_ksettings,
14148 static void tg3_get_stats64(struct net_device *dev,
14149 struct rtnl_link_stats64 *stats)
14151 struct tg3 *tp = netdev_priv(dev);
14153 spin_lock_bh(&tp->lock);
14154 if (!tp->hw_stats) {
14155 *stats = tp->net_stats_prev;
14156 spin_unlock_bh(&tp->lock);
14160 tg3_get_nstats(tp, stats);
14161 spin_unlock_bh(&tp->lock);
14164 static void tg3_set_rx_mode(struct net_device *dev)
14166 struct tg3 *tp = netdev_priv(dev);
14168 if (!netif_running(dev))
14171 tg3_full_lock(tp, 0);
14172 __tg3_set_rx_mode(dev);
14173 tg3_full_unlock(tp);
14176 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14179 dev->mtu = new_mtu;
14181 if (new_mtu > ETH_DATA_LEN) {
14182 if (tg3_flag(tp, 5780_CLASS)) {
14183 netdev_update_features(dev);
14184 tg3_flag_clear(tp, TSO_CAPABLE);
14186 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14189 if (tg3_flag(tp, 5780_CLASS)) {
14190 tg3_flag_set(tp, TSO_CAPABLE);
14191 netdev_update_features(dev);
14193 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14197 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14199 struct tg3 *tp = netdev_priv(dev);
14201 bool reset_phy = false;
14203 if (!netif_running(dev)) {
14204 /* We'll just catch it later when the
14207 tg3_set_mtu(dev, tp, new_mtu);
14213 tg3_netif_stop(tp);
14215 tg3_set_mtu(dev, tp, new_mtu);
14217 tg3_full_lock(tp, 1);
14219 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14221 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14222 * breaks all requests to 256 bytes.
14224 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14227 err = tg3_restart_hw(tp, reset_phy);
14230 tg3_netif_start(tp);
14232 tg3_full_unlock(tp);
14240 static const struct net_device_ops tg3_netdev_ops = {
14241 .ndo_open = tg3_open,
14242 .ndo_stop = tg3_close,
14243 .ndo_start_xmit = tg3_start_xmit,
14244 .ndo_get_stats64 = tg3_get_stats64,
14245 .ndo_validate_addr = eth_validate_addr,
14246 .ndo_set_rx_mode = tg3_set_rx_mode,
14247 .ndo_set_mac_address = tg3_set_mac_addr,
14248 .ndo_do_ioctl = tg3_ioctl,
14249 .ndo_tx_timeout = tg3_tx_timeout,
14250 .ndo_change_mtu = tg3_change_mtu,
14251 .ndo_fix_features = tg3_fix_features,
14252 .ndo_set_features = tg3_set_features,
14253 #ifdef CONFIG_NET_POLL_CONTROLLER
14254 .ndo_poll_controller = tg3_poll_controller,
14258 static void tg3_get_eeprom_size(struct tg3 *tp)
14260 u32 cursize, val, magic;
14262 tp->nvram_size = EEPROM_CHIP_SIZE;
14264 if (tg3_nvram_read(tp, 0, &magic) != 0)
14267 if ((magic != TG3_EEPROM_MAGIC) &&
14268 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14269 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14273 * Size the chip by reading offsets at increasing powers of two.
14274 * When we encounter our validation signature, we know the addressing
14275 * has wrapped around, and thus have our chip size.
14279 while (cursize < tp->nvram_size) {
14280 if (tg3_nvram_read(tp, cursize, &val) != 0)
14289 tp->nvram_size = cursize;
14292 static void tg3_get_nvram_size(struct tg3 *tp)
14296 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14299 /* Selfboot format */
14300 if (val != TG3_EEPROM_MAGIC) {
14301 tg3_get_eeprom_size(tp);
14305 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14307 /* This is confusing. We want to operate on the
14308 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14309 * call will read from NVRAM and byteswap the data
14310 * according to the byteswapping settings for all
14311 * other register accesses. This ensures the data we
14312 * want will always reside in the lower 16-bits.
14313 * However, the data in NVRAM is in LE format, which
14314 * means the data from the NVRAM read will always be
14315 * opposite the endianness of the CPU. The 16-bit
14316 * byteswap then brings the data to CPU endianness.
14318 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14322 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14325 static void tg3_get_nvram_info(struct tg3 *tp)
14329 nvcfg1 = tr32(NVRAM_CFG1);
14330 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14331 tg3_flag_set(tp, FLASH);
14333 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14334 tw32(NVRAM_CFG1, nvcfg1);
14337 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14338 tg3_flag(tp, 5780_CLASS)) {
14339 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14340 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14341 tp->nvram_jedecnum = JEDEC_ATMEL;
14342 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14343 tg3_flag_set(tp, NVRAM_BUFFERED);
14345 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14346 tp->nvram_jedecnum = JEDEC_ATMEL;
14347 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14349 case FLASH_VENDOR_ATMEL_EEPROM:
14350 tp->nvram_jedecnum = JEDEC_ATMEL;
14351 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14352 tg3_flag_set(tp, NVRAM_BUFFERED);
14354 case FLASH_VENDOR_ST:
14355 tp->nvram_jedecnum = JEDEC_ST;
14356 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14357 tg3_flag_set(tp, NVRAM_BUFFERED);
14359 case FLASH_VENDOR_SAIFUN:
14360 tp->nvram_jedecnum = JEDEC_SAIFUN;
14361 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14363 case FLASH_VENDOR_SST_SMALL:
14364 case FLASH_VENDOR_SST_LARGE:
14365 tp->nvram_jedecnum = JEDEC_SST;
14366 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14370 tp->nvram_jedecnum = JEDEC_ATMEL;
14371 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14372 tg3_flag_set(tp, NVRAM_BUFFERED);
14376 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14378 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14379 case FLASH_5752PAGE_SIZE_256:
14380 tp->nvram_pagesize = 256;
14382 case FLASH_5752PAGE_SIZE_512:
14383 tp->nvram_pagesize = 512;
14385 case FLASH_5752PAGE_SIZE_1K:
14386 tp->nvram_pagesize = 1024;
14388 case FLASH_5752PAGE_SIZE_2K:
14389 tp->nvram_pagesize = 2048;
14391 case FLASH_5752PAGE_SIZE_4K:
14392 tp->nvram_pagesize = 4096;
14394 case FLASH_5752PAGE_SIZE_264:
14395 tp->nvram_pagesize = 264;
14397 case FLASH_5752PAGE_SIZE_528:
14398 tp->nvram_pagesize = 528;
14403 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14407 nvcfg1 = tr32(NVRAM_CFG1);
14409 /* NVRAM protection for TPM */
14410 if (nvcfg1 & (1 << 27))
14411 tg3_flag_set(tp, PROTECTED_NVRAM);
14413 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14414 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14415 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14416 tp->nvram_jedecnum = JEDEC_ATMEL;
14417 tg3_flag_set(tp, NVRAM_BUFFERED);
14419 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14420 tp->nvram_jedecnum = JEDEC_ATMEL;
14421 tg3_flag_set(tp, NVRAM_BUFFERED);
14422 tg3_flag_set(tp, FLASH);
14424 case FLASH_5752VENDOR_ST_M45PE10:
14425 case FLASH_5752VENDOR_ST_M45PE20:
14426 case FLASH_5752VENDOR_ST_M45PE40:
14427 tp->nvram_jedecnum = JEDEC_ST;
14428 tg3_flag_set(tp, NVRAM_BUFFERED);
14429 tg3_flag_set(tp, FLASH);
14433 if (tg3_flag(tp, FLASH)) {
14434 tg3_nvram_get_pagesize(tp, nvcfg1);
14436 /* For eeprom, set pagesize to maximum eeprom size */
14437 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14439 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14440 tw32(NVRAM_CFG1, nvcfg1);
14444 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14446 u32 nvcfg1, protect = 0;
14448 nvcfg1 = tr32(NVRAM_CFG1);
14450 /* NVRAM protection for TPM */
14451 if (nvcfg1 & (1 << 27)) {
14452 tg3_flag_set(tp, PROTECTED_NVRAM);
14456 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14458 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14459 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14460 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14461 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14462 tp->nvram_jedecnum = JEDEC_ATMEL;
14463 tg3_flag_set(tp, NVRAM_BUFFERED);
14464 tg3_flag_set(tp, FLASH);
14465 tp->nvram_pagesize = 264;
14466 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14467 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14468 tp->nvram_size = (protect ? 0x3e200 :
14469 TG3_NVRAM_SIZE_512KB);
14470 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14471 tp->nvram_size = (protect ? 0x1f200 :
14472 TG3_NVRAM_SIZE_256KB);
14474 tp->nvram_size = (protect ? 0x1f200 :
14475 TG3_NVRAM_SIZE_128KB);
14477 case FLASH_5752VENDOR_ST_M45PE10:
14478 case FLASH_5752VENDOR_ST_M45PE20:
14479 case FLASH_5752VENDOR_ST_M45PE40:
14480 tp->nvram_jedecnum = JEDEC_ST;
14481 tg3_flag_set(tp, NVRAM_BUFFERED);
14482 tg3_flag_set(tp, FLASH);
14483 tp->nvram_pagesize = 256;
14484 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14485 tp->nvram_size = (protect ?
14486 TG3_NVRAM_SIZE_64KB :
14487 TG3_NVRAM_SIZE_128KB);
14488 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14489 tp->nvram_size = (protect ?
14490 TG3_NVRAM_SIZE_64KB :
14491 TG3_NVRAM_SIZE_256KB);
14493 tp->nvram_size = (protect ?
14494 TG3_NVRAM_SIZE_128KB :
14495 TG3_NVRAM_SIZE_512KB);
14500 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14504 nvcfg1 = tr32(NVRAM_CFG1);
14506 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14507 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14508 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14509 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14510 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14511 tp->nvram_jedecnum = JEDEC_ATMEL;
14512 tg3_flag_set(tp, NVRAM_BUFFERED);
14513 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14515 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14516 tw32(NVRAM_CFG1, nvcfg1);
14518 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14519 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14520 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14521 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14522 tp->nvram_jedecnum = JEDEC_ATMEL;
14523 tg3_flag_set(tp, NVRAM_BUFFERED);
14524 tg3_flag_set(tp, FLASH);
14525 tp->nvram_pagesize = 264;
14527 case FLASH_5752VENDOR_ST_M45PE10:
14528 case FLASH_5752VENDOR_ST_M45PE20:
14529 case FLASH_5752VENDOR_ST_M45PE40:
14530 tp->nvram_jedecnum = JEDEC_ST;
14531 tg3_flag_set(tp, NVRAM_BUFFERED);
14532 tg3_flag_set(tp, FLASH);
14533 tp->nvram_pagesize = 256;
14538 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14540 u32 nvcfg1, protect = 0;
14542 nvcfg1 = tr32(NVRAM_CFG1);
14544 /* NVRAM protection for TPM */
14545 if (nvcfg1 & (1 << 27)) {
14546 tg3_flag_set(tp, PROTECTED_NVRAM);
14550 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14552 case FLASH_5761VENDOR_ATMEL_ADB021D:
14553 case FLASH_5761VENDOR_ATMEL_ADB041D:
14554 case FLASH_5761VENDOR_ATMEL_ADB081D:
14555 case FLASH_5761VENDOR_ATMEL_ADB161D:
14556 case FLASH_5761VENDOR_ATMEL_MDB021D:
14557 case FLASH_5761VENDOR_ATMEL_MDB041D:
14558 case FLASH_5761VENDOR_ATMEL_MDB081D:
14559 case FLASH_5761VENDOR_ATMEL_MDB161D:
14560 tp->nvram_jedecnum = JEDEC_ATMEL;
14561 tg3_flag_set(tp, NVRAM_BUFFERED);
14562 tg3_flag_set(tp, FLASH);
14563 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14564 tp->nvram_pagesize = 256;
14566 case FLASH_5761VENDOR_ST_A_M45PE20:
14567 case FLASH_5761VENDOR_ST_A_M45PE40:
14568 case FLASH_5761VENDOR_ST_A_M45PE80:
14569 case FLASH_5761VENDOR_ST_A_M45PE16:
14570 case FLASH_5761VENDOR_ST_M_M45PE20:
14571 case FLASH_5761VENDOR_ST_M_M45PE40:
14572 case FLASH_5761VENDOR_ST_M_M45PE80:
14573 case FLASH_5761VENDOR_ST_M_M45PE16:
14574 tp->nvram_jedecnum = JEDEC_ST;
14575 tg3_flag_set(tp, NVRAM_BUFFERED);
14576 tg3_flag_set(tp, FLASH);
14577 tp->nvram_pagesize = 256;
14582 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14585 case FLASH_5761VENDOR_ATMEL_ADB161D:
14586 case FLASH_5761VENDOR_ATMEL_MDB161D:
14587 case FLASH_5761VENDOR_ST_A_M45PE16:
14588 case FLASH_5761VENDOR_ST_M_M45PE16:
14589 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14591 case FLASH_5761VENDOR_ATMEL_ADB081D:
14592 case FLASH_5761VENDOR_ATMEL_MDB081D:
14593 case FLASH_5761VENDOR_ST_A_M45PE80:
14594 case FLASH_5761VENDOR_ST_M_M45PE80:
14595 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14597 case FLASH_5761VENDOR_ATMEL_ADB041D:
14598 case FLASH_5761VENDOR_ATMEL_MDB041D:
14599 case FLASH_5761VENDOR_ST_A_M45PE40:
14600 case FLASH_5761VENDOR_ST_M_M45PE40:
14601 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14603 case FLASH_5761VENDOR_ATMEL_ADB021D:
14604 case FLASH_5761VENDOR_ATMEL_MDB021D:
14605 case FLASH_5761VENDOR_ST_A_M45PE20:
14606 case FLASH_5761VENDOR_ST_M_M45PE20:
14607 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14613 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14615 tp->nvram_jedecnum = JEDEC_ATMEL;
14616 tg3_flag_set(tp, NVRAM_BUFFERED);
14617 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14620 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14624 nvcfg1 = tr32(NVRAM_CFG1);
14626 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14627 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14628 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14629 tp->nvram_jedecnum = JEDEC_ATMEL;
14630 tg3_flag_set(tp, NVRAM_BUFFERED);
14631 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14633 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14634 tw32(NVRAM_CFG1, nvcfg1);
14636 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14637 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14638 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14639 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14640 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14641 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14642 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14643 tp->nvram_jedecnum = JEDEC_ATMEL;
14644 tg3_flag_set(tp, NVRAM_BUFFERED);
14645 tg3_flag_set(tp, FLASH);
14647 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14648 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14649 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14650 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14651 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14653 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14654 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14655 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14657 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14658 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14659 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14663 case FLASH_5752VENDOR_ST_M45PE10:
14664 case FLASH_5752VENDOR_ST_M45PE20:
14665 case FLASH_5752VENDOR_ST_M45PE40:
14666 tp->nvram_jedecnum = JEDEC_ST;
14667 tg3_flag_set(tp, NVRAM_BUFFERED);
14668 tg3_flag_set(tp, FLASH);
14670 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14671 case FLASH_5752VENDOR_ST_M45PE10:
14672 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14674 case FLASH_5752VENDOR_ST_M45PE20:
14675 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14677 case FLASH_5752VENDOR_ST_M45PE40:
14678 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14683 tg3_flag_set(tp, NO_NVRAM);
14687 tg3_nvram_get_pagesize(tp, nvcfg1);
14688 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14689 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14693 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14697 nvcfg1 = tr32(NVRAM_CFG1);
14699 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14700 case FLASH_5717VENDOR_ATMEL_EEPROM:
14701 case FLASH_5717VENDOR_MICRO_EEPROM:
14702 tp->nvram_jedecnum = JEDEC_ATMEL;
14703 tg3_flag_set(tp, NVRAM_BUFFERED);
14704 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14706 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14707 tw32(NVRAM_CFG1, nvcfg1);
14709 case FLASH_5717VENDOR_ATMEL_MDB011D:
14710 case FLASH_5717VENDOR_ATMEL_ADB011B:
14711 case FLASH_5717VENDOR_ATMEL_ADB011D:
14712 case FLASH_5717VENDOR_ATMEL_MDB021D:
14713 case FLASH_5717VENDOR_ATMEL_ADB021B:
14714 case FLASH_5717VENDOR_ATMEL_ADB021D:
14715 case FLASH_5717VENDOR_ATMEL_45USPT:
14716 tp->nvram_jedecnum = JEDEC_ATMEL;
14717 tg3_flag_set(tp, NVRAM_BUFFERED);
14718 tg3_flag_set(tp, FLASH);
14720 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14721 case FLASH_5717VENDOR_ATMEL_MDB021D:
14722 /* Detect size with tg3_nvram_get_size() */
14724 case FLASH_5717VENDOR_ATMEL_ADB021B:
14725 case FLASH_5717VENDOR_ATMEL_ADB021D:
14726 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14729 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14733 case FLASH_5717VENDOR_ST_M_M25PE10:
14734 case FLASH_5717VENDOR_ST_A_M25PE10:
14735 case FLASH_5717VENDOR_ST_M_M45PE10:
14736 case FLASH_5717VENDOR_ST_A_M45PE10:
14737 case FLASH_5717VENDOR_ST_M_M25PE20:
14738 case FLASH_5717VENDOR_ST_A_M25PE20:
14739 case FLASH_5717VENDOR_ST_M_M45PE20:
14740 case FLASH_5717VENDOR_ST_A_M45PE20:
14741 case FLASH_5717VENDOR_ST_25USPT:
14742 case FLASH_5717VENDOR_ST_45USPT:
14743 tp->nvram_jedecnum = JEDEC_ST;
14744 tg3_flag_set(tp, NVRAM_BUFFERED);
14745 tg3_flag_set(tp, FLASH);
14747 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14748 case FLASH_5717VENDOR_ST_M_M25PE20:
14749 case FLASH_5717VENDOR_ST_M_M45PE20:
14750 /* Detect size with tg3_nvram_get_size() */
14752 case FLASH_5717VENDOR_ST_A_M25PE20:
14753 case FLASH_5717VENDOR_ST_A_M45PE20:
14754 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14757 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14762 tg3_flag_set(tp, NO_NVRAM);
14766 tg3_nvram_get_pagesize(tp, nvcfg1);
14767 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14768 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14771 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14773 u32 nvcfg1, nvmpinstrp;
14775 nvcfg1 = tr32(NVRAM_CFG1);
14776 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14778 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14779 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14780 tg3_flag_set(tp, NO_NVRAM);
14784 switch (nvmpinstrp) {
14785 case FLASH_5762_EEPROM_HD:
14786 nvmpinstrp = FLASH_5720_EEPROM_HD;
14788 case FLASH_5762_EEPROM_LD:
14789 nvmpinstrp = FLASH_5720_EEPROM_LD;
14791 case FLASH_5720VENDOR_M_ST_M45PE20:
14792 /* This pinstrap supports multiple sizes, so force it
14793 * to read the actual size from location 0xf0.
14795 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14800 switch (nvmpinstrp) {
14801 case FLASH_5720_EEPROM_HD:
14802 case FLASH_5720_EEPROM_LD:
14803 tp->nvram_jedecnum = JEDEC_ATMEL;
14804 tg3_flag_set(tp, NVRAM_BUFFERED);
14806 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14807 tw32(NVRAM_CFG1, nvcfg1);
14808 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14809 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14811 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14813 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14814 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14815 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14816 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14817 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14818 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14819 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14820 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14821 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14822 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14823 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14824 case FLASH_5720VENDOR_ATMEL_45USPT:
14825 tp->nvram_jedecnum = JEDEC_ATMEL;
14826 tg3_flag_set(tp, NVRAM_BUFFERED);
14827 tg3_flag_set(tp, FLASH);
14829 switch (nvmpinstrp) {
14830 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14831 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14832 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14833 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14835 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14836 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14837 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14838 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14840 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14841 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14842 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14845 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14846 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14850 case FLASH_5720VENDOR_M_ST_M25PE10:
14851 case FLASH_5720VENDOR_M_ST_M45PE10:
14852 case FLASH_5720VENDOR_A_ST_M25PE10:
14853 case FLASH_5720VENDOR_A_ST_M45PE10:
14854 case FLASH_5720VENDOR_M_ST_M25PE20:
14855 case FLASH_5720VENDOR_M_ST_M45PE20:
14856 case FLASH_5720VENDOR_A_ST_M25PE20:
14857 case FLASH_5720VENDOR_A_ST_M45PE20:
14858 case FLASH_5720VENDOR_M_ST_M25PE40:
14859 case FLASH_5720VENDOR_M_ST_M45PE40:
14860 case FLASH_5720VENDOR_A_ST_M25PE40:
14861 case FLASH_5720VENDOR_A_ST_M45PE40:
14862 case FLASH_5720VENDOR_M_ST_M25PE80:
14863 case FLASH_5720VENDOR_M_ST_M45PE80:
14864 case FLASH_5720VENDOR_A_ST_M25PE80:
14865 case FLASH_5720VENDOR_A_ST_M45PE80:
14866 case FLASH_5720VENDOR_ST_25USPT:
14867 case FLASH_5720VENDOR_ST_45USPT:
14868 tp->nvram_jedecnum = JEDEC_ST;
14869 tg3_flag_set(tp, NVRAM_BUFFERED);
14870 tg3_flag_set(tp, FLASH);
14872 switch (nvmpinstrp) {
14873 case FLASH_5720VENDOR_M_ST_M25PE20:
14874 case FLASH_5720VENDOR_M_ST_M45PE20:
14875 case FLASH_5720VENDOR_A_ST_M25PE20:
14876 case FLASH_5720VENDOR_A_ST_M45PE20:
14877 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14879 case FLASH_5720VENDOR_M_ST_M25PE40:
14880 case FLASH_5720VENDOR_M_ST_M45PE40:
14881 case FLASH_5720VENDOR_A_ST_M25PE40:
14882 case FLASH_5720VENDOR_A_ST_M45PE40:
14883 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14885 case FLASH_5720VENDOR_M_ST_M25PE80:
14886 case FLASH_5720VENDOR_M_ST_M45PE80:
14887 case FLASH_5720VENDOR_A_ST_M25PE80:
14888 case FLASH_5720VENDOR_A_ST_M45PE80:
14889 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14892 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14893 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14898 tg3_flag_set(tp, NO_NVRAM);
14902 tg3_nvram_get_pagesize(tp, nvcfg1);
14903 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14904 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14906 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14909 if (tg3_nvram_read(tp, 0, &val))
14912 if (val != TG3_EEPROM_MAGIC &&
14913 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14914 tg3_flag_set(tp, NO_NVRAM);
14918 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14919 static void tg3_nvram_init(struct tg3 *tp)
14921 if (tg3_flag(tp, IS_SSB_CORE)) {
14922 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14923 tg3_flag_clear(tp, NVRAM);
14924 tg3_flag_clear(tp, NVRAM_BUFFERED);
14925 tg3_flag_set(tp, NO_NVRAM);
14929 tw32_f(GRC_EEPROM_ADDR,
14930 (EEPROM_ADDR_FSM_RESET |
14931 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14932 EEPROM_ADDR_CLKPERD_SHIFT)));
14936 /* Enable seeprom accesses. */
14937 tw32_f(GRC_LOCAL_CTRL,
14938 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14941 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14942 tg3_asic_rev(tp) != ASIC_REV_5701) {
14943 tg3_flag_set(tp, NVRAM);
14945 if (tg3_nvram_lock(tp)) {
14946 netdev_warn(tp->dev,
14947 "Cannot get nvram lock, %s failed\n",
14951 tg3_enable_nvram_access(tp);
14953 tp->nvram_size = 0;
14955 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14956 tg3_get_5752_nvram_info(tp);
14957 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14958 tg3_get_5755_nvram_info(tp);
14959 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14960 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14961 tg3_asic_rev(tp) == ASIC_REV_5785)
14962 tg3_get_5787_nvram_info(tp);
14963 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14964 tg3_get_5761_nvram_info(tp);
14965 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14966 tg3_get_5906_nvram_info(tp);
14967 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14968 tg3_flag(tp, 57765_CLASS))
14969 tg3_get_57780_nvram_info(tp);
14970 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14971 tg3_asic_rev(tp) == ASIC_REV_5719)
14972 tg3_get_5717_nvram_info(tp);
14973 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14974 tg3_asic_rev(tp) == ASIC_REV_5762)
14975 tg3_get_5720_nvram_info(tp);
14977 tg3_get_nvram_info(tp);
14979 if (tp->nvram_size == 0)
14980 tg3_get_nvram_size(tp);
14982 tg3_disable_nvram_access(tp);
14983 tg3_nvram_unlock(tp);
14986 tg3_flag_clear(tp, NVRAM);
14987 tg3_flag_clear(tp, NVRAM_BUFFERED);
14989 tg3_get_eeprom_size(tp);
14993 struct subsys_tbl_ent {
14994 u16 subsys_vendor, subsys_devid;
14998 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14999 /* Broadcom boards. */
15000 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15001 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
15002 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15003 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
15004 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15005 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
15006 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15007 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15008 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15009 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15010 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15011 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15012 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15013 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15014 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15015 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15016 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15017 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15018 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15019 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15020 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15021 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15024 { TG3PCI_SUBVENDOR_ID_3COM,
15025 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15026 { TG3PCI_SUBVENDOR_ID_3COM,
15027 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15028 { TG3PCI_SUBVENDOR_ID_3COM,
15029 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15030 { TG3PCI_SUBVENDOR_ID_3COM,
15031 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15032 { TG3PCI_SUBVENDOR_ID_3COM,
15033 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15036 { TG3PCI_SUBVENDOR_ID_DELL,
15037 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15038 { TG3PCI_SUBVENDOR_ID_DELL,
15039 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15040 { TG3PCI_SUBVENDOR_ID_DELL,
15041 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15042 { TG3PCI_SUBVENDOR_ID_DELL,
15043 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15045 /* Compaq boards. */
15046 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15047 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15048 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15049 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15050 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15051 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15052 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15053 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15054 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15055 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15058 { TG3PCI_SUBVENDOR_ID_IBM,
15059 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15062 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15066 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15067 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15068 tp->pdev->subsystem_vendor) &&
15069 (subsys_id_to_phy_id[i].subsys_devid ==
15070 tp->pdev->subsystem_device))
15071 return &subsys_id_to_phy_id[i];
15076 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15080 tp->phy_id = TG3_PHY_ID_INVALID;
15081 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15083 /* Assume an onboard device and WOL capable by default. */
15084 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15085 tg3_flag_set(tp, WOL_CAP);
15087 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15088 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15089 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15090 tg3_flag_set(tp, IS_NIC);
15092 val = tr32(VCPU_CFGSHDW);
15093 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15094 tg3_flag_set(tp, ASPM_WORKAROUND);
15095 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15096 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15097 tg3_flag_set(tp, WOL_ENABLE);
15098 device_set_wakeup_enable(&tp->pdev->dev, true);
15103 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15104 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15105 u32 nic_cfg, led_cfg;
15106 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15107 u32 nic_phy_id, ver, eeprom_phy_id;
15108 int eeprom_phy_serdes = 0;
15110 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15111 tp->nic_sram_data_cfg = nic_cfg;
15113 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15114 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15115 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15116 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15117 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15118 (ver > 0) && (ver < 0x100))
15119 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15121 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15122 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15124 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15125 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15126 tg3_asic_rev(tp) == ASIC_REV_5720)
15127 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15129 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15130 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15131 eeprom_phy_serdes = 1;
15133 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15134 if (nic_phy_id != 0) {
15135 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15136 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15138 eeprom_phy_id = (id1 >> 16) << 10;
15139 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15140 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15144 tp->phy_id = eeprom_phy_id;
15145 if (eeprom_phy_serdes) {
15146 if (!tg3_flag(tp, 5705_PLUS))
15147 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15149 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15152 if (tg3_flag(tp, 5750_PLUS))
15153 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15154 SHASTA_EXT_LED_MODE_MASK);
15156 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15160 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15161 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15164 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15165 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15168 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15169 tp->led_ctrl = LED_CTRL_MODE_MAC;
15171 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15172 * read on some older 5700/5701 bootcode.
15174 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15175 tg3_asic_rev(tp) == ASIC_REV_5701)
15176 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15180 case SHASTA_EXT_LED_SHARED:
15181 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15182 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15183 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15184 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15185 LED_CTRL_MODE_PHY_2);
15187 if (tg3_flag(tp, 5717_PLUS) ||
15188 tg3_asic_rev(tp) == ASIC_REV_5762)
15189 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15190 LED_CTRL_BLINK_RATE_MASK;
15194 case SHASTA_EXT_LED_MAC:
15195 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15198 case SHASTA_EXT_LED_COMBO:
15199 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15200 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15201 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15202 LED_CTRL_MODE_PHY_2);
15207 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15208 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15209 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15210 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15212 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15213 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15215 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15216 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15217 if ((tp->pdev->subsystem_vendor ==
15218 PCI_VENDOR_ID_ARIMA) &&
15219 (tp->pdev->subsystem_device == 0x205a ||
15220 tp->pdev->subsystem_device == 0x2063))
15221 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15223 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15224 tg3_flag_set(tp, IS_NIC);
15227 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15228 tg3_flag_set(tp, ENABLE_ASF);
15229 if (tg3_flag(tp, 5750_PLUS))
15230 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15233 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15234 tg3_flag(tp, 5750_PLUS))
15235 tg3_flag_set(tp, ENABLE_APE);
15237 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15238 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15239 tg3_flag_clear(tp, WOL_CAP);
15241 if (tg3_flag(tp, WOL_CAP) &&
15242 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15243 tg3_flag_set(tp, WOL_ENABLE);
15244 device_set_wakeup_enable(&tp->pdev->dev, true);
15247 if (cfg2 & (1 << 17))
15248 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15250 /* serdes signal pre-emphasis in register 0x590 set by */
15251 /* bootcode if bit 18 is set */
15252 if (cfg2 & (1 << 18))
15253 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15255 if ((tg3_flag(tp, 57765_PLUS) ||
15256 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15257 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15258 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15259 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15261 if (tg3_flag(tp, PCI_EXPRESS)) {
15264 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15265 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15266 !tg3_flag(tp, 57765_PLUS) &&
15267 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15268 tg3_flag_set(tp, ASPM_WORKAROUND);
15269 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15270 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15271 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15272 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15275 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15276 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15277 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15278 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15279 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15280 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15282 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15283 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15286 if (tg3_flag(tp, WOL_CAP))
15287 device_set_wakeup_enable(&tp->pdev->dev,
15288 tg3_flag(tp, WOL_ENABLE));
15290 device_set_wakeup_capable(&tp->pdev->dev, false);
15293 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15296 u32 val2, off = offset * 8;
15298 err = tg3_nvram_lock(tp);
15302 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15303 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15304 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15305 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15308 for (i = 0; i < 100; i++) {
15309 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15310 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15311 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15317 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15319 tg3_nvram_unlock(tp);
15320 if (val2 & APE_OTP_STATUS_CMD_DONE)
15326 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15331 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15332 tw32(OTP_CTRL, cmd);
15334 /* Wait for up to 1 ms for command to execute. */
15335 for (i = 0; i < 100; i++) {
15336 val = tr32(OTP_STATUS);
15337 if (val & OTP_STATUS_CMD_DONE)
15342 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15345 /* Read the gphy configuration from the OTP region of the chip. The gphy
15346 * configuration is a 32-bit value that straddles the alignment boundary.
15347 * We do two 32-bit reads and then shift and merge the results.
15349 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15351 u32 bhalf_otp, thalf_otp;
15353 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15355 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15358 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15360 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15363 thalf_otp = tr32(OTP_READ_DATA);
15365 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15367 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15370 bhalf_otp = tr32(OTP_READ_DATA);
15372 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15375 static void tg3_phy_init_link_config(struct tg3 *tp)
15377 u32 adv = ADVERTISED_Autoneg;
15379 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15380 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15381 adv |= ADVERTISED_1000baseT_Half;
15382 adv |= ADVERTISED_1000baseT_Full;
15385 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15386 adv |= ADVERTISED_100baseT_Half |
15387 ADVERTISED_100baseT_Full |
15388 ADVERTISED_10baseT_Half |
15389 ADVERTISED_10baseT_Full |
15392 adv |= ADVERTISED_FIBRE;
15394 tp->link_config.advertising = adv;
15395 tp->link_config.speed = SPEED_UNKNOWN;
15396 tp->link_config.duplex = DUPLEX_UNKNOWN;
15397 tp->link_config.autoneg = AUTONEG_ENABLE;
15398 tp->link_config.active_speed = SPEED_UNKNOWN;
15399 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15404 static int tg3_phy_probe(struct tg3 *tp)
15406 u32 hw_phy_id_1, hw_phy_id_2;
15407 u32 hw_phy_id, hw_phy_id_masked;
15410 /* flow control autonegotiation is default behavior */
15411 tg3_flag_set(tp, PAUSE_AUTONEG);
15412 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15414 if (tg3_flag(tp, ENABLE_APE)) {
15415 switch (tp->pci_fn) {
15417 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15420 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15423 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15426 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15431 if (!tg3_flag(tp, ENABLE_ASF) &&
15432 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15433 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15434 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15435 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15437 if (tg3_flag(tp, USE_PHYLIB))
15438 return tg3_phy_init(tp);
15440 /* Reading the PHY ID register can conflict with ASF
15441 * firmware access to the PHY hardware.
15444 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15445 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15447 /* Now read the physical PHY_ID from the chip and verify
15448 * that it is sane. If it doesn't look good, we fall back
15449 * to either the hard-coded table based PHY_ID and failing
15450 * that the value found in the eeprom area.
15452 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15453 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15455 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15456 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15457 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15459 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15462 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15463 tp->phy_id = hw_phy_id;
15464 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15465 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15467 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15469 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15470 /* Do nothing, phy ID already set up in
15471 * tg3_get_eeprom_hw_cfg().
15474 struct subsys_tbl_ent *p;
15476 /* No eeprom signature? Try the hardcoded
15477 * subsys device table.
15479 p = tg3_lookup_by_subsys(tp);
15481 tp->phy_id = p->phy_id;
15482 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15483 /* For now we saw the IDs 0xbc050cd0,
15484 * 0xbc050f80 and 0xbc050c30 on devices
15485 * connected to an BCM4785 and there are
15486 * probably more. Just assume that the phy is
15487 * supported when it is connected to a SSB core
15494 tp->phy_id == TG3_PHY_ID_BCM8002)
15495 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15499 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15500 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15501 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15502 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15503 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15504 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15505 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15506 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15507 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15508 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15510 tp->eee.supported = SUPPORTED_100baseT_Full |
15511 SUPPORTED_1000baseT_Full;
15512 tp->eee.advertised = ADVERTISED_100baseT_Full |
15513 ADVERTISED_1000baseT_Full;
15514 tp->eee.eee_enabled = 1;
15515 tp->eee.tx_lpi_enabled = 1;
15516 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15519 tg3_phy_init_link_config(tp);
15521 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15522 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15523 !tg3_flag(tp, ENABLE_APE) &&
15524 !tg3_flag(tp, ENABLE_ASF)) {
15527 tg3_readphy(tp, MII_BMSR, &bmsr);
15528 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15529 (bmsr & BMSR_LSTATUS))
15530 goto skip_phy_reset;
15532 err = tg3_phy_reset(tp);
15536 tg3_phy_set_wirespeed(tp);
15538 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15539 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15540 tp->link_config.flowctrl);
15542 tg3_writephy(tp, MII_BMCR,
15543 BMCR_ANENABLE | BMCR_ANRESTART);
15548 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15549 err = tg3_init_5401phy_dsp(tp);
15553 err = tg3_init_5401phy_dsp(tp);
15559 static void tg3_read_vpd(struct tg3 *tp)
15562 unsigned int block_end, rosize, len;
15566 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15570 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15572 goto out_not_found;
15574 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15575 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15576 i += PCI_VPD_LRDT_TAG_SIZE;
15578 if (block_end > vpdlen)
15579 goto out_not_found;
15581 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15582 PCI_VPD_RO_KEYWORD_MFR_ID);
15584 len = pci_vpd_info_field_size(&vpd_data[j]);
15586 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15587 if (j + len > block_end || len != 4 ||
15588 memcmp(&vpd_data[j], "1028", 4))
15591 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15592 PCI_VPD_RO_KEYWORD_VENDOR0);
15596 len = pci_vpd_info_field_size(&vpd_data[j]);
15598 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15599 if (j + len > block_end)
15602 if (len >= sizeof(tp->fw_ver))
15603 len = sizeof(tp->fw_ver) - 1;
15604 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15605 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15610 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15611 PCI_VPD_RO_KEYWORD_PARTNO);
15613 goto out_not_found;
15615 len = pci_vpd_info_field_size(&vpd_data[i]);
15617 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15618 if (len > TG3_BPN_SIZE ||
15619 (len + i) > vpdlen)
15620 goto out_not_found;
15622 memcpy(tp->board_part_number, &vpd_data[i], len);
15626 if (tp->board_part_number[0])
15630 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15631 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15632 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15633 strcpy(tp->board_part_number, "BCM5717");
15634 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15635 strcpy(tp->board_part_number, "BCM5718");
15638 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15639 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15640 strcpy(tp->board_part_number, "BCM57780");
15641 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15642 strcpy(tp->board_part_number, "BCM57760");
15643 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15644 strcpy(tp->board_part_number, "BCM57790");
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15646 strcpy(tp->board_part_number, "BCM57788");
15649 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15650 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15651 strcpy(tp->board_part_number, "BCM57761");
15652 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15653 strcpy(tp->board_part_number, "BCM57765");
15654 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15655 strcpy(tp->board_part_number, "BCM57781");
15656 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15657 strcpy(tp->board_part_number, "BCM57785");
15658 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15659 strcpy(tp->board_part_number, "BCM57791");
15660 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15661 strcpy(tp->board_part_number, "BCM57795");
15664 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15665 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15666 strcpy(tp->board_part_number, "BCM57762");
15667 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15668 strcpy(tp->board_part_number, "BCM57766");
15669 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15670 strcpy(tp->board_part_number, "BCM57782");
15671 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15672 strcpy(tp->board_part_number, "BCM57786");
15675 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15676 strcpy(tp->board_part_number, "BCM95906");
15679 strcpy(tp->board_part_number, "none");
15683 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15687 if (tg3_nvram_read(tp, offset, &val) ||
15688 (val & 0xfc000000) != 0x0c000000 ||
15689 tg3_nvram_read(tp, offset + 4, &val) ||
15696 static void tg3_read_bc_ver(struct tg3 *tp)
15698 u32 val, offset, start, ver_offset;
15700 bool newver = false;
15702 if (tg3_nvram_read(tp, 0xc, &offset) ||
15703 tg3_nvram_read(tp, 0x4, &start))
15706 offset = tg3_nvram_logical_addr(tp, offset);
15708 if (tg3_nvram_read(tp, offset, &val))
15711 if ((val & 0xfc000000) == 0x0c000000) {
15712 if (tg3_nvram_read(tp, offset + 4, &val))
15719 dst_off = strlen(tp->fw_ver);
15722 if (TG3_VER_SIZE - dst_off < 16 ||
15723 tg3_nvram_read(tp, offset + 8, &ver_offset))
15726 offset = offset + ver_offset - start;
15727 for (i = 0; i < 16; i += 4) {
15729 if (tg3_nvram_read_be32(tp, offset + i, &v))
15732 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15737 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15740 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15741 TG3_NVM_BCVER_MAJSFT;
15742 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15743 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15744 "v%d.%02d", major, minor);
15748 static void tg3_read_hwsb_ver(struct tg3 *tp)
15750 u32 val, major, minor;
15752 /* Use native endian representation */
15753 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15756 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15757 TG3_NVM_HWSB_CFG1_MAJSFT;
15758 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15759 TG3_NVM_HWSB_CFG1_MINSFT;
15761 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15764 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15766 u32 offset, major, minor, build;
15768 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15770 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15773 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15774 case TG3_EEPROM_SB_REVISION_0:
15775 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15777 case TG3_EEPROM_SB_REVISION_2:
15778 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15780 case TG3_EEPROM_SB_REVISION_3:
15781 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15783 case TG3_EEPROM_SB_REVISION_4:
15784 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15786 case TG3_EEPROM_SB_REVISION_5:
15787 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15789 case TG3_EEPROM_SB_REVISION_6:
15790 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15796 if (tg3_nvram_read(tp, offset, &val))
15799 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15800 TG3_EEPROM_SB_EDH_BLD_SHFT;
15801 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15802 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15803 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15805 if (minor > 99 || build > 26)
15808 offset = strlen(tp->fw_ver);
15809 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15810 " v%d.%02d", major, minor);
15813 offset = strlen(tp->fw_ver);
15814 if (offset < TG3_VER_SIZE - 1)
15815 tp->fw_ver[offset] = 'a' + build - 1;
15819 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15821 u32 val, offset, start;
15824 for (offset = TG3_NVM_DIR_START;
15825 offset < TG3_NVM_DIR_END;
15826 offset += TG3_NVM_DIRENT_SIZE) {
15827 if (tg3_nvram_read(tp, offset, &val))
15830 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15834 if (offset == TG3_NVM_DIR_END)
15837 if (!tg3_flag(tp, 5705_PLUS))
15838 start = 0x08000000;
15839 else if (tg3_nvram_read(tp, offset - 4, &start))
15842 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15843 !tg3_fw_img_is_valid(tp, offset) ||
15844 tg3_nvram_read(tp, offset + 8, &val))
15847 offset += val - start;
15849 vlen = strlen(tp->fw_ver);
15851 tp->fw_ver[vlen++] = ',';
15852 tp->fw_ver[vlen++] = ' ';
15854 for (i = 0; i < 4; i++) {
15856 if (tg3_nvram_read_be32(tp, offset, &v))
15859 offset += sizeof(v);
15861 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15862 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15866 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15871 static void tg3_probe_ncsi(struct tg3 *tp)
15875 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15876 if (apedata != APE_SEG_SIG_MAGIC)
15879 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15880 if (!(apedata & APE_FW_STATUS_READY))
15883 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15884 tg3_flag_set(tp, APE_HAS_NCSI);
15887 static void tg3_read_dash_ver(struct tg3 *tp)
15893 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15895 if (tg3_flag(tp, APE_HAS_NCSI))
15897 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15902 vlen = strlen(tp->fw_ver);
15904 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15906 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15907 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15908 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15909 (apedata & APE_FW_VERSION_BLDMSK));
15912 static void tg3_read_otp_ver(struct tg3 *tp)
15916 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15919 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15920 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15921 TG3_OTP_MAGIC0_VALID(val)) {
15922 u64 val64 = (u64) val << 32 | val2;
15926 for (i = 0; i < 7; i++) {
15927 if ((val64 & 0xff) == 0)
15929 ver = val64 & 0xff;
15932 vlen = strlen(tp->fw_ver);
15933 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15937 static void tg3_read_fw_ver(struct tg3 *tp)
15940 bool vpd_vers = false;
15942 if (tp->fw_ver[0] != 0)
15945 if (tg3_flag(tp, NO_NVRAM)) {
15946 strcat(tp->fw_ver, "sb");
15947 tg3_read_otp_ver(tp);
15951 if (tg3_nvram_read(tp, 0, &val))
15954 if (val == TG3_EEPROM_MAGIC)
15955 tg3_read_bc_ver(tp);
15956 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15957 tg3_read_sb_ver(tp, val);
15958 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15959 tg3_read_hwsb_ver(tp);
15961 if (tg3_flag(tp, ENABLE_ASF)) {
15962 if (tg3_flag(tp, ENABLE_APE)) {
15963 tg3_probe_ncsi(tp);
15965 tg3_read_dash_ver(tp);
15966 } else if (!vpd_vers) {
15967 tg3_read_mgmtfw_ver(tp);
15971 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15974 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15976 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15977 return TG3_RX_RET_MAX_SIZE_5717;
15978 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15979 return TG3_RX_RET_MAX_SIZE_5700;
15981 return TG3_RX_RET_MAX_SIZE_5705;
15984 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15985 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15986 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15987 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15991 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15993 struct pci_dev *peer;
15994 unsigned int func, devnr = tp->pdev->devfn & ~7;
15996 for (func = 0; func < 8; func++) {
15997 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15998 if (peer && peer != tp->pdev)
16002 /* 5704 can be configured in single-port mode, set peer to
16003 * tp->pdev in that case.
16011 * We don't need to keep the refcount elevated; there's no way
16012 * to remove one half of this device without removing the other
16019 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16021 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16022 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16025 /* All devices that use the alternate
16026 * ASIC REV location have a CPMU.
16028 tg3_flag_set(tp, CPMU_PRESENT);
16030 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16031 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16032 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16033 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16034 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16035 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16041 reg = TG3PCI_GEN2_PRODID_ASICREV;
16042 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16046 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16047 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16049 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16050 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16051 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16052 reg = TG3PCI_GEN15_PRODID_ASICREV;
16054 reg = TG3PCI_PRODID_ASICREV;
16056 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16059 /* Wrong chip ID in 5752 A0. This code can be removed later
16060 * as A0 is not in production.
16062 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16063 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16065 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16066 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16068 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16069 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16070 tg3_asic_rev(tp) == ASIC_REV_5720)
16071 tg3_flag_set(tp, 5717_PLUS);
16073 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16074 tg3_asic_rev(tp) == ASIC_REV_57766)
16075 tg3_flag_set(tp, 57765_CLASS);
16077 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16078 tg3_asic_rev(tp) == ASIC_REV_5762)
16079 tg3_flag_set(tp, 57765_PLUS);
16081 /* Intentionally exclude ASIC_REV_5906 */
16082 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16083 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16084 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16085 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16086 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16087 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16088 tg3_flag(tp, 57765_PLUS))
16089 tg3_flag_set(tp, 5755_PLUS);
16091 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16092 tg3_asic_rev(tp) == ASIC_REV_5714)
16093 tg3_flag_set(tp, 5780_CLASS);
16095 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16096 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16097 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16098 tg3_flag(tp, 5755_PLUS) ||
16099 tg3_flag(tp, 5780_CLASS))
16100 tg3_flag_set(tp, 5750_PLUS);
16102 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16103 tg3_flag(tp, 5750_PLUS))
16104 tg3_flag_set(tp, 5705_PLUS);
16107 static bool tg3_10_100_only_device(struct tg3 *tp,
16108 const struct pci_device_id *ent)
16110 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16112 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16113 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16114 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16117 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16118 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16119 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16129 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16132 u32 pci_state_reg, grc_misc_cfg;
16137 /* Force memory write invalidate off. If we leave it on,
16138 * then on 5700_BX chips we have to enable a workaround.
16139 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16140 * to match the cacheline size. The Broadcom driver have this
16141 * workaround but turns MWI off all the times so never uses
16142 * it. This seems to suggest that the workaround is insufficient.
16144 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16145 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16146 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16148 /* Important! -- Make sure register accesses are byteswapped
16149 * correctly. Also, for those chips that require it, make
16150 * sure that indirect register accesses are enabled before
16151 * the first operation.
16153 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16155 tp->misc_host_ctrl |= (misc_ctrl_reg &
16156 MISC_HOST_CTRL_CHIPREV);
16157 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16158 tp->misc_host_ctrl);
16160 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16162 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16163 * we need to disable memory and use config. cycles
16164 * only to access all registers. The 5702/03 chips
16165 * can mistakenly decode the special cycles from the
16166 * ICH chipsets as memory write cycles, causing corruption
16167 * of register and memory space. Only certain ICH bridges
16168 * will drive special cycles with non-zero data during the
16169 * address phase which can fall within the 5703's address
16170 * range. This is not an ICH bug as the PCI spec allows
16171 * non-zero address during special cycles. However, only
16172 * these ICH bridges are known to drive non-zero addresses
16173 * during special cycles.
16175 * Since special cycles do not cross PCI bridges, we only
16176 * enable this workaround if the 5703 is on the secondary
16177 * bus of these ICH bridges.
16179 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16180 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16181 static struct tg3_dev_id {
16185 } ich_chipsets[] = {
16186 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16188 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16190 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16192 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16196 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16197 struct pci_dev *bridge = NULL;
16199 while (pci_id->vendor != 0) {
16200 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16206 if (pci_id->rev != PCI_ANY_ID) {
16207 if (bridge->revision > pci_id->rev)
16210 if (bridge->subordinate &&
16211 (bridge->subordinate->number ==
16212 tp->pdev->bus->number)) {
16213 tg3_flag_set(tp, ICH_WORKAROUND);
16214 pci_dev_put(bridge);
16220 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16221 static struct tg3_dev_id {
16224 } bridge_chipsets[] = {
16225 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16226 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16229 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16230 struct pci_dev *bridge = NULL;
16232 while (pci_id->vendor != 0) {
16233 bridge = pci_get_device(pci_id->vendor,
16240 if (bridge->subordinate &&
16241 (bridge->subordinate->number <=
16242 tp->pdev->bus->number) &&
16243 (bridge->subordinate->busn_res.end >=
16244 tp->pdev->bus->number)) {
16245 tg3_flag_set(tp, 5701_DMA_BUG);
16246 pci_dev_put(bridge);
16252 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16253 * DMA addresses > 40-bit. This bridge may have other additional
16254 * 57xx devices behind it in some 4-port NIC designs for example.
16255 * Any tg3 device found behind the bridge will also need the 40-bit
16258 if (tg3_flag(tp, 5780_CLASS)) {
16259 tg3_flag_set(tp, 40BIT_DMA_BUG);
16260 tp->msi_cap = tp->pdev->msi_cap;
16262 struct pci_dev *bridge = NULL;
16265 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16266 PCI_DEVICE_ID_SERVERWORKS_EPB,
16268 if (bridge && bridge->subordinate &&
16269 (bridge->subordinate->number <=
16270 tp->pdev->bus->number) &&
16271 (bridge->subordinate->busn_res.end >=
16272 tp->pdev->bus->number)) {
16273 tg3_flag_set(tp, 40BIT_DMA_BUG);
16274 pci_dev_put(bridge);
16280 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16281 tg3_asic_rev(tp) == ASIC_REV_5714)
16282 tp->pdev_peer = tg3_find_peer(tp);
16284 /* Determine TSO capabilities */
16285 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16286 ; /* Do nothing. HW bug. */
16287 else if (tg3_flag(tp, 57765_PLUS))
16288 tg3_flag_set(tp, HW_TSO_3);
16289 else if (tg3_flag(tp, 5755_PLUS) ||
16290 tg3_asic_rev(tp) == ASIC_REV_5906)
16291 tg3_flag_set(tp, HW_TSO_2);
16292 else if (tg3_flag(tp, 5750_PLUS)) {
16293 tg3_flag_set(tp, HW_TSO_1);
16294 tg3_flag_set(tp, TSO_BUG);
16295 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16296 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16297 tg3_flag_clear(tp, TSO_BUG);
16298 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16299 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16300 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16301 tg3_flag_set(tp, FW_TSO);
16302 tg3_flag_set(tp, TSO_BUG);
16303 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16304 tp->fw_needed = FIRMWARE_TG3TSO5;
16306 tp->fw_needed = FIRMWARE_TG3TSO;
16309 /* Selectively allow TSO based on operating conditions */
16310 if (tg3_flag(tp, HW_TSO_1) ||
16311 tg3_flag(tp, HW_TSO_2) ||
16312 tg3_flag(tp, HW_TSO_3) ||
16313 tg3_flag(tp, FW_TSO)) {
16314 /* For firmware TSO, assume ASF is disabled.
16315 * We'll disable TSO later if we discover ASF
16316 * is enabled in tg3_get_eeprom_hw_cfg().
16318 tg3_flag_set(tp, TSO_CAPABLE);
16320 tg3_flag_clear(tp, TSO_CAPABLE);
16321 tg3_flag_clear(tp, TSO_BUG);
16322 tp->fw_needed = NULL;
16325 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16326 tp->fw_needed = FIRMWARE_TG3;
16328 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16329 tp->fw_needed = FIRMWARE_TG357766;
16333 if (tg3_flag(tp, 5750_PLUS)) {
16334 tg3_flag_set(tp, SUPPORT_MSI);
16335 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16336 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16337 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16338 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16339 tp->pdev_peer == tp->pdev))
16340 tg3_flag_clear(tp, SUPPORT_MSI);
16342 if (tg3_flag(tp, 5755_PLUS) ||
16343 tg3_asic_rev(tp) == ASIC_REV_5906) {
16344 tg3_flag_set(tp, 1SHOT_MSI);
16347 if (tg3_flag(tp, 57765_PLUS)) {
16348 tg3_flag_set(tp, SUPPORT_MSIX);
16349 tp->irq_max = TG3_IRQ_MAX_VECS;
16355 if (tp->irq_max > 1) {
16356 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16357 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16359 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16360 tg3_asic_rev(tp) == ASIC_REV_5720)
16361 tp->txq_max = tp->irq_max - 1;
16364 if (tg3_flag(tp, 5755_PLUS) ||
16365 tg3_asic_rev(tp) == ASIC_REV_5906)
16366 tg3_flag_set(tp, SHORT_DMA_BUG);
16368 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16369 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16371 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16372 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16373 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16374 tg3_asic_rev(tp) == ASIC_REV_5762)
16375 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16377 if (tg3_flag(tp, 57765_PLUS) &&
16378 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16379 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16381 if (!tg3_flag(tp, 5705_PLUS) ||
16382 tg3_flag(tp, 5780_CLASS) ||
16383 tg3_flag(tp, USE_JUMBO_BDFLAG))
16384 tg3_flag_set(tp, JUMBO_CAPABLE);
16386 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16389 if (pci_is_pcie(tp->pdev)) {
16392 tg3_flag_set(tp, PCI_EXPRESS);
16394 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16395 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16396 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16397 tg3_flag_clear(tp, HW_TSO_2);
16398 tg3_flag_clear(tp, TSO_CAPABLE);
16400 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16401 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16402 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16403 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16404 tg3_flag_set(tp, CLKREQ_BUG);
16405 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16406 tg3_flag_set(tp, L1PLLPD_EN);
16408 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16409 /* BCM5785 devices are effectively PCIe devices, and should
16410 * follow PCIe codepaths, but do not have a PCIe capabilities
16413 tg3_flag_set(tp, PCI_EXPRESS);
16414 } else if (!tg3_flag(tp, 5705_PLUS) ||
16415 tg3_flag(tp, 5780_CLASS)) {
16416 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16417 if (!tp->pcix_cap) {
16418 dev_err(&tp->pdev->dev,
16419 "Cannot find PCI-X capability, aborting\n");
16423 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16424 tg3_flag_set(tp, PCIX_MODE);
16427 /* If we have an AMD 762 or VIA K8T800 chipset, write
16428 * reordering to the mailbox registers done by the host
16429 * controller can cause major troubles. We read back from
16430 * every mailbox register write to force the writes to be
16431 * posted to the chip in order.
16433 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16434 !tg3_flag(tp, PCI_EXPRESS))
16435 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16437 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16438 &tp->pci_cacheline_sz);
16439 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16440 &tp->pci_lat_timer);
16441 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16442 tp->pci_lat_timer < 64) {
16443 tp->pci_lat_timer = 64;
16444 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16445 tp->pci_lat_timer);
16448 /* Important! -- It is critical that the PCI-X hw workaround
16449 * situation is decided before the first MMIO register access.
16451 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16452 /* 5700 BX chips need to have their TX producer index
16453 * mailboxes written twice to workaround a bug.
16455 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16457 /* If we are in PCI-X mode, enable register write workaround.
16459 * The workaround is to use indirect register accesses
16460 * for all chip writes not to mailbox registers.
16462 if (tg3_flag(tp, PCIX_MODE)) {
16465 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16467 /* The chip can have it's power management PCI config
16468 * space registers clobbered due to this bug.
16469 * So explicitly force the chip into D0 here.
16471 pci_read_config_dword(tp->pdev,
16472 tp->pdev->pm_cap + PCI_PM_CTRL,
16474 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16475 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16476 pci_write_config_dword(tp->pdev,
16477 tp->pdev->pm_cap + PCI_PM_CTRL,
16480 /* Also, force SERR#/PERR# in PCI command. */
16481 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16482 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16483 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16487 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16488 tg3_flag_set(tp, PCI_HIGH_SPEED);
16489 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16490 tg3_flag_set(tp, PCI_32BIT);
16492 /* Chip-specific fixup from Broadcom driver */
16493 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16494 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16495 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16496 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16499 /* Default fast path register access methods */
16500 tp->read32 = tg3_read32;
16501 tp->write32 = tg3_write32;
16502 tp->read32_mbox = tg3_read32;
16503 tp->write32_mbox = tg3_write32;
16504 tp->write32_tx_mbox = tg3_write32;
16505 tp->write32_rx_mbox = tg3_write32;
16507 /* Various workaround register access methods */
16508 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16509 tp->write32 = tg3_write_indirect_reg32;
16510 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16511 (tg3_flag(tp, PCI_EXPRESS) &&
16512 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16514 * Back to back register writes can cause problems on these
16515 * chips, the workaround is to read back all reg writes
16516 * except those to mailbox regs.
16518 * See tg3_write_indirect_reg32().
16520 tp->write32 = tg3_write_flush_reg32;
16523 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16524 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16525 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16526 tp->write32_rx_mbox = tg3_write_flush_reg32;
16529 if (tg3_flag(tp, ICH_WORKAROUND)) {
16530 tp->read32 = tg3_read_indirect_reg32;
16531 tp->write32 = tg3_write_indirect_reg32;
16532 tp->read32_mbox = tg3_read_indirect_mbox;
16533 tp->write32_mbox = tg3_write_indirect_mbox;
16534 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16535 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16540 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16541 pci_cmd &= ~PCI_COMMAND_MEMORY;
16542 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16544 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16545 tp->read32_mbox = tg3_read32_mbox_5906;
16546 tp->write32_mbox = tg3_write32_mbox_5906;
16547 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16548 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16551 if (tp->write32 == tg3_write_indirect_reg32 ||
16552 (tg3_flag(tp, PCIX_MODE) &&
16553 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16554 tg3_asic_rev(tp) == ASIC_REV_5701)))
16555 tg3_flag_set(tp, SRAM_USE_CONFIG);
16557 /* The memory arbiter has to be enabled in order for SRAM accesses
16558 * to succeed. Normally on powerup the tg3 chip firmware will make
16559 * sure it is enabled, but other entities such as system netboot
16560 * code might disable it.
16562 val = tr32(MEMARB_MODE);
16563 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16565 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16566 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16567 tg3_flag(tp, 5780_CLASS)) {
16568 if (tg3_flag(tp, PCIX_MODE)) {
16569 pci_read_config_dword(tp->pdev,
16570 tp->pcix_cap + PCI_X_STATUS,
16572 tp->pci_fn = val & 0x7;
16574 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16575 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16576 tg3_asic_rev(tp) == ASIC_REV_5720) {
16577 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16578 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16579 val = tr32(TG3_CPMU_STATUS);
16581 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16582 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16584 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16585 TG3_CPMU_STATUS_FSHFT_5719;
16588 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16589 tp->write32_tx_mbox = tg3_write_flush_reg32;
16590 tp->write32_rx_mbox = tg3_write_flush_reg32;
16593 /* Get eeprom hw config before calling tg3_set_power_state().
16594 * In particular, the TG3_FLAG_IS_NIC flag must be
16595 * determined before calling tg3_set_power_state() so that
16596 * we know whether or not to switch out of Vaux power.
16597 * When the flag is set, it means that GPIO1 is used for eeprom
16598 * write protect and also implies that it is a LOM where GPIOs
16599 * are not used to switch power.
16601 tg3_get_eeprom_hw_cfg(tp);
16603 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16604 tg3_flag_clear(tp, TSO_CAPABLE);
16605 tg3_flag_clear(tp, TSO_BUG);
16606 tp->fw_needed = NULL;
16609 if (tg3_flag(tp, ENABLE_APE)) {
16610 /* Allow reads and writes to the
16611 * APE register and memory space.
16613 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16614 PCISTATE_ALLOW_APE_SHMEM_WR |
16615 PCISTATE_ALLOW_APE_PSPACE_WR;
16616 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16619 tg3_ape_lock_init(tp);
16622 /* Set up tp->grc_local_ctrl before calling
16623 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16624 * will bring 5700's external PHY out of reset.
16625 * It is also used as eeprom write protect on LOMs.
16627 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16628 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16629 tg3_flag(tp, EEPROM_WRITE_PROT))
16630 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16631 GRC_LCLCTRL_GPIO_OUTPUT1);
16632 /* Unused GPIO3 must be driven as output on 5752 because there
16633 * are no pull-up resistors on unused GPIO pins.
16635 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16636 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16638 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16639 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16640 tg3_flag(tp, 57765_CLASS))
16641 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16643 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16645 /* Turn off the debug UART. */
16646 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16647 if (tg3_flag(tp, IS_NIC))
16648 /* Keep VMain power. */
16649 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16650 GRC_LCLCTRL_GPIO_OUTPUT0;
16653 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16654 tp->grc_local_ctrl |=
16655 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16657 /* Switch out of Vaux if it is a NIC */
16658 tg3_pwrsrc_switch_to_vmain(tp);
16660 /* Derive initial jumbo mode from MTU assigned in
16661 * ether_setup() via the alloc_etherdev() call
16663 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16664 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16666 /* Determine WakeOnLan speed to use. */
16667 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16668 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16669 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16670 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16671 tg3_flag_clear(tp, WOL_SPEED_100MB);
16673 tg3_flag_set(tp, WOL_SPEED_100MB);
16676 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16677 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16679 /* A few boards don't want Ethernet@WireSpeed phy feature */
16680 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16681 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16682 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16683 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16684 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16685 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16686 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16688 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16689 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16690 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16691 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16692 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16694 if (tg3_flag(tp, 5705_PLUS) &&
16695 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16696 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16697 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16698 !tg3_flag(tp, 57765_PLUS)) {
16699 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16700 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16701 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16702 tg3_asic_rev(tp) == ASIC_REV_5761) {
16703 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16704 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16705 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16706 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16707 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16709 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16712 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16713 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16714 tp->phy_otp = tg3_read_otp_phycfg(tp);
16715 if (tp->phy_otp == 0)
16716 tp->phy_otp = TG3_OTP_DEFAULT;
16719 if (tg3_flag(tp, CPMU_PRESENT))
16720 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16722 tp->mi_mode = MAC_MI_MODE_BASE;
16724 tp->coalesce_mode = 0;
16725 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16726 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16727 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16729 /* Set these bits to enable statistics workaround. */
16730 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16731 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16732 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16733 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16734 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16735 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16738 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16739 tg3_asic_rev(tp) == ASIC_REV_57780)
16740 tg3_flag_set(tp, USE_PHYLIB);
16742 err = tg3_mdio_init(tp);
16746 /* Initialize data/descriptor byte/word swapping. */
16747 val = tr32(GRC_MODE);
16748 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16749 tg3_asic_rev(tp) == ASIC_REV_5762)
16750 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16751 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16752 GRC_MODE_B2HRX_ENABLE |
16753 GRC_MODE_HTX2B_ENABLE |
16754 GRC_MODE_HOST_STACKUP);
16756 val &= GRC_MODE_HOST_STACKUP;
16758 tw32(GRC_MODE, val | tp->grc_mode);
16760 tg3_switch_clocks(tp);
16762 /* Clear this out for sanity. */
16763 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16765 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16766 tw32(TG3PCI_REG_BASE_ADDR, 0);
16768 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16770 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16771 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16772 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16773 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16774 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16775 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16776 void __iomem *sram_base;
16778 /* Write some dummy words into the SRAM status block
16779 * area, see if it reads back correctly. If the return
16780 * value is bad, force enable the PCIX workaround.
16782 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16784 writel(0x00000000, sram_base);
16785 writel(0x00000000, sram_base + 4);
16786 writel(0xffffffff, sram_base + 4);
16787 if (readl(sram_base) != 0x00000000)
16788 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16793 tg3_nvram_init(tp);
16795 /* If the device has an NVRAM, no need to load patch firmware */
16796 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16797 !tg3_flag(tp, NO_NVRAM))
16798 tp->fw_needed = NULL;
16800 grc_misc_cfg = tr32(GRC_MISC_CFG);
16801 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16803 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16804 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16805 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16806 tg3_flag_set(tp, IS_5788);
16808 if (!tg3_flag(tp, IS_5788) &&
16809 tg3_asic_rev(tp) != ASIC_REV_5700)
16810 tg3_flag_set(tp, TAGGED_STATUS);
16811 if (tg3_flag(tp, TAGGED_STATUS)) {
16812 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16813 HOSTCC_MODE_CLRTICK_TXBD);
16815 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16816 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16817 tp->misc_host_ctrl);
16820 /* Preserve the APE MAC_MODE bits */
16821 if (tg3_flag(tp, ENABLE_APE))
16822 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16826 if (tg3_10_100_only_device(tp, ent))
16827 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16829 err = tg3_phy_probe(tp);
16831 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16832 /* ... but do not return immediately ... */
16837 tg3_read_fw_ver(tp);
16839 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16840 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16842 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16843 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16845 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16848 /* 5700 {AX,BX} chips have a broken status block link
16849 * change bit implementation, so we must use the
16850 * status register in those cases.
16852 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16853 tg3_flag_set(tp, USE_LINKCHG_REG);
16855 tg3_flag_clear(tp, USE_LINKCHG_REG);
16857 /* The led_ctrl is set during tg3_phy_probe, here we might
16858 * have to force the link status polling mechanism based
16859 * upon subsystem IDs.
16861 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16862 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16863 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16864 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16865 tg3_flag_set(tp, USE_LINKCHG_REG);
16868 /* For all SERDES we poll the MAC status register. */
16869 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16870 tg3_flag_set(tp, POLL_SERDES);
16872 tg3_flag_clear(tp, POLL_SERDES);
16874 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16875 tg3_flag_set(tp, POLL_CPMU_LINK);
16877 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16878 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16879 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16880 tg3_flag(tp, PCIX_MODE)) {
16881 tp->rx_offset = NET_SKB_PAD;
16882 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16883 tp->rx_copy_thresh = ~(u16)0;
16887 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16888 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16889 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16891 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16893 /* Increment the rx prod index on the rx std ring by at most
16894 * 8 for these chips to workaround hw errata.
16896 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16897 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16898 tg3_asic_rev(tp) == ASIC_REV_5755)
16899 tp->rx_std_max_post = 8;
16901 if (tg3_flag(tp, ASPM_WORKAROUND))
16902 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16903 PCIE_PWR_MGMT_L1_THRESH_MSK;
16908 #ifdef CONFIG_SPARC
16909 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16911 struct net_device *dev = tp->dev;
16912 struct pci_dev *pdev = tp->pdev;
16913 struct device_node *dp = pci_device_to_OF_node(pdev);
16914 const unsigned char *addr;
16917 addr = of_get_property(dp, "local-mac-address", &len);
16918 if (addr && len == ETH_ALEN) {
16919 memcpy(dev->dev_addr, addr, ETH_ALEN);
16925 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16927 struct net_device *dev = tp->dev;
16929 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16934 static int tg3_get_device_address(struct tg3 *tp)
16936 struct net_device *dev = tp->dev;
16937 u32 hi, lo, mac_offset;
16941 #ifdef CONFIG_SPARC
16942 if (!tg3_get_macaddr_sparc(tp))
16946 if (tg3_flag(tp, IS_SSB_CORE)) {
16947 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16948 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16953 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16954 tg3_flag(tp, 5780_CLASS)) {
16955 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16957 if (tg3_nvram_lock(tp))
16958 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16960 tg3_nvram_unlock(tp);
16961 } else if (tg3_flag(tp, 5717_PLUS)) {
16962 if (tp->pci_fn & 1)
16964 if (tp->pci_fn > 1)
16965 mac_offset += 0x18c;
16966 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16969 /* First try to get it from MAC address mailbox. */
16970 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16971 if ((hi >> 16) == 0x484b) {
16972 dev->dev_addr[0] = (hi >> 8) & 0xff;
16973 dev->dev_addr[1] = (hi >> 0) & 0xff;
16975 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16976 dev->dev_addr[2] = (lo >> 24) & 0xff;
16977 dev->dev_addr[3] = (lo >> 16) & 0xff;
16978 dev->dev_addr[4] = (lo >> 8) & 0xff;
16979 dev->dev_addr[5] = (lo >> 0) & 0xff;
16981 /* Some old bootcode may report a 0 MAC address in SRAM */
16982 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16985 /* Next, try NVRAM. */
16986 if (!tg3_flag(tp, NO_NVRAM) &&
16987 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16988 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16989 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16990 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16992 /* Finally just fetch it out of the MAC control regs. */
16994 hi = tr32(MAC_ADDR_0_HIGH);
16995 lo = tr32(MAC_ADDR_0_LOW);
16997 dev->dev_addr[5] = lo & 0xff;
16998 dev->dev_addr[4] = (lo >> 8) & 0xff;
16999 dev->dev_addr[3] = (lo >> 16) & 0xff;
17000 dev->dev_addr[2] = (lo >> 24) & 0xff;
17001 dev->dev_addr[1] = hi & 0xff;
17002 dev->dev_addr[0] = (hi >> 8) & 0xff;
17006 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
17007 #ifdef CONFIG_SPARC
17008 if (!tg3_get_default_macaddr_sparc(tp))
17016 #define BOUNDARY_SINGLE_CACHELINE 1
17017 #define BOUNDARY_MULTI_CACHELINE 2
17019 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17021 int cacheline_size;
17025 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17027 cacheline_size = 1024;
17029 cacheline_size = (int) byte * 4;
17031 /* On 5703 and later chips, the boundary bits have no
17034 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17035 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17036 !tg3_flag(tp, PCI_EXPRESS))
17039 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17040 goal = BOUNDARY_MULTI_CACHELINE;
17042 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17043 goal = BOUNDARY_SINGLE_CACHELINE;
17049 if (tg3_flag(tp, 57765_PLUS)) {
17050 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17057 /* PCI controllers on most RISC systems tend to disconnect
17058 * when a device tries to burst across a cache-line boundary.
17059 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17061 * Unfortunately, for PCI-E there are only limited
17062 * write-side controls for this, and thus for reads
17063 * we will still get the disconnects. We'll also waste
17064 * these PCI cycles for both read and write for chips
17065 * other than 5700 and 5701 which do not implement the
17068 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17069 switch (cacheline_size) {
17074 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17075 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17076 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17078 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17079 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17084 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17085 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17089 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17090 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17093 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17094 switch (cacheline_size) {
17098 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17099 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17100 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17106 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17107 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17111 switch (cacheline_size) {
17113 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17114 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17115 DMA_RWCTRL_WRITE_BNDRY_16);
17120 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17121 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17122 DMA_RWCTRL_WRITE_BNDRY_32);
17127 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17128 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17129 DMA_RWCTRL_WRITE_BNDRY_64);
17134 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17135 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17136 DMA_RWCTRL_WRITE_BNDRY_128);
17141 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17142 DMA_RWCTRL_WRITE_BNDRY_256);
17145 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17146 DMA_RWCTRL_WRITE_BNDRY_512);
17150 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17151 DMA_RWCTRL_WRITE_BNDRY_1024);
17160 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17161 int size, bool to_device)
17163 struct tg3_internal_buffer_desc test_desc;
17164 u32 sram_dma_descs;
17167 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17169 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17170 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17171 tw32(RDMAC_STATUS, 0);
17172 tw32(WDMAC_STATUS, 0);
17174 tw32(BUFMGR_MODE, 0);
17175 tw32(FTQ_RESET, 0);
17177 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17178 test_desc.addr_lo = buf_dma & 0xffffffff;
17179 test_desc.nic_mbuf = 0x00002100;
17180 test_desc.len = size;
17183 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17184 * the *second* time the tg3 driver was getting loaded after an
17187 * Broadcom tells me:
17188 * ...the DMA engine is connected to the GRC block and a DMA
17189 * reset may affect the GRC block in some unpredictable way...
17190 * The behavior of resets to individual blocks has not been tested.
17192 * Broadcom noted the GRC reset will also reset all sub-components.
17195 test_desc.cqid_sqid = (13 << 8) | 2;
17197 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17200 test_desc.cqid_sqid = (16 << 8) | 7;
17202 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17205 test_desc.flags = 0x00000005;
17207 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17210 val = *(((u32 *)&test_desc) + i);
17211 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17212 sram_dma_descs + (i * sizeof(u32)));
17213 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17215 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17218 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17220 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17223 for (i = 0; i < 40; i++) {
17227 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17229 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17230 if ((val & 0xffff) == sram_dma_descs) {
17241 #define TEST_BUFFER_SIZE 0x2000
17243 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17244 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17248 static int tg3_test_dma(struct tg3 *tp)
17250 dma_addr_t buf_dma;
17251 u32 *buf, saved_dma_rwctrl;
17254 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17255 &buf_dma, GFP_KERNEL);
17261 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17262 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17264 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17266 if (tg3_flag(tp, 57765_PLUS))
17269 if (tg3_flag(tp, PCI_EXPRESS)) {
17270 /* DMA read watermark not used on PCIE */
17271 tp->dma_rwctrl |= 0x00180000;
17272 } else if (!tg3_flag(tp, PCIX_MODE)) {
17273 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17274 tg3_asic_rev(tp) == ASIC_REV_5750)
17275 tp->dma_rwctrl |= 0x003f0000;
17277 tp->dma_rwctrl |= 0x003f000f;
17279 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17280 tg3_asic_rev(tp) == ASIC_REV_5704) {
17281 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17282 u32 read_water = 0x7;
17284 /* If the 5704 is behind the EPB bridge, we can
17285 * do the less restrictive ONE_DMA workaround for
17286 * better performance.
17288 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17289 tg3_asic_rev(tp) == ASIC_REV_5704)
17290 tp->dma_rwctrl |= 0x8000;
17291 else if (ccval == 0x6 || ccval == 0x7)
17292 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17294 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17296 /* Set bit 23 to enable PCIX hw bug fix */
17298 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17299 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17301 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17302 /* 5780 always in PCIX mode */
17303 tp->dma_rwctrl |= 0x00144000;
17304 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17305 /* 5714 always in PCIX mode */
17306 tp->dma_rwctrl |= 0x00148000;
17308 tp->dma_rwctrl |= 0x001b000f;
17311 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17312 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17314 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17315 tg3_asic_rev(tp) == ASIC_REV_5704)
17316 tp->dma_rwctrl &= 0xfffffff0;
17318 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17319 tg3_asic_rev(tp) == ASIC_REV_5701) {
17320 /* Remove this if it causes problems for some boards. */
17321 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17323 /* On 5700/5701 chips, we need to set this bit.
17324 * Otherwise the chip will issue cacheline transactions
17325 * to streamable DMA memory with not all the byte
17326 * enables turned on. This is an error on several
17327 * RISC PCI controllers, in particular sparc64.
17329 * On 5703/5704 chips, this bit has been reassigned
17330 * a different meaning. In particular, it is used
17331 * on those chips to enable a PCI-X workaround.
17333 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17336 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17339 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17340 tg3_asic_rev(tp) != ASIC_REV_5701)
17343 /* It is best to perform DMA test with maximum write burst size
17344 * to expose the 5700/5701 write DMA bug.
17346 saved_dma_rwctrl = tp->dma_rwctrl;
17347 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17348 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17353 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17356 /* Send the buffer to the chip. */
17357 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17359 dev_err(&tp->pdev->dev,
17360 "%s: Buffer write failed. err = %d\n",
17365 /* Now read it back. */
17366 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17368 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17369 "err = %d\n", __func__, ret);
17374 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17378 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17379 DMA_RWCTRL_WRITE_BNDRY_16) {
17380 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17381 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17382 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17385 dev_err(&tp->pdev->dev,
17386 "%s: Buffer corrupted on read back! "
17387 "(%d != %d)\n", __func__, p[i], i);
17393 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17399 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17400 DMA_RWCTRL_WRITE_BNDRY_16) {
17401 /* DMA test passed without adjusting DMA boundary,
17402 * now look for chipsets that are known to expose the
17403 * DMA bug without failing the test.
17405 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17406 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17407 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17409 /* Safe to use the calculated DMA boundary. */
17410 tp->dma_rwctrl = saved_dma_rwctrl;
17413 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17417 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17422 static void tg3_init_bufmgr_config(struct tg3 *tp)
17424 if (tg3_flag(tp, 57765_PLUS)) {
17425 tp->bufmgr_config.mbuf_read_dma_low_water =
17426 DEFAULT_MB_RDMA_LOW_WATER_5705;
17427 tp->bufmgr_config.mbuf_mac_rx_low_water =
17428 DEFAULT_MB_MACRX_LOW_WATER_57765;
17429 tp->bufmgr_config.mbuf_high_water =
17430 DEFAULT_MB_HIGH_WATER_57765;
17432 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17433 DEFAULT_MB_RDMA_LOW_WATER_5705;
17434 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17435 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17436 tp->bufmgr_config.mbuf_high_water_jumbo =
17437 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17438 } else if (tg3_flag(tp, 5705_PLUS)) {
17439 tp->bufmgr_config.mbuf_read_dma_low_water =
17440 DEFAULT_MB_RDMA_LOW_WATER_5705;
17441 tp->bufmgr_config.mbuf_mac_rx_low_water =
17442 DEFAULT_MB_MACRX_LOW_WATER_5705;
17443 tp->bufmgr_config.mbuf_high_water =
17444 DEFAULT_MB_HIGH_WATER_5705;
17445 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17446 tp->bufmgr_config.mbuf_mac_rx_low_water =
17447 DEFAULT_MB_MACRX_LOW_WATER_5906;
17448 tp->bufmgr_config.mbuf_high_water =
17449 DEFAULT_MB_HIGH_WATER_5906;
17452 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17453 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17454 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17455 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17456 tp->bufmgr_config.mbuf_high_water_jumbo =
17457 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17459 tp->bufmgr_config.mbuf_read_dma_low_water =
17460 DEFAULT_MB_RDMA_LOW_WATER;
17461 tp->bufmgr_config.mbuf_mac_rx_low_water =
17462 DEFAULT_MB_MACRX_LOW_WATER;
17463 tp->bufmgr_config.mbuf_high_water =
17464 DEFAULT_MB_HIGH_WATER;
17466 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17467 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17468 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17469 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17470 tp->bufmgr_config.mbuf_high_water_jumbo =
17471 DEFAULT_MB_HIGH_WATER_JUMBO;
17474 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17475 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17478 static char *tg3_phy_string(struct tg3 *tp)
17480 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17481 case TG3_PHY_ID_BCM5400: return "5400";
17482 case TG3_PHY_ID_BCM5401: return "5401";
17483 case TG3_PHY_ID_BCM5411: return "5411";
17484 case TG3_PHY_ID_BCM5701: return "5701";
17485 case TG3_PHY_ID_BCM5703: return "5703";
17486 case TG3_PHY_ID_BCM5704: return "5704";
17487 case TG3_PHY_ID_BCM5705: return "5705";
17488 case TG3_PHY_ID_BCM5750: return "5750";
17489 case TG3_PHY_ID_BCM5752: return "5752";
17490 case TG3_PHY_ID_BCM5714: return "5714";
17491 case TG3_PHY_ID_BCM5780: return "5780";
17492 case TG3_PHY_ID_BCM5755: return "5755";
17493 case TG3_PHY_ID_BCM5787: return "5787";
17494 case TG3_PHY_ID_BCM5784: return "5784";
17495 case TG3_PHY_ID_BCM5756: return "5722/5756";
17496 case TG3_PHY_ID_BCM5906: return "5906";
17497 case TG3_PHY_ID_BCM5761: return "5761";
17498 case TG3_PHY_ID_BCM5718C: return "5718C";
17499 case TG3_PHY_ID_BCM5718S: return "5718S";
17500 case TG3_PHY_ID_BCM57765: return "57765";
17501 case TG3_PHY_ID_BCM5719C: return "5719C";
17502 case TG3_PHY_ID_BCM5720C: return "5720C";
17503 case TG3_PHY_ID_BCM5762: return "5762C";
17504 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17505 case 0: return "serdes";
17506 default: return "unknown";
17510 static char *tg3_bus_string(struct tg3 *tp, char *str)
17512 if (tg3_flag(tp, PCI_EXPRESS)) {
17513 strcpy(str, "PCI Express");
17515 } else if (tg3_flag(tp, PCIX_MODE)) {
17516 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17518 strcpy(str, "PCIX:");
17520 if ((clock_ctrl == 7) ||
17521 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17522 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17523 strcat(str, "133MHz");
17524 else if (clock_ctrl == 0)
17525 strcat(str, "33MHz");
17526 else if (clock_ctrl == 2)
17527 strcat(str, "50MHz");
17528 else if (clock_ctrl == 4)
17529 strcat(str, "66MHz");
17530 else if (clock_ctrl == 6)
17531 strcat(str, "100MHz");
17533 strcpy(str, "PCI:");
17534 if (tg3_flag(tp, PCI_HIGH_SPEED))
17535 strcat(str, "66MHz");
17537 strcat(str, "33MHz");
17539 if (tg3_flag(tp, PCI_32BIT))
17540 strcat(str, ":32-bit");
17542 strcat(str, ":64-bit");
17546 static void tg3_init_coal(struct tg3 *tp)
17548 struct ethtool_coalesce *ec = &tp->coal;
17550 memset(ec, 0, sizeof(*ec));
17551 ec->cmd = ETHTOOL_GCOALESCE;
17552 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17553 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17554 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17555 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17556 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17557 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17558 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17559 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17560 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17562 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17563 HOSTCC_MODE_CLRTICK_TXBD)) {
17564 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17565 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17566 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17567 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17570 if (tg3_flag(tp, 5705_PLUS)) {
17571 ec->rx_coalesce_usecs_irq = 0;
17572 ec->tx_coalesce_usecs_irq = 0;
17573 ec->stats_block_coalesce_usecs = 0;
17577 static int tg3_init_one(struct pci_dev *pdev,
17578 const struct pci_device_id *ent)
17580 struct net_device *dev;
17583 u32 sndmbx, rcvmbx, intmbx;
17585 u64 dma_mask, persist_dma_mask;
17586 netdev_features_t features = 0;
17588 printk_once(KERN_INFO "%s\n", version);
17590 err = pci_enable_device(pdev);
17592 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17596 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17598 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17599 goto err_out_disable_pdev;
17602 pci_set_master(pdev);
17604 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17607 goto err_out_free_res;
17610 SET_NETDEV_DEV(dev, &pdev->dev);
17612 tp = netdev_priv(dev);
17615 tp->rx_mode = TG3_DEF_RX_MODE;
17616 tp->tx_mode = TG3_DEF_TX_MODE;
17618 tp->pcierr_recovery = false;
17621 tp->msg_enable = tg3_debug;
17623 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17625 if (pdev_is_ssb_gige_core(pdev)) {
17626 tg3_flag_set(tp, IS_SSB_CORE);
17627 if (ssb_gige_must_flush_posted_writes(pdev))
17628 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17629 if (ssb_gige_one_dma_at_once(pdev))
17630 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17631 if (ssb_gige_have_roboswitch(pdev)) {
17632 tg3_flag_set(tp, USE_PHYLIB);
17633 tg3_flag_set(tp, ROBOSWITCH);
17635 if (ssb_gige_is_rgmii(pdev))
17636 tg3_flag_set(tp, RGMII_MODE);
17639 /* The word/byte swap controls here control register access byte
17640 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17643 tp->misc_host_ctrl =
17644 MISC_HOST_CTRL_MASK_PCI_INT |
17645 MISC_HOST_CTRL_WORD_SWAP |
17646 MISC_HOST_CTRL_INDIR_ACCESS |
17647 MISC_HOST_CTRL_PCISTATE_RW;
17649 /* The NONFRM (non-frame) byte/word swap controls take effect
17650 * on descriptor entries, anything which isn't packet data.
17652 * The StrongARM chips on the board (one for tx, one for rx)
17653 * are running in big-endian mode.
17655 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17656 GRC_MODE_WSWAP_NONFRM_DATA);
17657 #ifdef __BIG_ENDIAN
17658 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17660 spin_lock_init(&tp->lock);
17661 spin_lock_init(&tp->indirect_lock);
17662 INIT_WORK(&tp->reset_task, tg3_reset_task);
17664 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17666 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17668 goto err_out_free_dev;
17671 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17672 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17674 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17675 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17676 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17678 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17679 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17686 tg3_flag_set(tp, ENABLE_APE);
17687 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17688 if (!tp->aperegs) {
17689 dev_err(&pdev->dev,
17690 "Cannot map APE registers, aborting\n");
17692 goto err_out_iounmap;
17696 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17697 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17699 dev->ethtool_ops = &tg3_ethtool_ops;
17700 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17701 dev->netdev_ops = &tg3_netdev_ops;
17702 dev->irq = pdev->irq;
17704 err = tg3_get_invariants(tp, ent);
17706 dev_err(&pdev->dev,
17707 "Problem fetching invariants of chip, aborting\n");
17708 goto err_out_apeunmap;
17711 /* The EPB bridge inside 5714, 5715, and 5780 and any
17712 * device behind the EPB cannot support DMA addresses > 40-bit.
17713 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17714 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17715 * do DMA address check in tg3_start_xmit().
17717 if (tg3_flag(tp, IS_5788))
17718 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17719 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17720 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17721 #ifdef CONFIG_HIGHMEM
17722 dma_mask = DMA_BIT_MASK(64);
17725 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17727 /* Configure DMA attributes. */
17728 if (dma_mask > DMA_BIT_MASK(32)) {
17729 err = pci_set_dma_mask(pdev, dma_mask);
17731 features |= NETIF_F_HIGHDMA;
17732 err = pci_set_consistent_dma_mask(pdev,
17735 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17736 "DMA for consistent allocations\n");
17737 goto err_out_apeunmap;
17741 if (err || dma_mask == DMA_BIT_MASK(32)) {
17742 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17744 dev_err(&pdev->dev,
17745 "No usable DMA configuration, aborting\n");
17746 goto err_out_apeunmap;
17750 tg3_init_bufmgr_config(tp);
17752 /* 5700 B0 chips do not support checksumming correctly due
17753 * to hardware bugs.
17755 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17756 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17758 if (tg3_flag(tp, 5755_PLUS))
17759 features |= NETIF_F_IPV6_CSUM;
17762 /* TSO is on by default on chips that support hardware TSO.
17763 * Firmware TSO on older chips gives lower performance, so it
17764 * is off by default, but can be enabled using ethtool.
17766 if ((tg3_flag(tp, HW_TSO_1) ||
17767 tg3_flag(tp, HW_TSO_2) ||
17768 tg3_flag(tp, HW_TSO_3)) &&
17769 (features & NETIF_F_IP_CSUM))
17770 features |= NETIF_F_TSO;
17771 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17772 if (features & NETIF_F_IPV6_CSUM)
17773 features |= NETIF_F_TSO6;
17774 if (tg3_flag(tp, HW_TSO_3) ||
17775 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17776 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17777 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17778 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17779 tg3_asic_rev(tp) == ASIC_REV_57780)
17780 features |= NETIF_F_TSO_ECN;
17783 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17784 NETIF_F_HW_VLAN_CTAG_RX;
17785 dev->vlan_features |= features;
17788 * Add loopback capability only for a subset of devices that support
17789 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17790 * loopback for the remaining devices.
17792 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17793 !tg3_flag(tp, CPMU_PRESENT))
17794 /* Add the loopback capability */
17795 features |= NETIF_F_LOOPBACK;
17797 dev->hw_features |= features;
17798 dev->priv_flags |= IFF_UNICAST_FLT;
17800 /* MTU range: 60 - 9000 or 1500, depending on hardware */
17801 dev->min_mtu = TG3_MIN_MTU;
17802 dev->max_mtu = TG3_MAX_MTU(tp);
17804 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17805 !tg3_flag(tp, TSO_CAPABLE) &&
17806 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17807 tg3_flag_set(tp, MAX_RXPEND_64);
17808 tp->rx_pending = 63;
17811 err = tg3_get_device_address(tp);
17813 dev_err(&pdev->dev,
17814 "Could not obtain valid ethernet address, aborting\n");
17815 goto err_out_apeunmap;
17818 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17819 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17820 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17821 for (i = 0; i < tp->irq_max; i++) {
17822 struct tg3_napi *tnapi = &tp->napi[i];
17825 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17827 tnapi->int_mbox = intmbx;
17833 tnapi->consmbox = rcvmbx;
17834 tnapi->prodmbox = sndmbx;
17837 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17839 tnapi->coal_now = HOSTCC_MODE_NOW;
17841 if (!tg3_flag(tp, SUPPORT_MSIX))
17845 * If we support MSIX, we'll be using RSS. If we're using
17846 * RSS, the first vector only handles link interrupts and the
17847 * remaining vectors handle rx and tx interrupts. Reuse the
17848 * mailbox values for the next iteration. The values we setup
17849 * above are still useful for the single vectored mode.
17863 * Reset chip in case UNDI or EFI driver did not shutdown
17864 * DMA self test will enable WDMAC and we'll see (spurious)
17865 * pending DMA on the PCI bus at that point.
17867 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17868 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17869 tg3_full_lock(tp, 0);
17870 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17871 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17872 tg3_full_unlock(tp);
17875 err = tg3_test_dma(tp);
17877 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17878 goto err_out_apeunmap;
17883 pci_set_drvdata(pdev, dev);
17885 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17886 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17887 tg3_asic_rev(tp) == ASIC_REV_5762)
17888 tg3_flag_set(tp, PTP_CAPABLE);
17890 tg3_timer_init(tp);
17892 tg3_carrier_off(tp);
17894 err = register_netdev(dev);
17896 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17897 goto err_out_apeunmap;
17900 if (tg3_flag(tp, PTP_CAPABLE)) {
17902 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17904 if (IS_ERR(tp->ptp_clock))
17905 tp->ptp_clock = NULL;
17908 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17909 tp->board_part_number,
17910 tg3_chip_rev_id(tp),
17911 tg3_bus_string(tp, str),
17914 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
17917 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17918 ethtype = "10/100Base-TX";
17919 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17920 ethtype = "1000Base-SX";
17922 ethtype = "10/100/1000Base-T";
17924 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17925 "(WireSpeed[%d], EEE[%d])\n",
17926 tg3_phy_string(tp), ethtype,
17927 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17928 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17931 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17932 (dev->features & NETIF_F_RXCSUM) != 0,
17933 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17934 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17935 tg3_flag(tp, ENABLE_ASF) != 0,
17936 tg3_flag(tp, TSO_CAPABLE) != 0);
17937 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17939 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17940 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17942 pci_save_state(pdev);
17948 iounmap(tp->aperegs);
17949 tp->aperegs = NULL;
17962 pci_release_regions(pdev);
17964 err_out_disable_pdev:
17965 if (pci_is_enabled(pdev))
17966 pci_disable_device(pdev);
17970 static void tg3_remove_one(struct pci_dev *pdev)
17972 struct net_device *dev = pci_get_drvdata(pdev);
17975 struct tg3 *tp = netdev_priv(dev);
17979 release_firmware(tp->fw);
17981 tg3_reset_task_cancel(tp);
17983 if (tg3_flag(tp, USE_PHYLIB)) {
17988 unregister_netdev(dev);
17990 iounmap(tp->aperegs);
17991 tp->aperegs = NULL;
17998 pci_release_regions(pdev);
17999 pci_disable_device(pdev);
18003 #ifdef CONFIG_PM_SLEEP
18004 static int tg3_suspend(struct device *device)
18006 struct pci_dev *pdev = to_pci_dev(device);
18007 struct net_device *dev = pci_get_drvdata(pdev);
18008 struct tg3 *tp = netdev_priv(dev);
18013 if (!netif_running(dev))
18016 tg3_reset_task_cancel(tp);
18018 tg3_netif_stop(tp);
18020 tg3_timer_stop(tp);
18022 tg3_full_lock(tp, 1);
18023 tg3_disable_ints(tp);
18024 tg3_full_unlock(tp);
18026 netif_device_detach(dev);
18028 tg3_full_lock(tp, 0);
18029 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18030 tg3_flag_clear(tp, INIT_COMPLETE);
18031 tg3_full_unlock(tp);
18033 err = tg3_power_down_prepare(tp);
18037 tg3_full_lock(tp, 0);
18039 tg3_flag_set(tp, INIT_COMPLETE);
18040 err2 = tg3_restart_hw(tp, true);
18044 tg3_timer_start(tp);
18046 netif_device_attach(dev);
18047 tg3_netif_start(tp);
18050 tg3_full_unlock(tp);
18061 static int tg3_resume(struct device *device)
18063 struct pci_dev *pdev = to_pci_dev(device);
18064 struct net_device *dev = pci_get_drvdata(pdev);
18065 struct tg3 *tp = netdev_priv(dev);
18070 if (!netif_running(dev))
18073 netif_device_attach(dev);
18075 tg3_full_lock(tp, 0);
18077 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18079 tg3_flag_set(tp, INIT_COMPLETE);
18080 err = tg3_restart_hw(tp,
18081 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18085 tg3_timer_start(tp);
18087 tg3_netif_start(tp);
18090 tg3_full_unlock(tp);
18099 #endif /* CONFIG_PM_SLEEP */
18101 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18103 static void tg3_shutdown(struct pci_dev *pdev)
18105 struct net_device *dev = pci_get_drvdata(pdev);
18106 struct tg3 *tp = netdev_priv(dev);
18109 netif_device_detach(dev);
18111 if (netif_running(dev))
18114 if (system_state == SYSTEM_POWER_OFF)
18115 tg3_power_down(tp);
18121 * tg3_io_error_detected - called when PCI error is detected
18122 * @pdev: Pointer to PCI device
18123 * @state: The current pci connection state
18125 * This function is called after a PCI bus error affecting
18126 * this device has been detected.
18128 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18129 pci_channel_state_t state)
18131 struct net_device *netdev = pci_get_drvdata(pdev);
18132 struct tg3 *tp = netdev_priv(netdev);
18133 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18135 netdev_info(netdev, "PCI I/O error detected\n");
18139 /* We probably don't have netdev yet */
18140 if (!netdev || !netif_running(netdev))
18143 /* We needn't recover from permanent error */
18144 if (state == pci_channel_io_frozen)
18145 tp->pcierr_recovery = true;
18149 tg3_netif_stop(tp);
18151 tg3_timer_stop(tp);
18153 /* Want to make sure that the reset task doesn't run */
18154 tg3_reset_task_cancel(tp);
18156 netif_device_detach(netdev);
18158 /* Clean up software state, even if MMIO is blocked */
18159 tg3_full_lock(tp, 0);
18160 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18161 tg3_full_unlock(tp);
18164 if (state == pci_channel_io_perm_failure) {
18166 tg3_napi_enable(tp);
18169 err = PCI_ERS_RESULT_DISCONNECT;
18171 pci_disable_device(pdev);
18180 * tg3_io_slot_reset - called after the pci bus has been reset.
18181 * @pdev: Pointer to PCI device
18183 * Restart the card from scratch, as if from a cold-boot.
18184 * At this point, the card has exprienced a hard reset,
18185 * followed by fixups by BIOS, and has its config space
18186 * set up identically to what it was at cold boot.
18188 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18190 struct net_device *netdev = pci_get_drvdata(pdev);
18191 struct tg3 *tp = netdev_priv(netdev);
18192 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18197 if (pci_enable_device(pdev)) {
18198 dev_err(&pdev->dev,
18199 "Cannot re-enable PCI device after reset.\n");
18203 pci_set_master(pdev);
18204 pci_restore_state(pdev);
18205 pci_save_state(pdev);
18207 if (!netdev || !netif_running(netdev)) {
18208 rc = PCI_ERS_RESULT_RECOVERED;
18212 err = tg3_power_up(tp);
18216 rc = PCI_ERS_RESULT_RECOVERED;
18219 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18220 tg3_napi_enable(tp);
18229 * tg3_io_resume - called when traffic can start flowing again.
18230 * @pdev: Pointer to PCI device
18232 * This callback is called when the error recovery driver tells
18233 * us that its OK to resume normal operation.
18235 static void tg3_io_resume(struct pci_dev *pdev)
18237 struct net_device *netdev = pci_get_drvdata(pdev);
18238 struct tg3 *tp = netdev_priv(netdev);
18243 if (!netdev || !netif_running(netdev))
18246 tg3_full_lock(tp, 0);
18247 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18248 tg3_flag_set(tp, INIT_COMPLETE);
18249 err = tg3_restart_hw(tp, true);
18251 tg3_full_unlock(tp);
18252 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18256 netif_device_attach(netdev);
18258 tg3_timer_start(tp);
18260 tg3_netif_start(tp);
18262 tg3_full_unlock(tp);
18267 tp->pcierr_recovery = false;
18271 static const struct pci_error_handlers tg3_err_handler = {
18272 .error_detected = tg3_io_error_detected,
18273 .slot_reset = tg3_io_slot_reset,
18274 .resume = tg3_io_resume
18277 static struct pci_driver tg3_driver = {
18278 .name = DRV_MODULE_NAME,
18279 .id_table = tg3_pci_tbl,
18280 .probe = tg3_init_one,
18281 .remove = tg3_remove_one,
18282 .err_handler = &tg3_err_handler,
18283 .driver.pm = &tg3_pm_ops,
18284 .shutdown = tg3_shutdown,
18287 module_pci_driver(tg3_driver);