2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/macb.h>
26 #include <linux/platform_device.h>
27 #include <linux/phy.h>
29 #include <linux/of_device.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/pinctrl/consumer.h>
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
55 * Graceful stop timeouts in us. We should allow up to
56 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 #define MACB_HALT_TIMEOUT 1230
60 /* Ring buffer accessors */
61 static unsigned int macb_tx_ring_wrap(unsigned int index)
63 return index & (TX_RING_SIZE - 1);
66 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68 return &bp->tx_ring[macb_tx_ring_wrap(index)];
71 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73 return &bp->tx_skb[macb_tx_ring_wrap(index)];
76 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
80 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82 return bp->tx_ring_dma + offset;
85 static unsigned int macb_rx_ring_wrap(unsigned int index)
87 return index & (RX_RING_SIZE - 1);
90 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92 return &bp->rx_ring[macb_rx_ring_wrap(index)];
95 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
100 void macb_set_hwaddr(struct macb *bp)
105 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
106 macb_or_gem_writel(bp, SA1B, bottom);
107 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
108 macb_or_gem_writel(bp, SA1T, top);
110 /* Clear unused address register sets */
111 macb_or_gem_writel(bp, SA2B, 0);
112 macb_or_gem_writel(bp, SA2T, 0);
113 macb_or_gem_writel(bp, SA3B, 0);
114 macb_or_gem_writel(bp, SA3T, 0);
115 macb_or_gem_writel(bp, SA4B, 0);
116 macb_or_gem_writel(bp, SA4T, 0);
118 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
120 void macb_get_hwaddr(struct macb *bp)
122 struct macb_platform_data *pdata;
128 pdata = dev_get_platdata(&bp->pdev->dev);
130 /* Check all 4 address register for vaild address */
131 for (i = 0; i < 4; i++) {
132 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
133 top = macb_or_gem_readl(bp, SA1T + i * 8);
135 if (pdata && pdata->rev_eth_addr) {
136 addr[5] = bottom & 0xff;
137 addr[4] = (bottom >> 8) & 0xff;
138 addr[3] = (bottom >> 16) & 0xff;
139 addr[2] = (bottom >> 24) & 0xff;
140 addr[1] = top & 0xff;
141 addr[0] = (top & 0xff00) >> 8;
143 addr[0] = bottom & 0xff;
144 addr[1] = (bottom >> 8) & 0xff;
145 addr[2] = (bottom >> 16) & 0xff;
146 addr[3] = (bottom >> 24) & 0xff;
147 addr[4] = top & 0xff;
148 addr[5] = (top >> 8) & 0xff;
151 if (is_valid_ether_addr(addr)) {
152 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 netdev_info(bp->dev, "invalid hw address, using random\n");
158 eth_hw_addr_random(bp->dev);
160 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
162 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
164 struct macb *bp = bus->priv;
167 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
168 | MACB_BF(RW, MACB_MAN_READ)
169 | MACB_BF(PHYA, mii_id)
170 | MACB_BF(REGA, regnum)
171 | MACB_BF(CODE, MACB_MAN_CODE)));
173 /* wait for end of transfer */
174 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
177 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
182 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
185 struct macb *bp = bus->priv;
187 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
188 | MACB_BF(RW, MACB_MAN_WRITE)
189 | MACB_BF(PHYA, mii_id)
190 | MACB_BF(REGA, regnum)
191 | MACB_BF(CODE, MACB_MAN_CODE)
192 | MACB_BF(DATA, value)));
194 /* wait for end of transfer */
195 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
201 static int macb_mdio_reset(struct mii_bus *bus)
206 static void macb_handle_link_change(struct net_device *dev)
208 struct macb *bp = netdev_priv(dev);
209 struct phy_device *phydev = bp->phy_dev;
212 int status_change = 0;
214 spin_lock_irqsave(&bp->lock, flags);
217 if ((bp->speed != phydev->speed) ||
218 (bp->duplex != phydev->duplex)) {
221 reg = macb_readl(bp, NCFGR);
222 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
224 reg &= ~GEM_BIT(GBE);
228 if (phydev->speed == SPEED_100)
229 reg |= MACB_BIT(SPD);
230 if (phydev->speed == SPEED_1000)
233 macb_or_gem_writel(bp, NCFGR, reg);
235 bp->speed = phydev->speed;
236 bp->duplex = phydev->duplex;
241 if (phydev->link != bp->link) {
246 bp->link = phydev->link;
251 spin_unlock_irqrestore(&bp->lock, flags);
255 netif_carrier_on(dev);
256 netdev_info(dev, "link up (%d/%s)\n",
258 phydev->duplex == DUPLEX_FULL ?
261 netif_carrier_off(dev);
262 netdev_info(dev, "link down\n");
267 /* based on au1000_eth. c*/
268 static int macb_mii_probe(struct net_device *dev)
270 struct macb *bp = netdev_priv(dev);
271 struct macb_platform_data *pdata;
272 struct phy_device *phydev;
276 phydev = phy_find_first(bp->mii_bus);
278 netdev_err(dev, "no PHY found\n");
282 pdata = dev_get_platdata(&bp->pdev->dev);
283 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
284 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
286 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
287 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
291 /* attach the mac to the phy */
292 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
295 netdev_err(dev, "Could not attach to PHY\n");
299 /* mask with MAC supported features */
301 phydev->supported &= PHY_GBIT_FEATURES;
303 phydev->supported &= PHY_BASIC_FEATURES;
305 phydev->advertising = phydev->supported;
310 bp->phy_dev = phydev;
315 int macb_mii_init(struct macb *bp)
317 struct macb_platform_data *pdata;
318 struct device_node *np;
321 /* Enable management port */
322 macb_writel(bp, NCR, MACB_BIT(MPE));
324 bp->mii_bus = mdiobus_alloc();
325 if (bp->mii_bus == NULL) {
330 bp->mii_bus->name = "MACB_mii_bus";
331 bp->mii_bus->read = &macb_mdio_read;
332 bp->mii_bus->write = &macb_mdio_write;
333 bp->mii_bus->reset = &macb_mdio_reset;
334 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
335 bp->pdev->name, bp->pdev->id);
336 bp->mii_bus->priv = bp;
337 bp->mii_bus->parent = &bp->dev->dev;
338 pdata = dev_get_platdata(&bp->pdev->dev);
340 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
341 if (!bp->mii_bus->irq) {
343 goto err_out_free_mdiobus;
346 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
348 np = bp->pdev->dev.of_node;
350 /* try dt phy registration */
351 err = of_mdiobus_register(bp->mii_bus, np);
353 /* fallback to standard phy registration if no phy were
354 found during dt phy registration */
355 if (!err && !phy_find_first(bp->mii_bus)) {
356 for (i = 0; i < PHY_MAX_ADDR; i++) {
357 struct phy_device *phydev;
359 phydev = mdiobus_scan(bp->mii_bus, i);
360 if (IS_ERR(phydev)) {
361 err = PTR_ERR(phydev);
367 goto err_out_unregister_bus;
370 for (i = 0; i < PHY_MAX_ADDR; i++)
371 bp->mii_bus->irq[i] = PHY_POLL;
374 bp->mii_bus->phy_mask = pdata->phy_mask;
376 err = mdiobus_register(bp->mii_bus);
380 goto err_out_free_mdio_irq;
382 err = macb_mii_probe(bp->dev);
384 goto err_out_unregister_bus;
388 err_out_unregister_bus:
389 mdiobus_unregister(bp->mii_bus);
390 err_out_free_mdio_irq:
391 kfree(bp->mii_bus->irq);
392 err_out_free_mdiobus:
393 mdiobus_free(bp->mii_bus);
397 EXPORT_SYMBOL_GPL(macb_mii_init);
399 static void macb_update_stats(struct macb *bp)
401 u32 __iomem *reg = bp->regs + MACB_PFR;
402 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
403 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
405 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
407 for(; p < end; p++, reg++)
408 *p += __raw_readl(reg);
411 static int macb_halt_tx(struct macb *bp)
413 unsigned long halt_time, timeout;
416 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
418 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
421 status = macb_readl(bp, TSR);
422 if (!(status & MACB_BIT(TGO)))
425 usleep_range(10, 250);
426 } while (time_before(halt_time, timeout));
431 static void macb_tx_error_task(struct work_struct *work)
433 struct macb *bp = container_of(work, struct macb, tx_error_task);
434 struct macb_tx_skb *tx_skb;
438 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
439 bp->tx_tail, bp->tx_head);
441 /* Make sure nobody is trying to queue up new packets */
442 netif_stop_queue(bp->dev);
445 * Stop transmission now
446 * (in case we have just queued new packets)
448 if (macb_halt_tx(bp))
449 /* Just complain for now, reinitializing TX path can be good */
450 netdev_err(bp->dev, "BUG: halt tx timed out\n");
452 /* No need for the lock here as nobody will interrupt us anymore */
455 * Treat frames in TX queue including the ones that caused the error.
456 * Free transmit buffers in upper layer.
458 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
459 struct macb_dma_desc *desc;
462 desc = macb_tx_desc(bp, tail);
464 tx_skb = macb_tx_skb(bp, tail);
467 if (ctrl & MACB_BIT(TX_USED)) {
468 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
469 macb_tx_ring_wrap(tail), skb->data);
470 bp->stats.tx_packets++;
471 bp->stats.tx_bytes += skb->len;
474 * "Buffers exhausted mid-frame" errors may only happen
475 * if the driver is buggy, so complain loudly about those.
476 * Statistics are updated by hardware.
478 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
480 "BUG: TX buffers exhausted mid-frame\n");
482 desc->ctrl = ctrl | MACB_BIT(TX_USED);
485 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
491 /* Make descriptor updates visible to hardware */
494 /* Reinitialize the TX desc queue */
495 macb_writel(bp, TBQP, bp->tx_ring_dma);
496 /* Make TX ring reflect state of hardware */
497 bp->tx_head = bp->tx_tail = 0;
499 /* Now we are ready to start transmission again */
500 netif_wake_queue(bp->dev);
502 /* Housework before enabling TX IRQ */
503 macb_writel(bp, TSR, macb_readl(bp, TSR));
504 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
507 static void macb_tx_interrupt(struct macb *bp)
513 status = macb_readl(bp, TSR);
514 macb_writel(bp, TSR, status);
516 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
517 macb_writel(bp, ISR, MACB_BIT(TCOMP));
519 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
520 (unsigned long)status);
523 for (tail = bp->tx_tail; tail != head; tail++) {
524 struct macb_tx_skb *tx_skb;
526 struct macb_dma_desc *desc;
529 desc = macb_tx_desc(bp, tail);
531 /* Make hw descriptor updates visible to CPU */
536 if (!(ctrl & MACB_BIT(TX_USED)))
539 tx_skb = macb_tx_skb(bp, tail);
542 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
543 macb_tx_ring_wrap(tail), skb->data);
544 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
546 bp->stats.tx_packets++;
547 bp->stats.tx_bytes += skb->len;
549 dev_kfree_skb_irq(skb);
553 if (netif_queue_stopped(bp->dev)
554 && CIRC_CNT(bp->tx_head, bp->tx_tail,
555 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
556 netif_wake_queue(bp->dev);
559 static void gem_rx_refill(struct macb *bp)
563 struct macb_dma_desc *desc;
566 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
569 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
570 desc = &bp->rx_ring[entry];
572 /* Make hw descriptor updates visible to CPU */
577 bp->rx_prepared_head++;
579 if ((addr & MACB_BIT(RX_USED)))
582 if (bp->rx_skbuff[entry] == NULL) {
583 /* allocate sk_buff for this free entry in ring */
584 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
585 if (unlikely(skb == NULL)) {
587 "Unable to allocate sk_buff\n");
590 bp->rx_skbuff[entry] = skb;
592 /* now fill corresponding descriptor entry */
593 paddr = dma_map_single(&bp->pdev->dev, skb->data,
594 bp->rx_buffer_size, DMA_FROM_DEVICE);
596 if (entry == RX_RING_SIZE - 1)
597 paddr |= MACB_BIT(RX_WRAP);
598 bp->rx_ring[entry].addr = paddr;
599 bp->rx_ring[entry].ctrl = 0;
601 /* properly align Ethernet header */
602 skb_reserve(skb, NET_IP_ALIGN);
606 /* Make descriptor updates visible to hardware */
609 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
610 bp->rx_prepared_head, bp->rx_tail);
613 /* Mark DMA descriptors from begin up to and not including end as unused */
614 static void discard_partial_frame(struct macb *bp, unsigned int begin,
619 for (frag = begin; frag != end; frag++) {
620 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
621 desc->addr &= ~MACB_BIT(RX_USED);
624 /* Make descriptor updates visible to hardware */
628 * When this happens, the hardware stats registers for
629 * whatever caused this is updated, so we don't have to record
634 static int gem_rx(struct macb *bp, int budget)
639 struct macb_dma_desc *desc;
642 while (count < budget) {
645 entry = macb_rx_ring_wrap(bp->rx_tail);
646 desc = &bp->rx_ring[entry];
648 /* Make hw descriptor updates visible to CPU */
654 if (!(addr & MACB_BIT(RX_USED)))
657 desc->addr &= ~MACB_BIT(RX_USED);
661 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
663 "not whole frame pointed by descriptor\n");
664 bp->stats.rx_dropped++;
667 skb = bp->rx_skbuff[entry];
668 if (unlikely(!skb)) {
670 "inconsistent Rx descriptor chain\n");
671 bp->stats.rx_dropped++;
674 /* now everything is ready for receiving packet */
675 bp->rx_skbuff[entry] = NULL;
676 len = MACB_BFEXT(RX_FRMLEN, ctrl);
678 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
681 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
682 dma_unmap_single(&bp->pdev->dev, addr,
683 len, DMA_FROM_DEVICE);
685 skb->protocol = eth_type_trans(skb, bp->dev);
686 skb_checksum_none_assert(skb);
688 bp->stats.rx_packets++;
689 bp->stats.rx_bytes += skb->len;
691 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
692 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
693 skb->len, skb->csum);
694 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
695 skb->mac_header, 16, true);
696 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
697 skb->data, 32, true);
700 netif_receive_skb(skb);
708 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
709 unsigned int last_frag)
715 struct macb_dma_desc *desc;
717 desc = macb_rx_desc(bp, last_frag);
718 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
720 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
721 macb_rx_ring_wrap(first_frag),
722 macb_rx_ring_wrap(last_frag), len);
725 * The ethernet header starts NET_IP_ALIGN bytes into the
726 * first buffer. Since the header is 14 bytes, this makes the
727 * payload word-aligned.
729 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
730 * the two padding bytes into the skb so that we avoid hitting
731 * the slowpath in memcpy(), and pull them off afterwards.
733 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
735 bp->stats.rx_dropped++;
736 for (frag = first_frag; ; frag++) {
737 desc = macb_rx_desc(bp, frag);
738 desc->addr &= ~MACB_BIT(RX_USED);
739 if (frag == last_frag)
743 /* Make descriptor updates visible to hardware */
751 skb_checksum_none_assert(skb);
754 for (frag = first_frag; ; frag++) {
755 unsigned int frag_len = bp->rx_buffer_size;
757 if (offset + frag_len > len) {
758 BUG_ON(frag != last_frag);
759 frag_len = len - offset;
761 skb_copy_to_linear_data_offset(skb, offset,
762 macb_rx_buffer(bp, frag), frag_len);
763 offset += bp->rx_buffer_size;
764 desc = macb_rx_desc(bp, frag);
765 desc->addr &= ~MACB_BIT(RX_USED);
767 if (frag == last_frag)
771 /* Make descriptor updates visible to hardware */
774 __skb_pull(skb, NET_IP_ALIGN);
775 skb->protocol = eth_type_trans(skb, bp->dev);
777 bp->stats.rx_packets++;
778 bp->stats.rx_bytes += skb->len;
779 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
780 skb->len, skb->csum);
781 netif_receive_skb(skb);
786 static int macb_rx(struct macb *bp, int budget)
792 for (tail = bp->rx_tail; budget > 0; tail++) {
793 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
796 /* Make hw descriptor updates visible to CPU */
802 if (!(addr & MACB_BIT(RX_USED)))
805 if (ctrl & MACB_BIT(RX_SOF)) {
806 if (first_frag != -1)
807 discard_partial_frame(bp, first_frag, tail);
811 if (ctrl & MACB_BIT(RX_EOF)) {
813 BUG_ON(first_frag == -1);
815 dropped = macb_rx_frame(bp, first_frag, tail);
824 if (first_frag != -1)
825 bp->rx_tail = first_frag;
832 static int macb_poll(struct napi_struct *napi, int budget)
834 struct macb *bp = container_of(napi, struct macb, napi);
838 status = macb_readl(bp, RSR);
839 macb_writel(bp, RSR, status);
843 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
844 (unsigned long)status, budget);
846 work_done = bp->macbgem_ops.mog_rx(bp, budget);
847 if (work_done < budget) {
851 * We've done what we can to clean the buffers. Make sure we
852 * get notified when new packets arrive.
854 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
856 /* Packets received while interrupts were disabled */
857 status = macb_readl(bp, RSR);
858 if (unlikely(status))
859 napi_reschedule(napi);
862 /* TODO: Handle errors */
867 static irqreturn_t macb_interrupt(int irq, void *dev_id)
869 struct net_device *dev = dev_id;
870 struct macb *bp = netdev_priv(dev);
873 status = macb_readl(bp, ISR);
875 if (unlikely(!status))
878 spin_lock(&bp->lock);
881 /* close possible race with dev_close */
882 if (unlikely(!netif_running(dev))) {
883 macb_writel(bp, IDR, -1);
887 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
889 if (status & MACB_RX_INT_FLAGS) {
891 * There's no point taking any more interrupts
892 * until we have processed the buffers. The
893 * scheduling call may fail if the poll routine
894 * is already scheduled, so disable interrupts
897 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
898 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
899 macb_writel(bp, ISR, MACB_BIT(RCOMP));
901 if (napi_schedule_prep(&bp->napi)) {
902 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
903 __napi_schedule(&bp->napi);
907 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
908 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
909 schedule_work(&bp->tx_error_task);
913 if (status & MACB_BIT(TCOMP))
914 macb_tx_interrupt(bp);
917 * Link change detection isn't possible with RMII, so we'll
918 * add that if/when we get our hands on a full-blown MII PHY.
921 if (status & MACB_BIT(ISR_ROVR)) {
922 /* We missed at least one packet */
924 bp->hw_stats.gem.rx_overruns++;
926 bp->hw_stats.macb.rx_overruns++;
929 if (status & MACB_BIT(HRESP)) {
931 * TODO: Reset the hardware, and maybe move the
932 * netdev_err to a lower-priority context as well
935 netdev_err(dev, "DMA bus error: HRESP not OK\n");
938 status = macb_readl(bp, ISR);
941 spin_unlock(&bp->lock);
946 #ifdef CONFIG_NET_POLL_CONTROLLER
948 * Polling receive - used by netconsole and other diagnostic tools
949 * to allow network i/o with interrupts disabled.
951 static void macb_poll_controller(struct net_device *dev)
955 local_irq_save(flags);
956 macb_interrupt(dev->irq, dev);
957 local_irq_restore(flags);
961 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
963 struct macb *bp = netdev_priv(dev);
965 unsigned int len, entry;
966 struct macb_dma_desc *desc;
967 struct macb_tx_skb *tx_skb;
971 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
973 "start_xmit: len %u head %p data %p tail %p end %p\n",
974 skb->len, skb->head, skb->data,
975 skb_tail_pointer(skb), skb_end_pointer(skb));
976 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
977 skb->data, 16, true);
981 spin_lock_irqsave(&bp->lock, flags);
983 /* This is a hard error, log it. */
984 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
985 netif_stop_queue(dev);
986 spin_unlock_irqrestore(&bp->lock, flags);
987 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
988 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
989 bp->tx_head, bp->tx_tail);
990 return NETDEV_TX_BUSY;
993 entry = macb_tx_ring_wrap(bp->tx_head);
995 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
996 mapping = dma_map_single(&bp->pdev->dev, skb->data,
999 tx_skb = &bp->tx_skb[entry];
1001 tx_skb->mapping = mapping;
1002 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1003 skb->data, (unsigned long)mapping);
1005 ctrl = MACB_BF(TX_FRMLEN, len);
1006 ctrl |= MACB_BIT(TX_LAST);
1007 if (entry == (TX_RING_SIZE - 1))
1008 ctrl |= MACB_BIT(TX_WRAP);
1010 desc = &bp->tx_ring[entry];
1011 desc->addr = mapping;
1014 /* Make newly initialized descriptor visible to hardware */
1017 skb_tx_timestamp(skb);
1019 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1021 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1022 netif_stop_queue(dev);
1024 spin_unlock_irqrestore(&bp->lock, flags);
1026 return NETDEV_TX_OK;
1029 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1031 if (!macb_is_gem(bp)) {
1032 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1034 bp->rx_buffer_size = size;
1036 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1038 "RX buffer must be multiple of %d bytes, expanding\n",
1039 RX_BUFFER_MULTIPLE);
1040 bp->rx_buffer_size =
1041 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1045 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1046 bp->dev->mtu, bp->rx_buffer_size);
1049 static void gem_free_rx_buffers(struct macb *bp)
1051 struct sk_buff *skb;
1052 struct macb_dma_desc *desc;
1059 for (i = 0; i < RX_RING_SIZE; i++) {
1060 skb = bp->rx_skbuff[i];
1065 desc = &bp->rx_ring[i];
1066 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1067 dma_unmap_single(&bp->pdev->dev, addr, skb->len,
1069 dev_kfree_skb_any(skb);
1073 kfree(bp->rx_skbuff);
1074 bp->rx_skbuff = NULL;
1077 static void macb_free_rx_buffers(struct macb *bp)
1079 if (bp->rx_buffers) {
1080 dma_free_coherent(&bp->pdev->dev,
1081 RX_RING_SIZE * bp->rx_buffer_size,
1082 bp->rx_buffers, bp->rx_buffers_dma);
1083 bp->rx_buffers = NULL;
1087 static void macb_free_consistent(struct macb *bp)
1093 bp->macbgem_ops.mog_free_rx_buffers(bp);
1095 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1096 bp->rx_ring, bp->rx_ring_dma);
1100 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1101 bp->tx_ring, bp->tx_ring_dma);
1106 static int gem_alloc_rx_buffers(struct macb *bp)
1110 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1111 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1116 "Allocated %d RX struct sk_buff entries at %p\n",
1117 RX_RING_SIZE, bp->rx_skbuff);
1121 static int macb_alloc_rx_buffers(struct macb *bp)
1125 size = RX_RING_SIZE * bp->rx_buffer_size;
1126 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1127 &bp->rx_buffers_dma, GFP_KERNEL);
1128 if (!bp->rx_buffers)
1132 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1133 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1137 static int macb_alloc_consistent(struct macb *bp)
1141 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1142 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1146 size = RX_RING_BYTES;
1147 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1148 &bp->rx_ring_dma, GFP_KERNEL);
1152 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1153 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1155 size = TX_RING_BYTES;
1156 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1157 &bp->tx_ring_dma, GFP_KERNEL);
1161 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1162 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1164 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1170 macb_free_consistent(bp);
1174 static void gem_init_rings(struct macb *bp)
1178 for (i = 0; i < TX_RING_SIZE; i++) {
1179 bp->tx_ring[i].addr = 0;
1180 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1182 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1184 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1189 static void macb_init_rings(struct macb *bp)
1194 addr = bp->rx_buffers_dma;
1195 for (i = 0; i < RX_RING_SIZE; i++) {
1196 bp->rx_ring[i].addr = addr;
1197 bp->rx_ring[i].ctrl = 0;
1198 addr += bp->rx_buffer_size;
1200 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1202 for (i = 0; i < TX_RING_SIZE; i++) {
1203 bp->tx_ring[i].addr = 0;
1204 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1206 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1208 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1211 static void macb_reset_hw(struct macb *bp)
1214 * Disable RX and TX (XXX: Should we halt the transmission
1217 macb_writel(bp, NCR, 0);
1219 /* Clear the stats registers (XXX: Update stats first?) */
1220 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1222 /* Clear all status flags */
1223 macb_writel(bp, TSR, -1);
1224 macb_writel(bp, RSR, -1);
1226 /* Disable all interrupts */
1227 macb_writel(bp, IDR, -1);
1228 macb_readl(bp, ISR);
1231 static u32 gem_mdc_clk_div(struct macb *bp)
1234 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1236 if (pclk_hz <= 20000000)
1237 config = GEM_BF(CLK, GEM_CLK_DIV8);
1238 else if (pclk_hz <= 40000000)
1239 config = GEM_BF(CLK, GEM_CLK_DIV16);
1240 else if (pclk_hz <= 80000000)
1241 config = GEM_BF(CLK, GEM_CLK_DIV32);
1242 else if (pclk_hz <= 120000000)
1243 config = GEM_BF(CLK, GEM_CLK_DIV48);
1244 else if (pclk_hz <= 160000000)
1245 config = GEM_BF(CLK, GEM_CLK_DIV64);
1247 config = GEM_BF(CLK, GEM_CLK_DIV96);
1252 static u32 macb_mdc_clk_div(struct macb *bp)
1255 unsigned long pclk_hz;
1257 if (macb_is_gem(bp))
1258 return gem_mdc_clk_div(bp);
1260 pclk_hz = clk_get_rate(bp->pclk);
1261 if (pclk_hz <= 20000000)
1262 config = MACB_BF(CLK, MACB_CLK_DIV8);
1263 else if (pclk_hz <= 40000000)
1264 config = MACB_BF(CLK, MACB_CLK_DIV16);
1265 else if (pclk_hz <= 80000000)
1266 config = MACB_BF(CLK, MACB_CLK_DIV32);
1268 config = MACB_BF(CLK, MACB_CLK_DIV64);
1274 * Get the DMA bus width field of the network configuration register that we
1275 * should program. We find the width from decoding the design configuration
1276 * register to find the maximum supported data bus width.
1278 static u32 macb_dbw(struct macb *bp)
1280 if (!macb_is_gem(bp))
1283 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1285 return GEM_BF(DBW, GEM_DBW128);
1287 return GEM_BF(DBW, GEM_DBW64);
1290 return GEM_BF(DBW, GEM_DBW32);
1295 * Configure the receive DMA engine
1296 * - use the correct receive buffer size
1297 * - set the possibility to use INCR16 bursts
1298 * (if not supported by FIFO, it will fallback to default)
1299 * - set both rx/tx packet buffers to full memory size
1300 * These are configurable parameters for GEM.
1302 static void macb_configure_dma(struct macb *bp)
1306 if (macb_is_gem(bp)) {
1307 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1308 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1309 dmacfg |= GEM_BF(FBLDO, 16);
1310 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1311 dmacfg &= ~GEM_BIT(ENDIA);
1312 gem_writel(bp, DMACFG, dmacfg);
1317 * Configure peripheral capacities according to integration options used
1319 static void macb_configure_caps(struct macb *bp)
1321 if (macb_is_gem(bp)) {
1322 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1323 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1327 static void macb_init_hw(struct macb *bp)
1332 macb_set_hwaddr(bp);
1334 config = macb_mdc_clk_div(bp);
1335 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1336 config |= MACB_BIT(PAE); /* PAuse Enable */
1337 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1338 config |= MACB_BIT(BIG); /* Receive oversized frames */
1339 if (bp->dev->flags & IFF_PROMISC)
1340 config |= MACB_BIT(CAF); /* Copy All Frames */
1341 if (!(bp->dev->flags & IFF_BROADCAST))
1342 config |= MACB_BIT(NBC); /* No BroadCast */
1343 config |= macb_dbw(bp);
1344 macb_writel(bp, NCFGR, config);
1345 bp->speed = SPEED_10;
1346 bp->duplex = DUPLEX_HALF;
1348 macb_configure_dma(bp);
1349 macb_configure_caps(bp);
1351 /* Initialize TX and RX buffers */
1352 macb_writel(bp, RBQP, bp->rx_ring_dma);
1353 macb_writel(bp, TBQP, bp->tx_ring_dma);
1355 /* Enable TX and RX */
1356 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1358 /* Enable interrupts */
1359 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1361 | MACB_BIT(HRESP)));
1366 * The hash address register is 64 bits long and takes up two
1367 * locations in the memory map. The least significant bits are stored
1368 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1370 * The unicast hash enable and the multicast hash enable bits in the
1371 * network configuration register enable the reception of hash matched
1372 * frames. The destination address is reduced to a 6 bit index into
1373 * the 64 bit hash register using the following hash function. The
1374 * hash function is an exclusive or of every sixth bit of the
1375 * destination address.
1377 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1378 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1379 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1380 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1381 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1382 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1384 * da[0] represents the least significant bit of the first byte
1385 * received, that is, the multicast/unicast indicator, and da[47]
1386 * represents the most significant bit of the last byte received. If
1387 * the hash index, hi[n], points to a bit that is set in the hash
1388 * register then the frame will be matched according to whether the
1389 * frame is multicast or unicast. A multicast match will be signalled
1390 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1391 * index points to a bit set in the hash register. A unicast match
1392 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1393 * and the hash index points to a bit set in the hash register. To
1394 * receive all multicast frames, the hash register should be set with
1395 * all ones and the multicast hash enable bit should be set in the
1396 * network configuration register.
1399 static inline int hash_bit_value(int bitnr, __u8 *addr)
1401 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1407 * Return the hash index value for the specified address.
1409 static int hash_get_index(__u8 *addr)
1414 for (j = 0; j < 6; j++) {
1415 for (i = 0, bitval = 0; i < 8; i++)
1416 bitval ^= hash_bit_value(i*6 + j, addr);
1418 hash_index |= (bitval << j);
1425 * Add multicast addresses to the internal multicast-hash table.
1427 static void macb_sethashtable(struct net_device *dev)
1429 struct netdev_hw_addr *ha;
1430 unsigned long mc_filter[2];
1432 struct macb *bp = netdev_priv(dev);
1434 mc_filter[0] = mc_filter[1] = 0;
1436 netdev_for_each_mc_addr(ha, dev) {
1437 bitnr = hash_get_index(ha->addr);
1438 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1441 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1442 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1446 * Enable/Disable promiscuous and multicast modes.
1448 void macb_set_rx_mode(struct net_device *dev)
1451 struct macb *bp = netdev_priv(dev);
1453 cfg = macb_readl(bp, NCFGR);
1455 if (dev->flags & IFF_PROMISC)
1456 /* Enable promiscuous mode */
1457 cfg |= MACB_BIT(CAF);
1458 else if (dev->flags & (~IFF_PROMISC))
1459 /* Disable promiscuous mode */
1460 cfg &= ~MACB_BIT(CAF);
1462 if (dev->flags & IFF_ALLMULTI) {
1463 /* Enable all multicast mode */
1464 macb_or_gem_writel(bp, HRB, -1);
1465 macb_or_gem_writel(bp, HRT, -1);
1466 cfg |= MACB_BIT(NCFGR_MTI);
1467 } else if (!netdev_mc_empty(dev)) {
1468 /* Enable specific multicasts */
1469 macb_sethashtable(dev);
1470 cfg |= MACB_BIT(NCFGR_MTI);
1471 } else if (dev->flags & (~IFF_ALLMULTI)) {
1472 /* Disable all multicast mode */
1473 macb_or_gem_writel(bp, HRB, 0);
1474 macb_or_gem_writel(bp, HRT, 0);
1475 cfg &= ~MACB_BIT(NCFGR_MTI);
1478 macb_writel(bp, NCFGR, cfg);
1480 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1482 static int macb_open(struct net_device *dev)
1484 struct macb *bp = netdev_priv(dev);
1485 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1488 netdev_dbg(bp->dev, "open\n");
1490 /* carrier starts down */
1491 netif_carrier_off(dev);
1493 /* if the phy is not yet register, retry later*/
1497 /* RX buffers initialization */
1498 macb_init_rx_buffer_size(bp, bufsz);
1500 err = macb_alloc_consistent(bp);
1502 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1507 napi_enable(&bp->napi);
1509 bp->macbgem_ops.mog_init_rings(bp);
1512 /* schedule a link state check */
1513 phy_start(bp->phy_dev);
1515 netif_start_queue(dev);
1520 static int macb_close(struct net_device *dev)
1522 struct macb *bp = netdev_priv(dev);
1523 unsigned long flags;
1525 netif_stop_queue(dev);
1526 napi_disable(&bp->napi);
1529 phy_stop(bp->phy_dev);
1531 spin_lock_irqsave(&bp->lock, flags);
1533 netif_carrier_off(dev);
1534 spin_unlock_irqrestore(&bp->lock, flags);
1536 macb_free_consistent(bp);
1541 static void gem_update_stats(struct macb *bp)
1543 u32 __iomem *reg = bp->regs + GEM_OTX;
1544 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1545 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1547 for (; p < end; p++, reg++)
1548 *p += __raw_readl(reg);
1551 static struct net_device_stats *gem_get_stats(struct macb *bp)
1553 struct gem_stats *hwstat = &bp->hw_stats.gem;
1554 struct net_device_stats *nstat = &bp->stats;
1556 gem_update_stats(bp);
1558 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1559 hwstat->rx_alignment_errors +
1560 hwstat->rx_resource_errors +
1561 hwstat->rx_overruns +
1562 hwstat->rx_oversize_frames +
1563 hwstat->rx_jabbers +
1564 hwstat->rx_undersized_frames +
1565 hwstat->rx_length_field_frame_errors);
1566 nstat->tx_errors = (hwstat->tx_late_collisions +
1567 hwstat->tx_excessive_collisions +
1568 hwstat->tx_underrun +
1569 hwstat->tx_carrier_sense_errors);
1570 nstat->multicast = hwstat->rx_multicast_frames;
1571 nstat->collisions = (hwstat->tx_single_collision_frames +
1572 hwstat->tx_multiple_collision_frames +
1573 hwstat->tx_excessive_collisions);
1574 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1575 hwstat->rx_jabbers +
1576 hwstat->rx_undersized_frames +
1577 hwstat->rx_length_field_frame_errors);
1578 nstat->rx_over_errors = hwstat->rx_resource_errors;
1579 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1580 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1581 nstat->rx_fifo_errors = hwstat->rx_overruns;
1582 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1583 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1584 nstat->tx_fifo_errors = hwstat->tx_underrun;
1589 struct net_device_stats *macb_get_stats(struct net_device *dev)
1591 struct macb *bp = netdev_priv(dev);
1592 struct net_device_stats *nstat = &bp->stats;
1593 struct macb_stats *hwstat = &bp->hw_stats.macb;
1595 if (macb_is_gem(bp))
1596 return gem_get_stats(bp);
1598 /* read stats from hardware */
1599 macb_update_stats(bp);
1601 /* Convert HW stats into netdevice stats */
1602 nstat->rx_errors = (hwstat->rx_fcs_errors +
1603 hwstat->rx_align_errors +
1604 hwstat->rx_resource_errors +
1605 hwstat->rx_overruns +
1606 hwstat->rx_oversize_pkts +
1607 hwstat->rx_jabbers +
1608 hwstat->rx_undersize_pkts +
1609 hwstat->sqe_test_errors +
1610 hwstat->rx_length_mismatch);
1611 nstat->tx_errors = (hwstat->tx_late_cols +
1612 hwstat->tx_excessive_cols +
1613 hwstat->tx_underruns +
1614 hwstat->tx_carrier_errors);
1615 nstat->collisions = (hwstat->tx_single_cols +
1616 hwstat->tx_multiple_cols +
1617 hwstat->tx_excessive_cols);
1618 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1619 hwstat->rx_jabbers +
1620 hwstat->rx_undersize_pkts +
1621 hwstat->rx_length_mismatch);
1622 nstat->rx_over_errors = hwstat->rx_resource_errors +
1623 hwstat->rx_overruns;
1624 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1625 nstat->rx_frame_errors = hwstat->rx_align_errors;
1626 nstat->rx_fifo_errors = hwstat->rx_overruns;
1627 /* XXX: What does "missed" mean? */
1628 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1629 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1630 nstat->tx_fifo_errors = hwstat->tx_underruns;
1631 /* Don't know about heartbeat or window errors... */
1635 EXPORT_SYMBOL_GPL(macb_get_stats);
1637 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1639 struct macb *bp = netdev_priv(dev);
1640 struct phy_device *phydev = bp->phy_dev;
1645 return phy_ethtool_gset(phydev, cmd);
1648 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1650 struct macb *bp = netdev_priv(dev);
1651 struct phy_device *phydev = bp->phy_dev;
1656 return phy_ethtool_sset(phydev, cmd);
1659 static int macb_get_regs_len(struct net_device *netdev)
1661 return MACB_GREGS_NBR * sizeof(u32);
1664 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1667 struct macb *bp = netdev_priv(dev);
1668 unsigned int tail, head;
1671 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1672 | MACB_GREGS_VERSION;
1674 tail = macb_tx_ring_wrap(bp->tx_tail);
1675 head = macb_tx_ring_wrap(bp->tx_head);
1677 regs_buff[0] = macb_readl(bp, NCR);
1678 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1679 regs_buff[2] = macb_readl(bp, NSR);
1680 regs_buff[3] = macb_readl(bp, TSR);
1681 regs_buff[4] = macb_readl(bp, RBQP);
1682 regs_buff[5] = macb_readl(bp, TBQP);
1683 regs_buff[6] = macb_readl(bp, RSR);
1684 regs_buff[7] = macb_readl(bp, IMR);
1686 regs_buff[8] = tail;
1687 regs_buff[9] = head;
1688 regs_buff[10] = macb_tx_dma(bp, tail);
1689 regs_buff[11] = macb_tx_dma(bp, head);
1691 if (macb_is_gem(bp)) {
1692 regs_buff[12] = gem_readl(bp, USRIO);
1693 regs_buff[13] = gem_readl(bp, DMACFG);
1697 const struct ethtool_ops macb_ethtool_ops = {
1698 .get_settings = macb_get_settings,
1699 .set_settings = macb_set_settings,
1700 .get_regs_len = macb_get_regs_len,
1701 .get_regs = macb_get_regs,
1702 .get_link = ethtool_op_get_link,
1703 .get_ts_info = ethtool_op_get_ts_info,
1705 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1707 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1709 struct macb *bp = netdev_priv(dev);
1710 struct phy_device *phydev = bp->phy_dev;
1712 if (!netif_running(dev))
1718 return phy_mii_ioctl(phydev, rq, cmd);
1720 EXPORT_SYMBOL_GPL(macb_ioctl);
1722 static const struct net_device_ops macb_netdev_ops = {
1723 .ndo_open = macb_open,
1724 .ndo_stop = macb_close,
1725 .ndo_start_xmit = macb_start_xmit,
1726 .ndo_set_rx_mode = macb_set_rx_mode,
1727 .ndo_get_stats = macb_get_stats,
1728 .ndo_do_ioctl = macb_ioctl,
1729 .ndo_validate_addr = eth_validate_addr,
1730 .ndo_change_mtu = eth_change_mtu,
1731 .ndo_set_mac_address = eth_mac_addr,
1732 #ifdef CONFIG_NET_POLL_CONTROLLER
1733 .ndo_poll_controller = macb_poll_controller,
1737 #if defined(CONFIG_OF)
1738 static const struct of_device_id macb_dt_ids[] = {
1739 { .compatible = "cdns,at32ap7000-macb" },
1740 { .compatible = "cdns,at91sam9260-macb" },
1741 { .compatible = "cdns,macb" },
1742 { .compatible = "cdns,pc302-gem" },
1743 { .compatible = "cdns,gem" },
1746 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1749 static int __init macb_probe(struct platform_device *pdev)
1751 struct macb_platform_data *pdata;
1752 struct resource *regs;
1753 struct net_device *dev;
1755 struct phy_device *phydev;
1758 struct pinctrl *pinctrl;
1761 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1763 dev_err(&pdev->dev, "no mmio resource defined\n");
1767 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1768 if (IS_ERR(pinctrl)) {
1769 err = PTR_ERR(pinctrl);
1770 if (err == -EPROBE_DEFER)
1773 dev_warn(&pdev->dev, "No pinctrl provided\n");
1777 dev = alloc_etherdev(sizeof(*bp));
1781 SET_NETDEV_DEV(dev, &pdev->dev);
1783 /* TODO: Actually, we have some interesting features... */
1786 bp = netdev_priv(dev);
1790 spin_lock_init(&bp->lock);
1791 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1793 bp->pclk = clk_get(&pdev->dev, "pclk");
1794 if (IS_ERR(bp->pclk)) {
1795 dev_err(&pdev->dev, "failed to get macb_clk\n");
1796 goto err_out_free_dev;
1798 clk_prepare_enable(bp->pclk);
1800 bp->hclk = clk_get(&pdev->dev, "hclk");
1801 if (IS_ERR(bp->hclk)) {
1802 dev_err(&pdev->dev, "failed to get hclk\n");
1803 goto err_out_put_pclk;
1805 clk_prepare_enable(bp->hclk);
1807 bp->regs = ioremap(regs->start, resource_size(regs));
1809 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1811 goto err_out_disable_clocks;
1814 dev->irq = platform_get_irq(pdev, 0);
1815 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1817 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1819 goto err_out_iounmap;
1822 dev->netdev_ops = &macb_netdev_ops;
1823 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1824 dev->ethtool_ops = &macb_ethtool_ops;
1826 dev->base_addr = regs->start;
1828 /* setup appropriated routines according to adapter type */
1829 if (macb_is_gem(bp)) {
1830 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1831 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1832 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1833 bp->macbgem_ops.mog_rx = gem_rx;
1835 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1836 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1837 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1838 bp->macbgem_ops.mog_rx = macb_rx;
1841 /* Set MII management clock divider */
1842 config = macb_mdc_clk_div(bp);
1843 config |= macb_dbw(bp);
1844 macb_writel(bp, NCFGR, config);
1846 mac = of_get_mac_address(pdev->dev.of_node);
1848 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1850 macb_get_hwaddr(bp);
1852 err = of_get_phy_mode(pdev->dev.of_node);
1854 pdata = dev_get_platdata(&pdev->dev);
1855 if (pdata && pdata->is_rmii)
1856 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1858 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1860 bp->phy_interface = err;
1863 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1864 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1865 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1866 #if defined(CONFIG_ARCH_AT91)
1867 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1870 macb_or_gem_writel(bp, USRIO, 0);
1873 #if defined(CONFIG_ARCH_AT91)
1874 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1876 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1879 err = register_netdev(dev);
1881 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1882 goto err_out_free_irq;
1885 err = macb_mii_init(bp);
1887 goto err_out_unregister_netdev;
1889 platform_set_drvdata(pdev, dev);
1891 netif_carrier_off(dev);
1893 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1894 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1895 dev->irq, dev->dev_addr);
1897 phydev = bp->phy_dev;
1898 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1899 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1903 err_out_unregister_netdev:
1904 unregister_netdev(dev);
1906 free_irq(dev->irq, dev);
1909 err_out_disable_clocks:
1910 clk_disable_unprepare(bp->hclk);
1912 clk_disable_unprepare(bp->pclk);
1921 static int __exit macb_remove(struct platform_device *pdev)
1923 struct net_device *dev;
1926 dev = platform_get_drvdata(pdev);
1929 bp = netdev_priv(dev);
1931 phy_disconnect(bp->phy_dev);
1932 mdiobus_unregister(bp->mii_bus);
1933 kfree(bp->mii_bus->irq);
1934 mdiobus_free(bp->mii_bus);
1935 unregister_netdev(dev);
1936 free_irq(dev->irq, dev);
1938 clk_disable_unprepare(bp->hclk);
1940 clk_disable_unprepare(bp->pclk);
1949 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1951 struct net_device *netdev = platform_get_drvdata(pdev);
1952 struct macb *bp = netdev_priv(netdev);
1954 netif_carrier_off(netdev);
1955 netif_device_detach(netdev);
1957 clk_disable_unprepare(bp->hclk);
1958 clk_disable_unprepare(bp->pclk);
1963 static int macb_resume(struct platform_device *pdev)
1965 struct net_device *netdev = platform_get_drvdata(pdev);
1966 struct macb *bp = netdev_priv(netdev);
1968 clk_prepare_enable(bp->pclk);
1969 clk_prepare_enable(bp->hclk);
1971 netif_device_attach(netdev);
1976 #define macb_suspend NULL
1977 #define macb_resume NULL
1980 static struct platform_driver macb_driver = {
1981 .remove = __exit_p(macb_remove),
1982 .suspend = macb_suspend,
1983 .resume = macb_resume,
1986 .owner = THIS_MODULE,
1987 .of_match_table = of_match_ptr(macb_dt_ids),
1991 module_platform_driver_probe(macb_driver, macb_probe);
1993 MODULE_LICENSE("GPL");
1994 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1995 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1996 MODULE_ALIAS("platform:macb");