2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_data/macb.h>
25 #include <linux/platform_device.h>
26 #include <linux/phy.h>
28 #include <linux/of_device.h>
29 #include <linux/of_net.h>
30 #include <linux/pinctrl/consumer.h>
34 #define RX_BUFFER_SIZE 128
35 #define RX_RING_SIZE 512 /* must be power of 2 */
36 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
38 #define TX_RING_SIZE 128 /* must be power of 2 */
39 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
41 /* minimum number of free TX descriptors before waking up TX process */
42 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
44 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
46 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
49 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
52 * Graceful stop timeouts in us. We should allow up to
53 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
55 #define MACB_HALT_TIMEOUT 1230
57 /* Ring buffer accessors */
58 static unsigned int macb_tx_ring_wrap(unsigned int index)
60 return index & (TX_RING_SIZE - 1);
63 static unsigned int macb_tx_ring_avail(struct macb *bp)
65 return (bp->tx_tail - bp->tx_head) & (TX_RING_SIZE - 1);
68 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
70 return &bp->tx_ring[macb_tx_ring_wrap(index)];
73 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
75 return &bp->tx_skb[macb_tx_ring_wrap(index)];
78 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
82 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
84 return bp->tx_ring_dma + offset;
87 static unsigned int macb_rx_ring_wrap(unsigned int index)
89 return index & (RX_RING_SIZE - 1);
92 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
94 return &bp->rx_ring[macb_rx_ring_wrap(index)];
97 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
99 return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index);
102 void macb_set_hwaddr(struct macb *bp)
107 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
108 macb_or_gem_writel(bp, SA1B, bottom);
109 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
110 macb_or_gem_writel(bp, SA1T, top);
112 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
114 void macb_get_hwaddr(struct macb *bp)
116 struct macb_platform_data *pdata;
122 pdata = bp->pdev->dev.platform_data;
124 /* Check all 4 address register for vaild address */
125 for (i = 0; i < 4; i++) {
126 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
127 top = macb_or_gem_readl(bp, SA1T + i * 8);
129 if (pdata && pdata->rev_eth_addr) {
130 addr[5] = bottom & 0xff;
131 addr[4] = (bottom >> 8) & 0xff;
132 addr[3] = (bottom >> 16) & 0xff;
133 addr[2] = (bottom >> 24) & 0xff;
134 addr[1] = top & 0xff;
135 addr[0] = (top & 0xff00) >> 8;
137 addr[0] = bottom & 0xff;
138 addr[1] = (bottom >> 8) & 0xff;
139 addr[2] = (bottom >> 16) & 0xff;
140 addr[3] = (bottom >> 24) & 0xff;
141 addr[4] = top & 0xff;
142 addr[5] = (top >> 8) & 0xff;
145 if (is_valid_ether_addr(addr)) {
146 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
151 netdev_info(bp->dev, "invalid hw address, using random\n");
152 eth_hw_addr_random(bp->dev);
154 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
156 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
158 struct macb *bp = bus->priv;
161 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
162 | MACB_BF(RW, MACB_MAN_READ)
163 | MACB_BF(PHYA, mii_id)
164 | MACB_BF(REGA, regnum)
165 | MACB_BF(CODE, MACB_MAN_CODE)));
167 /* wait for end of transfer */
168 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
171 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
176 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
179 struct macb *bp = bus->priv;
181 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
182 | MACB_BF(RW, MACB_MAN_WRITE)
183 | MACB_BF(PHYA, mii_id)
184 | MACB_BF(REGA, regnum)
185 | MACB_BF(CODE, MACB_MAN_CODE)
186 | MACB_BF(DATA, value)));
188 /* wait for end of transfer */
189 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
195 static int macb_mdio_reset(struct mii_bus *bus)
200 static void macb_handle_link_change(struct net_device *dev)
202 struct macb *bp = netdev_priv(dev);
203 struct phy_device *phydev = bp->phy_dev;
206 int status_change = 0;
208 spin_lock_irqsave(&bp->lock, flags);
211 if ((bp->speed != phydev->speed) ||
212 (bp->duplex != phydev->duplex)) {
215 reg = macb_readl(bp, NCFGR);
216 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
218 reg &= ~GEM_BIT(GBE);
222 if (phydev->speed == SPEED_100)
223 reg |= MACB_BIT(SPD);
224 if (phydev->speed == SPEED_1000)
227 macb_or_gem_writel(bp, NCFGR, reg);
229 bp->speed = phydev->speed;
230 bp->duplex = phydev->duplex;
235 if (phydev->link != bp->link) {
240 bp->link = phydev->link;
245 spin_unlock_irqrestore(&bp->lock, flags);
249 netif_carrier_on(dev);
250 netdev_info(dev, "link up (%d/%s)\n",
252 phydev->duplex == DUPLEX_FULL ?
255 netif_carrier_off(dev);
256 netdev_info(dev, "link down\n");
261 /* based on au1000_eth. c*/
262 static int macb_mii_probe(struct net_device *dev)
264 struct macb *bp = netdev_priv(dev);
265 struct macb_platform_data *pdata;
266 struct phy_device *phydev;
270 phydev = phy_find_first(bp->mii_bus);
272 netdev_err(dev, "no PHY found\n");
276 pdata = dev_get_platdata(&bp->pdev->dev);
277 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
278 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
280 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
281 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
285 /* attach the mac to the phy */
286 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
289 netdev_err(dev, "Could not attach to PHY\n");
293 /* mask with MAC supported features */
295 phydev->supported &= PHY_GBIT_FEATURES;
297 phydev->supported &= PHY_BASIC_FEATURES;
299 phydev->advertising = phydev->supported;
304 bp->phy_dev = phydev;
309 int macb_mii_init(struct macb *bp)
311 struct macb_platform_data *pdata;
314 /* Enable management port */
315 macb_writel(bp, NCR, MACB_BIT(MPE));
317 bp->mii_bus = mdiobus_alloc();
318 if (bp->mii_bus == NULL) {
323 bp->mii_bus->name = "MACB_mii_bus";
324 bp->mii_bus->read = &macb_mdio_read;
325 bp->mii_bus->write = &macb_mdio_write;
326 bp->mii_bus->reset = &macb_mdio_reset;
327 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
328 bp->pdev->name, bp->pdev->id);
329 bp->mii_bus->priv = bp;
330 bp->mii_bus->parent = &bp->dev->dev;
331 pdata = bp->pdev->dev.platform_data;
334 bp->mii_bus->phy_mask = pdata->phy_mask;
336 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
337 if (!bp->mii_bus->irq) {
339 goto err_out_free_mdiobus;
342 for (i = 0; i < PHY_MAX_ADDR; i++)
343 bp->mii_bus->irq[i] = PHY_POLL;
345 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
347 if (mdiobus_register(bp->mii_bus))
348 goto err_out_free_mdio_irq;
350 if (macb_mii_probe(bp->dev) != 0) {
351 goto err_out_unregister_bus;
356 err_out_unregister_bus:
357 mdiobus_unregister(bp->mii_bus);
358 err_out_free_mdio_irq:
359 kfree(bp->mii_bus->irq);
360 err_out_free_mdiobus:
361 mdiobus_free(bp->mii_bus);
365 EXPORT_SYMBOL_GPL(macb_mii_init);
367 static void macb_update_stats(struct macb *bp)
369 u32 __iomem *reg = bp->regs + MACB_PFR;
370 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
371 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
373 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
375 for(; p < end; p++, reg++)
376 *p += __raw_readl(reg);
379 static int macb_halt_tx(struct macb *bp)
381 unsigned long halt_time, timeout;
384 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
386 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
389 status = macb_readl(bp, TSR);
390 if (!(status & MACB_BIT(TGO)))
393 usleep_range(10, 250);
394 } while (time_before(halt_time, timeout));
399 static void macb_tx_error_task(struct work_struct *work)
401 struct macb *bp = container_of(work, struct macb, tx_error_task);
402 struct macb_tx_skb *tx_skb;
406 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
407 bp->tx_tail, bp->tx_head);
409 /* Make sure nobody is trying to queue up new packets */
410 netif_stop_queue(bp->dev);
413 * Stop transmission now
414 * (in case we have just queued new packets)
416 if (macb_halt_tx(bp))
417 /* Just complain for now, reinitializing TX path can be good */
418 netdev_err(bp->dev, "BUG: halt tx timed out\n");
420 /* No need for the lock here as nobody will interrupt us anymore */
423 * Treat frames in TX queue including the ones that caused the error.
424 * Free transmit buffers in upper layer.
426 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
427 struct macb_dma_desc *desc;
430 desc = macb_tx_desc(bp, tail);
432 tx_skb = macb_tx_skb(bp, tail);
435 if (ctrl & MACB_BIT(TX_USED)) {
436 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
437 macb_tx_ring_wrap(tail), skb->data);
438 bp->stats.tx_packets++;
439 bp->stats.tx_bytes += skb->len;
442 * "Buffers exhausted mid-frame" errors may only happen
443 * if the driver is buggy, so complain loudly about those.
444 * Statistics are updated by hardware.
446 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
448 "BUG: TX buffers exhausted mid-frame\n");
450 desc->ctrl = ctrl | MACB_BIT(TX_USED);
453 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
459 /* Make descriptor updates visible to hardware */
462 /* Reinitialize the TX desc queue */
463 macb_writel(bp, TBQP, bp->tx_ring_dma);
464 /* Make TX ring reflect state of hardware */
465 bp->tx_head = bp->tx_tail = 0;
467 /* Now we are ready to start transmission again */
468 netif_wake_queue(bp->dev);
470 /* Housework before enabling TX IRQ */
471 macb_writel(bp, TSR, macb_readl(bp, TSR));
472 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
475 static void macb_tx_interrupt(struct macb *bp)
481 status = macb_readl(bp, TSR);
482 macb_writel(bp, TSR, status);
484 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
485 (unsigned long)status);
488 for (tail = bp->tx_tail; tail != head; tail++) {
489 struct macb_tx_skb *tx_skb;
491 struct macb_dma_desc *desc;
494 desc = macb_tx_desc(bp, tail);
496 /* Make hw descriptor updates visible to CPU */
501 if (!(ctrl & MACB_BIT(TX_USED)))
504 tx_skb = macb_tx_skb(bp, tail);
507 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
508 macb_tx_ring_wrap(tail), skb->data);
509 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
511 bp->stats.tx_packets++;
512 bp->stats.tx_bytes += skb->len;
514 dev_kfree_skb_irq(skb);
518 if (netif_queue_stopped(bp->dev)
519 && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH)
520 netif_wake_queue(bp->dev);
523 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
524 unsigned int last_frag)
530 struct macb_dma_desc *desc;
532 desc = macb_rx_desc(bp, last_frag);
533 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
535 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
536 macb_rx_ring_wrap(first_frag),
537 macb_rx_ring_wrap(last_frag), len);
540 * The ethernet header starts NET_IP_ALIGN bytes into the
541 * first buffer. Since the header is 14 bytes, this makes the
542 * payload word-aligned.
544 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
545 * the two padding bytes into the skb so that we avoid hitting
546 * the slowpath in memcpy(), and pull them off afterwards.
548 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
550 bp->stats.rx_dropped++;
551 for (frag = first_frag; ; frag++) {
552 desc = macb_rx_desc(bp, frag);
553 desc->addr &= ~MACB_BIT(RX_USED);
554 if (frag == last_frag)
558 /* Make descriptor updates visible to hardware */
566 skb_checksum_none_assert(skb);
569 for (frag = first_frag; ; frag++) {
570 unsigned int frag_len = RX_BUFFER_SIZE;
572 if (offset + frag_len > len) {
573 BUG_ON(frag != last_frag);
574 frag_len = len - offset;
576 skb_copy_to_linear_data_offset(skb, offset,
577 macb_rx_buffer(bp, frag), frag_len);
578 offset += RX_BUFFER_SIZE;
579 desc = macb_rx_desc(bp, frag);
580 desc->addr &= ~MACB_BIT(RX_USED);
582 if (frag == last_frag)
586 /* Make descriptor updates visible to hardware */
589 __skb_pull(skb, NET_IP_ALIGN);
590 skb->protocol = eth_type_trans(skb, bp->dev);
592 bp->stats.rx_packets++;
593 bp->stats.rx_bytes += skb->len;
594 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
595 skb->len, skb->csum);
596 netif_receive_skb(skb);
601 /* Mark DMA descriptors from begin up to and not including end as unused */
602 static void discard_partial_frame(struct macb *bp, unsigned int begin,
607 for (frag = begin; frag != end; frag++) {
608 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
609 desc->addr &= ~MACB_BIT(RX_USED);
612 /* Make descriptor updates visible to hardware */
616 * When this happens, the hardware stats registers for
617 * whatever caused this is updated, so we don't have to record
622 static int macb_rx(struct macb *bp, int budget)
628 for (tail = bp->rx_tail; budget > 0; tail++) {
629 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
632 /* Make hw descriptor updates visible to CPU */
638 if (!(addr & MACB_BIT(RX_USED)))
641 if (ctrl & MACB_BIT(RX_SOF)) {
642 if (first_frag != -1)
643 discard_partial_frame(bp, first_frag, tail);
647 if (ctrl & MACB_BIT(RX_EOF)) {
649 BUG_ON(first_frag == -1);
651 dropped = macb_rx_frame(bp, first_frag, tail);
660 if (first_frag != -1)
661 bp->rx_tail = first_frag;
668 static int macb_poll(struct napi_struct *napi, int budget)
670 struct macb *bp = container_of(napi, struct macb, napi);
674 status = macb_readl(bp, RSR);
675 macb_writel(bp, RSR, status);
679 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
680 (unsigned long)status, budget);
682 work_done = macb_rx(bp, budget);
683 if (work_done < budget) {
687 * We've done what we can to clean the buffers. Make sure we
688 * get notified when new packets arrive.
690 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
693 /* TODO: Handle errors */
698 static irqreturn_t macb_interrupt(int irq, void *dev_id)
700 struct net_device *dev = dev_id;
701 struct macb *bp = netdev_priv(dev);
704 status = macb_readl(bp, ISR);
706 if (unlikely(!status))
709 spin_lock(&bp->lock);
712 /* close possible race with dev_close */
713 if (unlikely(!netif_running(dev))) {
714 macb_writel(bp, IDR, -1);
718 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
720 if (status & MACB_RX_INT_FLAGS) {
722 * There's no point taking any more interrupts
723 * until we have processed the buffers. The
724 * scheduling call may fail if the poll routine
725 * is already scheduled, so disable interrupts
728 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
730 if (napi_schedule_prep(&bp->napi)) {
731 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
732 __napi_schedule(&bp->napi);
736 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
737 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
738 schedule_work(&bp->tx_error_task);
742 if (status & MACB_BIT(TCOMP))
743 macb_tx_interrupt(bp);
746 * Link change detection isn't possible with RMII, so we'll
747 * add that if/when we get our hands on a full-blown MII PHY.
750 if (status & MACB_BIT(ISR_ROVR)) {
751 /* We missed at least one packet */
753 bp->hw_stats.gem.rx_overruns++;
755 bp->hw_stats.macb.rx_overruns++;
758 if (status & MACB_BIT(HRESP)) {
760 * TODO: Reset the hardware, and maybe move the
761 * netdev_err to a lower-priority context as well
764 netdev_err(dev, "DMA bus error: HRESP not OK\n");
767 status = macb_readl(bp, ISR);
770 spin_unlock(&bp->lock);
775 #ifdef CONFIG_NET_POLL_CONTROLLER
777 * Polling receive - used by netconsole and other diagnostic tools
778 * to allow network i/o with interrupts disabled.
780 static void macb_poll_controller(struct net_device *dev)
784 local_irq_save(flags);
785 macb_interrupt(dev->irq, dev);
786 local_irq_restore(flags);
790 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
792 struct macb *bp = netdev_priv(dev);
794 unsigned int len, entry;
795 struct macb_dma_desc *desc;
796 struct macb_tx_skb *tx_skb;
800 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
802 "start_xmit: len %u head %p data %p tail %p end %p\n",
803 skb->len, skb->head, skb->data,
804 skb_tail_pointer(skb), skb_end_pointer(skb));
805 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
806 skb->data, 16, true);
810 spin_lock_irqsave(&bp->lock, flags);
812 /* This is a hard error, log it. */
813 if (macb_tx_ring_avail(bp) < 1) {
814 netif_stop_queue(dev);
815 spin_unlock_irqrestore(&bp->lock, flags);
816 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
817 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
818 bp->tx_head, bp->tx_tail);
819 return NETDEV_TX_BUSY;
822 entry = macb_tx_ring_wrap(bp->tx_head);
824 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
825 mapping = dma_map_single(&bp->pdev->dev, skb->data,
828 tx_skb = &bp->tx_skb[entry];
830 tx_skb->mapping = mapping;
831 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
832 skb->data, (unsigned long)mapping);
834 ctrl = MACB_BF(TX_FRMLEN, len);
835 ctrl |= MACB_BIT(TX_LAST);
836 if (entry == (TX_RING_SIZE - 1))
837 ctrl |= MACB_BIT(TX_WRAP);
839 desc = &bp->tx_ring[entry];
840 desc->addr = mapping;
843 /* Make newly initialized descriptor visible to hardware */
846 skb_tx_timestamp(skb);
848 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
850 if (macb_tx_ring_avail(bp) < 1)
851 netif_stop_queue(dev);
853 spin_unlock_irqrestore(&bp->lock, flags);
858 static void macb_free_consistent(struct macb *bp)
865 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
866 bp->rx_ring, bp->rx_ring_dma);
870 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
871 bp->tx_ring, bp->tx_ring_dma);
874 if (bp->rx_buffers) {
875 dma_free_coherent(&bp->pdev->dev,
876 RX_RING_SIZE * RX_BUFFER_SIZE,
877 bp->rx_buffers, bp->rx_buffers_dma);
878 bp->rx_buffers = NULL;
882 static int macb_alloc_consistent(struct macb *bp)
886 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
887 bp->tx_skb = kmalloc(size, GFP_KERNEL);
891 size = RX_RING_BYTES;
892 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
893 &bp->rx_ring_dma, GFP_KERNEL);
897 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
898 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
900 size = TX_RING_BYTES;
901 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
902 &bp->tx_ring_dma, GFP_KERNEL);
906 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
907 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
909 size = RX_RING_SIZE * RX_BUFFER_SIZE;
910 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
911 &bp->rx_buffers_dma, GFP_KERNEL);
915 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
916 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
921 macb_free_consistent(bp);
925 static void macb_init_rings(struct macb *bp)
930 addr = bp->rx_buffers_dma;
931 for (i = 0; i < RX_RING_SIZE; i++) {
932 bp->rx_ring[i].addr = addr;
933 bp->rx_ring[i].ctrl = 0;
934 addr += RX_BUFFER_SIZE;
936 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
938 for (i = 0; i < TX_RING_SIZE; i++) {
939 bp->tx_ring[i].addr = 0;
940 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
942 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
944 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
947 static void macb_reset_hw(struct macb *bp)
950 * Disable RX and TX (XXX: Should we halt the transmission
953 macb_writel(bp, NCR, 0);
955 /* Clear the stats registers (XXX: Update stats first?) */
956 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
958 /* Clear all status flags */
959 macb_writel(bp, TSR, -1);
960 macb_writel(bp, RSR, -1);
962 /* Disable all interrupts */
963 macb_writel(bp, IDR, -1);
967 static u32 gem_mdc_clk_div(struct macb *bp)
970 unsigned long pclk_hz = clk_get_rate(bp->pclk);
972 if (pclk_hz <= 20000000)
973 config = GEM_BF(CLK, GEM_CLK_DIV8);
974 else if (pclk_hz <= 40000000)
975 config = GEM_BF(CLK, GEM_CLK_DIV16);
976 else if (pclk_hz <= 80000000)
977 config = GEM_BF(CLK, GEM_CLK_DIV32);
978 else if (pclk_hz <= 120000000)
979 config = GEM_BF(CLK, GEM_CLK_DIV48);
980 else if (pclk_hz <= 160000000)
981 config = GEM_BF(CLK, GEM_CLK_DIV64);
983 config = GEM_BF(CLK, GEM_CLK_DIV96);
988 static u32 macb_mdc_clk_div(struct macb *bp)
991 unsigned long pclk_hz;
994 return gem_mdc_clk_div(bp);
996 pclk_hz = clk_get_rate(bp->pclk);
997 if (pclk_hz <= 20000000)
998 config = MACB_BF(CLK, MACB_CLK_DIV8);
999 else if (pclk_hz <= 40000000)
1000 config = MACB_BF(CLK, MACB_CLK_DIV16);
1001 else if (pclk_hz <= 80000000)
1002 config = MACB_BF(CLK, MACB_CLK_DIV32);
1004 config = MACB_BF(CLK, MACB_CLK_DIV64);
1010 * Get the DMA bus width field of the network configuration register that we
1011 * should program. We find the width from decoding the design configuration
1012 * register to find the maximum supported data bus width.
1014 static u32 macb_dbw(struct macb *bp)
1016 if (!macb_is_gem(bp))
1019 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1021 return GEM_BF(DBW, GEM_DBW128);
1023 return GEM_BF(DBW, GEM_DBW64);
1026 return GEM_BF(DBW, GEM_DBW32);
1031 * Configure the receive DMA engine to use the correct receive buffer size.
1032 * This is a configurable parameter for GEM.
1034 static void macb_configure_dma(struct macb *bp)
1038 if (macb_is_gem(bp)) {
1039 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1040 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
1041 gem_writel(bp, DMACFG, dmacfg);
1045 static void macb_init_hw(struct macb *bp)
1050 macb_set_hwaddr(bp);
1052 config = macb_mdc_clk_div(bp);
1053 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1054 config |= MACB_BIT(PAE); /* PAuse Enable */
1055 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1056 config |= MACB_BIT(BIG); /* Receive oversized frames */
1057 if (bp->dev->flags & IFF_PROMISC)
1058 config |= MACB_BIT(CAF); /* Copy All Frames */
1059 if (!(bp->dev->flags & IFF_BROADCAST))
1060 config |= MACB_BIT(NBC); /* No BroadCast */
1061 config |= macb_dbw(bp);
1062 macb_writel(bp, NCFGR, config);
1063 bp->speed = SPEED_10;
1064 bp->duplex = DUPLEX_HALF;
1066 macb_configure_dma(bp);
1068 /* Initialize TX and RX buffers */
1069 macb_writel(bp, RBQP, bp->rx_ring_dma);
1070 macb_writel(bp, TBQP, bp->tx_ring_dma);
1072 /* Enable TX and RX */
1073 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1075 /* Enable interrupts */
1076 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1078 | MACB_BIT(HRESP)));
1083 * The hash address register is 64 bits long and takes up two
1084 * locations in the memory map. The least significant bits are stored
1085 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1087 * The unicast hash enable and the multicast hash enable bits in the
1088 * network configuration register enable the reception of hash matched
1089 * frames. The destination address is reduced to a 6 bit index into
1090 * the 64 bit hash register using the following hash function. The
1091 * hash function is an exclusive or of every sixth bit of the
1092 * destination address.
1094 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1095 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1096 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1097 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1098 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1099 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1101 * da[0] represents the least significant bit of the first byte
1102 * received, that is, the multicast/unicast indicator, and da[47]
1103 * represents the most significant bit of the last byte received. If
1104 * the hash index, hi[n], points to a bit that is set in the hash
1105 * register then the frame will be matched according to whether the
1106 * frame is multicast or unicast. A multicast match will be signalled
1107 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1108 * index points to a bit set in the hash register. A unicast match
1109 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1110 * and the hash index points to a bit set in the hash register. To
1111 * receive all multicast frames, the hash register should be set with
1112 * all ones and the multicast hash enable bit should be set in the
1113 * network configuration register.
1116 static inline int hash_bit_value(int bitnr, __u8 *addr)
1118 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1124 * Return the hash index value for the specified address.
1126 static int hash_get_index(__u8 *addr)
1131 for (j = 0; j < 6; j++) {
1132 for (i = 0, bitval = 0; i < 8; i++)
1133 bitval ^= hash_bit_value(i*6 + j, addr);
1135 hash_index |= (bitval << j);
1142 * Add multicast addresses to the internal multicast-hash table.
1144 static void macb_sethashtable(struct net_device *dev)
1146 struct netdev_hw_addr *ha;
1147 unsigned long mc_filter[2];
1149 struct macb *bp = netdev_priv(dev);
1151 mc_filter[0] = mc_filter[1] = 0;
1153 netdev_for_each_mc_addr(ha, dev) {
1154 bitnr = hash_get_index(ha->addr);
1155 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1158 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1159 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1163 * Enable/Disable promiscuous and multicast modes.
1165 void macb_set_rx_mode(struct net_device *dev)
1168 struct macb *bp = netdev_priv(dev);
1170 cfg = macb_readl(bp, NCFGR);
1172 if (dev->flags & IFF_PROMISC)
1173 /* Enable promiscuous mode */
1174 cfg |= MACB_BIT(CAF);
1175 else if (dev->flags & (~IFF_PROMISC))
1176 /* Disable promiscuous mode */
1177 cfg &= ~MACB_BIT(CAF);
1179 if (dev->flags & IFF_ALLMULTI) {
1180 /* Enable all multicast mode */
1181 macb_or_gem_writel(bp, HRB, -1);
1182 macb_or_gem_writel(bp, HRT, -1);
1183 cfg |= MACB_BIT(NCFGR_MTI);
1184 } else if (!netdev_mc_empty(dev)) {
1185 /* Enable specific multicasts */
1186 macb_sethashtable(dev);
1187 cfg |= MACB_BIT(NCFGR_MTI);
1188 } else if (dev->flags & (~IFF_ALLMULTI)) {
1189 /* Disable all multicast mode */
1190 macb_or_gem_writel(bp, HRB, 0);
1191 macb_or_gem_writel(bp, HRT, 0);
1192 cfg &= ~MACB_BIT(NCFGR_MTI);
1195 macb_writel(bp, NCFGR, cfg);
1197 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1199 static int macb_open(struct net_device *dev)
1201 struct macb *bp = netdev_priv(dev);
1204 netdev_dbg(bp->dev, "open\n");
1206 /* carrier starts down */
1207 netif_carrier_off(dev);
1209 /* if the phy is not yet register, retry later*/
1213 if (!is_valid_ether_addr(dev->dev_addr))
1214 return -EADDRNOTAVAIL;
1216 err = macb_alloc_consistent(bp);
1218 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1223 napi_enable(&bp->napi);
1225 macb_init_rings(bp);
1228 /* schedule a link state check */
1229 phy_start(bp->phy_dev);
1231 netif_start_queue(dev);
1236 static int macb_close(struct net_device *dev)
1238 struct macb *bp = netdev_priv(dev);
1239 unsigned long flags;
1241 netif_stop_queue(dev);
1242 napi_disable(&bp->napi);
1245 phy_stop(bp->phy_dev);
1247 spin_lock_irqsave(&bp->lock, flags);
1249 netif_carrier_off(dev);
1250 spin_unlock_irqrestore(&bp->lock, flags);
1252 macb_free_consistent(bp);
1257 static void gem_update_stats(struct macb *bp)
1259 u32 __iomem *reg = bp->regs + GEM_OTX;
1260 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1261 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1263 for (; p < end; p++, reg++)
1264 *p += __raw_readl(reg);
1267 static struct net_device_stats *gem_get_stats(struct macb *bp)
1269 struct gem_stats *hwstat = &bp->hw_stats.gem;
1270 struct net_device_stats *nstat = &bp->stats;
1272 gem_update_stats(bp);
1274 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1275 hwstat->rx_alignment_errors +
1276 hwstat->rx_resource_errors +
1277 hwstat->rx_overruns +
1278 hwstat->rx_oversize_frames +
1279 hwstat->rx_jabbers +
1280 hwstat->rx_undersized_frames +
1281 hwstat->rx_length_field_frame_errors);
1282 nstat->tx_errors = (hwstat->tx_late_collisions +
1283 hwstat->tx_excessive_collisions +
1284 hwstat->tx_underrun +
1285 hwstat->tx_carrier_sense_errors);
1286 nstat->multicast = hwstat->rx_multicast_frames;
1287 nstat->collisions = (hwstat->tx_single_collision_frames +
1288 hwstat->tx_multiple_collision_frames +
1289 hwstat->tx_excessive_collisions);
1290 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1291 hwstat->rx_jabbers +
1292 hwstat->rx_undersized_frames +
1293 hwstat->rx_length_field_frame_errors);
1294 nstat->rx_over_errors = hwstat->rx_resource_errors;
1295 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1296 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1297 nstat->rx_fifo_errors = hwstat->rx_overruns;
1298 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1299 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1300 nstat->tx_fifo_errors = hwstat->tx_underrun;
1305 struct net_device_stats *macb_get_stats(struct net_device *dev)
1307 struct macb *bp = netdev_priv(dev);
1308 struct net_device_stats *nstat = &bp->stats;
1309 struct macb_stats *hwstat = &bp->hw_stats.macb;
1311 if (macb_is_gem(bp))
1312 return gem_get_stats(bp);
1314 /* read stats from hardware */
1315 macb_update_stats(bp);
1317 /* Convert HW stats into netdevice stats */
1318 nstat->rx_errors = (hwstat->rx_fcs_errors +
1319 hwstat->rx_align_errors +
1320 hwstat->rx_resource_errors +
1321 hwstat->rx_overruns +
1322 hwstat->rx_oversize_pkts +
1323 hwstat->rx_jabbers +
1324 hwstat->rx_undersize_pkts +
1325 hwstat->sqe_test_errors +
1326 hwstat->rx_length_mismatch);
1327 nstat->tx_errors = (hwstat->tx_late_cols +
1328 hwstat->tx_excessive_cols +
1329 hwstat->tx_underruns +
1330 hwstat->tx_carrier_errors);
1331 nstat->collisions = (hwstat->tx_single_cols +
1332 hwstat->tx_multiple_cols +
1333 hwstat->tx_excessive_cols);
1334 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1335 hwstat->rx_jabbers +
1336 hwstat->rx_undersize_pkts +
1337 hwstat->rx_length_mismatch);
1338 nstat->rx_over_errors = hwstat->rx_resource_errors +
1339 hwstat->rx_overruns;
1340 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1341 nstat->rx_frame_errors = hwstat->rx_align_errors;
1342 nstat->rx_fifo_errors = hwstat->rx_overruns;
1343 /* XXX: What does "missed" mean? */
1344 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1345 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1346 nstat->tx_fifo_errors = hwstat->tx_underruns;
1347 /* Don't know about heartbeat or window errors... */
1351 EXPORT_SYMBOL_GPL(macb_get_stats);
1353 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1355 struct macb *bp = netdev_priv(dev);
1356 struct phy_device *phydev = bp->phy_dev;
1361 return phy_ethtool_gset(phydev, cmd);
1364 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1366 struct macb *bp = netdev_priv(dev);
1367 struct phy_device *phydev = bp->phy_dev;
1372 return phy_ethtool_sset(phydev, cmd);
1375 static int macb_get_regs_len(struct net_device *netdev)
1377 return MACB_GREGS_NBR * sizeof(u32);
1380 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1383 struct macb *bp = netdev_priv(dev);
1384 unsigned int tail, head;
1387 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1388 | MACB_GREGS_VERSION;
1390 tail = macb_tx_ring_wrap(bp->tx_tail);
1391 head = macb_tx_ring_wrap(bp->tx_head);
1393 regs_buff[0] = macb_readl(bp, NCR);
1394 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1395 regs_buff[2] = macb_readl(bp, NSR);
1396 regs_buff[3] = macb_readl(bp, TSR);
1397 regs_buff[4] = macb_readl(bp, RBQP);
1398 regs_buff[5] = macb_readl(bp, TBQP);
1399 regs_buff[6] = macb_readl(bp, RSR);
1400 regs_buff[7] = macb_readl(bp, IMR);
1402 regs_buff[8] = tail;
1403 regs_buff[9] = head;
1404 regs_buff[10] = macb_tx_dma(bp, tail);
1405 regs_buff[11] = macb_tx_dma(bp, head);
1407 if (macb_is_gem(bp)) {
1408 regs_buff[12] = gem_readl(bp, USRIO);
1409 regs_buff[13] = gem_readl(bp, DMACFG);
1413 const struct ethtool_ops macb_ethtool_ops = {
1414 .get_settings = macb_get_settings,
1415 .set_settings = macb_set_settings,
1416 .get_regs_len = macb_get_regs_len,
1417 .get_regs = macb_get_regs,
1418 .get_link = ethtool_op_get_link,
1419 .get_ts_info = ethtool_op_get_ts_info,
1421 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1423 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1425 struct macb *bp = netdev_priv(dev);
1426 struct phy_device *phydev = bp->phy_dev;
1428 if (!netif_running(dev))
1434 return phy_mii_ioctl(phydev, rq, cmd);
1436 EXPORT_SYMBOL_GPL(macb_ioctl);
1438 static const struct net_device_ops macb_netdev_ops = {
1439 .ndo_open = macb_open,
1440 .ndo_stop = macb_close,
1441 .ndo_start_xmit = macb_start_xmit,
1442 .ndo_set_rx_mode = macb_set_rx_mode,
1443 .ndo_get_stats = macb_get_stats,
1444 .ndo_do_ioctl = macb_ioctl,
1445 .ndo_validate_addr = eth_validate_addr,
1446 .ndo_change_mtu = eth_change_mtu,
1447 .ndo_set_mac_address = eth_mac_addr,
1448 #ifdef CONFIG_NET_POLL_CONTROLLER
1449 .ndo_poll_controller = macb_poll_controller,
1453 #if defined(CONFIG_OF)
1454 static const struct of_device_id macb_dt_ids[] = {
1455 { .compatible = "cdns,at32ap7000-macb" },
1456 { .compatible = "cdns,at91sam9260-macb" },
1457 { .compatible = "cdns,macb" },
1458 { .compatible = "cdns,pc302-gem" },
1459 { .compatible = "cdns,gem" },
1463 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1465 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1467 struct device_node *np = pdev->dev.of_node;
1470 return of_get_phy_mode(np);
1475 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1477 struct device_node *np = bp->pdev->dev.of_node;
1479 const char *mac = of_get_mac_address(np);
1481 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1489 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1493 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1499 static int __init macb_probe(struct platform_device *pdev)
1501 struct macb_platform_data *pdata;
1502 struct resource *regs;
1503 struct net_device *dev;
1505 struct phy_device *phydev;
1508 struct pinctrl *pinctrl;
1510 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1512 dev_err(&pdev->dev, "no mmio resource defined\n");
1516 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1517 if (IS_ERR(pinctrl)) {
1518 err = PTR_ERR(pinctrl);
1519 if (err == -EPROBE_DEFER)
1522 dev_warn(&pdev->dev, "No pinctrl provided\n");
1526 dev = alloc_etherdev(sizeof(*bp));
1530 SET_NETDEV_DEV(dev, &pdev->dev);
1532 /* TODO: Actually, we have some interesting features... */
1535 bp = netdev_priv(dev);
1539 spin_lock_init(&bp->lock);
1540 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1542 bp->pclk = clk_get(&pdev->dev, "pclk");
1543 if (IS_ERR(bp->pclk)) {
1544 dev_err(&pdev->dev, "failed to get macb_clk\n");
1545 goto err_out_free_dev;
1547 clk_enable(bp->pclk);
1549 bp->hclk = clk_get(&pdev->dev, "hclk");
1550 if (IS_ERR(bp->hclk)) {
1551 dev_err(&pdev->dev, "failed to get hclk\n");
1552 goto err_out_put_pclk;
1554 clk_enable(bp->hclk);
1556 bp->regs = ioremap(regs->start, resource_size(regs));
1558 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1560 goto err_out_disable_clocks;
1563 dev->irq = platform_get_irq(pdev, 0);
1564 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1566 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1568 goto err_out_iounmap;
1571 dev->netdev_ops = &macb_netdev_ops;
1572 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1573 dev->ethtool_ops = &macb_ethtool_ops;
1575 dev->base_addr = regs->start;
1577 /* Set MII management clock divider */
1578 config = macb_mdc_clk_div(bp);
1579 config |= macb_dbw(bp);
1580 macb_writel(bp, NCFGR, config);
1582 err = macb_get_hwaddr_dt(bp);
1584 macb_get_hwaddr(bp);
1586 err = macb_get_phy_mode_dt(pdev);
1588 pdata = pdev->dev.platform_data;
1589 if (pdata && pdata->is_rmii)
1590 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1592 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1594 bp->phy_interface = err;
1597 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1598 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1599 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1600 #if defined(CONFIG_ARCH_AT91)
1601 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1604 macb_or_gem_writel(bp, USRIO, 0);
1607 #if defined(CONFIG_ARCH_AT91)
1608 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1610 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1613 err = register_netdev(dev);
1615 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1616 goto err_out_free_irq;
1619 if (macb_mii_init(bp) != 0) {
1620 goto err_out_unregister_netdev;
1623 platform_set_drvdata(pdev, dev);
1625 netif_carrier_off(dev);
1627 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1628 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1629 dev->irq, dev->dev_addr);
1631 phydev = bp->phy_dev;
1632 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1633 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1637 err_out_unregister_netdev:
1638 unregister_netdev(dev);
1640 free_irq(dev->irq, dev);
1643 err_out_disable_clocks:
1644 clk_disable(bp->hclk);
1646 clk_disable(bp->pclk);
1652 platform_set_drvdata(pdev, NULL);
1656 static int __exit macb_remove(struct platform_device *pdev)
1658 struct net_device *dev;
1661 dev = platform_get_drvdata(pdev);
1664 bp = netdev_priv(dev);
1666 phy_disconnect(bp->phy_dev);
1667 mdiobus_unregister(bp->mii_bus);
1668 kfree(bp->mii_bus->irq);
1669 mdiobus_free(bp->mii_bus);
1670 unregister_netdev(dev);
1671 free_irq(dev->irq, dev);
1673 clk_disable(bp->hclk);
1675 clk_disable(bp->pclk);
1678 platform_set_drvdata(pdev, NULL);
1685 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1687 struct net_device *netdev = platform_get_drvdata(pdev);
1688 struct macb *bp = netdev_priv(netdev);
1690 netif_carrier_off(netdev);
1691 netif_device_detach(netdev);
1693 clk_disable(bp->hclk);
1694 clk_disable(bp->pclk);
1699 static int macb_resume(struct platform_device *pdev)
1701 struct net_device *netdev = platform_get_drvdata(pdev);
1702 struct macb *bp = netdev_priv(netdev);
1704 clk_enable(bp->pclk);
1705 clk_enable(bp->hclk);
1707 netif_device_attach(netdev);
1712 #define macb_suspend NULL
1713 #define macb_resume NULL
1716 static struct platform_driver macb_driver = {
1717 .remove = __exit_p(macb_remove),
1718 .suspend = macb_suspend,
1719 .resume = macb_resume,
1722 .owner = THIS_MODULE,
1723 .of_match_table = of_match_ptr(macb_dt_ids),
1727 static int __init macb_init(void)
1729 return platform_driver_probe(&macb_driver, macb_probe);
1732 static void __exit macb_exit(void)
1734 platform_driver_unregister(&macb_driver);
1737 module_init(macb_init);
1738 module_exit(macb_exit);
1740 MODULE_LICENSE("GPL");
1741 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1742 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1743 MODULE_ALIAS("platform:macb");