2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_data/macb.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy.h>
27 #include <linux/of_device.h>
28 #include <linux/of_net.h>
32 #define RX_BUFFER_SIZE 128
33 #define RX_RING_SIZE 512
34 #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
36 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
39 #define TX_RING_SIZE 128
40 #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
41 #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
43 #define TX_RING_GAP(bp) \
44 (TX_RING_SIZE - (bp)->tx_pending)
45 #define TX_BUFFS_AVAIL(bp) \
46 (((bp)->tx_tail <= (bp)->tx_head) ? \
47 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
48 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
49 #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
51 #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
53 /* minimum number of free TX descriptors before waking up TX process */
54 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
56 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
59 static void __macb_set_hwaddr(struct macb *bp)
64 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
65 macb_or_gem_writel(bp, SA1B, bottom);
66 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
67 macb_or_gem_writel(bp, SA1T, top);
70 static void __init macb_get_hwaddr(struct macb *bp)
76 bottom = macb_or_gem_readl(bp, SA1B);
77 top = macb_or_gem_readl(bp, SA1T);
79 addr[0] = bottom & 0xff;
80 addr[1] = (bottom >> 8) & 0xff;
81 addr[2] = (bottom >> 16) & 0xff;
82 addr[3] = (bottom >> 24) & 0xff;
84 addr[5] = (top >> 8) & 0xff;
86 if (is_valid_ether_addr(addr)) {
87 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
89 netdev_info(bp->dev, "invalid hw address, using random\n");
90 random_ether_addr(bp->dev->dev_addr);
94 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
96 struct macb *bp = bus->priv;
99 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
100 | MACB_BF(RW, MACB_MAN_READ)
101 | MACB_BF(PHYA, mii_id)
102 | MACB_BF(REGA, regnum)
103 | MACB_BF(CODE, MACB_MAN_CODE)));
105 /* wait for end of transfer */
106 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
109 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
114 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
117 struct macb *bp = bus->priv;
119 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
120 | MACB_BF(RW, MACB_MAN_WRITE)
121 | MACB_BF(PHYA, mii_id)
122 | MACB_BF(REGA, regnum)
123 | MACB_BF(CODE, MACB_MAN_CODE)
124 | MACB_BF(DATA, value)));
126 /* wait for end of transfer */
127 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
133 static int macb_mdio_reset(struct mii_bus *bus)
138 static void macb_handle_link_change(struct net_device *dev)
140 struct macb *bp = netdev_priv(dev);
141 struct phy_device *phydev = bp->phy_dev;
144 int status_change = 0;
146 spin_lock_irqsave(&bp->lock, flags);
149 if ((bp->speed != phydev->speed) ||
150 (bp->duplex != phydev->duplex)) {
153 reg = macb_readl(bp, NCFGR);
154 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
158 if (phydev->speed == SPEED_100)
159 reg |= MACB_BIT(SPD);
161 macb_writel(bp, NCFGR, reg);
163 bp->speed = phydev->speed;
164 bp->duplex = phydev->duplex;
169 if (phydev->link != bp->link) {
174 bp->link = phydev->link;
179 spin_unlock_irqrestore(&bp->lock, flags);
183 netdev_info(dev, "link up (%d/%s)\n",
185 phydev->duplex == DUPLEX_FULL ?
188 netdev_info(dev, "link down\n");
192 /* based on au1000_eth. c*/
193 static int macb_mii_probe(struct net_device *dev)
195 struct macb *bp = netdev_priv(dev);
196 struct phy_device *phydev;
199 phydev = phy_find_first(bp->mii_bus);
201 netdev_err(dev, "no PHY found\n");
205 /* TODO : add pin_irq */
207 /* attach the mac to the phy */
208 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
211 netdev_err(dev, "Could not attach to PHY\n");
215 /* mask with MAC supported features */
216 phydev->supported &= PHY_BASIC_FEATURES;
218 phydev->advertising = phydev->supported;
223 bp->phy_dev = phydev;
228 static int macb_mii_init(struct macb *bp)
230 struct macb_platform_data *pdata;
233 /* Enable management port */
234 macb_writel(bp, NCR, MACB_BIT(MPE));
236 bp->mii_bus = mdiobus_alloc();
237 if (bp->mii_bus == NULL) {
242 bp->mii_bus->name = "MACB_mii_bus";
243 bp->mii_bus->read = &macb_mdio_read;
244 bp->mii_bus->write = &macb_mdio_write;
245 bp->mii_bus->reset = &macb_mdio_reset;
246 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
247 bp->mii_bus->priv = bp;
248 bp->mii_bus->parent = &bp->dev->dev;
249 pdata = bp->pdev->dev.platform_data;
252 bp->mii_bus->phy_mask = pdata->phy_mask;
254 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
255 if (!bp->mii_bus->irq) {
257 goto err_out_free_mdiobus;
260 for (i = 0; i < PHY_MAX_ADDR; i++)
261 bp->mii_bus->irq[i] = PHY_POLL;
263 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
265 if (mdiobus_register(bp->mii_bus))
266 goto err_out_free_mdio_irq;
268 if (macb_mii_probe(bp->dev) != 0) {
269 goto err_out_unregister_bus;
274 err_out_unregister_bus:
275 mdiobus_unregister(bp->mii_bus);
276 err_out_free_mdio_irq:
277 kfree(bp->mii_bus->irq);
278 err_out_free_mdiobus:
279 mdiobus_free(bp->mii_bus);
284 static void macb_update_stats(struct macb *bp)
286 u32 __iomem *reg = bp->regs + MACB_PFR;
287 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
288 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
290 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
292 for(; p < end; p++, reg++)
293 *p += __raw_readl(reg);
296 static void macb_tx(struct macb *bp)
302 status = macb_readl(bp, TSR);
303 macb_writel(bp, TSR, status);
305 netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status);
307 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
309 netdev_err(bp->dev, "TX %s, resetting buffers\n",
310 status & MACB_BIT(UND) ?
311 "underrun" : "retry limit exceeded");
313 /* Transfer ongoing, disable transmitter, to avoid confusion */
314 if (status & MACB_BIT(TGO))
315 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
319 /*Mark all the buffer as used to avoid sending a lost buffer*/
320 for (i = 0; i < TX_RING_SIZE; i++)
321 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
324 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
326 /* free transmit buffer in upper layer*/
327 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
328 struct ring_info *rp = &bp->tx_skb[tail];
329 struct sk_buff *skb = rp->skb;
335 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
338 dev_kfree_skb_irq(skb);
341 bp->tx_head = bp->tx_tail = 0;
343 /* Enable the transmitter again */
344 if (status & MACB_BIT(TGO))
345 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
348 if (!(status & MACB_BIT(COMP)))
350 * This may happen when a buffer becomes complete
351 * between reading the ISR and scanning the
352 * descriptors. Nothing to worry about.
357 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
358 struct ring_info *rp = &bp->tx_skb[tail];
359 struct sk_buff *skb = rp->skb;
365 bufstat = bp->tx_ring[tail].ctrl;
367 if (!(bufstat & MACB_BIT(TX_USED)))
370 netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n",
372 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
374 bp->stats.tx_packets++;
375 bp->stats.tx_bytes += skb->len;
377 dev_kfree_skb_irq(skb);
381 if (netif_queue_stopped(bp->dev) &&
382 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
383 netif_wake_queue(bp->dev);
386 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
387 unsigned int last_frag)
391 unsigned int offset = 0;
394 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
396 netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
397 first_frag, last_frag, len);
399 skb = dev_alloc_skb(len + RX_OFFSET);
401 bp->stats.rx_dropped++;
402 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
403 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
404 if (frag == last_frag)
411 skb_reserve(skb, RX_OFFSET);
412 skb_checksum_none_assert(skb);
415 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
416 unsigned int frag_len = RX_BUFFER_SIZE;
418 if (offset + frag_len > len) {
419 BUG_ON(frag != last_frag);
420 frag_len = len - offset;
422 skb_copy_to_linear_data_offset(skb, offset,
424 (RX_BUFFER_SIZE * frag)),
426 offset += RX_BUFFER_SIZE;
427 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
430 if (frag == last_frag)
434 skb->protocol = eth_type_trans(skb, bp->dev);
436 bp->stats.rx_packets++;
437 bp->stats.rx_bytes += len;
438 netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n",
439 skb->len, skb->csum);
440 netif_receive_skb(skb);
445 /* Mark DMA descriptors from begin up to and not including end as unused */
446 static void discard_partial_frame(struct macb *bp, unsigned int begin,
451 for (frag = begin; frag != end; frag = NEXT_RX(frag))
452 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
456 * When this happens, the hardware stats registers for
457 * whatever caused this is updated, so we don't have to record
462 static int macb_rx(struct macb *bp, int budget)
465 unsigned int tail = bp->rx_tail;
468 for (; budget > 0; tail = NEXT_RX(tail)) {
472 addr = bp->rx_ring[tail].addr;
473 ctrl = bp->rx_ring[tail].ctrl;
475 if (!(addr & MACB_BIT(RX_USED)))
478 if (ctrl & MACB_BIT(RX_SOF)) {
479 if (first_frag != -1)
480 discard_partial_frame(bp, first_frag, tail);
484 if (ctrl & MACB_BIT(RX_EOF)) {
486 BUG_ON(first_frag == -1);
488 dropped = macb_rx_frame(bp, first_frag, tail);
497 if (first_frag != -1)
498 bp->rx_tail = first_frag;
505 static int macb_poll(struct napi_struct *napi, int budget)
507 struct macb *bp = container_of(napi, struct macb, napi);
511 status = macb_readl(bp, RSR);
512 macb_writel(bp, RSR, status);
516 netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n",
517 (unsigned long)status, budget);
519 work_done = macb_rx(bp, budget);
520 if (work_done < budget) {
524 * We've done what we can to clean the buffers. Make sure we
525 * get notified when new packets arrive.
527 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
530 /* TODO: Handle errors */
535 static irqreturn_t macb_interrupt(int irq, void *dev_id)
537 struct net_device *dev = dev_id;
538 struct macb *bp = netdev_priv(dev);
541 status = macb_readl(bp, ISR);
543 if (unlikely(!status))
546 spin_lock(&bp->lock);
549 /* close possible race with dev_close */
550 if (unlikely(!netif_running(dev))) {
551 macb_writel(bp, IDR, ~0UL);
555 if (status & MACB_RX_INT_FLAGS) {
557 * There's no point taking any more interrupts
558 * until we have processed the buffers. The
559 * scheduling call may fail if the poll routine
560 * is already scheduled, so disable interrupts
563 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
565 if (napi_schedule_prep(&bp->napi)) {
566 netdev_dbg(bp->dev, "scheduling RX softirq\n");
567 __napi_schedule(&bp->napi);
571 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
576 * Link change detection isn't possible with RMII, so we'll
577 * add that if/when we get our hands on a full-blown MII PHY.
580 if (status & MACB_BIT(ISR_ROVR)) {
581 /* We missed at least one packet */
583 bp->hw_stats.gem.rx_overruns++;
585 bp->hw_stats.macb.rx_overruns++;
588 if (status & MACB_BIT(HRESP)) {
590 * TODO: Reset the hardware, and maybe move the
591 * netdev_err to a lower-priority context as well
594 netdev_err(dev, "DMA bus error: HRESP not OK\n");
597 status = macb_readl(bp, ISR);
600 spin_unlock(&bp->lock);
605 #ifdef CONFIG_NET_POLL_CONTROLLER
607 * Polling receive - used by netconsole and other diagnostic tools
608 * to allow network i/o with interrupts disabled.
610 static void macb_poll_controller(struct net_device *dev)
614 local_irq_save(flags);
615 macb_interrupt(dev->irq, dev);
616 local_irq_restore(flags);
620 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
622 struct macb *bp = netdev_priv(dev);
624 unsigned int len, entry;
630 "start_xmit: len %u head %p data %p tail %p end %p\n",
631 skb->len, skb->head, skb->data,
632 skb_tail_pointer(skb), skb_end_pointer(skb));
633 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
634 skb->data, 16, true);
638 spin_lock_irqsave(&bp->lock, flags);
640 /* This is a hard error, log it. */
641 if (TX_BUFFS_AVAIL(bp) < 1) {
642 netif_stop_queue(dev);
643 spin_unlock_irqrestore(&bp->lock, flags);
644 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
645 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
646 bp->tx_head, bp->tx_tail);
647 return NETDEV_TX_BUSY;
651 netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry);
652 mapping = dma_map_single(&bp->pdev->dev, skb->data,
654 bp->tx_skb[entry].skb = skb;
655 bp->tx_skb[entry].mapping = mapping;
656 netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
657 skb->data, (unsigned long)mapping);
659 ctrl = MACB_BF(TX_FRMLEN, len);
660 ctrl |= MACB_BIT(TX_LAST);
661 if (entry == (TX_RING_SIZE - 1))
662 ctrl |= MACB_BIT(TX_WRAP);
664 bp->tx_ring[entry].addr = mapping;
665 bp->tx_ring[entry].ctrl = ctrl;
668 entry = NEXT_TX(entry);
671 skb_tx_timestamp(skb);
673 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
675 if (TX_BUFFS_AVAIL(bp) < 1)
676 netif_stop_queue(dev);
678 spin_unlock_irqrestore(&bp->lock, flags);
683 static void macb_free_consistent(struct macb *bp)
690 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
691 bp->rx_ring, bp->rx_ring_dma);
695 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
696 bp->tx_ring, bp->tx_ring_dma);
699 if (bp->rx_buffers) {
700 dma_free_coherent(&bp->pdev->dev,
701 RX_RING_SIZE * RX_BUFFER_SIZE,
702 bp->rx_buffers, bp->rx_buffers_dma);
703 bp->rx_buffers = NULL;
707 static int macb_alloc_consistent(struct macb *bp)
711 size = TX_RING_SIZE * sizeof(struct ring_info);
712 bp->tx_skb = kmalloc(size, GFP_KERNEL);
716 size = RX_RING_BYTES;
717 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
718 &bp->rx_ring_dma, GFP_KERNEL);
722 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
723 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
725 size = TX_RING_BYTES;
726 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
727 &bp->tx_ring_dma, GFP_KERNEL);
731 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
732 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
734 size = RX_RING_SIZE * RX_BUFFER_SIZE;
735 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
736 &bp->rx_buffers_dma, GFP_KERNEL);
740 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
741 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
746 macb_free_consistent(bp);
750 static void macb_init_rings(struct macb *bp)
755 addr = bp->rx_buffers_dma;
756 for (i = 0; i < RX_RING_SIZE; i++) {
757 bp->rx_ring[i].addr = addr;
758 bp->rx_ring[i].ctrl = 0;
759 addr += RX_BUFFER_SIZE;
761 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
763 for (i = 0; i < TX_RING_SIZE; i++) {
764 bp->tx_ring[i].addr = 0;
765 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
767 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
769 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
772 static void macb_reset_hw(struct macb *bp)
774 /* Make sure we have the write buffer for ourselves */
778 * Disable RX and TX (XXX: Should we halt the transmission
781 macb_writel(bp, NCR, 0);
783 /* Clear the stats registers (XXX: Update stats first?) */
784 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
786 /* Clear all status flags */
787 macb_writel(bp, TSR, ~0UL);
788 macb_writel(bp, RSR, ~0UL);
790 /* Disable all interrupts */
791 macb_writel(bp, IDR, ~0UL);
795 static u32 gem_mdc_clk_div(struct macb *bp)
798 unsigned long pclk_hz = clk_get_rate(bp->pclk);
800 if (pclk_hz <= 20000000)
801 config = GEM_BF(CLK, GEM_CLK_DIV8);
802 else if (pclk_hz <= 40000000)
803 config = GEM_BF(CLK, GEM_CLK_DIV16);
804 else if (pclk_hz <= 80000000)
805 config = GEM_BF(CLK, GEM_CLK_DIV32);
806 else if (pclk_hz <= 120000000)
807 config = GEM_BF(CLK, GEM_CLK_DIV48);
808 else if (pclk_hz <= 160000000)
809 config = GEM_BF(CLK, GEM_CLK_DIV64);
811 config = GEM_BF(CLK, GEM_CLK_DIV96);
816 static u32 macb_mdc_clk_div(struct macb *bp)
819 unsigned long pclk_hz;
822 return gem_mdc_clk_div(bp);
824 pclk_hz = clk_get_rate(bp->pclk);
825 if (pclk_hz <= 20000000)
826 config = MACB_BF(CLK, MACB_CLK_DIV8);
827 else if (pclk_hz <= 40000000)
828 config = MACB_BF(CLK, MACB_CLK_DIV16);
829 else if (pclk_hz <= 80000000)
830 config = MACB_BF(CLK, MACB_CLK_DIV32);
832 config = MACB_BF(CLK, MACB_CLK_DIV64);
838 * Get the DMA bus width field of the network configuration register that we
839 * should program. We find the width from decoding the design configuration
840 * register to find the maximum supported data bus width.
842 static u32 macb_dbw(struct macb *bp)
844 if (!macb_is_gem(bp))
847 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
849 return GEM_BF(DBW, GEM_DBW128);
851 return GEM_BF(DBW, GEM_DBW64);
854 return GEM_BF(DBW, GEM_DBW32);
859 * Configure the receive DMA engine to use the correct receive buffer size.
860 * This is a configurable parameter for GEM.
862 static void macb_configure_dma(struct macb *bp)
866 if (macb_is_gem(bp)) {
867 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
868 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
869 gem_writel(bp, DMACFG, dmacfg);
873 static void macb_init_hw(struct macb *bp)
878 __macb_set_hwaddr(bp);
880 config = macb_mdc_clk_div(bp);
881 config |= MACB_BIT(PAE); /* PAuse Enable */
882 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
883 config |= MACB_BIT(BIG); /* Receive oversized frames */
884 if (bp->dev->flags & IFF_PROMISC)
885 config |= MACB_BIT(CAF); /* Copy All Frames */
886 if (!(bp->dev->flags & IFF_BROADCAST))
887 config |= MACB_BIT(NBC); /* No BroadCast */
888 config |= macb_dbw(bp);
889 macb_writel(bp, NCFGR, config);
891 macb_configure_dma(bp);
893 /* Initialize TX and RX buffers */
894 macb_writel(bp, RBQP, bp->rx_ring_dma);
895 macb_writel(bp, TBQP, bp->tx_ring_dma);
897 /* Enable TX and RX */
898 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
900 /* Enable interrupts */
901 macb_writel(bp, IER, (MACB_BIT(RCOMP)
913 * The hash address register is 64 bits long and takes up two
914 * locations in the memory map. The least significant bits are stored
915 * in EMAC_HSL and the most significant bits in EMAC_HSH.
917 * The unicast hash enable and the multicast hash enable bits in the
918 * network configuration register enable the reception of hash matched
919 * frames. The destination address is reduced to a 6 bit index into
920 * the 64 bit hash register using the following hash function. The
921 * hash function is an exclusive or of every sixth bit of the
922 * destination address.
924 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
925 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
926 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
927 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
928 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
929 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
931 * da[0] represents the least significant bit of the first byte
932 * received, that is, the multicast/unicast indicator, and da[47]
933 * represents the most significant bit of the last byte received. If
934 * the hash index, hi[n], points to a bit that is set in the hash
935 * register then the frame will be matched according to whether the
936 * frame is multicast or unicast. A multicast match will be signalled
937 * if the multicast hash enable bit is set, da[0] is 1 and the hash
938 * index points to a bit set in the hash register. A unicast match
939 * will be signalled if the unicast hash enable bit is set, da[0] is 0
940 * and the hash index points to a bit set in the hash register. To
941 * receive all multicast frames, the hash register should be set with
942 * all ones and the multicast hash enable bit should be set in the
943 * network configuration register.
946 static inline int hash_bit_value(int bitnr, __u8 *addr)
948 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
954 * Return the hash index value for the specified address.
956 static int hash_get_index(__u8 *addr)
961 for (j = 0; j < 6; j++) {
962 for (i = 0, bitval = 0; i < 8; i++)
963 bitval ^= hash_bit_value(i*6 + j, addr);
965 hash_index |= (bitval << j);
972 * Add multicast addresses to the internal multicast-hash table.
974 static void macb_sethashtable(struct net_device *dev)
976 struct netdev_hw_addr *ha;
977 unsigned long mc_filter[2];
979 struct macb *bp = netdev_priv(dev);
981 mc_filter[0] = mc_filter[1] = 0;
983 netdev_for_each_mc_addr(ha, dev) {
984 bitnr = hash_get_index(ha->addr);
985 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
988 macb_or_gem_writel(bp, HRB, mc_filter[0]);
989 macb_or_gem_writel(bp, HRT, mc_filter[1]);
993 * Enable/Disable promiscuous and multicast modes.
995 static void macb_set_rx_mode(struct net_device *dev)
998 struct macb *bp = netdev_priv(dev);
1000 cfg = macb_readl(bp, NCFGR);
1002 if (dev->flags & IFF_PROMISC)
1003 /* Enable promiscuous mode */
1004 cfg |= MACB_BIT(CAF);
1005 else if (dev->flags & (~IFF_PROMISC))
1006 /* Disable promiscuous mode */
1007 cfg &= ~MACB_BIT(CAF);
1009 if (dev->flags & IFF_ALLMULTI) {
1010 /* Enable all multicast mode */
1011 macb_or_gem_writel(bp, HRB, -1);
1012 macb_or_gem_writel(bp, HRT, -1);
1013 cfg |= MACB_BIT(NCFGR_MTI);
1014 } else if (!netdev_mc_empty(dev)) {
1015 /* Enable specific multicasts */
1016 macb_sethashtable(dev);
1017 cfg |= MACB_BIT(NCFGR_MTI);
1018 } else if (dev->flags & (~IFF_ALLMULTI)) {
1019 /* Disable all multicast mode */
1020 macb_or_gem_writel(bp, HRB, 0);
1021 macb_or_gem_writel(bp, HRT, 0);
1022 cfg &= ~MACB_BIT(NCFGR_MTI);
1025 macb_writel(bp, NCFGR, cfg);
1028 static int macb_open(struct net_device *dev)
1030 struct macb *bp = netdev_priv(dev);
1033 netdev_dbg(bp->dev, "open\n");
1035 /* if the phy is not yet register, retry later*/
1039 if (!is_valid_ether_addr(dev->dev_addr))
1040 return -EADDRNOTAVAIL;
1042 err = macb_alloc_consistent(bp);
1044 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1049 napi_enable(&bp->napi);
1051 macb_init_rings(bp);
1054 /* schedule a link state check */
1055 phy_start(bp->phy_dev);
1057 netif_start_queue(dev);
1062 static int macb_close(struct net_device *dev)
1064 struct macb *bp = netdev_priv(dev);
1065 unsigned long flags;
1067 netif_stop_queue(dev);
1068 napi_disable(&bp->napi);
1071 phy_stop(bp->phy_dev);
1073 spin_lock_irqsave(&bp->lock, flags);
1075 netif_carrier_off(dev);
1076 spin_unlock_irqrestore(&bp->lock, flags);
1078 macb_free_consistent(bp);
1083 static void gem_update_stats(struct macb *bp)
1085 u32 __iomem *reg = bp->regs + GEM_OTX;
1086 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1087 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1089 for (; p < end; p++, reg++)
1090 *p += __raw_readl(reg);
1093 static struct net_device_stats *gem_get_stats(struct macb *bp)
1095 struct gem_stats *hwstat = &bp->hw_stats.gem;
1096 struct net_device_stats *nstat = &bp->stats;
1098 gem_update_stats(bp);
1100 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1101 hwstat->rx_alignment_errors +
1102 hwstat->rx_resource_errors +
1103 hwstat->rx_overruns +
1104 hwstat->rx_oversize_frames +
1105 hwstat->rx_jabbers +
1106 hwstat->rx_undersized_frames +
1107 hwstat->rx_length_field_frame_errors);
1108 nstat->tx_errors = (hwstat->tx_late_collisions +
1109 hwstat->tx_excessive_collisions +
1110 hwstat->tx_underrun +
1111 hwstat->tx_carrier_sense_errors);
1112 nstat->multicast = hwstat->rx_multicast_frames;
1113 nstat->collisions = (hwstat->tx_single_collision_frames +
1114 hwstat->tx_multiple_collision_frames +
1115 hwstat->tx_excessive_collisions);
1116 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1117 hwstat->rx_jabbers +
1118 hwstat->rx_undersized_frames +
1119 hwstat->rx_length_field_frame_errors);
1120 nstat->rx_over_errors = hwstat->rx_resource_errors;
1121 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1122 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1123 nstat->rx_fifo_errors = hwstat->rx_overruns;
1124 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1125 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1126 nstat->tx_fifo_errors = hwstat->tx_underrun;
1131 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1133 struct macb *bp = netdev_priv(dev);
1134 struct net_device_stats *nstat = &bp->stats;
1135 struct macb_stats *hwstat = &bp->hw_stats.macb;
1137 if (macb_is_gem(bp))
1138 return gem_get_stats(bp);
1140 /* read stats from hardware */
1141 macb_update_stats(bp);
1143 /* Convert HW stats into netdevice stats */
1144 nstat->rx_errors = (hwstat->rx_fcs_errors +
1145 hwstat->rx_align_errors +
1146 hwstat->rx_resource_errors +
1147 hwstat->rx_overruns +
1148 hwstat->rx_oversize_pkts +
1149 hwstat->rx_jabbers +
1150 hwstat->rx_undersize_pkts +
1151 hwstat->sqe_test_errors +
1152 hwstat->rx_length_mismatch);
1153 nstat->tx_errors = (hwstat->tx_late_cols +
1154 hwstat->tx_excessive_cols +
1155 hwstat->tx_underruns +
1156 hwstat->tx_carrier_errors);
1157 nstat->collisions = (hwstat->tx_single_cols +
1158 hwstat->tx_multiple_cols +
1159 hwstat->tx_excessive_cols);
1160 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1161 hwstat->rx_jabbers +
1162 hwstat->rx_undersize_pkts +
1163 hwstat->rx_length_mismatch);
1164 nstat->rx_over_errors = hwstat->rx_resource_errors +
1165 hwstat->rx_overruns;
1166 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1167 nstat->rx_frame_errors = hwstat->rx_align_errors;
1168 nstat->rx_fifo_errors = hwstat->rx_overruns;
1169 /* XXX: What does "missed" mean? */
1170 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1171 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1172 nstat->tx_fifo_errors = hwstat->tx_underruns;
1173 /* Don't know about heartbeat or window errors... */
1178 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1180 struct macb *bp = netdev_priv(dev);
1181 struct phy_device *phydev = bp->phy_dev;
1186 return phy_ethtool_gset(phydev, cmd);
1189 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1191 struct macb *bp = netdev_priv(dev);
1192 struct phy_device *phydev = bp->phy_dev;
1197 return phy_ethtool_sset(phydev, cmd);
1200 static void macb_get_drvinfo(struct net_device *dev,
1201 struct ethtool_drvinfo *info)
1203 struct macb *bp = netdev_priv(dev);
1205 strcpy(info->driver, bp->pdev->dev.driver->name);
1206 strcpy(info->version, "$Revision: 1.14 $");
1207 strcpy(info->bus_info, dev_name(&bp->pdev->dev));
1210 static const struct ethtool_ops macb_ethtool_ops = {
1211 .get_settings = macb_get_settings,
1212 .set_settings = macb_set_settings,
1213 .get_drvinfo = macb_get_drvinfo,
1214 .get_link = ethtool_op_get_link,
1217 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1219 struct macb *bp = netdev_priv(dev);
1220 struct phy_device *phydev = bp->phy_dev;
1222 if (!netif_running(dev))
1228 return phy_mii_ioctl(phydev, rq, cmd);
1231 static const struct net_device_ops macb_netdev_ops = {
1232 .ndo_open = macb_open,
1233 .ndo_stop = macb_close,
1234 .ndo_start_xmit = macb_start_xmit,
1235 .ndo_set_rx_mode = macb_set_rx_mode,
1236 .ndo_get_stats = macb_get_stats,
1237 .ndo_do_ioctl = macb_ioctl,
1238 .ndo_validate_addr = eth_validate_addr,
1239 .ndo_change_mtu = eth_change_mtu,
1240 .ndo_set_mac_address = eth_mac_addr,
1241 #ifdef CONFIG_NET_POLL_CONTROLLER
1242 .ndo_poll_controller = macb_poll_controller,
1246 #if defined(CONFIG_OF)
1247 static const struct of_device_id macb_dt_ids[] = {
1248 { .compatible = "cdns,at32ap7000-macb" },
1249 { .compatible = "cdns,at91sam9260-macb" },
1250 { .compatible = "cdns,macb" },
1251 { .compatible = "cdns,pc302-gem" },
1252 { .compatible = "cdns,gem" },
1256 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1258 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1260 struct device_node *np = pdev->dev.of_node;
1263 return of_get_phy_mode(np);
1268 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1270 struct device_node *np = bp->pdev->dev.of_node;
1272 const char *mac = of_get_mac_address(np);
1274 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1282 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1286 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1292 static int __init macb_probe(struct platform_device *pdev)
1294 struct macb_platform_data *pdata;
1295 struct resource *regs;
1296 struct net_device *dev;
1298 struct phy_device *phydev;
1302 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304 dev_err(&pdev->dev, "no mmio resource defined\n");
1309 dev = alloc_etherdev(sizeof(*bp));
1311 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1315 SET_NETDEV_DEV(dev, &pdev->dev);
1317 /* TODO: Actually, we have some interesting features... */
1320 bp = netdev_priv(dev);
1324 spin_lock_init(&bp->lock);
1326 bp->pclk = clk_get(&pdev->dev, "pclk");
1327 if (IS_ERR(bp->pclk)) {
1328 dev_err(&pdev->dev, "failed to get macb_clk\n");
1329 goto err_out_free_dev;
1331 clk_enable(bp->pclk);
1333 bp->hclk = clk_get(&pdev->dev, "hclk");
1334 if (IS_ERR(bp->hclk)) {
1335 dev_err(&pdev->dev, "failed to get hclk\n");
1336 goto err_out_put_pclk;
1338 clk_enable(bp->hclk);
1340 bp->regs = ioremap(regs->start, resource_size(regs));
1342 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1344 goto err_out_disable_clocks;
1347 dev->irq = platform_get_irq(pdev, 0);
1348 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1350 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1352 goto err_out_iounmap;
1355 dev->netdev_ops = &macb_netdev_ops;
1356 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1357 dev->ethtool_ops = &macb_ethtool_ops;
1359 dev->base_addr = regs->start;
1361 /* Set MII management clock divider */
1362 config = macb_mdc_clk_div(bp);
1363 config |= macb_dbw(bp);
1364 macb_writel(bp, NCFGR, config);
1366 err = macb_get_hwaddr_dt(bp);
1368 macb_get_hwaddr(bp);
1370 err = macb_get_phy_mode_dt(pdev);
1372 pdata = pdev->dev.platform_data;
1373 if (pdata && pdata->is_rmii)
1374 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1376 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1378 bp->phy_interface = err;
1381 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1382 #if defined(CONFIG_ARCH_AT91)
1383 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1386 macb_or_gem_writel(bp, USRIO, 0);
1389 #if defined(CONFIG_ARCH_AT91)
1390 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1392 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1395 bp->tx_pending = DEF_TX_RING_PENDING;
1397 err = register_netdev(dev);
1399 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1400 goto err_out_free_irq;
1403 if (macb_mii_init(bp) != 0) {
1404 goto err_out_unregister_netdev;
1407 platform_set_drvdata(pdev, dev);
1409 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1410 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1411 dev->irq, dev->dev_addr);
1413 phydev = bp->phy_dev;
1414 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1415 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1419 err_out_unregister_netdev:
1420 unregister_netdev(dev);
1422 free_irq(dev->irq, dev);
1425 err_out_disable_clocks:
1426 clk_disable(bp->hclk);
1428 clk_disable(bp->pclk);
1434 platform_set_drvdata(pdev, NULL);
1438 static int __exit macb_remove(struct platform_device *pdev)
1440 struct net_device *dev;
1443 dev = platform_get_drvdata(pdev);
1446 bp = netdev_priv(dev);
1448 phy_disconnect(bp->phy_dev);
1449 mdiobus_unregister(bp->mii_bus);
1450 kfree(bp->mii_bus->irq);
1451 mdiobus_free(bp->mii_bus);
1452 unregister_netdev(dev);
1453 free_irq(dev->irq, dev);
1455 clk_disable(bp->hclk);
1457 clk_disable(bp->pclk);
1460 platform_set_drvdata(pdev, NULL);
1467 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1469 struct net_device *netdev = platform_get_drvdata(pdev);
1470 struct macb *bp = netdev_priv(netdev);
1472 netif_device_detach(netdev);
1474 clk_disable(bp->hclk);
1475 clk_disable(bp->pclk);
1480 static int macb_resume(struct platform_device *pdev)
1482 struct net_device *netdev = platform_get_drvdata(pdev);
1483 struct macb *bp = netdev_priv(netdev);
1485 clk_enable(bp->pclk);
1486 clk_enable(bp->hclk);
1488 netif_device_attach(netdev);
1493 #define macb_suspend NULL
1494 #define macb_resume NULL
1497 static struct platform_driver macb_driver = {
1498 .remove = __exit_p(macb_remove),
1499 .suspend = macb_suspend,
1500 .resume = macb_resume,
1503 .owner = THIS_MODULE,
1504 .of_match_table = of_match_ptr(macb_dt_ids),
1508 static int __init macb_init(void)
1510 return platform_driver_probe(&macb_driver, macb_probe);
1513 static void __exit macb_exit(void)
1515 platform_driver_unregister(&macb_driver);
1518 module_init(macb_init);
1519 module_exit(macb_exit);
1521 MODULE_LICENSE("GPL");
1522 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1523 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1524 MODULE_ALIAS("platform:macb");