1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
23 /*! \file liquidio_common.h
24 * \brief Common: Structures and macros used in PCI-NIC package by core and
28 #ifndef __LIQUIDIO_COMMON_H__
29 #define __LIQUIDIO_COMMON_H__
31 #include "octeon_config.h"
33 #define LIQUIDIO_PACKAGE ""
34 #define LIQUIDIO_BASE_MAJOR_VERSION 1
35 #define LIQUIDIO_BASE_MINOR_VERSION 4
36 #define LIQUIDIO_BASE_MICRO_VERSION 1
37 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
38 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
39 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
40 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
41 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
42 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
43 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
53 /** Tag types used by Octeon cores in its work. */
54 enum octeon_tag_type {
61 /* pre-defined host->NIC tag values */
62 #define LIO_CONTROL (0x11111110)
63 #define LIO_DATA(i) (0x11111111 + (i))
65 /* Opcodes used by host driver/apps to perform operations on the core.
66 * These are used to identify the major subsystem that the operation
69 #define OPCODE_CORE 0 /* used for generic core operations */
70 #define OPCODE_NIC 1 /* used for NIC operations */
71 /* Subcodes are used by host driver/apps to identify the sub-operation
72 * for the core. They only need to by unique for a given subsystem.
74 #define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f))
76 /** OPCODE_CORE subcodes. For future use. */
78 /** OPCODE_NIC subcodes */
80 /* This subcode is sent by core PCI driver to indicate cores are ready. */
81 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
82 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
83 #define OPCODE_NIC_CMD 0x03
84 #define OPCODE_NIC_INFO 0x04
85 #define OPCODE_NIC_PORT_STATS 0x05
86 #define OPCODE_NIC_MDIO45 0x06
87 #define OPCODE_NIC_TIMESTAMP 0x07
88 #define OPCODE_NIC_INTRMOD_CFG 0x08
89 #define OPCODE_NIC_IF_CFG 0x09
90 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
91 #define VF_DRV_LOADED 1
92 #define VF_DRV_REMOVED -1
93 #define VF_DRV_MACADDR_CHANGED 2
95 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
97 #define OPCODE_SLOW_PATH(rh) \
98 (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
99 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
101 /* Application codes advertised by the core driver initialization packet. */
102 #define CVM_DRV_APP_START 0x0
103 #define CVM_DRV_NO_APP 0
104 #define CVM_DRV_APP_COUNT 0x2
105 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
106 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
107 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
108 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
110 /* Macro to increment index.
111 * Index is incremented by count; if the sum exceeds
112 * max, index is wrapped-around to the start.
114 #define INCR_INDEX(index, count, max) \
116 if (((index) + (count)) >= (max)) \
117 index = ((index) + (count)) - (max); \
122 #define INCR_INDEX_BY1(index, max) \
124 if ((++(index)) == (max)) \
128 #define DECR_INDEX(index, count, max) \
130 if ((count) > (index)) \
131 index = ((max) - ((count - index))); \
136 #define OCT_BOARD_NAME 32
137 #define OCT_SERIAL_LEN 64
139 /* Structure used by core driver to send indication that the Octeon
140 * application is ready.
142 struct octeon_core_setup {
145 char boardname[OCT_BOARD_NAME];
147 char board_serial_number[OCT_SERIAL_LEN];
155 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
157 /* The Scatter-Gather List Entry. The scatter or gather component used with
158 * a Octeon input instruction has this format.
160 struct octeon_sg_entry {
161 /** The first 64 bit gives the size of data in each dptr.*/
167 /** The 4 dptr pointers for this entry. */
172 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
174 /* \brief Add size to gather list
175 * @param sg_entry scatter/gather entry
176 * @param size size to add
177 * @param pos position to add it.
179 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
183 #ifdef __BIG_ENDIAN_BITFIELD
184 sg_entry->u.size[pos] = size;
186 sg_entry->u.size[3 - pos] = size;
190 /*------------------------- End Scatter/Gather ---------------------------*/
192 #define OCTNET_FRM_PTP_HEADER_SIZE 8
194 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
196 #define OCTNET_MIN_FRM_SIZE 64
198 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
200 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
202 /** NIC Commands are sent using this Octeon Input Queue */
203 #define OCTNET_CMD_Q 0
205 /* NIC Command types */
206 #define OCTNET_CMD_CHANGE_MTU 0x1
207 #define OCTNET_CMD_CHANGE_MACADDR 0x2
208 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
209 #define OCTNET_CMD_RX_CTL 0x4
211 #define OCTNET_CMD_SET_MULTI_LIST 0x5
212 #define OCTNET_CMD_CLEAR_STATS 0x6
214 /* command for setting the speed, duplex & autoneg */
215 #define OCTNET_CMD_SET_SETTINGS 0x7
216 #define OCTNET_CMD_SET_FLOW_CTL 0x8
218 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
219 #define OCTNET_CMD_GPIO_ACCESS 0xA
220 #define OCTNET_CMD_LRO_ENABLE 0xB
221 #define OCTNET_CMD_LRO_DISABLE 0xC
222 #define OCTNET_CMD_SET_RSS 0xD
223 #define OCTNET_CMD_WRITE_SA 0xE
224 #define OCTNET_CMD_DELETE_SA 0xF
225 #define OCTNET_CMD_UPDATE_SA 0x12
227 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
228 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
229 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
230 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
231 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
233 #define OCTNET_CMD_ENABLE_VLAN_FILTER 0x16
234 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
235 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
236 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
238 #define OCTNET_CMD_ID_ACTIVE 0x1a
240 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
241 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
242 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
243 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
244 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
245 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
246 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
248 /* RX(packets coming from wire) Checksum verification flags */
250 #define CNNIC_L4SUM_VERIFIED 0x1
251 #define CNNIC_IPSUM_VERIFIED 0x2
252 #define CNNIC_TUN_CSUM_VERIFIED 0x4
253 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
255 /*LROIPV4 and LROIPV6 Flags*/
256 #define OCTNIC_LROIPV4 0x1
257 #define OCTNIC_LROIPV6 0x2
259 /* Interface flags communicated between host driver and core app. */
260 enum octnet_ifflags {
261 OCTNET_IFFLAG_PROMISC = 0x01,
262 OCTNET_IFFLAG_ALLMULTI = 0x02,
263 OCTNET_IFFLAG_MULTICAST = 0x04,
264 OCTNET_IFFLAG_BROADCAST = 0x08,
265 OCTNET_IFFLAG_UNICAST = 0x10
289 #ifdef __BIG_ENDIAN_BITFIELD
292 u64 more:6; /* How many udd words follow the command */
317 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
319 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
320 #define LIO_SOFTCMDRESP_IH2 40
321 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
323 #define LIO_PCICMD_O2 24
324 #define LIO_PCICMD_O3 (24 + 8)
326 /* Instruction Header(DPI) - for OCTEON-III models */
327 struct octeon_instr_ih3 {
328 #ifdef __BIG_ENDIAN_BITFIELD
333 /** Gather indicator 1=gather*/
336 /** Data length OR no. of entries in gather list */
339 /** Front Data size */
345 /** PKI port kind - PKIND */
355 /** PKI port kind - PKIND */
361 /** Front Data size */
364 /** Data length OR no. of entries in gather list */
367 /** Gather indicator 1=gather*/
376 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
377 /** BIG ENDIAN format. */
378 struct octeon_instr_pki_ih3 {
379 #ifdef __BIG_ENDIAN_BITFIELD
384 /** Raw mode indicator 1 = RAW */
449 /** Raw mode indicator 1 = RAW */
458 /** Instruction Header */
459 struct octeon_instr_ih2 {
460 #ifdef __BIG_ENDIAN_BITFIELD
461 /** Raw mode indicator 1 = RAW */
464 /** Gather indicator 1=gather*/
467 /** Data length OR no. of entries in gather list */
470 /** Front Data size */
473 /** Packet Order / Work Unit selection (1 of 8)*/
476 /** Core group selection (1 of 16) */
479 /** Short Raw Packet Indicator 1=short raw pkt */
494 /** Short Raw Packet Indicator 1=short raw pkt */
497 /** Core group selection (1 of 16) */
500 /** Packet Order / Work Unit selection (1 of 8)*/
503 /** Front Data size */
506 /** Data length OR no. of entries in gather list */
509 /** Gather indicator 1=gather*/
512 /** Raw mode indicator 1 = RAW */
517 /** Input Request Header */
518 struct octeon_instr_irh {
519 #ifdef __BIG_ENDIAN_BITFIELD
526 u64 ossp:32; /* opcode/subcode specific parameters */
528 u64 ossp:32; /* opcode/subcode specific parameters */
538 /** Return Data Parameters */
539 struct octeon_instr_rdp {
540 #ifdef __BIG_ENDIAN_BITFIELD
551 /** Receive Header */
553 #ifdef __BIG_ENDIAN_BITFIELD
558 u64 len:3; /** additional 64-bit words */
560 u64 ossp:32; /** opcode/subcode specific parameters */
565 u64 len:3; /** additional 64-bit words */
569 u64 csum_verified:3; /** checksum verified. */
570 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
572 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
577 u64 len:3; /** additional 64-bit words */
580 u64 max_nic_ports:10;
588 u64 len:3; /** additional 64-bit words */
596 u64 ossp:32; /** opcode/subcode specific parameters */
598 u64 len:3; /** additional 64-bit words */
603 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
605 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
606 u64 csum_verified:3; /** checksum verified. */
610 u64 len:3; /** additional 64-bit words */
618 u64 max_nic_ports:10;
621 u64 len:3; /** additional 64-bit words */
629 u64 len:3; /** additional 64-bit words */
636 #define OCT_RH_SIZE (sizeof(union octeon_rh))
638 union octnic_packet_params {
641 #ifdef __BIG_ENDIAN_BITFIELD
643 u32 ip_csum:1; /* Perform IP header checksum(s) */
644 /* Perform Outer transport header checksum */
645 u32 transport_csum:1;
646 /* Find tunnel, and perform transport csum. */
648 u32 tsflag:1; /* Timestamp this packet */
649 u32 ipsec_ops:4; /* IPsec operation */
654 u32 transport_csum:1;
661 /** Status of a RGMII Link on Octeon as seen by core driver. */
662 union oct_link_status {
666 #ifdef __BIG_ENDIAN_BITFIELD
690 /** The txpciq info passed to host from the firmware */
696 #ifdef __BIG_ENDIAN_BITFIELD
714 /** The rxpciq info passed to host from the firmware */
720 #ifdef __BIG_ENDIAN_BITFIELD
730 /** Information for a OCTEON ethernet interface shared between core & host. */
731 struct oct_link_info {
732 union oct_link_status link;
735 #ifdef __BIG_ENDIAN_BITFIELD
737 u64 macaddr_is_admin_asgnd:1;
745 u64 macaddr_is_admin_asgnd:1;
749 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
750 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
753 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
755 struct liquidio_if_cfg_info {
756 u64 iqmask; /** mask for IQs enabled for the port */
757 u64 oqmask; /** mask for OQs enabled for the port */
758 struct oct_link_info linfo; /** initial link information */
759 char liquidio_firmware_version[32];
762 /** Stats for each NIC port in RX direction. */
763 struct nic_rx_stats {
764 /* link-level stats */
771 u64 fifo_err; /* Accounts for over/under-run of buffers */
788 u64 fw_lro_pkts; /* Number of packets that are LROed */
789 u64 fw_lro_octs; /* Number of octets that are LROed */
790 u64 fw_total_lro; /* Number of LRO packets formed */
791 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
792 u64 fw_lro_aborts_port;
793 u64 fw_lro_aborts_seq;
794 u64 fw_lro_aborts_tsval;
795 u64 fw_lro_aborts_timer;
796 /* intrmod: packet forward rate */
800 /** Stats for each NIC port in RX direction. */
801 struct nic_tx_stats {
802 /* link-level stats */
804 u64 total_bytes_sent;
808 u64 one_collision_sent; /* Packets sent after one collision*/
809 u64 multi_collision_sent; /* Packets sent after multiple collision*/
810 u64 max_collision_fail; /* Packets not sent due to max collisions */
811 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
812 u64 fifo_err; /* Accounts for over/under-run of buffers */
814 u64 total_collisions; /* Total number of collisions detected */
819 u64 fw_total_fwd_bytes;
824 u64 fw_tso; /* number of tso requests */
825 u64 fw_tso_fwd; /* number of packets segmented in tso */
829 struct oct_link_stats {
830 struct nic_rx_stats fromwire;
831 struct nic_tx_stats fromhost;
835 #define LIO68XX_LED_CTRL_ADDR 0x3501
836 #define LIO68XX_LED_CTRL_CFGON 0x1f
837 #define LIO68XX_LED_CTRL_CFGOFF 0x100
838 #define LIO68XX_LED_BEACON_ADDR 0x3508
839 #define LIO68XX_LED_BEACON_CFGON 0x47fd
840 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
841 #define VITESSE_PHY_GPIO_DRIVEON 0x1
842 #define VITESSE_PHY_GPIO_CFG 0x8
843 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
844 #define VITESSE_PHY_GPIO_HIGH 0x2
845 #define VITESSE_PHY_GPIO_LOW 0x3
846 #define LED_IDENTIFICATION_ON 0x1
847 #define LED_IDENTIFICATION_OFF 0x0
849 struct oct_mdio_cmd {
857 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
859 /* intrmod: max. packet rate threshold */
860 #define LIO_INTRMOD_MAXPKT_RATETHR 196608
861 /* intrmod: min. packet rate threshold */
862 #define LIO_INTRMOD_MINPKT_RATETHR 9216
863 /* intrmod: max. packets to trigger interrupt */
864 #define LIO_INTRMOD_RXMAXCNT_TRIGGER 384
865 /* intrmod: min. packets to trigger interrupt */
866 #define LIO_INTRMOD_RXMINCNT_TRIGGER 0
867 /* intrmod: max. time to trigger interrupt */
868 #define LIO_INTRMOD_RXMAXTMR_TRIGGER 128
869 /* 66xx:intrmod: min. time to trigger interrupt
870 * (value of 1 is optimum for TCP_RR)
872 #define LIO_INTRMOD_RXMINTMR_TRIGGER 1
874 /* intrmod: max. packets to trigger interrupt */
875 #define LIO_INTRMOD_TXMAXCNT_TRIGGER 64
876 /* intrmod: min. packets to trigger interrupt */
877 #define LIO_INTRMOD_TXMINCNT_TRIGGER 0
879 /* intrmod: poll interval in seconds */
880 #define LIO_INTRMOD_CHECK_INTERVAL 1
882 struct oct_intrmod_cfg {
888 u64 rx_maxcnt_trigger;
889 u64 rx_mincnt_trigger;
890 u64 rx_maxtmr_trigger;
891 u64 rx_mintmr_trigger;
892 u64 tx_mincnt_trigger;
893 u64 tx_maxcnt_trigger;
899 #define BASE_QUEUE_NOT_REQUESTED 65535
901 union oct_nic_if_cfg {
904 #ifdef __BIG_ENDIAN_BITFIELD