1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
23 /*! \file liquidio_common.h
24 * \brief Common: Structures and macros used in PCI-NIC package by core and
28 #ifndef __LIQUIDIO_COMMON_H__
29 #define __LIQUIDIO_COMMON_H__
31 #include "octeon_config.h"
33 #define LIQUIDIO_PACKAGE ""
34 #define LIQUIDIO_BASE_MAJOR_VERSION 1
35 #define LIQUIDIO_BASE_MINOR_VERSION 4
36 #define LIQUIDIO_BASE_MICRO_VERSION 1
37 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
38 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
39 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
40 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
41 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
42 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
43 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
53 /** Tag types used by Octeon cores in its work. */
54 enum octeon_tag_type {
61 /* pre-defined host->NIC tag values */
62 #define LIO_CONTROL (0x11111110)
63 #define LIO_DATA(i) (0x11111111 + (i))
65 /* Opcodes used by host driver/apps to perform operations on the core.
66 * These are used to identify the major subsystem that the operation
69 #define OPCODE_CORE 0 /* used for generic core operations */
70 #define OPCODE_NIC 1 /* used for NIC operations */
71 #define OPCODE_LAST OPCODE_NIC
73 /* Subcodes are used by host driver/apps to identify the sub-operation
74 * for the core. They only need to by unique for a given subsystem.
76 #define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f))
78 /** OPCODE_CORE subcodes. For future use. */
80 /** OPCODE_NIC subcodes */
82 /* This subcode is sent by core PCI driver to indicate cores are ready. */
83 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
84 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
85 #define OPCODE_NIC_CMD 0x03
86 #define OPCODE_NIC_INFO 0x04
87 #define OPCODE_NIC_PORT_STATS 0x05
88 #define OPCODE_NIC_MDIO45 0x06
89 #define OPCODE_NIC_TIMESTAMP 0x07
90 #define OPCODE_NIC_INTRMOD_CFG 0x08
91 #define OPCODE_NIC_IF_CFG 0x09
93 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
95 #define OPCODE_SLOW_PATH(rh) \
96 (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
97 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
99 /* Application codes advertised by the core driver initialization packet. */
100 #define CVM_DRV_APP_START 0x0
101 #define CVM_DRV_NO_APP 0
102 #define CVM_DRV_APP_COUNT 0x2
103 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
104 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
105 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
106 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
108 /* Macro to increment index.
109 * Index is incremented by count; if the sum exceeds
110 * max, index is wrapped-around to the start.
112 #define INCR_INDEX(index, count, max) \
114 if (((index) + (count)) >= (max)) \
115 index = ((index) + (count)) - (max); \
120 #define INCR_INDEX_BY1(index, max) \
122 if ((++(index)) == (max)) \
126 #define DECR_INDEX(index, count, max) \
128 if ((count) > (index)) \
129 index = ((max) - ((count - index))); \
134 #define OCT_BOARD_NAME 32
135 #define OCT_SERIAL_LEN 64
137 /* Structure used by core driver to send indication that the Octeon
138 * application is ready.
140 struct octeon_core_setup {
143 char boardname[OCT_BOARD_NAME];
145 char board_serial_number[OCT_SERIAL_LEN];
153 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
155 /* The Scatter-Gather List Entry. The scatter or gather component used with
156 * a Octeon input instruction has this format.
158 struct octeon_sg_entry {
159 /** The first 64 bit gives the size of data in each dptr.*/
165 /** The 4 dptr pointers for this entry. */
170 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
172 /* \brief Add size to gather list
173 * @param sg_entry scatter/gather entry
174 * @param size size to add
175 * @param pos position to add it.
177 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
181 #ifdef __BIG_ENDIAN_BITFIELD
182 sg_entry->u.size[pos] = size;
184 sg_entry->u.size[3 - pos] = size;
188 /*------------------------- End Scatter/Gather ---------------------------*/
190 #define OCTNET_FRM_PTP_HEADER_SIZE 8
192 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
194 #define OCTNET_MIN_FRM_SIZE 64
196 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
198 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
200 /** NIC Commands are sent using this Octeon Input Queue */
201 #define OCTNET_CMD_Q 0
203 /* NIC Command types */
204 #define OCTNET_CMD_CHANGE_MTU 0x1
205 #define OCTNET_CMD_CHANGE_MACADDR 0x2
206 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
207 #define OCTNET_CMD_RX_CTL 0x4
209 #define OCTNET_CMD_SET_MULTI_LIST 0x5
210 #define OCTNET_CMD_CLEAR_STATS 0x6
212 /* command for setting the speed, duplex & autoneg */
213 #define OCTNET_CMD_SET_SETTINGS 0x7
214 #define OCTNET_CMD_SET_FLOW_CTL 0x8
216 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
217 #define OCTNET_CMD_GPIO_ACCESS 0xA
218 #define OCTNET_CMD_LRO_ENABLE 0xB
219 #define OCTNET_CMD_LRO_DISABLE 0xC
220 #define OCTNET_CMD_SET_RSS 0xD
221 #define OCTNET_CMD_WRITE_SA 0xE
222 #define OCTNET_CMD_DELETE_SA 0xF
223 #define OCTNET_CMD_UPDATE_SA 0x12
225 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
226 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
227 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
228 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
229 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
231 #define OCTNET_CMD_ENABLE_VLAN_FILTER 0x16
232 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
233 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
234 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
236 #define OCTNET_CMD_ID_ACTIVE 0x1a
238 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
239 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
240 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
241 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
242 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
243 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
245 /* RX(packets coming from wire) Checksum verification flags */
247 #define CNNIC_L4SUM_VERIFIED 0x1
248 #define CNNIC_IPSUM_VERIFIED 0x2
249 #define CNNIC_TUN_CSUM_VERIFIED 0x4
250 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
252 /*LROIPV4 and LROIPV6 Flags*/
253 #define OCTNIC_LROIPV4 0x1
254 #define OCTNIC_LROIPV6 0x2
256 /* Interface flags communicated between host driver and core app. */
257 enum octnet_ifflags {
258 OCTNET_IFFLAG_PROMISC = 0x01,
259 OCTNET_IFFLAG_ALLMULTI = 0x02,
260 OCTNET_IFFLAG_MULTICAST = 0x04,
261 OCTNET_IFFLAG_BROADCAST = 0x08,
262 OCTNET_IFFLAG_UNICAST = 0x10
286 #ifdef __BIG_ENDIAN_BITFIELD
289 u64 more:6; /* How many udd words follow the command */
314 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
316 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
317 #define LIO_SOFTCMDRESP_IH2 40
318 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
320 #define LIO_PCICMD_O2 24
321 #define LIO_PCICMD_O3 (24 + 8)
323 /* Instruction Header(DPI) - for OCTEON-III models */
324 struct octeon_instr_ih3 {
325 #ifdef __BIG_ENDIAN_BITFIELD
330 /** Gather indicator 1=gather*/
333 /** Data length OR no. of entries in gather list */
336 /** Front Data size */
342 /** PKI port kind - PKIND */
352 /** PKI port kind - PKIND */
358 /** Front Data size */
361 /** Data length OR no. of entries in gather list */
364 /** Gather indicator 1=gather*/
373 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
374 /** BIG ENDIAN format. */
375 struct octeon_instr_pki_ih3 {
376 #ifdef __BIG_ENDIAN_BITFIELD
381 /** Raw mode indicator 1 = RAW */
446 /** Raw mode indicator 1 = RAW */
455 /** Instruction Header */
456 struct octeon_instr_ih2 {
457 #ifdef __BIG_ENDIAN_BITFIELD
458 /** Raw mode indicator 1 = RAW */
461 /** Gather indicator 1=gather*/
464 /** Data length OR no. of entries in gather list */
467 /** Front Data size */
470 /** Packet Order / Work Unit selection (1 of 8)*/
473 /** Core group selection (1 of 16) */
476 /** Short Raw Packet Indicator 1=short raw pkt */
491 /** Short Raw Packet Indicator 1=short raw pkt */
494 /** Core group selection (1 of 16) */
497 /** Packet Order / Work Unit selection (1 of 8)*/
500 /** Front Data size */
503 /** Data length OR no. of entries in gather list */
506 /** Gather indicator 1=gather*/
509 /** Raw mode indicator 1 = RAW */
514 /** Input Request Header */
515 struct octeon_instr_irh {
516 #ifdef __BIG_ENDIAN_BITFIELD
523 u64 ossp:32; /* opcode/subcode specific parameters */
525 u64 ossp:32; /* opcode/subcode specific parameters */
535 /** Return Data Parameters */
536 struct octeon_instr_rdp {
537 #ifdef __BIG_ENDIAN_BITFIELD
548 /** Receive Header */
550 #ifdef __BIG_ENDIAN_BITFIELD
555 u64 len:3; /** additional 64-bit words */
557 u64 ossp:32; /** opcode/subcode specific parameters */
562 u64 len:3; /** additional 64-bit words */
566 u64 csum_verified:3; /** checksum verified. */
567 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
569 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
574 u64 len:3; /** additional 64-bit words */
577 u64 max_nic_ports:10;
585 u64 len:3; /** additional 64-bit words */
593 u64 ossp:32; /** opcode/subcode specific parameters */
595 u64 len:3; /** additional 64-bit words */
600 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
602 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
603 u64 csum_verified:3; /** checksum verified. */
607 u64 len:3; /** additional 64-bit words */
615 u64 max_nic_ports:10;
618 u64 len:3; /** additional 64-bit words */
626 u64 len:3; /** additional 64-bit words */
633 #define OCT_RH_SIZE (sizeof(union octeon_rh))
635 union octnic_packet_params {
638 #ifdef __BIG_ENDIAN_BITFIELD
640 u32 ip_csum:1; /* Perform IP header checksum(s) */
641 /* Perform Outer transport header checksum */
642 u32 transport_csum:1;
643 /* Find tunnel, and perform transport csum. */
645 u32 tsflag:1; /* Timestamp this packet */
646 u32 ipsec_ops:4; /* IPsec operation */
651 u32 transport_csum:1;
658 /** Status of a RGMII Link on Octeon as seen by core driver. */
659 union oct_link_status {
663 #ifdef __BIG_ENDIAN_BITFIELD
687 /** The txpciq info passed to host from the firmware */
693 #ifdef __BIG_ENDIAN_BITFIELD
711 /** The rxpciq info passed to host from the firmware */
717 #ifdef __BIG_ENDIAN_BITFIELD
727 /** Information for a OCTEON ethernet interface shared between core & host. */
728 struct oct_link_info {
729 union oct_link_status link;
732 #ifdef __BIG_ENDIAN_BITFIELD
744 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
745 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
748 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
750 struct liquidio_if_cfg_info {
751 u64 iqmask; /** mask for IQs enabled for the port */
752 u64 oqmask; /** mask for OQs enabled for the port */
753 struct oct_link_info linfo; /** initial link information */
754 char liquidio_firmware_version[32];
757 /** Stats for each NIC port in RX direction. */
758 struct nic_rx_stats {
759 /* link-level stats */
766 u64 fifo_err; /* Accounts for over/under-run of buffers */
783 u64 fw_lro_pkts; /* Number of packets that are LROed */
784 u64 fw_lro_octs; /* Number of octets that are LROed */
785 u64 fw_total_lro; /* Number of LRO packets formed */
786 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
787 u64 fw_lro_aborts_port;
788 u64 fw_lro_aborts_seq;
789 u64 fw_lro_aborts_tsval;
790 u64 fw_lro_aborts_timer;
791 /* intrmod: packet forward rate */
795 /** Stats for each NIC port in RX direction. */
796 struct nic_tx_stats {
797 /* link-level stats */
799 u64 total_bytes_sent;
803 u64 one_collision_sent; /* Packets sent after one collision*/
804 u64 multi_collision_sent; /* Packets sent after multiple collision*/
805 u64 max_collision_fail; /* Packets not sent due to max collisions */
806 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
807 u64 fifo_err; /* Accounts for over/under-run of buffers */
809 u64 total_collisions; /* Total number of collisions detected */
814 u64 fw_total_fwd_bytes;
819 u64 fw_tso; /* number of tso requests */
820 u64 fw_tso_fwd; /* number of packets segmented in tso */
824 struct oct_link_stats {
825 struct nic_rx_stats fromwire;
826 struct nic_tx_stats fromhost;
830 #define LIO68XX_LED_CTRL_ADDR 0x3501
831 #define LIO68XX_LED_CTRL_CFGON 0x1f
832 #define LIO68XX_LED_CTRL_CFGOFF 0x100
833 #define LIO68XX_LED_BEACON_ADDR 0x3508
834 #define LIO68XX_LED_BEACON_CFGON 0x47fd
835 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
836 #define VITESSE_PHY_GPIO_DRIVEON 0x1
837 #define VITESSE_PHY_GPIO_CFG 0x8
838 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
839 #define VITESSE_PHY_GPIO_HIGH 0x2
840 #define VITESSE_PHY_GPIO_LOW 0x3
841 #define LED_IDENTIFICATION_ON 0x1
842 #define LED_IDENTIFICATION_OFF 0x0
844 struct oct_mdio_cmd {
852 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
854 /* intrmod: max. packet rate threshold */
855 #define LIO_INTRMOD_MAXPKT_RATETHR 196608
856 /* intrmod: min. packet rate threshold */
857 #define LIO_INTRMOD_MINPKT_RATETHR 9216
858 /* intrmod: max. packets to trigger interrupt */
859 #define LIO_INTRMOD_RXMAXCNT_TRIGGER 384
860 /* intrmod: min. packets to trigger interrupt */
861 #define LIO_INTRMOD_RXMINCNT_TRIGGER 0
862 /* intrmod: max. time to trigger interrupt */
863 #define LIO_INTRMOD_RXMAXTMR_TRIGGER 128
864 /* 66xx:intrmod: min. time to trigger interrupt
865 * (value of 1 is optimum for TCP_RR)
867 #define LIO_INTRMOD_RXMINTMR_TRIGGER 1
869 /* intrmod: max. packets to trigger interrupt */
870 #define LIO_INTRMOD_TXMAXCNT_TRIGGER 64
871 /* intrmod: min. packets to trigger interrupt */
872 #define LIO_INTRMOD_TXMINCNT_TRIGGER 0
874 /* intrmod: poll interval in seconds */
875 #define LIO_INTRMOD_CHECK_INTERVAL 1
877 struct oct_intrmod_cfg {
883 u64 rx_maxcnt_trigger;
884 u64 rx_mincnt_trigger;
885 u64 rx_maxtmr_trigger;
886 u64 rx_mintmr_trigger;
887 u64 tx_mincnt_trigger;
888 u64 tx_maxcnt_trigger;
894 #define BASE_QUEUE_NOT_REQUESTED 65535
896 union oct_nic_if_cfg {
899 #ifdef __BIG_ENDIAN_BITFIELD