2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
18 #include "thunder_bgx.h"
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
27 u8 num_vf_en; /* No of VF enabled */
28 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
29 void __iomem *reg_base; /* Register start address */
30 u8 num_sqs_en; /* Secondary qsets enabled */
31 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
32 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
33 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
34 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
35 struct pkind_cfg pkind;
36 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
37 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
38 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
39 u8 vf_lmac_map[MAX_LMAC];
41 struct delayed_work dwork;
42 struct workqueue_struct *check_link;
46 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
47 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
49 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
54 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
55 bool irq_allocated[NIC_PF_MSIX_VECTORS];
58 static inline bool pass1_silicon(struct nicpf *nic)
60 return nic->pdev->revision < 8;
63 /* Supported devices */
64 static const struct pci_device_id nic_id_table[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
66 { 0, } /* end of table */
69 MODULE_AUTHOR("Sunil Goutham");
70 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
71 MODULE_LICENSE("GPL v2");
72 MODULE_VERSION(DRV_VERSION);
73 MODULE_DEVICE_TABLE(pci, nic_id_table);
75 /* The Cavium ThunderX network controller can *only* be found in SoCs
76 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
77 * registers on this platform are implicitly strongly ordered with respect
78 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
79 * with no memory barriers in this driver. The readq()/writeq() functions add
80 * explicit ordering operation which in this case are redundant, and only
84 /* Register read/write APIs */
85 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
87 writeq_relaxed(val, nic->reg_base + offset);
90 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
92 return readq_relaxed(nic->reg_base + offset);
95 /* PF -> VF mailbox communication APIs */
96 static void nic_enable_mbx_intr(struct nicpf *nic)
98 /* Enable mailbox interrupt for all 128 VFs */
99 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
100 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
103 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
105 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
108 static u64 nic_get_mbx_addr(int vf)
110 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
113 /* Send a mailbox message to VF
114 * @vf: vf to which this message to be sent
115 * @mbx: Message to be sent
117 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
119 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
120 u64 *msg = (u64 *)mbx;
122 /* In first revision HW, mbox interrupt is triggerred
123 * when PF writes to MBOX(1), in next revisions when
124 * PF writes to MBOX(0)
126 if (pass1_silicon(nic)) {
127 /* see the comment for nic_reg_write()/nic_reg_read()
130 writeq_relaxed(msg[0], mbx_addr);
131 writeq_relaxed(msg[1], mbx_addr + 8);
133 writeq_relaxed(msg[1], mbx_addr + 8);
134 writeq_relaxed(msg[0], mbx_addr);
138 /* Responds to VF's READY message with VF's
139 * ID, node, MAC address e.t.c
140 * @vf: VF which sent READY message
142 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
144 union nic_mbx mbx = {};
148 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
149 mbx.nic_cfg.vf_id = vf;
151 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
154 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
155 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
157 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
159 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
161 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
162 mbx.nic_cfg.node_id = nic->node;
164 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
166 nic_send_msg_to_vf(nic, vf, &mbx);
169 /* ACKs VF's mailbox message
170 * @vf: VF to which ACK to be sent
172 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
174 union nic_mbx mbx = {};
176 mbx.msg.msg = NIC_MBOX_MSG_ACK;
177 nic_send_msg_to_vf(nic, vf, &mbx);
180 /* NACKs VF's mailbox message that PF is not able to
181 * complete the action
182 * @vf: VF to which ACK to be sent
184 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
186 union nic_mbx mbx = {};
188 mbx.msg.msg = NIC_MBOX_MSG_NACK;
189 nic_send_msg_to_vf(nic, vf, &mbx);
192 /* Flush all in flight receive packets to memory and
193 * bring down an active RQ
195 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
199 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
200 /* Wait till sync cycle is finished */
202 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
206 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
208 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
214 /* Get BGX Rx/Tx stats and respond to VF's request */
215 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
218 union nic_mbx mbx = {};
220 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
221 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
223 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
224 mbx.bgx_stats.vf_id = bgx->vf_id;
225 mbx.bgx_stats.rx = bgx->rx;
226 mbx.bgx_stats.idx = bgx->idx;
228 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
231 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
233 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
236 /* Update hardware min/max frame size */
237 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
239 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
240 dev_err(&nic->pdev->dev,
241 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
242 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
246 if (new_frs <= nic->pkind.maxlen)
249 nic->pkind.maxlen = new_frs;
250 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
254 /* Set minimum transmit packet size */
255 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
260 /* Max value that can be set is 60 */
264 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
265 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
266 lmac_cfg &= ~(0xF << 2);
267 lmac_cfg |= ((size / 4) << 2);
268 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
272 /* Function to check number of LMACs present and set VF::LMAC mapping.
273 * Mapping will be used while initializing channels.
275 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
277 unsigned bgx_map = bgx_get_map(nic->node);
278 int bgx, next_bgx_lmac = 0;
279 int lmac, lmac_cnt = 0;
285 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
286 if (!(bgx_map & (1 << bgx)))
288 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
289 for (lmac = 0; lmac < lmac_cnt; lmac++)
290 nic->vf_lmac_map[next_bgx_lmac++] =
291 NIC_SET_VF_LMAC_MAP(bgx, lmac);
292 nic->num_vf_en += lmac_cnt;
293 nic->lmac_cnt += lmac_cnt;
295 /* Program LMAC credits */
296 lmac_credit = (1ull << 1); /* channel credit enable */
297 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
298 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
299 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
300 NIC_HW_MAX_FRS) / 16) << 12);
301 lmac = bgx * MAX_LMAC_PER_BGX;
302 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
304 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
312 static void nic_init_hw(struct nicpf *nic)
316 /* Enable NIC HW block */
317 nic_reg_write(nic, NIC_PF_CFG, 0x3);
319 /* Enable backpressure */
320 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
322 /* Disable TNS mode on both interfaces */
323 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
324 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
325 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
326 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
327 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
328 (1ULL << 63) | BGX0_BLOCK);
329 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
330 (1ULL << 63) | BGX1_BLOCK);
332 /* PKIND configuration */
333 nic->pkind.minlen = 0;
334 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
335 nic->pkind.lenerr_en = 1;
336 nic->pkind.rx_hdr = 0;
337 nic->pkind.hdr_sl = 0;
339 for (i = 0; i < NIC_MAX_PKIND; i++)
340 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
341 *(u64 *)&nic->pkind);
343 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
346 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
348 /* Enable VLAN ethertype matching and stripping */
349 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
350 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
353 /* Channel parse index configuration */
354 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
356 u32 vnic, bgx, lmac, chan;
357 u32 padd, cpi_count = 0;
358 u64 cpi_base, cpi, rssi_base, rssi;
362 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
363 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
365 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
366 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
367 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
369 /* Rx channel configuration */
370 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
371 (1ull << 63) | (vnic << 0));
372 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
373 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
375 if (cfg->cpi_alg == CPI_ALG_NONE)
377 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
379 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
381 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
382 cpi_count = NIC_MAX_CPI_PER_LMAC;
384 /* RSS Qset, Qidx mapping */
387 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
388 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
389 (qset << 3) | rq_idx);
395 for (; cpi < (cpi_base + cpi_count); cpi++) {
396 /* Determine port to channel adder */
397 if (cfg->cpi_alg != CPI_ALG_DIFF)
398 padd = cpi % cpi_count;
400 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
402 /* Leave RSS_SIZE as '0' to disable RSS */
403 if (pass1_silicon(nic)) {
404 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
405 (vnic << 24) | (padd << 16) |
408 /* Set MPI_ALG to '0' to disable MCAM parsing */
409 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
411 /* MPI index is same as CPI if MPI_ALG is not enabled */
412 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
413 (vnic << 24) | (rssi_base + rssi));
416 if ((rssi + 1) >= cfg->rq_cnt)
419 if (cfg->cpi_alg == CPI_ALG_VLAN)
421 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
422 rssi = ((cpi - cpi_base) & 0xe) >> 1;
423 else if (cfg->cpi_alg == CPI_ALG_DIFF)
424 rssi = ((cpi - cpi_base) & 0x38) >> 3;
426 nic->cpi_base[cfg->vf_id] = cpi_base;
427 nic->rssi_base[cfg->vf_id] = rssi_base;
430 /* Responsds to VF with its RSS indirection table size */
431 static void nic_send_rss_size(struct nicpf *nic, int vf)
433 union nic_mbx mbx = {};
438 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
439 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
440 nic_send_msg_to_vf(nic, vf, &mbx);
443 /* Receive side scaling configuration
446 * - indir table i.e hash::RQ mapping
447 * - no of hash bits to consider
449 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
452 u64 cpi_cfg, cpi_base, rssi_base, rssi;
455 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
460 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
461 u8 svf = cfg->ind_tbl[idx] >> 3;
464 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
467 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
468 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
472 cpi_base = nic->cpi_base[cfg->vf_id];
473 if (pass1_silicon(nic))
474 idx_addr = NIC_PF_CPI_0_2047_CFG;
476 idx_addr = NIC_PF_MPI_0_2047_CFG;
477 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
478 cpi_cfg &= ~(0xFULL << 20);
479 cpi_cfg |= (cfg->hash_bits << 20);
480 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
483 /* 4 level transmit side scheduler configutation
484 * for TNS bypass mode
486 * Sample configuration for SQ0
487 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
488 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
489 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
490 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
491 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
492 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
493 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
494 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
496 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
497 struct sq_cfg_msg *sq)
502 u8 sq_idx = sq->sq_num;
506 pqs_vnic = nic->pqs_vf[vnic];
510 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
511 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
513 /* 24 bytes for FCS, IPG and preamble */
514 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
516 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
521 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
522 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
523 ((u64)vnic << NIC_QS_ID_SHIFT) |
524 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
525 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
526 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
528 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
529 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
530 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
531 /* Enable backpressure on the channel */
532 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
535 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
536 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
537 /* No priorities as of now */
538 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
541 /* Send primary nicvf pointer to secondary QS's VF */
542 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
544 union nic_mbx mbx = {};
546 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
547 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
548 nic_send_msg_to_vf(nic, sqs, &mbx);
551 /* Send SQS's nicvf pointer to primary QS's VF */
552 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
554 union nic_mbx mbx = {};
555 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
557 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
558 mbx.nicvf.sqs_id = nicvf->sqs_id;
559 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
560 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
563 /* Find next available Qset that can be assigned as a
564 * secondary Qset to a VF.
566 static int nic_nxt_avail_sqs(struct nicpf *nic)
570 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
571 if (!nic->sqs_used[sqs])
572 nic->sqs_used[sqs] = true;
575 return sqs + nic->num_vf_en;
580 /* Allocate additional Qsets for requested VF */
581 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
583 union nic_mbx mbx = {};
584 int idx, alloc_qs = 0;
587 if (!nic->num_sqs_en)
590 for (idx = 0; idx < sqs->qs_count; idx++) {
591 sqs_id = nic_nxt_avail_sqs(nic);
594 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
595 nic->pqs_vf[sqs_id] = sqs->vf_id;
600 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
601 mbx.sqs_alloc.vf_id = sqs->vf_id;
602 mbx.sqs_alloc.qs_count = alloc_qs;
603 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
606 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
608 int bgx_idx, lmac_idx;
610 if (lbk->vf_id > MAX_LMAC)
613 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
614 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
616 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
621 /* Interrupt handler to handle mailbox messages from VFs */
622 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
624 union nic_mbx mbx = {};
633 nic->mbx_lock[vf] = true;
635 mbx_addr = nic_get_mbx_addr(vf);
636 mbx_data = (u64 *)&mbx;
638 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
639 *mbx_data = nic_reg_read(nic, mbx_addr);
641 mbx_addr += sizeof(u64);
644 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
645 __func__, mbx.msg.msg, vf);
646 switch (mbx.msg.msg) {
647 case NIC_MBOX_MSG_READY:
648 nic_mbx_send_ready(nic, vf);
656 case NIC_MBOX_MSG_QS_CFG:
657 reg_addr = NIC_PF_QSET_0_127_CFG |
658 (mbx.qs.num << NIC_QS_ID_SHIFT);
660 /* Check if its a secondary Qset */
661 if (vf >= nic->num_vf_en) {
662 cfg = cfg & (~0x7FULL);
663 /* Assign this Qset to primary Qset's VF */
664 cfg |= nic->pqs_vf[vf];
666 nic_reg_write(nic, reg_addr, cfg);
668 case NIC_MBOX_MSG_RQ_CFG:
669 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
670 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
671 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
672 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
674 case NIC_MBOX_MSG_RQ_BP_CFG:
675 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
676 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
677 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
678 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
680 case NIC_MBOX_MSG_RQ_SW_SYNC:
681 ret = nic_rcv_queue_sw_sync(nic);
683 case NIC_MBOX_MSG_RQ_DROP_CFG:
684 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
685 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
686 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
687 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
689 case NIC_MBOX_MSG_SQ_CFG:
690 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
691 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
692 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
693 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
694 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
696 case NIC_MBOX_MSG_SET_MAC:
697 if (vf >= nic->num_vf_en)
699 lmac = mbx.mac.vf_id;
700 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
701 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
702 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
704 case NIC_MBOX_MSG_SET_MAX_FRS:
705 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
708 case NIC_MBOX_MSG_CPI_CFG:
709 nic_config_cpi(nic, &mbx.cpi_cfg);
711 case NIC_MBOX_MSG_RSS_SIZE:
712 nic_send_rss_size(nic, vf);
714 case NIC_MBOX_MSG_RSS_CFG:
715 case NIC_MBOX_MSG_RSS_CFG_CONT:
716 nic_config_rss(nic, &mbx.rss_cfg);
718 case NIC_MBOX_MSG_CFG_DONE:
719 /* Last message of VF config msg sequence */
720 nic->vf_enabled[vf] = true;
721 if (vf >= nic->lmac_cnt)
724 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
725 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
727 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, true);
729 case NIC_MBOX_MSG_SHUTDOWN:
730 /* First msg in VF teardown sequence */
731 nic->vf_enabled[vf] = false;
732 if (vf >= nic->num_vf_en)
733 nic->sqs_used[vf - nic->num_vf_en] = false;
736 if (vf >= nic->lmac_cnt)
739 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
740 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
742 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, false);
744 case NIC_MBOX_MSG_ALLOC_SQS:
745 nic_alloc_sqs(nic, &mbx.sqs_alloc);
747 case NIC_MBOX_MSG_NICVF_PTR:
748 nic->nicvf[vf] = mbx.nicvf.nicvf;
750 case NIC_MBOX_MSG_PNICVF_PTR:
751 nic_send_pnicvf(nic, vf);
753 case NIC_MBOX_MSG_SNICVF_PTR:
754 nic_send_snicvf(nic, &mbx.nicvf);
756 case NIC_MBOX_MSG_BGX_STATS:
757 nic_get_bgx_stats(nic, &mbx.bgx_stats);
759 case NIC_MBOX_MSG_LOOPBACK:
760 ret = nic_config_loopback(nic, &mbx.lbk);
763 dev_err(&nic->pdev->dev,
764 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
769 nic_mbx_send_ack(nic, vf);
770 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
771 nic_mbx_send_nack(nic, vf);
773 nic->mbx_lock[vf] = false;
776 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
779 u8 vf, vf_per_mbx_reg = 64;
781 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
782 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
783 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
784 if (intr & (1ULL << vf)) {
785 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
786 vf + (mbx * vf_per_mbx_reg));
788 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
789 nic_clear_mbx_intr(nic, vf, mbx);
794 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
796 struct nicpf *nic = (struct nicpf *)nic_irq;
798 nic_mbx_intr_handler(nic, 0);
803 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
805 struct nicpf *nic = (struct nicpf *)nic_irq;
807 nic_mbx_intr_handler(nic, 1);
812 static int nic_enable_msix(struct nicpf *nic)
816 nic->num_vec = NIC_PF_MSIX_VECTORS;
818 for (i = 0; i < nic->num_vec; i++)
819 nic->msix_entries[i].entry = i;
821 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
823 dev_err(&nic->pdev->dev,
824 "Request for #%d msix vectors failed\n",
829 nic->msix_enabled = 1;
833 static void nic_disable_msix(struct nicpf *nic)
835 if (nic->msix_enabled) {
836 pci_disable_msix(nic->pdev);
837 nic->msix_enabled = 0;
842 static void nic_free_all_interrupts(struct nicpf *nic)
846 for (irq = 0; irq < nic->num_vec; irq++) {
847 if (nic->irq_allocated[irq])
848 free_irq(nic->msix_entries[irq].vector, nic);
849 nic->irq_allocated[irq] = false;
853 static int nic_register_interrupts(struct nicpf *nic)
858 ret = nic_enable_msix(nic);
862 /* Register mailbox interrupt handlers */
863 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
864 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
868 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
870 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
871 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
875 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
877 /* Enable mailbox interrupt */
878 nic_enable_mbx_intr(nic);
882 dev_err(&nic->pdev->dev, "Request irq failed\n");
883 nic_free_all_interrupts(nic);
887 static void nic_unregister_interrupts(struct nicpf *nic)
889 nic_free_all_interrupts(nic);
890 nic_disable_msix(nic);
893 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
895 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
898 /* Check if its a multi-node environment */
900 sqs_per_vf = MAX_SQS_PER_VF;
902 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
903 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
904 return min(total_vf - vf_en, vf_en * sqs_per_vf);
907 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
914 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
916 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
920 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
921 if (total_vf_cnt < nic->num_vf_en)
922 nic->num_vf_en = total_vf_cnt;
927 vf_en = nic->num_vf_en;
928 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
929 vf_en += nic->num_sqs_en;
931 err = pci_enable_sriov(pdev, vf_en);
933 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
939 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
942 nic->flags |= NIC_SRIOV_ENABLED;
946 /* Poll for BGX LMAC link status and update corresponding VF
947 * if there is a change, valid only if internal L2 switch
948 * is not present otherwise VF link is always treated as up
950 static void nic_poll_for_link(struct work_struct *work)
952 union nic_mbx mbx = {};
954 struct bgx_link_status link;
957 nic = container_of(work, struct nicpf, dwork.work);
959 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
961 for (vf = 0; vf < nic->lmac_cnt; vf++) {
962 /* Poll only if VF is UP */
963 if (!nic->vf_enabled[vf])
966 /* Get BGX, LMAC indices for the VF */
967 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
968 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
969 /* Get interface link status */
970 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
972 /* Inform VF only if link status changed */
973 if (nic->link[vf] == link.link_up)
976 if (!nic->mbx_lock[vf]) {
977 nic->link[vf] = link.link_up;
978 nic->duplex[vf] = link.duplex;
979 nic->speed[vf] = link.speed;
981 /* Send a mbox message to VF with current link status */
982 mbx.link_status.link_up = link.link_up;
983 mbx.link_status.duplex = link.duplex;
984 mbx.link_status.speed = link.speed;
985 nic_send_msg_to_vf(nic, vf, &mbx);
988 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
991 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
993 struct device *dev = &pdev->dev;
997 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
999 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
1003 pci_set_drvdata(pdev, nic);
1007 err = pci_enable_device(pdev);
1009 dev_err(dev, "Failed to enable PCI device\n");
1010 pci_set_drvdata(pdev, NULL);
1014 err = pci_request_regions(pdev, DRV_NAME);
1016 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1017 goto err_disable_device;
1020 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1022 dev_err(dev, "Unable to get usable DMA configuration\n");
1023 goto err_release_regions;
1026 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1028 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1029 goto err_release_regions;
1032 /* MAP PF's configuration registers */
1033 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1034 if (!nic->reg_base) {
1035 dev_err(dev, "Cannot map config register space, aborting\n");
1037 goto err_release_regions;
1040 nic->node = nic_get_node_id(pdev);
1042 nic_set_lmac_vf_mapping(nic);
1044 /* Initialize hardware */
1047 /* Set RSS TBL size for each VF */
1048 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
1050 /* Register interrupts */
1051 err = nic_register_interrupts(nic);
1053 goto err_release_regions;
1055 /* Configure SRIOV */
1056 err = nic_sriov_init(pdev, nic);
1058 goto err_unregister_interrupts;
1060 /* Register a physical link status poll fn() */
1061 nic->check_link = alloc_workqueue("check_link_status",
1062 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1063 if (!nic->check_link) {
1065 goto err_disable_sriov;
1068 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1069 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1074 if (nic->flags & NIC_SRIOV_ENABLED)
1075 pci_disable_sriov(pdev);
1076 err_unregister_interrupts:
1077 nic_unregister_interrupts(nic);
1078 err_release_regions:
1079 pci_release_regions(pdev);
1081 pci_disable_device(pdev);
1082 pci_set_drvdata(pdev, NULL);
1086 static void nic_remove(struct pci_dev *pdev)
1088 struct nicpf *nic = pci_get_drvdata(pdev);
1090 if (nic->flags & NIC_SRIOV_ENABLED)
1091 pci_disable_sriov(pdev);
1093 if (nic->check_link) {
1094 /* Destroy work Queue */
1095 cancel_delayed_work_sync(&nic->dwork);
1096 destroy_workqueue(nic->check_link);
1099 nic_unregister_interrupts(nic);
1100 pci_release_regions(pdev);
1101 pci_disable_device(pdev);
1102 pci_set_drvdata(pdev, NULL);
1105 static struct pci_driver nic_driver = {
1107 .id_table = nic_id_table,
1109 .remove = nic_remove,
1112 static int __init nic_init_module(void)
1114 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1116 return pci_register_driver(&nic_driver);
1119 static void __exit nic_cleanup_module(void)
1121 pci_unregister_driver(&nic_driver);
1124 module_init(nic_init_module);
1125 module_exit(nic_cleanup_module);