2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
12 #define NIC_PF_REG_COUNT 29573
13 #define NIC_VF_REG_COUNT 249
15 /* Physical function register offsets */
16 #define NIC_PF_CFG (0x0000)
17 #define NIC_PF_STATUS (0x0010)
18 #define NIC_PF_INTR_TIMER_CFG (0x0030)
19 #define NIC_PF_BIST_STATUS (0x0040)
20 #define NIC_PF_SOFT_RESET (0x0050)
21 #define NIC_PF_TCP_TIMER (0x0060)
22 #define NIC_PF_BP_CFG (0x0080)
23 #define NIC_PF_RRM_CFG (0x0088)
24 #define NIC_PF_CQM_CF (0x00A0)
25 #define NIC_PF_CNM_CF (0x00A8)
26 #define NIC_PF_CNM_STATUS (0x00B0)
27 #define NIC_PF_CQ_AVG_CFG (0x00C0)
28 #define NIC_PF_RRM_AVG_CFG (0x00C8)
29 #define NIC_PF_INTF_0_1_SEND_CFG (0x0200)
30 #define NIC_PF_INTF_0_1_BP_CFG (0x0208)
31 #define NIC_PF_INTF_0_1_BP_DIS_0_1 (0x0210)
32 #define NIC_PF_INTF_0_1_BP_SW_0_1 (0x0220)
33 #define NIC_PF_RBDR_BP_STATE_0_3 (0x0240)
34 #define NIC_PF_MAILBOX_INT (0x0410)
35 #define NIC_PF_MAILBOX_INT_W1S (0x0430)
36 #define NIC_PF_MAILBOX_ENA_W1C (0x0450)
37 #define NIC_PF_MAILBOX_ENA_W1S (0x0470)
38 #define NIC_PF_RX_ETYPE_0_7 (0x0500)
39 #define NIC_PF_PKIND_0_15_CFG (0x0600)
40 #define NIC_PF_ECC0_FLIP0 (0x1000)
41 #define NIC_PF_ECC1_FLIP0 (0x1008)
42 #define NIC_PF_ECC2_FLIP0 (0x1010)
43 #define NIC_PF_ECC3_FLIP0 (0x1018)
44 #define NIC_PF_ECC0_FLIP1 (0x1080)
45 #define NIC_PF_ECC1_FLIP1 (0x1088)
46 #define NIC_PF_ECC2_FLIP1 (0x1090)
47 #define NIC_PF_ECC3_FLIP1 (0x1098)
48 #define NIC_PF_ECC0_CDIS (0x1100)
49 #define NIC_PF_ECC1_CDIS (0x1108)
50 #define NIC_PF_ECC2_CDIS (0x1110)
51 #define NIC_PF_ECC3_CDIS (0x1118)
52 #define NIC_PF_BIST0_STATUS (0x1280)
53 #define NIC_PF_BIST1_STATUS (0x1288)
54 #define NIC_PF_BIST2_STATUS (0x1290)
55 #define NIC_PF_BIST3_STATUS (0x1298)
56 #define NIC_PF_ECC0_SBE_INT (0x2000)
57 #define NIC_PF_ECC0_SBE_INT_W1S (0x2008)
58 #define NIC_PF_ECC0_SBE_ENA_W1C (0x2010)
59 #define NIC_PF_ECC0_SBE_ENA_W1S (0x2018)
60 #define NIC_PF_ECC0_DBE_INT (0x2100)
61 #define NIC_PF_ECC0_DBE_INT_W1S (0x2108)
62 #define NIC_PF_ECC0_DBE_ENA_W1C (0x2110)
63 #define NIC_PF_ECC0_DBE_ENA_W1S (0x2118)
64 #define NIC_PF_ECC1_SBE_INT (0x2200)
65 #define NIC_PF_ECC1_SBE_INT_W1S (0x2208)
66 #define NIC_PF_ECC1_SBE_ENA_W1C (0x2210)
67 #define NIC_PF_ECC1_SBE_ENA_W1S (0x2218)
68 #define NIC_PF_ECC1_DBE_INT (0x2300)
69 #define NIC_PF_ECC1_DBE_INT_W1S (0x2308)
70 #define NIC_PF_ECC1_DBE_ENA_W1C (0x2310)
71 #define NIC_PF_ECC1_DBE_ENA_W1S (0x2318)
72 #define NIC_PF_ECC2_SBE_INT (0x2400)
73 #define NIC_PF_ECC2_SBE_INT_W1S (0x2408)
74 #define NIC_PF_ECC2_SBE_ENA_W1C (0x2410)
75 #define NIC_PF_ECC2_SBE_ENA_W1S (0x2418)
76 #define NIC_PF_ECC2_DBE_INT (0x2500)
77 #define NIC_PF_ECC2_DBE_INT_W1S (0x2508)
78 #define NIC_PF_ECC2_DBE_ENA_W1C (0x2510)
79 #define NIC_PF_ECC2_DBE_ENA_W1S (0x2518)
80 #define NIC_PF_ECC3_SBE_INT (0x2600)
81 #define NIC_PF_ECC3_SBE_INT_W1S (0x2608)
82 #define NIC_PF_ECC3_SBE_ENA_W1C (0x2610)
83 #define NIC_PF_ECC3_SBE_ENA_W1S (0x2618)
84 #define NIC_PF_ECC3_DBE_INT (0x2700)
85 #define NIC_PF_ECC3_DBE_INT_W1S (0x2708)
86 #define NIC_PF_ECC3_DBE_ENA_W1C (0x2710)
87 #define NIC_PF_ECC3_DBE_ENA_W1S (0x2718)
88 #define NIC_PF_CPI_0_2047_CFG (0x200000)
89 #define NIC_PF_RSSI_0_4097_RQ (0x220000)
90 #define NIC_PF_LMAC_0_7_CFG (0x240000)
91 #define NIC_PF_LMAC_0_7_SW_XOFF (0x242000)
92 #define NIC_PF_LMAC_0_7_CREDIT (0x244000)
93 #define NIC_PF_CHAN_0_255_TX_CFG (0x400000)
94 #define NIC_PF_CHAN_0_255_RX_CFG (0x420000)
95 #define NIC_PF_CHAN_0_255_SW_XOFF (0x440000)
96 #define NIC_PF_CHAN_0_255_CREDIT (0x460000)
97 #define NIC_PF_CHAN_0_255_RX_BP_CFG (0x480000)
98 #define NIC_PF_SW_SYNC_RX (0x490000)
99 #define NIC_PF_SW_SYNC_RX_DONE (0x490008)
100 #define NIC_PF_TL2_0_63_CFG (0x500000)
101 #define NIC_PF_TL2_0_63_PRI (0x520000)
102 #define NIC_PF_TL2_0_63_SH_STATUS (0x580000)
103 #define NIC_PF_TL3A_0_63_CFG (0x5F0000)
104 #define NIC_PF_TL3_0_255_CFG (0x600000)
105 #define NIC_PF_TL3_0_255_CHAN (0x620000)
106 #define NIC_PF_TL3_0_255_PIR (0x640000)
107 #define NIC_PF_TL3_0_255_SW_XOFF (0x660000)
108 #define NIC_PF_TL3_0_255_CNM_RATE (0x680000)
109 #define NIC_PF_TL3_0_255_SH_STATUS (0x6A0000)
110 #define NIC_PF_TL4A_0_255_CFG (0x6F0000)
111 #define NIC_PF_TL4_0_1023_CFG (0x800000)
112 #define NIC_PF_TL4_0_1023_SW_XOFF (0x820000)
113 #define NIC_PF_TL4_0_1023_SH_STATUS (0x840000)
114 #define NIC_PF_TL4A_0_1023_CNM_RATE (0x880000)
115 #define NIC_PF_TL4A_0_1023_CNM_STATUS (0x8A0000)
116 #define NIC_PF_VF_0_127_MAILBOX_0_1 (0x20002030)
117 #define NIC_PF_VNIC_0_127_TX_STAT_0_4 (0x20004000)
118 #define NIC_PF_VNIC_0_127_RX_STAT_0_13 (0x20004100)
119 #define NIC_PF_QSET_0_127_LOCK_0_15 (0x20006000)
120 #define NIC_PF_QSET_0_127_CFG (0x20010000)
121 #define NIC_PF_QSET_0_127_RQ_0_7_CFG (0x20010400)
122 #define NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420)
123 #define NIC_PF_QSET_0_127_RQ_0_7_BP_CFG (0x20010500)
124 #define NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600)
125 #define NIC_PF_QSET_0_127_SQ_0_7_CFG (0x20010C00)
126 #define NIC_PF_QSET_0_127_SQ_0_7_CFG2 (0x20010C08)
127 #define NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00)
129 #define NIC_PF_MSIX_VEC_0_18_ADDR (0x000000)
130 #define NIC_PF_MSIX_VEC_0_CTL (0x000008)
131 #define NIC_PF_MSIX_PBA_0 (0x0F0000)
133 /* Virtual function register offsets */
134 #define NIC_VNIC_CFG (0x000020)
135 #define NIC_VF_PF_MAILBOX_0_1 (0x000130)
136 #define NIC_VF_INT (0x000200)
137 #define NIC_VF_INT_W1S (0x000220)
138 #define NIC_VF_ENA_W1C (0x000240)
139 #define NIC_VF_ENA_W1S (0x000260)
141 #define NIC_VNIC_RSS_CFG (0x0020E0)
142 #define NIC_VNIC_RSS_KEY_0_4 (0x002200)
143 #define NIC_VNIC_TX_STAT_0_4 (0x004000)
144 #define NIC_VNIC_RX_STAT_0_13 (0x004100)
145 #define NIC_QSET_RQ_GEN_CFG (0x010010)
147 #define NIC_QSET_CQ_0_7_CFG (0x010400)
148 #define NIC_QSET_CQ_0_7_CFG2 (0x010408)
149 #define NIC_QSET_CQ_0_7_THRESH (0x010410)
150 #define NIC_QSET_CQ_0_7_BASE (0x010420)
151 #define NIC_QSET_CQ_0_7_HEAD (0x010428)
152 #define NIC_QSET_CQ_0_7_TAIL (0x010430)
153 #define NIC_QSET_CQ_0_7_DOOR (0x010438)
154 #define NIC_QSET_CQ_0_7_STATUS (0x010440)
155 #define NIC_QSET_CQ_0_7_STATUS2 (0x010448)
156 #define NIC_QSET_CQ_0_7_DEBUG (0x010450)
158 #define NIC_QSET_RQ_0_7_CFG (0x010600)
159 #define NIC_QSET_RQ_0_7_STAT_0_1 (0x010700)
161 #define NIC_QSET_SQ_0_7_CFG (0x010800)
162 #define NIC_QSET_SQ_0_7_THRESH (0x010810)
163 #define NIC_QSET_SQ_0_7_BASE (0x010820)
164 #define NIC_QSET_SQ_0_7_HEAD (0x010828)
165 #define NIC_QSET_SQ_0_7_TAIL (0x010830)
166 #define NIC_QSET_SQ_0_7_DOOR (0x010838)
167 #define NIC_QSET_SQ_0_7_STATUS (0x010840)
168 #define NIC_QSET_SQ_0_7_DEBUG (0x010848)
169 #define NIC_QSET_SQ_0_7_CNM_CHG (0x010860)
170 #define NIC_QSET_SQ_0_7_STAT_0_1 (0x010900)
172 #define NIC_QSET_RBDR_0_1_CFG (0x010C00)
173 #define NIC_QSET_RBDR_0_1_THRESH (0x010C10)
174 #define NIC_QSET_RBDR_0_1_BASE (0x010C20)
175 #define NIC_QSET_RBDR_0_1_HEAD (0x010C28)
176 #define NIC_QSET_RBDR_0_1_TAIL (0x010C30)
177 #define NIC_QSET_RBDR_0_1_DOOR (0x010C38)
178 #define NIC_QSET_RBDR_0_1_STATUS0 (0x010C40)
179 #define NIC_QSET_RBDR_0_1_STATUS1 (0x010C48)
180 #define NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50)
182 #define NIC_VF_MSIX_VECTOR_0_19_ADDR (0x000000)
183 #define NIC_VF_MSIX_VECTOR_0_19_CTL (0x000008)
184 #define NIC_VF_MSIX_PBA (0x0F0000)
186 /* Offsets within registers */
187 #define NIC_MSIX_VEC_SHIFT 4
188 #define NIC_Q_NUM_SHIFT 18
189 #define NIC_QS_ID_SHIFT 21
190 #define NIC_VF_NUM_SHIFT 21
192 /* Port kind configuration register */
194 #if defined(__BIG_ENDIAN_BITFIELD)
195 u64 reserved_42_63:22;
196 u64 hdr_sl:5; /* Header skip length */
197 u64 rx_hdr:3; /* TNS Receive header present */
198 u64 lenerr_en:1;/* L2 length error check enable */
199 u64 reserved_32_32:1;
200 u64 maxlen:16; /* Max frame size */
201 u64 minlen:16; /* Min frame size */
202 #elif defined(__LITTLE_ENDIAN_BITFIELD)
205 u64 reserved_32_32:1;
209 u64 reserved_42_63:22;
213 #endif /* NIC_REG_H */