2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
35 int lmacid; /* ID within BGX */
36 int lmacid_bd; /* ID on board */
37 struct net_device netdev;
38 struct phy_device *phydev;
39 unsigned int last_duplex;
40 unsigned int last_link;
41 unsigned int last_speed;
43 struct delayed_work dwork;
44 struct workqueue_struct *check_link;
49 struct lmac lmac[MAX_LMAC_PER_BGX];
51 void __iomem *reg_base;
56 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
57 static int lmac_count; /* Total no of LMACs in system */
59 static int bgx_xaui_check_link(struct lmac *lmac);
61 /* Supported devices */
62 static const struct pci_device_id bgx_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
64 { 0, } /* end of table */
67 MODULE_AUTHOR("Cavium Inc");
68 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
69 MODULE_LICENSE("GPL v2");
70 MODULE_VERSION(DRV_VERSION);
71 MODULE_DEVICE_TABLE(pci, bgx_id_table);
73 /* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
82 /* Register read/write APIs */
83 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
85 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
87 return readq_relaxed(addr);
90 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
92 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
94 writeq_relaxed(val, addr);
97 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
99 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
101 writeq_relaxed(val | readq_relaxed(addr), addr);
104 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
110 reg_val = bgx_reg_read(bgx, lmac, reg);
111 if (zero && !(reg_val & mask))
113 if (!zero && (reg_val & mask))
115 usleep_range(1000, 2000);
121 /* Return number of BGX present in HW */
122 unsigned bgx_get_map(int node)
127 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
128 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
134 EXPORT_SYMBOL(bgx_get_map);
136 /* Return number of LMAC configured for this BGX */
137 int bgx_get_lmac_count(int node, int bgx_idx)
141 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
143 return bgx->lmac_count;
147 EXPORT_SYMBOL(bgx_get_lmac_count);
149 /* Returns the current link status of LMAC */
150 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
152 struct bgx_link_status *link = (struct bgx_link_status *)status;
156 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
160 lmac = &bgx->lmac[lmacid];
161 link->link_up = lmac->link_up;
162 link->duplex = lmac->last_duplex;
163 link->speed = lmac->last_speed;
165 EXPORT_SYMBOL(bgx_get_lmac_link_state);
167 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
169 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
172 return bgx->lmac[lmacid].mac;
176 EXPORT_SYMBOL(bgx_get_lmac_mac);
178 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
180 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
185 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
187 EXPORT_SYMBOL(bgx_set_lmac_mac);
189 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
191 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
197 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
199 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
201 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
202 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
204 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
206 static void bgx_sgmii_change_link_state(struct lmac *lmac)
208 struct bgx *bgx = lmac->bgx;
213 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
215 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
217 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
218 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
221 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
222 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
223 port_cfg |= (lmac->last_duplex << 2);
225 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
228 switch (lmac->last_speed) {
230 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
231 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
232 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
233 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
234 misc_ctl |= 50; /* samp_pt */
235 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
236 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
239 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
240 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
241 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
242 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
243 misc_ctl |= 5; /* samp_pt */
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
248 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
249 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
250 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
251 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
252 misc_ctl |= 1; /* samp_pt */
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
254 if (lmac->last_duplex)
255 bgx_reg_write(bgx, lmac->lmacid,
256 BGX_GMP_GMI_TXX_BURST, 0);
258 bgx_reg_write(bgx, lmac->lmacid,
259 BGX_GMP_GMI_TXX_BURST, 8192);
264 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
265 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
267 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
271 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
274 static void bgx_lmac_handler(struct net_device *netdev)
276 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
277 struct phy_device *phydev;
278 int link_changed = 0;
283 phydev = lmac->phydev;
285 if (!phydev->link && lmac->last_link)
289 (lmac->last_duplex != phydev->duplex ||
290 lmac->last_link != phydev->link ||
291 lmac->last_speed != phydev->speed)) {
295 lmac->last_link = phydev->link;
296 lmac->last_speed = phydev->speed;
297 lmac->last_duplex = phydev->duplex;
302 if (link_changed > 0)
303 lmac->link_up = true;
305 lmac->link_up = false;
308 bgx_sgmii_change_link_state(lmac);
310 bgx_xaui_check_link(lmac);
313 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
317 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
323 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
325 EXPORT_SYMBOL(bgx_get_rx_stats);
327 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
331 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
335 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
337 EXPORT_SYMBOL(bgx_get_tx_stats);
339 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
343 while (bgx->lmac[lmac].dmac > 0) {
344 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
345 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
346 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
347 bgx->lmac[lmac].dmac--;
351 /* Configure BGX LMAC in internal loopback mode */
352 void bgx_lmac_internal_loopback(int node, int bgx_idx,
353 int lmac_idx, bool enable)
359 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
363 lmac = &bgx->lmac[lmac_idx];
364 if (lmac->is_sgmii) {
365 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
367 cfg |= PCS_MRX_CTL_LOOPBACK1;
369 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
370 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
372 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
374 cfg |= SPU_CTL_LOOPBACK;
376 cfg &= ~SPU_CTL_LOOPBACK;
377 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
380 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
382 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
384 int lmacid = lmac->lmacid;
387 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
388 /* max packet size */
389 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
391 /* Disable frame alignment if using preamble */
392 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
394 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
397 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
400 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
401 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
402 PCS_MRX_CTL_RESET, true)) {
403 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
407 /* power down, reset autoneg, autoneg enable */
408 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
409 cfg &= ~PCS_MRX_CTL_PWR_DN;
410 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
411 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
413 if (lmac->lmac_type == BGX_MODE_QSGMII) {
414 /* Disable disparity check for QSGMII */
415 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
416 cfg &= ~PCS_MISC_CTL_DISP_EN;
417 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
421 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
422 PCS_MRX_STATUS_AN_CPT, false)) {
423 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
430 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
433 int lmacid = lmac->lmacid;
436 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
437 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
438 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
443 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
445 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
447 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
448 /* Set interleaved running disparity for RXAUI */
449 if (lmac->lmac_type != BGX_MODE_RXAUI)
450 bgx_reg_modify(bgx, lmacid,
451 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
453 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
454 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
456 /* clear all interrupts */
457 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
458 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
459 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
460 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
461 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
462 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
464 if (lmac->use_training) {
465 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
466 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
467 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
468 /* training enable */
469 bgx_reg_modify(bgx, lmacid,
470 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
473 /* Append FCS to each packet */
474 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
476 /* Disable forward error correction */
477 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
478 cfg &= ~SPU_FEC_CTL_FEC_EN;
479 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
481 /* Disable autoneg */
482 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
483 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
484 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
486 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
487 if (lmac->lmac_type == BGX_MODE_10G_KR)
489 else if (lmac->lmac_type == BGX_MODE_40G_KR)
492 cfg &= ~((1 << 23) | (1 << 24));
493 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
494 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
496 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
497 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
498 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
501 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
503 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
504 cfg &= ~SPU_CTL_LOW_POWER;
505 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
507 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
508 cfg &= ~SMU_TX_CTL_UNI_EN;
509 cfg |= SMU_TX_CTL_DIC_EN;
510 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
512 /* take lmac_count into account */
513 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
514 /* max packet size */
515 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
520 static int bgx_xaui_check_link(struct lmac *lmac)
522 struct bgx *bgx = lmac->bgx;
523 int lmacid = lmac->lmacid;
524 int lmac_type = lmac->lmac_type;
527 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
528 if (lmac->use_training) {
529 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
530 if (!(cfg & (1ull << 13))) {
531 cfg = (1ull << 13) | (1ull << 14);
532 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
533 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
535 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
540 /* wait for PCS to come out of reset */
541 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
542 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
546 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
547 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
548 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
549 SPU_BR_STATUS_BLK_LOCK, false)) {
550 dev_err(&bgx->pdev->dev,
551 "SPU_BR_STATUS_BLK_LOCK not completed\n");
555 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
556 SPU_BX_STATUS_RX_ALIGN, false)) {
557 dev_err(&bgx->pdev->dev,
558 "SPU_BX_STATUS_RX_ALIGN not completed\n");
563 /* Clear rcvflt bit (latching high) and read it back */
564 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
565 bgx_reg_modify(bgx, lmacid,
566 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
567 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
568 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
569 if (lmac->use_training) {
570 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
571 if (!(cfg & (1ull << 13))) {
572 cfg = (1ull << 13) | (1ull << 14);
573 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
574 cfg = bgx_reg_read(bgx, lmacid,
575 BGX_SPUX_BR_PMD_CRTL);
577 bgx_reg_write(bgx, lmacid,
578 BGX_SPUX_BR_PMD_CRTL, cfg);
585 /* Wait for BGX RX to be idle */
586 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
587 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
591 /* Wait for BGX TX to be idle */
592 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
593 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
597 /* Clear receive packet disable */
598 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
599 cfg &= ~SPU_MISC_CTL_RX_DIS;
600 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
602 /* Check for MAC RX faults */
603 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
604 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
605 cfg &= SMU_RX_CTL_STATUS;
609 /* Rx local/remote fault seen.
610 * Do lmac reinit to see if condition recovers
612 bgx_lmac_xaui_init(bgx, lmac);
617 static void bgx_poll_for_link(struct work_struct *work)
620 u64 spu_link, smu_link;
622 lmac = container_of(work, struct lmac, dwork.work);
624 /* Receive link is latching low. Force it high and verify it */
625 bgx_reg_modify(lmac->bgx, lmac->lmacid,
626 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
627 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
628 SPU_STATUS1_RCV_LNK, false);
630 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
631 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
633 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
634 !(smu_link & SMU_RX_CTL_STATUS)) {
636 if (lmac->lmac_type == BGX_MODE_XLAUI)
637 lmac->last_speed = 40000;
639 lmac->last_speed = 10000;
640 lmac->last_duplex = 1;
643 lmac->last_speed = SPEED_UNKNOWN;
644 lmac->last_duplex = DUPLEX_UNKNOWN;
647 if (lmac->last_link != lmac->link_up) {
649 if (bgx_xaui_check_link(lmac)) {
650 /* Errors, clear link_up state */
652 lmac->last_speed = SPEED_UNKNOWN;
653 lmac->last_duplex = DUPLEX_UNKNOWN;
656 lmac->last_link = lmac->link_up;
659 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
662 static int phy_interface_mode(u8 lmac_type)
664 if (lmac_type == BGX_MODE_QSGMII)
665 return PHY_INTERFACE_MODE_QSGMII;
667 return PHY_INTERFACE_MODE_SGMII;
670 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
675 lmac = &bgx->lmac[lmacid];
678 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
679 (lmac->lmac_type == BGX_MODE_QSGMII)) {
681 if (bgx_lmac_sgmii_init(bgx, lmac))
685 if (bgx_lmac_xaui_init(bgx, lmac))
689 if (lmac->is_sgmii) {
690 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
691 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
692 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
693 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
695 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
696 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
697 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
698 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
702 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
704 /* Restore default cfg, incase low level firmware changed it */
705 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
707 if ((lmac->lmac_type != BGX_MODE_XFI) &&
708 (lmac->lmac_type != BGX_MODE_XLAUI) &&
709 (lmac->lmac_type != BGX_MODE_40G_KR) &&
710 (lmac->lmac_type != BGX_MODE_10G_KR)) {
714 lmac->phydev->dev_flags = 0;
716 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
718 phy_interface_mode(lmac->lmac_type)))
721 phy_start_aneg(lmac->phydev);
723 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
725 if (!lmac->check_link)
727 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
728 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
734 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
739 lmac = &bgx->lmac[lmacid];
740 if (lmac->check_link) {
741 /* Destroy work queue */
742 cancel_delayed_work_sync(&lmac->dwork);
743 destroy_workqueue(lmac->check_link);
746 /* Disable packet reception */
747 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
748 cfg &= ~CMR_PKT_RX_EN;
749 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
751 /* Give chance for Rx/Tx FIFO to get drained */
752 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
753 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
755 /* Disable packet transmission */
756 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
757 cfg &= ~CMR_PKT_TX_EN;
758 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
760 /* Disable serdes lanes */
762 bgx_reg_modify(bgx, lmacid,
763 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
765 bgx_reg_modify(bgx, lmacid,
766 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
769 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
771 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
773 bgx_flush_dmac_addrs(bgx, lmacid);
775 if ((lmac->lmac_type != BGX_MODE_XFI) &&
776 (lmac->lmac_type != BGX_MODE_XLAUI) &&
777 (lmac->lmac_type != BGX_MODE_40G_KR) &&
778 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
779 phy_disconnect(lmac->phydev);
784 static void bgx_init_hw(struct bgx *bgx)
789 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
790 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
791 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
793 /* Set lmac type and lane2serdes mapping */
794 for (i = 0; i < bgx->lmac_count; i++) {
795 lmac = &bgx->lmac[i];
796 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
797 (lmac->lmac_type << 8) | lmac->lane_to_sds);
798 bgx->lmac[i].lmacid_bd = lmac_count;
802 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
803 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
805 /* Set the backpressure AND mask */
806 for (i = 0; i < bgx->lmac_count; i++)
807 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
808 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
809 (i * MAX_BGX_CHANS_PER_LMAC));
811 /* Disable all MAC filtering */
812 for (i = 0; i < RX_DMAC_COUNT; i++)
813 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
815 /* Disable MAC steering (NCSI traffic) */
816 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
817 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
820 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
822 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
825 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
827 struct device *dev = &bgx->pdev->dev;
832 if (lmacid > MAX_LMAC_PER_BGX)
835 lmac = &bgx->lmac[lmacid];
836 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
838 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
840 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
842 switch (lmac->lmac_type) {
844 dev_info(dev, "%s: SGMII\n", (char *)str);
847 dev_info(dev, "%s: XAUI\n", (char *)str);
850 dev_info(dev, "%s: RXAUI\n", (char *)str);
853 if (!lmac->use_training)
854 dev_info(dev, "%s: XFI\n", (char *)str);
856 dev_info(dev, "%s: 10G_KR\n", (char *)str);
859 if (!lmac->use_training)
860 dev_info(dev, "%s: XLAUI\n", (char *)str);
862 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
864 case BGX_MODE_QSGMII:
866 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
869 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
871 dev_info(dev, "%s: QSGMII\n", (char *)str);
873 case BGX_MODE_INVALID:
879 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
881 switch (lmac->lmac_type) {
884 lmac->lane_to_sds = lmac->lmacid;
888 lmac->lane_to_sds = 0xE4;
891 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
893 case BGX_MODE_QSGMII:
894 /* There is no way to determine if DLM0/2 is QSGMII or
895 * DLM1/3 is configured to QSGMII as bootloader will
896 * configure all LMACs, so take whatever is configured
897 * by low level firmware.
899 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
902 lmac->lane_to_sds = 0;
907 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
915 lmac = &bgx->lmac[idx];
918 /* Read LMAC0 type to figure out QLM mode
919 * This is configured by low level firmware
921 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
922 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
924 bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
925 SPU_PMD_CRTL_TRAIN_EN;
926 lmac_set_lane2sds(bgx, lmac);
930 /* On 81xx BGX can be split across 2 DLMs
931 * firmware programs lmac_type of LMAC0 and LMAC2
933 if ((idx == 0) || (idx == 2)) {
934 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
935 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
936 lane_to_sds = (u8)(cmr_cfg & 0xFF);
937 /* Check if config is not reset value */
938 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
939 lmac->lmac_type = BGX_MODE_INVALID;
941 lmac->lmac_type = lmac_type;
943 bgx_reg_read(bgx, idx, BGX_SPUX_BR_PMD_CRTL) &
944 SPU_PMD_CRTL_TRAIN_EN;
945 lmac_set_lane2sds(bgx, lmac);
947 /* Set LMAC type of other lmac on same DLM i.e LMAC 1/3 */
948 olmac = &bgx->lmac[idx + 1];
949 olmac->lmac_type = lmac->lmac_type;
950 olmac->use_training =
951 bgx_reg_read(bgx, idx + 1, BGX_SPUX_BR_PMD_CRTL) &
952 SPU_PMD_CRTL_TRAIN_EN;
953 lmac_set_lane2sds(bgx, olmac);
957 static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
964 lmac = &bgx->lmac[0];
965 if (lmac->lmac_type == BGX_MODE_INVALID)
971 static void bgx_get_qlm_mode(struct bgx *bgx)
978 /* Init all LMAC's type to invalid */
979 for (idx = 0; idx < MAX_LMAC_PER_BGX; idx++) {
980 lmac = &bgx->lmac[idx];
981 lmac->lmac_type = BGX_MODE_INVALID;
985 /* It is assumed that low level firmware sets this value */
986 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
987 if (bgx->lmac_count > MAX_LMAC_PER_BGX)
988 bgx->lmac_count = MAX_LMAC_PER_BGX;
990 for (idx = 0; idx < MAX_LMAC_PER_BGX; idx++)
991 bgx_set_lmac_config(bgx, idx);
994 bgx_print_qlm_mode(bgx, 0);
998 if (bgx->lmac_count) {
999 bgx_print_qlm_mode(bgx, 0);
1000 bgx_print_qlm_mode(bgx, 2);
1003 /* If DLM0 is not in BGX mode then LMAC0/1 have
1004 * to be configured with serdes lanes of DLM1
1006 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1008 for (idx = 0; idx < bgx->lmac_count; idx++) {
1009 lmac01 = &bgx->lmac[idx];
1010 lmac23 = &bgx->lmac[idx + 2];
1011 lmac01->lmac_type = lmac23->lmac_type;
1012 lmac01->lane_to_sds = lmac23->lane_to_sds;
1018 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1024 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1025 "mac-address", mac, ETH_ALEN);
1029 if (!is_valid_ether_addr(mac)) {
1030 dev_err(dev, "MAC address invalid: %pM\n", mac);
1035 dev_info(dev, "MAC address set to: %pM\n", mac);
1037 memcpy(dst, mac, ETH_ALEN);
1042 /* Currently only sets the MAC address. */
1043 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1044 u32 lvl, void *context, void **rv)
1046 struct bgx *bgx = context;
1047 struct device *dev = &bgx->pdev->dev;
1048 struct acpi_device *adev;
1050 if (acpi_bus_get_device(handle, &adev))
1053 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
1055 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
1057 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
1063 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1064 void *context, void **ret_val)
1066 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1067 struct bgx *bgx = context;
1070 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1071 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1072 pr_warn("Invalid link device\n");
1076 if (strncmp(string.pointer, bgx_sel, 4))
1079 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1080 bgx_acpi_register_phy, NULL, bgx, NULL);
1082 kfree(string.pointer);
1083 return AE_CTRL_TERMINATE;
1086 static int bgx_init_acpi_phy(struct bgx *bgx)
1088 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1094 static int bgx_init_acpi_phy(struct bgx *bgx)
1099 #endif /* CONFIG_ACPI */
1101 #if IS_ENABLED(CONFIG_OF_MDIO)
1103 static int bgx_init_of_phy(struct bgx *bgx)
1105 struct fwnode_handle *fwn;
1106 struct device_node *node = NULL;
1109 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1110 struct phy_device *pd;
1111 struct device_node *phy_np;
1114 /* Should always be an OF node. But if it is not, we
1115 * cannot handle it, so exit the loop.
1117 node = to_of_node(fwn);
1121 mac = of_get_mac_address(node);
1123 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1125 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1126 bgx->lmac[lmac].lmacid = lmac;
1128 phy_np = of_parse_phandle(node, "phy-handle", 0);
1129 /* If there is no phy or defective firmware presents
1130 * this cortina phy, for which there is no driver
1131 * support, ignore it.
1134 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1135 /* Wait until the phy drivers are available */
1136 pd = of_phy_find_device(phy_np);
1139 bgx->lmac[lmac].phydev = pd;
1143 if (lmac == MAX_LMAC_PER_BGX) {
1151 /* We are bailing out, try not to leak device reference counts
1152 * for phy devices we may have already found.
1155 if (bgx->lmac[lmac].phydev) {
1156 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1157 bgx->lmac[lmac].phydev = NULL;
1162 return -EPROBE_DEFER;
1167 static int bgx_init_of_phy(struct bgx *bgx)
1172 #endif /* CONFIG_OF_MDIO */
1174 static int bgx_init_phy(struct bgx *bgx)
1177 return bgx_init_acpi_phy(bgx);
1179 return bgx_init_of_phy(bgx);
1182 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1185 struct device *dev = &pdev->dev;
1186 struct bgx *bgx = NULL;
1190 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1195 pci_set_drvdata(pdev, bgx);
1197 err = pci_enable_device(pdev);
1199 dev_err(dev, "Failed to enable PCI device\n");
1200 pci_set_drvdata(pdev, NULL);
1204 err = pci_request_regions(pdev, DRV_NAME);
1206 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1207 goto err_disable_device;
1210 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1211 if (sdevid == PCI_SUBSYS_DEVID_81XX_BGX)
1212 bgx->is_81xx = true;
1214 /* MAP configuration registers */
1215 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1216 if (!bgx->reg_base) {
1217 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1219 goto err_release_regions;
1221 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
1222 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX;
1224 bgx_vnic[bgx->bgx_id] = bgx;
1225 bgx_get_qlm_mode(bgx);
1227 err = bgx_init_phy(bgx);
1233 /* Enable all LMACs */
1234 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1235 err = bgx_lmac_enable(bgx, lmac);
1237 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1240 bgx_lmac_disable(bgx, --lmac);
1248 bgx_vnic[bgx->bgx_id] = NULL;
1249 err_release_regions:
1250 pci_release_regions(pdev);
1252 pci_disable_device(pdev);
1253 pci_set_drvdata(pdev, NULL);
1257 static void bgx_remove(struct pci_dev *pdev)
1259 struct bgx *bgx = pci_get_drvdata(pdev);
1262 /* Disable all LMACs */
1263 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1264 bgx_lmac_disable(bgx, lmac);
1266 bgx_vnic[bgx->bgx_id] = NULL;
1267 pci_release_regions(pdev);
1268 pci_disable_device(pdev);
1269 pci_set_drvdata(pdev, NULL);
1272 static struct pci_driver bgx_driver = {
1274 .id_table = bgx_id_table,
1276 .remove = bgx_remove,
1279 static int __init bgx_init_module(void)
1281 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1283 return pci_register_driver(&bgx_driver);
1286 static void __exit bgx_cleanup_module(void)
1288 pci_unregister_driver(&bgx_driver);
1291 module_init(bgx_init_module);
1292 module_exit(bgx_cleanup_module);