2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
32 int lmacid; /* ID within BGX */
33 int lmacid_bd; /* ID on board */
34 struct net_device netdev;
35 struct phy_device *phydev;
36 unsigned int last_duplex;
37 unsigned int last_link;
38 unsigned int last_speed;
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
47 struct lmac lmac[MAX_LMAC_PER_BGX];
52 void __iomem *reg_base;
56 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
57 static int lmac_count; /* Total no of LMACs in system */
59 static int bgx_xaui_check_link(struct lmac *lmac);
61 /* Supported devices */
62 static const struct pci_device_id bgx_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
64 { 0, } /* end of table */
67 MODULE_AUTHOR("Cavium Inc");
68 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
69 MODULE_LICENSE("GPL v2");
70 MODULE_VERSION(DRV_VERSION);
71 MODULE_DEVICE_TABLE(pci, bgx_id_table);
73 /* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
82 /* Register read/write APIs */
83 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
85 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
87 return readq_relaxed(addr);
90 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
92 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
94 writeq_relaxed(val, addr);
97 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
99 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
101 writeq_relaxed(val | readq_relaxed(addr), addr);
104 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
110 reg_val = bgx_reg_read(bgx, lmac, reg);
111 if (zero && !(reg_val & mask))
113 if (!zero && (reg_val & mask))
115 usleep_range(1000, 2000);
121 /* Return number of BGX present in HW */
122 unsigned bgx_get_map(int node)
127 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
128 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
134 EXPORT_SYMBOL(bgx_get_map);
136 /* Return number of LMAC configured for this BGX */
137 int bgx_get_lmac_count(int node, int bgx_idx)
141 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
143 return bgx->lmac_count;
147 EXPORT_SYMBOL(bgx_get_lmac_count);
149 /* Returns the current link status of LMAC */
150 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
152 struct bgx_link_status *link = (struct bgx_link_status *)status;
156 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
160 lmac = &bgx->lmac[lmacid];
161 link->link_up = lmac->link_up;
162 link->duplex = lmac->last_duplex;
163 link->speed = lmac->last_speed;
165 EXPORT_SYMBOL(bgx_get_lmac_link_state);
167 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
169 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
172 return bgx->lmac[lmacid].mac;
176 EXPORT_SYMBOL(bgx_get_lmac_mac);
178 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
180 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
185 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
187 EXPORT_SYMBOL(bgx_set_lmac_mac);
189 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
191 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
197 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
199 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
201 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
202 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
204 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
206 static void bgx_sgmii_change_link_state(struct lmac *lmac)
208 struct bgx *bgx = lmac->bgx;
213 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
215 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
217 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
218 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
221 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
222 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
223 port_cfg |= (lmac->last_duplex << 2);
225 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
228 switch (lmac->last_speed) {
230 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
231 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
232 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
233 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
234 misc_ctl |= 50; /* samp_pt */
235 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
236 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
239 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
240 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
241 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
242 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
243 misc_ctl |= 5; /* samp_pt */
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
248 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
249 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
250 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
251 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
252 misc_ctl |= 1; /* samp_pt */
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
254 if (lmac->last_duplex)
255 bgx_reg_write(bgx, lmac->lmacid,
256 BGX_GMP_GMI_TXX_BURST, 0);
258 bgx_reg_write(bgx, lmac->lmacid,
259 BGX_GMP_GMI_TXX_BURST, 8192);
264 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
265 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
267 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
271 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
274 static void bgx_lmac_handler(struct net_device *netdev)
276 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
277 struct phy_device *phydev = lmac->phydev;
278 int link_changed = 0;
283 if (!phydev->link && lmac->last_link)
287 (lmac->last_duplex != phydev->duplex ||
288 lmac->last_link != phydev->link ||
289 lmac->last_speed != phydev->speed)) {
293 lmac->last_link = phydev->link;
294 lmac->last_speed = phydev->speed;
295 lmac->last_duplex = phydev->duplex;
300 if (link_changed > 0)
301 lmac->link_up = true;
303 lmac->link_up = false;
306 bgx_sgmii_change_link_state(lmac);
308 bgx_xaui_check_link(lmac);
311 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
315 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
321 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
323 EXPORT_SYMBOL(bgx_get_rx_stats);
325 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
329 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
333 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
335 EXPORT_SYMBOL(bgx_get_tx_stats);
337 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
341 while (bgx->lmac[lmac].dmac > 0) {
342 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
343 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
344 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
345 bgx->lmac[lmac].dmac--;
349 /* Configure BGX LMAC in internal loopback mode */
350 void bgx_lmac_internal_loopback(int node, int bgx_idx,
351 int lmac_idx, bool enable)
357 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
361 lmac = &bgx->lmac[lmac_idx];
362 if (lmac->is_sgmii) {
363 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
365 cfg |= PCS_MRX_CTL_LOOPBACK1;
367 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
368 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
370 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
372 cfg |= SPU_CTL_LOOPBACK;
374 cfg &= ~SPU_CTL_LOOPBACK;
375 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
378 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
380 static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid)
384 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
385 /* max packet size */
386 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
388 /* Disable frame alignment if using preamble */
389 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
391 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
394 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
397 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
398 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
399 PCS_MRX_CTL_RESET, true)) {
400 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
404 /* power down, reset autoneg, autoneg enable */
405 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
406 cfg &= ~PCS_MRX_CTL_PWR_DN;
407 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
408 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
410 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
411 PCS_MRX_STATUS_AN_CPT, false)) {
412 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
419 static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type)
424 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
425 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
426 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
431 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
433 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
435 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
436 /* Set interleaved running disparity for RXAUI */
437 if (bgx->lmac_type != BGX_MODE_RXAUI)
438 bgx_reg_modify(bgx, lmacid,
439 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
441 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
442 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
444 /* clear all interrupts */
445 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
446 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
447 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
448 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
449 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
450 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
452 if (bgx->use_training) {
453 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
454 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
455 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
456 /* training enable */
457 bgx_reg_modify(bgx, lmacid,
458 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
461 /* Append FCS to each packet */
462 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
464 /* Disable forward error correction */
465 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
466 cfg &= ~SPU_FEC_CTL_FEC_EN;
467 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
469 /* Disable autoneg */
470 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
471 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
472 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
474 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
475 if (bgx->lmac_type == BGX_MODE_10G_KR)
477 else if (bgx->lmac_type == BGX_MODE_40G_KR)
480 cfg &= ~((1 << 23) | (1 << 24));
481 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
482 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
484 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
485 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
486 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
489 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
491 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
492 cfg &= ~SPU_CTL_LOW_POWER;
493 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
495 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
496 cfg &= ~SMU_TX_CTL_UNI_EN;
497 cfg |= SMU_TX_CTL_DIC_EN;
498 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
500 /* take lmac_count into account */
501 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
502 /* max packet size */
503 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
508 static int bgx_xaui_check_link(struct lmac *lmac)
510 struct bgx *bgx = lmac->bgx;
511 int lmacid = lmac->lmacid;
512 int lmac_type = bgx->lmac_type;
515 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
516 if (bgx->use_training) {
517 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
518 if (!(cfg & (1ull << 13))) {
519 cfg = (1ull << 13) | (1ull << 14);
520 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
521 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
523 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
528 /* wait for PCS to come out of reset */
529 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
530 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
534 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
535 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
536 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
537 SPU_BR_STATUS_BLK_LOCK, false)) {
538 dev_err(&bgx->pdev->dev,
539 "SPU_BR_STATUS_BLK_LOCK not completed\n");
543 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
544 SPU_BX_STATUS_RX_ALIGN, false)) {
545 dev_err(&bgx->pdev->dev,
546 "SPU_BX_STATUS_RX_ALIGN not completed\n");
551 /* Clear rcvflt bit (latching high) and read it back */
552 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
553 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
554 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
555 if (bgx->use_training) {
556 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
557 if (!(cfg & (1ull << 13))) {
558 cfg = (1ull << 13) | (1ull << 14);
559 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
560 cfg = bgx_reg_read(bgx, lmacid,
561 BGX_SPUX_BR_PMD_CRTL);
563 bgx_reg_write(bgx, lmacid,
564 BGX_SPUX_BR_PMD_CRTL, cfg);
571 /* Wait for MAC RX to be ready */
572 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL,
573 SMU_RX_CTL_STATUS, true)) {
574 dev_err(&bgx->pdev->dev, "SMU RX link not okay\n");
578 /* Wait for BGX RX to be idle */
579 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
580 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
584 /* Wait for BGX TX to be idle */
585 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
586 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
590 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
591 dev_err(&bgx->pdev->dev, "Receive fault\n");
595 /* Receive link is latching low. Force it high and verify it */
596 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
597 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1,
598 SPU_STATUS1_RCV_LNK, false)) {
599 dev_err(&bgx->pdev->dev, "SPU receive link down\n");
603 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
604 cfg &= ~SPU_MISC_CTL_RX_DIS;
605 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
609 static void bgx_poll_for_link(struct work_struct *work)
614 lmac = container_of(work, struct lmac, dwork.work);
616 /* Receive link is latching low. Force it high and verify it */
617 bgx_reg_modify(lmac->bgx, lmac->lmacid,
618 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
619 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
620 SPU_STATUS1_RCV_LNK, false);
622 link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
623 if (link & SPU_STATUS1_RCV_LNK) {
625 if (lmac->bgx->lmac_type == BGX_MODE_XLAUI)
626 lmac->last_speed = 40000;
628 lmac->last_speed = 10000;
629 lmac->last_duplex = 1;
632 lmac->last_speed = SPEED_UNKNOWN;
633 lmac->last_duplex = DUPLEX_UNKNOWN;
636 if (lmac->last_link != lmac->link_up) {
637 lmac->last_link = lmac->link_up;
639 bgx_xaui_check_link(lmac);
642 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
645 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
650 lmac = &bgx->lmac[lmacid];
653 if (bgx->lmac_type == BGX_MODE_SGMII) {
655 if (bgx_lmac_sgmii_init(bgx, lmacid))
659 if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type))
663 if (lmac->is_sgmii) {
664 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
665 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
666 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
667 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
669 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
670 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
671 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
672 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
676 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
678 /* Restore default cfg, incase low level firmware changed it */
679 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
681 if ((bgx->lmac_type != BGX_MODE_XFI) &&
682 (bgx->lmac_type != BGX_MODE_XLAUI) &&
683 (bgx->lmac_type != BGX_MODE_40G_KR) &&
684 (bgx->lmac_type != BGX_MODE_10G_KR)) {
688 lmac->phydev->dev_flags = 0;
690 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
692 PHY_INTERFACE_MODE_SGMII))
695 phy_start_aneg(lmac->phydev);
697 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
699 if (!lmac->check_link)
701 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
702 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
708 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
713 lmac = &bgx->lmac[lmacid];
714 if (lmac->check_link) {
715 /* Destroy work queue */
716 cancel_delayed_work_sync(&lmac->dwork);
717 destroy_workqueue(lmac->check_link);
720 cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
721 cmrx_cfg &= ~(1 << 15);
722 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg);
723 bgx_flush_dmac_addrs(bgx, lmacid);
725 if ((bgx->lmac_type != BGX_MODE_XFI) &&
726 (bgx->lmac_type != BGX_MODE_XLAUI) &&
727 (bgx->lmac_type != BGX_MODE_40G_KR) &&
728 (bgx->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
729 phy_disconnect(lmac->phydev);
734 static void bgx_set_num_ports(struct bgx *bgx)
738 switch (bgx->qlm_mode) {
741 bgx->lmac_type = BGX_MODE_SGMII;
742 bgx->lane_to_sds = 0;
744 case QLM_MODE_XAUI_1X4:
746 bgx->lmac_type = BGX_MODE_XAUI;
747 bgx->lane_to_sds = 0xE4;
749 case QLM_MODE_RXAUI_2X2:
751 bgx->lmac_type = BGX_MODE_RXAUI;
752 bgx->lane_to_sds = 0xE4;
754 case QLM_MODE_XFI_4X1:
756 bgx->lmac_type = BGX_MODE_XFI;
757 bgx->lane_to_sds = 0;
759 case QLM_MODE_XLAUI_1X4:
761 bgx->lmac_type = BGX_MODE_XLAUI;
762 bgx->lane_to_sds = 0xE4;
764 case QLM_MODE_10G_KR_4X1:
766 bgx->lmac_type = BGX_MODE_10G_KR;
767 bgx->lane_to_sds = 0;
768 bgx->use_training = 1;
770 case QLM_MODE_40G_KR4_1X4:
772 bgx->lmac_type = BGX_MODE_40G_KR;
773 bgx->lane_to_sds = 0xE4;
774 bgx->use_training = 1;
781 /* Check if low level firmware has programmed LMAC count
782 * based on board type, if yes consider that otherwise
783 * the default static values
785 lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
787 bgx->lmac_count = lmac_count;
790 static void bgx_init_hw(struct bgx *bgx)
794 bgx_set_num_ports(bgx);
796 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
797 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
798 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
800 /* Set lmac type and lane2serdes mapping */
801 for (i = 0; i < bgx->lmac_count; i++) {
802 if (bgx->lmac_type == BGX_MODE_RXAUI) {
804 bgx->lane_to_sds = 0x0e;
806 bgx->lane_to_sds = 0x04;
807 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
808 (bgx->lmac_type << 8) | bgx->lane_to_sds);
811 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
812 (bgx->lmac_type << 8) | (bgx->lane_to_sds + i));
813 bgx->lmac[i].lmacid_bd = lmac_count;
817 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
818 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
820 /* Set the backpressure AND mask */
821 for (i = 0; i < bgx->lmac_count; i++)
822 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
823 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
824 (i * MAX_BGX_CHANS_PER_LMAC));
826 /* Disable all MAC filtering */
827 for (i = 0; i < RX_DMAC_COUNT; i++)
828 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
830 /* Disable MAC steering (NCSI traffic) */
831 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
832 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
835 static void bgx_get_qlm_mode(struct bgx *bgx)
837 struct device *dev = &bgx->pdev->dev;
841 /* Read LMAC0 type to figure out QLM mode
842 * This is configured by low level firmware
844 lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
845 lmac_type = (lmac_type >> 8) & 0x07;
847 train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
848 SPU_PMD_CRTL_TRAIN_EN;
852 bgx->qlm_mode = QLM_MODE_SGMII;
853 dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id);
856 bgx->qlm_mode = QLM_MODE_XAUI_1X4;
857 dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id);
860 bgx->qlm_mode = QLM_MODE_RXAUI_2X2;
861 dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id);
865 bgx->qlm_mode = QLM_MODE_XFI_4X1;
866 dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id);
868 bgx->qlm_mode = QLM_MODE_10G_KR_4X1;
869 dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id);
874 bgx->qlm_mode = QLM_MODE_XLAUI_1X4;
875 dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id);
877 bgx->qlm_mode = QLM_MODE_40G_KR4_1X4;
878 dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id);
882 bgx->qlm_mode = QLM_MODE_SGMII;
883 dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id);
889 static int acpi_get_mac_address(struct acpi_device *adev, u8 *dst)
894 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
895 "mac-address", mac, ETH_ALEN);
899 if (!is_valid_ether_addr(mac)) {
904 memcpy(dst, mac, ETH_ALEN);
909 /* Currently only sets the MAC address. */
910 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
911 u32 lvl, void *context, void **rv)
913 struct bgx *bgx = context;
914 struct acpi_device *adev;
916 if (acpi_bus_get_device(handle, &adev))
919 acpi_get_mac_address(adev, bgx->lmac[bgx->lmac_count].mac);
921 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, &bgx->pdev->dev);
923 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
929 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
930 void *context, void **ret_val)
932 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
933 struct bgx *bgx = context;
936 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
937 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
938 pr_warn("Invalid link device\n");
942 if (strncmp(string.pointer, bgx_sel, 4))
945 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
946 bgx_acpi_register_phy, NULL, bgx, NULL);
948 kfree(string.pointer);
949 return AE_CTRL_TERMINATE;
952 static int bgx_init_acpi_phy(struct bgx *bgx)
954 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
960 static int bgx_init_acpi_phy(struct bgx *bgx)
965 #endif /* CONFIG_ACPI */
967 #if IS_ENABLED(CONFIG_OF_MDIO)
969 static int bgx_init_of_phy(struct bgx *bgx)
971 struct device_node *np;
972 struct device_node *np_child;
977 /* Get BGX node from DT */
978 snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id);
979 np = of_find_node_by_name(NULL, bgx_sel);
983 for_each_child_of_node(np, np_child) {
984 struct device_node *phy_np = of_parse_phandle(np_child,
988 bgx->lmac[lmac].phydev = of_phy_find_device(phy_np);
990 mac = of_get_mac_address(np_child);
992 ether_addr_copy(bgx->lmac[lmac].mac, mac);
994 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
995 bgx->lmac[lmac].lmacid = lmac;
997 if (lmac == MAX_LMAC_PER_BGX) {
998 of_node_put(np_child);
1007 static int bgx_init_of_phy(struct bgx *bgx)
1012 #endif /* CONFIG_OF_MDIO */
1014 static int bgx_init_phy(struct bgx *bgx)
1017 return bgx_init_acpi_phy(bgx);
1019 return bgx_init_of_phy(bgx);
1022 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1025 struct device *dev = &pdev->dev;
1026 struct bgx *bgx = NULL;
1029 /* Load octeon mdio driver */
1030 octeon_mdiobus_force_mod_depencency();
1032 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1037 pci_set_drvdata(pdev, bgx);
1039 err = pci_enable_device(pdev);
1041 dev_err(dev, "Failed to enable PCI device\n");
1042 pci_set_drvdata(pdev, NULL);
1046 err = pci_request_regions(pdev, DRV_NAME);
1048 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1049 goto err_disable_device;
1052 /* MAP configuration registers */
1053 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1054 if (!bgx->reg_base) {
1055 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1057 goto err_release_regions;
1059 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
1060 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX;
1062 bgx_vnic[bgx->bgx_id] = bgx;
1063 bgx_get_qlm_mode(bgx);
1065 err = bgx_init_phy(bgx);
1071 /* Enable all LMACs */
1072 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1073 err = bgx_lmac_enable(bgx, lmac);
1075 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1084 bgx_vnic[bgx->bgx_id] = NULL;
1085 err_release_regions:
1086 pci_release_regions(pdev);
1088 pci_disable_device(pdev);
1089 pci_set_drvdata(pdev, NULL);
1093 static void bgx_remove(struct pci_dev *pdev)
1095 struct bgx *bgx = pci_get_drvdata(pdev);
1098 /* Disable all LMACs */
1099 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1100 bgx_lmac_disable(bgx, lmac);
1102 bgx_vnic[bgx->bgx_id] = NULL;
1103 pci_release_regions(pdev);
1104 pci_disable_device(pdev);
1105 pci_set_drvdata(pdev, NULL);
1108 static struct pci_driver bgx_driver = {
1110 .id_table = bgx_id_table,
1112 .remove = bgx_remove,
1115 static int __init bgx_init_module(void)
1117 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1119 return pci_register_driver(&bgx_driver);
1122 static void __exit bgx_cleanup_module(void)
1124 pci_unregister_driver(&bgx_driver);
1127 module_init(bgx_init_module);
1128 module_exit(bgx_cleanup_module);