drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <net/addrconf.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/crash_dump.h>
  68
  69 #include "cxgb4.h"
  70 #include "cxgb4_filter.h"
  71 #include "t4_regs.h"
  72 #include "t4_values.h"
  73 #include "t4_msg.h"
  74 #include "t4fw_api.h"
  75 #include "t4fw_version.h"
  76 #include "cxgb4_dcb.h"
  77 #include "cxgb4_debugfs.h"
  78 #include "clip_tbl.h"
  79 #include "l2t.h"
  80 #include "sched.h"
  81 #include "cxgb4_tc_u32.h"
  82
  83 char cxgb4_driver_name[] = KBUILD_MODNAME;
  84
  85 #ifdef DRV_VERSION
  86 #undef DRV_VERSION
  87 #endif
  88 #define DRV_VERSION "2.0.0-ko"
  89 const char cxgb4_driver_version[] = DRV_VERSION;
  90 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  91
  92 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  93                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  94                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
  95
  96 /* Macros needed to support the PCI Device ID Table ...
  97  */
  98 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  99         static const struct pci_device_id cxgb4_pci_tbl[] = {
 100 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
 101
 102 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 103  * called for both.
 104  */
 105 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 106
 107 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 108                 {PCI_VDEVICE(CHELSIO, (devid)), 4}
 109
 110 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 111                 { 0, } \
 112         }
 113
 114 #include "t4_pci_id_tbl.h"
 115
 116 #define FW4_FNAME "cxgb4/t4fw.bin"
 117 #define FW5_FNAME "cxgb4/t5fw.bin"
 118 #define FW6_FNAME "cxgb4/t6fw.bin"
 119 #define FW4_CFNAME "cxgb4/t4-config.txt"
 120 #define FW5_CFNAME "cxgb4/t5-config.txt"
 121 #define FW6_CFNAME "cxgb4/t6-config.txt"
 122 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 123 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 124 #define PHY_AQ1202_DEVICEID 0x4409
 125 #define PHY_BCM84834_DEVICEID 0x4486
 126
 127 MODULE_DESCRIPTION(DRV_DESC);
 128 MODULE_AUTHOR("Chelsio Communications");
 129 MODULE_LICENSE("Dual BSD/GPL");
 130 MODULE_VERSION(DRV_VERSION);
 131 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 132 MODULE_FIRMWARE(FW4_FNAME);
 133 MODULE_FIRMWARE(FW5_FNAME);
 134 MODULE_FIRMWARE(FW6_FNAME);
 135
 136 /*
 137  * The driver uses the best interrupt scheme available on a platform in the
 138  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 139  * of these schemes the driver may consider as follows:
 140  *
 141  * msi = 2: choose from among all three options
 142  * msi = 1: only consider MSI and INTx interrupts
 143  * msi = 0: force INTx interrupts
 144  */
 145 static int msi = 2;
 146
 147 module_param(msi, int, 0644);
 148 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 149
 150 /*
 151  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 152  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 153  * boundaries.  This is a requirement for many architectures which will throw
 154  * a machine check fault if an attempt is made to access one of the 4-byte IP
 155  * header fields on a non-4-byte boundary.  And it's a major performance issue
 156  * even on some architectures which allow it like some implementations of the
 157  * x86 ISA.  However, some architectures don't mind this and for some very
 158  * edge-case performance sensitive applications (like forwarding large volumes
 159  * of small packets), setting this DMA offset to 0 will decrease the number of
 160  * PCI-E Bus transfers enough to measurably affect performance.
 161  */
 162 static int rx_dma_offset = 2;
 163
 164 /* TX Queue select used to determine what algorithm to use for selecting TX
 165  * queue. Select between the kernel provided function (select_queue=0) or user
 166  * cxgb_select_queue function (select_queue=1)
 167  *
 168  * Default: select_queue=0
 169  */
 170 static int select_queue;
 171 module_param(select_queue, int, 0644);
 172 MODULE_PARM_DESC(select_queue,
 173                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 174
 175 static struct dentry *cxgb4_debugfs_root;
 176
 177 LIST_HEAD(adapter_list);
 178 DEFINE_MUTEX(uld_mutex);
 179
 180 static void link_report(struct net_device *dev)
 181 {
 182         if (!netif_carrier_ok(dev))
 183                 netdev_info(dev, "link down\n");
 184         else {
 185                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 186
 187                 const char *s;
 188                 const struct port_info *p = netdev_priv(dev);
 189
 190                 switch (p->link_cfg.speed) {
 191                 case 100:
 192                         s = "100Mbps";
 193                         break;
 194                 case 1000:
 195                         s = "1Gbps";
 196                         break;
 197                 case 10000:
 198                         s = "10Gbps";
 199                         break;
 200                 case 25000:
 201                         s = "25Gbps";
 202                         break;
 203                 case 40000:
 204                         s = "40Gbps";
 205                         break;
 206                 case 100000:
 207                         s = "100Gbps";
 208                         break;
 209                 default:
 210                         pr_info("%s: unsupported speed: %d\n",
 211                                 dev->name, p->link_cfg.speed);
 212                         return;
 213                 }
 214
 215                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 216                             fc[p->link_cfg.fc]);
 217         }
 218 }
 219
 220 #ifdef CONFIG_CHELSIO_T4_DCB
 221 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 222 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 223 {
 224         struct port_info *pi = netdev_priv(dev);
 225         struct adapter *adap = pi->adapter;
 226         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 227         int i;
 228
 229         /* We use a simple mapping of Port TX Queue Index to DCB
 230          * Priority when we're enabling DCB.
 231          */
 232         for (i = 0; i < pi->nqsets; i++, txq++) {
 233                 u32 name, value;
 234                 int err;
 235
 236                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 237                         FW_PARAMS_PARAM_X_V(
 238                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 239                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 240                 value = enable ? i : 0xffffffff;
 241
 242                 /* Since we can be called while atomic (from "interrupt
 243                  * level") we need to issue the Set Parameters Commannd
 244                  * without sleeping (timeout < 0).
 245                  */
 246                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 247                                             &name, &value,
 248                                             -FW_CMD_MAX_TIMEOUT);
 249
 250                 if (err)
 251                         dev_err(adap->pdev_dev,
 252                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 253                                 enable ? "set" : "unset", pi->port_id, i, -err);
 254                 else
 255                         txq->dcb_prio = value;
 256         }
 257 }
 258
 259 static int cxgb4_dcb_enabled(const struct net_device *dev)
 260 {
 261         struct port_info *pi = netdev_priv(dev);
 262
 263         if (!pi->dcb.enabled)
 264                 return 0;
 265
 266         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 267                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 268 }
 269 #endif /* CONFIG_CHELSIO_T4_DCB */
 270
 271 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 272 {
 273         struct net_device *dev = adapter->port[port_id];
 274
 275         /* Skip changes from disabled ports. */
 276         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 277                 if (link_stat)
 278                         netif_carrier_on(dev);
 279                 else {
 280 #ifdef CONFIG_CHELSIO_T4_DCB
 281                         if (cxgb4_dcb_enabled(dev)) {
 282                                 cxgb4_dcb_state_init(dev);
 283                                 dcb_tx_queue_prio_enable(dev, false);
 284                         }
 285 #endif /* CONFIG_CHELSIO_T4_DCB */
 286                         netif_carrier_off(dev);
 287                 }
 288
 289                 link_report(dev);
 290         }
 291 }
 292
 293 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 294 {
 295         static const char *mod_str[] = {
 296                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 297         };
 298
 299         const struct net_device *dev = adap->port[port_id];
 300         const struct port_info *pi = netdev_priv(dev);
 301
 302         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 303                 netdev_info(dev, "port module unplugged\n");
 304         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 305                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 306         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 307                 netdev_info(dev, "%s: unsupported port module inserted\n",
 308                             dev->name);
 309         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 310                 netdev_info(dev, "%s: unknown port module inserted\n",
 311                             dev->name);
 312         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 313                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 314         else
 315                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 316                             dev->name, pi->mod_type);
 317 }
 318
 319 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 320 module_param(dbfifo_int_thresh, int, 0644);
 321 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 322
 323 /*
 324  * usecs to sleep while draining the dbfifo
 325  */
 326 static int dbfifo_drain_delay = 1000;
 327 module_param(dbfifo_drain_delay, int, 0644);
 328 MODULE_PARM_DESC(dbfifo_drain_delay,
 329                  "usecs to sleep while draining the dbfifo");
 330
 331 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 332 {
 333         struct adapter *adap = pi->adapter;
 334         u64 vec = 0;
 335         bool ucast = false;
 336         struct hash_mac_addr *entry;
 337
 338         /* Calculate the hash vector for the updated list and program it */
 339         list_for_each_entry(entry, &adap->mac_hlist, list) {
 340                 ucast |= is_unicast_ether_addr(entry->addr);
 341                 vec |= (1ULL << hash_mac_addr(entry->addr));
 342         }
 343         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 344                                 vec, false);
 345 }
 346
 347 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 348 {
 349         struct port_info *pi = netdev_priv(netdev);
 350         struct adapter *adap = pi->adapter;
 351         int ret;
 352         u64 mhash = 0;
 353         u64 uhash = 0;
 354         bool free = false;
 355         bool ucast = is_unicast_ether_addr(mac_addr);
 356         const u8 *maclist[1] = {mac_addr};
 357         struct hash_mac_addr *new_entry;
 358
 359         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
 360                                 NULL, ucast ? &uhash : &mhash, false);
 361         if (ret < 0)
 362                 goto out;
 363         /* if hash != 0, then add the addr to hash addr list
 364          * so on the end we will calculate the hash for the
 365          * list and program it
 366          */
 367         if (uhash || mhash) {
 368                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 369                 if (!new_entry)
 370                         return -ENOMEM;
 371                 ether_addr_copy(new_entry->addr, mac_addr);
 372                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 373                 ret = cxgb4_set_addr_hash(pi);
 374         }
 375 out:
 376         return ret < 0 ? ret : 0;
 377 }
 378
 379 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 380 {
 381         struct port_info *pi = netdev_priv(netdev);
 382         struct adapter *adap = pi->adapter;
 383         int ret;
 384         const u8 *maclist[1] = {mac_addr};
 385         struct hash_mac_addr *entry, *tmp;
 386
 387         /* If the MAC address to be removed is in the hash addr
 388          * list, delete it from the list and update hash vector
 389          */
 390         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 391                 if (ether_addr_equal(entry->addr, mac_addr)) {
 392                         list_del(&entry->list);
 393                         kfree(entry);
 394                         return cxgb4_set_addr_hash(pi);
 395                 }
 396         }
 397
 398         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
 399         return ret < 0 ? -EINVAL : 0;
 400 }
 401
 402 /*
 403  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 404  * If @mtu is -1 it is left unchanged.
 405  */
 406 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 407 {
 408         struct port_info *pi = netdev_priv(dev);
 409         struct adapter *adapter = pi->adapter;
 410
 411         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 412         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 413
 414         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 415                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 416                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 417                              sleep_ok);
 418 }
 419
 420 /**
 421  *      link_start - enable a port
 422  *      @dev: the port to enable
 423  *
 424  *      Performs the MAC and PHY actions needed to enable a port.
 425  */
 426 static int link_start(struct net_device *dev)
 427 {
 428         int ret;
 429         struct port_info *pi = netdev_priv(dev);
 430         unsigned int mb = pi->adapter->pf;
 431
 432         /*
 433          * We do not set address filters and promiscuity here, the stack does
 434          * that step explicitly.
 435          */
 436         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 437                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 438         if (ret == 0) {
 439                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 440                                     pi->xact_addr_filt, dev->dev_addr, true,
 441                                     true);
 442                 if (ret >= 0) {
 443                         pi->xact_addr_filt = ret;
 444                         ret = 0;
 445                 }
 446         }
 447         if (ret == 0)
 448                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 449                                     &pi->link_cfg);
 450         if (ret == 0) {
 451                 local_bh_disable();
 452                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 453                                           true, CXGB4_DCB_ENABLED);
 454                 local_bh_enable();
 455         }
 456
 457         return ret;
 458 }
 459
 460 #ifdef CONFIG_CHELSIO_T4_DCB
 461 /* Handle a Data Center Bridging update message from the firmware. */
 462 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 463 {
 464         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 465         struct net_device *dev = adap->port[adap->chan_map[port]];
 466         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 467         int new_dcb_enabled;
 468
 469         cxgb4_dcb_handle_fw_update(adap, pcmd);
 470         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 471
 472         /* If the DCB has become enabled or disabled on the port then we're
 473          * going to need to set up/tear down DCB Priority parameters for the
 474          * TX Queues associated with the port.
 475          */
 476         if (new_dcb_enabled != old_dcb_enabled)
 477                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 478 }
 479 #endif /* CONFIG_CHELSIO_T4_DCB */
 480
 481 /* Response queue handler for the FW event queue.
 482  */
 483 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 484                           const struct pkt_gl *gl)
 485 {
 486         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 487
 488         rsp++;                                          /* skip RSS header */
 489
 490         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 491          */
 492         if (unlikely(opcode == CPL_FW4_MSG &&
 493            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 494                 rsp++;
 495                 opcode = ((const struct rss_header *)rsp)->opcode;
 496                 rsp++;
 497                 if (opcode != CPL_SGE_EGR_UPDATE) {
 498                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 499                                 , opcode);
 500                         goto out;
 501                 }
 502         }
 503
 504         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 505                 const struct cpl_sge_egr_update *p = (void *)rsp;
 506                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 507                 struct sge_txq *txq;
 508
 509                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 510                 txq->restarts++;
 511                 if (txq->q_type == CXGB4_TXQ_ETH) {
 512                         struct sge_eth_txq *eq;
 513
 514                         eq = container_of(txq, struct sge_eth_txq, q);
 515                         netif_tx_wake_queue(eq->txq);
 516                 } else {
 517                         struct sge_uld_txq *oq;
 518
 519                         oq = container_of(txq, struct sge_uld_txq, q);
 520                         tasklet_schedule(&oq->qresume_tsk);
 521                 }
 522         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 523                 const struct cpl_fw6_msg *p = (void *)rsp;
 524
 525 #ifdef CONFIG_CHELSIO_T4_DCB
 526                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 527                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 528                 unsigned int action =
 529                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 530
 531                 if (cmd == FW_PORT_CMD &&
 532                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 533                         int port = FW_PORT_CMD_PORTID_G(
 534                                         be32_to_cpu(pcmd->op_to_portid));
 535                         struct net_device *dev =
 536                                 q->adap->port[q->adap->chan_map[port]];
 537                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 538                                             FW_PORT_CMD_DCBXDIS_F)
 539                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 540                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 541
 542                         cxgb4_dcb_state_fsm(dev, state_input);
 543                 }
 544
 545                 if (cmd == FW_PORT_CMD &&
 546                     action == FW_PORT_ACTION_L2_DCB_CFG)
 547                         dcb_rpl(q->adap, pcmd);
 548                 else
 549 #endif
 550                         if (p->type == 0)
 551                                 t4_handle_fw_rpl(q->adap, p->data);
 552         } else if (opcode == CPL_L2T_WRITE_RPL) {
 553                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 554
 555                 do_l2t_write_rpl(q->adap, p);
 556         } else if (opcode == CPL_SET_TCB_RPL) {
 557                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 558
 559                 filter_rpl(q->adap, p);
 560         } else
 561                 dev_err(q->adap->pdev_dev,
 562                         "unexpected CPL %#x on FW event queue\n", opcode);
 563 out:
 564         return 0;
 565 }
 566
 567 static void disable_msi(struct adapter *adapter)
 568 {
 569         if (adapter->flags & USING_MSIX) {
 570                 pci_disable_msix(adapter->pdev);
 571                 adapter->flags &= ~USING_MSIX;
 572         } else if (adapter->flags & USING_MSI) {
 573                 pci_disable_msi(adapter->pdev);
 574                 adapter->flags &= ~USING_MSI;
 575         }
 576 }
 577
 578 /*
 579  * Interrupt handler for non-data events used with MSI-X.
 580  */
 581 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 582 {
 583         struct adapter *adap = cookie;
 584         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 585
 586         if (v & PFSW_F) {
 587                 adap->swintr = 1;
 588                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 589         }
 590         if (adap->flags & MASTER_PF)
 591                 t4_slow_intr_handler(adap);
 592         return IRQ_HANDLED;
 593 }
 594
 595 /*
 596  * Name the MSI-X interrupts.
 597  */
 598 static void name_msix_vecs(struct adapter *adap)
 599 {
 600         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 601
 602         /* non-data interrupts */
 603         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 604
 605         /* FW events */
 606         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 607                  adap->port[0]->name);
 608
 609         /* Ethernet queues */
 610         for_each_port(adap, j) {
 611                 struct net_device *d = adap->port[j];
 612                 const struct port_info *pi = netdev_priv(d);
 613
 614                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 615                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 616                                  d->name, i);
 617         }
 618 }
 619
 620 static int request_msix_queue_irqs(struct adapter *adap)
 621 {
 622         struct sge *s = &adap->sge;
 623         int err, ethqidx;
 624         int msi_index = 2;
 625
 626         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 627                           adap->msix_info[1].desc, &s->fw_evtq);
 628         if (err)
 629                 return err;
 630
 631         for_each_ethrxq(s, ethqidx) {
 632                 err = request_irq(adap->msix_info[msi_index].vec,
 633                                   t4_sge_intr_msix, 0,
 634                                   adap->msix_info[msi_index].desc,
 635                                   &s->ethrxq[ethqidx].rspq);
 636                 if (err)
 637                         goto unwind;
 638                 msi_index++;
 639         }
 640         return 0;
 641
 642 unwind:
 643         while (--ethqidx >= 0)
 644                 free_irq(adap->msix_info[--msi_index].vec,
 645                          &s->ethrxq[ethqidx].rspq);
 646         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 647         return err;
 648 }
 649
 650 static void free_msix_queue_irqs(struct adapter *adap)
 651 {
 652         int i, msi_index = 2;
 653         struct sge *s = &adap->sge;
 654
 655         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 656         for_each_ethrxq(s, i)
 657                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 658 }
 659
 660 /**
 661  *      cxgb4_write_rss - write the RSS table for a given port
 662  *      @pi: the port
 663  *      @queues: array of queue indices for RSS
 664  *
 665  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 666  *      packets to the Rx queues in @queues.
 667  *      Should never be called before setting up sge eth rx queues
 668  */
 669 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 670 {
 671         u16 *rss;
 672         int i, err;
 673         struct adapter *adapter = pi->adapter;
 674         const struct sge_eth_rxq *rxq;
 675
 676         rxq = &adapter->sge.ethrxq[pi->first_qset];
 677         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 678         if (!rss)
 679                 return -ENOMEM;
 680
 681         /* map the queue indices to queue ids */
 682         for (i = 0; i < pi->rss_size; i++, queues++)
 683                 rss[i] = rxq[*queues].rspq.abs_id;
 684
 685         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 686                                   pi->rss_size, rss, pi->rss_size);
 687         /* If Tunnel All Lookup isn't specified in the global RSS
 688          * Configuration, then we need to specify a default Ingress
 689          * Queue for any ingress packets which aren't hashed.  We'll
 690          * use our first ingress queue ...
 691          */
 692         if (!err)
 693                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 694                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 695                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 696                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 697                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 698                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 699                                        rss[0]);
 700         kfree(rss);
 701         return err;
 702 }
 703
 704 /**
 705  *      setup_rss - configure RSS
 706  *      @adap: the adapter
 707  *
 708  *      Sets up RSS for each port.
 709  */
 710 static int setup_rss(struct adapter *adap)
 711 {
 712         int i, j, err;
 713
 714         for_each_port(adap, i) {
 715                 const struct port_info *pi = adap2pinfo(adap, i);
 716
 717                 /* Fill default values with equal distribution */
 718                 for (j = 0; j < pi->rss_size; j++)
 719                         pi->rss[j] = j % pi->nqsets;
 720
 721                 err = cxgb4_write_rss(pi, pi->rss);
 722                 if (err)
 723                         return err;
 724         }
 725         return 0;
 726 }
 727
 728 /*
 729  * Return the channel of the ingress queue with the given qid.
 730  */
 731 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 732 {
 733         qid -= p->ingr_start;
 734         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 735 }
 736
 737 /*
 738  * Wait until all NAPI handlers are descheduled.
 739  */
 740 static void quiesce_rx(struct adapter *adap)
 741 {
 742         int i;
 743
 744         for (i = 0; i < adap->sge.ingr_sz; i++) {
 745                 struct sge_rspq *q = adap->sge.ingr_map[i];
 746
 747                 if (q && q->handler)
 748                         napi_disable(&q->napi);
 749         }
 750 }
 751
 752 /* Disable interrupt and napi handler */
 753 static void disable_interrupts(struct adapter *adap)
 754 {
 755         if (adap->flags & FULL_INIT_DONE) {
 756                 t4_intr_disable(adap);
 757                 if (adap->flags & USING_MSIX) {
 758                         free_msix_queue_irqs(adap);
 759                         free_irq(adap->msix_info[0].vec, adap);
 760                 } else {
 761                         free_irq(adap->pdev->irq, adap);
 762                 }
 763                 quiesce_rx(adap);
 764         }
 765 }
 766
 767 /*
 768  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 769  */
 770 static void enable_rx(struct adapter *adap)
 771 {
 772         int i;
 773
 774         for (i = 0; i < adap->sge.ingr_sz; i++) {
 775                 struct sge_rspq *q = adap->sge.ingr_map[i];
 776
 777                 if (!q)
 778                         continue;
 779                 if (q->handler)
 780                         napi_enable(&q->napi);
 781
 782                 /* 0-increment GTS to start the timer and enable interrupts */
 783                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 784                              SEINTARM_V(q->intr_params) |
 785                              INGRESSQID_V(q->cntxt_id));
 786         }
 787 }
 788
 789
 790 static int setup_fw_sge_queues(struct adapter *adap)
 791 {
 792         struct sge *s = &adap->sge;
 793         int err = 0;
 794
 795         bitmap_zero(s->starving_fl, s->egr_sz);
 796         bitmap_zero(s->txq_maperr, s->egr_sz);
 797
 798         if (adap->flags & USING_MSIX)
 799                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 800         else {
 801                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 802                                        NULL, NULL, NULL, -1);
 803                 if (err)
 804                         return err;
 805                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
 806         }
 807
 808         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 809                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
 810         if (err)
 811                 t4_free_sge_resources(adap);
 812         return err;
 813 }
 814
 815 /**
 816  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 817  *      @adap: the adapter
 818  *
 819  *      Determines how many sets of SGE queues to use and initializes them.
 820  *      We support multiple queue sets per port if we have MSI-X, otherwise
 821  *      just one queue set per port.
 822  */
 823 static int setup_sge_queues(struct adapter *adap)
 824 {
 825         int err, i, j;
 826         struct sge *s = &adap->sge;
 827         struct sge_uld_rxq_info *rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
 828         unsigned int cmplqid = 0;
 829
 830         for_each_port(adap, i) {
 831                 struct net_device *dev = adap->port[i];
 832                 struct port_info *pi = netdev_priv(dev);
 833                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
 834                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
 835
 836                 for (j = 0; j < pi->nqsets; j++, q++) {
 837                         if (adap->msi_idx > 0)
 838                                 adap->msi_idx++;
 839                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
 840                                                adap->msi_idx, &q->fl,
 841                                                t4_ethrx_handler,
 842                                                NULL,
 843                                                t4_get_mps_bg_map(adap,
 844                                                                  pi->tx_chan));
 845                         if (err)
 846                                 goto freeout;
 847                         q->rspq.idx = j;
 848                         memset(&q->stats, 0, sizeof(q->stats));
 849                 }
 850                 for (j = 0; j < pi->nqsets; j++, t++) {
 851                         err = t4_sge_alloc_eth_txq(adap, t, dev,
 852                                         netdev_get_tx_queue(dev, j),
 853                                         s->fw_evtq.cntxt_id);
 854                         if (err)
 855                                 goto freeout;
 856                 }
 857         }
 858
 859         for_each_port(adap, i) {
 860                 /* Note that cmplqid below is 0 if we don't
 861                  * have RDMA queues, and that's the right value.
 862                  */
 863                 if (rxq_info)
 864                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 865
 866                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
 867                                             s->fw_evtq.cntxt_id, cmplqid);
 868                 if (err)
 869                         goto freeout;
 870         }
 871
 872         t4_write_reg(adap, is_t4(adap->params.chip) ?
 873                                 MPS_TRC_RSS_CONTROL_A :
 874                                 MPS_T5_TRC_RSS_CONTROL_A,
 875                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
 876                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
 877         return 0;
 878 freeout:
 879         t4_free_sge_resources(adap);
 880         return err;
 881 }
 882
 883 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
 884                              void *accel_priv, select_queue_fallback_t fallback)
 885 {
 886         int txq;
 887
 888 #ifdef CONFIG_CHELSIO_T4_DCB
 889         /* If a Data Center Bridging has been successfully negotiated on this
 890          * link then we'll use the skb's priority to map it to a TX Queue.
 891          * The skb's priority is determined via the VLAN Tag Priority Code
 892          * Point field.
 893          */
 894         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
 895                 u16 vlan_tci;
 896                 int err;
 897
 898                 err = vlan_get_tag(skb, &vlan_tci);
 899                 if (unlikely(err)) {
 900                         if (net_ratelimit())
 901                                 netdev_warn(dev,
 902                                             "TX Packet without VLAN Tag on DCB Link\n");
 903                         txq = 0;
 904                 } else {
 905                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
 906 #ifdef CONFIG_CHELSIO_T4_FCOE
 907                         if (skb->protocol == htons(ETH_P_FCOE))
 908                                 txq = skb->priority & 0x7;
 909 #endif /* CONFIG_CHELSIO_T4_FCOE */
 910                 }
 911                 return txq;
 912         }
 913 #endif /* CONFIG_CHELSIO_T4_DCB */
 914
 915         if (select_queue) {
 916                 txq = (skb_rx_queue_recorded(skb)
 917                         ? skb_get_rx_queue(skb)
 918                         : smp_processor_id());
 919
 920                 while (unlikely(txq >= dev->real_num_tx_queues))
 921                         txq -= dev->real_num_tx_queues;
 922
 923                 return txq;
 924         }
 925
 926         return fallback(dev, skb) % dev->real_num_tx_queues;
 927 }
 928
 929 static int closest_timer(const struct sge *s, int time)
 930 {
 931         int i, delta, match = 0, min_delta = INT_MAX;
 932
 933         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 934                 delta = time - s->timer_val[i];
 935                 if (delta < 0)
 936                         delta = -delta;
 937                 if (delta < min_delta) {
 938                         min_delta = delta;
 939                         match = i;
 940                 }
 941         }
 942         return match;
 943 }
 944
 945 static int closest_thres(const struct sge *s, int thres)
 946 {
 947         int i, delta, match = 0, min_delta = INT_MAX;
 948
 949         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 950                 delta = thres - s->counter_val[i];
 951                 if (delta < 0)
 952                         delta = -delta;
 953                 if (delta < min_delta) {
 954                         min_delta = delta;
 955                         match = i;
 956                 }
 957         }
 958         return match;
 959 }
 960
 961 /**
 962  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 963  *      @q: the Rx queue
 964  *      @us: the hold-off time in us, or 0 to disable timer
 965  *      @cnt: the hold-off packet count, or 0 to disable counter
 966  *
 967  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
 968  *      one of the two needs to be enabled for the queue to generate interrupts.
 969  */
 970 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
 971                                unsigned int us, unsigned int cnt)
 972 {
 973         struct adapter *adap = q->adap;
 974
 975         if ((us | cnt) == 0)
 976                 cnt = 1;
 977
 978         if (cnt) {
 979                 int err;
 980                 u32 v, new_idx;
 981
 982                 new_idx = closest_thres(&adap->sge, cnt);
 983                 if (q->desc && q->pktcnt_idx != new_idx) {
 984                         /* the queue has already been created, update it */
 985                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 986                             FW_PARAMS_PARAM_X_V(
 987                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 988                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
 989                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 990                                             &v, &new_idx);
 991                         if (err)
 992                                 return err;
 993                 }
 994                 q->pktcnt_idx = new_idx;
 995         }
 996
 997         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
 998         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
 999         return 0;
1000 }
1001
1002 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1003 {
1004         const struct port_info *pi = netdev_priv(dev);
1005         netdev_features_t changed = dev->features ^ features;
1006         int err;
1007
1008         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1009                 return 0;
1010
1011         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1012                             -1, -1, -1,
1013                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1014         if (unlikely(err))
1015                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1016         return err;
1017 }
1018
1019 static int setup_debugfs(struct adapter *adap)
1020 {
1021         if (IS_ERR_OR_NULL(adap->debugfs_root))
1022                 return -1;
1023
1024 #ifdef CONFIG_DEBUG_FS
1025         t4_setup_debugfs(adap);
1026 #endif
1027         return 0;
1028 }
1029
1030 /*
1031  * upper-layer driver support
1032  */
1033
1034 /*
1035  * Allocate an active-open TID and set it to the supplied value.
1036  */
1037 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1038 {
1039         int atid = -1;
1040
1041         spin_lock_bh(&t->atid_lock);
1042         if (t->afree) {
1043                 union aopen_entry *p = t->afree;
1044
1045                 atid = (p - t->atid_tab) + t->atid_base;
1046                 t->afree = p->next;
1047                 p->data = data;
1048                 t->atids_in_use++;
1049         }
1050         spin_unlock_bh(&t->atid_lock);
1051         return atid;
1052 }
1053 EXPORT_SYMBOL(cxgb4_alloc_atid);
1054
1055 /*
1056  * Release an active-open TID.
1057  */
1058 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1059 {
1060         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1061
1062         spin_lock_bh(&t->atid_lock);
1063         p->next = t->afree;
1064         t->afree = p;
1065         t->atids_in_use--;
1066         spin_unlock_bh(&t->atid_lock);
1067 }
1068 EXPORT_SYMBOL(cxgb4_free_atid);
1069
1070 /*
1071  * Allocate a server TID and set it to the supplied value.
1072  */
1073 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1074 {
1075         int stid;
1076
1077         spin_lock_bh(&t->stid_lock);
1078         if (family == PF_INET) {
1079                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1080                 if (stid < t->nstids)
1081                         __set_bit(stid, t->stid_bmap);
1082                 else
1083                         stid = -1;
1084         } else {
1085                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1086                 if (stid < 0)
1087                         stid = -1;
1088         }
1089         if (stid >= 0) {
1090                 t->stid_tab[stid].data = data;
1091                 stid += t->stid_base;
1092                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1093                  * This is equivalent to 4 TIDs. With CLIP enabled it
1094                  * needs 2 TIDs.
1095                  */
1096                 if (family == PF_INET6) {
1097                         t->stids_in_use += 2;
1098                         t->v6_stids_in_use += 2;
1099                 } else {
1100                         t->stids_in_use++;
1101                 }
1102         }
1103         spin_unlock_bh(&t->stid_lock);
1104         return stid;
1105 }
1106 EXPORT_SYMBOL(cxgb4_alloc_stid);
1107
1108 /* Allocate a server filter TID and set it to the supplied value.
1109  */
1110 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1111 {
1112         int stid;
1113
1114         spin_lock_bh(&t->stid_lock);
1115         if (family == PF_INET) {
1116                 stid = find_next_zero_bit(t->stid_bmap,
1117                                 t->nstids + t->nsftids, t->nstids);
1118                 if (stid < (t->nstids + t->nsftids))
1119                         __set_bit(stid, t->stid_bmap);
1120                 else
1121                         stid = -1;
1122         } else {
1123                 stid = -1;
1124         }
1125         if (stid >= 0) {
1126                 t->stid_tab[stid].data = data;
1127                 stid -= t->nstids;
1128                 stid += t->sftid_base;
1129                 t->sftids_in_use++;
1130         }
1131         spin_unlock_bh(&t->stid_lock);
1132         return stid;
1133 }
1134 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1135
1136 /* Release a server TID.
1137  */
1138 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1139 {
1140         /* Is it a server filter TID? */
1141         if (t->nsftids && (stid >= t->sftid_base)) {
1142                 stid -= t->sftid_base;
1143                 stid += t->nstids;
1144         } else {
1145                 stid -= t->stid_base;
1146         }
1147
1148         spin_lock_bh(&t->stid_lock);
1149         if (family == PF_INET)
1150                 __clear_bit(stid, t->stid_bmap);
1151         else
1152                 bitmap_release_region(t->stid_bmap, stid, 1);
1153         t->stid_tab[stid].data = NULL;
1154         if (stid < t->nstids) {
1155                 if (family == PF_INET6) {
1156                         t->stids_in_use -= 2;
1157                         t->v6_stids_in_use -= 2;
1158                 } else {
1159                         t->stids_in_use--;
1160                 }
1161         } else {
1162                 t->sftids_in_use--;
1163         }
1164
1165         spin_unlock_bh(&t->stid_lock);
1166 }
1167 EXPORT_SYMBOL(cxgb4_free_stid);
1168
1169 /*
1170  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1171  */
1172 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1173                            unsigned int tid)
1174 {
1175         struct cpl_tid_release *req;
1176
1177         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1178         req = __skb_put(skb, sizeof(*req));
1179         INIT_TP_WR(req, tid);
1180         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1181 }
1182
1183 /*
1184  * Queue a TID release request and if necessary schedule a work queue to
1185  * process it.
1186  */
1187 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1188                                     unsigned int tid)
1189 {
1190         void **p = &t->tid_tab[tid];
1191         struct adapter *adap = container_of(t, struct adapter, tids);
1192
1193         spin_lock_bh(&adap->tid_release_lock);
1194         *p = adap->tid_release_head;
1195         /* Low 2 bits encode the Tx channel number */
1196         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1197         if (!adap->tid_release_task_busy) {
1198                 adap->tid_release_task_busy = true;
1199                 queue_work(adap->workq, &adap->tid_release_task);
1200         }
1201         spin_unlock_bh(&adap->tid_release_lock);
1202 }
1203
1204 /*
1205  * Process the list of pending TID release requests.
1206  */
1207 static void process_tid_release_list(struct work_struct *work)
1208 {
1209         struct sk_buff *skb;
1210         struct adapter *adap;
1211
1212         adap = container_of(work, struct adapter, tid_release_task);
1213
1214         spin_lock_bh(&adap->tid_release_lock);
1215         while (adap->tid_release_head) {
1216                 void **p = adap->tid_release_head;
1217                 unsigned int chan = (uintptr_t)p & 3;
1218                 p = (void *)p - chan;
1219
1220                 adap->tid_release_head = *p;
1221                 *p = NULL;
1222                 spin_unlock_bh(&adap->tid_release_lock);
1223
1224                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1225                                          GFP_KERNEL)))
1226                         schedule_timeout_uninterruptible(1);
1227
1228                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1229                 t4_ofld_send(adap, skb);
1230                 spin_lock_bh(&adap->tid_release_lock);
1231         }
1232         adap->tid_release_task_busy = false;
1233         spin_unlock_bh(&adap->tid_release_lock);
1234 }
1235
1236 /*
1237  * Release a TID and inform HW.  If we are unable to allocate the release
1238  * message we defer to a work queue.
1239  */
1240 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1241                       unsigned short family)
1242 {
1243         struct sk_buff *skb;
1244         struct adapter *adap = container_of(t, struct adapter, tids);
1245
1246         WARN_ON(tid >= t->ntids);
1247
1248         if (t->tid_tab[tid]) {
1249                 t->tid_tab[tid] = NULL;
1250                 atomic_dec(&t->conns_in_use);
1251                 if (t->hash_base && (tid >= t->hash_base)) {
1252                         if (family == AF_INET6)
1253                                 atomic_sub(2, &t->hash_tids_in_use);
1254                         else
1255                                 atomic_dec(&t->hash_tids_in_use);
1256                 } else {
1257                         if (family == AF_INET6)
1258                                 atomic_sub(2, &t->tids_in_use);
1259                         else
1260                                 atomic_dec(&t->tids_in_use);
1261                 }
1262         }
1263
1264         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1265         if (likely(skb)) {
1266                 mk_tid_release(skb, chan, tid);
1267                 t4_ofld_send(adap, skb);
1268         } else
1269                 cxgb4_queue_tid_release(t, chan, tid);
1270 }
1271 EXPORT_SYMBOL(cxgb4_remove_tid);
1272
1273 /*
1274  * Allocate and initialize the TID tables.  Returns 0 on success.
1275  */
1276 static int tid_init(struct tid_info *t)
1277 {
1278         struct adapter *adap = container_of(t, struct adapter, tids);
1279         unsigned int max_ftids = t->nftids + t->nsftids;
1280         unsigned int natids = t->natids;
1281         unsigned int stid_bmap_size;
1282         unsigned int ftid_bmap_size;
1283         size_t size;
1284
1285         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1286         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1287         size = t->ntids * sizeof(*t->tid_tab) +
1288                natids * sizeof(*t->atid_tab) +
1289                t->nstids * sizeof(*t->stid_tab) +
1290                t->nsftids * sizeof(*t->stid_tab) +
1291                stid_bmap_size * sizeof(long) +
1292                max_ftids * sizeof(*t->ftid_tab) +
1293                ftid_bmap_size * sizeof(long);
1294
1295         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1296         if (!t->tid_tab)
1297                 return -ENOMEM;
1298
1299         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1300         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1301         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1302         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1303         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1304         spin_lock_init(&t->stid_lock);
1305         spin_lock_init(&t->atid_lock);
1306         spin_lock_init(&t->ftid_lock);
1307
1308         t->stids_in_use = 0;
1309         t->v6_stids_in_use = 0;
1310         t->sftids_in_use = 0;
1311         t->afree = NULL;
1312         t->atids_in_use = 0;
1313         atomic_set(&t->tids_in_use, 0);
1314         atomic_set(&t->conns_in_use, 0);
1315         atomic_set(&t->hash_tids_in_use, 0);
1316
1317         /* Setup the free list for atid_tab and clear the stid bitmap. */
1318         if (natids) {
1319                 while (--natids)
1320                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1321                 t->afree = t->atid_tab;
1322         }
1323
1324         if (is_offload(adap)) {
1325                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1326                 /* Reserve stid 0 for T4/T5 adapters */
1327                 if (!t->stid_base &&
1328                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1329                         __set_bit(0, t->stid_bmap);
1330         }
1331
1332         bitmap_zero(t->ftid_bmap, t->nftids);
1333         return 0;
1334 }
1335
1336 /**
1337  *      cxgb4_create_server - create an IP server
1338  *      @dev: the device
1339  *      @stid: the server TID
1340  *      @sip: local IP address to bind server to
1341  *      @sport: the server's TCP port
1342  *      @queue: queue to direct messages from this server to
1343  *
1344  *      Create an IP server for the given port and address.
1345  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1346  */
1347 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1348                         __be32 sip, __be16 sport, __be16 vlan,
1349                         unsigned int queue)
1350 {
1351         unsigned int chan;
1352         struct sk_buff *skb;
1353         struct adapter *adap;
1354         struct cpl_pass_open_req *req;
1355         int ret;
1356
1357         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1358         if (!skb)
1359                 return -ENOMEM;
1360
1361         adap = netdev2adap(dev);
1362         req = __skb_put(skb, sizeof(*req));
1363         INIT_TP_WR(req, 0);
1364         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1365         req->local_port = sport;
1366         req->peer_port = htons(0);
1367         req->local_ip = sip;
1368         req->peer_ip = htonl(0);
1369         chan = rxq_to_chan(&adap->sge, queue);
1370         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1371         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1372                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1373         ret = t4_mgmt_tx(adap, skb);
1374         return net_xmit_eval(ret);
1375 }
1376 EXPORT_SYMBOL(cxgb4_create_server);
1377
1378 /*      cxgb4_create_server6 - create an IPv6 server
1379  *      @dev: the device
1380  *      @stid: the server TID
1381  *      @sip: local IPv6 address to bind server to
1382  *      @sport: the server's TCP port
1383  *      @queue: queue to direct messages from this server to
1384  *
1385  *      Create an IPv6 server for the given port and address.
1386  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1387  */
1388 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1389                          const struct in6_addr *sip, __be16 sport,
1390                          unsigned int queue)
1391 {
1392         unsigned int chan;
1393         struct sk_buff *skb;
1394         struct adapter *adap;
1395         struct cpl_pass_open_req6 *req;
1396         int ret;
1397
1398         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1399         if (!skb)
1400                 return -ENOMEM;
1401
1402         adap = netdev2adap(dev);
1403         req = __skb_put(skb, sizeof(*req));
1404         INIT_TP_WR(req, 0);
1405         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1406         req->local_port = sport;
1407         req->peer_port = htons(0);
1408         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1409         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1410         req->peer_ip_hi = cpu_to_be64(0);
1411         req->peer_ip_lo = cpu_to_be64(0);
1412         chan = rxq_to_chan(&adap->sge, queue);
1413         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1414         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1415                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1416         ret = t4_mgmt_tx(adap, skb);
1417         return net_xmit_eval(ret);
1418 }
1419 EXPORT_SYMBOL(cxgb4_create_server6);
1420
1421 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1422                         unsigned int queue, bool ipv6)
1423 {
1424         struct sk_buff *skb;
1425         struct adapter *adap;
1426         struct cpl_close_listsvr_req *req;
1427         int ret;
1428
1429         adap = netdev2adap(dev);
1430
1431         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1432         if (!skb)
1433                 return -ENOMEM;
1434
1435         req = __skb_put(skb, sizeof(*req));
1436         INIT_TP_WR(req, 0);
1437         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1438         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1439                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1440         ret = t4_mgmt_tx(adap, skb);
1441         return net_xmit_eval(ret);
1442 }
1443 EXPORT_SYMBOL(cxgb4_remove_server);
1444
1445 /**
1446  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1447  *      @mtus: the HW MTU table
1448  *      @mtu: the target MTU
1449  *      @idx: index of selected entry in the MTU table
1450  *
1451  *      Returns the index and the value in the HW MTU table that is closest to
1452  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1453  *      table, in which case that smallest available value is selected.
1454  */
1455 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1456                             unsigned int *idx)
1457 {
1458         unsigned int i = 0;
1459
1460         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1461                 ++i;
1462         if (idx)
1463                 *idx = i;
1464         return mtus[i];
1465 }
1466 EXPORT_SYMBOL(cxgb4_best_mtu);
1467
1468 /**
1469  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1470  *     @mtus: the HW MTU table
1471  *     @header_size: Header Size
1472  *     @data_size_max: maximum Data Segment Size
1473  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1474  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1475  *
1476  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1477  *     MTU Table based solely on a Maximum MTU parameter, we break that
1478  *     parameter up into a Header Size and Maximum Data Segment Size, and
1479  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1480  *     the Hardware MTU Table which will result in a Data Segment Size with
1481  *     the requested alignment _and_ that MTU isn't "too far" from the
1482  *     closest MTU, then we'll return that rather than the closest MTU.
1483  */
1484 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1485                                     unsigned short header_size,
1486                                     unsigned short data_size_max,
1487                                     unsigned short data_size_align,
1488                                     unsigned int *mtu_idxp)
1489 {
1490         unsigned short max_mtu = header_size + data_size_max;
1491         unsigned short data_size_align_mask = data_size_align - 1;
1492         int mtu_idx, aligned_mtu_idx;
1493
1494         /* Scan the MTU Table till we find an MTU which is larger than our
1495          * Maximum MTU or we reach the end of the table.  Along the way,
1496          * record the last MTU found, if any, which will result in a Data
1497          * Segment Length matching the requested alignment.
1498          */
1499         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1500                 unsigned short data_size = mtus[mtu_idx] - header_size;
1501
1502                 /* If this MTU minus the Header Size would result in a
1503                  * Data Segment Size of the desired alignment, remember it.
1504                  */
1505                 if ((data_size & data_size_align_mask) == 0)
1506                         aligned_mtu_idx = mtu_idx;
1507
1508                 /* If we're not at the end of the Hardware MTU Table and the
1509                  * next element is larger than our Maximum MTU, drop out of
1510                  * the loop.
1511                  */
1512                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1513                         break;
1514         }
1515
1516         /* If we fell out of the loop because we ran to the end of the table,
1517          * then we just have to use the last [largest] entry.
1518          */
1519         if (mtu_idx == NMTUS)
1520                 mtu_idx--;
1521
1522         /* If we found an MTU which resulted in the requested Data Segment
1523          * Length alignment and that's "not far" from the largest MTU which is
1524          * less than or equal to the maximum MTU, then use that.
1525          */
1526         if (aligned_mtu_idx >= 0 &&
1527             mtu_idx - aligned_mtu_idx <= 1)
1528                 mtu_idx = aligned_mtu_idx;
1529
1530         /* If the caller has passed in an MTU Index pointer, pass the
1531          * MTU Index back.  Return the MTU value.
1532          */
1533         if (mtu_idxp)
1534                 *mtu_idxp = mtu_idx;
1535         return mtus[mtu_idx];
1536 }
1537 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1538
1539 /**
1540  *      cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1541  *      @chip: chip type
1542  *      @viid: VI id of the given port
1543  *
1544  *      Return the SMT index for this VI.
1545  */
1546 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1547 {
1548         /* In T4/T5, SMT contains 256 SMAC entries organized in
1549          * 128 rows of 2 entries each.
1550          * In T6, SMT contains 256 SMAC entries in 256 rows.
1551          * TODO: The below code needs to be updated when we add support
1552          * for 256 VFs.
1553          */
1554         if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1555                 return ((viid & 0x7f) << 1);
1556         else
1557                 return (viid & 0x7f);
1558 }
1559 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1560
1561 /**
1562  *      cxgb4_port_chan - get the HW channel of a port
1563  *      @dev: the net device for the port
1564  *
1565  *      Return the HW Tx channel of the given port.
1566  */
1567 unsigned int cxgb4_port_chan(const struct net_device *dev)
1568 {
1569         return netdev2pinfo(dev)->tx_chan;
1570 }
1571 EXPORT_SYMBOL(cxgb4_port_chan);
1572
1573 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1574 {
1575         struct adapter *adap = netdev2adap(dev);
1576         u32 v1, v2, lp_count, hp_count;
1577
1578         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1579         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1580         if (is_t4(adap->params.chip)) {
1581                 lp_count = LP_COUNT_G(v1);
1582                 hp_count = HP_COUNT_G(v1);
1583         } else {
1584                 lp_count = LP_COUNT_T5_G(v1);
1585                 hp_count = HP_COUNT_T5_G(v2);
1586         }
1587         return lpfifo ? lp_count : hp_count;
1588 }
1589 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1590
1591 /**
1592  *      cxgb4_port_viid - get the VI id of a port
1593  *      @dev: the net device for the port
1594  *
1595  *      Return the VI id of the given port.
1596  */
1597 unsigned int cxgb4_port_viid(const struct net_device *dev)
1598 {
1599         return netdev2pinfo(dev)->viid;
1600 }
1601 EXPORT_SYMBOL(cxgb4_port_viid);
1602
1603 /**
1604  *      cxgb4_port_idx - get the index of a port
1605  *      @dev: the net device for the port
1606  *
1607  *      Return the index of the given port.
1608  */
1609 unsigned int cxgb4_port_idx(const struct net_device *dev)
1610 {
1611         return netdev2pinfo(dev)->port_id;
1612 }
1613 EXPORT_SYMBOL(cxgb4_port_idx);
1614
1615 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1616                          struct tp_tcp_stats *v6)
1617 {
1618         struct adapter *adap = pci_get_drvdata(pdev);
1619
1620         spin_lock(&adap->stats_lock);
1621         t4_tp_get_tcp_stats(adap, v4, v6);
1622         spin_unlock(&adap->stats_lock);
1623 }
1624 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1625
1626 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1627                       const unsigned int *pgsz_order)
1628 {
1629         struct adapter *adap = netdev2adap(dev);
1630
1631         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1632         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1633                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1634                      HPZ3_V(pgsz_order[3]));
1635 }
1636 EXPORT_SYMBOL(cxgb4_iscsi_init);
1637
1638 int cxgb4_flush_eq_cache(struct net_device *dev)
1639 {
1640         struct adapter *adap = netdev2adap(dev);
1641
1642         return t4_sge_ctxt_flush(adap, adap->mbox);
1643 }
1644 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1645
1646 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1647 {
1648         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1649         __be64 indices;
1650         int ret;
1651
1652         spin_lock(&adap->win0_lock);
1653         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1654                            sizeof(indices), (__be32 *)&indices,
1655                            T4_MEMORY_READ);
1656         spin_unlock(&adap->win0_lock);
1657         if (!ret) {
1658                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1659                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1660         }
1661         return ret;
1662 }
1663
1664 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1665                         u16 size)
1666 {
1667         struct adapter *adap = netdev2adap(dev);
1668         u16 hw_pidx, hw_cidx;
1669         int ret;
1670
1671         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1672         if (ret)
1673                 goto out;
1674
1675         if (pidx != hw_pidx) {
1676                 u16 delta;
1677                 u32 val;
1678
1679                 if (pidx >= hw_pidx)
1680                         delta = pidx - hw_pidx;
1681                 else
1682                         delta = size - hw_pidx + pidx;
1683
1684                 if (is_t4(adap->params.chip))
1685                         val = PIDX_V(delta);
1686                 else
1687                         val = PIDX_T5_V(delta);
1688                 wmb();
1689                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1690                              QID_V(qid) | val);
1691         }
1692 out:
1693         return ret;
1694 }
1695 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1696
1697 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1698 {
1699         struct adapter *adap;
1700         u32 offset, memtype, memaddr;
1701         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1702         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1703         int ret;
1704
1705         adap = netdev2adap(dev);
1706
1707         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1708
1709         /* Figure out where the offset lands in the Memory Type/Address scheme.
1710          * This code assumes that the memory is laid out starting at offset 0
1711          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1712          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1713          * MC0, and some have both MC0 and MC1.
1714          */
1715         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1716         edc0_size = EDRAM0_SIZE_G(size) << 20;
1717         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1718         edc1_size = EDRAM1_SIZE_G(size) << 20;
1719         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1720         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1721
1722         edc0_end = edc0_size;
1723         edc1_end = edc0_end + edc1_size;
1724         mc0_end = edc1_end + mc0_size;
1725
1726         if (offset < edc0_end) {
1727                 memtype = MEM_EDC0;
1728                 memaddr = offset;
1729         } else if (offset < edc1_end) {
1730                 memtype = MEM_EDC1;
1731                 memaddr = offset - edc0_end;
1732         } else {
1733                 if (offset < mc0_end) {
1734                         memtype = MEM_MC0;
1735                         memaddr = offset - edc1_end;
1736                 } else if (is_t5(adap->params.chip)) {
1737                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1738                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1739                         mc1_end = mc0_end + mc1_size;
1740                         if (offset < mc1_end) {
1741                                 memtype = MEM_MC1;
1742                                 memaddr = offset - mc0_end;
1743                         } else {
1744                                 /* offset beyond the end of any memory */
1745                                 goto err;
1746                         }
1747                 } else {
1748                         /* T4/T6 only has a single memory channel */
1749                         goto err;
1750                 }
1751         }
1752
1753         spin_lock(&adap->win0_lock);
1754         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1755         spin_unlock(&adap->win0_lock);
1756         return ret;
1757
1758 err:
1759         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1760                 stag, offset);
1761         return -EINVAL;
1762 }
1763 EXPORT_SYMBOL(cxgb4_read_tpte);
1764
1765 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1766 {
1767         u32 hi, lo;
1768         struct adapter *adap;
1769
1770         adap = netdev2adap(dev);
1771         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1772         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1773
1774         return ((u64)hi << 32) | (u64)lo;
1775 }
1776 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1777
1778 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1779                          unsigned int qid,
1780                          enum cxgb4_bar2_qtype qtype,
1781                          int user,
1782                          u64 *pbar2_qoffset,
1783                          unsigned int *pbar2_qid)
1784 {
1785         return t4_bar2_sge_qregs(netdev2adap(dev),
1786                                  qid,
1787                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1788                                   ? T4_BAR2_QTYPE_EGRESS
1789                                   : T4_BAR2_QTYPE_INGRESS),
1790                                  user,
1791                                  pbar2_qoffset,
1792                                  pbar2_qid);
1793 }
1794 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1795
1796 static struct pci_driver cxgb4_driver;
1797
1798 static void check_neigh_update(struct neighbour *neigh)
1799 {
1800         const struct device *parent;
1801         const struct net_device *netdev = neigh->dev;
1802
1803         if (is_vlan_dev(netdev))
1804                 netdev = vlan_dev_real_dev(netdev);
1805         parent = netdev->dev.parent;
1806         if (parent && parent->driver == &cxgb4_driver.driver)
1807                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1808 }
1809
1810 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1811                        void *data)
1812 {
1813         switch (event) {
1814         case NETEVENT_NEIGH_UPDATE:
1815                 check_neigh_update(data);
1816                 break;
1817         case NETEVENT_REDIRECT:
1818         default:
1819                 break;
1820         }
1821         return 0;
1822 }
1823
1824 static bool netevent_registered;
1825 static struct notifier_block cxgb4_netevent_nb = {
1826         .notifier_call = netevent_cb
1827 };
1828
1829 static void drain_db_fifo(struct adapter *adap, int usecs)
1830 {
1831         u32 v1, v2, lp_count, hp_count;
1832
1833         do {
1834                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1835                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1836                 if (is_t4(adap->params.chip)) {
1837                         lp_count = LP_COUNT_G(v1);
1838                         hp_count = HP_COUNT_G(v1);
1839                 } else {
1840                         lp_count = LP_COUNT_T5_G(v1);
1841                         hp_count = HP_COUNT_T5_G(v2);
1842                 }
1843
1844                 if (lp_count == 0 && hp_count == 0)
1845                         break;
1846                 set_current_state(TASK_UNINTERRUPTIBLE);
1847                 schedule_timeout(usecs_to_jiffies(usecs));
1848         } while (1);
1849 }
1850
1851 static void disable_txq_db(struct sge_txq *q)
1852 {
1853         unsigned long flags;
1854
1855         spin_lock_irqsave(&q->db_lock, flags);
1856         q->db_disabled = 1;
1857         spin_unlock_irqrestore(&q->db_lock, flags);
1858 }
1859
1860 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1861 {
1862         spin_lock_irq(&q->db_lock);
1863         if (q->db_pidx_inc) {
1864                 /* Make sure that all writes to the TX descriptors
1865                  * are committed before we tell HW about them.
1866                  */
1867                 wmb();
1868                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1869                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1870                 q->db_pidx_inc = 0;
1871         }
1872         q->db_disabled = 0;
1873         spin_unlock_irq(&q->db_lock);
1874 }
1875
1876 static void disable_dbs(struct adapter *adap)
1877 {
1878         int i;
1879
1880         for_each_ethrxq(&adap->sge, i)
1881                 disable_txq_db(&adap->sge.ethtxq[i].q);
1882         if (is_offload(adap)) {
1883                 struct sge_uld_txq_info *txq_info =
1884                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1885
1886                 if (txq_info) {
1887                         for_each_ofldtxq(&adap->sge, i) {
1888                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1889
1890                                 disable_txq_db(&txq->q);
1891                         }
1892                 }
1893         }
1894         for_each_port(adap, i)
1895                 disable_txq_db(&adap->sge.ctrlq[i].q);
1896 }
1897
1898 static void enable_dbs(struct adapter *adap)
1899 {
1900         int i;
1901
1902         for_each_ethrxq(&adap->sge, i)
1903                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1904         if (is_offload(adap)) {
1905                 struct sge_uld_txq_info *txq_info =
1906                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1907
1908                 if (txq_info) {
1909                         for_each_ofldtxq(&adap->sge, i) {
1910                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1911
1912                                 enable_txq_db(adap, &txq->q);
1913                         }
1914                 }
1915         }
1916         for_each_port(adap, i)
1917                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1918 }
1919
1920 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1921 {
1922         enum cxgb4_uld type = CXGB4_ULD_RDMA;
1923
1924         if (adap->uld && adap->uld[type].handle)
1925                 adap->uld[type].control(adap->uld[type].handle, cmd);
1926 }
1927
1928 static void process_db_full(struct work_struct *work)
1929 {
1930         struct adapter *adap;
1931
1932         adap = container_of(work, struct adapter, db_full_task);
1933
1934         drain_db_fifo(adap, dbfifo_drain_delay);
1935         enable_dbs(adap);
1936         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
1937         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1938                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1939                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1940                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1941         else
1942                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1943                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
1944 }
1945
1946 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1947 {
1948         u16 hw_pidx, hw_cidx;
1949         int ret;
1950
1951         spin_lock_irq(&q->db_lock);
1952         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
1953         if (ret)
1954                 goto out;
1955         if (q->db_pidx != hw_pidx) {
1956                 u16 delta;
1957                 u32 val;
1958
1959                 if (q->db_pidx >= hw_pidx)
1960                         delta = q->db_pidx - hw_pidx;
1961                 else
1962                         delta = q->size - hw_pidx + q->db_pidx;
1963
1964                 if (is_t4(adap->params.chip))
1965                         val = PIDX_V(delta);
1966                 else
1967                         val = PIDX_T5_V(delta);
1968                 wmb();
1969                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1970                              QID_V(q->cntxt_id) | val);
1971         }
1972 out:
1973         q->db_disabled = 0;
1974         q->db_pidx_inc = 0;
1975         spin_unlock_irq(&q->db_lock);
1976         if (ret)
1977                 CH_WARN(adap, "DB drop recovery failed.\n");
1978 }
1979
1980 static void recover_all_queues(struct adapter *adap)
1981 {
1982         int i;
1983
1984         for_each_ethrxq(&adap->sge, i)
1985                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
1986         if (is_offload(adap)) {
1987                 struct sge_uld_txq_info *txq_info =
1988                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1989                 if (txq_info) {
1990                         for_each_ofldtxq(&adap->sge, i) {
1991                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1992
1993                                 sync_txq_pidx(adap, &txq->q);
1994                         }
1995                 }
1996         }
1997         for_each_port(adap, i)
1998                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
1999 }
2000
2001 static void process_db_drop(struct work_struct *work)
2002 {
2003         struct adapter *adap;
2004
2005         adap = container_of(work, struct adapter, db_drop_task);
2006
2007         if (is_t4(adap->params.chip)) {
2008                 drain_db_fifo(adap, dbfifo_drain_delay);
2009                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2010                 drain_db_fifo(adap, dbfifo_drain_delay);
2011                 recover_all_queues(adap);
2012                 drain_db_fifo(adap, dbfifo_drain_delay);
2013                 enable_dbs(adap);
2014                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2015         } else if (is_t5(adap->params.chip)) {
2016                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2017                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2018                 u16 pidx_inc = dropped_db & 0x1fff;
2019                 u64 bar2_qoffset;
2020                 unsigned int bar2_qid;
2021                 int ret;
2022
2023                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2024                                         0, &bar2_qoffset, &bar2_qid);
2025                 if (ret)
2026                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2027                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2028                 else
2029                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2030                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2031
2032                 /* Re-enable BAR2 WC */
2033                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2034         }
2035
2036         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2037                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2038 }
2039
2040 void t4_db_full(struct adapter *adap)
2041 {
2042         if (is_t4(adap->params.chip)) {
2043                 disable_dbs(adap);
2044                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2045                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2046                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2047                 queue_work(adap->workq, &adap->db_full_task);
2048         }
2049 }
2050
2051 void t4_db_dropped(struct adapter *adap)
2052 {
2053         if (is_t4(adap->params.chip)) {
2054                 disable_dbs(adap);
2055                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2056         }
2057         queue_work(adap->workq, &adap->db_drop_task);
2058 }
2059
2060 void t4_register_netevent_notifier(void)
2061 {
2062         if (!netevent_registered) {
2063                 register_netevent_notifier(&cxgb4_netevent_nb);
2064                 netevent_registered = true;
2065         }
2066 }
2067
2068 static void detach_ulds(struct adapter *adap)
2069 {
2070         unsigned int i;
2071
2072         mutex_lock(&uld_mutex);
2073         list_del(&adap->list_node);
2074         for (i = 0; i < CXGB4_ULD_MAX; i++)
2075                 if (adap->uld && adap->uld[i].handle) {
2076                         adap->uld[i].state_change(adap->uld[i].handle,
2077                                              CXGB4_STATE_DETACH);
2078                         adap->uld[i].handle = NULL;
2079                 }
2080         if (netevent_registered && list_empty(&adapter_list)) {
2081                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2082                 netevent_registered = false;
2083         }
2084         mutex_unlock(&uld_mutex);
2085 }
2086
2087 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2088 {
2089         unsigned int i;
2090
2091         mutex_lock(&uld_mutex);
2092         for (i = 0; i < CXGB4_ULD_MAX; i++)
2093                 if (adap->uld && adap->uld[i].handle)
2094                         adap->uld[i].state_change(adap->uld[i].handle,
2095                                                   new_state);
2096         mutex_unlock(&uld_mutex);
2097 }
2098
2099 #if IS_ENABLED(CONFIG_IPV6)
2100 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2101                                    unsigned long event, void *data)
2102 {
2103         struct inet6_ifaddr *ifa = data;
2104         struct net_device *event_dev = ifa->idev->dev;
2105         const struct device *parent = NULL;
2106 #if IS_ENABLED(CONFIG_BONDING)
2107         struct adapter *adap;
2108 #endif
2109         if (is_vlan_dev(event_dev))
2110                 event_dev = vlan_dev_real_dev(event_dev);
2111 #if IS_ENABLED(CONFIG_BONDING)
2112         if (event_dev->flags & IFF_MASTER) {
2113                 list_for_each_entry(adap, &adapter_list, list_node) {
2114                         switch (event) {
2115                         case NETDEV_UP:
2116                                 cxgb4_clip_get(adap->port[0],
2117                                                (const u32 *)ifa, 1);
2118                                 break;
2119                         case NETDEV_DOWN:
2120                                 cxgb4_clip_release(adap->port[0],
2121                                                    (const u32 *)ifa, 1);
2122                                 break;
2123                         default:
2124                                 break;
2125                         }
2126                 }
2127                 return NOTIFY_OK;
2128         }
2129 #endif
2130
2131         if (event_dev)
2132                 parent = event_dev->dev.parent;
2133
2134         if (parent && parent->driver == &cxgb4_driver.driver) {
2135                 switch (event) {
2136                 case NETDEV_UP:
2137                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2138                         break;
2139                 case NETDEV_DOWN:
2140                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2141                         break;
2142                 default:
2143                         break;
2144                 }
2145         }
2146         return NOTIFY_OK;
2147 }
2148
2149 static bool inet6addr_registered;
2150 static struct notifier_block cxgb4_inet6addr_notifier = {
2151         .notifier_call = cxgb4_inet6addr_handler
2152 };
2153
2154 static void update_clip(const struct adapter *adap)
2155 {
2156         int i;
2157         struct net_device *dev;
2158         int ret;
2159
2160         rcu_read_lock();
2161
2162         for (i = 0; i < MAX_NPORTS; i++) {
2163                 dev = adap->port[i];
2164                 ret = 0;
2165
2166                 if (dev)
2167                         ret = cxgb4_update_root_dev_clip(dev);
2168
2169                 if (ret < 0)
2170                         break;
2171         }
2172         rcu_read_unlock();
2173 }
2174 #endif /* IS_ENABLED(CONFIG_IPV6) */
2175
2176 /**
2177  *      cxgb_up - enable the adapter
2178  *      @adap: adapter being enabled
2179  *
2180  *      Called when the first port is enabled, this function performs the
2181  *      actions necessary to make an adapter operational, such as completing
2182  *      the initialization of HW modules, and enabling interrupts.
2183  *
2184  *      Must be called with the rtnl lock held.
2185  */
2186 static int cxgb_up(struct adapter *adap)
2187 {
2188         int err;
2189
2190         err = setup_sge_queues(adap);
2191         if (err)
2192                 goto out;
2193         err = setup_rss(adap);
2194         if (err)
2195                 goto freeq;
2196
2197         if (adap->flags & USING_MSIX) {
2198                 name_msix_vecs(adap);
2199                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2200                                   adap->msix_info[0].desc, adap);
2201                 if (err)
2202                         goto irq_err;
2203                 err = request_msix_queue_irqs(adap);
2204                 if (err) {
2205                         free_irq(adap->msix_info[0].vec, adap);
2206                         goto irq_err;
2207                 }
2208         } else {
2209                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2210                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2211                                   adap->port[0]->name, adap);
2212                 if (err)
2213                         goto irq_err;
2214         }
2215
2216         mutex_lock(&uld_mutex);
2217         enable_rx(adap);
2218         t4_sge_start(adap);
2219         t4_intr_enable(adap);
2220         adap->flags |= FULL_INIT_DONE;
2221         mutex_unlock(&uld_mutex);
2222
2223         notify_ulds(adap, CXGB4_STATE_UP);
2224 #if IS_ENABLED(CONFIG_IPV6)
2225         update_clip(adap);
2226 #endif
2227         /* Initialize hash mac addr list*/
2228         INIT_LIST_HEAD(&adap->mac_hlist);
2229  out:
2230         return err;
2231  irq_err:
2232         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2233  freeq:
2234         t4_free_sge_resources(adap);
2235         goto out;
2236 }
2237
2238 static void cxgb_down(struct adapter *adapter)
2239 {
2240         cancel_work_sync(&adapter->tid_release_task);
2241         cancel_work_sync(&adapter->db_full_task);
2242         cancel_work_sync(&adapter->db_drop_task);
2243         adapter->tid_release_task_busy = false;
2244         adapter->tid_release_head = NULL;
2245
2246         t4_sge_stop(adapter);
2247         t4_free_sge_resources(adapter);
2248         adapter->flags &= ~FULL_INIT_DONE;
2249 }
2250
2251 /*
2252  * net_device operations
2253  */
2254 static int cxgb_open(struct net_device *dev)
2255 {
2256         int err;
2257         struct port_info *pi = netdev_priv(dev);
2258         struct adapter *adapter = pi->adapter;
2259
2260         netif_carrier_off(dev);
2261
2262         if (!(adapter->flags & FULL_INIT_DONE)) {
2263                 err = cxgb_up(adapter);
2264                 if (err < 0)
2265                         return err;
2266         }
2267
2268         /* It's possible that the basic port information could have
2269          * changed since we first read it.
2270          */
2271         err = t4_update_port_info(pi);
2272         if (err < 0)
2273                 return err;
2274
2275         err = link_start(dev);
2276         if (!err)
2277                 netif_tx_start_all_queues(dev);
2278         return err;
2279 }
2280
2281 static int cxgb_close(struct net_device *dev)
2282 {
2283         struct port_info *pi = netdev_priv(dev);
2284         struct adapter *adapter = pi->adapter;
2285
2286         netif_tx_stop_all_queues(dev);
2287         netif_carrier_off(dev);
2288         return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2289 }
2290
2291 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2292                 __be32 sip, __be16 sport, __be16 vlan,
2293                 unsigned int queue, unsigned char port, unsigned char mask)
2294 {
2295         int ret;
2296         struct filter_entry *f;
2297         struct adapter *adap;
2298         int i;
2299         u8 *val;
2300
2301         adap = netdev2adap(dev);
2302
2303         /* Adjust stid to correct filter index */
2304         stid -= adap->tids.sftid_base;
2305         stid += adap->tids.nftids;
2306
2307         /* Check to make sure the filter requested is writable ...
2308          */
2309         f = &adap->tids.ftid_tab[stid];
2310         ret = writable_filter(f);
2311         if (ret)
2312                 return ret;
2313
2314         /* Clear out any old resources being used by the filter before
2315          * we start constructing the new filter.
2316          */
2317         if (f->valid)
2318                 clear_filter(adap, f);
2319
2320         /* Clear out filter specifications */
2321         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2322         f->fs.val.lport = cpu_to_be16(sport);
2323         f->fs.mask.lport  = ~0;
2324         val = (u8 *)&sip;
2325         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2326                 for (i = 0; i < 4; i++) {
2327                         f->fs.val.lip[i] = val[i];
2328                         f->fs.mask.lip[i] = ~0;
2329                 }
2330                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2331                         f->fs.val.iport = port;
2332                         f->fs.mask.iport = mask;
2333                 }
2334         }
2335
2336         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2337                 f->fs.val.proto = IPPROTO_TCP;
2338                 f->fs.mask.proto = ~0;
2339         }
2340
2341         f->fs.dirsteer = 1;
2342         f->fs.iq = queue;
2343         /* Mark filter as locked */
2344         f->locked = 1;
2345         f->fs.rpttid = 1;
2346
2347         /* Save the actual tid. We need this to get the corresponding
2348          * filter entry structure in filter_rpl.
2349          */
2350         f->tid = stid + adap->tids.ftid_base;
2351         ret = set_filter_wr(adap, stid);
2352         if (ret) {
2353                 clear_filter(adap, f);
2354                 return ret;
2355         }
2356
2357         return 0;
2358 }
2359 EXPORT_SYMBOL(cxgb4_create_server_filter);
2360
2361 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2362                 unsigned int queue, bool ipv6)
2363 {
2364         struct filter_entry *f;
2365         struct adapter *adap;
2366
2367         adap = netdev2adap(dev);
2368
2369         /* Adjust stid to correct filter index */
2370         stid -= adap->tids.sftid_base;
2371         stid += adap->tids.nftids;
2372
2373         f = &adap->tids.ftid_tab[stid];
2374         /* Unlock the filter */
2375         f->locked = 0;
2376
2377         return delete_filter(adap, stid);
2378 }
2379 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2380
2381 static void cxgb_get_stats(struct net_device *dev,
2382                            struct rtnl_link_stats64 *ns)
2383 {
2384         struct port_stats stats;
2385         struct port_info *p = netdev_priv(dev);
2386         struct adapter *adapter = p->adapter;
2387
2388         /* Block retrieving statistics during EEH error
2389          * recovery. Otherwise, the recovery might fail
2390          * and the PCI device will be removed permanently
2391          */
2392         spin_lock(&adapter->stats_lock);
2393         if (!netif_device_present(dev)) {
2394                 spin_unlock(&adapter->stats_lock);
2395                 return;
2396         }
2397         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2398                                  &p->stats_base);
2399         spin_unlock(&adapter->stats_lock);
2400
2401         ns->tx_bytes   = stats.tx_octets;
2402         ns->tx_packets = stats.tx_frames;
2403         ns->rx_bytes   = stats.rx_octets;
2404         ns->rx_packets = stats.rx_frames;
2405         ns->multicast  = stats.rx_mcast_frames;
2406
2407         /* detailed rx_errors */
2408         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2409                                stats.rx_runt;
2410         ns->rx_over_errors   = 0;
2411         ns->rx_crc_errors    = stats.rx_fcs_err;
2412         ns->rx_frame_errors  = stats.rx_symbol_err;
2413         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2414                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2415                                stats.rx_trunc0 + stats.rx_trunc1 +
2416                                stats.rx_trunc2 + stats.rx_trunc3;
2417         ns->rx_missed_errors = 0;
2418
2419         /* detailed tx_errors */
2420         ns->tx_aborted_errors   = 0;
2421         ns->tx_carrier_errors   = 0;
2422         ns->tx_fifo_errors      = 0;
2423         ns->tx_heartbeat_errors = 0;
2424         ns->tx_window_errors    = 0;
2425
2426         ns->tx_errors = stats.tx_error_frames;
2427         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2428                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2429 }
2430
2431 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2432 {
2433         unsigned int mbox;
2434         int ret = 0, prtad, devad;
2435         struct port_info *pi = netdev_priv(dev);
2436         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2437
2438         switch (cmd) {
2439         case SIOCGMIIPHY:
2440                 if (pi->mdio_addr < 0)
2441                         return -EOPNOTSUPP;
2442                 data->phy_id = pi->mdio_addr;
2443                 break;
2444         case SIOCGMIIREG:
2445         case SIOCSMIIREG:
2446                 if (mdio_phy_id_is_c45(data->phy_id)) {
2447                         prtad = mdio_phy_id_prtad(data->phy_id);
2448                         devad = mdio_phy_id_devad(data->phy_id);
2449                 } else if (data->phy_id < 32) {
2450                         prtad = data->phy_id;
2451                         devad = 0;
2452                         data->reg_num &= 0x1f;
2453                 } else
2454                         return -EINVAL;
2455
2456                 mbox = pi->adapter->pf;
2457                 if (cmd == SIOCGMIIREG)
2458                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2459                                          data->reg_num, &data->val_out);
2460                 else
2461                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2462                                          data->reg_num, data->val_in);
2463                 break;
2464         case SIOCGHWTSTAMP:
2465                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2466                                     sizeof(pi->tstamp_config)) ?
2467                         -EFAULT : 0;
2468         case SIOCSHWTSTAMP:
2469                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2470                                    sizeof(pi->tstamp_config)))
2471                         return -EFAULT;
2472
2473                 switch (pi->tstamp_config.rx_filter) {
2474                 case HWTSTAMP_FILTER_NONE:
2475                         pi->rxtstamp = false;
2476                         break;
2477                 case HWTSTAMP_FILTER_ALL:
2478                         pi->rxtstamp = true;
2479                         break;
2480                 default:
2481                         pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2482                         return -ERANGE;
2483                 }
2484
2485                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2486                                     sizeof(pi->tstamp_config)) ?
2487                         -EFAULT : 0;
2488         default:
2489                 return -EOPNOTSUPP;
2490         }
2491         return ret;
2492 }
2493
2494 static void cxgb_set_rxmode(struct net_device *dev)
2495 {
2496         /* unfortunately we can't return errors to the stack */
2497         set_rxmode(dev, -1, false);
2498 }
2499
2500 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2501 {
2502         int ret;
2503         struct port_info *pi = netdev_priv(dev);
2504
2505         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2506                             -1, -1, -1, true);
2507         if (!ret)
2508                 dev->mtu = new_mtu;
2509         return ret;
2510 }
2511
2512 #ifdef CONFIG_PCI_IOV
2513 static int dummy_open(struct net_device *dev)
2514 {
2515         /* Turn carrier off since we don't have to transmit anything on this
2516          * interface.
2517          */
2518         netif_carrier_off(dev);
2519         return 0;
2520 }
2521
2522 /* Fill MAC address that will be assigned by the FW */
2523 static void fill_vf_station_mac_addr(struct adapter *adap)
2524 {
2525         unsigned int i;
2526         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2527         int err;
2528         u8 *na;
2529         u16 a, b;
2530
2531         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2532         if (!err) {
2533                 na = adap->params.vpd.na;
2534                 for (i = 0; i < ETH_ALEN; i++)
2535                         hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2536                                       hex2val(na[2 * i + 1]));
2537                 a = (hw_addr[0] << 8) | hw_addr[1];
2538                 b = (hw_addr[1] << 8) | hw_addr[2];
2539                 a ^= b;
2540                 a |= 0x0200;    /* locally assigned Ethernet MAC address */
2541                 a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2542                 macaddr[0] = a >> 8;
2543                 macaddr[1] = a & 0xff;
2544
2545                 for (i = 2; i < 5; i++)
2546                         macaddr[i] = hw_addr[i + 1];
2547
2548                 for (i = 0; i < adap->num_vfs; i++) {
2549                         macaddr[5] = adap->pf * 16 + i;
2550                         ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr);
2551                 }
2552         }
2553 }
2554
2555 static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2556 {
2557         struct port_info *pi = netdev_priv(dev);
2558         struct adapter *adap = pi->adapter;
2559         int ret;
2560
2561         /* verify MAC addr is valid */
2562         if (!is_valid_ether_addr(mac)) {
2563                 dev_err(pi->adapter->pdev_dev,
2564                         "Invalid Ethernet address %pM for VF %d\n",
2565                         mac, vf);
2566                 return -EINVAL;
2567         }
2568
2569         dev_info(pi->adapter->pdev_dev,
2570                  "Setting MAC %pM on VF %d\n", mac, vf);
2571         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2572         if (!ret)
2573                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2574         return ret;
2575 }
2576
2577 static int cxgb_get_vf_config(struct net_device *dev,
2578                               int vf, struct ifla_vf_info *ivi)
2579 {
2580         struct port_info *pi = netdev_priv(dev);
2581         struct adapter *adap = pi->adapter;
2582
2583         if (vf >= adap->num_vfs)
2584                 return -EINVAL;
2585         ivi->vf = vf;
2586         ivi->max_tx_rate = adap->vfinfo[vf].tx_rate;
2587         ivi->min_tx_rate = 0;
2588         ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
2589         return 0;
2590 }
2591
2592 static int cxgb_get_phys_port_id(struct net_device *dev,
2593                                  struct netdev_phys_item_id *ppid)
2594 {
2595         struct port_info *pi = netdev_priv(dev);
2596         unsigned int phy_port_id;
2597
2598         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2599         ppid->id_len = sizeof(phy_port_id);
2600         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2601         return 0;
2602 }
2603
2604 static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2605                             int max_tx_rate)
2606 {
2607         struct port_info *pi = netdev_priv(dev);
2608         struct adapter *adap = pi->adapter;
2609         struct fw_port_cmd port_cmd, port_rpl;
2610         u32 link_status, speed = 0;
2611         u32 fw_pfvf, fw_class;
2612         int class_id = vf;
2613         int link_ok, ret;
2614         u16 pktsize;
2615
2616         if (vf >= adap->num_vfs)
2617                 return -EINVAL;
2618
2619         if (min_tx_rate) {
2620                 dev_err(adap->pdev_dev,
2621                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2622                         min_tx_rate, vf);
2623                 return -EINVAL;
2624         }
2625         /* Retrieve link details for VF port */
2626         memset(&port_cmd, 0, sizeof(port_cmd));
2627         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
2628                                             FW_CMD_REQUEST_F |
2629                                             FW_CMD_READ_F |
2630                                             FW_PORT_CMD_PORTID_V(pi->port_id));
2631         port_cmd.action_to_len16 =
2632                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
2633                             FW_LEN16(port_cmd));
2634         ret = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
2635                          &port_rpl);
2636         if (ret != FW_SUCCESS) {
2637                 dev_err(adap->pdev_dev,
2638                         "Failed to get link status for VF %d\n", vf);
2639                 return -EINVAL;
2640         }
2641         link_status = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype);
2642         link_ok = (link_status & FW_PORT_CMD_LSTATUS_F) != 0;
2643         if (!link_ok) {
2644                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2645                 return -EINVAL;
2646         }
2647         /* Determine link speed */
2648         if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
2649                 speed = 100;
2650         else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
2651                 speed = 1000;
2652         else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
2653                 speed = 10000;
2654         else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
2655                 speed = 25000;
2656         else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
2657                 speed = 40000;
2658         else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
2659                 speed = 100000;
2660
2661         if (max_tx_rate > speed) {
2662                 dev_err(adap->pdev_dev,
2663                         "Max tx rate %d for VF %d can't be > link-speed %u",
2664                         max_tx_rate, vf, speed);
2665                 return -EINVAL;
2666         }
2667         pktsize = be16_to_cpu(port_rpl.u.info.mtu);
2668         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2669         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2670         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2671         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2672         /* configure Traffic Class for rate-limiting */
2673         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2674                               SCHED_CLASS_LEVEL_CL_RL,
2675                               SCHED_CLASS_MODE_CLASS,
2676                               SCHED_CLASS_RATEUNIT_BITS,
2677                               SCHED_CLASS_RATEMODE_ABS,
2678                               pi->port_id, class_id, 0,
2679                               max_tx_rate * 1000, 0, pktsize);
2680         if (ret) {
2681                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2682                         ret);
2683                 return -EINVAL;
2684         }
2685         dev_info(adap->pdev_dev,
2686                  "Class %d with MSS %u configured with rate %u\n",
2687                  class_id, pktsize, max_tx_rate);
2688
2689         /* bind VF to configured Traffic Class */
2690         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2691                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2692         fw_class = class_id;
2693         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2694                             &fw_class);
2695         if (ret) {
2696                 dev_err(adap->pdev_dev,
2697                         "Err %d in binding VF %d to Traffic Class %d\n",
2698                         ret, vf, class_id);
2699                 return -EINVAL;
2700         }
2701         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2702                  adap->pf, vf, class_id);
2703         adap->vfinfo[vf].tx_rate = max_tx_rate;
2704         return 0;
2705 }
2706
2707 #endif
2708
2709 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2710 {
2711         int ret;
2712         struct sockaddr *addr = p;
2713         struct port_info *pi = netdev_priv(dev);
2714
2715         if (!is_valid_ether_addr(addr->sa_data))
2716                 return -EADDRNOTAVAIL;
2717
2718         ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
2719                             pi->xact_addr_filt, addr->sa_data, true, true);
2720         if (ret < 0)
2721                 return ret;
2722
2723         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2724         pi->xact_addr_filt = ret;
2725         return 0;
2726 }
2727
2728 #ifdef CONFIG_NET_POLL_CONTROLLER
2729 static void cxgb_netpoll(struct net_device *dev)
2730 {
2731         struct port_info *pi = netdev_priv(dev);
2732         struct adapter *adap = pi->adapter;
2733
2734         if (adap->flags & USING_MSIX) {
2735                 int i;
2736                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2737
2738                 for (i = pi->nqsets; i; i--, rx++)
2739                         t4_sge_intr_msix(0, &rx->rspq);
2740         } else
2741                 t4_intr_handler(adap)(0, adap);
2742 }
2743 #endif
2744
2745 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2746 {
2747         struct port_info *pi = netdev_priv(dev);
2748         struct adapter *adap = pi->adapter;
2749         struct sched_class *e;
2750         struct ch_sched_params p;
2751         struct ch_sched_queue qe;
2752         u32 req_rate;
2753         int err = 0;
2754
2755         if (!can_sched(dev))
2756                 return -ENOTSUPP;
2757
2758         if (index < 0 || index > pi->nqsets - 1)
2759                 return -EINVAL;
2760
2761         if (!(adap->flags & FULL_INIT_DONE)) {
2762                 dev_err(adap->pdev_dev,
2763                         "Failed to rate limit on queue %d. Link Down?\n",
2764                         index);
2765                 return -EINVAL;
2766         }
2767
2768         /* Convert from Mbps to Kbps */
2769         req_rate = rate << 10;
2770
2771         /* Max rate is 10 Gbps */
2772         if (req_rate >= SCHED_MAX_RATE_KBPS) {
2773                 dev_err(adap->pdev_dev,
2774                         "Invalid rate %u Mbps, Max rate is %u Gbps\n",
2775                         rate, SCHED_MAX_RATE_KBPS);
2776                 return -ERANGE;
2777         }
2778
2779         /* First unbind the queue from any existing class */
2780         memset(&qe, 0, sizeof(qe));
2781         qe.queue = index;
2782         qe.class = SCHED_CLS_NONE;
2783
2784         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2785         if (err) {
2786                 dev_err(adap->pdev_dev,
2787                         "Unbinding Queue %d on port %d fail. Err: %d\n",
2788                         index, pi->port_id, err);
2789                 return err;
2790         }
2791
2792         /* Queue already unbound */
2793         if (!req_rate)
2794                 return 0;
2795
2796         /* Fetch any available unused or matching scheduling class */
2797         memset(&p, 0, sizeof(p));
2798         p.type = SCHED_CLASS_TYPE_PACKET;
2799         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
2800         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
2801         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2802         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2803         p.u.params.channel  = pi->tx_chan;
2804         p.u.params.class    = SCHED_CLS_NONE;
2805         p.u.params.minrate  = 0;
2806         p.u.params.maxrate  = req_rate;
2807         p.u.params.weight   = 0;
2808         p.u.params.pktsize  = dev->mtu;
2809
2810         e = cxgb4_sched_class_alloc(dev, &p);
2811         if (!e)
2812                 return -ENOMEM;
2813
2814         /* Bind the queue to a scheduling class */
2815         memset(&qe, 0, sizeof(qe));
2816         qe.queue = index;
2817         qe.class = e->idx;
2818
2819         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2820         if (err)
2821                 dev_err(adap->pdev_dev,
2822                         "Queue rate limiting failed. Err: %d\n", err);
2823         return err;
2824 }
2825
2826 static int cxgb_setup_tc(struct net_device *dev, u32 handle, u32 chain_index,
2827                          __be16 proto, struct tc_to_netdev *tc)
2828 {
2829         struct port_info *pi = netdev2pinfo(dev);
2830         struct adapter *adap = netdev2adap(dev);
2831
2832         if (chain_index)
2833                 return -EOPNOTSUPP;
2834
2835         if (!(adap->flags & FULL_INIT_DONE)) {
2836                 dev_err(adap->pdev_dev,
2837                         "Failed to setup tc on port %d. Link Down?\n",
2838                         pi->port_id);
2839                 return -EINVAL;
2840         }
2841
2842         if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
2843             tc->type == TC_SETUP_CLSU32) {
2844                 switch (tc->cls_u32->command) {
2845                 case TC_CLSU32_NEW_KNODE:
2846                 case TC_CLSU32_REPLACE_KNODE:
2847                         return cxgb4_config_knode(dev, proto, tc->cls_u32);
2848                 case TC_CLSU32_DELETE_KNODE:
2849                         return cxgb4_delete_knode(dev, proto, tc->cls_u32);
2850                 default:
2851                         return -EOPNOTSUPP;
2852                 }
2853         }
2854
2855         return -EOPNOTSUPP;
2856 }
2857
2858 static netdev_features_t cxgb_fix_features(struct net_device *dev,
2859                                            netdev_features_t features)
2860 {
2861         /* Disable GRO, if RX_CSUM is disabled */
2862         if (!(features & NETIF_F_RXCSUM))
2863                 features &= ~NETIF_F_GRO;
2864
2865         return features;
2866 }
2867
2868 static const struct net_device_ops cxgb4_netdev_ops = {
2869         .ndo_open             = cxgb_open,
2870         .ndo_stop             = cxgb_close,
2871         .ndo_start_xmit       = t4_eth_xmit,
2872         .ndo_select_queue     = cxgb_select_queue,
2873         .ndo_get_stats64      = cxgb_get_stats,
2874         .ndo_set_rx_mode      = cxgb_set_rxmode,
2875         .ndo_set_mac_address  = cxgb_set_mac_addr,
2876         .ndo_set_features     = cxgb_set_features,
2877         .ndo_validate_addr    = eth_validate_addr,
2878         .ndo_do_ioctl         = cxgb_ioctl,
2879         .ndo_change_mtu       = cxgb_change_mtu,
2880 #ifdef CONFIG_NET_POLL_CONTROLLER
2881         .ndo_poll_controller  = cxgb_netpoll,
2882 #endif
2883 #ifdef CONFIG_CHELSIO_T4_FCOE
2884         .ndo_fcoe_enable      = cxgb_fcoe_enable,
2885         .ndo_fcoe_disable     = cxgb_fcoe_disable,
2886 #endif /* CONFIG_CHELSIO_T4_FCOE */
2887         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
2888         .ndo_setup_tc         = cxgb_setup_tc,
2889         .ndo_fix_features     = cxgb_fix_features,
2890 };
2891
2892 #ifdef CONFIG_PCI_IOV
2893 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
2894         .ndo_open             = dummy_open,
2895         .ndo_set_vf_mac       = cxgb_set_vf_mac,
2896         .ndo_get_vf_config    = cxgb_get_vf_config,
2897         .ndo_set_vf_rate      = cxgb_set_vf_rate,
2898         .ndo_get_phys_port_id = cxgb_get_phys_port_id,
2899 };
2900 #endif
2901
2902 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2903 {
2904         struct adapter *adapter = netdev2adap(dev);
2905
2906         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
2907         strlcpy(info->version, cxgb4_driver_version,
2908                 sizeof(info->version));
2909         strlcpy(info->bus_info, pci_name(adapter->pdev),
2910                 sizeof(info->bus_info));
2911 }
2912
2913 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
2914         .get_drvinfo       = get_drvinfo,
2915 };
2916
2917 void t4_fatal_err(struct adapter *adap)
2918 {
2919         int port;
2920
2921         if (pci_channel_offline(adap->pdev))
2922                 return;
2923
2924         /* Disable the SGE since ULDs are going to free resources that
2925          * could be exposed to the adapter.  RDMA MWs for example...
2926          */
2927         t4_shutdown_adapter(adap);
2928         for_each_port(adap, port) {
2929                 struct net_device *dev = adap->port[port];
2930
2931                 /* If we get here in very early initialization the network
2932                  * devices may not have been set up yet.
2933                  */
2934                 if (!dev)
2935                         continue;
2936
2937                 netif_tx_stop_all_queues(dev);
2938                 netif_carrier_off(dev);
2939         }
2940         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
2941 }
2942
2943 static void setup_memwin(struct adapter *adap)
2944 {
2945         u32 nic_win_base = t4_get_util_window(adap);
2946
2947         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
2948 }
2949
2950 static void setup_memwin_rdma(struct adapter *adap)
2951 {
2952         if (adap->vres.ocq.size) {
2953                 u32 start;
2954                 unsigned int sz_kb;
2955
2956                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
2957                 start &= PCI_BASE_ADDRESS_MEM_MASK;
2958                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
2959                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
2960                 t4_write_reg(adap,
2961                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
2962                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
2963                 t4_write_reg(adap,
2964                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
2965                              adap->vres.ocq.start);
2966                 t4_read_reg(adap,
2967                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
2968         }
2969 }
2970
2971 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
2972 {
2973         u32 v;
2974         int ret;
2975
2976         /* get device capabilities */
2977         memset(c, 0, sizeof(*c));
2978         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2979                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
2980         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
2981         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
2982         if (ret < 0)
2983                 return ret;
2984
2985         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2986                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
2987         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
2988         if (ret < 0)
2989                 return ret;
2990
2991         ret = t4_config_glbl_rss(adap, adap->pf,
2992                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
2993                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
2994                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
2995         if (ret < 0)
2996                 return ret;
2997
2998         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
2999                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3000                           FW_CMD_CAP_PF);
3001         if (ret < 0)
3002                 return ret;
3003
3004         t4_sge_init(adap);
3005
3006         /* tweak some settings */
3007         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3008         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3009         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3010         v = t4_read_reg(adap, TP_PIO_DATA_A);
3011         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3012
3013         /* first 4 Tx modulation queues point to consecutive Tx channels */
3014         adap->params.tp.tx_modq_map = 0xE4;
3015         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3016                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3017
3018         /* associate each Tx modulation queue with consecutive Tx channels */
3019         v = 0x84218421;
3020         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3021                           &v, 1, TP_TX_SCHED_HDR_A);
3022         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3023                           &v, 1, TP_TX_SCHED_FIFO_A);
3024         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3025                           &v, 1, TP_TX_SCHED_PCMD_A);
3026
3027 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3028         if (is_offload(adap)) {
3029                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3030                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3031                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3032                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3033                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3034                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3035                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3036                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3037                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3038                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3039         }
3040
3041         /* get basic stuff going */
3042         return t4_early_init(adap, adap->pf);
3043 }
3044
3045 /*
3046  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3047  */
3048 #define MAX_ATIDS 8192U
3049
3050 /*
3051  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3052  *
3053  * If the firmware we're dealing with has Configuration File support, then
3054  * we use that to perform all configuration
3055  */
3056
3057 /*
3058  * Tweak configuration based on module parameters, etc.  Most of these have
3059  * defaults assigned to them by Firmware Configuration Files (if we're using
3060  * them) but need to be explicitly set if we're using hard-coded
3061  * initialization.  But even in the case of using Firmware Configuration
3062  * Files, we'd like to expose the ability to change these via module
3063  * parameters so these are essentially common tweaks/settings for
3064  * Configuration Files and hard-coded initialization ...
3065  */
3066 static int adap_init0_tweaks(struct adapter *adapter)
3067 {
3068         /*
3069          * Fix up various Host-Dependent Parameters like Page Size, Cache
3070          * Line Size, etc.  The firmware default is for a 4KB Page Size and
3071          * 64B Cache Line Size ...
3072          */
3073         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3074
3075         /*
3076          * Process module parameters which affect early initialization.
3077          */
3078         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3079                 dev_err(&adapter->pdev->dev,
3080                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
3081                         rx_dma_offset);
3082                 rx_dma_offset = 2;
3083         }
3084         t4_set_reg_field(adapter, SGE_CONTROL_A,
3085                          PKTSHIFT_V(PKTSHIFT_M),
3086                          PKTSHIFT_V(rx_dma_offset));
3087
3088         /*
3089          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3090          * adds the pseudo header itself.
3091          */
3092         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3093                                CSUM_HAS_PSEUDO_HDR_F, 0);
3094
3095         return 0;
3096 }
3097
3098 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3099  * unto themselves and they contain their own firmware to perform their
3100  * tasks ...
3101  */
3102 static int phy_aq1202_version(const u8 *phy_fw_data,
3103                               size_t phy_fw_size)
3104 {
3105         int offset;
3106
3107         /* At offset 0x8 you're looking for the primary image's
3108          * starting offset which is 3 Bytes wide
3109          *
3110          * At offset 0xa of the primary image, you look for the offset
3111          * of the DRAM segment which is 3 Bytes wide.
3112          *
3113          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3114          * wide
3115          */
3116         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3117         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3118         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3119
3120         offset = le24(phy_fw_data + 0x8) << 12;
3121         offset = le24(phy_fw_data + offset + 0xa);
3122         return be16(phy_fw_data + offset + 0x27e);
3123
3124         #undef be16
3125         #undef le16
3126         #undef le24
3127 }
3128
3129 static struct info_10gbt_phy_fw {
3130         unsigned int phy_fw_id;         /* PCI Device ID */
3131         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
3132         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3133         int phy_flash;                  /* Has FLASH for PHY Firmware */
3134 } phy_info_array[] = {
3135         {
3136                 PHY_AQ1202_DEVICEID,
3137                 PHY_AQ1202_FIRMWARE,
3138                 phy_aq1202_version,
3139                 1,
3140         },
3141         {
3142                 PHY_BCM84834_DEVICEID,
3143                 PHY_BCM84834_FIRMWARE,
3144                 NULL,
3145                 0,
3146         },
3147         { 0, NULL, NULL },
3148 };
3149
3150 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3151 {
3152         int i;
3153
3154         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3155                 if (phy_info_array[i].phy_fw_id == devid)
3156                         return &phy_info_array[i];
3157         }
3158         return NULL;
3159 }
3160
3161 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
3162  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
3163  * we return a negative error number.  If we transfer new firmware we return 1
3164  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
3165  */
3166 static int adap_init0_phy(struct adapter *adap)
3167 {
3168         const struct firmware *phyf;
3169         int ret;
3170         struct info_10gbt_phy_fw *phy_info;
3171
3172         /* Use the device ID to determine which PHY file to flash.
3173          */
3174         phy_info = find_phy_info(adap->pdev->device);
3175         if (!phy_info) {
3176                 dev_warn(adap->pdev_dev,
3177                          "No PHY Firmware file found for this PHY\n");
3178                 return -EOPNOTSUPP;
3179         }
3180
3181         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3182          * use that. The adapter firmware provides us with a memory buffer
3183          * where we can load a PHY firmware file from the host if we want to
3184          * override the PHY firmware File in flash.
3185          */
3186         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3187                                       adap->pdev_dev);
3188         if (ret < 0) {
3189                 /* For adapters without FLASH attached to PHY for their
3190                  * firmware, it's obviously a fatal error if we can't get the
3191                  * firmware to the adapter.  For adapters with PHY firmware
3192                  * FLASH storage, it's worth a warning if we can't find the
3193                  * PHY Firmware but we'll neuter the error ...
3194                  */
3195                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3196                         "/lib/firmware/%s, error %d\n",
3197                         phy_info->phy_fw_file, -ret);
3198                 if (phy_info->phy_flash) {
3199                         int cur_phy_fw_ver = 0;
3200
3201                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3202                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3203                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
3204                         ret = 0;
3205                 }
3206
3207                 return ret;
3208         }
3209
3210         /* Load PHY Firmware onto adapter.
3211          */
3212         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3213                              phy_info->phy_fw_version,
3214                              (u8 *)phyf->data, phyf->size);
3215         if (ret < 0)
3216                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3217                         -ret);
3218         else if (ret > 0) {
3219                 int new_phy_fw_ver = 0;
3220
3221                 if (phy_info->phy_fw_version)
3222                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3223                                                                   phyf->size);
3224                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3225                          "Firmware /lib/firmware/%s, version %#x\n",
3226                          phy_info->phy_fw_file, new_phy_fw_ver);
3227         }
3228
3229         release_firmware(phyf);
3230
3231         return ret;
3232 }
3233
3234 /*
3235  * Attempt to initialize the adapter via a Firmware Configuration File.
3236  */
3237 static int adap_init0_config(struct adapter *adapter, int reset)
3238 {
3239         struct fw_caps_config_cmd caps_cmd;
3240         const struct firmware *cf;
3241         unsigned long mtype = 0, maddr = 0;
3242         u32 finiver, finicsum, cfcsum;
3243         int ret;
3244         int config_issued = 0;
3245         char *fw_config_file, fw_config_file_path[256];
3246         char *config_name = NULL;
3247
3248         /*
3249          * Reset device if necessary.
3250          */
3251         if (reset) {
3252                 ret = t4_fw_reset(adapter, adapter->mbox,
3253                                   PIORSTMODE_F | PIORST_F);
3254                 if (ret < 0)
3255                         goto bye;
3256         }
3257
3258         /* If this is a 10Gb/s-BT adapter make sure the chip-external
3259          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
3260          * to be performed after any global adapter RESET above since some
3261          * PHYs only have local RAM copies of the PHY firmware.
3262          */
3263         if (is_10gbt_device(adapter->pdev->device)) {
3264                 ret = adap_init0_phy(adapter);
3265                 if (ret < 0)
3266                         goto bye;
3267         }
3268         /*
3269          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3270          * then use that.  Otherwise, use the configuration file stored
3271          * in the adapter flash ...
3272          */
3273         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3274         case CHELSIO_T4:
3275                 fw_config_file = FW4_CFNAME;
3276                 break;
3277         case CHELSIO_T5:
3278                 fw_config_file = FW5_CFNAME;
3279                 break;
3280         case CHELSIO_T6:
3281                 fw_config_file = FW6_CFNAME;
3282                 break;
3283         default:
3284                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3285                        adapter->pdev->device);
3286                 ret = -EINVAL;
3287                 goto bye;
3288         }
3289
3290         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3291         if (ret < 0) {
3292                 config_name = "On FLASH";
3293                 mtype = FW_MEMTYPE_CF_FLASH;
3294                 maddr = t4_flash_cfg_addr(adapter);
3295         } else {
3296                 u32 params[7], val[7];
3297
3298                 sprintf(fw_config_file_path,
3299                         "/lib/firmware/%s", fw_config_file);
3300                 config_name = fw_config_file_path;
3301
3302                 if (cf->size >= FLASH_CFG_MAX_SIZE)
3303                         ret = -ENOMEM;
3304                 else {
3305                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3306                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3307                         ret = t4_query_params(adapter, adapter->mbox,
3308                                               adapter->pf, 0, 1, params, val);
3309                         if (ret == 0) {
3310                                 /*
3311                                  * For t4_memory_rw() below addresses and
3312                                  * sizes have to be in terms of multiples of 4
3313                                  * bytes.  So, if the Configuration File isn't
3314                                  * a multiple of 4 bytes in length we'll have
3315                                  * to write that out separately since we can't
3316                                  * guarantee that the bytes following the
3317                                  * residual byte in the buffer returned by
3318                                  * request_firmware() are zeroed out ...
3319                                  */
3320                                 size_t resid = cf->size & 0x3;
3321                                 size_t size = cf->size & ~0x3;
3322                                 __be32 *data = (__be32 *)cf->data;
3323
3324                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3325                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3326
3327                                 spin_lock(&adapter->win0_lock);
3328                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3329                                                    size, data, T4_MEMORY_WRITE);
3330                                 if (ret == 0 && resid != 0) {
3331                                         union {
3332                                                 __be32 word;
3333                                                 char buf[4];
3334                                         } last;
3335                                         int i;
3336
3337                                         last.word = data[size >> 2];
3338                                         for (i = resid; i < 4; i++)
3339                                                 last.buf[i] = 0;
3340                                         ret = t4_memory_rw(adapter, 0, mtype,
3341                                                            maddr + size,
3342                                                            4, &last.word,
3343                                                            T4_MEMORY_WRITE);
3344                                 }
3345                                 spin_unlock(&adapter->win0_lock);
3346                         }
3347                 }
3348
3349                 release_firmware(cf);
3350                 if (ret)
3351                         goto bye;
3352         }
3353
3354         /*
3355          * Issue a Capability Configuration command to the firmware to get it
3356          * to parse the Configuration File.  We don't use t4_fw_config_file()
3357          * because we want the ability to modify various features after we've
3358          * processed the configuration file ...
3359          */
3360         memset(&caps_cmd, 0, sizeof(caps_cmd));
3361         caps_cmd.op_to_write =
3362                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3363                       FW_CMD_REQUEST_F |
3364                       FW_CMD_READ_F);
3365         caps_cmd.cfvalid_to_len16 =
3366                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3367                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3368                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3369                       FW_LEN16(caps_cmd));
3370         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3371                          &caps_cmd);
3372
3373         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3374          * Configuration File in FLASH), our last gasp effort is to use the
3375          * Firmware Configuration File which is embedded in the firmware.  A
3376          * very few early versions of the firmware didn't have one embedded
3377          * but we can ignore those.
3378          */
3379         if (ret == -ENOENT) {
3380                 memset(&caps_cmd, 0, sizeof(caps_cmd));
3381                 caps_cmd.op_to_write =
3382                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3383                                         FW_CMD_REQUEST_F |
3384                                         FW_CMD_READ_F);
3385                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3386                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3387                                 sizeof(caps_cmd), &caps_cmd);
3388                 config_name = "Firmware Default";
3389         }
3390
3391         config_issued = 1;
3392         if (ret < 0)
3393                 goto bye;
3394
3395         finiver = ntohl(caps_cmd.finiver);
3396         finicsum = ntohl(caps_cmd.finicsum);
3397         cfcsum = ntohl(caps_cmd.cfcsum);
3398         if (finicsum != cfcsum)
3399                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3400                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3401                          finicsum, cfcsum);
3402
3403         /*
3404          * And now tell the firmware to use the configuration we just loaded.
3405          */
3406         caps_cmd.op_to_write =
3407                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3408                       FW_CMD_REQUEST_F |
3409                       FW_CMD_WRITE_F);
3410         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3411         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3412                          NULL);
3413         if (ret < 0)
3414                 goto bye;
3415
3416         /*
3417          * Tweak configuration based on system architecture, module
3418          * parameters, etc.
3419          */
3420         ret = adap_init0_tweaks(adapter);
3421         if (ret < 0)
3422                 goto bye;
3423
3424         /*
3425          * And finally tell the firmware to initialize itself using the
3426          * parameters from the Configuration File.
3427          */
3428         ret = t4_fw_initialize(adapter, adapter->mbox);
3429         if (ret < 0)
3430                 goto bye;
3431
3432         /* Emit Firmware Configuration File information and return
3433          * successfully.
3434          */
3435         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3436                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3437                  config_name, finiver, cfcsum);
3438         return 0;
3439
3440         /*
3441          * Something bad happened.  Return the error ...  (If the "error"
3442          * is that there's no Configuration File on the adapter we don't
3443          * want to issue a warning since this is fairly common.)
3444          */
3445 bye:
3446         if (config_issued && ret != -ENOENT)
3447                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3448                          config_name, -ret);
3449         return ret;
3450 }
3451
3452 static struct fw_info fw_info_array[] = {
3453         {
3454                 .chip = CHELSIO_T4,
3455                 .fs_name = FW4_CFNAME,
3456                 .fw_mod_name = FW4_FNAME,
3457                 .fw_hdr = {
3458                         .chip = FW_HDR_CHIP_T4,
3459                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3460                         .intfver_nic = FW_INTFVER(T4, NIC),
3461                         .intfver_vnic = FW_INTFVER(T4, VNIC),
3462                         .intfver_ri = FW_INTFVER(T4, RI),
3463                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3464                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
3465                 },
3466         }, {
3467                 .chip = CHELSIO_T5,
3468                 .fs_name = FW5_CFNAME,
3469                 .fw_mod_name = FW5_FNAME,
3470                 .fw_hdr = {
3471                         .chip = FW_HDR_CHIP_T5,
3472                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3473                         .intfver_nic = FW_INTFVER(T5, NIC),
3474                         .intfver_vnic = FW_INTFVER(T5, VNIC),
3475                         .intfver_ri = FW_INTFVER(T5, RI),
3476                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3477                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
3478                 },
3479         }, {
3480                 .chip = CHELSIO_T6,
3481                 .fs_name = FW6_CFNAME,
3482                 .fw_mod_name = FW6_FNAME,
3483                 .fw_hdr = {
3484                         .chip = FW_HDR_CHIP_T6,
3485                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3486                         .intfver_nic = FW_INTFVER(T6, NIC),
3487                         .intfver_vnic = FW_INTFVER(T6, VNIC),
3488                         .intfver_ofld = FW_INTFVER(T6, OFLD),
3489                         .intfver_ri = FW_INTFVER(T6, RI),
3490                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3491                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3492                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3493                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
3494                 },
3495         }
3496
3497 };
3498
3499 static struct fw_info *find_fw_info(int chip)
3500 {
3501         int i;
3502
3503         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3504                 if (fw_info_array[i].chip == chip)
3505                         return &fw_info_array[i];
3506         }
3507         return NULL;
3508 }
3509
3510 /*
3511  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3512  */
3513 static int adap_init0(struct adapter *adap)
3514 {
3515         int ret;
3516         u32 v, port_vec;
3517         enum dev_state state;
3518         u32 params[7], val[7];
3519         struct fw_caps_config_cmd caps_cmd;
3520         int reset = 1;
3521
3522         /* Grab Firmware Device Log parameters as early as possible so we have
3523          * access to it for debugging, etc.
3524          */
3525         ret = t4_init_devlog_params(adap);
3526         if (ret < 0)
3527                 return ret;
3528
3529         /* Contact FW, advertising Master capability */
3530         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
3531                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
3532         if (ret < 0) {
3533                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3534                         ret);
3535                 return ret;
3536         }
3537         if (ret == adap->mbox)
3538                 adap->flags |= MASTER_PF;
3539
3540         /*
3541          * If we're the Master PF Driver and the device is uninitialized,
3542          * then let's consider upgrading the firmware ...  (We always want
3543          * to check the firmware version number in order to A. get it for
3544          * later reporting and B. to warn if the currently loaded firmware
3545          * is excessively mismatched relative to the driver.)
3546          */
3547         t4_get_fw_version(adap, &adap->params.fw_vers);
3548         t4_get_bs_version(adap, &adap->params.bs_vers);
3549         t4_get_tp_version(adap, &adap->params.tp_vers);
3550         t4_get_exprom_version(adap, &adap->params.er_vers);
3551
3552         ret = t4_check_fw_version(adap);
3553         /* If firmware is too old (not supported by driver) force an update. */
3554         if (ret)
3555                 state = DEV_STATE_UNINIT;
3556         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3557                 struct fw_info *fw_info;
3558                 struct fw_hdr *card_fw;
3559                 const struct firmware *fw;
3560                 const u8 *fw_data = NULL;
3561                 unsigned int fw_size = 0;
3562
3563                 /* This is the firmware whose headers the driver was compiled
3564                  * against
3565                  */
3566                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3567                 if (fw_info == NULL) {
3568                         dev_err(adap->pdev_dev,
3569                                 "unable to get firmware info for chip %d.\n",
3570                                 CHELSIO_CHIP_VERSION(adap->params.chip));
3571                         return -EINVAL;
3572                 }
3573
3574                 /* allocate memory to read the header of the firmware on the
3575                  * card
3576                  */
3577                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
3578
3579                 /* Get FW from from /lib/firmware/ */
3580                 ret = request_firmware(&fw, fw_info->fw_mod_name,
3581                                        adap->pdev_dev);
3582                 if (ret < 0) {
3583                         dev_err(adap->pdev_dev,
3584                                 "unable to load firmware image %s, error %d\n",
3585                                 fw_info->fw_mod_name, ret);
3586                 } else {
3587                         fw_data = fw->data;
3588                         fw_size = fw->size;
3589                 }
3590
3591                 /* upgrade FW logic */
3592                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3593                                  state, &reset);
3594
3595                 /* Cleaning up */
3596                 release_firmware(fw);
3597                 kvfree(card_fw);
3598
3599                 if (ret < 0)
3600                         goto bye;
3601         }
3602
3603         /*
3604          * Grab VPD parameters.  This should be done after we establish a
3605          * connection to the firmware since some of the VPD parameters
3606          * (notably the Core Clock frequency) are retrieved via requests to
3607          * the firmware.  On the other hand, we need these fairly early on
3608          * so we do this right after getting ahold of the firmware.
3609          */
3610         ret = t4_get_vpd_params(adap, &adap->params.vpd);
3611         if (ret < 0)
3612                 goto bye;
3613
3614         /*
3615          * Find out what ports are available to us.  Note that we need to do
3616          * this before calling adap_init0_no_config() since it needs nports
3617          * and portvec ...
3618          */
3619         v =
3620             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3621             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3622         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3623         if (ret < 0)
3624                 goto bye;
3625
3626         adap->params.nports = hweight32(port_vec);
3627         adap->params.portvec = port_vec;
3628
3629         /* If the firmware is initialized already, emit a simply note to that
3630          * effect. Otherwise, it's time to try initializing the adapter.
3631          */
3632         if (state == DEV_STATE_INIT) {
3633                 dev_info(adap->pdev_dev, "Coming up as %s: "\
3634                          "Adapter already initialized\n",
3635                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3636         } else {
3637                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3638                          "Initializing adapter\n");
3639
3640                 /* Find out whether we're dealing with a version of the
3641                  * firmware which has configuration file support.
3642                  */
3643                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3644                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3645                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3646                                       params, val);
3647
3648                 /* If the firmware doesn't support Configuration Files,
3649                  * return an error.
3650                  */
3651                 if (ret < 0) {
3652                         dev_err(adap->pdev_dev, "firmware doesn't support "
3653                                 "Firmware Configuration Files\n");
3654                         goto bye;
3655                 }
3656
3657                 /* The firmware provides us with a memory buffer where we can
3658                  * load a Configuration File from the host if we want to
3659                  * override the Configuration File in flash.
3660                  */
3661                 ret = adap_init0_config(adap, reset);
3662                 if (ret == -ENOENT) {
3663                         dev_err(adap->pdev_dev, "no Configuration File "
3664                                 "present on adapter.\n");
3665                         goto bye;
3666                 }
3667                 if (ret < 0) {
3668                         dev_err(adap->pdev_dev, "could not initialize "
3669                                 "adapter, error %d\n", -ret);
3670                         goto bye;
3671                 }
3672         }
3673
3674         /* Give the SGE code a chance to pull in anything that it needs ...
3675          * Note that this must be called after we retrieve our VPD parameters
3676          * in order to know how to convert core ticks to seconds, etc.
3677          */
3678         ret = t4_sge_init(adap);
3679         if (ret < 0)
3680                 goto bye;
3681
3682         if (is_bypass_device(adap->pdev->device))
3683                 adap->params.bypass = 1;
3684
3685         /*
3686          * Grab some of our basic fundamental operating parameters.
3687          */
3688 #define FW_PARAM_DEV(param) \
3689         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3690         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3691
3692 #define FW_PARAM_PFVF(param) \
3693         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3694         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
3695         FW_PARAMS_PARAM_Y_V(0) | \
3696         FW_PARAMS_PARAM_Z_V(0)
3697
3698         params[0] = FW_PARAM_PFVF(EQ_START);
3699         params[1] = FW_PARAM_PFVF(L2T_START);
3700         params[2] = FW_PARAM_PFVF(L2T_END);
3701         params[3] = FW_PARAM_PFVF(FILTER_START);
3702         params[4] = FW_PARAM_PFVF(FILTER_END);
3703         params[5] = FW_PARAM_PFVF(IQFLINT_START);
3704         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3705         if (ret < 0)
3706                 goto bye;
3707         adap->sge.egr_start = val[0];
3708         adap->l2t_start = val[1];
3709         adap->l2t_end = val[2];
3710         adap->tids.ftid_base = val[3];
3711         adap->tids.nftids = val[4] - val[3] + 1;
3712         adap->sge.ingr_start = val[5];
3713
3714         /* qids (ingress/egress) returned from firmware can be anywhere
3715          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3716          * Hence driver needs to allocate memory for this range to
3717          * store the queue info. Get the highest IQFLINT/EQ index returned
3718          * in FW_EQ_*_CMD.alloc command.
3719          */
3720         params[0] = FW_PARAM_PFVF(EQ_END);
3721         params[1] = FW_PARAM_PFVF(IQFLINT_END);
3722         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3723         if (ret < 0)
3724                 goto bye;
3725         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3726         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3727
3728         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3729                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
3730         if (!adap->sge.egr_map) {
3731                 ret = -ENOMEM;
3732                 goto bye;
3733         }
3734
3735         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3736                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3737         if (!adap->sge.ingr_map) {
3738                 ret = -ENOMEM;
3739                 goto bye;
3740         }
3741
3742         /* Allocate the memory for the vaious egress queue bitmaps
3743          * ie starving_fl, txq_maperr and blocked_fl.
3744          */
3745         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3746                                         sizeof(long), GFP_KERNEL);
3747         if (!adap->sge.starving_fl) {
3748                 ret = -ENOMEM;
3749                 goto bye;
3750         }
3751
3752         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3753                                        sizeof(long), GFP_KERNEL);
3754         if (!adap->sge.txq_maperr) {
3755                 ret = -ENOMEM;
3756                 goto bye;
3757         }
3758
3759 #ifdef CONFIG_DEBUG_FS
3760         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3761                                        sizeof(long), GFP_KERNEL);
3762         if (!adap->sge.blocked_fl) {
3763                 ret = -ENOMEM;
3764                 goto bye;
3765         }
3766 #endif
3767
3768         params[0] = FW_PARAM_PFVF(CLIP_START);
3769         params[1] = FW_PARAM_PFVF(CLIP_END);
3770         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3771         if (ret < 0)
3772                 goto bye;
3773         adap->clipt_start = val[0];
3774         adap->clipt_end = val[1];
3775
3776         /* We don't yet have a PARAMs calls to retrieve the number of Traffic
3777          * Classes supported by the hardware/firmware so we hard code it here
3778          * for now.
3779          */
3780         adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
3781
3782         /* query params related to active filter region */
3783         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3784         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3785         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3786         /* If Active filter size is set we enable establishing
3787          * offload connection through firmware work request
3788          */
3789         if ((val[0] != val[1]) && (ret >= 0)) {
3790                 adap->flags |= FW_OFLD_CONN;
3791                 adap->tids.aftid_base = val[0];
3792                 adap->tids.aftid_end = val[1];
3793         }
3794
3795         /* If we're running on newer firmware, let it know that we're
3796          * prepared to deal with encapsulated CPL messages.  Older
3797          * firmware won't understand this and we'll just get
3798          * unencapsulated messages ...
3799          */
3800         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3801         val[0] = 1;
3802         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3803
3804         /*
3805          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3806          * capability.  Earlier versions of the firmware didn't have the
3807          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3808          * permission to use ULPTX MEMWRITE DSGL.
3809          */
3810         if (is_t4(adap->params.chip)) {
3811                 adap->params.ulptx_memwrite_dsgl = false;
3812         } else {
3813                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3814                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3815                                       1, params, val);
3816                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3817         }
3818
3819         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
3820         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
3821         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3822                               1, params, val);
3823         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
3824
3825         /*
3826          * Get device capabilities so we can determine what resources we need
3827          * to manage.
3828          */
3829         memset(&caps_cmd, 0, sizeof(caps_cmd));
3830         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3831                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
3832         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3833         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3834                          &caps_cmd);
3835         if (ret < 0)
3836                 goto bye;
3837
3838         if (caps_cmd.ofldcaps) {
3839                 /* query offload-related parameters */
3840                 params[0] = FW_PARAM_DEV(NTID);
3841                 params[1] = FW_PARAM_PFVF(SERVER_START);
3842                 params[2] = FW_PARAM_PFVF(SERVER_END);
3843                 params[3] = FW_PARAM_PFVF(TDDP_START);
3844                 params[4] = FW_PARAM_PFVF(TDDP_END);
3845                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3846                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3847                                       params, val);
3848                 if (ret < 0)
3849                         goto bye;
3850                 adap->tids.ntids = val[0];
3851                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3852                 adap->tids.stid_base = val[1];
3853                 adap->tids.nstids = val[2] - val[1] + 1;
3854                 /*
3855                  * Setup server filter region. Divide the available filter
3856                  * region into two parts. Regular filters get 1/3rd and server
3857                  * filters get 2/3rd part. This is only enabled if workarond
3858                  * path is enabled.
3859                  * 1. For regular filters.
3860                  * 2. Server filter: This are special filters which are used
3861                  * to redirect SYN packets to offload queue.
3862                  */
3863                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3864                         adap->tids.sftid_base = adap->tids.ftid_base +
3865                                         DIV_ROUND_UP(adap->tids.nftids, 3);
3866                         adap->tids.nsftids = adap->tids.nftids -
3867                                          DIV_ROUND_UP(adap->tids.nftids, 3);
3868                         adap->tids.nftids = adap->tids.sftid_base -
3869                                                 adap->tids.ftid_base;
3870                 }
3871                 adap->vres.ddp.start = val[3];
3872                 adap->vres.ddp.size = val[4] - val[3] + 1;
3873                 adap->params.ofldq_wr_cred = val[5];
3874
3875                 adap->params.offload = 1;
3876                 adap->num_ofld_uld += 1;
3877         }
3878         if (caps_cmd.rdmacaps) {
3879                 params[0] = FW_PARAM_PFVF(STAG_START);
3880                 params[1] = FW_PARAM_PFVF(STAG_END);
3881                 params[2] = FW_PARAM_PFVF(RQ_START);
3882                 params[3] = FW_PARAM_PFVF(RQ_END);
3883                 params[4] = FW_PARAM_PFVF(PBL_START);
3884                 params[5] = FW_PARAM_PFVF(PBL_END);
3885                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3886                                       params, val);
3887                 if (ret < 0)
3888                         goto bye;
3889                 adap->vres.stag.start = val[0];
3890                 adap->vres.stag.size = val[1] - val[0] + 1;
3891                 adap->vres.rq.start = val[2];
3892                 adap->vres.rq.size = val[3] - val[2] + 1;
3893                 adap->vres.pbl.start = val[4];
3894                 adap->vres.pbl.size = val[5] - val[4] + 1;
3895
3896                 params[0] = FW_PARAM_PFVF(SQRQ_START);
3897                 params[1] = FW_PARAM_PFVF(SQRQ_END);
3898                 params[2] = FW_PARAM_PFVF(CQ_START);
3899                 params[3] = FW_PARAM_PFVF(CQ_END);
3900                 params[4] = FW_PARAM_PFVF(OCQ_START);
3901                 params[5] = FW_PARAM_PFVF(OCQ_END);
3902                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
3903                                       val);
3904                 if (ret < 0)
3905                         goto bye;
3906                 adap->vres.qp.start = val[0];
3907                 adap->vres.qp.size = val[1] - val[0] + 1;
3908                 adap->vres.cq.start = val[2];
3909                 adap->vres.cq.size = val[3] - val[2] + 1;
3910                 adap->vres.ocq.start = val[4];
3911                 adap->vres.ocq.size = val[5] - val[4] + 1;
3912
3913                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3914                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3915                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
3916                                       val);
3917                 if (ret < 0) {
3918                         adap->params.max_ordird_qp = 8;
3919                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3920                         ret = 0;
3921                 } else {
3922                         adap->params.max_ordird_qp = val[0];
3923                         adap->params.max_ird_adapter = val[1];
3924                 }
3925                 dev_info(adap->pdev_dev,
3926                          "max_ordird_qp %d max_ird_adapter %d\n",
3927                          adap->params.max_ordird_qp,
3928                          adap->params.max_ird_adapter);
3929                 adap->num_ofld_uld += 2;
3930         }
3931         if (caps_cmd.iscsicaps) {
3932                 params[0] = FW_PARAM_PFVF(ISCSI_START);
3933                 params[1] = FW_PARAM_PFVF(ISCSI_END);
3934                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
3935                                       params, val);
3936                 if (ret < 0)
3937                         goto bye;
3938                 adap->vres.iscsi.start = val[0];
3939                 adap->vres.iscsi.size = val[1] - val[0] + 1;
3940                 /* LIO target and cxgb4i initiaitor */
3941                 adap->num_ofld_uld += 2;
3942         }
3943         if (caps_cmd.cryptocaps) {
3944                 /* Should query params here...TODO */
3945                 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
3946                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
3947                                       params, val);
3948                 if (ret < 0) {
3949                         if (ret != -EINVAL)
3950                                 goto bye;
3951                 } else {
3952                         adap->vres.ncrypto_fc = val[0];
3953                 }
3954                 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
3955                 adap->num_uld += 1;
3956         }
3957 #undef FW_PARAM_PFVF
3958 #undef FW_PARAM_DEV
3959
3960         /* The MTU/MSS Table is initialized by now, so load their values.  If
3961          * we're initializing the adapter, then we'll make any modifications
3962          * we want to the MTU/MSS Table and also initialize the congestion
3963          * parameters.
3964          */
3965         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
3966         if (state != DEV_STATE_INIT) {
3967                 int i;
3968
3969                 /* The default MTU Table contains values 1492 and 1500.
3970                  * However, for TCP, it's better to have two values which are
3971                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
3972                  * This allows us to have a TCP Data Payload which is a
3973                  * multiple of 8 regardless of what combination of TCP Options
3974                  * are in use (always a multiple of 4 bytes) which is
3975                  * important for performance reasons.  For instance, if no
3976                  * options are in use, then we have a 20-byte IP header and a
3977                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
3978                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
3979                  * which is not a multiple of 8.  So using an MSS of 1488 in
3980                  * this case results in a TCP Data Payload of 1448 bytes which
3981                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
3982                  * Stamps have been negotiated, then an MTU of 1500 bytes
3983                  * results in a TCP Data Payload of 1448 bytes which, as
3984                  * above, is a multiple of 8 bytes ...
3985                  */
3986                 for (i = 0; i < NMTUS; i++)
3987                         if (adap->params.mtus[i] == 1492) {
3988                                 adap->params.mtus[i] = 1488;
3989                                 break;
3990                         }
3991
3992                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3993                              adap->params.b_wnd);
3994         }
3995         t4_init_sge_params(adap);
3996         adap->flags |= FW_OK;
3997         t4_init_tp_params(adap);
3998         return 0;
3999
4000         /*
4001          * Something bad happened.  If a command timed out or failed with EIO
4002          * FW does not operate within its spec or something catastrophic
4003          * happened to HW/FW, stop issuing commands.
4004          */
4005 bye:
4006         kfree(adap->sge.egr_map);
4007         kfree(adap->sge.ingr_map);
4008         kfree(adap->sge.starving_fl);
4009         kfree(adap->sge.txq_maperr);
4010 #ifdef CONFIG_DEBUG_FS
4011         kfree(adap->sge.blocked_fl);
4012 #endif
4013         if (ret != -ETIMEDOUT && ret != -EIO)
4014                 t4_fw_bye(adap, adap->mbox);
4015         return ret;
4016 }
4017
4018 /* EEH callbacks */
4019
4020 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4021                                          pci_channel_state_t state)
4022 {
4023         int i;
4024         struct adapter *adap = pci_get_drvdata(pdev);
4025
4026         if (!adap)
4027                 goto out;
4028
4029         rtnl_lock();
4030         adap->flags &= ~FW_OK;
4031         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4032         spin_lock(&adap->stats_lock);
4033         for_each_port(adap, i) {
4034                 struct net_device *dev = adap->port[i];
4035                 if (dev) {
4036                         netif_device_detach(dev);
4037                         netif_carrier_off(dev);
4038                 }
4039         }
4040         spin_unlock(&adap->stats_lock);
4041         disable_interrupts(adap);
4042         if (adap->flags & FULL_INIT_DONE)
4043                 cxgb_down(adap);
4044         rtnl_unlock();
4045         if ((adap->flags & DEV_ENABLED)) {
4046                 pci_disable_device(pdev);
4047                 adap->flags &= ~DEV_ENABLED;
4048         }
4049 out:    return state == pci_channel_io_perm_failure ?
4050                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4051 }
4052
4053 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4054 {
4055         int i, ret;
4056         struct fw_caps_config_cmd c;
4057         struct adapter *adap = pci_get_drvdata(pdev);
4058
4059         if (!adap) {
4060                 pci_restore_state(pdev);
4061                 pci_save_state(pdev);
4062                 return PCI_ERS_RESULT_RECOVERED;
4063         }
4064
4065         if (!(adap->flags & DEV_ENABLED)) {
4066                 if (pci_enable_device(pdev)) {
4067                         dev_err(&pdev->dev, "Cannot reenable PCI "
4068                                             "device after reset\n");
4069                         return PCI_ERS_RESULT_DISCONNECT;
4070                 }
4071                 adap->flags |= DEV_ENABLED;
4072         }
4073
4074         pci_set_master(pdev);
4075         pci_restore_state(pdev);
4076         pci_save_state(pdev);
4077         pci_cleanup_aer_uncorrect_error_status(pdev);
4078
4079         if (t4_wait_dev_ready(adap->regs) < 0)
4080                 return PCI_ERS_RESULT_DISCONNECT;
4081         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4082                 return PCI_ERS_RESULT_DISCONNECT;
4083         adap->flags |= FW_OK;
4084         if (adap_init1(adap, &c))
4085                 return PCI_ERS_RESULT_DISCONNECT;
4086
4087         for_each_port(adap, i) {
4088                 struct port_info *p = adap2pinfo(adap, i);
4089
4090                 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4091                                   NULL, NULL);
4092                 if (ret < 0)
4093                         return PCI_ERS_RESULT_DISCONNECT;
4094                 p->viid = ret;
4095                 p->xact_addr_filt = -1;
4096         }
4097
4098         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4099                      adap->params.b_wnd);
4100         setup_memwin(adap);
4101         if (cxgb_up(adap))
4102                 return PCI_ERS_RESULT_DISCONNECT;
4103         return PCI_ERS_RESULT_RECOVERED;
4104 }
4105
4106 static void eeh_resume(struct pci_dev *pdev)
4107 {
4108         int i;
4109         struct adapter *adap = pci_get_drvdata(pdev);
4110
4111         if (!adap)
4112                 return;
4113
4114         rtnl_lock();
4115         for_each_port(adap, i) {
4116                 struct net_device *dev = adap->port[i];
4117                 if (dev) {
4118                         if (netif_running(dev)) {
4119                                 link_start(dev);
4120                                 cxgb_set_rxmode(dev);
4121                         }
4122                         netif_device_attach(dev);
4123                 }
4124         }
4125         rtnl_unlock();
4126 }
4127
4128 static const struct pci_error_handlers cxgb4_eeh = {
4129         .error_detected = eeh_err_detected,
4130         .slot_reset     = eeh_slot_reset,
4131         .resume         = eeh_resume,
4132 };
4133
4134 /* Return true if the Link Configuration supports "High Speeds" (those greater
4135  * than 1Gb/s).
4136  */
4137 static inline bool is_x_10g_port(const struct link_config *lc)
4138 {
4139         unsigned int speeds, high_speeds;
4140
4141         speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));
4142         high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
4143
4144         return high_speeds != 0;
4145 }
4146
4147 /*
4148  * Perform default configuration of DMA queues depending on the number and type
4149  * of ports we found and the number of available CPUs.  Most settings can be
4150  * modified by the admin prior to actual use.
4151  */
4152 static void cfg_queues(struct adapter *adap)
4153 {
4154         struct sge *s = &adap->sge;
4155         int i = 0, n10g = 0, qidx = 0;
4156 #ifndef CONFIG_CHELSIO_T4_DCB
4157         int q10g = 0;
4158 #endif
4159
4160         /* Reduce memory usage in kdump environment, disable all offload.
4161          */
4162         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
4163                 adap->params.offload = 0;
4164                 adap->params.crypto = 0;
4165         }
4166
4167         n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4168 #ifdef CONFIG_CHELSIO_T4_DCB
4169         /* For Data Center Bridging support we need to be able to support up
4170          * to 8 Traffic Priorities; each of which will be assigned to its
4171          * own TX Queue in order to prevent Head-Of-Line Blocking.
4172          */
4173         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4174                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4175                         MAX_ETH_QSETS, adap->params.nports * 8);
4176                 BUG_ON(1);
4177         }
4178
4179         for_each_port(adap, i) {
4180                 struct port_info *pi = adap2pinfo(adap, i);
4181
4182                 pi->first_qset = qidx;
4183                 pi->nqsets = is_kdump_kernel() ? 1 : 8;
4184                 qidx += pi->nqsets;
4185         }
4186 #else /* !CONFIG_CHELSIO_T4_DCB */
4187         /*
4188          * We default to 1 queue per non-10G port and up to # of cores queues
4189          * per 10G port.
4190          */
4191         if (n10g)
4192                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4193         if (q10g > netif_get_num_default_rss_queues())
4194                 q10g = netif_get_num_default_rss_queues();
4195
4196         if (is_kdump_kernel())
4197                 q10g = 1;
4198
4199         for_each_port(adap, i) {
4200                 struct port_info *pi = adap2pinfo(adap, i);
4201
4202                 pi->first_qset = qidx;
4203                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4204                 qidx += pi->nqsets;
4205         }
4206 #endif /* !CONFIG_CHELSIO_T4_DCB */
4207
4208         s->ethqsets = qidx;
4209         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
4210
4211         if (is_uld(adap)) {
4212                 /*
4213                  * For offload we use 1 queue/channel if all ports are up to 1G,
4214                  * otherwise we divide all available queues amongst the channels
4215                  * capped by the number of available cores.
4216                  */
4217                 if (n10g) {
4218                         i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
4219                         s->ofldqsets = roundup(i, adap->params.nports);
4220                 } else {
4221                         s->ofldqsets = adap->params.nports;
4222                 }
4223         }
4224
4225         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4226                 struct sge_eth_rxq *r = &s->ethrxq[i];
4227
4228                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4229                 r->fl.size = 72;
4230         }
4231
4232         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4233                 s->ethtxq[i].q.size = 1024;
4234
4235         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4236                 s->ctrlq[i].q.size = 512;
4237
4238         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4239         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
4240 }
4241
4242 /*
4243  * Reduce the number of Ethernet queues across all ports to at most n.
4244  * n provides at least one queue per port.
4245  */
4246 static void reduce_ethqs(struct adapter *adap, int n)
4247 {
4248         int i;
4249         struct port_info *pi;
4250
4251         while (n < adap->sge.ethqsets)
4252                 for_each_port(adap, i) {
4253                         pi = adap2pinfo(adap, i);
4254                         if (pi->nqsets > 1) {
4255                                 pi->nqsets--;
4256                                 adap->sge.ethqsets--;
4257                                 if (adap->sge.ethqsets <= n)
4258                                         break;
4259                         }
4260                 }
4261
4262         n = 0;
4263         for_each_port(adap, i) {
4264                 pi = adap2pinfo(adap, i);
4265                 pi->first_qset = n;
4266                 n += pi->nqsets;
4267         }
4268 }
4269
4270 static int get_msix_info(struct adapter *adap)
4271 {
4272         struct uld_msix_info *msix_info;
4273         unsigned int max_ingq = 0;
4274
4275         if (is_offload(adap))
4276                 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
4277         if (is_pci_uld(adap))
4278                 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
4279
4280         if (!max_ingq)
4281                 goto out;
4282
4283         msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
4284         if (!msix_info)
4285                 return -ENOMEM;
4286
4287         adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
4288                                                  sizeof(long), GFP_KERNEL);
4289         if (!adap->msix_bmap_ulds.msix_bmap) {
4290                 kfree(msix_info);
4291                 return -ENOMEM;
4292         }
4293         spin_lock_init(&adap->msix_bmap_ulds.lock);
4294         adap->msix_info_ulds = msix_info;
4295 out:
4296         return 0;
4297 }
4298
4299 static void free_msix_info(struct adapter *adap)
4300 {
4301         if (!(adap->num_uld && adap->num_ofld_uld))
4302                 return;
4303
4304         kfree(adap->msix_info_ulds);
4305         kfree(adap->msix_bmap_ulds.msix_bmap);
4306 }
4307
4308 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4309 #define EXTRA_VECS 2
4310
4311 static int enable_msix(struct adapter *adap)
4312 {
4313         int ofld_need = 0, uld_need = 0;
4314         int i, j, want, need, allocated;
4315         struct sge *s = &adap->sge;
4316         unsigned int nchan = adap->params.nports;
4317         struct msix_entry *entries;
4318         int max_ingq = MAX_INGQ;
4319
4320         if (is_pci_uld(adap))
4321                 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
4322         if (is_offload(adap))
4323                 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
4324         entries = kmalloc(sizeof(*entries) * (max_ingq + 1),
4325                           GFP_KERNEL);
4326         if (!entries)
4327                 return -ENOMEM;
4328
4329         /* map for msix */
4330         if (get_msix_info(adap)) {
4331                 adap->params.offload = 0;
4332                 adap->params.crypto = 0;
4333         }
4334
4335         for (i = 0; i < max_ingq + 1; ++i)
4336                 entries[i].entry = i;
4337
4338         want = s->max_ethqsets + EXTRA_VECS;
4339         if (is_offload(adap)) {
4340                 want += adap->num_ofld_uld * s->ofldqsets;
4341                 ofld_need = adap->num_ofld_uld * nchan;
4342         }
4343         if (is_pci_uld(adap)) {
4344                 want += adap->num_uld * s->ofldqsets;
4345                 uld_need = adap->num_uld * nchan;
4346         }
4347 #ifdef CONFIG_CHELSIO_T4_DCB
4348         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4349          * each port.
4350          */
4351         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4352 #else
4353         need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4354 #endif
4355         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4356         if (allocated < 0) {
4357                 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4358                          " not using MSI-X\n");
4359                 kfree(entries);
4360                 return allocated;
4361         }
4362
4363         /* Distribute available vectors to the various queue groups.
4364          * Every group gets its minimum requirement and NIC gets top
4365          * priority for leftovers.
4366          */
4367         i = allocated - EXTRA_VECS - ofld_need - uld_need;
4368         if (i < s->max_ethqsets) {
4369                 s->max_ethqsets = i;
4370                 if (i < s->ethqsets)
4371                         reduce_ethqs(adap, i);
4372         }
4373         if (is_uld(adap)) {
4374                 if (allocated < want)
4375                         s->nqs_per_uld = nchan;
4376                 else
4377                         s->nqs_per_uld = s->ofldqsets;
4378         }
4379
4380         for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
4381                 adap->msix_info[i].vec = entries[i].vector;
4382         if (is_uld(adap)) {
4383                 for (j = 0 ; i < allocated; ++i, j++) {
4384                         adap->msix_info_ulds[j].vec = entries[i].vector;
4385                         adap->msix_info_ulds[j].idx = i;
4386                 }
4387                 adap->msix_bmap_ulds.mapsize = j;
4388         }
4389         dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4390                  "nic %d per uld %d\n",
4391                  allocated, s->max_ethqsets, s->nqs_per_uld);
4392
4393         kfree(entries);
4394         return 0;
4395 }
4396
4397 #undef EXTRA_VECS
4398
4399 static int init_rss(struct adapter *adap)
4400 {
4401         unsigned int i;
4402         int err;
4403
4404         err = t4_init_rss_mode(adap, adap->mbox);
4405         if (err)
4406                 return err;
4407
4408         for_each_port(adap, i) {
4409                 struct port_info *pi = adap2pinfo(adap, i);
4410
4411                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4412                 if (!pi->rss)
4413                         return -ENOMEM;
4414         }
4415         return 0;
4416 }
4417
4418 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4419                                         enum pci_bus_speed *speed,
4420                                         enum pcie_link_width *width)
4421 {
4422         u32 lnkcap1, lnkcap2;
4423         int err1, err2;
4424
4425 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
4426
4427         *speed = PCI_SPEED_UNKNOWN;
4428         *width = PCIE_LNK_WIDTH_UNKNOWN;
4429
4430         err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4431                                           &lnkcap1);
4432         err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4433                                           &lnkcap2);
4434         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4435                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4436                         *speed = PCIE_SPEED_8_0GT;
4437                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4438                         *speed = PCIE_SPEED_5_0GT;
4439                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4440                         *speed = PCIE_SPEED_2_5GT;
4441         }
4442         if (!err1) {
4443                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4444                 if (!lnkcap2) { /* pre-r3.0 */
4445                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4446                                 *speed = PCIE_SPEED_5_0GT;
4447                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4448                                 *speed = PCIE_SPEED_2_5GT;
4449                 }
4450         }
4451
4452         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4453                 return err1 ? err1 : err2 ? err2 : -EINVAL;
4454         return 0;
4455 }
4456
4457 static void cxgb4_check_pcie_caps(struct adapter *adap)
4458 {
4459         enum pcie_link_width width, width_cap;
4460         enum pci_bus_speed speed, speed_cap;
4461
4462 #define PCIE_SPEED_STR(speed) \
4463         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4464          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4465          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4466          "Unknown")
4467
4468         if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4469                 dev_warn(adap->pdev_dev,
4470                          "Unable to determine PCIe device BW capabilities\n");
4471                 return;
4472         }
4473
4474         if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4475             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4476                 dev_warn(adap->pdev_dev,
4477                          "Unable to determine PCI Express bandwidth.\n");
4478                 return;
4479         }
4480
4481         dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4482                  PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4483         dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4484                  width, width_cap);
4485         if (speed < speed_cap || width < width_cap)
4486                 dev_info(adap->pdev_dev,
4487                          "A slot with more lanes and/or higher speed is "
4488                          "suggested for optimal performance.\n");
4489 }
4490
4491 /* Dump basic information about the adapter */
4492 static void print_adapter_info(struct adapter *adapter)
4493 {
4494         /* Device information */
4495         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
4496                  adapter->params.vpd.id,
4497                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
4498         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
4499                  adapter->params.vpd.sn, adapter->params.vpd.pn);
4500
4501         /* Firmware Version */
4502         if (!adapter->params.fw_vers)
4503                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
4504         else
4505                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
4506                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
4507                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
4508                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
4509                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
4510
4511         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
4512          * Firmware, so dev_info() is more appropriate here.)
4513          */
4514         if (!adapter->params.bs_vers)
4515                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
4516         else
4517                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
4518                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
4519                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
4520                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
4521                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
4522
4523         /* TP Microcode Version */
4524         if (!adapter->params.tp_vers)
4525                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
4526         else
4527                 dev_info(adapter->pdev_dev,
4528                          "TP Microcode version: %u.%u.%u.%u\n",
4529                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
4530                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
4531                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
4532                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
4533
4534         /* Expansion ROM version */
4535         if (!adapter->params.er_vers)
4536                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
4537         else
4538                 dev_info(adapter->pdev_dev,
4539                          "Expansion ROM version: %u.%u.%u.%u\n",
4540                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
4541                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
4542                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
4543                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
4544
4545         /* Software/Hardware configuration */
4546         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
4547                  is_offload(adapter) ? "R" : "",
4548                  ((adapter->flags & USING_MSIX) ? "MSI-X" :
4549                   (adapter->flags & USING_MSI) ? "MSI" : ""),
4550                  is_offload(adapter) ? "Offload" : "non-Offload");
4551 }
4552
4553 static void print_port_info(const struct net_device *dev)
4554 {
4555         char buf[80];
4556         char *bufp = buf;
4557         const char *spd = "";
4558         const struct port_info *pi = netdev_priv(dev);
4559         const struct adapter *adap = pi->adapter;
4560
4561         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4562                 spd = " 2.5 GT/s";
4563         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4564                 spd = " 5 GT/s";
4565         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4566                 spd = " 8 GT/s";
4567
4568         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4569                 bufp += sprintf(bufp, "100M/");
4570         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4571                 bufp += sprintf(bufp, "1G/");
4572         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4573                 bufp += sprintf(bufp, "10G/");
4574         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
4575                 bufp += sprintf(bufp, "25G/");
4576         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4577                 bufp += sprintf(bufp, "40G/");
4578         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
4579                 bufp += sprintf(bufp, "100G/");
4580         if (bufp != buf)
4581                 --bufp;
4582         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4583
4584         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
4585                     dev->name, adap->params.vpd.id, adap->name, buf);
4586 }
4587
4588 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4589 {
4590         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4591 }
4592
4593 /*
4594  * Free the following resources:
4595  * - memory used for tables
4596  * - MSI/MSI-X
4597  * - net devices
4598  * - resources FW is holding for us
4599  */
4600 static void free_some_resources(struct adapter *adapter)
4601 {
4602         unsigned int i;
4603
4604         kvfree(adapter->l2t);
4605         t4_cleanup_sched(adapter);
4606         kvfree(adapter->tids.tid_tab);
4607         cxgb4_cleanup_tc_u32(adapter);
4608         kfree(adapter->sge.egr_map);
4609         kfree(adapter->sge.ingr_map);
4610         kfree(adapter->sge.starving_fl);
4611         kfree(adapter->sge.txq_maperr);
4612 #ifdef CONFIG_DEBUG_FS
4613         kfree(adapter->sge.blocked_fl);
4614 #endif
4615         disable_msi(adapter);
4616
4617         for_each_port(adapter, i)
4618                 if (adapter->port[i]) {
4619                         struct port_info *pi = adap2pinfo(adapter, i);
4620
4621                         if (pi->viid != 0)
4622                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4623                                            0, pi->viid);
4624                         kfree(adap2pinfo(adapter, i)->rss);
4625                         free_netdev(adapter->port[i]);
4626                 }
4627         if (adapter->flags & FW_OK)
4628                 t4_fw_bye(adapter, adapter->pf);
4629 }
4630
4631 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4632 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4633                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4634 #define SEGMENT_SIZE 128
4635
4636 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4637 {
4638         u16 device_id;
4639
4640         /* Retrieve adapter's device ID */
4641         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4642
4643         switch (device_id >> 12) {
4644         case CHELSIO_T4:
4645                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4646         case CHELSIO_T5:
4647                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4648         case CHELSIO_T6:
4649                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4650         default:
4651                 dev_err(&pdev->dev, "Device %d is not supported\n",
4652                         device_id);
4653         }
4654         return -EINVAL;
4655 }
4656
4657 #ifdef CONFIG_PCI_IOV
4658 static void dummy_setup(struct net_device *dev)
4659 {
4660         dev->type = ARPHRD_NONE;
4661         dev->mtu = 0;
4662         dev->hard_header_len = 0;
4663         dev->addr_len = 0;
4664         dev->tx_queue_len = 0;
4665         dev->flags |= IFF_NOARP;
4666         dev->priv_flags |= IFF_NO_QUEUE;
4667
4668         /* Initialize the device structure. */
4669         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
4670         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
4671         dev->needs_free_netdev = true;
4672 }
4673
4674 static int config_mgmt_dev(struct pci_dev *pdev)
4675 {
4676         struct adapter *adap = pci_get_drvdata(pdev);
4677         struct net_device *netdev;
4678         struct port_info *pi;
4679         char name[IFNAMSIZ];
4680         int err;
4681
4682         snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf);
4683         netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN,
4684                               dummy_setup);
4685         if (!netdev)
4686                 return -ENOMEM;
4687
4688         pi = netdev_priv(netdev);
4689         pi->adapter = adap;
4690         pi->port_id = adap->pf % adap->params.nports;
4691         SET_NETDEV_DEV(netdev, &pdev->dev);
4692
4693         adap->port[0] = netdev;
4694
4695         err = register_netdev(adap->port[0]);
4696         if (err) {
4697                 pr_info("Unable to register VF mgmt netdev %s\n", name);
4698                 free_netdev(adap->port[0]);
4699                 adap->port[0] = NULL;
4700                 return err;
4701         }
4702         return 0;
4703 }
4704
4705 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
4706 {
4707         struct adapter *adap = pci_get_drvdata(pdev);
4708         int err = 0;
4709         int current_vfs = pci_num_vf(pdev);
4710         u32 pcie_fw;
4711
4712         pcie_fw = readl(adap->regs + PCIE_FW_A);
4713         /* Check if cxgb4 is the MASTER and fw is initialized */
4714         if (!(pcie_fw & PCIE_FW_INIT_F) ||
4715             !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
4716             PCIE_FW_MASTER_G(pcie_fw) != 4) {
4717                 dev_warn(&pdev->dev,
4718                          "cxgb4 driver needs to be MASTER to support SRIOV\n");
4719                 return -EOPNOTSUPP;
4720         }
4721
4722         /* If any of the VF's is already assigned to Guest OS, then
4723          * SRIOV for the same cannot be modified
4724          */
4725         if (current_vfs && pci_vfs_assigned(pdev)) {
4726                 dev_err(&pdev->dev,
4727                         "Cannot modify SR-IOV while VFs are assigned\n");
4728                 num_vfs = current_vfs;
4729                 return num_vfs;
4730         }
4731
4732         /* Disable SRIOV when zero is passed.
4733          * One needs to disable SRIOV before modifying it, else
4734          * stack throws the below warning:
4735          * " 'n' VFs already enabled. Disable before enabling 'm' VFs."
4736          */
4737         if (!num_vfs) {
4738                 pci_disable_sriov(pdev);
4739                 if (adap->port[0]) {
4740                         unregister_netdev(adap->port[0]);
4741                         adap->port[0] = NULL;
4742                 }
4743                 /* free VF resources */
4744                 kfree(adap->vfinfo);
4745                 adap->vfinfo = NULL;
4746                 adap->num_vfs = 0;
4747                 return num_vfs;
4748         }
4749
4750         if (num_vfs != current_vfs) {
4751                 err = pci_enable_sriov(pdev, num_vfs);
4752                 if (err)
4753                         return err;
4754
4755                 adap->num_vfs = num_vfs;
4756                 err = config_mgmt_dev(pdev);
4757                 if (err)
4758                         return err;
4759         }
4760
4761         adap->vfinfo = kcalloc(adap->num_vfs,
4762                                sizeof(struct vf_info), GFP_KERNEL);
4763         if (adap->vfinfo)
4764                 fill_vf_station_mac_addr(adap);
4765         return num_vfs;
4766 }
4767 #endif
4768
4769 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4770 {
4771         int func, i, err, s_qpp, qpp, num_seg;
4772         struct port_info *pi;
4773         bool highdma = false;
4774         struct adapter *adapter = NULL;
4775         struct net_device *netdev;
4776         void __iomem *regs;
4777         u32 whoami, pl_rev;
4778         enum chip_type chip;
4779         static int adap_idx = 1;
4780 #ifdef CONFIG_PCI_IOV
4781         u32 v, port_vec;
4782 #endif
4783
4784         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4785
4786         err = pci_request_regions(pdev, KBUILD_MODNAME);
4787         if (err) {
4788                 /* Just info, some other driver may have claimed the device. */
4789                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4790                 return err;
4791         }
4792
4793         err = pci_enable_device(pdev);
4794         if (err) {
4795                 dev_err(&pdev->dev, "cannot enable PCI device\n");
4796                 goto out_release_regions;
4797         }
4798
4799         regs = pci_ioremap_bar(pdev, 0);
4800         if (!regs) {
4801                 dev_err(&pdev->dev, "cannot map device registers\n");
4802                 err = -ENOMEM;
4803                 goto out_disable_device;
4804         }
4805
4806         err = t4_wait_dev_ready(regs);
4807         if (err < 0)
4808                 goto out_unmap_bar0;
4809
4810         /* We control everything through one PF */
4811         whoami = readl(regs + PL_WHOAMI_A);
4812         pl_rev = REV_G(readl(regs + PL_REV_A));
4813         chip = get_chip_type(pdev, pl_rev);
4814         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4815                 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4816         if (func != ent->driver_data) {
4817 #ifndef CONFIG_PCI_IOV
4818                 iounmap(regs);
4819 #endif
4820                 pci_disable_device(pdev);
4821                 pci_save_state(pdev);        /* to restore SR-IOV later */
4822                 goto sriov;
4823         }
4824
4825         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4826                 highdma = true;
4827                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4828                 if (err) {
4829                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4830                                 "coherent allocations\n");
4831                         goto out_unmap_bar0;
4832                 }
4833         } else {
4834                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4835                 if (err) {
4836                         dev_err(&pdev->dev, "no usable DMA configuration\n");
4837                         goto out_unmap_bar0;
4838                 }
4839         }
4840
4841         pci_enable_pcie_error_reporting(pdev);
4842         enable_pcie_relaxed_ordering(pdev);
4843         pci_set_master(pdev);
4844         pci_save_state(pdev);
4845
4846         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4847         if (!adapter) {
4848                 err = -ENOMEM;
4849                 goto out_unmap_bar0;
4850         }
4851         adap_idx++;
4852
4853         adapter->workq = create_singlethread_workqueue("cxgb4");
4854         if (!adapter->workq) {
4855                 err = -ENOMEM;
4856                 goto out_free_adapter;
4857         }
4858
4859         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4860                                     (sizeof(struct mbox_cmd) *
4861                                      T4_OS_LOG_MBOX_CMDS),
4862                                     GFP_KERNEL);
4863         if (!adapter->mbox_log) {
4864                 err = -ENOMEM;
4865                 goto out_free_adapter;
4866         }
4867         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
4868
4869         /* PCI device has been enabled */
4870         adapter->flags |= DEV_ENABLED;
4871
4872         adapter->regs = regs;
4873         adapter->pdev = pdev;
4874         adapter->pdev_dev = &pdev->dev;
4875         adapter->name = pci_name(pdev);
4876         adapter->mbox = func;
4877         adapter->pf = func;
4878         adapter->msg_enable = DFLT_MSG_ENABLE;
4879         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4880
4881         spin_lock_init(&adapter->stats_lock);
4882         spin_lock_init(&adapter->tid_release_lock);
4883         spin_lock_init(&adapter->win0_lock);
4884         spin_lock_init(&adapter->mbox_lock);
4885
4886         INIT_LIST_HEAD(&adapter->mlist.list);
4887
4888         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4889         INIT_WORK(&adapter->db_full_task, process_db_full);
4890         INIT_WORK(&adapter->db_drop_task, process_db_drop);
4891
4892         err = t4_prep_adapter(adapter);
4893         if (err)
4894                 goto out_free_adapter;
4895
4896
4897         if (!is_t4(adapter->params.chip)) {
4898                 s_qpp = (QUEUESPERPAGEPF0_S +
4899                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4900                         adapter->pf);
4901                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4902                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4903                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4904
4905                 /* Each segment size is 128B. Write coalescing is enabled only
4906                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4907                  * queue is less no of segments that can be accommodated in
4908                  * a page size.
4909                  */
4910                 if (qpp > num_seg) {
4911                         dev_err(&pdev->dev,
4912                                 "Incorrect number of egress queues per page\n");
4913                         err = -EINVAL;
4914                         goto out_free_adapter;
4915                 }
4916                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4917                 pci_resource_len(pdev, 2));
4918                 if (!adapter->bar2) {
4919                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
4920                         err = -ENOMEM;
4921                         goto out_free_adapter;
4922                 }
4923         }
4924
4925         setup_memwin(adapter);
4926         err = adap_init0(adapter);
4927 #ifdef CONFIG_DEBUG_FS
4928         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4929 #endif
4930         setup_memwin_rdma(adapter);
4931         if (err)
4932                 goto out_unmap_bar;
4933
4934         /* configure SGE_STAT_CFG_A to read WC stats */
4935         if (!is_t4(adapter->params.chip))
4936                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4937                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4938                               T6_STATMODE_V(0)));
4939
4940         for_each_port(adapter, i) {
4941                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4942                                            MAX_ETH_QSETS);
4943                 if (!netdev) {
4944                         err = -ENOMEM;
4945                         goto out_free_dev;
4946                 }
4947
4948                 SET_NETDEV_DEV(netdev, &pdev->dev);
4949
4950                 adapter->port[i] = netdev;
4951                 pi = netdev_priv(netdev);
4952                 pi->adapter = adapter;
4953                 pi->xact_addr_filt = -1;
4954                 pi->port_id = i;
4955                 netdev->irq = pdev->irq;
4956
4957                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4958                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4959                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
4960                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
4961                         NETIF_F_HW_TC;
4962                 if (highdma)
4963                         netdev->hw_features |= NETIF_F_HIGHDMA;
4964                 netdev->features |= netdev->hw_features;
4965                 netdev->vlan_features = netdev->features & VLAN_FEAT;
4966
4967                 netdev->priv_flags |= IFF_UNICAST_FLT;
4968
4969                 /* MTU range: 81 - 9600 */
4970                 netdev->min_mtu = 81;
4971                 netdev->max_mtu = MAX_MTU;
4972
4973                 netdev->netdev_ops = &cxgb4_netdev_ops;
4974 #ifdef CONFIG_CHELSIO_T4_DCB
4975                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4976                 cxgb4_dcb_state_init(netdev);
4977 #endif
4978                 cxgb4_set_ethtool_ops(netdev);
4979         }
4980
4981         pci_set_drvdata(pdev, adapter);
4982
4983         if (adapter->flags & FW_OK) {
4984                 err = t4_port_init(adapter, func, func, 0);
4985                 if (err)
4986                         goto out_free_dev;
4987         } else if (adapter->params.nports == 1) {
4988                 /* If we don't have a connection to the firmware -- possibly
4989                  * because of an error -- grab the raw VPD parameters so we
4990                  * can set the proper MAC Address on the debug network
4991                  * interface that we've created.
4992                  */
4993                 u8 hw_addr[ETH_ALEN];
4994                 u8 *na = adapter->params.vpd.na;
4995
4996                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4997                 if (!err) {
4998                         for (i = 0; i < ETH_ALEN; i++)
4999                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5000                                               hex2val(na[2 * i + 1]));
5001                         t4_set_hw_addr(adapter, 0, hw_addr);
5002                 }
5003         }
5004
5005         /* Configure queues and allocate tables now, they can be needed as
5006          * soon as the first register_netdev completes.
5007          */
5008         cfg_queues(adapter);
5009
5010         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5011         if (!adapter->l2t) {
5012                 /* We tolerate a lack of L2T, giving up some functionality */
5013                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5014                 adapter->params.offload = 0;
5015         }
5016
5017 #if IS_ENABLED(CONFIG_IPV6)
5018         if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
5019             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5020                 /* CLIP functionality is not present in hardware,
5021                  * hence disable all offload features
5022                  */
5023                 dev_warn(&pdev->dev,
5024                          "CLIP not enabled in hardware, continuing\n");
5025                 adapter->params.offload = 0;
5026         } else {
5027                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5028                                                   adapter->clipt_end);
5029                 if (!adapter->clipt) {
5030                         /* We tolerate a lack of clip_table, giving up
5031                          * some functionality
5032                          */
5033                         dev_warn(&pdev->dev,
5034                                  "could not allocate Clip table, continuing\n");
5035                         adapter->params.offload = 0;
5036                 }
5037         }
5038 #endif
5039
5040         for_each_port(adapter, i) {
5041                 pi = adap2pinfo(adapter, i);
5042                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5043                 if (!pi->sched_tbl)
5044                         dev_warn(&pdev->dev,
5045                                  "could not activate scheduling on port %d\n",
5046                                  i);
5047         }
5048
5049         if (tid_init(&adapter->tids) < 0) {
5050                 dev_warn(&pdev->dev, "could not allocate TID table, "
5051                          "continuing\n");
5052                 adapter->params.offload = 0;
5053         } else {
5054                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5055                 if (!adapter->tc_u32)
5056                         dev_warn(&pdev->dev,
5057                                  "could not offload tc u32, continuing\n");
5058         }
5059
5060         if (is_offload(adapter)) {
5061                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5062                         u32 hash_base, hash_reg;
5063
5064                         if (chip <= CHELSIO_T5) {
5065                                 hash_reg = LE_DB_TID_HASHBASE_A;
5066                                 hash_base = t4_read_reg(adapter, hash_reg);
5067                                 adapter->tids.hash_base = hash_base / 4;
5068                         } else {
5069                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5070                                 hash_base = t4_read_reg(adapter, hash_reg);
5071                                 adapter->tids.hash_base = hash_base;
5072                         }
5073                 }
5074         }
5075
5076         /* See what interrupts we'll be using */
5077         if (msi > 1 && enable_msix(adapter) == 0)
5078                 adapter->flags |= USING_MSIX;
5079         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
5080                 adapter->flags |= USING_MSI;
5081                 if (msi > 1)
5082                         free_msix_info(adapter);
5083         }
5084
5085         /* check for PCI Express bandwidth capabiltites */
5086         cxgb4_check_pcie_caps(adapter);
5087
5088         err = init_rss(adapter);
5089         if (err)
5090                 goto out_free_dev;
5091
5092         /*
5093          * The card is now ready to go.  If any errors occur during device
5094          * registration we do not fail the whole card but rather proceed only
5095          * with the ports we manage to register successfully.  However we must
5096          * register at least one net device.
5097          */
5098         for_each_port(adapter, i) {
5099                 pi = adap2pinfo(adapter, i);
5100                 adapter->port[i]->dev_port = pi->lport;
5101                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5102                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5103
5104                 netif_carrier_off(adapter->port[i]);
5105
5106                 err = register_netdev(adapter->port[i]);
5107                 if (err)
5108                         break;
5109                 adapter->chan_map[pi->tx_chan] = i;
5110                 print_port_info(adapter->port[i]);
5111         }
5112         if (i == 0) {
5113                 dev_err(&pdev->dev, "could not register any net devices\n");
5114                 goto out_free_dev;
5115         }
5116         if (err) {
5117                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5118                 err = 0;
5119         }
5120
5121         if (cxgb4_debugfs_root) {
5122                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5123                                                            cxgb4_debugfs_root);
5124                 setup_debugfs(adapter);
5125         }
5126
5127         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5128         pdev->needs_freset = 1;
5129
5130         if (is_uld(adapter)) {
5131                 mutex_lock(&uld_mutex);
5132                 list_add_tail(&adapter->list_node, &adapter_list);
5133                 mutex_unlock(&uld_mutex);
5134         }
5135
5136         print_adapter_info(adapter);
5137         setup_fw_sge_queues(adapter);
5138         return 0;
5139
5140 sriov:
5141 #ifdef CONFIG_PCI_IOV
5142         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5143         if (!adapter) {
5144                 err = -ENOMEM;
5145                 goto free_pci_region;
5146         }
5147
5148         adapter->pdev = pdev;
5149         adapter->pdev_dev = &pdev->dev;
5150         adapter->name = pci_name(pdev);
5151         adapter->mbox = func;
5152         adapter->pf = func;
5153         adapter->regs = regs;
5154         adapter->adap_idx = adap_idx;
5155         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5156                                     (sizeof(struct mbox_cmd) *
5157                                      T4_OS_LOG_MBOX_CMDS),
5158                                     GFP_KERNEL);
5159         if (!adapter->mbox_log) {
5160                 err = -ENOMEM;
5161                 goto free_adapter;
5162         }
5163         spin_lock_init(&adapter->mbox_lock);
5164         INIT_LIST_HEAD(&adapter->mlist.list);
5165
5166         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5167             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5168         err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1,
5169                               &v, &port_vec);
5170         if (err < 0) {
5171                 dev_err(adapter->pdev_dev, "Could not fetch port params\n");
5172                 goto free_mbox_log;
5173         }
5174
5175         adapter->params.nports = hweight32(port_vec);
5176         pci_set_drvdata(pdev, adapter);
5177         return 0;
5178
5179 free_mbox_log:
5180         kfree(adapter->mbox_log);
5181  free_adapter:
5182         kfree(adapter);
5183  free_pci_region:
5184         iounmap(regs);
5185         pci_disable_sriov(pdev);
5186         pci_release_regions(pdev);
5187         return err;
5188 #else
5189         return 0;
5190 #endif
5191
5192  out_free_dev:
5193         free_some_resources(adapter);
5194         if (adapter->flags & USING_MSIX)
5195                 free_msix_info(adapter);
5196         if (adapter->num_uld || adapter->num_ofld_uld)
5197                 t4_uld_mem_free(adapter);
5198  out_unmap_bar:
5199         if (!is_t4(adapter->params.chip))
5200                 iounmap(adapter->bar2);
5201  out_free_adapter:
5202         if (adapter->workq)
5203                 destroy_workqueue(adapter->workq);
5204
5205         kfree(adapter->mbox_log);
5206         kfree(adapter);
5207  out_unmap_bar0:
5208         iounmap(regs);
5209  out_disable_device:
5210         pci_disable_pcie_error_reporting(pdev);
5211         pci_disable_device(pdev);
5212  out_release_regions:
5213         pci_release_regions(pdev);
5214         return err;
5215 }
5216
5217 static void remove_one(struct pci_dev *pdev)
5218 {
5219         struct adapter *adapter = pci_get_drvdata(pdev);
5220
5221         if (!adapter) {
5222                 pci_release_regions(pdev);
5223                 return;
5224         }
5225
5226         if (adapter->pf == 4) {
5227                 int i;
5228
5229                 /* Tear down per-adapter Work Queue first since it can contain
5230                  * references to our adapter data structure.
5231                  */
5232                 destroy_workqueue(adapter->workq);
5233
5234                 if (is_uld(adapter))
5235                         detach_ulds(adapter);
5236
5237                 disable_interrupts(adapter);
5238
5239                 for_each_port(adapter, i)
5240                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5241                                 unregister_netdev(adapter->port[i]);
5242
5243                 debugfs_remove_recursive(adapter->debugfs_root);
5244
5245                 /* If we allocated filters, free up state associated with any
5246                  * valid filters ...
5247                  */
5248                 clear_all_filters(adapter);
5249
5250                 if (adapter->flags & FULL_INIT_DONE)
5251                         cxgb_down(adapter);
5252
5253                 if (adapter->flags & USING_MSIX)
5254                         free_msix_info(adapter);
5255                 if (adapter->num_uld || adapter->num_ofld_uld)
5256                         t4_uld_mem_free(adapter);
5257                 free_some_resources(adapter);
5258 #if IS_ENABLED(CONFIG_IPV6)
5259                 t4_cleanup_clip_tbl(adapter);
5260 #endif
5261                 iounmap(adapter->regs);
5262                 if (!is_t4(adapter->params.chip))
5263                         iounmap(adapter->bar2);
5264                 pci_disable_pcie_error_reporting(pdev);
5265                 if ((adapter->flags & DEV_ENABLED)) {
5266                         pci_disable_device(pdev);
5267                         adapter->flags &= ~DEV_ENABLED;
5268                 }
5269                 pci_release_regions(pdev);
5270                 kfree(adapter->mbox_log);
5271                 synchronize_rcu();
5272                 kfree(adapter);
5273         }
5274 #ifdef CONFIG_PCI_IOV
5275         else {
5276                 if (adapter->port[0])
5277                         unregister_netdev(adapter->port[0]);
5278                 iounmap(adapter->regs);
5279                 kfree(adapter->vfinfo);
5280                 kfree(adapter->mbox_log);
5281                 kfree(adapter);
5282                 pci_disable_sriov(pdev);
5283                 pci_release_regions(pdev);
5284         }
5285 #endif
5286 }
5287
5288 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5289  * delivery.  This is essentially a stripped down version of the PCI remove()
5290  * function where we do the minimal amount of work necessary to shutdown any
5291  * further activity.
5292  */
5293 static void shutdown_one(struct pci_dev *pdev)
5294 {
5295         struct adapter *adapter = pci_get_drvdata(pdev);
5296
5297         /* As with remove_one() above (see extended comment), we only want do
5298          * do cleanup on PCI Devices which went all the way through init_one()
5299          * ...
5300          */
5301         if (!adapter) {
5302                 pci_release_regions(pdev);
5303                 return;
5304         }
5305
5306         if (adapter->pf == 4) {
5307                 int i;
5308
5309                 for_each_port(adapter, i)
5310                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5311                                 cxgb_close(adapter->port[i]);
5312
5313                 t4_uld_clean_up(adapter);
5314                 disable_interrupts(adapter);
5315                 disable_msi(adapter);
5316
5317                 t4_sge_stop(adapter);
5318                 if (adapter->flags & FW_OK)
5319                         t4_fw_bye(adapter, adapter->mbox);
5320         }
5321 #ifdef CONFIG_PCI_IOV
5322         else {
5323                 if (adapter->port[0])
5324                         unregister_netdev(adapter->port[0]);
5325                 iounmap(adapter->regs);
5326                 kfree(adapter->vfinfo);
5327                 kfree(adapter->mbox_log);
5328                 kfree(adapter);
5329                 pci_disable_sriov(pdev);
5330                 pci_release_regions(pdev);
5331         }
5332 #endif
5333 }
5334
5335 static struct pci_driver cxgb4_driver = {
5336         .name     = KBUILD_MODNAME,
5337         .id_table = cxgb4_pci_tbl,
5338         .probe    = init_one,
5339         .remove   = remove_one,
5340         .shutdown = shutdown_one,
5341 #ifdef CONFIG_PCI_IOV
5342         .sriov_configure = cxgb4_iov_configure,
5343 #endif
5344         .err_handler = &cxgb4_eeh,
5345 };
5346
5347 static int __init cxgb4_init_module(void)
5348 {
5349         int ret;
5350
5351         /* Debugfs support is optional, just warn if this fails */
5352         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5353         if (!cxgb4_debugfs_root)
5354                 pr_warn("could not create debugfs entry, continuing\n");
5355
5356         ret = pci_register_driver(&cxgb4_driver);
5357         if (ret < 0)
5358                 debugfs_remove(cxgb4_debugfs_root);
5359
5360 #if IS_ENABLED(CONFIG_IPV6)
5361         if (!inet6addr_registered) {
5362                 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5363                 inet6addr_registered = true;
5364         }
5365 #endif
5366
5367         return ret;
5368 }
5369
5370 static void __exit cxgb4_cleanup_module(void)
5371 {
5372 #if IS_ENABLED(CONFIG_IPV6)
5373         if (inet6addr_registered) {
5374                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5375                 inet6addr_registered = false;
5376         }
5377 #endif
5378         pci_unregister_driver(&cxgb4_driver);
5379         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
5380 }
5381
5382 module_init(cxgb4_init_module);
5383 module_exit(cxgb4_cleanup_module);