drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <net/addrconf.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/crash_dump.h>
  68
  69 #include "cxgb4.h"
  70 #include "cxgb4_filter.h"
  71 #include "t4_regs.h"
  72 #include "t4_values.h"
  73 #include "t4_msg.h"
  74 #include "t4fw_api.h"
  75 #include "t4fw_version.h"
  76 #include "cxgb4_dcb.h"
  77 #include "cxgb4_debugfs.h"
  78 #include "clip_tbl.h"
  79 #include "l2t.h"
  80 #include "sched.h"
  81 #include "cxgb4_tc_u32.h"
  82
  83 char cxgb4_driver_name[] = KBUILD_MODNAME;
  84
  85 #ifdef DRV_VERSION
  86 #undef DRV_VERSION
  87 #endif
  88 #define DRV_VERSION "2.0.0-ko"
  89 const char cxgb4_driver_version[] = DRV_VERSION;
  90 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  91
  92 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  93                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  94                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
  95
  96 /* Macros needed to support the PCI Device ID Table ...
  97  */
  98 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  99         static const struct pci_device_id cxgb4_pci_tbl[] = {
 100 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
 101
 102 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 103  * called for both.
 104  */
 105 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 106
 107 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 108                 {PCI_VDEVICE(CHELSIO, (devid)), 4}
 109
 110 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 111                 { 0, } \
 112         }
 113
 114 #include "t4_pci_id_tbl.h"
 115
 116 #define FW4_FNAME "cxgb4/t4fw.bin"
 117 #define FW5_FNAME "cxgb4/t5fw.bin"
 118 #define FW6_FNAME "cxgb4/t6fw.bin"
 119 #define FW4_CFNAME "cxgb4/t4-config.txt"
 120 #define FW5_CFNAME "cxgb4/t5-config.txt"
 121 #define FW6_CFNAME "cxgb4/t6-config.txt"
 122 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 123 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 124 #define PHY_AQ1202_DEVICEID 0x4409
 125 #define PHY_BCM84834_DEVICEID 0x4486
 126
 127 MODULE_DESCRIPTION(DRV_DESC);
 128 MODULE_AUTHOR("Chelsio Communications");
 129 MODULE_LICENSE("Dual BSD/GPL");
 130 MODULE_VERSION(DRV_VERSION);
 131 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 132 MODULE_FIRMWARE(FW4_FNAME);
 133 MODULE_FIRMWARE(FW5_FNAME);
 134 MODULE_FIRMWARE(FW6_FNAME);
 135
 136 /*
 137  * The driver uses the best interrupt scheme available on a platform in the
 138  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 139  * of these schemes the driver may consider as follows:
 140  *
 141  * msi = 2: choose from among all three options
 142  * msi = 1: only consider MSI and INTx interrupts
 143  * msi = 0: force INTx interrupts
 144  */
 145 static int msi = 2;
 146
 147 module_param(msi, int, 0644);
 148 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 149
 150 /*
 151  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 152  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 153  * boundaries.  This is a requirement for many architectures which will throw
 154  * a machine check fault if an attempt is made to access one of the 4-byte IP
 155  * header fields on a non-4-byte boundary.  And it's a major performance issue
 156  * even on some architectures which allow it like some implementations of the
 157  * x86 ISA.  However, some architectures don't mind this and for some very
 158  * edge-case performance sensitive applications (like forwarding large volumes
 159  * of small packets), setting this DMA offset to 0 will decrease the number of
 160  * PCI-E Bus transfers enough to measurably affect performance.
 161  */
 162 static int rx_dma_offset = 2;
 163
 164 /* TX Queue select used to determine what algorithm to use for selecting TX
 165  * queue. Select between the kernel provided function (select_queue=0) or user
 166  * cxgb_select_queue function (select_queue=1)
 167  *
 168  * Default: select_queue=0
 169  */
 170 static int select_queue;
 171 module_param(select_queue, int, 0644);
 172 MODULE_PARM_DESC(select_queue,
 173                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 174
 175 static struct dentry *cxgb4_debugfs_root;
 176
 177 LIST_HEAD(adapter_list);
 178 DEFINE_MUTEX(uld_mutex);
 179
 180 static void link_report(struct net_device *dev)
 181 {
 182         if (!netif_carrier_ok(dev))
 183                 netdev_info(dev, "link down\n");
 184         else {
 185                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 186
 187                 const char *s;
 188                 const struct port_info *p = netdev_priv(dev);
 189
 190                 switch (p->link_cfg.speed) {
 191                 case 100:
 192                         s = "100Mbps";
 193                         break;
 194                 case 1000:
 195                         s = "1Gbps";
 196                         break;
 197                 case 10000:
 198                         s = "10Gbps";
 199                         break;
 200                 case 25000:
 201                         s = "25Gbps";
 202                         break;
 203                 case 40000:
 204                         s = "40Gbps";
 205                         break;
 206                 case 100000:
 207                         s = "100Gbps";
 208                         break;
 209                 default:
 210                         pr_info("%s: unsupported speed: %d\n",
 211                                 dev->name, p->link_cfg.speed);
 212                         return;
 213                 }
 214
 215                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 216                             fc[p->link_cfg.fc]);
 217         }
 218 }
 219
 220 #ifdef CONFIG_CHELSIO_T4_DCB
 221 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 222 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 223 {
 224         struct port_info *pi = netdev_priv(dev);
 225         struct adapter *adap = pi->adapter;
 226         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 227         int i;
 228
 229         /* We use a simple mapping of Port TX Queue Index to DCB
 230          * Priority when we're enabling DCB.
 231          */
 232         for (i = 0; i < pi->nqsets; i++, txq++) {
 233                 u32 name, value;
 234                 int err;
 235
 236                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 237                         FW_PARAMS_PARAM_X_V(
 238                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 239                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 240                 value = enable ? i : 0xffffffff;
 241
 242                 /* Since we can be called while atomic (from "interrupt
 243                  * level") we need to issue the Set Parameters Commannd
 244                  * without sleeping (timeout < 0).
 245                  */
 246                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 247                                             &name, &value,
 248                                             -FW_CMD_MAX_TIMEOUT);
 249
 250                 if (err)
 251                         dev_err(adap->pdev_dev,
 252                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 253                                 enable ? "set" : "unset", pi->port_id, i, -err);
 254                 else
 255                         txq->dcb_prio = value;
 256         }
 257 }
 258
 259 static int cxgb4_dcb_enabled(const struct net_device *dev)
 260 {
 261         struct port_info *pi = netdev_priv(dev);
 262
 263         if (!pi->dcb.enabled)
 264                 return 0;
 265
 266         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 267                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 268 }
 269 #endif /* CONFIG_CHELSIO_T4_DCB */
 270
 271 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 272 {
 273         struct net_device *dev = adapter->port[port_id];
 274
 275         /* Skip changes from disabled ports. */
 276         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 277                 if (link_stat)
 278                         netif_carrier_on(dev);
 279                 else {
 280 #ifdef CONFIG_CHELSIO_T4_DCB
 281                         if (cxgb4_dcb_enabled(dev)) {
 282                                 cxgb4_dcb_state_init(dev);
 283                                 dcb_tx_queue_prio_enable(dev, false);
 284                         }
 285 #endif /* CONFIG_CHELSIO_T4_DCB */
 286                         netif_carrier_off(dev);
 287                 }
 288
 289                 link_report(dev);
 290         }
 291 }
 292
 293 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 294 {
 295         static const char *mod_str[] = {
 296                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 297         };
 298
 299         const struct net_device *dev = adap->port[port_id];
 300         const struct port_info *pi = netdev_priv(dev);
 301
 302         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 303                 netdev_info(dev, "port module unplugged\n");
 304         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 305                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 306         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 307                 netdev_info(dev, "%s: unsupported port module inserted\n",
 308                             dev->name);
 309         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 310                 netdev_info(dev, "%s: unknown port module inserted\n",
 311                             dev->name);
 312         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 313                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 314         else
 315                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 316                             dev->name, pi->mod_type);
 317 }
 318
 319 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 320 module_param(dbfifo_int_thresh, int, 0644);
 321 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 322
 323 /*
 324  * usecs to sleep while draining the dbfifo
 325  */
 326 static int dbfifo_drain_delay = 1000;
 327 module_param(dbfifo_drain_delay, int, 0644);
 328 MODULE_PARM_DESC(dbfifo_drain_delay,
 329                  "usecs to sleep while draining the dbfifo");
 330
 331 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 332 {
 333         struct adapter *adap = pi->adapter;
 334         u64 vec = 0;
 335         bool ucast = false;
 336         struct hash_mac_addr *entry;
 337
 338         /* Calculate the hash vector for the updated list and program it */
 339         list_for_each_entry(entry, &adap->mac_hlist, list) {
 340                 ucast |= is_unicast_ether_addr(entry->addr);
 341                 vec |= (1ULL << hash_mac_addr(entry->addr));
 342         }
 343         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 344                                 vec, false);
 345 }
 346
 347 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 348 {
 349         struct port_info *pi = netdev_priv(netdev);
 350         struct adapter *adap = pi->adapter;
 351         int ret;
 352         u64 mhash = 0;
 353         u64 uhash = 0;
 354         bool free = false;
 355         bool ucast = is_unicast_ether_addr(mac_addr);
 356         const u8 *maclist[1] = {mac_addr};
 357         struct hash_mac_addr *new_entry;
 358
 359         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
 360                                 NULL, ucast ? &uhash : &mhash, false);
 361         if (ret < 0)
 362                 goto out;
 363         /* if hash != 0, then add the addr to hash addr list
 364          * so on the end we will calculate the hash for the
 365          * list and program it
 366          */
 367         if (uhash || mhash) {
 368                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 369                 if (!new_entry)
 370                         return -ENOMEM;
 371                 ether_addr_copy(new_entry->addr, mac_addr);
 372                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 373                 ret = cxgb4_set_addr_hash(pi);
 374         }
 375 out:
 376         return ret < 0 ? ret : 0;
 377 }
 378
 379 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 380 {
 381         struct port_info *pi = netdev_priv(netdev);
 382         struct adapter *adap = pi->adapter;
 383         int ret;
 384         const u8 *maclist[1] = {mac_addr};
 385         struct hash_mac_addr *entry, *tmp;
 386
 387         /* If the MAC address to be removed is in the hash addr
 388          * list, delete it from the list and update hash vector
 389          */
 390         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 391                 if (ether_addr_equal(entry->addr, mac_addr)) {
 392                         list_del(&entry->list);
 393                         kfree(entry);
 394                         return cxgb4_set_addr_hash(pi);
 395                 }
 396         }
 397
 398         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
 399         return ret < 0 ? -EINVAL : 0;
 400 }
 401
 402 /*
 403  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 404  * If @mtu is -1 it is left unchanged.
 405  */
 406 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 407 {
 408         struct port_info *pi = netdev_priv(dev);
 409         struct adapter *adapter = pi->adapter;
 410
 411         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 412         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 413
 414         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 415                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 416                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 417                              sleep_ok);
 418 }
 419
 420 /**
 421  *      link_start - enable a port
 422  *      @dev: the port to enable
 423  *
 424  *      Performs the MAC and PHY actions needed to enable a port.
 425  */
 426 static int link_start(struct net_device *dev)
 427 {
 428         int ret;
 429         struct port_info *pi = netdev_priv(dev);
 430         unsigned int mb = pi->adapter->pf;
 431
 432         /*
 433          * We do not set address filters and promiscuity here, the stack does
 434          * that step explicitly.
 435          */
 436         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 437                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 438         if (ret == 0) {
 439                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 440                                     pi->xact_addr_filt, dev->dev_addr, true,
 441                                     true);
 442                 if (ret >= 0) {
 443                         pi->xact_addr_filt = ret;
 444                         ret = 0;
 445                 }
 446         }
 447         if (ret == 0)
 448                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 449                                     &pi->link_cfg);
 450         if (ret == 0) {
 451                 local_bh_disable();
 452                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 453                                           true, CXGB4_DCB_ENABLED);
 454                 local_bh_enable();
 455         }
 456
 457         return ret;
 458 }
 459
 460 #ifdef CONFIG_CHELSIO_T4_DCB
 461 /* Handle a Data Center Bridging update message from the firmware. */
 462 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 463 {
 464         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 465         struct net_device *dev = adap->port[adap->chan_map[port]];
 466         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 467         int new_dcb_enabled;
 468
 469         cxgb4_dcb_handle_fw_update(adap, pcmd);
 470         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 471
 472         /* If the DCB has become enabled or disabled on the port then we're
 473          * going to need to set up/tear down DCB Priority parameters for the
 474          * TX Queues associated with the port.
 475          */
 476         if (new_dcb_enabled != old_dcb_enabled)
 477                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 478 }
 479 #endif /* CONFIG_CHELSIO_T4_DCB */
 480
 481 /* Response queue handler for the FW event queue.
 482  */
 483 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 484                           const struct pkt_gl *gl)
 485 {
 486         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 487
 488         rsp++;                                          /* skip RSS header */
 489
 490         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 491          */
 492         if (unlikely(opcode == CPL_FW4_MSG &&
 493            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 494                 rsp++;
 495                 opcode = ((const struct rss_header *)rsp)->opcode;
 496                 rsp++;
 497                 if (opcode != CPL_SGE_EGR_UPDATE) {
 498                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 499                                 , opcode);
 500                         goto out;
 501                 }
 502         }
 503
 504         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 505                 const struct cpl_sge_egr_update *p = (void *)rsp;
 506                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 507                 struct sge_txq *txq;
 508
 509                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 510                 txq->restarts++;
 511                 if (txq->q_type == CXGB4_TXQ_ETH) {
 512                         struct sge_eth_txq *eq;
 513
 514                         eq = container_of(txq, struct sge_eth_txq, q);
 515                         netif_tx_wake_queue(eq->txq);
 516                 } else {
 517                         struct sge_uld_txq *oq;
 518
 519                         oq = container_of(txq, struct sge_uld_txq, q);
 520                         tasklet_schedule(&oq->qresume_tsk);
 521                 }
 522         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 523                 const struct cpl_fw6_msg *p = (void *)rsp;
 524
 525 #ifdef CONFIG_CHELSIO_T4_DCB
 526                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 527                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 528                 unsigned int action =
 529                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 530
 531                 if (cmd == FW_PORT_CMD &&
 532                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 533                         int port = FW_PORT_CMD_PORTID_G(
 534                                         be32_to_cpu(pcmd->op_to_portid));
 535                         struct net_device *dev =
 536                                 q->adap->port[q->adap->chan_map[port]];
 537                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 538                                             FW_PORT_CMD_DCBXDIS_F)
 539                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 540                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 541
 542                         cxgb4_dcb_state_fsm(dev, state_input);
 543                 }
 544
 545                 if (cmd == FW_PORT_CMD &&
 546                     action == FW_PORT_ACTION_L2_DCB_CFG)
 547                         dcb_rpl(q->adap, pcmd);
 548                 else
 549 #endif
 550                         if (p->type == 0)
 551                                 t4_handle_fw_rpl(q->adap, p->data);
 552         } else if (opcode == CPL_L2T_WRITE_RPL) {
 553                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 554
 555                 do_l2t_write_rpl(q->adap, p);
 556         } else if (opcode == CPL_SET_TCB_RPL) {
 557                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 558
 559                 filter_rpl(q->adap, p);
 560         } else
 561                 dev_err(q->adap->pdev_dev,
 562                         "unexpected CPL %#x on FW event queue\n", opcode);
 563 out:
 564         return 0;
 565 }
 566
 567 static void disable_msi(struct adapter *adapter)
 568 {
 569         if (adapter->flags & USING_MSIX) {
 570                 pci_disable_msix(adapter->pdev);
 571                 adapter->flags &= ~USING_MSIX;
 572         } else if (adapter->flags & USING_MSI) {
 573                 pci_disable_msi(adapter->pdev);
 574                 adapter->flags &= ~USING_MSI;
 575         }
 576 }
 577
 578 /*
 579  * Interrupt handler for non-data events used with MSI-X.
 580  */
 581 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 582 {
 583         struct adapter *adap = cookie;
 584         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 585
 586         if (v & PFSW_F) {
 587                 adap->swintr = 1;
 588                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 589         }
 590         if (adap->flags & MASTER_PF)
 591                 t4_slow_intr_handler(adap);
 592         return IRQ_HANDLED;
 593 }
 594
 595 /*
 596  * Name the MSI-X interrupts.
 597  */
 598 static void name_msix_vecs(struct adapter *adap)
 599 {
 600         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 601
 602         /* non-data interrupts */
 603         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 604
 605         /* FW events */
 606         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 607                  adap->port[0]->name);
 608
 609         /* Ethernet queues */
 610         for_each_port(adap, j) {
 611                 struct net_device *d = adap->port[j];
 612                 const struct port_info *pi = netdev_priv(d);
 613
 614                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 615                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 616                                  d->name, i);
 617         }
 618 }
 619
 620 static int request_msix_queue_irqs(struct adapter *adap)
 621 {
 622         struct sge *s = &adap->sge;
 623         int err, ethqidx;
 624         int msi_index = 2;
 625
 626         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 627                           adap->msix_info[1].desc, &s->fw_evtq);
 628         if (err)
 629                 return err;
 630
 631         for_each_ethrxq(s, ethqidx) {
 632                 err = request_irq(adap->msix_info[msi_index].vec,
 633                                   t4_sge_intr_msix, 0,
 634                                   adap->msix_info[msi_index].desc,
 635                                   &s->ethrxq[ethqidx].rspq);
 636                 if (err)
 637                         goto unwind;
 638                 msi_index++;
 639         }
 640         return 0;
 641
 642 unwind:
 643         while (--ethqidx >= 0)
 644                 free_irq(adap->msix_info[--msi_index].vec,
 645                          &s->ethrxq[ethqidx].rspq);
 646         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 647         return err;
 648 }
 649
 650 static void free_msix_queue_irqs(struct adapter *adap)
 651 {
 652         int i, msi_index = 2;
 653         struct sge *s = &adap->sge;
 654
 655         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 656         for_each_ethrxq(s, i)
 657                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 658 }
 659
 660 /**
 661  *      cxgb4_write_rss - write the RSS table for a given port
 662  *      @pi: the port
 663  *      @queues: array of queue indices for RSS
 664  *
 665  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 666  *      packets to the Rx queues in @queues.
 667  *      Should never be called before setting up sge eth rx queues
 668  */
 669 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 670 {
 671         u16 *rss;
 672         int i, err;
 673         struct adapter *adapter = pi->adapter;
 674         const struct sge_eth_rxq *rxq;
 675
 676         rxq = &adapter->sge.ethrxq[pi->first_qset];
 677         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 678         if (!rss)
 679                 return -ENOMEM;
 680
 681         /* map the queue indices to queue ids */
 682         for (i = 0; i < pi->rss_size; i++, queues++)
 683                 rss[i] = rxq[*queues].rspq.abs_id;
 684
 685         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 686                                   pi->rss_size, rss, pi->rss_size);
 687         /* If Tunnel All Lookup isn't specified in the global RSS
 688          * Configuration, then we need to specify a default Ingress
 689          * Queue for any ingress packets which aren't hashed.  We'll
 690          * use our first ingress queue ...
 691          */
 692         if (!err)
 693                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 694                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 695                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 696                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 697                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 698                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 699                                        rss[0]);
 700         kfree(rss);
 701         return err;
 702 }
 703
 704 /**
 705  *      setup_rss - configure RSS
 706  *      @adap: the adapter
 707  *
 708  *      Sets up RSS for each port.
 709  */
 710 static int setup_rss(struct adapter *adap)
 711 {
 712         int i, j, err;
 713
 714         for_each_port(adap, i) {
 715                 const struct port_info *pi = adap2pinfo(adap, i);
 716
 717                 /* Fill default values with equal distribution */
 718                 for (j = 0; j < pi->rss_size; j++)
 719                         pi->rss[j] = j % pi->nqsets;
 720
 721                 err = cxgb4_write_rss(pi, pi->rss);
 722                 if (err)
 723                         return err;
 724         }
 725         return 0;
 726 }
 727
 728 /*
 729  * Return the channel of the ingress queue with the given qid.
 730  */
 731 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 732 {
 733         qid -= p->ingr_start;
 734         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 735 }
 736
 737 /*
 738  * Wait until all NAPI handlers are descheduled.
 739  */
 740 static void quiesce_rx(struct adapter *adap)
 741 {
 742         int i;
 743
 744         for (i = 0; i < adap->sge.ingr_sz; i++) {
 745                 struct sge_rspq *q = adap->sge.ingr_map[i];
 746
 747                 if (q && q->handler) {
 748                         napi_disable(&q->napi);
 749                         local_bh_disable();
 750                         while (!cxgb_poll_lock_napi(q))
 751                                 mdelay(1);
 752                         local_bh_enable();
 753                 }
 754
 755         }
 756 }
 757
 758 /* Disable interrupt and napi handler */
 759 static void disable_interrupts(struct adapter *adap)
 760 {
 761         if (adap->flags & FULL_INIT_DONE) {
 762                 t4_intr_disable(adap);
 763                 if (adap->flags & USING_MSIX) {
 764                         free_msix_queue_irqs(adap);
 765                         free_irq(adap->msix_info[0].vec, adap);
 766                 } else {
 767                         free_irq(adap->pdev->irq, adap);
 768                 }
 769                 quiesce_rx(adap);
 770         }
 771 }
 772
 773 /*
 774  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 775  */
 776 static void enable_rx(struct adapter *adap)
 777 {
 778         int i;
 779
 780         for (i = 0; i < adap->sge.ingr_sz; i++) {
 781                 struct sge_rspq *q = adap->sge.ingr_map[i];
 782
 783                 if (!q)
 784                         continue;
 785                 if (q->handler) {
 786                         cxgb_busy_poll_init_lock(q);
 787                         napi_enable(&q->napi);
 788                 }
 789                 /* 0-increment GTS to start the timer and enable interrupts */
 790                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 791                              SEINTARM_V(q->intr_params) |
 792                              INGRESSQID_V(q->cntxt_id));
 793         }
 794 }
 795
 796
 797 static int setup_fw_sge_queues(struct adapter *adap)
 798 {
 799         struct sge *s = &adap->sge;
 800         int err = 0;
 801
 802         bitmap_zero(s->starving_fl, s->egr_sz);
 803         bitmap_zero(s->txq_maperr, s->egr_sz);
 804
 805         if (adap->flags & USING_MSIX)
 806                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 807         else {
 808                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 809                                        NULL, NULL, NULL, -1);
 810                 if (err)
 811                         return err;
 812                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
 813         }
 814
 815         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 816                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
 817         if (err)
 818                 t4_free_sge_resources(adap);
 819         return err;
 820 }
 821
 822 /**
 823  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 824  *      @adap: the adapter
 825  *
 826  *      Determines how many sets of SGE queues to use and initializes them.
 827  *      We support multiple queue sets per port if we have MSI-X, otherwise
 828  *      just one queue set per port.
 829  */
 830 static int setup_sge_queues(struct adapter *adap)
 831 {
 832         int err, i, j;
 833         struct sge *s = &adap->sge;
 834         struct sge_uld_rxq_info *rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
 835         unsigned int cmplqid = 0;
 836
 837         for_each_port(adap, i) {
 838                 struct net_device *dev = adap->port[i];
 839                 struct port_info *pi = netdev_priv(dev);
 840                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
 841                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
 842
 843                 for (j = 0; j < pi->nqsets; j++, q++) {
 844                         if (adap->msi_idx > 0)
 845                                 adap->msi_idx++;
 846                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
 847                                                adap->msi_idx, &q->fl,
 848                                                t4_ethrx_handler,
 849                                                NULL,
 850                                                t4_get_mps_bg_map(adap,
 851                                                                  pi->tx_chan));
 852                         if (err)
 853                                 goto freeout;
 854                         q->rspq.idx = j;
 855                         memset(&q->stats, 0, sizeof(q->stats));
 856                 }
 857                 for (j = 0; j < pi->nqsets; j++, t++) {
 858                         err = t4_sge_alloc_eth_txq(adap, t, dev,
 859                                         netdev_get_tx_queue(dev, j),
 860                                         s->fw_evtq.cntxt_id);
 861                         if (err)
 862                                 goto freeout;
 863                 }
 864         }
 865
 866         for_each_port(adap, i) {
 867                 /* Note that cmplqid below is 0 if we don't
 868                  * have RDMA queues, and that's the right value.
 869                  */
 870                 if (rxq_info)
 871                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 872
 873                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
 874                                             s->fw_evtq.cntxt_id, cmplqid);
 875                 if (err)
 876                         goto freeout;
 877         }
 878
 879         t4_write_reg(adap, is_t4(adap->params.chip) ?
 880                                 MPS_TRC_RSS_CONTROL_A :
 881                                 MPS_T5_TRC_RSS_CONTROL_A,
 882                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
 883                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
 884         return 0;
 885 freeout:
 886         t4_free_sge_resources(adap);
 887         return err;
 888 }
 889
 890 /*
 891  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
 892  * The allocated memory is cleared.
 893  */
 894 void *t4_alloc_mem(size_t size)
 895 {
 896         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
 897
 898         if (!p)
 899                 p = vzalloc(size);
 900         return p;
 901 }
 902
 903 /*
 904  * Free memory allocated through alloc_mem().
 905  */
 906 void t4_free_mem(void *addr)
 907 {
 908         kvfree(addr);
 909 }
 910
 911 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
 912                              void *accel_priv, select_queue_fallback_t fallback)
 913 {
 914         int txq;
 915
 916 #ifdef CONFIG_CHELSIO_T4_DCB
 917         /* If a Data Center Bridging has been successfully negotiated on this
 918          * link then we'll use the skb's priority to map it to a TX Queue.
 919          * The skb's priority is determined via the VLAN Tag Priority Code
 920          * Point field.
 921          */
 922         if (cxgb4_dcb_enabled(dev)) {
 923                 u16 vlan_tci;
 924                 int err;
 925
 926                 err = vlan_get_tag(skb, &vlan_tci);
 927                 if (unlikely(err)) {
 928                         if (net_ratelimit())
 929                                 netdev_warn(dev,
 930                                             "TX Packet without VLAN Tag on DCB Link\n");
 931                         txq = 0;
 932                 } else {
 933                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
 934 #ifdef CONFIG_CHELSIO_T4_FCOE
 935                         if (skb->protocol == htons(ETH_P_FCOE))
 936                                 txq = skb->priority & 0x7;
 937 #endif /* CONFIG_CHELSIO_T4_FCOE */
 938                 }
 939                 return txq;
 940         }
 941 #endif /* CONFIG_CHELSIO_T4_DCB */
 942
 943         if (select_queue) {
 944                 txq = (skb_rx_queue_recorded(skb)
 945                         ? skb_get_rx_queue(skb)
 946                         : smp_processor_id());
 947
 948                 while (unlikely(txq >= dev->real_num_tx_queues))
 949                         txq -= dev->real_num_tx_queues;
 950
 951                 return txq;
 952         }
 953
 954         return fallback(dev, skb) % dev->real_num_tx_queues;
 955 }
 956
 957 static int closest_timer(const struct sge *s, int time)
 958 {
 959         int i, delta, match = 0, min_delta = INT_MAX;
 960
 961         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 962                 delta = time - s->timer_val[i];
 963                 if (delta < 0)
 964                         delta = -delta;
 965                 if (delta < min_delta) {
 966                         min_delta = delta;
 967                         match = i;
 968                 }
 969         }
 970         return match;
 971 }
 972
 973 static int closest_thres(const struct sge *s, int thres)
 974 {
 975         int i, delta, match = 0, min_delta = INT_MAX;
 976
 977         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 978                 delta = thres - s->counter_val[i];
 979                 if (delta < 0)
 980                         delta = -delta;
 981                 if (delta < min_delta) {
 982                         min_delta = delta;
 983                         match = i;
 984                 }
 985         }
 986         return match;
 987 }
 988
 989 /**
 990  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 991  *      @q: the Rx queue
 992  *      @us: the hold-off time in us, or 0 to disable timer
 993  *      @cnt: the hold-off packet count, or 0 to disable counter
 994  *
 995  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
 996  *      one of the two needs to be enabled for the queue to generate interrupts.
 997  */
 998 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
 999                                unsigned int us, unsigned int cnt)
1000 {
1001         struct adapter *adap = q->adap;
1002
1003         if ((us | cnt) == 0)
1004                 cnt = 1;
1005
1006         if (cnt) {
1007                 int err;
1008                 u32 v, new_idx;
1009
1010                 new_idx = closest_thres(&adap->sge, cnt);
1011                 if (q->desc && q->pktcnt_idx != new_idx) {
1012                         /* the queue has already been created, update it */
1013                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1014                             FW_PARAMS_PARAM_X_V(
1015                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1016                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1017                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1018                                             &v, &new_idx);
1019                         if (err)
1020                                 return err;
1021                 }
1022                 q->pktcnt_idx = new_idx;
1023         }
1024
1025         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1026         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1027         return 0;
1028 }
1029
1030 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1031 {
1032         const struct port_info *pi = netdev_priv(dev);
1033         netdev_features_t changed = dev->features ^ features;
1034         int err;
1035
1036         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1037                 return 0;
1038
1039         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1040                             -1, -1, -1,
1041                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1042         if (unlikely(err))
1043                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1044         return err;
1045 }
1046
1047 static int setup_debugfs(struct adapter *adap)
1048 {
1049         if (IS_ERR_OR_NULL(adap->debugfs_root))
1050                 return -1;
1051
1052 #ifdef CONFIG_DEBUG_FS
1053         t4_setup_debugfs(adap);
1054 #endif
1055         return 0;
1056 }
1057
1058 /*
1059  * upper-layer driver support
1060  */
1061
1062 /*
1063  * Allocate an active-open TID and set it to the supplied value.
1064  */
1065 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1066 {
1067         int atid = -1;
1068
1069         spin_lock_bh(&t->atid_lock);
1070         if (t->afree) {
1071                 union aopen_entry *p = t->afree;
1072
1073                 atid = (p - t->atid_tab) + t->atid_base;
1074                 t->afree = p->next;
1075                 p->data = data;
1076                 t->atids_in_use++;
1077         }
1078         spin_unlock_bh(&t->atid_lock);
1079         return atid;
1080 }
1081 EXPORT_SYMBOL(cxgb4_alloc_atid);
1082
1083 /*
1084  * Release an active-open TID.
1085  */
1086 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1087 {
1088         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1089
1090         spin_lock_bh(&t->atid_lock);
1091         p->next = t->afree;
1092         t->afree = p;
1093         t->atids_in_use--;
1094         spin_unlock_bh(&t->atid_lock);
1095 }
1096 EXPORT_SYMBOL(cxgb4_free_atid);
1097
1098 /*
1099  * Allocate a server TID and set it to the supplied value.
1100  */
1101 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1102 {
1103         int stid;
1104
1105         spin_lock_bh(&t->stid_lock);
1106         if (family == PF_INET) {
1107                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1108                 if (stid < t->nstids)
1109                         __set_bit(stid, t->stid_bmap);
1110                 else
1111                         stid = -1;
1112         } else {
1113                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1114                 if (stid < 0)
1115                         stid = -1;
1116         }
1117         if (stid >= 0) {
1118                 t->stid_tab[stid].data = data;
1119                 stid += t->stid_base;
1120                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1121                  * This is equivalent to 4 TIDs. With CLIP enabled it
1122                  * needs 2 TIDs.
1123                  */
1124                 if (family == PF_INET)
1125                         t->stids_in_use++;
1126                 else
1127                         t->stids_in_use += 2;
1128         }
1129         spin_unlock_bh(&t->stid_lock);
1130         return stid;
1131 }
1132 EXPORT_SYMBOL(cxgb4_alloc_stid);
1133
1134 /* Allocate a server filter TID and set it to the supplied value.
1135  */
1136 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1137 {
1138         int stid;
1139
1140         spin_lock_bh(&t->stid_lock);
1141         if (family == PF_INET) {
1142                 stid = find_next_zero_bit(t->stid_bmap,
1143                                 t->nstids + t->nsftids, t->nstids);
1144                 if (stid < (t->nstids + t->nsftids))
1145                         __set_bit(stid, t->stid_bmap);
1146                 else
1147                         stid = -1;
1148         } else {
1149                 stid = -1;
1150         }
1151         if (stid >= 0) {
1152                 t->stid_tab[stid].data = data;
1153                 stid -= t->nstids;
1154                 stid += t->sftid_base;
1155                 t->sftids_in_use++;
1156         }
1157         spin_unlock_bh(&t->stid_lock);
1158         return stid;
1159 }
1160 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1161
1162 /* Release a server TID.
1163  */
1164 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1165 {
1166         /* Is it a server filter TID? */
1167         if (t->nsftids && (stid >= t->sftid_base)) {
1168                 stid -= t->sftid_base;
1169                 stid += t->nstids;
1170         } else {
1171                 stid -= t->stid_base;
1172         }
1173
1174         spin_lock_bh(&t->stid_lock);
1175         if (family == PF_INET)
1176                 __clear_bit(stid, t->stid_bmap);
1177         else
1178                 bitmap_release_region(t->stid_bmap, stid, 1);
1179         t->stid_tab[stid].data = NULL;
1180         if (stid < t->nstids) {
1181                 if (family == PF_INET)
1182                         t->stids_in_use--;
1183                 else
1184                         t->stids_in_use -= 2;
1185         } else {
1186                 t->sftids_in_use--;
1187         }
1188         spin_unlock_bh(&t->stid_lock);
1189 }
1190 EXPORT_SYMBOL(cxgb4_free_stid);
1191
1192 /*
1193  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1194  */
1195 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1196                            unsigned int tid)
1197 {
1198         struct cpl_tid_release *req;
1199
1200         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1201         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1202         INIT_TP_WR(req, tid);
1203         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1204 }
1205
1206 /*
1207  * Queue a TID release request and if necessary schedule a work queue to
1208  * process it.
1209  */
1210 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1211                                     unsigned int tid)
1212 {
1213         void **p = &t->tid_tab[tid];
1214         struct adapter *adap = container_of(t, struct adapter, tids);
1215
1216         spin_lock_bh(&adap->tid_release_lock);
1217         *p = adap->tid_release_head;
1218         /* Low 2 bits encode the Tx channel number */
1219         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1220         if (!adap->tid_release_task_busy) {
1221                 adap->tid_release_task_busy = true;
1222                 queue_work(adap->workq, &adap->tid_release_task);
1223         }
1224         spin_unlock_bh(&adap->tid_release_lock);
1225 }
1226
1227 /*
1228  * Process the list of pending TID release requests.
1229  */
1230 static void process_tid_release_list(struct work_struct *work)
1231 {
1232         struct sk_buff *skb;
1233         struct adapter *adap;
1234
1235         adap = container_of(work, struct adapter, tid_release_task);
1236
1237         spin_lock_bh(&adap->tid_release_lock);
1238         while (adap->tid_release_head) {
1239                 void **p = adap->tid_release_head;
1240                 unsigned int chan = (uintptr_t)p & 3;
1241                 p = (void *)p - chan;
1242
1243                 adap->tid_release_head = *p;
1244                 *p = NULL;
1245                 spin_unlock_bh(&adap->tid_release_lock);
1246
1247                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1248                                          GFP_KERNEL)))
1249                         schedule_timeout_uninterruptible(1);
1250
1251                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1252                 t4_ofld_send(adap, skb);
1253                 spin_lock_bh(&adap->tid_release_lock);
1254         }
1255         adap->tid_release_task_busy = false;
1256         spin_unlock_bh(&adap->tid_release_lock);
1257 }
1258
1259 /*
1260  * Release a TID and inform HW.  If we are unable to allocate the release
1261  * message we defer to a work queue.
1262  */
1263 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1264 {
1265         struct sk_buff *skb;
1266         struct adapter *adap = container_of(t, struct adapter, tids);
1267
1268         WARN_ON(tid >= t->ntids);
1269
1270         if (t->tid_tab[tid]) {
1271                 t->tid_tab[tid] = NULL;
1272                 if (t->hash_base && (tid >= t->hash_base))
1273                         atomic_dec(&t->hash_tids_in_use);
1274                 else
1275                         atomic_dec(&t->tids_in_use);
1276         }
1277
1278         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1279         if (likely(skb)) {
1280                 mk_tid_release(skb, chan, tid);
1281                 t4_ofld_send(adap, skb);
1282         } else
1283                 cxgb4_queue_tid_release(t, chan, tid);
1284 }
1285 EXPORT_SYMBOL(cxgb4_remove_tid);
1286
1287 /*
1288  * Allocate and initialize the TID tables.  Returns 0 on success.
1289  */
1290 static int tid_init(struct tid_info *t)
1291 {
1292         struct adapter *adap = container_of(t, struct adapter, tids);
1293         unsigned int max_ftids = t->nftids + t->nsftids;
1294         unsigned int natids = t->natids;
1295         unsigned int stid_bmap_size;
1296         unsigned int ftid_bmap_size;
1297         size_t size;
1298
1299         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1300         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1301         size = t->ntids * sizeof(*t->tid_tab) +
1302                natids * sizeof(*t->atid_tab) +
1303                t->nstids * sizeof(*t->stid_tab) +
1304                t->nsftids * sizeof(*t->stid_tab) +
1305                stid_bmap_size * sizeof(long) +
1306                max_ftids * sizeof(*t->ftid_tab) +
1307                ftid_bmap_size * sizeof(long);
1308
1309         t->tid_tab = t4_alloc_mem(size);
1310         if (!t->tid_tab)
1311                 return -ENOMEM;
1312
1313         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1314         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1315         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1316         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1317         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1318         spin_lock_init(&t->stid_lock);
1319         spin_lock_init(&t->atid_lock);
1320         spin_lock_init(&t->ftid_lock);
1321
1322         t->stids_in_use = 0;
1323         t->sftids_in_use = 0;
1324         t->afree = NULL;
1325         t->atids_in_use = 0;
1326         atomic_set(&t->tids_in_use, 0);
1327         atomic_set(&t->hash_tids_in_use, 0);
1328
1329         /* Setup the free list for atid_tab and clear the stid bitmap. */
1330         if (natids) {
1331                 while (--natids)
1332                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1333                 t->afree = t->atid_tab;
1334         }
1335
1336         if (is_offload(adap)) {
1337                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1338                 /* Reserve stid 0 for T4/T5 adapters */
1339                 if (!t->stid_base &&
1340                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1341                         __set_bit(0, t->stid_bmap);
1342         }
1343
1344         bitmap_zero(t->ftid_bmap, t->nftids);
1345         return 0;
1346 }
1347
1348 /**
1349  *      cxgb4_create_server - create an IP server
1350  *      @dev: the device
1351  *      @stid: the server TID
1352  *      @sip: local IP address to bind server to
1353  *      @sport: the server's TCP port
1354  *      @queue: queue to direct messages from this server to
1355  *
1356  *      Create an IP server for the given port and address.
1357  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1358  */
1359 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1360                         __be32 sip, __be16 sport, __be16 vlan,
1361                         unsigned int queue)
1362 {
1363         unsigned int chan;
1364         struct sk_buff *skb;
1365         struct adapter *adap;
1366         struct cpl_pass_open_req *req;
1367         int ret;
1368
1369         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1370         if (!skb)
1371                 return -ENOMEM;
1372
1373         adap = netdev2adap(dev);
1374         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1375         INIT_TP_WR(req, 0);
1376         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1377         req->local_port = sport;
1378         req->peer_port = htons(0);
1379         req->local_ip = sip;
1380         req->peer_ip = htonl(0);
1381         chan = rxq_to_chan(&adap->sge, queue);
1382         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1383         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1384                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1385         ret = t4_mgmt_tx(adap, skb);
1386         return net_xmit_eval(ret);
1387 }
1388 EXPORT_SYMBOL(cxgb4_create_server);
1389
1390 /*      cxgb4_create_server6 - create an IPv6 server
1391  *      @dev: the device
1392  *      @stid: the server TID
1393  *      @sip: local IPv6 address to bind server to
1394  *      @sport: the server's TCP port
1395  *      @queue: queue to direct messages from this server to
1396  *
1397  *      Create an IPv6 server for the given port and address.
1398  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1399  */
1400 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1401                          const struct in6_addr *sip, __be16 sport,
1402                          unsigned int queue)
1403 {
1404         unsigned int chan;
1405         struct sk_buff *skb;
1406         struct adapter *adap;
1407         struct cpl_pass_open_req6 *req;
1408         int ret;
1409
1410         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1411         if (!skb)
1412                 return -ENOMEM;
1413
1414         adap = netdev2adap(dev);
1415         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1416         INIT_TP_WR(req, 0);
1417         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1418         req->local_port = sport;
1419         req->peer_port = htons(0);
1420         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1421         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1422         req->peer_ip_hi = cpu_to_be64(0);
1423         req->peer_ip_lo = cpu_to_be64(0);
1424         chan = rxq_to_chan(&adap->sge, queue);
1425         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1426         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1427                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1428         ret = t4_mgmt_tx(adap, skb);
1429         return net_xmit_eval(ret);
1430 }
1431 EXPORT_SYMBOL(cxgb4_create_server6);
1432
1433 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1434                         unsigned int queue, bool ipv6)
1435 {
1436         struct sk_buff *skb;
1437         struct adapter *adap;
1438         struct cpl_close_listsvr_req *req;
1439         int ret;
1440
1441         adap = netdev2adap(dev);
1442
1443         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1444         if (!skb)
1445                 return -ENOMEM;
1446
1447         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1448         INIT_TP_WR(req, 0);
1449         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1450         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1451                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1452         ret = t4_mgmt_tx(adap, skb);
1453         return net_xmit_eval(ret);
1454 }
1455 EXPORT_SYMBOL(cxgb4_remove_server);
1456
1457 /**
1458  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1459  *      @mtus: the HW MTU table
1460  *      @mtu: the target MTU
1461  *      @idx: index of selected entry in the MTU table
1462  *
1463  *      Returns the index and the value in the HW MTU table that is closest to
1464  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1465  *      table, in which case that smallest available value is selected.
1466  */
1467 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1468                             unsigned int *idx)
1469 {
1470         unsigned int i = 0;
1471
1472         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1473                 ++i;
1474         if (idx)
1475                 *idx = i;
1476         return mtus[i];
1477 }
1478 EXPORT_SYMBOL(cxgb4_best_mtu);
1479
1480 /**
1481  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1482  *     @mtus: the HW MTU table
1483  *     @header_size: Header Size
1484  *     @data_size_max: maximum Data Segment Size
1485  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1486  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1487  *
1488  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1489  *     MTU Table based solely on a Maximum MTU parameter, we break that
1490  *     parameter up into a Header Size and Maximum Data Segment Size, and
1491  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1492  *     the Hardware MTU Table which will result in a Data Segment Size with
1493  *     the requested alignment _and_ that MTU isn't "too far" from the
1494  *     closest MTU, then we'll return that rather than the closest MTU.
1495  */
1496 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1497                                     unsigned short header_size,
1498                                     unsigned short data_size_max,
1499                                     unsigned short data_size_align,
1500                                     unsigned int *mtu_idxp)
1501 {
1502         unsigned short max_mtu = header_size + data_size_max;
1503         unsigned short data_size_align_mask = data_size_align - 1;
1504         int mtu_idx, aligned_mtu_idx;
1505
1506         /* Scan the MTU Table till we find an MTU which is larger than our
1507          * Maximum MTU or we reach the end of the table.  Along the way,
1508          * record the last MTU found, if any, which will result in a Data
1509          * Segment Length matching the requested alignment.
1510          */
1511         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1512                 unsigned short data_size = mtus[mtu_idx] - header_size;
1513
1514                 /* If this MTU minus the Header Size would result in a
1515                  * Data Segment Size of the desired alignment, remember it.
1516                  */
1517                 if ((data_size & data_size_align_mask) == 0)
1518                         aligned_mtu_idx = mtu_idx;
1519
1520                 /* If we're not at the end of the Hardware MTU Table and the
1521                  * next element is larger than our Maximum MTU, drop out of
1522                  * the loop.
1523                  */
1524                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1525                         break;
1526         }
1527
1528         /* If we fell out of the loop because we ran to the end of the table,
1529          * then we just have to use the last [largest] entry.
1530          */
1531         if (mtu_idx == NMTUS)
1532                 mtu_idx--;
1533
1534         /* If we found an MTU which resulted in the requested Data Segment
1535          * Length alignment and that's "not far" from the largest MTU which is
1536          * less than or equal to the maximum MTU, then use that.
1537          */
1538         if (aligned_mtu_idx >= 0 &&
1539             mtu_idx - aligned_mtu_idx <= 1)
1540                 mtu_idx = aligned_mtu_idx;
1541
1542         /* If the caller has passed in an MTU Index pointer, pass the
1543          * MTU Index back.  Return the MTU value.
1544          */
1545         if (mtu_idxp)
1546                 *mtu_idxp = mtu_idx;
1547         return mtus[mtu_idx];
1548 }
1549 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1550
1551 /**
1552  *      cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1553  *      @chip: chip type
1554  *      @viid: VI id of the given port
1555  *
1556  *      Return the SMT index for this VI.
1557  */
1558 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1559 {
1560         /* In T4/T5, SMT contains 256 SMAC entries organized in
1561          * 128 rows of 2 entries each.
1562          * In T6, SMT contains 256 SMAC entries in 256 rows.
1563          * TODO: The below code needs to be updated when we add support
1564          * for 256 VFs.
1565          */
1566         if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1567                 return ((viid & 0x7f) << 1);
1568         else
1569                 return (viid & 0x7f);
1570 }
1571 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1572
1573 /**
1574  *      cxgb4_port_chan - get the HW channel of a port
1575  *      @dev: the net device for the port
1576  *
1577  *      Return the HW Tx channel of the given port.
1578  */
1579 unsigned int cxgb4_port_chan(const struct net_device *dev)
1580 {
1581         return netdev2pinfo(dev)->tx_chan;
1582 }
1583 EXPORT_SYMBOL(cxgb4_port_chan);
1584
1585 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1586 {
1587         struct adapter *adap = netdev2adap(dev);
1588         u32 v1, v2, lp_count, hp_count;
1589
1590         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1591         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1592         if (is_t4(adap->params.chip)) {
1593                 lp_count = LP_COUNT_G(v1);
1594                 hp_count = HP_COUNT_G(v1);
1595         } else {
1596                 lp_count = LP_COUNT_T5_G(v1);
1597                 hp_count = HP_COUNT_T5_G(v2);
1598         }
1599         return lpfifo ? lp_count : hp_count;
1600 }
1601 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1602
1603 /**
1604  *      cxgb4_port_viid - get the VI id of a port
1605  *      @dev: the net device for the port
1606  *
1607  *      Return the VI id of the given port.
1608  */
1609 unsigned int cxgb4_port_viid(const struct net_device *dev)
1610 {
1611         return netdev2pinfo(dev)->viid;
1612 }
1613 EXPORT_SYMBOL(cxgb4_port_viid);
1614
1615 /**
1616  *      cxgb4_port_idx - get the index of a port
1617  *      @dev: the net device for the port
1618  *
1619  *      Return the index of the given port.
1620  */
1621 unsigned int cxgb4_port_idx(const struct net_device *dev)
1622 {
1623         return netdev2pinfo(dev)->port_id;
1624 }
1625 EXPORT_SYMBOL(cxgb4_port_idx);
1626
1627 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1628                          struct tp_tcp_stats *v6)
1629 {
1630         struct adapter *adap = pci_get_drvdata(pdev);
1631
1632         spin_lock(&adap->stats_lock);
1633         t4_tp_get_tcp_stats(adap, v4, v6);
1634         spin_unlock(&adap->stats_lock);
1635 }
1636 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1637
1638 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1639                       const unsigned int *pgsz_order)
1640 {
1641         struct adapter *adap = netdev2adap(dev);
1642
1643         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1644         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1645                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1646                      HPZ3_V(pgsz_order[3]));
1647 }
1648 EXPORT_SYMBOL(cxgb4_iscsi_init);
1649
1650 int cxgb4_flush_eq_cache(struct net_device *dev)
1651 {
1652         struct adapter *adap = netdev2adap(dev);
1653
1654         return t4_sge_ctxt_flush(adap, adap->mbox);
1655 }
1656 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1657
1658 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1659 {
1660         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1661         __be64 indices;
1662         int ret;
1663
1664         spin_lock(&adap->win0_lock);
1665         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1666                            sizeof(indices), (__be32 *)&indices,
1667                            T4_MEMORY_READ);
1668         spin_unlock(&adap->win0_lock);
1669         if (!ret) {
1670                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1671                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1672         }
1673         return ret;
1674 }
1675
1676 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1677                         u16 size)
1678 {
1679         struct adapter *adap = netdev2adap(dev);
1680         u16 hw_pidx, hw_cidx;
1681         int ret;
1682
1683         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1684         if (ret)
1685                 goto out;
1686
1687         if (pidx != hw_pidx) {
1688                 u16 delta;
1689                 u32 val;
1690
1691                 if (pidx >= hw_pidx)
1692                         delta = pidx - hw_pidx;
1693                 else
1694                         delta = size - hw_pidx + pidx;
1695
1696                 if (is_t4(adap->params.chip))
1697                         val = PIDX_V(delta);
1698                 else
1699                         val = PIDX_T5_V(delta);
1700                 wmb();
1701                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1702                              QID_V(qid) | val);
1703         }
1704 out:
1705         return ret;
1706 }
1707 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1708
1709 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1710 {
1711         struct adapter *adap;
1712         u32 offset, memtype, memaddr;
1713         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1714         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1715         int ret;
1716
1717         adap = netdev2adap(dev);
1718
1719         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1720
1721         /* Figure out where the offset lands in the Memory Type/Address scheme.
1722          * This code assumes that the memory is laid out starting at offset 0
1723          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1724          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1725          * MC0, and some have both MC0 and MC1.
1726          */
1727         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1728         edc0_size = EDRAM0_SIZE_G(size) << 20;
1729         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1730         edc1_size = EDRAM1_SIZE_G(size) << 20;
1731         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1732         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1733
1734         edc0_end = edc0_size;
1735         edc1_end = edc0_end + edc1_size;
1736         mc0_end = edc1_end + mc0_size;
1737
1738         if (offset < edc0_end) {
1739                 memtype = MEM_EDC0;
1740                 memaddr = offset;
1741         } else if (offset < edc1_end) {
1742                 memtype = MEM_EDC1;
1743                 memaddr = offset - edc0_end;
1744         } else {
1745                 if (offset < mc0_end) {
1746                         memtype = MEM_MC0;
1747                         memaddr = offset - edc1_end;
1748                 } else if (is_t5(adap->params.chip)) {
1749                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1750                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1751                         mc1_end = mc0_end + mc1_size;
1752                         if (offset < mc1_end) {
1753                                 memtype = MEM_MC1;
1754                                 memaddr = offset - mc0_end;
1755                         } else {
1756                                 /* offset beyond the end of any memory */
1757                                 goto err;
1758                         }
1759                 } else {
1760                         /* T4/T6 only has a single memory channel */
1761                         goto err;
1762                 }
1763         }
1764
1765         spin_lock(&adap->win0_lock);
1766         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1767         spin_unlock(&adap->win0_lock);
1768         return ret;
1769
1770 err:
1771         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1772                 stag, offset);
1773         return -EINVAL;
1774 }
1775 EXPORT_SYMBOL(cxgb4_read_tpte);
1776
1777 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1778 {
1779         u32 hi, lo;
1780         struct adapter *adap;
1781
1782         adap = netdev2adap(dev);
1783         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1784         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1785
1786         return ((u64)hi << 32) | (u64)lo;
1787 }
1788 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1789
1790 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1791                          unsigned int qid,
1792                          enum cxgb4_bar2_qtype qtype,
1793                          int user,
1794                          u64 *pbar2_qoffset,
1795                          unsigned int *pbar2_qid)
1796 {
1797         return t4_bar2_sge_qregs(netdev2adap(dev),
1798                                  qid,
1799                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1800                                   ? T4_BAR2_QTYPE_EGRESS
1801                                   : T4_BAR2_QTYPE_INGRESS),
1802                                  user,
1803                                  pbar2_qoffset,
1804                                  pbar2_qid);
1805 }
1806 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1807
1808 static struct pci_driver cxgb4_driver;
1809
1810 static void check_neigh_update(struct neighbour *neigh)
1811 {
1812         const struct device *parent;
1813         const struct net_device *netdev = neigh->dev;
1814
1815         if (netdev->priv_flags & IFF_802_1Q_VLAN)
1816                 netdev = vlan_dev_real_dev(netdev);
1817         parent = netdev->dev.parent;
1818         if (parent && parent->driver == &cxgb4_driver.driver)
1819                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1820 }
1821
1822 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1823                        void *data)
1824 {
1825         switch (event) {
1826         case NETEVENT_NEIGH_UPDATE:
1827                 check_neigh_update(data);
1828                 break;
1829         case NETEVENT_REDIRECT:
1830         default:
1831                 break;
1832         }
1833         return 0;
1834 }
1835
1836 static bool netevent_registered;
1837 static struct notifier_block cxgb4_netevent_nb = {
1838         .notifier_call = netevent_cb
1839 };
1840
1841 static void drain_db_fifo(struct adapter *adap, int usecs)
1842 {
1843         u32 v1, v2, lp_count, hp_count;
1844
1845         do {
1846                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1847                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1848                 if (is_t4(adap->params.chip)) {
1849                         lp_count = LP_COUNT_G(v1);
1850                         hp_count = HP_COUNT_G(v1);
1851                 } else {
1852                         lp_count = LP_COUNT_T5_G(v1);
1853                         hp_count = HP_COUNT_T5_G(v2);
1854                 }
1855
1856                 if (lp_count == 0 && hp_count == 0)
1857                         break;
1858                 set_current_state(TASK_UNINTERRUPTIBLE);
1859                 schedule_timeout(usecs_to_jiffies(usecs));
1860         } while (1);
1861 }
1862
1863 static void disable_txq_db(struct sge_txq *q)
1864 {
1865         unsigned long flags;
1866
1867         spin_lock_irqsave(&q->db_lock, flags);
1868         q->db_disabled = 1;
1869         spin_unlock_irqrestore(&q->db_lock, flags);
1870 }
1871
1872 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1873 {
1874         spin_lock_irq(&q->db_lock);
1875         if (q->db_pidx_inc) {
1876                 /* Make sure that all writes to the TX descriptors
1877                  * are committed before we tell HW about them.
1878                  */
1879                 wmb();
1880                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1881                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1882                 q->db_pidx_inc = 0;
1883         }
1884         q->db_disabled = 0;
1885         spin_unlock_irq(&q->db_lock);
1886 }
1887
1888 static void disable_dbs(struct adapter *adap)
1889 {
1890         int i;
1891
1892         for_each_ethrxq(&adap->sge, i)
1893                 disable_txq_db(&adap->sge.ethtxq[i].q);
1894         if (is_offload(adap)) {
1895                 struct sge_uld_txq_info *txq_info =
1896                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1897
1898                 if (txq_info) {
1899                         for_each_ofldtxq(&adap->sge, i) {
1900                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1901
1902                                 disable_txq_db(&txq->q);
1903                         }
1904                 }
1905         }
1906         for_each_port(adap, i)
1907                 disable_txq_db(&adap->sge.ctrlq[i].q);
1908 }
1909
1910 static void enable_dbs(struct adapter *adap)
1911 {
1912         int i;
1913
1914         for_each_ethrxq(&adap->sge, i)
1915                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1916         if (is_offload(adap)) {
1917                 struct sge_uld_txq_info *txq_info =
1918                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1919
1920                 if (txq_info) {
1921                         for_each_ofldtxq(&adap->sge, i) {
1922                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1923
1924                                 enable_txq_db(adap, &txq->q);
1925                         }
1926                 }
1927         }
1928         for_each_port(adap, i)
1929                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1930 }
1931
1932 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1933 {
1934         enum cxgb4_uld type = CXGB4_ULD_RDMA;
1935
1936         if (adap->uld && adap->uld[type].handle)
1937                 adap->uld[type].control(adap->uld[type].handle, cmd);
1938 }
1939
1940 static void process_db_full(struct work_struct *work)
1941 {
1942         struct adapter *adap;
1943
1944         adap = container_of(work, struct adapter, db_full_task);
1945
1946         drain_db_fifo(adap, dbfifo_drain_delay);
1947         enable_dbs(adap);
1948         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
1949         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1950                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1951                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1952                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1953         else
1954                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1955                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
1956 }
1957
1958 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1959 {
1960         u16 hw_pidx, hw_cidx;
1961         int ret;
1962
1963         spin_lock_irq(&q->db_lock);
1964         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
1965         if (ret)
1966                 goto out;
1967         if (q->db_pidx != hw_pidx) {
1968                 u16 delta;
1969                 u32 val;
1970
1971                 if (q->db_pidx >= hw_pidx)
1972                         delta = q->db_pidx - hw_pidx;
1973                 else
1974                         delta = q->size - hw_pidx + q->db_pidx;
1975
1976                 if (is_t4(adap->params.chip))
1977                         val = PIDX_V(delta);
1978                 else
1979                         val = PIDX_T5_V(delta);
1980                 wmb();
1981                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1982                              QID_V(q->cntxt_id) | val);
1983         }
1984 out:
1985         q->db_disabled = 0;
1986         q->db_pidx_inc = 0;
1987         spin_unlock_irq(&q->db_lock);
1988         if (ret)
1989                 CH_WARN(adap, "DB drop recovery failed.\n");
1990 }
1991
1992 static void recover_all_queues(struct adapter *adap)
1993 {
1994         int i;
1995
1996         for_each_ethrxq(&adap->sge, i)
1997                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
1998         if (is_offload(adap)) {
1999                 struct sge_uld_txq_info *txq_info =
2000                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2001                 if (txq_info) {
2002                         for_each_ofldtxq(&adap->sge, i) {
2003                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2004
2005                                 sync_txq_pidx(adap, &txq->q);
2006                         }
2007                 }
2008         }
2009         for_each_port(adap, i)
2010                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2011 }
2012
2013 static void process_db_drop(struct work_struct *work)
2014 {
2015         struct adapter *adap;
2016
2017         adap = container_of(work, struct adapter, db_drop_task);
2018
2019         if (is_t4(adap->params.chip)) {
2020                 drain_db_fifo(adap, dbfifo_drain_delay);
2021                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2022                 drain_db_fifo(adap, dbfifo_drain_delay);
2023                 recover_all_queues(adap);
2024                 drain_db_fifo(adap, dbfifo_drain_delay);
2025                 enable_dbs(adap);
2026                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2027         } else if (is_t5(adap->params.chip)) {
2028                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2029                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2030                 u16 pidx_inc = dropped_db & 0x1fff;
2031                 u64 bar2_qoffset;
2032                 unsigned int bar2_qid;
2033                 int ret;
2034
2035                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2036                                         0, &bar2_qoffset, &bar2_qid);
2037                 if (ret)
2038                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2039                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2040                 else
2041                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2042                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2043
2044                 /* Re-enable BAR2 WC */
2045                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2046         }
2047
2048         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2049                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2050 }
2051
2052 void t4_db_full(struct adapter *adap)
2053 {
2054         if (is_t4(adap->params.chip)) {
2055                 disable_dbs(adap);
2056                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2057                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2058                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2059                 queue_work(adap->workq, &adap->db_full_task);
2060         }
2061 }
2062
2063 void t4_db_dropped(struct adapter *adap)
2064 {
2065         if (is_t4(adap->params.chip)) {
2066                 disable_dbs(adap);
2067                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2068         }
2069         queue_work(adap->workq, &adap->db_drop_task);
2070 }
2071
2072 void t4_register_netevent_notifier(void)
2073 {
2074         if (!netevent_registered) {
2075                 register_netevent_notifier(&cxgb4_netevent_nb);
2076                 netevent_registered = true;
2077         }
2078 }
2079
2080 static void detach_ulds(struct adapter *adap)
2081 {
2082         unsigned int i;
2083
2084         mutex_lock(&uld_mutex);
2085         list_del(&adap->list_node);
2086         for (i = 0; i < CXGB4_ULD_MAX; i++)
2087                 if (adap->uld && adap->uld[i].handle) {
2088                         adap->uld[i].state_change(adap->uld[i].handle,
2089                                              CXGB4_STATE_DETACH);
2090                         adap->uld[i].handle = NULL;
2091                 }
2092         if (netevent_registered && list_empty(&adapter_list)) {
2093                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2094                 netevent_registered = false;
2095         }
2096         mutex_unlock(&uld_mutex);
2097 }
2098
2099 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2100 {
2101         unsigned int i;
2102
2103         mutex_lock(&uld_mutex);
2104         for (i = 0; i < CXGB4_ULD_MAX; i++)
2105                 if (adap->uld && adap->uld[i].handle)
2106                         adap->uld[i].state_change(adap->uld[i].handle,
2107                                                   new_state);
2108         mutex_unlock(&uld_mutex);
2109 }
2110
2111 #if IS_ENABLED(CONFIG_IPV6)
2112 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2113                                    unsigned long event, void *data)
2114 {
2115         struct inet6_ifaddr *ifa = data;
2116         struct net_device *event_dev = ifa->idev->dev;
2117         const struct device *parent = NULL;
2118 #if IS_ENABLED(CONFIG_BONDING)
2119         struct adapter *adap;
2120 #endif
2121         if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2122                 event_dev = vlan_dev_real_dev(event_dev);
2123 #if IS_ENABLED(CONFIG_BONDING)
2124         if (event_dev->flags & IFF_MASTER) {
2125                 list_for_each_entry(adap, &adapter_list, list_node) {
2126                         switch (event) {
2127                         case NETDEV_UP:
2128                                 cxgb4_clip_get(adap->port[0],
2129                                                (const u32 *)ifa, 1);
2130                                 break;
2131                         case NETDEV_DOWN:
2132                                 cxgb4_clip_release(adap->port[0],
2133                                                    (const u32 *)ifa, 1);
2134                                 break;
2135                         default:
2136                                 break;
2137                         }
2138                 }
2139                 return NOTIFY_OK;
2140         }
2141 #endif
2142
2143         if (event_dev)
2144                 parent = event_dev->dev.parent;
2145
2146         if (parent && parent->driver == &cxgb4_driver.driver) {
2147                 switch (event) {
2148                 case NETDEV_UP:
2149                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2150                         break;
2151                 case NETDEV_DOWN:
2152                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2153                         break;
2154                 default:
2155                         break;
2156                 }
2157         }
2158         return NOTIFY_OK;
2159 }
2160
2161 static bool inet6addr_registered;
2162 static struct notifier_block cxgb4_inet6addr_notifier = {
2163         .notifier_call = cxgb4_inet6addr_handler
2164 };
2165
2166 static void update_clip(const struct adapter *adap)
2167 {
2168         int i;
2169         struct net_device *dev;
2170         int ret;
2171
2172         rcu_read_lock();
2173
2174         for (i = 0; i < MAX_NPORTS; i++) {
2175                 dev = adap->port[i];
2176                 ret = 0;
2177
2178                 if (dev)
2179                         ret = cxgb4_update_root_dev_clip(dev);
2180
2181                 if (ret < 0)
2182                         break;
2183         }
2184         rcu_read_unlock();
2185 }
2186 #endif /* IS_ENABLED(CONFIG_IPV6) */
2187
2188 /**
2189  *      cxgb_up - enable the adapter
2190  *      @adap: adapter being enabled
2191  *
2192  *      Called when the first port is enabled, this function performs the
2193  *      actions necessary to make an adapter operational, such as completing
2194  *      the initialization of HW modules, and enabling interrupts.
2195  *
2196  *      Must be called with the rtnl lock held.
2197  */
2198 static int cxgb_up(struct adapter *adap)
2199 {
2200         int err;
2201
2202         err = setup_sge_queues(adap);
2203         if (err)
2204                 goto out;
2205         err = setup_rss(adap);
2206         if (err)
2207                 goto freeq;
2208
2209         if (adap->flags & USING_MSIX) {
2210                 name_msix_vecs(adap);
2211                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2212                                   adap->msix_info[0].desc, adap);
2213                 if (err)
2214                         goto irq_err;
2215                 err = request_msix_queue_irqs(adap);
2216                 if (err) {
2217                         free_irq(adap->msix_info[0].vec, adap);
2218                         goto irq_err;
2219                 }
2220         } else {
2221                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2222                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2223                                   adap->port[0]->name, adap);
2224                 if (err)
2225                         goto irq_err;
2226         }
2227         enable_rx(adap);
2228         t4_sge_start(adap);
2229         t4_intr_enable(adap);
2230         adap->flags |= FULL_INIT_DONE;
2231         notify_ulds(adap, CXGB4_STATE_UP);
2232 #if IS_ENABLED(CONFIG_IPV6)
2233         update_clip(adap);
2234 #endif
2235         /* Initialize hash mac addr list*/
2236         INIT_LIST_HEAD(&adap->mac_hlist);
2237  out:
2238         return err;
2239  irq_err:
2240         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2241  freeq:
2242         t4_free_sge_resources(adap);
2243         goto out;
2244 }
2245
2246 static void cxgb_down(struct adapter *adapter)
2247 {
2248         cancel_work_sync(&adapter->tid_release_task);
2249         cancel_work_sync(&adapter->db_full_task);
2250         cancel_work_sync(&adapter->db_drop_task);
2251         adapter->tid_release_task_busy = false;
2252         adapter->tid_release_head = NULL;
2253
2254         t4_sge_stop(adapter);
2255         t4_free_sge_resources(adapter);
2256         adapter->flags &= ~FULL_INIT_DONE;
2257 }
2258
2259 /*
2260  * net_device operations
2261  */
2262 static int cxgb_open(struct net_device *dev)
2263 {
2264         int err;
2265         struct port_info *pi = netdev_priv(dev);
2266         struct adapter *adapter = pi->adapter;
2267
2268         netif_carrier_off(dev);
2269
2270         if (!(adapter->flags & FULL_INIT_DONE)) {
2271                 err = cxgb_up(adapter);
2272                 if (err < 0)
2273                         return err;
2274         }
2275
2276         err = link_start(dev);
2277         if (!err)
2278                 netif_tx_start_all_queues(dev);
2279         return err;
2280 }
2281
2282 static int cxgb_close(struct net_device *dev)
2283 {
2284         struct port_info *pi = netdev_priv(dev);
2285         struct adapter *adapter = pi->adapter;
2286
2287         netif_tx_stop_all_queues(dev);
2288         netif_carrier_off(dev);
2289         return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2290 }
2291
2292 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2293                 __be32 sip, __be16 sport, __be16 vlan,
2294                 unsigned int queue, unsigned char port, unsigned char mask)
2295 {
2296         int ret;
2297         struct filter_entry *f;
2298         struct adapter *adap;
2299         int i;
2300         u8 *val;
2301
2302         adap = netdev2adap(dev);
2303
2304         /* Adjust stid to correct filter index */
2305         stid -= adap->tids.sftid_base;
2306         stid += adap->tids.nftids;
2307
2308         /* Check to make sure the filter requested is writable ...
2309          */
2310         f = &adap->tids.ftid_tab[stid];
2311         ret = writable_filter(f);
2312         if (ret)
2313                 return ret;
2314
2315         /* Clear out any old resources being used by the filter before
2316          * we start constructing the new filter.
2317          */
2318         if (f->valid)
2319                 clear_filter(adap, f);
2320
2321         /* Clear out filter specifications */
2322         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2323         f->fs.val.lport = cpu_to_be16(sport);
2324         f->fs.mask.lport  = ~0;
2325         val = (u8 *)&sip;
2326         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2327                 for (i = 0; i < 4; i++) {
2328                         f->fs.val.lip[i] = val[i];
2329                         f->fs.mask.lip[i] = ~0;
2330                 }
2331                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2332                         f->fs.val.iport = port;
2333                         f->fs.mask.iport = mask;
2334                 }
2335         }
2336
2337         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2338                 f->fs.val.proto = IPPROTO_TCP;
2339                 f->fs.mask.proto = ~0;
2340         }
2341
2342         f->fs.dirsteer = 1;
2343         f->fs.iq = queue;
2344         /* Mark filter as locked */
2345         f->locked = 1;
2346         f->fs.rpttid = 1;
2347
2348         ret = set_filter_wr(adap, stid);
2349         if (ret) {
2350                 clear_filter(adap, f);
2351                 return ret;
2352         }
2353
2354         return 0;
2355 }
2356 EXPORT_SYMBOL(cxgb4_create_server_filter);
2357
2358 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2359                 unsigned int queue, bool ipv6)
2360 {
2361         struct filter_entry *f;
2362         struct adapter *adap;
2363
2364         adap = netdev2adap(dev);
2365
2366         /* Adjust stid to correct filter index */
2367         stid -= adap->tids.sftid_base;
2368         stid += adap->tids.nftids;
2369
2370         f = &adap->tids.ftid_tab[stid];
2371         /* Unlock the filter */
2372         f->locked = 0;
2373
2374         return delete_filter(adap, stid);
2375 }
2376 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2377
2378 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2379                                                 struct rtnl_link_stats64 *ns)
2380 {
2381         struct port_stats stats;
2382         struct port_info *p = netdev_priv(dev);
2383         struct adapter *adapter = p->adapter;
2384
2385         /* Block retrieving statistics during EEH error
2386          * recovery. Otherwise, the recovery might fail
2387          * and the PCI device will be removed permanently
2388          */
2389         spin_lock(&adapter->stats_lock);
2390         if (!netif_device_present(dev)) {
2391                 spin_unlock(&adapter->stats_lock);
2392                 return ns;
2393         }
2394         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2395                                  &p->stats_base);
2396         spin_unlock(&adapter->stats_lock);
2397
2398         ns->tx_bytes   = stats.tx_octets;
2399         ns->tx_packets = stats.tx_frames;
2400         ns->rx_bytes   = stats.rx_octets;
2401         ns->rx_packets = stats.rx_frames;
2402         ns->multicast  = stats.rx_mcast_frames;
2403
2404         /* detailed rx_errors */
2405         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2406                                stats.rx_runt;
2407         ns->rx_over_errors   = 0;
2408         ns->rx_crc_errors    = stats.rx_fcs_err;
2409         ns->rx_frame_errors  = stats.rx_symbol_err;
2410         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
2411                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2412                                stats.rx_trunc0 + stats.rx_trunc1 +
2413                                stats.rx_trunc2 + stats.rx_trunc3;
2414         ns->rx_missed_errors = 0;
2415
2416         /* detailed tx_errors */
2417         ns->tx_aborted_errors   = 0;
2418         ns->tx_carrier_errors   = 0;
2419         ns->tx_fifo_errors      = 0;
2420         ns->tx_heartbeat_errors = 0;
2421         ns->tx_window_errors    = 0;
2422
2423         ns->tx_errors = stats.tx_error_frames;
2424         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2425                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2426         return ns;
2427 }
2428
2429 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2430 {
2431         unsigned int mbox;
2432         int ret = 0, prtad, devad;
2433         struct port_info *pi = netdev_priv(dev);
2434         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2435
2436         switch (cmd) {
2437         case SIOCGMIIPHY:
2438                 if (pi->mdio_addr < 0)
2439                         return -EOPNOTSUPP;
2440                 data->phy_id = pi->mdio_addr;
2441                 break;
2442         case SIOCGMIIREG:
2443         case SIOCSMIIREG:
2444                 if (mdio_phy_id_is_c45(data->phy_id)) {
2445                         prtad = mdio_phy_id_prtad(data->phy_id);
2446                         devad = mdio_phy_id_devad(data->phy_id);
2447                 } else if (data->phy_id < 32) {
2448                         prtad = data->phy_id;
2449                         devad = 0;
2450                         data->reg_num &= 0x1f;
2451                 } else
2452                         return -EINVAL;
2453
2454                 mbox = pi->adapter->pf;
2455                 if (cmd == SIOCGMIIREG)
2456                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2457                                          data->reg_num, &data->val_out);
2458                 else
2459                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2460                                          data->reg_num, data->val_in);
2461                 break;
2462         case SIOCGHWTSTAMP:
2463                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2464                                     sizeof(pi->tstamp_config)) ?
2465                         -EFAULT : 0;
2466         case SIOCSHWTSTAMP:
2467                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2468                                    sizeof(pi->tstamp_config)))
2469                         return -EFAULT;
2470
2471                 switch (pi->tstamp_config.rx_filter) {
2472                 case HWTSTAMP_FILTER_NONE:
2473                         pi->rxtstamp = false;
2474                         break;
2475                 case HWTSTAMP_FILTER_ALL:
2476                         pi->rxtstamp = true;
2477                         break;
2478                 default:
2479                         pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2480                         return -ERANGE;
2481                 }
2482
2483                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2484                                     sizeof(pi->tstamp_config)) ?
2485                         -EFAULT : 0;
2486         default:
2487                 return -EOPNOTSUPP;
2488         }
2489         return ret;
2490 }
2491
2492 static void cxgb_set_rxmode(struct net_device *dev)
2493 {
2494         /* unfortunately we can't return errors to the stack */
2495         set_rxmode(dev, -1, false);
2496 }
2497
2498 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2499 {
2500         int ret;
2501         struct port_info *pi = netdev_priv(dev);
2502
2503         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2504                             -1, -1, -1, true);
2505         if (!ret)
2506                 dev->mtu = new_mtu;
2507         return ret;
2508 }
2509
2510 #ifdef CONFIG_PCI_IOV
2511 static int dummy_open(struct net_device *dev)
2512 {
2513         /* Turn carrier off since we don't have to transmit anything on this
2514          * interface.
2515          */
2516         netif_carrier_off(dev);
2517         return 0;
2518 }
2519
2520 /* Fill MAC address that will be assigned by the FW */
2521 static void fill_vf_station_mac_addr(struct adapter *adap)
2522 {
2523         unsigned int i;
2524         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2525         int err;
2526         u8 *na;
2527         u16 a, b;
2528
2529         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2530         if (!err) {
2531                 na = adap->params.vpd.na;
2532                 for (i = 0; i < ETH_ALEN; i++)
2533                         hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2534                                       hex2val(na[2 * i + 1]));
2535                 a = (hw_addr[0] << 8) | hw_addr[1];
2536                 b = (hw_addr[1] << 8) | hw_addr[2];
2537                 a ^= b;
2538                 a |= 0x0200;    /* locally assigned Ethernet MAC address */
2539                 a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2540                 macaddr[0] = a >> 8;
2541                 macaddr[1] = a & 0xff;
2542
2543                 for (i = 2; i < 5; i++)
2544                         macaddr[i] = hw_addr[i + 1];
2545
2546                 for (i = 0; i < adap->num_vfs; i++) {
2547                         macaddr[5] = adap->pf * 16 + i;
2548                         ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr);
2549                 }
2550         }
2551 }
2552
2553 static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2554 {
2555         struct port_info *pi = netdev_priv(dev);
2556         struct adapter *adap = pi->adapter;
2557         int ret;
2558
2559         /* verify MAC addr is valid */
2560         if (!is_valid_ether_addr(mac)) {
2561                 dev_err(pi->adapter->pdev_dev,
2562                         "Invalid Ethernet address %pM for VF %d\n",
2563                         mac, vf);
2564                 return -EINVAL;
2565         }
2566
2567         dev_info(pi->adapter->pdev_dev,
2568                  "Setting MAC %pM on VF %d\n", mac, vf);
2569         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2570         if (!ret)
2571                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2572         return ret;
2573 }
2574
2575 static int cxgb_get_vf_config(struct net_device *dev,
2576                               int vf, struct ifla_vf_info *ivi)
2577 {
2578         struct port_info *pi = netdev_priv(dev);
2579         struct adapter *adap = pi->adapter;
2580
2581         if (vf >= adap->num_vfs)
2582                 return -EINVAL;
2583         ivi->vf = vf;
2584         ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
2585         return 0;
2586 }
2587 #endif
2588
2589 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2590 {
2591         int ret;
2592         struct sockaddr *addr = p;
2593         struct port_info *pi = netdev_priv(dev);
2594
2595         if (!is_valid_ether_addr(addr->sa_data))
2596                 return -EADDRNOTAVAIL;
2597
2598         ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
2599                             pi->xact_addr_filt, addr->sa_data, true, true);
2600         if (ret < 0)
2601                 return ret;
2602
2603         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2604         pi->xact_addr_filt = ret;
2605         return 0;
2606 }
2607
2608 #ifdef CONFIG_NET_POLL_CONTROLLER
2609 static void cxgb_netpoll(struct net_device *dev)
2610 {
2611         struct port_info *pi = netdev_priv(dev);
2612         struct adapter *adap = pi->adapter;
2613
2614         if (adap->flags & USING_MSIX) {
2615                 int i;
2616                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2617
2618                 for (i = pi->nqsets; i; i--, rx++)
2619                         t4_sge_intr_msix(0, &rx->rspq);
2620         } else
2621                 t4_intr_handler(adap)(0, adap);
2622 }
2623 #endif
2624
2625 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2626 {
2627         struct port_info *pi = netdev_priv(dev);
2628         struct adapter *adap = pi->adapter;
2629         struct sched_class *e;
2630         struct ch_sched_params p;
2631         struct ch_sched_queue qe;
2632         u32 req_rate;
2633         int err = 0;
2634
2635         if (!can_sched(dev))
2636                 return -ENOTSUPP;
2637
2638         if (index < 0 || index > pi->nqsets - 1)
2639                 return -EINVAL;
2640
2641         if (!(adap->flags & FULL_INIT_DONE)) {
2642                 dev_err(adap->pdev_dev,
2643                         "Failed to rate limit on queue %d. Link Down?\n",
2644                         index);
2645                 return -EINVAL;
2646         }
2647
2648         /* Convert from Mbps to Kbps */
2649         req_rate = rate << 10;
2650
2651         /* Max rate is 10 Gbps */
2652         if (req_rate >= SCHED_MAX_RATE_KBPS) {
2653                 dev_err(adap->pdev_dev,
2654                         "Invalid rate %u Mbps, Max rate is %u Gbps\n",
2655                         rate, SCHED_MAX_RATE_KBPS);
2656                 return -ERANGE;
2657         }
2658
2659         /* First unbind the queue from any existing class */
2660         memset(&qe, 0, sizeof(qe));
2661         qe.queue = index;
2662         qe.class = SCHED_CLS_NONE;
2663
2664         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2665         if (err) {
2666                 dev_err(adap->pdev_dev,
2667                         "Unbinding Queue %d on port %d fail. Err: %d\n",
2668                         index, pi->port_id, err);
2669                 return err;
2670         }
2671
2672         /* Queue already unbound */
2673         if (!req_rate)
2674                 return 0;
2675
2676         /* Fetch any available unused or matching scheduling class */
2677         memset(&p, 0, sizeof(p));
2678         p.type = SCHED_CLASS_TYPE_PACKET;
2679         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
2680         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
2681         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2682         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2683         p.u.params.channel  = pi->tx_chan;
2684         p.u.params.class    = SCHED_CLS_NONE;
2685         p.u.params.minrate  = 0;
2686         p.u.params.maxrate  = req_rate;
2687         p.u.params.weight   = 0;
2688         p.u.params.pktsize  = dev->mtu;
2689
2690         e = cxgb4_sched_class_alloc(dev, &p);
2691         if (!e)
2692                 return -ENOMEM;
2693
2694         /* Bind the queue to a scheduling class */
2695         memset(&qe, 0, sizeof(qe));
2696         qe.queue = index;
2697         qe.class = e->idx;
2698
2699         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2700         if (err)
2701                 dev_err(adap->pdev_dev,
2702                         "Queue rate limiting failed. Err: %d\n", err);
2703         return err;
2704 }
2705
2706 static int cxgb_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
2707                          struct tc_to_netdev *tc)
2708 {
2709         struct port_info *pi = netdev2pinfo(dev);
2710         struct adapter *adap = netdev2adap(dev);
2711
2712         if (!(adap->flags & FULL_INIT_DONE)) {
2713                 dev_err(adap->pdev_dev,
2714                         "Failed to setup tc on port %d. Link Down?\n",
2715                         pi->port_id);
2716                 return -EINVAL;
2717         }
2718
2719         if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
2720             tc->type == TC_SETUP_CLSU32) {
2721                 switch (tc->cls_u32->command) {
2722                 case TC_CLSU32_NEW_KNODE:
2723                 case TC_CLSU32_REPLACE_KNODE:
2724                         return cxgb4_config_knode(dev, proto, tc->cls_u32);
2725                 case TC_CLSU32_DELETE_KNODE:
2726                         return cxgb4_delete_knode(dev, proto, tc->cls_u32);
2727                 default:
2728                         return -EOPNOTSUPP;
2729                 }
2730         }
2731
2732         return -EOPNOTSUPP;
2733 }
2734
2735 static const struct net_device_ops cxgb4_netdev_ops = {
2736         .ndo_open             = cxgb_open,
2737         .ndo_stop             = cxgb_close,
2738         .ndo_start_xmit       = t4_eth_xmit,
2739         .ndo_select_queue     = cxgb_select_queue,
2740         .ndo_get_stats64      = cxgb_get_stats,
2741         .ndo_set_rx_mode      = cxgb_set_rxmode,
2742         .ndo_set_mac_address  = cxgb_set_mac_addr,
2743         .ndo_set_features     = cxgb_set_features,
2744         .ndo_validate_addr    = eth_validate_addr,
2745         .ndo_do_ioctl         = cxgb_ioctl,
2746         .ndo_change_mtu       = cxgb_change_mtu,
2747 #ifdef CONFIG_NET_POLL_CONTROLLER
2748         .ndo_poll_controller  = cxgb_netpoll,
2749 #endif
2750 #ifdef CONFIG_CHELSIO_T4_FCOE
2751         .ndo_fcoe_enable      = cxgb_fcoe_enable,
2752         .ndo_fcoe_disable     = cxgb_fcoe_disable,
2753 #endif /* CONFIG_CHELSIO_T4_FCOE */
2754 #ifdef CONFIG_NET_RX_BUSY_POLL
2755         .ndo_busy_poll        = cxgb_busy_poll,
2756 #endif
2757         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
2758         .ndo_setup_tc         = cxgb_setup_tc,
2759 };
2760
2761 #ifdef CONFIG_PCI_IOV
2762 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
2763         .ndo_open             = dummy_open,
2764         .ndo_set_vf_mac       = cxgb_set_vf_mac,
2765         .ndo_get_vf_config    = cxgb_get_vf_config,
2766 };
2767 #endif
2768
2769 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2770 {
2771         struct adapter *adapter = netdev2adap(dev);
2772
2773         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
2774         strlcpy(info->version, cxgb4_driver_version,
2775                 sizeof(info->version));
2776         strlcpy(info->bus_info, pci_name(adapter->pdev),
2777                 sizeof(info->bus_info));
2778 }
2779
2780 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
2781         .get_drvinfo       = get_drvinfo,
2782 };
2783
2784 void t4_fatal_err(struct adapter *adap)
2785 {
2786         t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
2787         t4_intr_disable(adap);
2788         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
2789 }
2790
2791 static void setup_memwin(struct adapter *adap)
2792 {
2793         u32 nic_win_base = t4_get_util_window(adap);
2794
2795         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
2796 }
2797
2798 static void setup_memwin_rdma(struct adapter *adap)
2799 {
2800         if (adap->vres.ocq.size) {
2801                 u32 start;
2802                 unsigned int sz_kb;
2803
2804                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
2805                 start &= PCI_BASE_ADDRESS_MEM_MASK;
2806                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
2807                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
2808                 t4_write_reg(adap,
2809                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
2810                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
2811                 t4_write_reg(adap,
2812                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
2813                              adap->vres.ocq.start);
2814                 t4_read_reg(adap,
2815                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
2816         }
2817 }
2818
2819 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
2820 {
2821         u32 v;
2822         int ret;
2823
2824         /* get device capabilities */
2825         memset(c, 0, sizeof(*c));
2826         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2827                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
2828         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
2829         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
2830         if (ret < 0)
2831                 return ret;
2832
2833         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
2834                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
2835         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
2836         if (ret < 0)
2837                 return ret;
2838
2839         ret = t4_config_glbl_rss(adap, adap->pf,
2840                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
2841                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
2842                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
2843         if (ret < 0)
2844                 return ret;
2845
2846         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
2847                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
2848                           FW_CMD_CAP_PF);
2849         if (ret < 0)
2850                 return ret;
2851
2852         t4_sge_init(adap);
2853
2854         /* tweak some settings */
2855         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
2856         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
2857         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
2858         v = t4_read_reg(adap, TP_PIO_DATA_A);
2859         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
2860
2861         /* first 4 Tx modulation queues point to consecutive Tx channels */
2862         adap->params.tp.tx_modq_map = 0xE4;
2863         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
2864                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
2865
2866         /* associate each Tx modulation queue with consecutive Tx channels */
2867         v = 0x84218421;
2868         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2869                           &v, 1, TP_TX_SCHED_HDR_A);
2870         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2871                           &v, 1, TP_TX_SCHED_FIFO_A);
2872         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2873                           &v, 1, TP_TX_SCHED_PCMD_A);
2874
2875 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
2876         if (is_offload(adap)) {
2877                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
2878                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2879                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2880                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2881                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
2882                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
2883                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2884                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2885                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
2886                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
2887         }
2888
2889         /* get basic stuff going */
2890         return t4_early_init(adap, adap->pf);
2891 }
2892
2893 /*
2894  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
2895  */
2896 #define MAX_ATIDS 8192U
2897
2898 /*
2899  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
2900  *
2901  * If the firmware we're dealing with has Configuration File support, then
2902  * we use that to perform all configuration
2903  */
2904
2905 /*
2906  * Tweak configuration based on module parameters, etc.  Most of these have
2907  * defaults assigned to them by Firmware Configuration Files (if we're using
2908  * them) but need to be explicitly set if we're using hard-coded
2909  * initialization.  But even in the case of using Firmware Configuration
2910  * Files, we'd like to expose the ability to change these via module
2911  * parameters so these are essentially common tweaks/settings for
2912  * Configuration Files and hard-coded initialization ...
2913  */
2914 static int adap_init0_tweaks(struct adapter *adapter)
2915 {
2916         /*
2917          * Fix up various Host-Dependent Parameters like Page Size, Cache
2918          * Line Size, etc.  The firmware default is for a 4KB Page Size and
2919          * 64B Cache Line Size ...
2920          */
2921         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
2922
2923         /*
2924          * Process module parameters which affect early initialization.
2925          */
2926         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
2927                 dev_err(&adapter->pdev->dev,
2928                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
2929                         rx_dma_offset);
2930                 rx_dma_offset = 2;
2931         }
2932         t4_set_reg_field(adapter, SGE_CONTROL_A,
2933                          PKTSHIFT_V(PKTSHIFT_M),
2934                          PKTSHIFT_V(rx_dma_offset));
2935
2936         /*
2937          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
2938          * adds the pseudo header itself.
2939          */
2940         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
2941                                CSUM_HAS_PSEUDO_HDR_F, 0);
2942
2943         return 0;
2944 }
2945
2946 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
2947  * unto themselves and they contain their own firmware to perform their
2948  * tasks ...
2949  */
2950 static int phy_aq1202_version(const u8 *phy_fw_data,
2951                               size_t phy_fw_size)
2952 {
2953         int offset;
2954
2955         /* At offset 0x8 you're looking for the primary image's
2956          * starting offset which is 3 Bytes wide
2957          *
2958          * At offset 0xa of the primary image, you look for the offset
2959          * of the DRAM segment which is 3 Bytes wide.
2960          *
2961          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
2962          * wide
2963          */
2964         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
2965         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
2966         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
2967
2968         offset = le24(phy_fw_data + 0x8) << 12;
2969         offset = le24(phy_fw_data + offset + 0xa);
2970         return be16(phy_fw_data + offset + 0x27e);
2971
2972         #undef be16
2973         #undef le16
2974         #undef le24
2975 }
2976
2977 static struct info_10gbt_phy_fw {
2978         unsigned int phy_fw_id;         /* PCI Device ID */
2979         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
2980         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
2981         int phy_flash;                  /* Has FLASH for PHY Firmware */
2982 } phy_info_array[] = {
2983         {
2984                 PHY_AQ1202_DEVICEID,
2985                 PHY_AQ1202_FIRMWARE,
2986                 phy_aq1202_version,
2987                 1,
2988         },
2989         {
2990                 PHY_BCM84834_DEVICEID,
2991                 PHY_BCM84834_FIRMWARE,
2992                 NULL,
2993                 0,
2994         },
2995         { 0, NULL, NULL },
2996 };
2997
2998 static struct info_10gbt_phy_fw *find_phy_info(int devid)
2999 {
3000         int i;
3001
3002         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3003                 if (phy_info_array[i].phy_fw_id == devid)
3004                         return &phy_info_array[i];
3005         }
3006         return NULL;
3007 }
3008
3009 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
3010  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
3011  * we return a negative error number.  If we transfer new firmware we return 1
3012  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
3013  */
3014 static int adap_init0_phy(struct adapter *adap)
3015 {
3016         const struct firmware *phyf;
3017         int ret;
3018         struct info_10gbt_phy_fw *phy_info;
3019
3020         /* Use the device ID to determine which PHY file to flash.
3021          */
3022         phy_info = find_phy_info(adap->pdev->device);
3023         if (!phy_info) {
3024                 dev_warn(adap->pdev_dev,
3025                          "No PHY Firmware file found for this PHY\n");
3026                 return -EOPNOTSUPP;
3027         }
3028
3029         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3030          * use that. The adapter firmware provides us with a memory buffer
3031          * where we can load a PHY firmware file from the host if we want to
3032          * override the PHY firmware File in flash.
3033          */
3034         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3035                                       adap->pdev_dev);
3036         if (ret < 0) {
3037                 /* For adapters without FLASH attached to PHY for their
3038                  * firmware, it's obviously a fatal error if we can't get the
3039                  * firmware to the adapter.  For adapters with PHY firmware
3040                  * FLASH storage, it's worth a warning if we can't find the
3041                  * PHY Firmware but we'll neuter the error ...
3042                  */
3043                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3044                         "/lib/firmware/%s, error %d\n",
3045                         phy_info->phy_fw_file, -ret);
3046                 if (phy_info->phy_flash) {
3047                         int cur_phy_fw_ver = 0;
3048
3049                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3050                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3051                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
3052                         ret = 0;
3053                 }
3054
3055                 return ret;
3056         }
3057
3058         /* Load PHY Firmware onto adapter.
3059          */
3060         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3061                              phy_info->phy_fw_version,
3062                              (u8 *)phyf->data, phyf->size);
3063         if (ret < 0)
3064                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3065                         -ret);
3066         else if (ret > 0) {
3067                 int new_phy_fw_ver = 0;
3068
3069                 if (phy_info->phy_fw_version)
3070                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3071                                                                   phyf->size);
3072                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3073                          "Firmware /lib/firmware/%s, version %#x\n",
3074                          phy_info->phy_fw_file, new_phy_fw_ver);
3075         }
3076
3077         release_firmware(phyf);
3078
3079         return ret;
3080 }
3081
3082 /*
3083  * Attempt to initialize the adapter via a Firmware Configuration File.
3084  */
3085 static int adap_init0_config(struct adapter *adapter, int reset)
3086 {
3087         struct fw_caps_config_cmd caps_cmd;
3088         const struct firmware *cf;
3089         unsigned long mtype = 0, maddr = 0;
3090         u32 finiver, finicsum, cfcsum;
3091         int ret;
3092         int config_issued = 0;
3093         char *fw_config_file, fw_config_file_path[256];
3094         char *config_name = NULL;
3095
3096         /*
3097          * Reset device if necessary.
3098          */
3099         if (reset) {
3100                 ret = t4_fw_reset(adapter, adapter->mbox,
3101                                   PIORSTMODE_F | PIORST_F);
3102                 if (ret < 0)
3103                         goto bye;
3104         }
3105
3106         /* If this is a 10Gb/s-BT adapter make sure the chip-external
3107          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
3108          * to be performed after any global adapter RESET above since some
3109          * PHYs only have local RAM copies of the PHY firmware.
3110          */
3111         if (is_10gbt_device(adapter->pdev->device)) {
3112                 ret = adap_init0_phy(adapter);
3113                 if (ret < 0)
3114                         goto bye;
3115         }
3116         /*
3117          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3118          * then use that.  Otherwise, use the configuration file stored
3119          * in the adapter flash ...
3120          */
3121         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3122         case CHELSIO_T4:
3123                 fw_config_file = FW4_CFNAME;
3124                 break;
3125         case CHELSIO_T5:
3126                 fw_config_file = FW5_CFNAME;
3127                 break;
3128         case CHELSIO_T6:
3129                 fw_config_file = FW6_CFNAME;
3130                 break;
3131         default:
3132                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3133                        adapter->pdev->device);
3134                 ret = -EINVAL;
3135                 goto bye;
3136         }
3137
3138         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3139         if (ret < 0) {
3140                 config_name = "On FLASH";
3141                 mtype = FW_MEMTYPE_CF_FLASH;
3142                 maddr = t4_flash_cfg_addr(adapter);
3143         } else {
3144                 u32 params[7], val[7];
3145
3146                 sprintf(fw_config_file_path,
3147                         "/lib/firmware/%s", fw_config_file);
3148                 config_name = fw_config_file_path;
3149
3150                 if (cf->size >= FLASH_CFG_MAX_SIZE)
3151                         ret = -ENOMEM;
3152                 else {
3153                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3154                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3155                         ret = t4_query_params(adapter, adapter->mbox,
3156                                               adapter->pf, 0, 1, params, val);
3157                         if (ret == 0) {
3158                                 /*
3159                                  * For t4_memory_rw() below addresses and
3160                                  * sizes have to be in terms of multiples of 4
3161                                  * bytes.  So, if the Configuration File isn't
3162                                  * a multiple of 4 bytes in length we'll have
3163                                  * to write that out separately since we can't
3164                                  * guarantee that the bytes following the
3165                                  * residual byte in the buffer returned by
3166                                  * request_firmware() are zeroed out ...
3167                                  */
3168                                 size_t resid = cf->size & 0x3;
3169                                 size_t size = cf->size & ~0x3;
3170                                 __be32 *data = (__be32 *)cf->data;
3171
3172                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3173                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3174
3175                                 spin_lock(&adapter->win0_lock);
3176                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3177                                                    size, data, T4_MEMORY_WRITE);
3178                                 if (ret == 0 && resid != 0) {
3179                                         union {
3180                                                 __be32 word;
3181                                                 char buf[4];
3182                                         } last;
3183                                         int i;
3184
3185                                         last.word = data[size >> 2];
3186                                         for (i = resid; i < 4; i++)
3187                                                 last.buf[i] = 0;
3188                                         ret = t4_memory_rw(adapter, 0, mtype,
3189                                                            maddr + size,
3190                                                            4, &last.word,
3191                                                            T4_MEMORY_WRITE);
3192                                 }
3193                                 spin_unlock(&adapter->win0_lock);
3194                         }
3195                 }
3196
3197                 release_firmware(cf);
3198                 if (ret)
3199                         goto bye;
3200         }
3201
3202         /*
3203          * Issue a Capability Configuration command to the firmware to get it
3204          * to parse the Configuration File.  We don't use t4_fw_config_file()
3205          * because we want the ability to modify various features after we've
3206          * processed the configuration file ...
3207          */
3208         memset(&caps_cmd, 0, sizeof(caps_cmd));
3209         caps_cmd.op_to_write =
3210                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3211                       FW_CMD_REQUEST_F |
3212                       FW_CMD_READ_F);
3213         caps_cmd.cfvalid_to_len16 =
3214                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3215                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3216                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3217                       FW_LEN16(caps_cmd));
3218         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3219                          &caps_cmd);
3220
3221         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3222          * Configuration File in FLASH), our last gasp effort is to use the
3223          * Firmware Configuration File which is embedded in the firmware.  A
3224          * very few early versions of the firmware didn't have one embedded
3225          * but we can ignore those.
3226          */
3227         if (ret == -ENOENT) {
3228                 memset(&caps_cmd, 0, sizeof(caps_cmd));
3229                 caps_cmd.op_to_write =
3230                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3231                                         FW_CMD_REQUEST_F |
3232                                         FW_CMD_READ_F);
3233                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3234                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3235                                 sizeof(caps_cmd), &caps_cmd);
3236                 config_name = "Firmware Default";
3237         }
3238
3239         config_issued = 1;
3240         if (ret < 0)
3241                 goto bye;
3242
3243         finiver = ntohl(caps_cmd.finiver);
3244         finicsum = ntohl(caps_cmd.finicsum);
3245         cfcsum = ntohl(caps_cmd.cfcsum);
3246         if (finicsum != cfcsum)
3247                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3248                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3249                          finicsum, cfcsum);
3250
3251         /*
3252          * And now tell the firmware to use the configuration we just loaded.
3253          */
3254         caps_cmd.op_to_write =
3255                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3256                       FW_CMD_REQUEST_F |
3257                       FW_CMD_WRITE_F);
3258         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3259         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3260                          NULL);
3261         if (ret < 0)
3262                 goto bye;
3263
3264         /*
3265          * Tweak configuration based on system architecture, module
3266          * parameters, etc.
3267          */
3268         ret = adap_init0_tweaks(adapter);
3269         if (ret < 0)
3270                 goto bye;
3271
3272         /*
3273          * And finally tell the firmware to initialize itself using the
3274          * parameters from the Configuration File.
3275          */
3276         ret = t4_fw_initialize(adapter, adapter->mbox);
3277         if (ret < 0)
3278                 goto bye;
3279
3280         /* Emit Firmware Configuration File information and return
3281          * successfully.
3282          */
3283         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3284                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3285                  config_name, finiver, cfcsum);
3286         return 0;
3287
3288         /*
3289          * Something bad happened.  Return the error ...  (If the "error"
3290          * is that there's no Configuration File on the adapter we don't
3291          * want to issue a warning since this is fairly common.)
3292          */
3293 bye:
3294         if (config_issued && ret != -ENOENT)
3295                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3296                          config_name, -ret);
3297         return ret;
3298 }
3299
3300 static struct fw_info fw_info_array[] = {
3301         {
3302                 .chip = CHELSIO_T4,
3303                 .fs_name = FW4_CFNAME,
3304                 .fw_mod_name = FW4_FNAME,
3305                 .fw_hdr = {
3306                         .chip = FW_HDR_CHIP_T4,
3307                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3308                         .intfver_nic = FW_INTFVER(T4, NIC),
3309                         .intfver_vnic = FW_INTFVER(T4, VNIC),
3310                         .intfver_ri = FW_INTFVER(T4, RI),
3311                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3312                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
3313                 },
3314         }, {
3315                 .chip = CHELSIO_T5,
3316                 .fs_name = FW5_CFNAME,
3317                 .fw_mod_name = FW5_FNAME,
3318                 .fw_hdr = {
3319                         .chip = FW_HDR_CHIP_T5,
3320                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3321                         .intfver_nic = FW_INTFVER(T5, NIC),
3322                         .intfver_vnic = FW_INTFVER(T5, VNIC),
3323                         .intfver_ri = FW_INTFVER(T5, RI),
3324                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3325                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
3326                 },
3327         }, {
3328                 .chip = CHELSIO_T6,
3329                 .fs_name = FW6_CFNAME,
3330                 .fw_mod_name = FW6_FNAME,
3331                 .fw_hdr = {
3332                         .chip = FW_HDR_CHIP_T6,
3333                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3334                         .intfver_nic = FW_INTFVER(T6, NIC),
3335                         .intfver_vnic = FW_INTFVER(T6, VNIC),
3336                         .intfver_ofld = FW_INTFVER(T6, OFLD),
3337                         .intfver_ri = FW_INTFVER(T6, RI),
3338                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3339                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3340                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3341                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
3342                 },
3343         }
3344
3345 };
3346
3347 static struct fw_info *find_fw_info(int chip)
3348 {
3349         int i;
3350
3351         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3352                 if (fw_info_array[i].chip == chip)
3353                         return &fw_info_array[i];
3354         }
3355         return NULL;
3356 }
3357
3358 /*
3359  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3360  */
3361 static int adap_init0(struct adapter *adap)
3362 {
3363         int ret;
3364         u32 v, port_vec;
3365         enum dev_state state;
3366         u32 params[7], val[7];
3367         struct fw_caps_config_cmd caps_cmd;
3368         int reset = 1;
3369
3370         /* Grab Firmware Device Log parameters as early as possible so we have
3371          * access to it for debugging, etc.
3372          */
3373         ret = t4_init_devlog_params(adap);
3374         if (ret < 0)
3375                 return ret;
3376
3377         /* Contact FW, advertising Master capability */
3378         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
3379                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
3380         if (ret < 0) {
3381                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3382                         ret);
3383                 return ret;
3384         }
3385         if (ret == adap->mbox)
3386                 adap->flags |= MASTER_PF;
3387
3388         /*
3389          * If we're the Master PF Driver and the device is uninitialized,
3390          * then let's consider upgrading the firmware ...  (We always want
3391          * to check the firmware version number in order to A. get it for
3392          * later reporting and B. to warn if the currently loaded firmware
3393          * is excessively mismatched relative to the driver.)
3394          */
3395         t4_get_fw_version(adap, &adap->params.fw_vers);
3396         t4_get_bs_version(adap, &adap->params.bs_vers);
3397         t4_get_tp_version(adap, &adap->params.tp_vers);
3398         t4_get_exprom_version(adap, &adap->params.er_vers);
3399
3400         ret = t4_check_fw_version(adap);
3401         /* If firmware is too old (not supported by driver) force an update. */
3402         if (ret)
3403                 state = DEV_STATE_UNINIT;
3404         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3405                 struct fw_info *fw_info;
3406                 struct fw_hdr *card_fw;
3407                 const struct firmware *fw;
3408                 const u8 *fw_data = NULL;
3409                 unsigned int fw_size = 0;
3410
3411                 /* This is the firmware whose headers the driver was compiled
3412                  * against
3413                  */
3414                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3415                 if (fw_info == NULL) {
3416                         dev_err(adap->pdev_dev,
3417                                 "unable to get firmware info for chip %d.\n",
3418                                 CHELSIO_CHIP_VERSION(adap->params.chip));
3419                         return -EINVAL;
3420                 }
3421
3422                 /* allocate memory to read the header of the firmware on the
3423                  * card
3424                  */
3425                 card_fw = t4_alloc_mem(sizeof(*card_fw));
3426
3427                 /* Get FW from from /lib/firmware/ */
3428                 ret = request_firmware(&fw, fw_info->fw_mod_name,
3429                                        adap->pdev_dev);
3430                 if (ret < 0) {
3431                         dev_err(adap->pdev_dev,
3432                                 "unable to load firmware image %s, error %d\n",
3433                                 fw_info->fw_mod_name, ret);
3434                 } else {
3435                         fw_data = fw->data;
3436                         fw_size = fw->size;
3437                 }
3438
3439                 /* upgrade FW logic */
3440                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3441                                  state, &reset);
3442
3443                 /* Cleaning up */
3444                 release_firmware(fw);
3445                 t4_free_mem(card_fw);
3446
3447                 if (ret < 0)
3448                         goto bye;
3449         }
3450
3451         /*
3452          * Grab VPD parameters.  This should be done after we establish a
3453          * connection to the firmware since some of the VPD parameters
3454          * (notably the Core Clock frequency) are retrieved via requests to
3455          * the firmware.  On the other hand, we need these fairly early on
3456          * so we do this right after getting ahold of the firmware.
3457          */
3458         ret = t4_get_vpd_params(adap, &adap->params.vpd);
3459         if (ret < 0)
3460                 goto bye;
3461
3462         /*
3463          * Find out what ports are available to us.  Note that we need to do
3464          * this before calling adap_init0_no_config() since it needs nports
3465          * and portvec ...
3466          */
3467         v =
3468             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3469             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3470         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3471         if (ret < 0)
3472                 goto bye;
3473
3474         adap->params.nports = hweight32(port_vec);
3475         adap->params.portvec = port_vec;
3476
3477         /* If the firmware is initialized already, emit a simply note to that
3478          * effect. Otherwise, it's time to try initializing the adapter.
3479          */
3480         if (state == DEV_STATE_INIT) {
3481                 dev_info(adap->pdev_dev, "Coming up as %s: "\
3482                          "Adapter already initialized\n",
3483                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3484         } else {
3485                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3486                          "Initializing adapter\n");
3487
3488                 /* Find out whether we're dealing with a version of the
3489                  * firmware which has configuration file support.
3490                  */
3491                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3492                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3493                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3494                                       params, val);
3495
3496                 /* If the firmware doesn't support Configuration Files,
3497                  * return an error.
3498                  */
3499                 if (ret < 0) {
3500                         dev_err(adap->pdev_dev, "firmware doesn't support "
3501                                 "Firmware Configuration Files\n");
3502                         goto bye;
3503                 }
3504
3505                 /* The firmware provides us with a memory buffer where we can
3506                  * load a Configuration File from the host if we want to
3507                  * override the Configuration File in flash.
3508                  */
3509                 ret = adap_init0_config(adap, reset);
3510                 if (ret == -ENOENT) {
3511                         dev_err(adap->pdev_dev, "no Configuration File "
3512                                 "present on adapter.\n");
3513                         goto bye;
3514                 }
3515                 if (ret < 0) {
3516                         dev_err(adap->pdev_dev, "could not initialize "
3517                                 "adapter, error %d\n", -ret);
3518                         goto bye;
3519                 }
3520         }
3521
3522         /* Give the SGE code a chance to pull in anything that it needs ...
3523          * Note that this must be called after we retrieve our VPD parameters
3524          * in order to know how to convert core ticks to seconds, etc.
3525          */
3526         ret = t4_sge_init(adap);
3527         if (ret < 0)
3528                 goto bye;
3529
3530         if (is_bypass_device(adap->pdev->device))
3531                 adap->params.bypass = 1;
3532
3533         /*
3534          * Grab some of our basic fundamental operating parameters.
3535          */
3536 #define FW_PARAM_DEV(param) \
3537         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3538         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3539
3540 #define FW_PARAM_PFVF(param) \
3541         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3542         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
3543         FW_PARAMS_PARAM_Y_V(0) | \
3544         FW_PARAMS_PARAM_Z_V(0)
3545
3546         params[0] = FW_PARAM_PFVF(EQ_START);
3547         params[1] = FW_PARAM_PFVF(L2T_START);
3548         params[2] = FW_PARAM_PFVF(L2T_END);
3549         params[3] = FW_PARAM_PFVF(FILTER_START);
3550         params[4] = FW_PARAM_PFVF(FILTER_END);
3551         params[5] = FW_PARAM_PFVF(IQFLINT_START);
3552         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3553         if (ret < 0)
3554                 goto bye;
3555         adap->sge.egr_start = val[0];
3556         adap->l2t_start = val[1];
3557         adap->l2t_end = val[2];
3558         adap->tids.ftid_base = val[3];
3559         adap->tids.nftids = val[4] - val[3] + 1;
3560         adap->sge.ingr_start = val[5];
3561
3562         /* qids (ingress/egress) returned from firmware can be anywhere
3563          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3564          * Hence driver needs to allocate memory for this range to
3565          * store the queue info. Get the highest IQFLINT/EQ index returned
3566          * in FW_EQ_*_CMD.alloc command.
3567          */
3568         params[0] = FW_PARAM_PFVF(EQ_END);
3569         params[1] = FW_PARAM_PFVF(IQFLINT_END);
3570         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3571         if (ret < 0)
3572                 goto bye;
3573         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3574         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3575
3576         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3577                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
3578         if (!adap->sge.egr_map) {
3579                 ret = -ENOMEM;
3580                 goto bye;
3581         }
3582
3583         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3584                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3585         if (!adap->sge.ingr_map) {
3586                 ret = -ENOMEM;
3587                 goto bye;
3588         }
3589
3590         /* Allocate the memory for the vaious egress queue bitmaps
3591          * ie starving_fl, txq_maperr and blocked_fl.
3592          */
3593         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3594                                         sizeof(long), GFP_KERNEL);
3595         if (!adap->sge.starving_fl) {
3596                 ret = -ENOMEM;
3597                 goto bye;
3598         }
3599
3600         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3601                                        sizeof(long), GFP_KERNEL);
3602         if (!adap->sge.txq_maperr) {
3603                 ret = -ENOMEM;
3604                 goto bye;
3605         }
3606
3607 #ifdef CONFIG_DEBUG_FS
3608         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3609                                        sizeof(long), GFP_KERNEL);
3610         if (!adap->sge.blocked_fl) {
3611                 ret = -ENOMEM;
3612                 goto bye;
3613         }
3614 #endif
3615
3616         params[0] = FW_PARAM_PFVF(CLIP_START);
3617         params[1] = FW_PARAM_PFVF(CLIP_END);
3618         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3619         if (ret < 0)
3620                 goto bye;
3621         adap->clipt_start = val[0];
3622         adap->clipt_end = val[1];
3623
3624         /* We don't yet have a PARAMs calls to retrieve the number of Traffic
3625          * Classes supported by the hardware/firmware so we hard code it here
3626          * for now.
3627          */
3628         adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
3629
3630         /* query params related to active filter region */
3631         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3632         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3633         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3634         /* If Active filter size is set we enable establishing
3635          * offload connection through firmware work request
3636          */
3637         if ((val[0] != val[1]) && (ret >= 0)) {
3638                 adap->flags |= FW_OFLD_CONN;
3639                 adap->tids.aftid_base = val[0];
3640                 adap->tids.aftid_end = val[1];
3641         }
3642
3643         /* If we're running on newer firmware, let it know that we're
3644          * prepared to deal with encapsulated CPL messages.  Older
3645          * firmware won't understand this and we'll just get
3646          * unencapsulated messages ...
3647          */
3648         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3649         val[0] = 1;
3650         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3651
3652         /*
3653          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3654          * capability.  Earlier versions of the firmware didn't have the
3655          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3656          * permission to use ULPTX MEMWRITE DSGL.
3657          */
3658         if (is_t4(adap->params.chip)) {
3659                 adap->params.ulptx_memwrite_dsgl = false;
3660         } else {
3661                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3662                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3663                                       1, params, val);
3664                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3665         }
3666
3667         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
3668         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
3669         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3670                               1, params, val);
3671         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
3672
3673         /*
3674          * Get device capabilities so we can determine what resources we need
3675          * to manage.
3676          */
3677         memset(&caps_cmd, 0, sizeof(caps_cmd));
3678         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3679                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
3680         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3681         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3682                          &caps_cmd);
3683         if (ret < 0)
3684                 goto bye;
3685
3686         if (caps_cmd.ofldcaps) {
3687                 /* query offload-related parameters */
3688                 params[0] = FW_PARAM_DEV(NTID);
3689                 params[1] = FW_PARAM_PFVF(SERVER_START);
3690                 params[2] = FW_PARAM_PFVF(SERVER_END);
3691                 params[3] = FW_PARAM_PFVF(TDDP_START);
3692                 params[4] = FW_PARAM_PFVF(TDDP_END);
3693                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3694                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3695                                       params, val);
3696                 if (ret < 0)
3697                         goto bye;
3698                 adap->tids.ntids = val[0];
3699                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3700                 adap->tids.stid_base = val[1];
3701                 adap->tids.nstids = val[2] - val[1] + 1;
3702                 /*
3703                  * Setup server filter region. Divide the available filter
3704                  * region into two parts. Regular filters get 1/3rd and server
3705                  * filters get 2/3rd part. This is only enabled if workarond
3706                  * path is enabled.
3707                  * 1. For regular filters.
3708                  * 2. Server filter: This are special filters which are used
3709                  * to redirect SYN packets to offload queue.
3710                  */
3711                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3712                         adap->tids.sftid_base = adap->tids.ftid_base +
3713                                         DIV_ROUND_UP(adap->tids.nftids, 3);
3714                         adap->tids.nsftids = adap->tids.nftids -
3715                                          DIV_ROUND_UP(adap->tids.nftids, 3);
3716                         adap->tids.nftids = adap->tids.sftid_base -
3717                                                 adap->tids.ftid_base;
3718                 }
3719                 adap->vres.ddp.start = val[3];
3720                 adap->vres.ddp.size = val[4] - val[3] + 1;
3721                 adap->params.ofldq_wr_cred = val[5];
3722
3723                 adap->params.offload = 1;
3724                 adap->num_ofld_uld += 1;
3725         }
3726         if (caps_cmd.rdmacaps) {
3727                 params[0] = FW_PARAM_PFVF(STAG_START);
3728                 params[1] = FW_PARAM_PFVF(STAG_END);
3729                 params[2] = FW_PARAM_PFVF(RQ_START);
3730                 params[3] = FW_PARAM_PFVF(RQ_END);
3731                 params[4] = FW_PARAM_PFVF(PBL_START);
3732                 params[5] = FW_PARAM_PFVF(PBL_END);
3733                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3734                                       params, val);
3735                 if (ret < 0)
3736                         goto bye;
3737                 adap->vres.stag.start = val[0];
3738                 adap->vres.stag.size = val[1] - val[0] + 1;
3739                 adap->vres.rq.start = val[2];
3740                 adap->vres.rq.size = val[3] - val[2] + 1;
3741                 adap->vres.pbl.start = val[4];
3742                 adap->vres.pbl.size = val[5] - val[4] + 1;
3743
3744                 params[0] = FW_PARAM_PFVF(SQRQ_START);
3745                 params[1] = FW_PARAM_PFVF(SQRQ_END);
3746                 params[2] = FW_PARAM_PFVF(CQ_START);
3747                 params[3] = FW_PARAM_PFVF(CQ_END);
3748                 params[4] = FW_PARAM_PFVF(OCQ_START);
3749                 params[5] = FW_PARAM_PFVF(OCQ_END);
3750                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
3751                                       val);
3752                 if (ret < 0)
3753                         goto bye;
3754                 adap->vres.qp.start = val[0];
3755                 adap->vres.qp.size = val[1] - val[0] + 1;
3756                 adap->vres.cq.start = val[2];
3757                 adap->vres.cq.size = val[3] - val[2] + 1;
3758                 adap->vres.ocq.start = val[4];
3759                 adap->vres.ocq.size = val[5] - val[4] + 1;
3760
3761                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3762                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3763                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
3764                                       val);
3765                 if (ret < 0) {
3766                         adap->params.max_ordird_qp = 8;
3767                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3768                         ret = 0;
3769                 } else {
3770                         adap->params.max_ordird_qp = val[0];
3771                         adap->params.max_ird_adapter = val[1];
3772                 }
3773                 dev_info(adap->pdev_dev,
3774                          "max_ordird_qp %d max_ird_adapter %d\n",
3775                          adap->params.max_ordird_qp,
3776                          adap->params.max_ird_adapter);
3777                 adap->num_ofld_uld += 2;
3778         }
3779         if (caps_cmd.iscsicaps) {
3780                 params[0] = FW_PARAM_PFVF(ISCSI_START);
3781                 params[1] = FW_PARAM_PFVF(ISCSI_END);
3782                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
3783                                       params, val);
3784                 if (ret < 0)
3785                         goto bye;
3786                 adap->vres.iscsi.start = val[0];
3787                 adap->vres.iscsi.size = val[1] - val[0] + 1;
3788                 /* LIO target and cxgb4i initiaitor */
3789                 adap->num_ofld_uld += 2;
3790         }
3791         if (caps_cmd.cryptocaps) {
3792                 /* Should query params here...TODO */
3793                 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
3794                 adap->num_uld += 1;
3795         }
3796 #undef FW_PARAM_PFVF
3797 #undef FW_PARAM_DEV
3798
3799         /* The MTU/MSS Table is initialized by now, so load their values.  If
3800          * we're initializing the adapter, then we'll make any modifications
3801          * we want to the MTU/MSS Table and also initialize the congestion
3802          * parameters.
3803          */
3804         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
3805         if (state != DEV_STATE_INIT) {
3806                 int i;
3807
3808                 /* The default MTU Table contains values 1492 and 1500.
3809                  * However, for TCP, it's better to have two values which are
3810                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
3811                  * This allows us to have a TCP Data Payload which is a
3812                  * multiple of 8 regardless of what combination of TCP Options
3813                  * are in use (always a multiple of 4 bytes) which is
3814                  * important for performance reasons.  For instance, if no
3815                  * options are in use, then we have a 20-byte IP header and a
3816                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
3817                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
3818                  * which is not a multiple of 8.  So using an MSS of 1488 in
3819                  * this case results in a TCP Data Payload of 1448 bytes which
3820                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
3821                  * Stamps have been negotiated, then an MTU of 1500 bytes
3822                  * results in a TCP Data Payload of 1448 bytes which, as
3823                  * above, is a multiple of 8 bytes ...
3824                  */
3825                 for (i = 0; i < NMTUS; i++)
3826                         if (adap->params.mtus[i] == 1492) {
3827                                 adap->params.mtus[i] = 1488;
3828                                 break;
3829                         }
3830
3831                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3832                              adap->params.b_wnd);
3833         }
3834         t4_init_sge_params(adap);
3835         adap->flags |= FW_OK;
3836         t4_init_tp_params(adap);
3837         return 0;
3838
3839         /*
3840          * Something bad happened.  If a command timed out or failed with EIO
3841          * FW does not operate within its spec or something catastrophic
3842          * happened to HW/FW, stop issuing commands.
3843          */
3844 bye:
3845         kfree(adap->sge.egr_map);
3846         kfree(adap->sge.ingr_map);
3847         kfree(adap->sge.starving_fl);
3848         kfree(adap->sge.txq_maperr);
3849 #ifdef CONFIG_DEBUG_FS
3850         kfree(adap->sge.blocked_fl);
3851 #endif
3852         if (ret != -ETIMEDOUT && ret != -EIO)
3853                 t4_fw_bye(adap, adap->mbox);
3854         return ret;
3855 }
3856
3857 /* EEH callbacks */
3858
3859 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
3860                                          pci_channel_state_t state)
3861 {
3862         int i;
3863         struct adapter *adap = pci_get_drvdata(pdev);
3864
3865         if (!adap)
3866                 goto out;
3867
3868         rtnl_lock();
3869         adap->flags &= ~FW_OK;
3870         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
3871         spin_lock(&adap->stats_lock);
3872         for_each_port(adap, i) {
3873                 struct net_device *dev = adap->port[i];
3874
3875                 netif_device_detach(dev);
3876                 netif_carrier_off(dev);
3877         }
3878         spin_unlock(&adap->stats_lock);
3879         disable_interrupts(adap);
3880         if (adap->flags & FULL_INIT_DONE)
3881                 cxgb_down(adap);
3882         rtnl_unlock();
3883         if ((adap->flags & DEV_ENABLED)) {
3884                 pci_disable_device(pdev);
3885                 adap->flags &= ~DEV_ENABLED;
3886         }
3887 out:    return state == pci_channel_io_perm_failure ?
3888                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3889 }
3890
3891 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
3892 {
3893         int i, ret;
3894         struct fw_caps_config_cmd c;
3895         struct adapter *adap = pci_get_drvdata(pdev);
3896
3897         if (!adap) {
3898                 pci_restore_state(pdev);
3899                 pci_save_state(pdev);
3900                 return PCI_ERS_RESULT_RECOVERED;
3901         }
3902
3903         if (!(adap->flags & DEV_ENABLED)) {
3904                 if (pci_enable_device(pdev)) {
3905                         dev_err(&pdev->dev, "Cannot reenable PCI "
3906                                             "device after reset\n");
3907                         return PCI_ERS_RESULT_DISCONNECT;
3908                 }
3909                 adap->flags |= DEV_ENABLED;
3910         }
3911
3912         pci_set_master(pdev);
3913         pci_restore_state(pdev);
3914         pci_save_state(pdev);
3915         pci_cleanup_aer_uncorrect_error_status(pdev);
3916
3917         if (t4_wait_dev_ready(adap->regs) < 0)
3918                 return PCI_ERS_RESULT_DISCONNECT;
3919         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
3920                 return PCI_ERS_RESULT_DISCONNECT;
3921         adap->flags |= FW_OK;
3922         if (adap_init1(adap, &c))
3923                 return PCI_ERS_RESULT_DISCONNECT;
3924
3925         for_each_port(adap, i) {
3926                 struct port_info *p = adap2pinfo(adap, i);
3927
3928                 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
3929                                   NULL, NULL);
3930                 if (ret < 0)
3931                         return PCI_ERS_RESULT_DISCONNECT;
3932                 p->viid = ret;
3933                 p->xact_addr_filt = -1;
3934         }
3935
3936         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3937                      adap->params.b_wnd);
3938         setup_memwin(adap);
3939         if (cxgb_up(adap))
3940                 return PCI_ERS_RESULT_DISCONNECT;
3941         return PCI_ERS_RESULT_RECOVERED;
3942 }
3943
3944 static void eeh_resume(struct pci_dev *pdev)
3945 {
3946         int i;
3947         struct adapter *adap = pci_get_drvdata(pdev);
3948
3949         if (!adap)
3950                 return;
3951
3952         rtnl_lock();
3953         for_each_port(adap, i) {
3954                 struct net_device *dev = adap->port[i];
3955
3956                 if (netif_running(dev)) {
3957                         link_start(dev);
3958                         cxgb_set_rxmode(dev);
3959                 }
3960                 netif_device_attach(dev);
3961         }
3962         rtnl_unlock();
3963 }
3964
3965 static const struct pci_error_handlers cxgb4_eeh = {
3966         .error_detected = eeh_err_detected,
3967         .slot_reset     = eeh_slot_reset,
3968         .resume         = eeh_resume,
3969 };
3970
3971 /* Return true if the Link Configuration supports "High Speeds" (those greater
3972  * than 1Gb/s).
3973  */
3974 static inline bool is_x_10g_port(const struct link_config *lc)
3975 {
3976         unsigned int speeds, high_speeds;
3977
3978         speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));
3979         high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
3980
3981         return high_speeds != 0;
3982 }
3983
3984 /*
3985  * Perform default configuration of DMA queues depending on the number and type
3986  * of ports we found and the number of available CPUs.  Most settings can be
3987  * modified by the admin prior to actual use.
3988  */
3989 static void cfg_queues(struct adapter *adap)
3990 {
3991         struct sge *s = &adap->sge;
3992         int i = 0, n10g = 0, qidx = 0;
3993 #ifndef CONFIG_CHELSIO_T4_DCB
3994         int q10g = 0;
3995 #endif
3996
3997         /* Reduce memory usage in kdump environment, disable all offload.
3998          */
3999         if (is_kdump_kernel()) {
4000                 adap->params.offload = 0;
4001                 adap->params.crypto = 0;
4002         } else if (is_uld(adap) && t4_uld_mem_alloc(adap)) {
4003                 adap->params.offload = 0;
4004                 adap->params.crypto = 0;
4005         }
4006
4007         n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4008 #ifdef CONFIG_CHELSIO_T4_DCB
4009         /* For Data Center Bridging support we need to be able to support up
4010          * to 8 Traffic Priorities; each of which will be assigned to its
4011          * own TX Queue in order to prevent Head-Of-Line Blocking.
4012          */
4013         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4014                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4015                         MAX_ETH_QSETS, adap->params.nports * 8);
4016                 BUG_ON(1);
4017         }
4018
4019         for_each_port(adap, i) {
4020                 struct port_info *pi = adap2pinfo(adap, i);
4021
4022                 pi->first_qset = qidx;
4023                 pi->nqsets = 8;
4024                 qidx += pi->nqsets;
4025         }
4026 #else /* !CONFIG_CHELSIO_T4_DCB */
4027         /*
4028          * We default to 1 queue per non-10G port and up to # of cores queues
4029          * per 10G port.
4030          */
4031         if (n10g)
4032                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4033         if (q10g > netif_get_num_default_rss_queues())
4034                 q10g = netif_get_num_default_rss_queues();
4035
4036         for_each_port(adap, i) {
4037                 struct port_info *pi = adap2pinfo(adap, i);
4038
4039                 pi->first_qset = qidx;
4040                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4041                 qidx += pi->nqsets;
4042         }
4043 #endif /* !CONFIG_CHELSIO_T4_DCB */
4044
4045         s->ethqsets = qidx;
4046         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
4047
4048         if (is_uld(adap)) {
4049                 /*
4050                  * For offload we use 1 queue/channel if all ports are up to 1G,
4051                  * otherwise we divide all available queues amongst the channels
4052                  * capped by the number of available cores.
4053                  */
4054                 if (n10g) {
4055                         i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
4056                         s->ofldqsets = roundup(i, adap->params.nports);
4057                 } else {
4058                         s->ofldqsets = adap->params.nports;
4059                 }
4060         }
4061
4062         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4063                 struct sge_eth_rxq *r = &s->ethrxq[i];
4064
4065                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4066                 r->fl.size = 72;
4067         }
4068
4069         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4070                 s->ethtxq[i].q.size = 1024;
4071
4072         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4073                 s->ctrlq[i].q.size = 512;
4074
4075         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4076         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
4077 }
4078
4079 /*
4080  * Reduce the number of Ethernet queues across all ports to at most n.
4081  * n provides at least one queue per port.
4082  */
4083 static void reduce_ethqs(struct adapter *adap, int n)
4084 {
4085         int i;
4086         struct port_info *pi;
4087
4088         while (n < adap->sge.ethqsets)
4089                 for_each_port(adap, i) {
4090                         pi = adap2pinfo(adap, i);
4091                         if (pi->nqsets > 1) {
4092                                 pi->nqsets--;
4093                                 adap->sge.ethqsets--;
4094                                 if (adap->sge.ethqsets <= n)
4095                                         break;
4096                         }
4097                 }
4098
4099         n = 0;
4100         for_each_port(adap, i) {
4101                 pi = adap2pinfo(adap, i);
4102                 pi->first_qset = n;
4103                 n += pi->nqsets;
4104         }
4105 }
4106
4107 static int get_msix_info(struct adapter *adap)
4108 {
4109         struct uld_msix_info *msix_info;
4110         unsigned int max_ingq = 0;
4111
4112         if (is_offload(adap))
4113                 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
4114         if (is_pci_uld(adap))
4115                 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
4116
4117         if (!max_ingq)
4118                 goto out;
4119
4120         msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
4121         if (!msix_info)
4122                 return -ENOMEM;
4123
4124         adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
4125                                                  sizeof(long), GFP_KERNEL);
4126         if (!adap->msix_bmap_ulds.msix_bmap) {
4127                 kfree(msix_info);
4128                 return -ENOMEM;
4129         }
4130         spin_lock_init(&adap->msix_bmap_ulds.lock);
4131         adap->msix_info_ulds = msix_info;
4132 out:
4133         return 0;
4134 }
4135
4136 static void free_msix_info(struct adapter *adap)
4137 {
4138         if (!(adap->num_uld && adap->num_ofld_uld))
4139                 return;
4140
4141         kfree(adap->msix_info_ulds);
4142         kfree(adap->msix_bmap_ulds.msix_bmap);
4143 }
4144
4145 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4146 #define EXTRA_VECS 2
4147
4148 static int enable_msix(struct adapter *adap)
4149 {
4150         int ofld_need = 0, uld_need = 0;
4151         int i, j, want, need, allocated;
4152         struct sge *s = &adap->sge;
4153         unsigned int nchan = adap->params.nports;
4154         struct msix_entry *entries;
4155         int max_ingq = MAX_INGQ;
4156
4157         if (is_pci_uld(adap))
4158                 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
4159         if (is_offload(adap))
4160                 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
4161         entries = kmalloc(sizeof(*entries) * (max_ingq + 1),
4162                           GFP_KERNEL);
4163         if (!entries)
4164                 return -ENOMEM;
4165
4166         /* map for msix */
4167         if (get_msix_info(adap)) {
4168                 adap->params.offload = 0;
4169                 adap->params.crypto = 0;
4170         }
4171
4172         for (i = 0; i < max_ingq + 1; ++i)
4173                 entries[i].entry = i;
4174
4175         want = s->max_ethqsets + EXTRA_VECS;
4176         if (is_offload(adap)) {
4177                 want += adap->num_ofld_uld * s->ofldqsets;
4178                 ofld_need = adap->num_ofld_uld * nchan;
4179         }
4180         if (is_pci_uld(adap)) {
4181                 want += adap->num_uld * s->ofldqsets;
4182                 uld_need = adap->num_uld * nchan;
4183         }
4184 #ifdef CONFIG_CHELSIO_T4_DCB
4185         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4186          * each port.
4187          */
4188         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4189 #else
4190         need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
4191 #endif
4192         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4193         if (allocated < 0) {
4194                 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4195                          " not using MSI-X\n");
4196                 kfree(entries);
4197                 return allocated;
4198         }
4199
4200         /* Distribute available vectors to the various queue groups.
4201          * Every group gets its minimum requirement and NIC gets top
4202          * priority for leftovers.
4203          */
4204         i = allocated - EXTRA_VECS - ofld_need - uld_need;
4205         if (i < s->max_ethqsets) {
4206                 s->max_ethqsets = i;
4207                 if (i < s->ethqsets)
4208                         reduce_ethqs(adap, i);
4209         }
4210         if (is_uld(adap)) {
4211                 if (allocated < want)
4212                         s->nqs_per_uld = nchan;
4213                 else
4214                         s->nqs_per_uld = s->ofldqsets;
4215         }
4216
4217         for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
4218                 adap->msix_info[i].vec = entries[i].vector;
4219         if (is_uld(adap)) {
4220                 for (j = 0 ; i < allocated; ++i, j++) {
4221                         adap->msix_info_ulds[j].vec = entries[i].vector;
4222                         adap->msix_info_ulds[j].idx = i;
4223                 }
4224                 adap->msix_bmap_ulds.mapsize = j;
4225         }
4226         dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4227                  "nic %d per uld %d\n",
4228                  allocated, s->max_ethqsets, s->nqs_per_uld);
4229
4230         kfree(entries);
4231         return 0;
4232 }
4233
4234 #undef EXTRA_VECS
4235
4236 static int init_rss(struct adapter *adap)
4237 {
4238         unsigned int i;
4239         int err;
4240
4241         err = t4_init_rss_mode(adap, adap->mbox);
4242         if (err)
4243                 return err;
4244
4245         for_each_port(adap, i) {
4246                 struct port_info *pi = adap2pinfo(adap, i);
4247
4248                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4249                 if (!pi->rss)
4250                         return -ENOMEM;
4251         }
4252         return 0;
4253 }
4254
4255 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4256                                         enum pci_bus_speed *speed,
4257                                         enum pcie_link_width *width)
4258 {
4259         u32 lnkcap1, lnkcap2;
4260         int err1, err2;
4261
4262 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
4263
4264         *speed = PCI_SPEED_UNKNOWN;
4265         *width = PCIE_LNK_WIDTH_UNKNOWN;
4266
4267         err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4268                                           &lnkcap1);
4269         err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4270                                           &lnkcap2);
4271         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4272                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4273                         *speed = PCIE_SPEED_8_0GT;
4274                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4275                         *speed = PCIE_SPEED_5_0GT;
4276                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4277                         *speed = PCIE_SPEED_2_5GT;
4278         }
4279         if (!err1) {
4280                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4281                 if (!lnkcap2) { /* pre-r3.0 */
4282                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4283                                 *speed = PCIE_SPEED_5_0GT;
4284                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4285                                 *speed = PCIE_SPEED_2_5GT;
4286                 }
4287         }
4288
4289         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4290                 return err1 ? err1 : err2 ? err2 : -EINVAL;
4291         return 0;
4292 }
4293
4294 static void cxgb4_check_pcie_caps(struct adapter *adap)
4295 {
4296         enum pcie_link_width width, width_cap;
4297         enum pci_bus_speed speed, speed_cap;
4298
4299 #define PCIE_SPEED_STR(speed) \
4300         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4301          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4302          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4303          "Unknown")
4304
4305         if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4306                 dev_warn(adap->pdev_dev,
4307                          "Unable to determine PCIe device BW capabilities\n");
4308                 return;
4309         }
4310
4311         if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4312             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4313                 dev_warn(adap->pdev_dev,
4314                          "Unable to determine PCI Express bandwidth.\n");
4315                 return;
4316         }
4317
4318         dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4319                  PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4320         dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4321                  width, width_cap);
4322         if (speed < speed_cap || width < width_cap)
4323                 dev_info(adap->pdev_dev,
4324                          "A slot with more lanes and/or higher speed is "
4325                          "suggested for optimal performance.\n");
4326 }
4327
4328 /* Dump basic information about the adapter */
4329 static void print_adapter_info(struct adapter *adapter)
4330 {
4331         /* Device information */
4332         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
4333                  adapter->params.vpd.id,
4334                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
4335         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
4336                  adapter->params.vpd.sn, adapter->params.vpd.pn);
4337
4338         /* Firmware Version */
4339         if (!adapter->params.fw_vers)
4340                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
4341         else
4342                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
4343                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
4344                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
4345                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
4346                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
4347
4348         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
4349          * Firmware, so dev_info() is more appropriate here.)
4350          */
4351         if (!adapter->params.bs_vers)
4352                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
4353         else
4354                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
4355                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
4356                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
4357                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
4358                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
4359
4360         /* TP Microcode Version */
4361         if (!adapter->params.tp_vers)
4362                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
4363         else
4364                 dev_info(adapter->pdev_dev,
4365                          "TP Microcode version: %u.%u.%u.%u\n",
4366                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
4367                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
4368                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
4369                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
4370
4371         /* Expansion ROM version */
4372         if (!adapter->params.er_vers)
4373                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
4374         else
4375                 dev_info(adapter->pdev_dev,
4376                          "Expansion ROM version: %u.%u.%u.%u\n",
4377                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
4378                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
4379                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
4380                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
4381
4382         /* Software/Hardware configuration */
4383         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
4384                  is_offload(adapter) ? "R" : "",
4385                  ((adapter->flags & USING_MSIX) ? "MSI-X" :
4386                   (adapter->flags & USING_MSI) ? "MSI" : ""),
4387                  is_offload(adapter) ? "Offload" : "non-Offload");
4388 }
4389
4390 static void print_port_info(const struct net_device *dev)
4391 {
4392         char buf[80];
4393         char *bufp = buf;
4394         const char *spd = "";
4395         const struct port_info *pi = netdev_priv(dev);
4396         const struct adapter *adap = pi->adapter;
4397
4398         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4399                 spd = " 2.5 GT/s";
4400         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4401                 spd = " 5 GT/s";
4402         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4403                 spd = " 8 GT/s";
4404
4405         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4406                 bufp += sprintf(bufp, "100M/");
4407         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4408                 bufp += sprintf(bufp, "1G/");
4409         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4410                 bufp += sprintf(bufp, "10G/");
4411         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
4412                 bufp += sprintf(bufp, "25G/");
4413         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4414                 bufp += sprintf(bufp, "40G/");
4415         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
4416                 bufp += sprintf(bufp, "100G/");
4417         if (bufp != buf)
4418                 --bufp;
4419         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4420
4421         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
4422                     dev->name, adap->params.vpd.id, adap->name, buf);
4423 }
4424
4425 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4426 {
4427         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4428 }
4429
4430 /*
4431  * Free the following resources:
4432  * - memory used for tables
4433  * - MSI/MSI-X
4434  * - net devices
4435  * - resources FW is holding for us
4436  */
4437 static void free_some_resources(struct adapter *adapter)
4438 {
4439         unsigned int i;
4440
4441         t4_free_mem(adapter->l2t);
4442         t4_cleanup_sched(adapter);
4443         t4_free_mem(adapter->tids.tid_tab);
4444         cxgb4_cleanup_tc_u32(adapter);
4445         kfree(adapter->sge.egr_map);
4446         kfree(adapter->sge.ingr_map);
4447         kfree(adapter->sge.starving_fl);
4448         kfree(adapter->sge.txq_maperr);
4449 #ifdef CONFIG_DEBUG_FS
4450         kfree(adapter->sge.blocked_fl);
4451 #endif
4452         disable_msi(adapter);
4453
4454         for_each_port(adapter, i)
4455                 if (adapter->port[i]) {
4456                         struct port_info *pi = adap2pinfo(adapter, i);
4457
4458                         if (pi->viid != 0)
4459                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4460                                            0, pi->viid);
4461                         kfree(adap2pinfo(adapter, i)->rss);
4462                         free_netdev(adapter->port[i]);
4463                 }
4464         if (adapter->flags & FW_OK)
4465                 t4_fw_bye(adapter, adapter->pf);
4466 }
4467
4468 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4469 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4470                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4471 #define SEGMENT_SIZE 128
4472
4473 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4474 {
4475         u16 device_id;
4476
4477         /* Retrieve adapter's device ID */
4478         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4479
4480         switch (device_id >> 12) {
4481         case CHELSIO_T4:
4482                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4483         case CHELSIO_T5:
4484                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4485         case CHELSIO_T6:
4486                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4487         default:
4488                 dev_err(&pdev->dev, "Device %d is not supported\n",
4489                         device_id);
4490         }
4491         return -EINVAL;
4492 }
4493
4494 #ifdef CONFIG_PCI_IOV
4495 static void dummy_setup(struct net_device *dev)
4496 {
4497         dev->type = ARPHRD_NONE;
4498         dev->mtu = 0;
4499         dev->hard_header_len = 0;
4500         dev->addr_len = 0;
4501         dev->tx_queue_len = 0;
4502         dev->flags |= IFF_NOARP;
4503         dev->priv_flags |= IFF_NO_QUEUE;
4504
4505         /* Initialize the device structure. */
4506         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
4507         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
4508         dev->destructor = free_netdev;
4509 }
4510
4511 static int config_mgmt_dev(struct pci_dev *pdev)
4512 {
4513         struct adapter *adap = pci_get_drvdata(pdev);
4514         struct net_device *netdev;
4515         struct port_info *pi;
4516         char name[IFNAMSIZ];
4517         int err;
4518
4519         snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf);
4520         netdev = alloc_netdev(0, name, NET_NAME_UNKNOWN, dummy_setup);
4521         if (!netdev)
4522                 return -ENOMEM;
4523
4524         pi = netdev_priv(netdev);
4525         pi->adapter = adap;
4526         SET_NETDEV_DEV(netdev, &pdev->dev);
4527
4528         adap->port[0] = netdev;
4529
4530         err = register_netdev(adap->port[0]);
4531         if (err) {
4532                 pr_info("Unable to register VF mgmt netdev %s\n", name);
4533                 free_netdev(adap->port[0]);
4534                 adap->port[0] = NULL;
4535                 return err;
4536         }
4537         return 0;
4538 }
4539
4540 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
4541 {
4542         struct adapter *adap = pci_get_drvdata(pdev);
4543         int err = 0;
4544         int current_vfs = pci_num_vf(pdev);
4545         u32 pcie_fw;
4546
4547         pcie_fw = readl(adap->regs + PCIE_FW_A);
4548         /* Check if cxgb4 is the MASTER and fw is initialized */
4549         if (!(pcie_fw & PCIE_FW_INIT_F) ||
4550             !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
4551             PCIE_FW_MASTER_G(pcie_fw) != 4) {
4552                 dev_warn(&pdev->dev,
4553                          "cxgb4 driver needs to be MASTER to support SRIOV\n");
4554                 return -EOPNOTSUPP;
4555         }
4556
4557         /* If any of the VF's is already assigned to Guest OS, then
4558          * SRIOV for the same cannot be modified
4559          */
4560         if (current_vfs && pci_vfs_assigned(pdev)) {
4561                 dev_err(&pdev->dev,
4562                         "Cannot modify SR-IOV while VFs are assigned\n");
4563                 num_vfs = current_vfs;
4564                 return num_vfs;
4565         }
4566
4567         /* Disable SRIOV when zero is passed.
4568          * One needs to disable SRIOV before modifying it, else
4569          * stack throws the below warning:
4570          * " 'n' VFs already enabled. Disable before enabling 'm' VFs."
4571          */
4572         if (!num_vfs) {
4573                 pci_disable_sriov(pdev);
4574                 if (adap->port[0]) {
4575                         unregister_netdev(adap->port[0]);
4576                         adap->port[0] = NULL;
4577                 }
4578                 /* free VF resources */
4579                 kfree(adap->vfinfo);
4580                 adap->vfinfo = NULL;
4581                 adap->num_vfs = 0;
4582                 return num_vfs;
4583         }
4584
4585         if (num_vfs != current_vfs) {
4586                 err = pci_enable_sriov(pdev, num_vfs);
4587                 if (err)
4588                         return err;
4589
4590                 adap->num_vfs = num_vfs;
4591                 err = config_mgmt_dev(pdev);
4592                 if (err)
4593                         return err;
4594         }
4595
4596         adap->vfinfo = kcalloc(adap->num_vfs,
4597                                sizeof(struct vf_info), GFP_KERNEL);
4598         if (adap->vfinfo)
4599                 fill_vf_station_mac_addr(adap);
4600         return num_vfs;
4601 }
4602 #endif
4603
4604 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4605 {
4606         int func, i, err, s_qpp, qpp, num_seg;
4607         struct port_info *pi;
4608         bool highdma = false;
4609         struct adapter *adapter = NULL;
4610         struct net_device *netdev;
4611         void __iomem *regs;
4612         u32 whoami, pl_rev;
4613         enum chip_type chip;
4614         static int adap_idx = 1;
4615
4616         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4617
4618         err = pci_request_regions(pdev, KBUILD_MODNAME);
4619         if (err) {
4620                 /* Just info, some other driver may have claimed the device. */
4621                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4622                 return err;
4623         }
4624
4625         err = pci_enable_device(pdev);
4626         if (err) {
4627                 dev_err(&pdev->dev, "cannot enable PCI device\n");
4628                 goto out_release_regions;
4629         }
4630
4631         regs = pci_ioremap_bar(pdev, 0);
4632         if (!regs) {
4633                 dev_err(&pdev->dev, "cannot map device registers\n");
4634                 err = -ENOMEM;
4635                 goto out_disable_device;
4636         }
4637
4638         err = t4_wait_dev_ready(regs);
4639         if (err < 0)
4640                 goto out_unmap_bar0;
4641
4642         /* We control everything through one PF */
4643         whoami = readl(regs + PL_WHOAMI_A);
4644         pl_rev = REV_G(readl(regs + PL_REV_A));
4645         chip = get_chip_type(pdev, pl_rev);
4646         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4647                 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4648         if (func != ent->driver_data) {
4649 #ifndef CONFIG_PCI_IOV
4650                 iounmap(regs);
4651 #endif
4652                 pci_disable_device(pdev);
4653                 pci_save_state(pdev);        /* to restore SR-IOV later */
4654                 goto sriov;
4655         }
4656
4657         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4658                 highdma = true;
4659                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4660                 if (err) {
4661                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4662                                 "coherent allocations\n");
4663                         goto out_unmap_bar0;
4664                 }
4665         } else {
4666                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4667                 if (err) {
4668                         dev_err(&pdev->dev, "no usable DMA configuration\n");
4669                         goto out_unmap_bar0;
4670                 }
4671         }
4672
4673         pci_enable_pcie_error_reporting(pdev);
4674         enable_pcie_relaxed_ordering(pdev);
4675         pci_set_master(pdev);
4676         pci_save_state(pdev);
4677
4678         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4679         if (!adapter) {
4680                 err = -ENOMEM;
4681                 goto out_unmap_bar0;
4682         }
4683         adap_idx++;
4684
4685         adapter->workq = create_singlethread_workqueue("cxgb4");
4686         if (!adapter->workq) {
4687                 err = -ENOMEM;
4688                 goto out_free_adapter;
4689         }
4690
4691         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4692                                     (sizeof(struct mbox_cmd) *
4693                                      T4_OS_LOG_MBOX_CMDS),
4694                                     GFP_KERNEL);
4695         if (!adapter->mbox_log) {
4696                 err = -ENOMEM;
4697                 goto out_free_adapter;
4698         }
4699         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
4700
4701         /* PCI device has been enabled */
4702         adapter->flags |= DEV_ENABLED;
4703
4704         adapter->regs = regs;
4705         adapter->pdev = pdev;
4706         adapter->pdev_dev = &pdev->dev;
4707         adapter->name = pci_name(pdev);
4708         adapter->mbox = func;
4709         adapter->pf = func;
4710         adapter->msg_enable = DFLT_MSG_ENABLE;
4711         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4712
4713         spin_lock_init(&adapter->stats_lock);
4714         spin_lock_init(&adapter->tid_release_lock);
4715         spin_lock_init(&adapter->win0_lock);
4716         spin_lock_init(&adapter->mbox_lock);
4717
4718         INIT_LIST_HEAD(&adapter->mlist.list);
4719
4720         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4721         INIT_WORK(&adapter->db_full_task, process_db_full);
4722         INIT_WORK(&adapter->db_drop_task, process_db_drop);
4723
4724         err = t4_prep_adapter(adapter);
4725         if (err)
4726                 goto out_free_adapter;
4727
4728
4729         if (!is_t4(adapter->params.chip)) {
4730                 s_qpp = (QUEUESPERPAGEPF0_S +
4731                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4732                         adapter->pf);
4733                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4734                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4735                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4736
4737                 /* Each segment size is 128B. Write coalescing is enabled only
4738                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4739                  * queue is less no of segments that can be accommodated in
4740                  * a page size.
4741                  */
4742                 if (qpp > num_seg) {
4743                         dev_err(&pdev->dev,
4744                                 "Incorrect number of egress queues per page\n");
4745                         err = -EINVAL;
4746                         goto out_free_adapter;
4747                 }
4748                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4749                 pci_resource_len(pdev, 2));
4750                 if (!adapter->bar2) {
4751                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
4752                         err = -ENOMEM;
4753                         goto out_free_adapter;
4754                 }
4755         }
4756
4757         setup_memwin(adapter);
4758         err = adap_init0(adapter);
4759 #ifdef CONFIG_DEBUG_FS
4760         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4761 #endif
4762         setup_memwin_rdma(adapter);
4763         if (err)
4764                 goto out_unmap_bar;
4765
4766         /* configure SGE_STAT_CFG_A to read WC stats */
4767         if (!is_t4(adapter->params.chip))
4768                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4769                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4770                               T6_STATMODE_V(0)));
4771
4772         for_each_port(adapter, i) {
4773                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4774                                            MAX_ETH_QSETS);
4775                 if (!netdev) {
4776                         err = -ENOMEM;
4777                         goto out_free_dev;
4778                 }
4779
4780                 SET_NETDEV_DEV(netdev, &pdev->dev);
4781
4782                 adapter->port[i] = netdev;
4783                 pi = netdev_priv(netdev);
4784                 pi->adapter = adapter;
4785                 pi->xact_addr_filt = -1;
4786                 pi->port_id = i;
4787                 netdev->irq = pdev->irq;
4788
4789                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4790                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4791                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
4792                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
4793                         NETIF_F_HW_TC;
4794                 if (highdma)
4795                         netdev->hw_features |= NETIF_F_HIGHDMA;
4796                 netdev->features |= netdev->hw_features;
4797                 netdev->vlan_features = netdev->features & VLAN_FEAT;
4798
4799                 netdev->priv_flags |= IFF_UNICAST_FLT;
4800
4801                 /* MTU range: 81 - 9600 */
4802                 netdev->min_mtu = 81;
4803                 netdev->max_mtu = MAX_MTU;
4804
4805                 netdev->netdev_ops = &cxgb4_netdev_ops;
4806 #ifdef CONFIG_CHELSIO_T4_DCB
4807                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4808                 cxgb4_dcb_state_init(netdev);
4809 #endif
4810                 cxgb4_set_ethtool_ops(netdev);
4811         }
4812
4813         pci_set_drvdata(pdev, adapter);
4814
4815         if (adapter->flags & FW_OK) {
4816                 err = t4_port_init(adapter, func, func, 0);
4817                 if (err)
4818                         goto out_free_dev;
4819         } else if (adapter->params.nports == 1) {
4820                 /* If we don't have a connection to the firmware -- possibly
4821                  * because of an error -- grab the raw VPD parameters so we
4822                  * can set the proper MAC Address on the debug network
4823                  * interface that we've created.
4824                  */
4825                 u8 hw_addr[ETH_ALEN];
4826                 u8 *na = adapter->params.vpd.na;
4827
4828                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4829                 if (!err) {
4830                         for (i = 0; i < ETH_ALEN; i++)
4831                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4832                                               hex2val(na[2 * i + 1]));
4833                         t4_set_hw_addr(adapter, 0, hw_addr);
4834                 }
4835         }
4836
4837         /* Configure queues and allocate tables now, they can be needed as
4838          * soon as the first register_netdev completes.
4839          */
4840         cfg_queues(adapter);
4841
4842         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4843         if (!adapter->l2t) {
4844                 /* We tolerate a lack of L2T, giving up some functionality */
4845                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4846                 adapter->params.offload = 0;
4847         }
4848
4849 #if IS_ENABLED(CONFIG_IPV6)
4850         if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
4851             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
4852                 /* CLIP functionality is not present in hardware,
4853                  * hence disable all offload features
4854                  */
4855                 dev_warn(&pdev->dev,
4856                          "CLIP not enabled in hardware, continuing\n");
4857                 adapter->params.offload = 0;
4858         } else {
4859                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4860                                                   adapter->clipt_end);
4861                 if (!adapter->clipt) {
4862                         /* We tolerate a lack of clip_table, giving up
4863                          * some functionality
4864                          */
4865                         dev_warn(&pdev->dev,
4866                                  "could not allocate Clip table, continuing\n");
4867                         adapter->params.offload = 0;
4868                 }
4869         }
4870 #endif
4871
4872         for_each_port(adapter, i) {
4873                 pi = adap2pinfo(adapter, i);
4874                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
4875                 if (!pi->sched_tbl)
4876                         dev_warn(&pdev->dev,
4877                                  "could not activate scheduling on port %d\n",
4878                                  i);
4879         }
4880
4881         if (tid_init(&adapter->tids) < 0) {
4882                 dev_warn(&pdev->dev, "could not allocate TID table, "
4883                          "continuing\n");
4884                 adapter->params.offload = 0;
4885         } else {
4886                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter,
4887                                                     CXGB4_MAX_LINK_HANDLE);
4888                 if (!adapter->tc_u32)
4889                         dev_warn(&pdev->dev,
4890                                  "could not offload tc u32, continuing\n");
4891         }
4892
4893         if (is_offload(adapter)) {
4894                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4895                         u32 hash_base, hash_reg;
4896
4897                         if (chip <= CHELSIO_T5) {
4898                                 hash_reg = LE_DB_TID_HASHBASE_A;
4899                                 hash_base = t4_read_reg(adapter, hash_reg);
4900                                 adapter->tids.hash_base = hash_base / 4;
4901                         } else {
4902                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4903                                 hash_base = t4_read_reg(adapter, hash_reg);
4904                                 adapter->tids.hash_base = hash_base;
4905                         }
4906                 }
4907         }
4908
4909         /* See what interrupts we'll be using */
4910         if (msi > 1 && enable_msix(adapter) == 0)
4911                 adapter->flags |= USING_MSIX;
4912         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
4913                 adapter->flags |= USING_MSI;
4914                 if (msi > 1)
4915                         free_msix_info(adapter);
4916         }
4917
4918         /* check for PCI Express bandwidth capabiltites */
4919         cxgb4_check_pcie_caps(adapter);
4920
4921         err = init_rss(adapter);
4922         if (err)
4923                 goto out_free_dev;
4924
4925         /*
4926          * The card is now ready to go.  If any errors occur during device
4927          * registration we do not fail the whole card but rather proceed only
4928          * with the ports we manage to register successfully.  However we must
4929          * register at least one net device.
4930          */
4931         for_each_port(adapter, i) {
4932                 pi = adap2pinfo(adapter, i);
4933                 adapter->port[i]->dev_port = pi->lport;
4934                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4935                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4936
4937                 err = register_netdev(adapter->port[i]);
4938                 if (err)
4939                         break;
4940                 adapter->chan_map[pi->tx_chan] = i;
4941                 print_port_info(adapter->port[i]);
4942         }
4943         if (i == 0) {
4944                 dev_err(&pdev->dev, "could not register any net devices\n");
4945                 goto out_free_dev;
4946         }
4947         if (err) {
4948                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4949                 err = 0;
4950         }
4951
4952         if (cxgb4_debugfs_root) {
4953                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4954                                                            cxgb4_debugfs_root);
4955                 setup_debugfs(adapter);
4956         }
4957
4958         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4959         pdev->needs_freset = 1;
4960
4961         if (is_uld(adapter)) {
4962                 mutex_lock(&uld_mutex);
4963                 list_add_tail(&adapter->list_node, &adapter_list);
4964                 mutex_unlock(&uld_mutex);
4965         }
4966
4967         print_adapter_info(adapter);
4968         setup_fw_sge_queues(adapter);
4969         return 0;
4970
4971 sriov:
4972 #ifdef CONFIG_PCI_IOV
4973         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4974         if (!adapter) {
4975                 err = -ENOMEM;
4976                 goto free_pci_region;
4977         }
4978
4979         adapter->pdev = pdev;
4980         adapter->pdev_dev = &pdev->dev;
4981         adapter->name = pci_name(pdev);
4982         adapter->mbox = func;
4983         adapter->pf = func;
4984         adapter->regs = regs;
4985         adapter->adap_idx = adap_idx;
4986         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4987                                     (sizeof(struct mbox_cmd) *
4988                                      T4_OS_LOG_MBOX_CMDS),
4989                                     GFP_KERNEL);
4990         if (!adapter->mbox_log) {
4991                 err = -ENOMEM;
4992                 goto free_adapter;
4993         }
4994         pci_set_drvdata(pdev, adapter);
4995         return 0;
4996
4997  free_adapter:
4998         kfree(adapter);
4999  free_pci_region:
5000         iounmap(regs);
5001         pci_disable_sriov(pdev);
5002         pci_release_regions(pdev);
5003         return err;
5004 #else
5005         return 0;
5006 #endif
5007
5008  out_free_dev:
5009         free_some_resources(adapter);
5010         if (adapter->flags & USING_MSIX)
5011                 free_msix_info(adapter);
5012         if (adapter->num_uld || adapter->num_ofld_uld)
5013                 t4_uld_mem_free(adapter);
5014  out_unmap_bar:
5015         if (!is_t4(adapter->params.chip))
5016                 iounmap(adapter->bar2);
5017  out_free_adapter:
5018         if (adapter->workq)
5019                 destroy_workqueue(adapter->workq);
5020
5021         kfree(adapter->mbox_log);
5022         kfree(adapter);
5023  out_unmap_bar0:
5024         iounmap(regs);
5025  out_disable_device:
5026         pci_disable_pcie_error_reporting(pdev);
5027         pci_disable_device(pdev);
5028  out_release_regions:
5029         pci_release_regions(pdev);
5030         return err;
5031 }
5032
5033 static void remove_one(struct pci_dev *pdev)
5034 {
5035         struct adapter *adapter = pci_get_drvdata(pdev);
5036
5037         if (!adapter) {
5038                 pci_release_regions(pdev);
5039                 return;
5040         }
5041
5042         if (adapter->pf == 4) {
5043                 int i;
5044
5045                 /* Tear down per-adapter Work Queue first since it can contain
5046                  * references to our adapter data structure.
5047                  */
5048                 destroy_workqueue(adapter->workq);
5049
5050                 if (is_uld(adapter))
5051                         detach_ulds(adapter);
5052
5053                 disable_interrupts(adapter);
5054
5055                 for_each_port(adapter, i)
5056                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5057                                 unregister_netdev(adapter->port[i]);
5058
5059                 debugfs_remove_recursive(adapter->debugfs_root);
5060
5061                 /* If we allocated filters, free up state associated with any
5062                  * valid filters ...
5063                  */
5064                 clear_all_filters(adapter);
5065
5066                 if (adapter->flags & FULL_INIT_DONE)
5067                         cxgb_down(adapter);
5068
5069                 if (adapter->flags & USING_MSIX)
5070                         free_msix_info(adapter);
5071                 if (adapter->num_uld || adapter->num_ofld_uld)
5072                         t4_uld_mem_free(adapter);
5073                 free_some_resources(adapter);
5074 #if IS_ENABLED(CONFIG_IPV6)
5075                 t4_cleanup_clip_tbl(adapter);
5076 #endif
5077                 iounmap(adapter->regs);
5078                 if (!is_t4(adapter->params.chip))
5079                         iounmap(adapter->bar2);
5080                 pci_disable_pcie_error_reporting(pdev);
5081                 if ((adapter->flags & DEV_ENABLED)) {
5082                         pci_disable_device(pdev);
5083                         adapter->flags &= ~DEV_ENABLED;
5084                 }
5085                 pci_release_regions(pdev);
5086                 kfree(adapter->mbox_log);
5087                 synchronize_rcu();
5088                 kfree(adapter);
5089         }
5090 #ifdef CONFIG_PCI_IOV
5091         else {
5092                 if (adapter->port[0])
5093                         unregister_netdev(adapter->port[0]);
5094                 iounmap(adapter->regs);
5095                 kfree(adapter->vfinfo);
5096                 kfree(adapter);
5097                 pci_disable_sriov(pdev);
5098                 pci_release_regions(pdev);
5099         }
5100 #endif
5101 }
5102
5103 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5104  * delivery.  This is essentially a stripped down version of the PCI remove()
5105  * function where we do the minimal amount of work necessary to shutdown any
5106  * further activity.
5107  */
5108 static void shutdown_one(struct pci_dev *pdev)
5109 {
5110         struct adapter *adapter = pci_get_drvdata(pdev);
5111
5112         /* As with remove_one() above (see extended comment), we only want do
5113          * do cleanup on PCI Devices which went all the way through init_one()
5114          * ...
5115          */
5116         if (!adapter) {
5117                 pci_release_regions(pdev);
5118                 return;
5119         }
5120
5121         if (adapter->pf == 4) {
5122                 int i;
5123
5124                 for_each_port(adapter, i)
5125                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5126                                 cxgb_close(adapter->port[i]);
5127
5128                 t4_uld_clean_up(adapter);
5129                 disable_interrupts(adapter);
5130                 disable_msi(adapter);
5131
5132                 t4_sge_stop(adapter);
5133                 if (adapter->flags & FW_OK)
5134                         t4_fw_bye(adapter, adapter->mbox);
5135         }
5136 #ifdef CONFIG_PCI_IOV
5137         else {
5138                 if (adapter->port[0])
5139                         unregister_netdev(adapter->port[0]);
5140                 iounmap(adapter->regs);
5141                 kfree(adapter->vfinfo);
5142                 kfree(adapter);
5143                 pci_disable_sriov(pdev);
5144                 pci_release_regions(pdev);
5145         }
5146 #endif
5147 }
5148
5149 static struct pci_driver cxgb4_driver = {
5150         .name     = KBUILD_MODNAME,
5151         .id_table = cxgb4_pci_tbl,
5152         .probe    = init_one,
5153         .remove   = remove_one,
5154         .shutdown = shutdown_one,
5155 #ifdef CONFIG_PCI_IOV
5156         .sriov_configure = cxgb4_iov_configure,
5157 #endif
5158         .err_handler = &cxgb4_eeh,
5159 };
5160
5161 static int __init cxgb4_init_module(void)
5162 {
5163         int ret;
5164
5165         /* Debugfs support is optional, just warn if this fails */
5166         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5167         if (!cxgb4_debugfs_root)
5168                 pr_warn("could not create debugfs entry, continuing\n");
5169
5170         ret = pci_register_driver(&cxgb4_driver);
5171         if (ret < 0)
5172                 debugfs_remove(cxgb4_debugfs_root);
5173
5174 #if IS_ENABLED(CONFIG_IPV6)
5175         if (!inet6addr_registered) {
5176                 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5177                 inet6addr_registered = true;
5178         }
5179 #endif
5180
5181         return ret;
5182 }
5183
5184 static void __exit cxgb4_cleanup_module(void)
5185 {
5186 #if IS_ENABLED(CONFIG_IPV6)
5187         if (inet6addr_registered) {
5188                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5189                 inet6addr_registered = false;
5190         }
5191 #endif
5192         pci_unregister_driver(&cxgb4_driver);
5193         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
5194 }
5195
5196 module_init(cxgb4_init_module);
5197 module_exit(cxgb4_cleanup_module);