drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11190,
 917                 0x19040, 0x1906c,
 918                 0x19078, 0x19080,
 919                 0x1908c, 0x190e4,
 920                 0x190f0, 0x190f8,
 921                 0x19100, 0x19110,
 922                 0x19120, 0x19124,
 923                 0x19150, 0x19194,
 924                 0x1919c, 0x191b0,
 925                 0x191d0, 0x191e8,
 926                 0x19238, 0x1924c,
 927                 0x193f8, 0x1943c,
 928                 0x1944c, 0x19474,
 929                 0x19490, 0x194e0,
 930                 0x194f0, 0x194f8,
 931                 0x19800, 0x19c08,
 932                 0x19c10, 0x19c90,
 933                 0x19ca0, 0x19ce4,
 934                 0x19cf0, 0x19d40,
 935                 0x19d50, 0x19d94,
 936                 0x19da0, 0x19de8,
 937                 0x19df0, 0x19e40,
 938                 0x19e50, 0x19e90,
 939                 0x19ea0, 0x19f4c,
 940                 0x1a000, 0x1a004,
 941                 0x1a010, 0x1a06c,
 942                 0x1a0b0, 0x1a0e4,
 943                 0x1a0ec, 0x1a0f4,
 944                 0x1a100, 0x1a108,
 945                 0x1a114, 0x1a120,
 946                 0x1a128, 0x1a130,
 947                 0x1a138, 0x1a138,
 948                 0x1a190, 0x1a1c4,
 949                 0x1a1fc, 0x1a1fc,
 950                 0x1e040, 0x1e04c,
 951                 0x1e284, 0x1e28c,
 952                 0x1e2c0, 0x1e2c0,
 953                 0x1e2e0, 0x1e2e0,
 954                 0x1e300, 0x1e384,
 955                 0x1e3c0, 0x1e3c8,
 956                 0x1e440, 0x1e44c,
 957                 0x1e684, 0x1e68c,
 958                 0x1e6c0, 0x1e6c0,
 959                 0x1e6e0, 0x1e6e0,
 960                 0x1e700, 0x1e784,
 961                 0x1e7c0, 0x1e7c8,
 962                 0x1e840, 0x1e84c,
 963                 0x1ea84, 0x1ea8c,
 964                 0x1eac0, 0x1eac0,
 965                 0x1eae0, 0x1eae0,
 966                 0x1eb00, 0x1eb84,
 967                 0x1ebc0, 0x1ebc8,
 968                 0x1ec40, 0x1ec4c,
 969                 0x1ee84, 0x1ee8c,
 970                 0x1eec0, 0x1eec0,
 971                 0x1eee0, 0x1eee0,
 972                 0x1ef00, 0x1ef84,
 973                 0x1efc0, 0x1efc8,
 974                 0x1f040, 0x1f04c,
 975                 0x1f284, 0x1f28c,
 976                 0x1f2c0, 0x1f2c0,
 977                 0x1f2e0, 0x1f2e0,
 978                 0x1f300, 0x1f384,
 979                 0x1f3c0, 0x1f3c8,
 980                 0x1f440, 0x1f44c,
 981                 0x1f684, 0x1f68c,
 982                 0x1f6c0, 0x1f6c0,
 983                 0x1f6e0, 0x1f6e0,
 984                 0x1f700, 0x1f784,
 985                 0x1f7c0, 0x1f7c8,
 986                 0x1f840, 0x1f84c,
 987                 0x1fa84, 0x1fa8c,
 988                 0x1fac0, 0x1fac0,
 989                 0x1fae0, 0x1fae0,
 990                 0x1fb00, 0x1fb84,
 991                 0x1fbc0, 0x1fbc8,
 992                 0x1fc40, 0x1fc4c,
 993                 0x1fe84, 0x1fe8c,
 994                 0x1fec0, 0x1fec0,
 995                 0x1fee0, 0x1fee0,
 996                 0x1ff00, 0x1ff84,
 997                 0x1ffc0, 0x1ffc8,
 998                 0x20000, 0x2002c,
 999                 0x20100, 0x2013c,
1000                 0x20190, 0x201a0,
1001                 0x201a8, 0x201b8,
1002                 0x201c4, 0x201c8,
1003                 0x20200, 0x20318,
1004                 0x20400, 0x204b4,
1005                 0x204c0, 0x20528,
1006                 0x20540, 0x20614,
1007                 0x21000, 0x21040,
1008                 0x2104c, 0x21060,
1009                 0x210c0, 0x210ec,
1010                 0x21200, 0x21268,
1011                 0x21270, 0x21284,
1012                 0x212fc, 0x21388,
1013                 0x21400, 0x21404,
1014                 0x21500, 0x21500,
1015                 0x21510, 0x21518,
1016                 0x2152c, 0x21530,
1017                 0x2153c, 0x2153c,
1018                 0x21550, 0x21554,
1019                 0x21600, 0x21600,
1020                 0x21608, 0x2161c,
1021                 0x21624, 0x21628,
1022                 0x21630, 0x21634,
1023                 0x2163c, 0x2163c,
1024                 0x21700, 0x2171c,
1025                 0x21780, 0x2178c,
1026                 0x21800, 0x21818,
1027                 0x21820, 0x21828,
1028                 0x21830, 0x21848,
1029                 0x21850, 0x21854,
1030                 0x21860, 0x21868,
1031                 0x21870, 0x21870,
1032                 0x21878, 0x21898,
1033                 0x218a0, 0x218a8,
1034                 0x218b0, 0x218c8,
1035                 0x218d0, 0x218d4,
1036                 0x218e0, 0x218e8,
1037                 0x218f0, 0x218f0,
1038                 0x218f8, 0x21a18,
1039                 0x21a20, 0x21a28,
1040                 0x21a30, 0x21a48,
1041                 0x21a50, 0x21a54,
1042                 0x21a60, 0x21a68,
1043                 0x21a70, 0x21a70,
1044                 0x21a78, 0x21a98,
1045                 0x21aa0, 0x21aa8,
1046                 0x21ab0, 0x21ac8,
1047                 0x21ad0, 0x21ad4,
1048                 0x21ae0, 0x21ae8,
1049                 0x21af0, 0x21af0,
1050                 0x21af8, 0x21c18,
1051                 0x21c20, 0x21c20,
1052                 0x21c28, 0x21c30,
1053                 0x21c38, 0x21c38,
1054                 0x21c80, 0x21c98,
1055                 0x21ca0, 0x21ca8,
1056                 0x21cb0, 0x21cc8,
1057                 0x21cd0, 0x21cd4,
1058                 0x21ce0, 0x21ce8,
1059                 0x21cf0, 0x21cf0,
1060                 0x21cf8, 0x21d7c,
1061                 0x21e00, 0x21e04,
1062                 0x22000, 0x2202c,
1063                 0x22100, 0x2213c,
1064                 0x22190, 0x221a0,
1065                 0x221a8, 0x221b8,
1066                 0x221c4, 0x221c8,
1067                 0x22200, 0x22318,
1068                 0x22400, 0x224b4,
1069                 0x224c0, 0x22528,
1070                 0x22540, 0x22614,
1071                 0x23000, 0x23040,
1072                 0x2304c, 0x23060,
1073                 0x230c0, 0x230ec,
1074                 0x23200, 0x23268,
1075                 0x23270, 0x23284,
1076                 0x232fc, 0x23388,
1077                 0x23400, 0x23404,
1078                 0x23500, 0x23500,
1079                 0x23510, 0x23518,
1080                 0x2352c, 0x23530,
1081                 0x2353c, 0x2353c,
1082                 0x23550, 0x23554,
1083                 0x23600, 0x23600,
1084                 0x23608, 0x2361c,
1085                 0x23624, 0x23628,
1086                 0x23630, 0x23634,
1087                 0x2363c, 0x2363c,
1088                 0x23700, 0x2371c,
1089                 0x23780, 0x2378c,
1090                 0x23800, 0x23818,
1091                 0x23820, 0x23828,
1092                 0x23830, 0x23848,
1093                 0x23850, 0x23854,
1094                 0x23860, 0x23868,
1095                 0x23870, 0x23870,
1096                 0x23878, 0x23898,
1097                 0x238a0, 0x238a8,
1098                 0x238b0, 0x238c8,
1099                 0x238d0, 0x238d4,
1100                 0x238e0, 0x238e8,
1101                 0x238f0, 0x238f0,
1102                 0x238f8, 0x23a18,
1103                 0x23a20, 0x23a28,
1104                 0x23a30, 0x23a48,
1105                 0x23a50, 0x23a54,
1106                 0x23a60, 0x23a68,
1107                 0x23a70, 0x23a70,
1108                 0x23a78, 0x23a98,
1109                 0x23aa0, 0x23aa8,
1110                 0x23ab0, 0x23ac8,
1111                 0x23ad0, 0x23ad4,
1112                 0x23ae0, 0x23ae8,
1113                 0x23af0, 0x23af0,
1114                 0x23af8, 0x23c18,
1115                 0x23c20, 0x23c20,
1116                 0x23c28, 0x23c30,
1117                 0x23c38, 0x23c38,
1118                 0x23c80, 0x23c98,
1119                 0x23ca0, 0x23ca8,
1120                 0x23cb0, 0x23cc8,
1121                 0x23cd0, 0x23cd4,
1122                 0x23ce0, 0x23ce8,
1123                 0x23cf0, 0x23cf0,
1124                 0x23cf8, 0x23d7c,
1125                 0x23e00, 0x23e04,
1126                 0x24000, 0x2402c,
1127                 0x24100, 0x2413c,
1128                 0x24190, 0x241a0,
1129                 0x241a8, 0x241b8,
1130                 0x241c4, 0x241c8,
1131                 0x24200, 0x24318,
1132                 0x24400, 0x244b4,
1133                 0x244c0, 0x24528,
1134                 0x24540, 0x24614,
1135                 0x25000, 0x25040,
1136                 0x2504c, 0x25060,
1137                 0x250c0, 0x250ec,
1138                 0x25200, 0x25268,
1139                 0x25270, 0x25284,
1140                 0x252fc, 0x25388,
1141                 0x25400, 0x25404,
1142                 0x25500, 0x25500,
1143                 0x25510, 0x25518,
1144                 0x2552c, 0x25530,
1145                 0x2553c, 0x2553c,
1146                 0x25550, 0x25554,
1147                 0x25600, 0x25600,
1148                 0x25608, 0x2561c,
1149                 0x25624, 0x25628,
1150                 0x25630, 0x25634,
1151                 0x2563c, 0x2563c,
1152                 0x25700, 0x2571c,
1153                 0x25780, 0x2578c,
1154                 0x25800, 0x25818,
1155                 0x25820, 0x25828,
1156                 0x25830, 0x25848,
1157                 0x25850, 0x25854,
1158                 0x25860, 0x25868,
1159                 0x25870, 0x25870,
1160                 0x25878, 0x25898,
1161                 0x258a0, 0x258a8,
1162                 0x258b0, 0x258c8,
1163                 0x258d0, 0x258d4,
1164                 0x258e0, 0x258e8,
1165                 0x258f0, 0x258f0,
1166                 0x258f8, 0x25a18,
1167                 0x25a20, 0x25a28,
1168                 0x25a30, 0x25a48,
1169                 0x25a50, 0x25a54,
1170                 0x25a60, 0x25a68,
1171                 0x25a70, 0x25a70,
1172                 0x25a78, 0x25a98,
1173                 0x25aa0, 0x25aa8,
1174                 0x25ab0, 0x25ac8,
1175                 0x25ad0, 0x25ad4,
1176                 0x25ae0, 0x25ae8,
1177                 0x25af0, 0x25af0,
1178                 0x25af8, 0x25c18,
1179                 0x25c20, 0x25c20,
1180                 0x25c28, 0x25c30,
1181                 0x25c38, 0x25c38,
1182                 0x25c80, 0x25c98,
1183                 0x25ca0, 0x25ca8,
1184                 0x25cb0, 0x25cc8,
1185                 0x25cd0, 0x25cd4,
1186                 0x25ce0, 0x25ce8,
1187                 0x25cf0, 0x25cf0,
1188                 0x25cf8, 0x25d7c,
1189                 0x25e00, 0x25e04,
1190                 0x26000, 0x2602c,
1191                 0x26100, 0x2613c,
1192                 0x26190, 0x261a0,
1193                 0x261a8, 0x261b8,
1194                 0x261c4, 0x261c8,
1195                 0x26200, 0x26318,
1196                 0x26400, 0x264b4,
1197                 0x264c0, 0x26528,
1198                 0x26540, 0x26614,
1199                 0x27000, 0x27040,
1200                 0x2704c, 0x27060,
1201                 0x270c0, 0x270ec,
1202                 0x27200, 0x27268,
1203                 0x27270, 0x27284,
1204                 0x272fc, 0x27388,
1205                 0x27400, 0x27404,
1206                 0x27500, 0x27500,
1207                 0x27510, 0x27518,
1208                 0x2752c, 0x27530,
1209                 0x2753c, 0x2753c,
1210                 0x27550, 0x27554,
1211                 0x27600, 0x27600,
1212                 0x27608, 0x2761c,
1213                 0x27624, 0x27628,
1214                 0x27630, 0x27634,
1215                 0x2763c, 0x2763c,
1216                 0x27700, 0x2771c,
1217                 0x27780, 0x2778c,
1218                 0x27800, 0x27818,
1219                 0x27820, 0x27828,
1220                 0x27830, 0x27848,
1221                 0x27850, 0x27854,
1222                 0x27860, 0x27868,
1223                 0x27870, 0x27870,
1224                 0x27878, 0x27898,
1225                 0x278a0, 0x278a8,
1226                 0x278b0, 0x278c8,
1227                 0x278d0, 0x278d4,
1228                 0x278e0, 0x278e8,
1229                 0x278f0, 0x278f0,
1230                 0x278f8, 0x27a18,
1231                 0x27a20, 0x27a28,
1232                 0x27a30, 0x27a48,
1233                 0x27a50, 0x27a54,
1234                 0x27a60, 0x27a68,
1235                 0x27a70, 0x27a70,
1236                 0x27a78, 0x27a98,
1237                 0x27aa0, 0x27aa8,
1238                 0x27ab0, 0x27ac8,
1239                 0x27ad0, 0x27ad4,
1240                 0x27ae0, 0x27ae8,
1241                 0x27af0, 0x27af0,
1242                 0x27af8, 0x27c18,
1243                 0x27c20, 0x27c20,
1244                 0x27c28, 0x27c30,
1245                 0x27c38, 0x27c38,
1246                 0x27c80, 0x27c98,
1247                 0x27ca0, 0x27ca8,
1248                 0x27cb0, 0x27cc8,
1249                 0x27cd0, 0x27cd4,
1250                 0x27ce0, 0x27ce8,
1251                 0x27cf0, 0x27cf0,
1252                 0x27cf8, 0x27d7c,
1253                 0x27e00, 0x27e04,
1254         };
1255
1256         static const unsigned int t5_reg_ranges[] = {
1257                 0x1008, 0x10c0,
1258                 0x10cc, 0x10f8,
1259                 0x1100, 0x1100,
1260                 0x110c, 0x1148,
1261                 0x1180, 0x1184,
1262                 0x1190, 0x1194,
1263                 0x11a0, 0x11a4,
1264                 0x11b0, 0x11b4,
1265                 0x11fc, 0x123c,
1266                 0x1280, 0x173c,
1267                 0x1800, 0x18fc,
1268                 0x3000, 0x3028,
1269                 0x3060, 0x30b0,
1270                 0x30b8, 0x30d8,
1271                 0x30e0, 0x30fc,
1272                 0x3140, 0x357c,
1273                 0x35a8, 0x35cc,
1274                 0x35ec, 0x35ec,
1275                 0x3600, 0x5624,
1276                 0x56cc, 0x56ec,
1277                 0x56f4, 0x5720,
1278                 0x5728, 0x575c,
1279                 0x580c, 0x5814,
1280                 0x5890, 0x589c,
1281                 0x58a4, 0x58ac,
1282                 0x58b8, 0x58bc,
1283                 0x5940, 0x59c8,
1284                 0x59d0, 0x59dc,
1285                 0x59fc, 0x5a18,
1286                 0x5a60, 0x5a70,
1287                 0x5a80, 0x5a9c,
1288                 0x5b94, 0x5bfc,
1289                 0x6000, 0x6020,
1290                 0x6028, 0x6040,
1291                 0x6058, 0x609c,
1292                 0x60a8, 0x614c,
1293                 0x7700, 0x7798,
1294                 0x77c0, 0x78fc,
1295                 0x7b00, 0x7b58,
1296                 0x7b60, 0x7b84,
1297                 0x7b8c, 0x7c54,
1298                 0x7d00, 0x7d38,
1299                 0x7d40, 0x7d80,
1300                 0x7d8c, 0x7ddc,
1301                 0x7de4, 0x7e04,
1302                 0x7e10, 0x7e1c,
1303                 0x7e24, 0x7e38,
1304                 0x7e40, 0x7e44,
1305                 0x7e4c, 0x7e78,
1306                 0x7e80, 0x7edc,
1307                 0x7ee8, 0x7efc,
1308                 0x8dc0, 0x8de0,
1309                 0x8df8, 0x8e04,
1310                 0x8e10, 0x8e84,
1311                 0x8ea0, 0x8f84,
1312                 0x8fc0, 0x9058,
1313                 0x9060, 0x9060,
1314                 0x9068, 0x90f8,
1315                 0x9400, 0x9408,
1316                 0x9410, 0x9470,
1317                 0x9600, 0x9600,
1318                 0x9608, 0x9638,
1319                 0x9640, 0x96f4,
1320                 0x9800, 0x9808,
1321                 0x9820, 0x983c,
1322                 0x9850, 0x9864,
1323                 0x9c00, 0x9c6c,
1324                 0x9c80, 0x9cec,
1325                 0x9d00, 0x9d6c,
1326                 0x9d80, 0x9dec,
1327                 0x9e00, 0x9e6c,
1328                 0x9e80, 0x9eec,
1329                 0x9f00, 0x9f6c,
1330                 0x9f80, 0xa020,
1331                 0xd004, 0xd004,
1332                 0xd010, 0xd03c,
1333                 0xdfc0, 0xdfe0,
1334                 0xe000, 0x1106c,
1335                 0x11074, 0x11088,
1336                 0x1109c, 0x1117c,
1337                 0x11190, 0x11204,
1338                 0x19040, 0x1906c,
1339                 0x19078, 0x19080,
1340                 0x1908c, 0x190e8,
1341                 0x190f0, 0x190f8,
1342                 0x19100, 0x19110,
1343                 0x19120, 0x19124,
1344                 0x19150, 0x19194,
1345                 0x1919c, 0x191b0,
1346                 0x191d0, 0x191e8,
1347                 0x19238, 0x19290,
1348                 0x193f8, 0x19428,
1349                 0x19430, 0x19444,
1350                 0x1944c, 0x1946c,
1351                 0x19474, 0x19474,
1352                 0x19490, 0x194cc,
1353                 0x194f0, 0x194f8,
1354                 0x19c00, 0x19c08,
1355                 0x19c10, 0x19c60,
1356                 0x19c94, 0x19ce4,
1357                 0x19cf0, 0x19d40,
1358                 0x19d50, 0x19d94,
1359                 0x19da0, 0x19de8,
1360                 0x19df0, 0x19e10,
1361                 0x19e50, 0x19e90,
1362                 0x19ea0, 0x19f24,
1363                 0x19f34, 0x19f34,
1364                 0x19f40, 0x19f50,
1365                 0x19f90, 0x19fb4,
1366                 0x19fc4, 0x19fe4,
1367                 0x1a000, 0x1a004,
1368                 0x1a010, 0x1a06c,
1369                 0x1a0b0, 0x1a0e4,
1370                 0x1a0ec, 0x1a0f8,
1371                 0x1a100, 0x1a108,
1372                 0x1a114, 0x1a120,
1373                 0x1a128, 0x1a130,
1374                 0x1a138, 0x1a138,
1375                 0x1a190, 0x1a1c4,
1376                 0x1a1fc, 0x1a1fc,
1377                 0x1e008, 0x1e00c,
1378                 0x1e040, 0x1e044,
1379                 0x1e04c, 0x1e04c,
1380                 0x1e284, 0x1e290,
1381                 0x1e2c0, 0x1e2c0,
1382                 0x1e2e0, 0x1e2e0,
1383                 0x1e300, 0x1e384,
1384                 0x1e3c0, 0x1e3c8,
1385                 0x1e408, 0x1e40c,
1386                 0x1e440, 0x1e444,
1387                 0x1e44c, 0x1e44c,
1388                 0x1e684, 0x1e690,
1389                 0x1e6c0, 0x1e6c0,
1390                 0x1e6e0, 0x1e6e0,
1391                 0x1e700, 0x1e784,
1392                 0x1e7c0, 0x1e7c8,
1393                 0x1e808, 0x1e80c,
1394                 0x1e840, 0x1e844,
1395                 0x1e84c, 0x1e84c,
1396                 0x1ea84, 0x1ea90,
1397                 0x1eac0, 0x1eac0,
1398                 0x1eae0, 0x1eae0,
1399                 0x1eb00, 0x1eb84,
1400                 0x1ebc0, 0x1ebc8,
1401                 0x1ec08, 0x1ec0c,
1402                 0x1ec40, 0x1ec44,
1403                 0x1ec4c, 0x1ec4c,
1404                 0x1ee84, 0x1ee90,
1405                 0x1eec0, 0x1eec0,
1406                 0x1eee0, 0x1eee0,
1407                 0x1ef00, 0x1ef84,
1408                 0x1efc0, 0x1efc8,
1409                 0x1f008, 0x1f00c,
1410                 0x1f040, 0x1f044,
1411                 0x1f04c, 0x1f04c,
1412                 0x1f284, 0x1f290,
1413                 0x1f2c0, 0x1f2c0,
1414                 0x1f2e0, 0x1f2e0,
1415                 0x1f300, 0x1f384,
1416                 0x1f3c0, 0x1f3c8,
1417                 0x1f408, 0x1f40c,
1418                 0x1f440, 0x1f444,
1419                 0x1f44c, 0x1f44c,
1420                 0x1f684, 0x1f690,
1421                 0x1f6c0, 0x1f6c0,
1422                 0x1f6e0, 0x1f6e0,
1423                 0x1f700, 0x1f784,
1424                 0x1f7c0, 0x1f7c8,
1425                 0x1f808, 0x1f80c,
1426                 0x1f840, 0x1f844,
1427                 0x1f84c, 0x1f84c,
1428                 0x1fa84, 0x1fa90,
1429                 0x1fac0, 0x1fac0,
1430                 0x1fae0, 0x1fae0,
1431                 0x1fb00, 0x1fb84,
1432                 0x1fbc0, 0x1fbc8,
1433                 0x1fc08, 0x1fc0c,
1434                 0x1fc40, 0x1fc44,
1435                 0x1fc4c, 0x1fc4c,
1436                 0x1fe84, 0x1fe90,
1437                 0x1fec0, 0x1fec0,
1438                 0x1fee0, 0x1fee0,
1439                 0x1ff00, 0x1ff84,
1440                 0x1ffc0, 0x1ffc8,
1441                 0x30000, 0x30030,
1442                 0x30038, 0x30038,
1443                 0x30040, 0x30040,
1444                 0x30100, 0x30144,
1445                 0x30190, 0x301a0,
1446                 0x301a8, 0x301b8,
1447                 0x301c4, 0x301c8,
1448                 0x301d0, 0x301d0,
1449                 0x30200, 0x30318,
1450                 0x30400, 0x304b4,
1451                 0x304c0, 0x3052c,
1452                 0x30540, 0x3061c,
1453                 0x30800, 0x30828,
1454                 0x30834, 0x30834,
1455                 0x308c0, 0x30908,
1456                 0x30910, 0x309ac,
1457                 0x30a00, 0x30a14,
1458                 0x30a1c, 0x30a2c,
1459                 0x30a44, 0x30a50,
1460                 0x30a74, 0x30a74,
1461                 0x30a7c, 0x30afc,
1462                 0x30b08, 0x30c24,
1463                 0x30d00, 0x30d00,
1464                 0x30d08, 0x30d14,
1465                 0x30d1c, 0x30d20,
1466                 0x30d3c, 0x30d3c,
1467                 0x30d48, 0x30d50,
1468                 0x31200, 0x3120c,
1469                 0x31220, 0x31220,
1470                 0x31240, 0x31240,
1471                 0x31600, 0x3160c,
1472                 0x31a00, 0x31a1c,
1473                 0x31e00, 0x31e20,
1474                 0x31e38, 0x31e3c,
1475                 0x31e80, 0x31e80,
1476                 0x31e88, 0x31ea8,
1477                 0x31eb0, 0x31eb4,
1478                 0x31ec8, 0x31ed4,
1479                 0x31fb8, 0x32004,
1480                 0x32200, 0x32200,
1481                 0x32208, 0x32240,
1482                 0x32248, 0x32280,
1483                 0x32288, 0x322c0,
1484                 0x322c8, 0x322fc,
1485                 0x32600, 0x32630,
1486                 0x32a00, 0x32abc,
1487                 0x32b00, 0x32b10,
1488                 0x32b20, 0x32b30,
1489                 0x32b40, 0x32b50,
1490                 0x32b60, 0x32b70,
1491                 0x33000, 0x33028,
1492                 0x33030, 0x33048,
1493                 0x33060, 0x33068,
1494                 0x33070, 0x3309c,
1495                 0x330f0, 0x33128,
1496                 0x33130, 0x33148,
1497                 0x33160, 0x33168,
1498                 0x33170, 0x3319c,
1499                 0x331f0, 0x33238,
1500                 0x33240, 0x33240,
1501                 0x33248, 0x33250,
1502                 0x3325c, 0x33264,
1503                 0x33270, 0x332b8,
1504                 0x332c0, 0x332e4,
1505                 0x332f8, 0x33338,
1506                 0x33340, 0x33340,
1507                 0x33348, 0x33350,
1508                 0x3335c, 0x33364,
1509                 0x33370, 0x333b8,
1510                 0x333c0, 0x333e4,
1511                 0x333f8, 0x33428,
1512                 0x33430, 0x33448,
1513                 0x33460, 0x33468,
1514                 0x33470, 0x3349c,
1515                 0x334f0, 0x33528,
1516                 0x33530, 0x33548,
1517                 0x33560, 0x33568,
1518                 0x33570, 0x3359c,
1519                 0x335f0, 0x33638,
1520                 0x33640, 0x33640,
1521                 0x33648, 0x33650,
1522                 0x3365c, 0x33664,
1523                 0x33670, 0x336b8,
1524                 0x336c0, 0x336e4,
1525                 0x336f8, 0x33738,
1526                 0x33740, 0x33740,
1527                 0x33748, 0x33750,
1528                 0x3375c, 0x33764,
1529                 0x33770, 0x337b8,
1530                 0x337c0, 0x337e4,
1531                 0x337f8, 0x337fc,
1532                 0x33814, 0x33814,
1533                 0x3382c, 0x3382c,
1534                 0x33880, 0x3388c,
1535                 0x338e8, 0x338ec,
1536                 0x33900, 0x33928,
1537                 0x33930, 0x33948,
1538                 0x33960, 0x33968,
1539                 0x33970, 0x3399c,
1540                 0x339f0, 0x33a38,
1541                 0x33a40, 0x33a40,
1542                 0x33a48, 0x33a50,
1543                 0x33a5c, 0x33a64,
1544                 0x33a70, 0x33ab8,
1545                 0x33ac0, 0x33ae4,
1546                 0x33af8, 0x33b10,
1547                 0x33b28, 0x33b28,
1548                 0x33b3c, 0x33b50,
1549                 0x33bf0, 0x33c10,
1550                 0x33c28, 0x33c28,
1551                 0x33c3c, 0x33c50,
1552                 0x33cf0, 0x33cfc,
1553                 0x34000, 0x34030,
1554                 0x34038, 0x34038,
1555                 0x34040, 0x34040,
1556                 0x34100, 0x34144,
1557                 0x34190, 0x341a0,
1558                 0x341a8, 0x341b8,
1559                 0x341c4, 0x341c8,
1560                 0x341d0, 0x341d0,
1561                 0x34200, 0x34318,
1562                 0x34400, 0x344b4,
1563                 0x344c0, 0x3452c,
1564                 0x34540, 0x3461c,
1565                 0x34800, 0x34828,
1566                 0x34834, 0x34834,
1567                 0x348c0, 0x34908,
1568                 0x34910, 0x349ac,
1569                 0x34a00, 0x34a14,
1570                 0x34a1c, 0x34a2c,
1571                 0x34a44, 0x34a50,
1572                 0x34a74, 0x34a74,
1573                 0x34a7c, 0x34afc,
1574                 0x34b08, 0x34c24,
1575                 0x34d00, 0x34d00,
1576                 0x34d08, 0x34d14,
1577                 0x34d1c, 0x34d20,
1578                 0x34d3c, 0x34d3c,
1579                 0x34d48, 0x34d50,
1580                 0x35200, 0x3520c,
1581                 0x35220, 0x35220,
1582                 0x35240, 0x35240,
1583                 0x35600, 0x3560c,
1584                 0x35a00, 0x35a1c,
1585                 0x35e00, 0x35e20,
1586                 0x35e38, 0x35e3c,
1587                 0x35e80, 0x35e80,
1588                 0x35e88, 0x35ea8,
1589                 0x35eb0, 0x35eb4,
1590                 0x35ec8, 0x35ed4,
1591                 0x35fb8, 0x36004,
1592                 0x36200, 0x36200,
1593                 0x36208, 0x36240,
1594                 0x36248, 0x36280,
1595                 0x36288, 0x362c0,
1596                 0x362c8, 0x362fc,
1597                 0x36600, 0x36630,
1598                 0x36a00, 0x36abc,
1599                 0x36b00, 0x36b10,
1600                 0x36b20, 0x36b30,
1601                 0x36b40, 0x36b50,
1602                 0x36b60, 0x36b70,
1603                 0x37000, 0x37028,
1604                 0x37030, 0x37048,
1605                 0x37060, 0x37068,
1606                 0x37070, 0x3709c,
1607                 0x370f0, 0x37128,
1608                 0x37130, 0x37148,
1609                 0x37160, 0x37168,
1610                 0x37170, 0x3719c,
1611                 0x371f0, 0x37238,
1612                 0x37240, 0x37240,
1613                 0x37248, 0x37250,
1614                 0x3725c, 0x37264,
1615                 0x37270, 0x372b8,
1616                 0x372c0, 0x372e4,
1617                 0x372f8, 0x37338,
1618                 0x37340, 0x37340,
1619                 0x37348, 0x37350,
1620                 0x3735c, 0x37364,
1621                 0x37370, 0x373b8,
1622                 0x373c0, 0x373e4,
1623                 0x373f8, 0x37428,
1624                 0x37430, 0x37448,
1625                 0x37460, 0x37468,
1626                 0x37470, 0x3749c,
1627                 0x374f0, 0x37528,
1628                 0x37530, 0x37548,
1629                 0x37560, 0x37568,
1630                 0x37570, 0x3759c,
1631                 0x375f0, 0x37638,
1632                 0x37640, 0x37640,
1633                 0x37648, 0x37650,
1634                 0x3765c, 0x37664,
1635                 0x37670, 0x376b8,
1636                 0x376c0, 0x376e4,
1637                 0x376f8, 0x37738,
1638                 0x37740, 0x37740,
1639                 0x37748, 0x37750,
1640                 0x3775c, 0x37764,
1641                 0x37770, 0x377b8,
1642                 0x377c0, 0x377e4,
1643                 0x377f8, 0x377fc,
1644                 0x37814, 0x37814,
1645                 0x3782c, 0x3782c,
1646                 0x37880, 0x3788c,
1647                 0x378e8, 0x378ec,
1648                 0x37900, 0x37928,
1649                 0x37930, 0x37948,
1650                 0x37960, 0x37968,
1651                 0x37970, 0x3799c,
1652                 0x379f0, 0x37a38,
1653                 0x37a40, 0x37a40,
1654                 0x37a48, 0x37a50,
1655                 0x37a5c, 0x37a64,
1656                 0x37a70, 0x37ab8,
1657                 0x37ac0, 0x37ae4,
1658                 0x37af8, 0x37b10,
1659                 0x37b28, 0x37b28,
1660                 0x37b3c, 0x37b50,
1661                 0x37bf0, 0x37c10,
1662                 0x37c28, 0x37c28,
1663                 0x37c3c, 0x37c50,
1664                 0x37cf0, 0x37cfc,
1665                 0x38000, 0x38030,
1666                 0x38038, 0x38038,
1667                 0x38040, 0x38040,
1668                 0x38100, 0x38144,
1669                 0x38190, 0x381a0,
1670                 0x381a8, 0x381b8,
1671                 0x381c4, 0x381c8,
1672                 0x381d0, 0x381d0,
1673                 0x38200, 0x38318,
1674                 0x38400, 0x384b4,
1675                 0x384c0, 0x3852c,
1676                 0x38540, 0x3861c,
1677                 0x38800, 0x38828,
1678                 0x38834, 0x38834,
1679                 0x388c0, 0x38908,
1680                 0x38910, 0x389ac,
1681                 0x38a00, 0x38a14,
1682                 0x38a1c, 0x38a2c,
1683                 0x38a44, 0x38a50,
1684                 0x38a74, 0x38a74,
1685                 0x38a7c, 0x38afc,
1686                 0x38b08, 0x38c24,
1687                 0x38d00, 0x38d00,
1688                 0x38d08, 0x38d14,
1689                 0x38d1c, 0x38d20,
1690                 0x38d3c, 0x38d3c,
1691                 0x38d48, 0x38d50,
1692                 0x39200, 0x3920c,
1693                 0x39220, 0x39220,
1694                 0x39240, 0x39240,
1695                 0x39600, 0x3960c,
1696                 0x39a00, 0x39a1c,
1697                 0x39e00, 0x39e20,
1698                 0x39e38, 0x39e3c,
1699                 0x39e80, 0x39e80,
1700                 0x39e88, 0x39ea8,
1701                 0x39eb0, 0x39eb4,
1702                 0x39ec8, 0x39ed4,
1703                 0x39fb8, 0x3a004,
1704                 0x3a200, 0x3a200,
1705                 0x3a208, 0x3a240,
1706                 0x3a248, 0x3a280,
1707                 0x3a288, 0x3a2c0,
1708                 0x3a2c8, 0x3a2fc,
1709                 0x3a600, 0x3a630,
1710                 0x3aa00, 0x3aabc,
1711                 0x3ab00, 0x3ab10,
1712                 0x3ab20, 0x3ab30,
1713                 0x3ab40, 0x3ab50,
1714                 0x3ab60, 0x3ab70,
1715                 0x3b000, 0x3b028,
1716                 0x3b030, 0x3b048,
1717                 0x3b060, 0x3b068,
1718                 0x3b070, 0x3b09c,
1719                 0x3b0f0, 0x3b128,
1720                 0x3b130, 0x3b148,
1721                 0x3b160, 0x3b168,
1722                 0x3b170, 0x3b19c,
1723                 0x3b1f0, 0x3b238,
1724                 0x3b240, 0x3b240,
1725                 0x3b248, 0x3b250,
1726                 0x3b25c, 0x3b264,
1727                 0x3b270, 0x3b2b8,
1728                 0x3b2c0, 0x3b2e4,
1729                 0x3b2f8, 0x3b338,
1730                 0x3b340, 0x3b340,
1731                 0x3b348, 0x3b350,
1732                 0x3b35c, 0x3b364,
1733                 0x3b370, 0x3b3b8,
1734                 0x3b3c0, 0x3b3e4,
1735                 0x3b3f8, 0x3b428,
1736                 0x3b430, 0x3b448,
1737                 0x3b460, 0x3b468,
1738                 0x3b470, 0x3b49c,
1739                 0x3b4f0, 0x3b528,
1740                 0x3b530, 0x3b548,
1741                 0x3b560, 0x3b568,
1742                 0x3b570, 0x3b59c,
1743                 0x3b5f0, 0x3b638,
1744                 0x3b640, 0x3b640,
1745                 0x3b648, 0x3b650,
1746                 0x3b65c, 0x3b664,
1747                 0x3b670, 0x3b6b8,
1748                 0x3b6c0, 0x3b6e4,
1749                 0x3b6f8, 0x3b738,
1750                 0x3b740, 0x3b740,
1751                 0x3b748, 0x3b750,
1752                 0x3b75c, 0x3b764,
1753                 0x3b770, 0x3b7b8,
1754                 0x3b7c0, 0x3b7e4,
1755                 0x3b7f8, 0x3b7fc,
1756                 0x3b814, 0x3b814,
1757                 0x3b82c, 0x3b82c,
1758                 0x3b880, 0x3b88c,
1759                 0x3b8e8, 0x3b8ec,
1760                 0x3b900, 0x3b928,
1761                 0x3b930, 0x3b948,
1762                 0x3b960, 0x3b968,
1763                 0x3b970, 0x3b99c,
1764                 0x3b9f0, 0x3ba38,
1765                 0x3ba40, 0x3ba40,
1766                 0x3ba48, 0x3ba50,
1767                 0x3ba5c, 0x3ba64,
1768                 0x3ba70, 0x3bab8,
1769                 0x3bac0, 0x3bae4,
1770                 0x3baf8, 0x3bb10,
1771                 0x3bb28, 0x3bb28,
1772                 0x3bb3c, 0x3bb50,
1773                 0x3bbf0, 0x3bc10,
1774                 0x3bc28, 0x3bc28,
1775                 0x3bc3c, 0x3bc50,
1776                 0x3bcf0, 0x3bcfc,
1777                 0x3c000, 0x3c030,
1778                 0x3c038, 0x3c038,
1779                 0x3c040, 0x3c040,
1780                 0x3c100, 0x3c144,
1781                 0x3c190, 0x3c1a0,
1782                 0x3c1a8, 0x3c1b8,
1783                 0x3c1c4, 0x3c1c8,
1784                 0x3c1d0, 0x3c1d0,
1785                 0x3c200, 0x3c318,
1786                 0x3c400, 0x3c4b4,
1787                 0x3c4c0, 0x3c52c,
1788                 0x3c540, 0x3c61c,
1789                 0x3c800, 0x3c828,
1790                 0x3c834, 0x3c834,
1791                 0x3c8c0, 0x3c908,
1792                 0x3c910, 0x3c9ac,
1793                 0x3ca00, 0x3ca14,
1794                 0x3ca1c, 0x3ca2c,
1795                 0x3ca44, 0x3ca50,
1796                 0x3ca74, 0x3ca74,
1797                 0x3ca7c, 0x3cafc,
1798                 0x3cb08, 0x3cc24,
1799                 0x3cd00, 0x3cd00,
1800                 0x3cd08, 0x3cd14,
1801                 0x3cd1c, 0x3cd20,
1802                 0x3cd3c, 0x3cd3c,
1803                 0x3cd48, 0x3cd50,
1804                 0x3d200, 0x3d20c,
1805                 0x3d220, 0x3d220,
1806                 0x3d240, 0x3d240,
1807                 0x3d600, 0x3d60c,
1808                 0x3da00, 0x3da1c,
1809                 0x3de00, 0x3de20,
1810                 0x3de38, 0x3de3c,
1811                 0x3de80, 0x3de80,
1812                 0x3de88, 0x3dea8,
1813                 0x3deb0, 0x3deb4,
1814                 0x3dec8, 0x3ded4,
1815                 0x3dfb8, 0x3e004,
1816                 0x3e200, 0x3e200,
1817                 0x3e208, 0x3e240,
1818                 0x3e248, 0x3e280,
1819                 0x3e288, 0x3e2c0,
1820                 0x3e2c8, 0x3e2fc,
1821                 0x3e600, 0x3e630,
1822                 0x3ea00, 0x3eabc,
1823                 0x3eb00, 0x3eb10,
1824                 0x3eb20, 0x3eb30,
1825                 0x3eb40, 0x3eb50,
1826                 0x3eb60, 0x3eb70,
1827                 0x3f000, 0x3f028,
1828                 0x3f030, 0x3f048,
1829                 0x3f060, 0x3f068,
1830                 0x3f070, 0x3f09c,
1831                 0x3f0f0, 0x3f128,
1832                 0x3f130, 0x3f148,
1833                 0x3f160, 0x3f168,
1834                 0x3f170, 0x3f19c,
1835                 0x3f1f0, 0x3f238,
1836                 0x3f240, 0x3f240,
1837                 0x3f248, 0x3f250,
1838                 0x3f25c, 0x3f264,
1839                 0x3f270, 0x3f2b8,
1840                 0x3f2c0, 0x3f2e4,
1841                 0x3f2f8, 0x3f338,
1842                 0x3f340, 0x3f340,
1843                 0x3f348, 0x3f350,
1844                 0x3f35c, 0x3f364,
1845                 0x3f370, 0x3f3b8,
1846                 0x3f3c0, 0x3f3e4,
1847                 0x3f3f8, 0x3f428,
1848                 0x3f430, 0x3f448,
1849                 0x3f460, 0x3f468,
1850                 0x3f470, 0x3f49c,
1851                 0x3f4f0, 0x3f528,
1852                 0x3f530, 0x3f548,
1853                 0x3f560, 0x3f568,
1854                 0x3f570, 0x3f59c,
1855                 0x3f5f0, 0x3f638,
1856                 0x3f640, 0x3f640,
1857                 0x3f648, 0x3f650,
1858                 0x3f65c, 0x3f664,
1859                 0x3f670, 0x3f6b8,
1860                 0x3f6c0, 0x3f6e4,
1861                 0x3f6f8, 0x3f738,
1862                 0x3f740, 0x3f740,
1863                 0x3f748, 0x3f750,
1864                 0x3f75c, 0x3f764,
1865                 0x3f770, 0x3f7b8,
1866                 0x3f7c0, 0x3f7e4,
1867                 0x3f7f8, 0x3f7fc,
1868                 0x3f814, 0x3f814,
1869                 0x3f82c, 0x3f82c,
1870                 0x3f880, 0x3f88c,
1871                 0x3f8e8, 0x3f8ec,
1872                 0x3f900, 0x3f928,
1873                 0x3f930, 0x3f948,
1874                 0x3f960, 0x3f968,
1875                 0x3f970, 0x3f99c,
1876                 0x3f9f0, 0x3fa38,
1877                 0x3fa40, 0x3fa40,
1878                 0x3fa48, 0x3fa50,
1879                 0x3fa5c, 0x3fa64,
1880                 0x3fa70, 0x3fab8,
1881                 0x3fac0, 0x3fae4,
1882                 0x3faf8, 0x3fb10,
1883                 0x3fb28, 0x3fb28,
1884                 0x3fb3c, 0x3fb50,
1885                 0x3fbf0, 0x3fc10,
1886                 0x3fc28, 0x3fc28,
1887                 0x3fc3c, 0x3fc50,
1888                 0x3fcf0, 0x3fcfc,
1889                 0x40000, 0x4000c,
1890                 0x40040, 0x40050,
1891                 0x40060, 0x40068,
1892                 0x4007c, 0x4008c,
1893                 0x40094, 0x400b0,
1894                 0x400c0, 0x40144,
1895                 0x40180, 0x4018c,
1896                 0x40200, 0x40254,
1897                 0x40260, 0x40264,
1898                 0x40270, 0x40288,
1899                 0x40290, 0x40298,
1900                 0x402ac, 0x402c8,
1901                 0x402d0, 0x402e0,
1902                 0x402f0, 0x402f0,
1903                 0x40300, 0x4033c,
1904                 0x403f8, 0x403fc,
1905                 0x41304, 0x413c4,
1906                 0x41400, 0x4140c,
1907                 0x41414, 0x4141c,
1908                 0x41480, 0x414d0,
1909                 0x44000, 0x44054,
1910                 0x4405c, 0x44078,
1911                 0x440c0, 0x44174,
1912                 0x44180, 0x441ac,
1913                 0x441b4, 0x441b8,
1914                 0x441c0, 0x44254,
1915                 0x4425c, 0x44278,
1916                 0x442c0, 0x44374,
1917                 0x44380, 0x443ac,
1918                 0x443b4, 0x443b8,
1919                 0x443c0, 0x44454,
1920                 0x4445c, 0x44478,
1921                 0x444c0, 0x44574,
1922                 0x44580, 0x445ac,
1923                 0x445b4, 0x445b8,
1924                 0x445c0, 0x44654,
1925                 0x4465c, 0x44678,
1926                 0x446c0, 0x44774,
1927                 0x44780, 0x447ac,
1928                 0x447b4, 0x447b8,
1929                 0x447c0, 0x44854,
1930                 0x4485c, 0x44878,
1931                 0x448c0, 0x44974,
1932                 0x44980, 0x449ac,
1933                 0x449b4, 0x449b8,
1934                 0x449c0, 0x449fc,
1935                 0x45000, 0x45004,
1936                 0x45010, 0x45030,
1937                 0x45040, 0x45060,
1938                 0x45068, 0x45068,
1939                 0x45080, 0x45084,
1940                 0x450a0, 0x450b0,
1941                 0x45200, 0x45204,
1942                 0x45210, 0x45230,
1943                 0x45240, 0x45260,
1944                 0x45268, 0x45268,
1945                 0x45280, 0x45284,
1946                 0x452a0, 0x452b0,
1947                 0x460c0, 0x460e4,
1948                 0x47000, 0x4703c,
1949                 0x47044, 0x4708c,
1950                 0x47200, 0x47250,
1951                 0x47400, 0x47408,
1952                 0x47414, 0x47420,
1953                 0x47600, 0x47618,
1954                 0x47800, 0x47814,
1955                 0x48000, 0x4800c,
1956                 0x48040, 0x48050,
1957                 0x48060, 0x48068,
1958                 0x4807c, 0x4808c,
1959                 0x48094, 0x480b0,
1960                 0x480c0, 0x48144,
1961                 0x48180, 0x4818c,
1962                 0x48200, 0x48254,
1963                 0x48260, 0x48264,
1964                 0x48270, 0x48288,
1965                 0x48290, 0x48298,
1966                 0x482ac, 0x482c8,
1967                 0x482d0, 0x482e0,
1968                 0x482f0, 0x482f0,
1969                 0x48300, 0x4833c,
1970                 0x483f8, 0x483fc,
1971                 0x49304, 0x493c4,
1972                 0x49400, 0x4940c,
1973                 0x49414, 0x4941c,
1974                 0x49480, 0x494d0,
1975                 0x4c000, 0x4c054,
1976                 0x4c05c, 0x4c078,
1977                 0x4c0c0, 0x4c174,
1978                 0x4c180, 0x4c1ac,
1979                 0x4c1b4, 0x4c1b8,
1980                 0x4c1c0, 0x4c254,
1981                 0x4c25c, 0x4c278,
1982                 0x4c2c0, 0x4c374,
1983                 0x4c380, 0x4c3ac,
1984                 0x4c3b4, 0x4c3b8,
1985                 0x4c3c0, 0x4c454,
1986                 0x4c45c, 0x4c478,
1987                 0x4c4c0, 0x4c574,
1988                 0x4c580, 0x4c5ac,
1989                 0x4c5b4, 0x4c5b8,
1990                 0x4c5c0, 0x4c654,
1991                 0x4c65c, 0x4c678,
1992                 0x4c6c0, 0x4c774,
1993                 0x4c780, 0x4c7ac,
1994                 0x4c7b4, 0x4c7b8,
1995                 0x4c7c0, 0x4c854,
1996                 0x4c85c, 0x4c878,
1997                 0x4c8c0, 0x4c974,
1998                 0x4c980, 0x4c9ac,
1999                 0x4c9b4, 0x4c9b8,
2000                 0x4c9c0, 0x4c9fc,
2001                 0x4d000, 0x4d004,
2002                 0x4d010, 0x4d030,
2003                 0x4d040, 0x4d060,
2004                 0x4d068, 0x4d068,
2005                 0x4d080, 0x4d084,
2006                 0x4d0a0, 0x4d0b0,
2007                 0x4d200, 0x4d204,
2008                 0x4d210, 0x4d230,
2009                 0x4d240, 0x4d260,
2010                 0x4d268, 0x4d268,
2011                 0x4d280, 0x4d284,
2012                 0x4d2a0, 0x4d2b0,
2013                 0x4e0c0, 0x4e0e4,
2014                 0x4f000, 0x4f03c,
2015                 0x4f044, 0x4f08c,
2016                 0x4f200, 0x4f250,
2017                 0x4f400, 0x4f408,
2018                 0x4f414, 0x4f420,
2019                 0x4f600, 0x4f618,
2020                 0x4f800, 0x4f814,
2021                 0x50000, 0x50084,
2022                 0x50090, 0x500cc,
2023                 0x50400, 0x50400,
2024                 0x50800, 0x50884,
2025                 0x50890, 0x508cc,
2026                 0x50c00, 0x50c00,
2027                 0x51000, 0x5101c,
2028                 0x51300, 0x51308,
2029         };
2030
2031         static const unsigned int t6_reg_ranges[] = {
2032                 0x1008, 0x101c,
2033                 0x1024, 0x10a8,
2034                 0x10b4, 0x10f8,
2035                 0x1100, 0x1114,
2036                 0x111c, 0x112c,
2037                 0x1138, 0x113c,
2038                 0x1144, 0x114c,
2039                 0x1180, 0x1184,
2040                 0x1190, 0x1194,
2041                 0x11a0, 0x11a4,
2042                 0x11b0, 0x11b4,
2043                 0x11fc, 0x1258,
2044                 0x1280, 0x12d4,
2045                 0x12d9, 0x12d9,
2046                 0x12de, 0x12de,
2047                 0x12e3, 0x12e3,
2048                 0x12e8, 0x133c,
2049                 0x1800, 0x18fc,
2050                 0x3000, 0x302c,
2051                 0x3060, 0x30b0,
2052                 0x30b8, 0x30d8,
2053                 0x30e0, 0x30fc,
2054                 0x3140, 0x357c,
2055                 0x35a8, 0x35cc,
2056                 0x35ec, 0x35ec,
2057                 0x3600, 0x5624,
2058                 0x56cc, 0x56ec,
2059                 0x56f4, 0x5720,
2060                 0x5728, 0x575c,
2061                 0x580c, 0x5814,
2062                 0x5890, 0x589c,
2063                 0x58a4, 0x58ac,
2064                 0x58b8, 0x58bc,
2065                 0x5940, 0x595c,
2066                 0x5980, 0x598c,
2067                 0x59b0, 0x59c8,
2068                 0x59d0, 0x59dc,
2069                 0x59fc, 0x5a18,
2070                 0x5a60, 0x5a6c,
2071                 0x5a80, 0x5a8c,
2072                 0x5a94, 0x5a9c,
2073                 0x5b94, 0x5bfc,
2074                 0x5c10, 0x5e48,
2075                 0x5e50, 0x5e94,
2076                 0x5ea0, 0x5eb0,
2077                 0x5ec0, 0x5ec0,
2078                 0x5ec8, 0x5ed0,
2079                 0x6000, 0x6020,
2080                 0x6028, 0x6040,
2081                 0x6058, 0x609c,
2082                 0x60a8, 0x619c,
2083                 0x7700, 0x7798,
2084                 0x77c0, 0x7880,
2085                 0x78cc, 0x78fc,
2086                 0x7b00, 0x7b58,
2087                 0x7b60, 0x7b84,
2088                 0x7b8c, 0x7c54,
2089                 0x7d00, 0x7d38,
2090                 0x7d40, 0x7d84,
2091                 0x7d8c, 0x7ddc,
2092                 0x7de4, 0x7e04,
2093                 0x7e10, 0x7e1c,
2094                 0x7e24, 0x7e38,
2095                 0x7e40, 0x7e44,
2096                 0x7e4c, 0x7e78,
2097                 0x7e80, 0x7edc,
2098                 0x7ee8, 0x7efc,
2099                 0x8dc0, 0x8de4,
2100                 0x8df8, 0x8e04,
2101                 0x8e10, 0x8e84,
2102                 0x8ea0, 0x8f88,
2103                 0x8fb8, 0x9058,
2104                 0x9060, 0x9060,
2105                 0x9068, 0x90f8,
2106                 0x9100, 0x9124,
2107                 0x9400, 0x9470,
2108                 0x9600, 0x9600,
2109                 0x9608, 0x9638,
2110                 0x9640, 0x9704,
2111                 0x9710, 0x971c,
2112                 0x9800, 0x9808,
2113                 0x9820, 0x983c,
2114                 0x9850, 0x9864,
2115                 0x9c00, 0x9c6c,
2116                 0x9c80, 0x9cec,
2117                 0x9d00, 0x9d6c,
2118                 0x9d80, 0x9dec,
2119                 0x9e00, 0x9e6c,
2120                 0x9e80, 0x9eec,
2121                 0x9f00, 0x9f6c,
2122                 0x9f80, 0xa020,
2123                 0xd004, 0xd03c,
2124                 0xd100, 0xd118,
2125                 0xd200, 0xd214,
2126                 0xd220, 0xd234,
2127                 0xd240, 0xd254,
2128                 0xd260, 0xd274,
2129                 0xd280, 0xd294,
2130                 0xd2a0, 0xd2b4,
2131                 0xd2c0, 0xd2d4,
2132                 0xd2e0, 0xd2f4,
2133                 0xd300, 0xd31c,
2134                 0xdfc0, 0xdfe0,
2135                 0xe000, 0xf008,
2136                 0x11000, 0x11014,
2137                 0x11048, 0x1106c,
2138                 0x11074, 0x11088,
2139                 0x11098, 0x11120,
2140                 0x1112c, 0x1117c,
2141                 0x11190, 0x112e0,
2142                 0x11300, 0x1130c,
2143                 0x12000, 0x1206c,
2144                 0x19040, 0x1906c,
2145                 0x19078, 0x19080,
2146                 0x1908c, 0x190e8,
2147                 0x190f0, 0x190f8,
2148                 0x19100, 0x19110,
2149                 0x19120, 0x19124,
2150                 0x19150, 0x19194,
2151                 0x1919c, 0x191b0,
2152                 0x191d0, 0x191e8,
2153                 0x19238, 0x19290,
2154                 0x192a4, 0x192b0,
2155                 0x192bc, 0x192bc,
2156                 0x19348, 0x1934c,
2157                 0x193f8, 0x19418,
2158                 0x19420, 0x19428,
2159                 0x19430, 0x19444,
2160                 0x1944c, 0x1946c,
2161                 0x19474, 0x19474,
2162                 0x19490, 0x194cc,
2163                 0x194f0, 0x194f8,
2164                 0x19c00, 0x19c48,
2165                 0x19c50, 0x19c80,
2166                 0x19c94, 0x19c98,
2167                 0x19ca0, 0x19cbc,
2168                 0x19ce4, 0x19ce4,
2169                 0x19cf0, 0x19cf8,
2170                 0x19d00, 0x19d28,
2171                 0x19d50, 0x19d78,
2172                 0x19d94, 0x19d98,
2173                 0x19da0, 0x19dc8,
2174                 0x19df0, 0x19e10,
2175                 0x19e50, 0x19e6c,
2176                 0x19ea0, 0x19ebc,
2177                 0x19ec4, 0x19ef4,
2178                 0x19f04, 0x19f2c,
2179                 0x19f34, 0x19f34,
2180                 0x19f40, 0x19f50,
2181                 0x19f90, 0x19fac,
2182                 0x19fc4, 0x19fc8,
2183                 0x19fd0, 0x19fe4,
2184                 0x1a000, 0x1a004,
2185                 0x1a010, 0x1a06c,
2186                 0x1a0b0, 0x1a0e4,
2187                 0x1a0ec, 0x1a0f8,
2188                 0x1a100, 0x1a108,
2189                 0x1a114, 0x1a120,
2190                 0x1a128, 0x1a130,
2191                 0x1a138, 0x1a138,
2192                 0x1a190, 0x1a1c4,
2193                 0x1a1fc, 0x1a1fc,
2194                 0x1e008, 0x1e00c,
2195                 0x1e040, 0x1e044,
2196                 0x1e04c, 0x1e04c,
2197                 0x1e284, 0x1e290,
2198                 0x1e2c0, 0x1e2c0,
2199                 0x1e2e0, 0x1e2e0,
2200                 0x1e300, 0x1e384,
2201                 0x1e3c0, 0x1e3c8,
2202                 0x1e408, 0x1e40c,
2203                 0x1e440, 0x1e444,
2204                 0x1e44c, 0x1e44c,
2205                 0x1e684, 0x1e690,
2206                 0x1e6c0, 0x1e6c0,
2207                 0x1e6e0, 0x1e6e0,
2208                 0x1e700, 0x1e784,
2209                 0x1e7c0, 0x1e7c8,
2210                 0x1e808, 0x1e80c,
2211                 0x1e840, 0x1e844,
2212                 0x1e84c, 0x1e84c,
2213                 0x1ea84, 0x1ea90,
2214                 0x1eac0, 0x1eac0,
2215                 0x1eae0, 0x1eae0,
2216                 0x1eb00, 0x1eb84,
2217                 0x1ebc0, 0x1ebc8,
2218                 0x1ec08, 0x1ec0c,
2219                 0x1ec40, 0x1ec44,
2220                 0x1ec4c, 0x1ec4c,
2221                 0x1ee84, 0x1ee90,
2222                 0x1eec0, 0x1eec0,
2223                 0x1eee0, 0x1eee0,
2224                 0x1ef00, 0x1ef84,
2225                 0x1efc0, 0x1efc8,
2226                 0x1f008, 0x1f00c,
2227                 0x1f040, 0x1f044,
2228                 0x1f04c, 0x1f04c,
2229                 0x1f284, 0x1f290,
2230                 0x1f2c0, 0x1f2c0,
2231                 0x1f2e0, 0x1f2e0,
2232                 0x1f300, 0x1f384,
2233                 0x1f3c0, 0x1f3c8,
2234                 0x1f408, 0x1f40c,
2235                 0x1f440, 0x1f444,
2236                 0x1f44c, 0x1f44c,
2237                 0x1f684, 0x1f690,
2238                 0x1f6c0, 0x1f6c0,
2239                 0x1f6e0, 0x1f6e0,
2240                 0x1f700, 0x1f784,
2241                 0x1f7c0, 0x1f7c8,
2242                 0x1f808, 0x1f80c,
2243                 0x1f840, 0x1f844,
2244                 0x1f84c, 0x1f84c,
2245                 0x1fa84, 0x1fa90,
2246                 0x1fac0, 0x1fac0,
2247                 0x1fae0, 0x1fae0,
2248                 0x1fb00, 0x1fb84,
2249                 0x1fbc0, 0x1fbc8,
2250                 0x1fc08, 0x1fc0c,
2251                 0x1fc40, 0x1fc44,
2252                 0x1fc4c, 0x1fc4c,
2253                 0x1fe84, 0x1fe90,
2254                 0x1fec0, 0x1fec0,
2255                 0x1fee0, 0x1fee0,
2256                 0x1ff00, 0x1ff84,
2257                 0x1ffc0, 0x1ffc8,
2258                 0x30000, 0x30030,
2259                 0x30038, 0x30038,
2260                 0x30040, 0x30040,
2261                 0x30048, 0x30048,
2262                 0x30050, 0x30050,
2263                 0x3005c, 0x30060,
2264                 0x30068, 0x30068,
2265                 0x30070, 0x30070,
2266                 0x30100, 0x30168,
2267                 0x30190, 0x301a0,
2268                 0x301a8, 0x301b8,
2269                 0x301c4, 0x301c8,
2270                 0x301d0, 0x301d0,
2271                 0x30200, 0x30320,
2272                 0x30400, 0x304b4,
2273                 0x304c0, 0x3052c,
2274                 0x30540, 0x3061c,
2275                 0x30800, 0x308a0,
2276                 0x308c0, 0x30908,
2277                 0x30910, 0x309b8,
2278                 0x30a00, 0x30a04,
2279                 0x30a0c, 0x30a14,
2280                 0x30a1c, 0x30a2c,
2281                 0x30a44, 0x30a50,
2282                 0x30a74, 0x30a74,
2283                 0x30a7c, 0x30afc,
2284                 0x30b08, 0x30c24,
2285                 0x30d00, 0x30d14,
2286                 0x30d1c, 0x30d3c,
2287                 0x30d44, 0x30d4c,
2288                 0x30d54, 0x30d74,
2289                 0x30d7c, 0x30d7c,
2290                 0x30de0, 0x30de0,
2291                 0x30e00, 0x30ed4,
2292                 0x30f00, 0x30fa4,
2293                 0x30fc0, 0x30fc4,
2294                 0x31000, 0x31004,
2295                 0x31080, 0x310fc,
2296                 0x31208, 0x31220,
2297                 0x3123c, 0x31254,
2298                 0x31300, 0x31300,
2299                 0x31308, 0x3131c,
2300                 0x31338, 0x3133c,
2301                 0x31380, 0x31380,
2302                 0x31388, 0x313a8,
2303                 0x313b4, 0x313b4,
2304                 0x31400, 0x31420,
2305                 0x31438, 0x3143c,
2306                 0x31480, 0x31480,
2307                 0x314a8, 0x314a8,
2308                 0x314b0, 0x314b4,
2309                 0x314c8, 0x314d4,
2310                 0x31a40, 0x31a4c,
2311                 0x31af0, 0x31b20,
2312                 0x31b38, 0x31b3c,
2313                 0x31b80, 0x31b80,
2314                 0x31ba8, 0x31ba8,
2315                 0x31bb0, 0x31bb4,
2316                 0x31bc8, 0x31bd4,
2317                 0x32140, 0x3218c,
2318                 0x321f0, 0x321f4,
2319                 0x32200, 0x32200,
2320                 0x32218, 0x32218,
2321                 0x32400, 0x32400,
2322                 0x32408, 0x3241c,
2323                 0x32618, 0x32620,
2324                 0x32664, 0x32664,
2325                 0x326a8, 0x326a8,
2326                 0x326ec, 0x326ec,
2327                 0x32a00, 0x32abc,
2328                 0x32b00, 0x32b38,
2329                 0x32b40, 0x32b58,
2330                 0x32b60, 0x32b78,
2331                 0x32c00, 0x32c00,
2332                 0x32c08, 0x32c3c,
2333                 0x32e00, 0x32e2c,
2334                 0x32f00, 0x32f2c,
2335                 0x33000, 0x3302c,
2336                 0x33034, 0x33050,
2337                 0x33058, 0x33058,
2338                 0x33060, 0x3308c,
2339                 0x3309c, 0x330ac,
2340                 0x330c0, 0x330c0,
2341                 0x330c8, 0x330d0,
2342                 0x330d8, 0x330e0,
2343                 0x330ec, 0x3312c,
2344                 0x33134, 0x33150,
2345                 0x33158, 0x33158,
2346                 0x33160, 0x3318c,
2347                 0x3319c, 0x331ac,
2348                 0x331c0, 0x331c0,
2349                 0x331c8, 0x331d0,
2350                 0x331d8, 0x331e0,
2351                 0x331ec, 0x33290,
2352                 0x33298, 0x332c4,
2353                 0x332e4, 0x33390,
2354                 0x33398, 0x333c4,
2355                 0x333e4, 0x3342c,
2356                 0x33434, 0x33450,
2357                 0x33458, 0x33458,
2358                 0x33460, 0x3348c,
2359                 0x3349c, 0x334ac,
2360                 0x334c0, 0x334c0,
2361                 0x334c8, 0x334d0,
2362                 0x334d8, 0x334e0,
2363                 0x334ec, 0x3352c,
2364                 0x33534, 0x33550,
2365                 0x33558, 0x33558,
2366                 0x33560, 0x3358c,
2367                 0x3359c, 0x335ac,
2368                 0x335c0, 0x335c0,
2369                 0x335c8, 0x335d0,
2370                 0x335d8, 0x335e0,
2371                 0x335ec, 0x33690,
2372                 0x33698, 0x336c4,
2373                 0x336e4, 0x33790,
2374                 0x33798, 0x337c4,
2375                 0x337e4, 0x337fc,
2376                 0x33814, 0x33814,
2377                 0x33854, 0x33868,
2378                 0x33880, 0x3388c,
2379                 0x338c0, 0x338d0,
2380                 0x338e8, 0x338ec,
2381                 0x33900, 0x3392c,
2382                 0x33934, 0x33950,
2383                 0x33958, 0x33958,
2384                 0x33960, 0x3398c,
2385                 0x3399c, 0x339ac,
2386                 0x339c0, 0x339c0,
2387                 0x339c8, 0x339d0,
2388                 0x339d8, 0x339e0,
2389                 0x339ec, 0x33a90,
2390                 0x33a98, 0x33ac4,
2391                 0x33ae4, 0x33b10,
2392                 0x33b24, 0x33b28,
2393                 0x33b38, 0x33b50,
2394                 0x33bf0, 0x33c10,
2395                 0x33c24, 0x33c28,
2396                 0x33c38, 0x33c50,
2397                 0x33cf0, 0x33cfc,
2398                 0x34000, 0x34030,
2399                 0x34038, 0x34038,
2400                 0x34040, 0x34040,
2401                 0x34048, 0x34048,
2402                 0x34050, 0x34050,
2403                 0x3405c, 0x34060,
2404                 0x34068, 0x34068,
2405                 0x34070, 0x34070,
2406                 0x34100, 0x34168,
2407                 0x34190, 0x341a0,
2408                 0x341a8, 0x341b8,
2409                 0x341c4, 0x341c8,
2410                 0x341d0, 0x341d0,
2411                 0x34200, 0x34320,
2412                 0x34400, 0x344b4,
2413                 0x344c0, 0x3452c,
2414                 0x34540, 0x3461c,
2415                 0x34800, 0x348a0,
2416                 0x348c0, 0x34908,
2417                 0x34910, 0x349b8,
2418                 0x34a00, 0x34a04,
2419                 0x34a0c, 0x34a14,
2420                 0x34a1c, 0x34a2c,
2421                 0x34a44, 0x34a50,
2422                 0x34a74, 0x34a74,
2423                 0x34a7c, 0x34afc,
2424                 0x34b08, 0x34c24,
2425                 0x34d00, 0x34d14,
2426                 0x34d1c, 0x34d3c,
2427                 0x34d44, 0x34d4c,
2428                 0x34d54, 0x34d74,
2429                 0x34d7c, 0x34d7c,
2430                 0x34de0, 0x34de0,
2431                 0x34e00, 0x34ed4,
2432                 0x34f00, 0x34fa4,
2433                 0x34fc0, 0x34fc4,
2434                 0x35000, 0x35004,
2435                 0x35080, 0x350fc,
2436                 0x35208, 0x35220,
2437                 0x3523c, 0x35254,
2438                 0x35300, 0x35300,
2439                 0x35308, 0x3531c,
2440                 0x35338, 0x3533c,
2441                 0x35380, 0x35380,
2442                 0x35388, 0x353a8,
2443                 0x353b4, 0x353b4,
2444                 0x35400, 0x35420,
2445                 0x35438, 0x3543c,
2446                 0x35480, 0x35480,
2447                 0x354a8, 0x354a8,
2448                 0x354b0, 0x354b4,
2449                 0x354c8, 0x354d4,
2450                 0x35a40, 0x35a4c,
2451                 0x35af0, 0x35b20,
2452                 0x35b38, 0x35b3c,
2453                 0x35b80, 0x35b80,
2454                 0x35ba8, 0x35ba8,
2455                 0x35bb0, 0x35bb4,
2456                 0x35bc8, 0x35bd4,
2457                 0x36140, 0x3618c,
2458                 0x361f0, 0x361f4,
2459                 0x36200, 0x36200,
2460                 0x36218, 0x36218,
2461                 0x36400, 0x36400,
2462                 0x36408, 0x3641c,
2463                 0x36618, 0x36620,
2464                 0x36664, 0x36664,
2465                 0x366a8, 0x366a8,
2466                 0x366ec, 0x366ec,
2467                 0x36a00, 0x36abc,
2468                 0x36b00, 0x36b38,
2469                 0x36b40, 0x36b58,
2470                 0x36b60, 0x36b78,
2471                 0x36c00, 0x36c00,
2472                 0x36c08, 0x36c3c,
2473                 0x36e00, 0x36e2c,
2474                 0x36f00, 0x36f2c,
2475                 0x37000, 0x3702c,
2476                 0x37034, 0x37050,
2477                 0x37058, 0x37058,
2478                 0x37060, 0x3708c,
2479                 0x3709c, 0x370ac,
2480                 0x370c0, 0x370c0,
2481                 0x370c8, 0x370d0,
2482                 0x370d8, 0x370e0,
2483                 0x370ec, 0x3712c,
2484                 0x37134, 0x37150,
2485                 0x37158, 0x37158,
2486                 0x37160, 0x3718c,
2487                 0x3719c, 0x371ac,
2488                 0x371c0, 0x371c0,
2489                 0x371c8, 0x371d0,
2490                 0x371d8, 0x371e0,
2491                 0x371ec, 0x37290,
2492                 0x37298, 0x372c4,
2493                 0x372e4, 0x37390,
2494                 0x37398, 0x373c4,
2495                 0x373e4, 0x3742c,
2496                 0x37434, 0x37450,
2497                 0x37458, 0x37458,
2498                 0x37460, 0x3748c,
2499                 0x3749c, 0x374ac,
2500                 0x374c0, 0x374c0,
2501                 0x374c8, 0x374d0,
2502                 0x374d8, 0x374e0,
2503                 0x374ec, 0x3752c,
2504                 0x37534, 0x37550,
2505                 0x37558, 0x37558,
2506                 0x37560, 0x3758c,
2507                 0x3759c, 0x375ac,
2508                 0x375c0, 0x375c0,
2509                 0x375c8, 0x375d0,
2510                 0x375d8, 0x375e0,
2511                 0x375ec, 0x37690,
2512                 0x37698, 0x376c4,
2513                 0x376e4, 0x37790,
2514                 0x37798, 0x377c4,
2515                 0x377e4, 0x377fc,
2516                 0x37814, 0x37814,
2517                 0x37854, 0x37868,
2518                 0x37880, 0x3788c,
2519                 0x378c0, 0x378d0,
2520                 0x378e8, 0x378ec,
2521                 0x37900, 0x3792c,
2522                 0x37934, 0x37950,
2523                 0x37958, 0x37958,
2524                 0x37960, 0x3798c,
2525                 0x3799c, 0x379ac,
2526                 0x379c0, 0x379c0,
2527                 0x379c8, 0x379d0,
2528                 0x379d8, 0x379e0,
2529                 0x379ec, 0x37a90,
2530                 0x37a98, 0x37ac4,
2531                 0x37ae4, 0x37b10,
2532                 0x37b24, 0x37b28,
2533                 0x37b38, 0x37b50,
2534                 0x37bf0, 0x37c10,
2535                 0x37c24, 0x37c28,
2536                 0x37c38, 0x37c50,
2537                 0x37cf0, 0x37cfc,
2538                 0x40040, 0x40040,
2539                 0x40080, 0x40084,
2540                 0x40100, 0x40100,
2541                 0x40140, 0x401bc,
2542                 0x40200, 0x40214,
2543                 0x40228, 0x40228,
2544                 0x40240, 0x40258,
2545                 0x40280, 0x40280,
2546                 0x40304, 0x40304,
2547                 0x40330, 0x4033c,
2548                 0x41304, 0x413b8,
2549                 0x413c0, 0x413c8,
2550                 0x413d0, 0x413dc,
2551                 0x413f0, 0x413f0,
2552                 0x41400, 0x4140c,
2553                 0x41414, 0x4141c,
2554                 0x41480, 0x414d0,
2555                 0x44000, 0x4407c,
2556                 0x440c0, 0x441ac,
2557                 0x441b4, 0x4427c,
2558                 0x442c0, 0x443ac,
2559                 0x443b4, 0x4447c,
2560                 0x444c0, 0x445ac,
2561                 0x445b4, 0x4467c,
2562                 0x446c0, 0x447ac,
2563                 0x447b4, 0x4487c,
2564                 0x448c0, 0x449ac,
2565                 0x449b4, 0x44a7c,
2566                 0x44ac0, 0x44bac,
2567                 0x44bb4, 0x44c7c,
2568                 0x44cc0, 0x44dac,
2569                 0x44db4, 0x44e7c,
2570                 0x44ec0, 0x44fac,
2571                 0x44fb4, 0x4507c,
2572                 0x450c0, 0x451ac,
2573                 0x451b4, 0x451fc,
2574                 0x45800, 0x45804,
2575                 0x45810, 0x45830,
2576                 0x45840, 0x45860,
2577                 0x45868, 0x45868,
2578                 0x45880, 0x45884,
2579                 0x458a0, 0x458b0,
2580                 0x45a00, 0x45a04,
2581                 0x45a10, 0x45a30,
2582                 0x45a40, 0x45a60,
2583                 0x45a68, 0x45a68,
2584                 0x45a80, 0x45a84,
2585                 0x45aa0, 0x45ab0,
2586                 0x460c0, 0x460e4,
2587                 0x47000, 0x4703c,
2588                 0x47044, 0x4708c,
2589                 0x47200, 0x47250,
2590                 0x47400, 0x47408,
2591                 0x47414, 0x47420,
2592                 0x47600, 0x47618,
2593                 0x47800, 0x47814,
2594                 0x47820, 0x4782c,
2595                 0x50000, 0x50084,
2596                 0x50090, 0x500cc,
2597                 0x50300, 0x50384,
2598                 0x50400, 0x50400,
2599                 0x50800, 0x50884,
2600                 0x50890, 0x508cc,
2601                 0x50b00, 0x50b84,
2602                 0x50c00, 0x50c00,
2603                 0x51000, 0x51020,
2604                 0x51028, 0x510b0,
2605                 0x51300, 0x51324,
2606         };
2607
2608         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2609         const unsigned int *reg_ranges;
2610         int reg_ranges_size, range;
2611         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2612
2613         /* Select the right set of register ranges to dump depending on the
2614          * adapter chip type.
2615          */
2616         switch (chip_version) {
2617         case CHELSIO_T4:
2618                 reg_ranges = t4_reg_ranges;
2619                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2620                 break;
2621
2622         case CHELSIO_T5:
2623                 reg_ranges = t5_reg_ranges;
2624                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2625                 break;
2626
2627         case CHELSIO_T6:
2628                 reg_ranges = t6_reg_ranges;
2629                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2630                 break;
2631
2632         default:
2633                 dev_err(adap->pdev_dev,
2634                         "Unsupported chip version %d\n", chip_version);
2635                 return;
2636         }
2637
2638         /* Clear the register buffer and insert the appropriate register
2639          * values selected by the above register ranges.
2640          */
2641         memset(buf, 0, buf_size);
2642         for (range = 0; range < reg_ranges_size; range += 2) {
2643                 unsigned int reg = reg_ranges[range];
2644                 unsigned int last_reg = reg_ranges[range + 1];
2645                 u32 *bufp = (u32 *)((char *)buf + reg);
2646
2647                 /* Iterate across the register range filling in the register
2648                  * buffer but don't write past the end of the register buffer.
2649                  */
2650                 while (reg <= last_reg && bufp < buf_end) {
2651                         *bufp++ = t4_read_reg(adap, reg);
2652                         reg += sizeof(u32);
2653                 }
2654         }
2655 }
2656
2657 #define EEPROM_STAT_ADDR   0x7bfc
2658 #define VPD_SIZE           0x800
2659 #define VPD_BASE           0x400
2660 #define VPD_BASE_OLD       0
2661 #define VPD_LEN            1024
2662 #define CHELSIO_VPD_UNIQUE_ID 0x82
2663
2664 /**
2665  *      t4_seeprom_wp - enable/disable EEPROM write protection
2666  *      @adapter: the adapter
2667  *      @enable: whether to enable or disable write protection
2668  *
2669  *      Enables or disables write protection on the serial EEPROM.
2670  */
2671 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2672 {
2673         unsigned int v = enable ? 0xc : 0;
2674         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2675         return ret < 0 ? ret : 0;
2676 }
2677
2678 /**
2679  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2680  *      @adapter: adapter to read
2681  *      @p: where to store the parameters
2682  *
2683  *      Reads card parameters stored in VPD EEPROM.
2684  */
2685 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2686 {
2687         int i, ret = 0, addr;
2688         int ec, sn, pn, na;
2689         u8 *vpd, csum;
2690         unsigned int vpdr_len, kw_offset, id_len;
2691
2692         vpd = vmalloc(VPD_LEN);
2693         if (!vpd)
2694                 return -ENOMEM;
2695
2696         /* We have two VPD data structures stored in the adapter VPD area.
2697          * By default, Linux calculates the size of the VPD area by traversing
2698          * the first VPD area at offset 0x0, so we need to tell the OS what
2699          * our real VPD size is.
2700          */
2701         ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2702         if (ret < 0)
2703                 goto out;
2704
2705         /* Card information normally starts at VPD_BASE but early cards had
2706          * it at 0.
2707          */
2708         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2709         if (ret < 0)
2710                 goto out;
2711
2712         /* The VPD shall have a unique identifier specified by the PCI SIG.
2713          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2714          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2715          * is expected to automatically put this entry at the
2716          * beginning of the VPD.
2717          */
2718         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2719
2720         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2721         if (ret < 0)
2722                 goto out;
2723
2724         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2725                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2726                 ret = -EINVAL;
2727                 goto out;
2728         }
2729
2730         id_len = pci_vpd_lrdt_size(vpd);
2731         if (id_len > ID_LEN)
2732                 id_len = ID_LEN;
2733
2734         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2735         if (i < 0) {
2736                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2737                 ret = -EINVAL;
2738                 goto out;
2739         }
2740
2741         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2742         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2743         if (vpdr_len + kw_offset > VPD_LEN) {
2744                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2745                 ret = -EINVAL;
2746                 goto out;
2747         }
2748
2749 #define FIND_VPD_KW(var, name) do { \
2750         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2751         if (var < 0) { \
2752                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2753                 ret = -EINVAL; \
2754                 goto out; \
2755         } \
2756         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2757 } while (0)
2758
2759         FIND_VPD_KW(i, "RV");
2760         for (csum = 0; i >= 0; i--)
2761                 csum += vpd[i];
2762
2763         if (csum) {
2764                 dev_err(adapter->pdev_dev,
2765                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2766                 ret = -EINVAL;
2767                 goto out;
2768         }
2769
2770         FIND_VPD_KW(ec, "EC");
2771         FIND_VPD_KW(sn, "SN");
2772         FIND_VPD_KW(pn, "PN");
2773         FIND_VPD_KW(na, "NA");
2774 #undef FIND_VPD_KW
2775
2776         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2777         strim(p->id);
2778         memcpy(p->ec, vpd + ec, EC_LEN);
2779         strim(p->ec);
2780         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2781         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2782         strim(p->sn);
2783         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2784         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2785         strim(p->pn);
2786         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2787         strim((char *)p->na);
2788
2789 out:
2790         vfree(vpd);
2791         return ret < 0 ? ret : 0;
2792 }
2793
2794 /**
2795  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2796  *      @adapter: adapter to read
2797  *      @p: where to store the parameters
2798  *
2799  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2800  *      Clock.  This can only be called after a connection to the firmware
2801  *      is established.
2802  */
2803 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2804 {
2805         u32 cclk_param, cclk_val;
2806         int ret;
2807
2808         /* Grab the raw VPD parameters.
2809          */
2810         ret = t4_get_raw_vpd_params(adapter, p);
2811         if (ret)
2812                 return ret;
2813
2814         /* Ask firmware for the Core Clock since it knows how to translate the
2815          * Reference Clock ('V2') VPD field into a Core Clock value ...
2816          */
2817         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2818                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2819         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2820                               1, &cclk_param, &cclk_val);
2821
2822         if (ret)
2823                 return ret;
2824         p->cclk = cclk_val;
2825
2826         return 0;
2827 }
2828
2829 /* serial flash and firmware constants */
2830 enum {
2831         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2832
2833         /* flash command opcodes */
2834         SF_PROG_PAGE    = 2,          /* program page */
2835         SF_WR_DISABLE   = 4,          /* disable writes */
2836         SF_RD_STATUS    = 5,          /* read status register */
2837         SF_WR_ENABLE    = 6,          /* enable writes */
2838         SF_RD_DATA_FAST = 0xb,        /* read flash */
2839         SF_RD_ID        = 0x9f,       /* read ID */
2840         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2841
2842         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2843 };
2844
2845 /**
2846  *      sf1_read - read data from the serial flash
2847  *      @adapter: the adapter
2848  *      @byte_cnt: number of bytes to read
2849  *      @cont: whether another operation will be chained
2850  *      @lock: whether to lock SF for PL access only
2851  *      @valp: where to store the read data
2852  *
2853  *      Reads up to 4 bytes of data from the serial flash.  The location of
2854  *      the read needs to be specified prior to calling this by issuing the
2855  *      appropriate commands to the serial flash.
2856  */
2857 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2858                     int lock, u32 *valp)
2859 {
2860         int ret;
2861
2862         if (!byte_cnt || byte_cnt > 4)
2863                 return -EINVAL;
2864         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2865                 return -EBUSY;
2866         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2867                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2868         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2869         if (!ret)
2870                 *valp = t4_read_reg(adapter, SF_DATA_A);
2871         return ret;
2872 }
2873
2874 /**
2875  *      sf1_write - write data to the serial flash
2876  *      @adapter: the adapter
2877  *      @byte_cnt: number of bytes to write
2878  *      @cont: whether another operation will be chained
2879  *      @lock: whether to lock SF for PL access only
2880  *      @val: value to write
2881  *
2882  *      Writes up to 4 bytes of data to the serial flash.  The location of
2883  *      the write needs to be specified prior to calling this by issuing the
2884  *      appropriate commands to the serial flash.
2885  */
2886 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2887                      int lock, u32 val)
2888 {
2889         if (!byte_cnt || byte_cnt > 4)
2890                 return -EINVAL;
2891         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2892                 return -EBUSY;
2893         t4_write_reg(adapter, SF_DATA_A, val);
2894         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2895                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2896         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2897 }
2898
2899 /**
2900  *      flash_wait_op - wait for a flash operation to complete
2901  *      @adapter: the adapter
2902  *      @attempts: max number of polls of the status register
2903  *      @delay: delay between polls in ms
2904  *
2905  *      Wait for a flash operation to complete by polling the status register.
2906  */
2907 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2908 {
2909         int ret;
2910         u32 status;
2911
2912         while (1) {
2913                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2914                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2915                         return ret;
2916                 if (!(status & 1))
2917                         return 0;
2918                 if (--attempts == 0)
2919                         return -EAGAIN;
2920                 if (delay)
2921                         msleep(delay);
2922         }
2923 }
2924
2925 /**
2926  *      t4_read_flash - read words from serial flash
2927  *      @adapter: the adapter
2928  *      @addr: the start address for the read
2929  *      @nwords: how many 32-bit words to read
2930  *      @data: where to store the read data
2931  *      @byte_oriented: whether to store data as bytes or as words
2932  *
2933  *      Read the specified number of 32-bit words from the serial flash.
2934  *      If @byte_oriented is set the read data is stored as a byte array
2935  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2936  *      natural endianness.
2937  */
2938 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2939                   unsigned int nwords, u32 *data, int byte_oriented)
2940 {
2941         int ret;
2942
2943         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2944                 return -EINVAL;
2945
2946         addr = swab32(addr) | SF_RD_DATA_FAST;
2947
2948         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2949             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2950                 return ret;
2951
2952         for ( ; nwords; nwords--, data++) {
2953                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2954                 if (nwords == 1)
2955                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2956                 if (ret)
2957                         return ret;
2958                 if (byte_oriented)
2959                         *data = (__force __u32)(cpu_to_be32(*data));
2960         }
2961         return 0;
2962 }
2963
2964 /**
2965  *      t4_write_flash - write up to a page of data to the serial flash
2966  *      @adapter: the adapter
2967  *      @addr: the start address to write
2968  *      @n: length of data to write in bytes
2969  *      @data: the data to write
2970  *
2971  *      Writes up to a page of data (256 bytes) to the serial flash starting
2972  *      at the given address.  All the data must be written to the same page.
2973  */
2974 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2975                           unsigned int n, const u8 *data)
2976 {
2977         int ret;
2978         u32 buf[64];
2979         unsigned int i, c, left, val, offset = addr & 0xff;
2980
2981         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2982                 return -EINVAL;
2983
2984         val = swab32(addr) | SF_PROG_PAGE;
2985
2986         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2987             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2988                 goto unlock;
2989
2990         for (left = n; left; left -= c) {
2991                 c = min(left, 4U);
2992                 for (val = 0, i = 0; i < c; ++i)
2993                         val = (val << 8) + *data++;
2994
2995                 ret = sf1_write(adapter, c, c != left, 1, val);
2996                 if (ret)
2997                         goto unlock;
2998         }
2999         ret = flash_wait_op(adapter, 8, 1);
3000         if (ret)
3001                 goto unlock;
3002
3003         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3004
3005         /* Read the page to verify the write succeeded */
3006         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3007         if (ret)
3008                 return ret;
3009
3010         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3011                 dev_err(adapter->pdev_dev,
3012                         "failed to correctly write the flash page at %#x\n",
3013                         addr);
3014                 return -EIO;
3015         }
3016         return 0;
3017
3018 unlock:
3019         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3020         return ret;
3021 }
3022
3023 /**
3024  *      t4_get_fw_version - read the firmware version
3025  *      @adapter: the adapter
3026  *      @vers: where to place the version
3027  *
3028  *      Reads the FW version from flash.
3029  */
3030 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3031 {
3032         return t4_read_flash(adapter, FLASH_FW_START +
3033                              offsetof(struct fw_hdr, fw_ver), 1,
3034                              vers, 0);
3035 }
3036
3037 /**
3038  *      t4_get_bs_version - read the firmware bootstrap version
3039  *      @adapter: the adapter
3040  *      @vers: where to place the version
3041  *
3042  *      Reads the FW Bootstrap version from flash.
3043  */
3044 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3045 {
3046         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3047                              offsetof(struct fw_hdr, fw_ver), 1,
3048                              vers, 0);
3049 }
3050
3051 /**
3052  *      t4_get_tp_version - read the TP microcode version
3053  *      @adapter: the adapter
3054  *      @vers: where to place the version
3055  *
3056  *      Reads the TP microcode version from flash.
3057  */
3058 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3059 {
3060         return t4_read_flash(adapter, FLASH_FW_START +
3061                              offsetof(struct fw_hdr, tp_microcode_ver),
3062                              1, vers, 0);
3063 }
3064
3065 /**
3066  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3067  *      @adapter: the adapter
3068  *      @vers: where to place the version
3069  *
3070  *      Reads the Expansion ROM header from FLASH and returns the version
3071  *      number (if present) through the @vers return value pointer.  We return
3072  *      this in the Firmware Version Format since it's convenient.  Return
3073  *      0 on success, -ENOENT if no Expansion ROM is present.
3074  */
3075 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3076 {
3077         struct exprom_header {
3078                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3079                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3080         } *hdr;
3081         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3082                                            sizeof(u32))];
3083         int ret;
3084
3085         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3086                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3087                             0);
3088         if (ret)
3089                 return ret;
3090
3091         hdr = (struct exprom_header *)exprom_header_buf;
3092         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3093                 return -ENOENT;
3094
3095         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3096                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3097                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3098                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3099         return 0;
3100 }
3101
3102 /**
3103  *      t4_check_fw_version - check if the FW is supported with this driver
3104  *      @adap: the adapter
3105  *
3106  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3107  *      if there's exact match, a negative error if the version could not be
3108  *      read or there's a major version mismatch
3109  */
3110 int t4_check_fw_version(struct adapter *adap)
3111 {
3112         int i, ret, major, minor, micro;
3113         int exp_major, exp_minor, exp_micro;
3114         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3115
3116         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3117         /* Try multiple times before returning error */
3118         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3119                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3120
3121         if (ret)
3122                 return ret;
3123
3124         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3125         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3126         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3127
3128         switch (chip_version) {
3129         case CHELSIO_T4:
3130                 exp_major = T4FW_MIN_VERSION_MAJOR;
3131                 exp_minor = T4FW_MIN_VERSION_MINOR;
3132                 exp_micro = T4FW_MIN_VERSION_MICRO;
3133                 break;
3134         case CHELSIO_T5:
3135                 exp_major = T5FW_MIN_VERSION_MAJOR;
3136                 exp_minor = T5FW_MIN_VERSION_MINOR;
3137                 exp_micro = T5FW_MIN_VERSION_MICRO;
3138                 break;
3139         case CHELSIO_T6:
3140                 exp_major = T6FW_MIN_VERSION_MAJOR;
3141                 exp_minor = T6FW_MIN_VERSION_MINOR;
3142                 exp_micro = T6FW_MIN_VERSION_MICRO;
3143                 break;
3144         default:
3145                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3146                         adap->chip);
3147                 return -EINVAL;
3148         }
3149
3150         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3151             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3152                 dev_err(adap->pdev_dev,
3153                         "Card has firmware version %u.%u.%u, minimum "
3154                         "supported firmware is %u.%u.%u.\n", major, minor,
3155                         micro, exp_major, exp_minor, exp_micro);
3156                 return -EFAULT;
3157         }
3158         return 0;
3159 }
3160
3161 /* Is the given firmware API compatible with the one the driver was compiled
3162  * with?
3163  */
3164 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3165 {
3166
3167         /* short circuit if it's the exact same firmware version */
3168         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3169                 return 1;
3170
3171 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3172         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3173             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3174                 return 1;
3175 #undef SAME_INTF
3176
3177         return 0;
3178 }
3179
3180 /* The firmware in the filesystem is usable, but should it be installed?
3181  * This routine explains itself in detail if it indicates the filesystem
3182  * firmware should be installed.
3183  */
3184 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3185                                 int k, int c)
3186 {
3187         const char *reason;
3188
3189         if (!card_fw_usable) {
3190                 reason = "incompatible or unusable";
3191                 goto install;
3192         }
3193
3194         if (k > c) {
3195                 reason = "older than the version supported with this driver";
3196                 goto install;
3197         }
3198
3199         return 0;
3200
3201 install:
3202         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3203                 "installing firmware %u.%u.%u.%u on card.\n",
3204                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3205                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3206                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3207                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3208
3209         return 1;
3210 }
3211
3212 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3213                const u8 *fw_data, unsigned int fw_size,
3214                struct fw_hdr *card_fw, enum dev_state state,
3215                int *reset)
3216 {
3217         int ret, card_fw_usable, fs_fw_usable;
3218         const struct fw_hdr *fs_fw;
3219         const struct fw_hdr *drv_fw;
3220
3221         drv_fw = &fw_info->fw_hdr;
3222
3223         /* Read the header of the firmware on the card */
3224         ret = -t4_read_flash(adap, FLASH_FW_START,
3225                             sizeof(*card_fw) / sizeof(uint32_t),
3226                             (uint32_t *)card_fw, 1);
3227         if (ret == 0) {
3228                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3229         } else {
3230                 dev_err(adap->pdev_dev,
3231                         "Unable to read card's firmware header: %d\n", ret);
3232                 card_fw_usable = 0;
3233         }
3234
3235         if (fw_data != NULL) {
3236                 fs_fw = (const void *)fw_data;
3237                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3238         } else {
3239                 fs_fw = NULL;
3240                 fs_fw_usable = 0;
3241         }
3242
3243         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3244             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3245                 /* Common case: the firmware on the card is an exact match and
3246                  * the filesystem one is an exact match too, or the filesystem
3247                  * one is absent/incompatible.
3248                  */
3249         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3250                    should_install_fs_fw(adap, card_fw_usable,
3251                                         be32_to_cpu(fs_fw->fw_ver),
3252                                         be32_to_cpu(card_fw->fw_ver))) {
3253                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3254                                      fw_size, 0);
3255                 if (ret != 0) {
3256                         dev_err(adap->pdev_dev,
3257                                 "failed to install firmware: %d\n", ret);
3258                         goto bye;
3259                 }
3260
3261                 /* Installed successfully, update the cached header too. */
3262                 *card_fw = *fs_fw;
3263                 card_fw_usable = 1;
3264                 *reset = 0;     /* already reset as part of load_fw */
3265         }
3266
3267         if (!card_fw_usable) {
3268                 uint32_t d, c, k;
3269
3270                 d = be32_to_cpu(drv_fw->fw_ver);
3271                 c = be32_to_cpu(card_fw->fw_ver);
3272                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3273
3274                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3275                         "chip state %d, "
3276                         "driver compiled with %d.%d.%d.%d, "
3277                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3278                         state,
3279                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3280                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3281                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3282                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3283                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3284                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3285                 ret = EINVAL;
3286                 goto bye;
3287         }
3288
3289         /* We're using whatever's on the card and it's known to be good. */
3290         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3291         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3292
3293 bye:
3294         return ret;
3295 }
3296
3297 /**
3298  *      t4_flash_erase_sectors - erase a range of flash sectors
3299  *      @adapter: the adapter
3300  *      @start: the first sector to erase
3301  *      @end: the last sector to erase
3302  *
3303  *      Erases the sectors in the given inclusive range.
3304  */
3305 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3306 {
3307         int ret = 0;
3308
3309         if (end >= adapter->params.sf_nsec)
3310                 return -EINVAL;
3311
3312         while (start <= end) {
3313                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3314                     (ret = sf1_write(adapter, 4, 0, 1,
3315                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3316                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3317                         dev_err(adapter->pdev_dev,
3318                                 "erase of flash sector %d failed, error %d\n",
3319                                 start, ret);
3320                         break;
3321                 }
3322                 start++;
3323         }
3324         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3325         return ret;
3326 }
3327
3328 /**
3329  *      t4_flash_cfg_addr - return the address of the flash configuration file
3330  *      @adapter: the adapter
3331  *
3332  *      Return the address within the flash where the Firmware Configuration
3333  *      File is stored.
3334  */
3335 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3336 {
3337         if (adapter->params.sf_size == 0x100000)
3338                 return FLASH_FPGA_CFG_START;
3339         else
3340                 return FLASH_CFG_START;
3341 }
3342
3343 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3344  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3345  * and emit an error message for mismatched firmware to save our caller the
3346  * effort ...
3347  */
3348 static bool t4_fw_matches_chip(const struct adapter *adap,
3349                                const struct fw_hdr *hdr)
3350 {
3351         /* The expression below will return FALSE for any unsupported adapter
3352          * which will keep us "honest" in the future ...
3353          */
3354         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3355             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3356             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3357                 return true;
3358
3359         dev_err(adap->pdev_dev,
3360                 "FW image (%d) is not suitable for this adapter (%d)\n",
3361                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3362         return false;
3363 }
3364
3365 /**
3366  *      t4_load_fw - download firmware
3367  *      @adap: the adapter
3368  *      @fw_data: the firmware image to write
3369  *      @size: image size
3370  *
3371  *      Write the supplied firmware image to the card's serial flash.
3372  */
3373 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3374 {
3375         u32 csum;
3376         int ret, addr;
3377         unsigned int i;
3378         u8 first_page[SF_PAGE_SIZE];
3379         const __be32 *p = (const __be32 *)fw_data;
3380         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3381         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3382         unsigned int fw_img_start = adap->params.sf_fw_start;
3383         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3384
3385         if (!size) {
3386                 dev_err(adap->pdev_dev, "FW image has no data\n");
3387                 return -EINVAL;
3388         }
3389         if (size & 511) {
3390                 dev_err(adap->pdev_dev,
3391                         "FW image size not multiple of 512 bytes\n");
3392                 return -EINVAL;
3393         }
3394         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3395                 dev_err(adap->pdev_dev,
3396                         "FW image size differs from size in FW header\n");
3397                 return -EINVAL;
3398         }
3399         if (size > FW_MAX_SIZE) {
3400                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3401                         FW_MAX_SIZE);
3402                 return -EFBIG;
3403         }
3404         if (!t4_fw_matches_chip(adap, hdr))
3405                 return -EINVAL;
3406
3407         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3408                 csum += be32_to_cpu(p[i]);
3409
3410         if (csum != 0xffffffff) {
3411                 dev_err(adap->pdev_dev,
3412                         "corrupted firmware image, checksum %#x\n", csum);
3413                 return -EINVAL;
3414         }
3415
3416         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3417         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3418         if (ret)
3419                 goto out;
3420
3421         /*
3422          * We write the correct version at the end so the driver can see a bad
3423          * version if the FW write fails.  Start by writing a copy of the
3424          * first page with a bad version.
3425          */
3426         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3427         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3428         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3429         if (ret)
3430                 goto out;
3431
3432         addr = fw_img_start;
3433         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3434                 addr += SF_PAGE_SIZE;
3435                 fw_data += SF_PAGE_SIZE;
3436                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3437                 if (ret)
3438                         goto out;
3439         }
3440
3441         ret = t4_write_flash(adap,
3442                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3443                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3444 out:
3445         if (ret)
3446                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3447                         ret);
3448         else
3449                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3450         return ret;
3451 }
3452
3453 /**
3454  *      t4_phy_fw_ver - return current PHY firmware version
3455  *      @adap: the adapter
3456  *      @phy_fw_ver: return value buffer for PHY firmware version
3457  *
3458  *      Returns the current version of external PHY firmware on the
3459  *      adapter.
3460  */
3461 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3462 {
3463         u32 param, val;
3464         int ret;
3465
3466         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3467                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3468                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3469                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3470         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3471                               &param, &val);
3472         if (ret < 0)
3473                 return ret;
3474         *phy_fw_ver = val;
3475         return 0;
3476 }
3477
3478 /**
3479  *      t4_load_phy_fw - download port PHY firmware
3480  *      @adap: the adapter
3481  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3482  *      @win_lock: the lock to use to guard the memory copy
3483  *      @phy_fw_version: function to check PHY firmware versions
3484  *      @phy_fw_data: the PHY firmware image to write
3485  *      @phy_fw_size: image size
3486  *
3487  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3488  *      @phy_fw_version is supplied, then it will be used to determine if
3489  *      it's necessary to perform the transfer by comparing the version
3490  *      of any existing adapter PHY firmware with that of the passed in
3491  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3492  *      around the call to t4_memory_rw() which transfers the PHY firmware
3493  *      to the adapter.
3494  *
3495  *      A negative error number will be returned if an error occurs.  If
3496  *      version number support is available and there's no need to upgrade
3497  *      the firmware, 0 will be returned.  If firmware is successfully
3498  *      transferred to the adapter, 1 will be retured.
3499  *
3500  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3501  *      a result, a RESET of the adapter would cause that RAM to lose its
3502  *      contents.  Thus, loading PHY firmware on such adapters must happen
3503  *      after any FW_RESET_CMDs ...
3504  */
3505 int t4_load_phy_fw(struct adapter *adap,
3506                    int win, spinlock_t *win_lock,
3507                    int (*phy_fw_version)(const u8 *, size_t),
3508                    const u8 *phy_fw_data, size_t phy_fw_size)
3509 {
3510         unsigned long mtype = 0, maddr = 0;
3511         u32 param, val;
3512         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3513         int ret;
3514
3515         /* If we have version number support, then check to see if the adapter
3516          * already has up-to-date PHY firmware loaded.
3517          */
3518          if (phy_fw_version) {
3519                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3520                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3521                 if (ret < 0)
3522                         return ret;
3523
3524                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3525                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3526                                 "version %#x\n", cur_phy_fw_ver);
3527                         return 0;
3528                 }
3529         }
3530
3531         /* Ask the firmware where it wants us to copy the PHY firmware image.
3532          * The size of the file requires a special version of the READ coommand
3533          * which will pass the file size via the values field in PARAMS_CMD and
3534          * retrieve the return value from firmware and place it in the same
3535          * buffer values
3536          */
3537         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3538                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3539                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3540                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3541         val = phy_fw_size;
3542         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3543                                  &param, &val, 1);
3544         if (ret < 0)
3545                 return ret;
3546         mtype = val >> 8;
3547         maddr = (val & 0xff) << 16;
3548
3549         /* Copy the supplied PHY Firmware image to the adapter memory location
3550          * allocated by the adapter firmware.
3551          */
3552         if (win_lock)
3553                 spin_lock_bh(win_lock);
3554         ret = t4_memory_rw(adap, win, mtype, maddr,
3555                            phy_fw_size, (__be32 *)phy_fw_data,
3556                            T4_MEMORY_WRITE);
3557         if (win_lock)
3558                 spin_unlock_bh(win_lock);
3559         if (ret)
3560                 return ret;
3561
3562         /* Tell the firmware that the PHY firmware image has been written to
3563          * RAM and it can now start copying it over to the PHYs.  The chip
3564          * firmware will RESET the affected PHYs as part of this operation
3565          * leaving them running the new PHY firmware image.
3566          */
3567         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3568                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3569                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3570                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3571         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3572                                     &param, &val, 30000);
3573
3574         /* If we have version number support, then check to see that the new
3575          * firmware got loaded properly.
3576          */
3577         if (phy_fw_version) {
3578                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3579                 if (ret < 0)
3580                         return ret;
3581
3582                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3583                         CH_WARN(adap, "PHY Firmware did not update: "
3584                                 "version on adapter %#x, "
3585                                 "version flashed %#x\n",
3586                                 cur_phy_fw_ver, new_phy_fw_vers);
3587                         return -ENXIO;
3588                 }
3589         }
3590
3591         return 1;
3592 }
3593
3594 /**
3595  *      t4_fwcache - firmware cache operation
3596  *      @adap: the adapter
3597  *      @op  : the operation (flush or flush and invalidate)
3598  */
3599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3600 {
3601         struct fw_params_cmd c;
3602
3603         memset(&c, 0, sizeof(c));
3604         c.op_to_vfn =
3605                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3606                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3607                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3608                             FW_PARAMS_CMD_VFN_V(0));
3609         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3610         c.param[0].mnem =
3611                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3612                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3613         c.param[0].val = (__force __be32)op;
3614
3615         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3616 }
3617
3618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3619                         unsigned int *pif_req_wrptr,
3620                         unsigned int *pif_rsp_wrptr)
3621 {
3622         int i, j;
3623         u32 cfg, val, req, rsp;
3624
3625         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3626         if (cfg & LADBGEN_F)
3627                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3628
3629         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3630         req = POLADBGWRPTR_G(val);
3631         rsp = PILADBGWRPTR_G(val);
3632         if (pif_req_wrptr)
3633                 *pif_req_wrptr = req;
3634         if (pif_rsp_wrptr)
3635                 *pif_rsp_wrptr = rsp;
3636
3637         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3638                 for (j = 0; j < 6; j++) {
3639                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3640                                      PILADBGRDPTR_V(rsp));
3641                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3642                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3643                         req++;
3644                         rsp++;
3645                 }
3646                 req = (req + 2) & POLADBGRDPTR_M;
3647                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3648         }
3649         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3650 }
3651
3652 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3653 {
3654         u32 cfg;
3655         int i, j, idx;
3656
3657         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3658         if (cfg & LADBGEN_F)
3659                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3660
3661         for (i = 0; i < CIM_MALA_SIZE; i++) {
3662                 for (j = 0; j < 5; j++) {
3663                         idx = 8 * i + j;
3664                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3665                                      PILADBGRDPTR_V(idx));
3666                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3667                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3668                 }
3669         }
3670         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3671 }
3672
3673 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3674 {
3675         unsigned int i, j;
3676
3677         for (i = 0; i < 8; i++) {
3678                 u32 *p = la_buf + i;
3679
3680                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3681                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3682                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3683                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3684                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3685         }
3686 }
3687
3688 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3689                      FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3690                      FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3691                      FW_PORT_CAP_ANEG)
3692
3693 /**
3694  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3695  *      @phy: the PHY to setup
3696  *      @mac: the MAC to setup
3697  *      @lc: the requested link configuration
3698  *
3699  *      Set up a port's MAC and PHY according to a desired link configuration.
3700  *      - If the PHY can auto-negotiate first decide what to advertise, then
3701  *        enable/disable auto-negotiation as desired, and reset.
3702  *      - If the PHY does not auto-negotiate just reset it.
3703  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3704  *        otherwise do it later based on the outcome of auto-negotiation.
3705  */
3706 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3707                   struct link_config *lc)
3708 {
3709         struct fw_port_cmd c;
3710         unsigned int mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3711         unsigned int fc = 0, fec = 0, fw_fec = 0;
3712
3713         lc->link_ok = 0;
3714         if (lc->requested_fc & PAUSE_RX)
3715                 fc |= FW_PORT_CAP_FC_RX;
3716         if (lc->requested_fc & PAUSE_TX)
3717                 fc |= FW_PORT_CAP_FC_TX;
3718
3719         fec = lc->requested_fec & FEC_AUTO ? lc->auto_fec : lc->requested_fec;
3720
3721         if (fec & FEC_RS)
3722                 fw_fec |= FW_PORT_CAP_FEC_RS;
3723         if (fec & FEC_BASER_RS)
3724                 fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
3725
3726         memset(&c, 0, sizeof(c));
3727         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3728                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3729                                      FW_PORT_CMD_PORTID_V(port));
3730         c.action_to_len16 =
3731                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3732                             FW_LEN16(c));
3733
3734         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3735                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3736                                              fc | fw_fec);
3737                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3738         } else if (lc->autoneg == AUTONEG_DISABLE) {
3739                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
3740                                              fw_fec | mdi);
3741                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3742         } else
3743                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc |
3744                                              fw_fec | mdi);
3745
3746         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3747 }
3748
3749 /**
3750  *      t4_restart_aneg - restart autonegotiation
3751  *      @adap: the adapter
3752  *      @mbox: mbox to use for the FW command
3753  *      @port: the port id
3754  *
3755  *      Restarts autonegotiation for the selected port.
3756  */
3757 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3758 {
3759         struct fw_port_cmd c;
3760
3761         memset(&c, 0, sizeof(c));
3762         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3763                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3764                                      FW_PORT_CMD_PORTID_V(port));
3765         c.action_to_len16 =
3766                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3767                             FW_LEN16(c));
3768         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3769         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3770 }
3771
3772 typedef void (*int_handler_t)(struct adapter *adap);
3773
3774 struct intr_info {
3775         unsigned int mask;       /* bits to check in interrupt status */
3776         const char *msg;         /* message to print or NULL */
3777         short stat_idx;          /* stat counter to increment or -1 */
3778         unsigned short fatal;    /* whether the condition reported is fatal */
3779         int_handler_t int_handler; /* platform-specific int handler */
3780 };
3781
3782 /**
3783  *      t4_handle_intr_status - table driven interrupt handler
3784  *      @adapter: the adapter that generated the interrupt
3785  *      @reg: the interrupt status register to process
3786  *      @acts: table of interrupt actions
3787  *
3788  *      A table driven interrupt handler that applies a set of masks to an
3789  *      interrupt status word and performs the corresponding actions if the
3790  *      interrupts described by the mask have occurred.  The actions include
3791  *      optionally emitting a warning or alert message.  The table is terminated
3792  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3793  *      conditions.
3794  */
3795 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3796                                  const struct intr_info *acts)
3797 {
3798         int fatal = 0;
3799         unsigned int mask = 0;
3800         unsigned int status = t4_read_reg(adapter, reg);
3801
3802         for ( ; acts->mask; ++acts) {
3803                 if (!(status & acts->mask))
3804                         continue;
3805                 if (acts->fatal) {
3806                         fatal++;
3807                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3808                                   status & acts->mask);
3809                 } else if (acts->msg && printk_ratelimit())
3810                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3811                                  status & acts->mask);
3812                 if (acts->int_handler)
3813                         acts->int_handler(adapter);
3814                 mask |= acts->mask;
3815         }
3816         status &= mask;
3817         if (status)                           /* clear processed interrupts */
3818                 t4_write_reg(adapter, reg, status);
3819         return fatal;
3820 }
3821
3822 /*
3823  * Interrupt handler for the PCIE module.
3824  */
3825 static void pcie_intr_handler(struct adapter *adapter)
3826 {
3827         static const struct intr_info sysbus_intr_info[] = {
3828                 { RNPP_F, "RXNP array parity error", -1, 1 },
3829                 { RPCP_F, "RXPC array parity error", -1, 1 },
3830                 { RCIP_F, "RXCIF array parity error", -1, 1 },
3831                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3832                 { RFTP_F, "RXFT array parity error", -1, 1 },
3833                 { 0 }
3834         };
3835         static const struct intr_info pcie_port_intr_info[] = {
3836                 { TPCP_F, "TXPC array parity error", -1, 1 },
3837                 { TNPP_F, "TXNP array parity error", -1, 1 },
3838                 { TFTP_F, "TXFT array parity error", -1, 1 },
3839                 { TCAP_F, "TXCA array parity error", -1, 1 },
3840                 { TCIP_F, "TXCIF array parity error", -1, 1 },
3841                 { RCAP_F, "RXCA array parity error", -1, 1 },
3842                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3843                 { RDPE_F, "Rx data parity error", -1, 1 },
3844                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3845                 { 0 }
3846         };
3847         static const struct intr_info pcie_intr_info[] = {
3848                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3849                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3850                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3851                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3852                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3853                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3854                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3855                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3856                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3857                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3858                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3859                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3860                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3861                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3862                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3863                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3864                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3865                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3866                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3867                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3868                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3869                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3870                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3871                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3872                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3873                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3874                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3875                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3876                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3877                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3878                   -1, 0 },
3879                 { 0 }
3880         };
3881
3882         static struct intr_info t5_pcie_intr_info[] = {
3883                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3884                   -1, 1 },
3885                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3886                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3887                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3888                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3889                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3890                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3891                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3892                   -1, 1 },
3893                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3894                   -1, 1 },
3895                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3896                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3897                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3898                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3899                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3900                   -1, 1 },
3901                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3902                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3903                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3904                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3905                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3906                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3907                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3908                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3909                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3910                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3911                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3912                   -1, 1 },
3913                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3914                   -1, 1 },
3915                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3916                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3917                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3918                 { READRSPERR_F, "Outbound read error", -1, 0 },
3919                 { 0 }
3920         };
3921
3922         int fat;
3923
3924         if (is_t4(adapter->params.chip))
3925                 fat = t4_handle_intr_status(adapter,
3926                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3927                                 sysbus_intr_info) +
3928                         t4_handle_intr_status(adapter,
3929                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3930                                         pcie_port_intr_info) +
3931                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3932                                               pcie_intr_info);
3933         else
3934                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3935                                             t5_pcie_intr_info);
3936
3937         if (fat)
3938                 t4_fatal_err(adapter);
3939 }
3940
3941 /*
3942  * TP interrupt handler.
3943  */
3944 static void tp_intr_handler(struct adapter *adapter)
3945 {
3946         static const struct intr_info tp_intr_info[] = {
3947                 { 0x3fffffff, "TP parity error", -1, 1 },
3948                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3949                 { 0 }
3950         };
3951
3952         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3953                 t4_fatal_err(adapter);
3954 }
3955
3956 /*
3957  * SGE interrupt handler.
3958  */
3959 static void sge_intr_handler(struct adapter *adapter)
3960 {
3961         u64 v;
3962         u32 err;
3963
3964         static const struct intr_info sge_intr_info[] = {
3965                 { ERR_CPL_EXCEED_IQE_SIZE_F,
3966                   "SGE received CPL exceeding IQE size", -1, 1 },
3967                 { ERR_INVALID_CIDX_INC_F,
3968                   "SGE GTS CIDX increment too large", -1, 0 },
3969                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3970                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3971                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3972                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
3973                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3974                   0 },
3975                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3976                   0 },
3977                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3978                   0 },
3979                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3980                   0 },
3981                 { ERR_ING_CTXT_PRIO_F,
3982                   "SGE too many priority ingress contexts", -1, 0 },
3983                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3984                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3985                 { 0 }
3986         };
3987
3988         static struct intr_info t4t5_sge_intr_info[] = {
3989                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3990                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3991                 { ERR_EGR_CTXT_PRIO_F,
3992                   "SGE too many priority egress contexts", -1, 0 },
3993                 { 0 }
3994         };
3995
3996         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3997                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3998         if (v) {
3999                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4000                                 (unsigned long long)v);
4001                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4002                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4003         }
4004
4005         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4006         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4007                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4008                                            t4t5_sge_intr_info);
4009
4010         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4011         if (err & ERROR_QID_VALID_F) {
4012                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4013                         ERROR_QID_G(err));
4014                 if (err & UNCAPTURED_ERROR_F)
4015                         dev_err(adapter->pdev_dev,
4016                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4017                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4018                              UNCAPTURED_ERROR_F);
4019         }
4020
4021         if (v != 0)
4022                 t4_fatal_err(adapter);
4023 }
4024
4025 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4026                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4027 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4028                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4029
4030 /*
4031  * CIM interrupt handler.
4032  */
4033 static void cim_intr_handler(struct adapter *adapter)
4034 {
4035         static const struct intr_info cim_intr_info[] = {
4036                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4037                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4038                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4039                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4040                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4041                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4042                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4043                 { 0 }
4044         };
4045         static const struct intr_info cim_upintr_info[] = {
4046                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4047                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4048                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4049                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4050                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4051                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4052                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4053                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4054                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4055                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4056                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4057                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4058                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4059                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4060                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4061                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4062                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4063                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4064                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4065                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4066                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4067                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4068                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4069                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4070                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4071                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4072                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4073                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4074                 { 0 }
4075         };
4076
4077         int fat;
4078
4079         if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4080                 t4_report_fw_error(adapter);
4081
4082         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4083                                     cim_intr_info) +
4084               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4085                                     cim_upintr_info);
4086         if (fat)
4087                 t4_fatal_err(adapter);
4088 }
4089
4090 /*
4091  * ULP RX interrupt handler.
4092  */
4093 static void ulprx_intr_handler(struct adapter *adapter)
4094 {
4095         static const struct intr_info ulprx_intr_info[] = {
4096                 { 0x1800000, "ULPRX context error", -1, 1 },
4097                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4098                 { 0 }
4099         };
4100
4101         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4102                 t4_fatal_err(adapter);
4103 }
4104
4105 /*
4106  * ULP TX interrupt handler.
4107  */
4108 static void ulptx_intr_handler(struct adapter *adapter)
4109 {
4110         static const struct intr_info ulptx_intr_info[] = {
4111                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4112                   0 },
4113                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4114                   0 },
4115                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4116                   0 },
4117                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4118                   0 },
4119                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4120                 { 0 }
4121         };
4122
4123         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4124                 t4_fatal_err(adapter);
4125 }
4126
4127 /*
4128  * PM TX interrupt handler.
4129  */
4130 static void pmtx_intr_handler(struct adapter *adapter)
4131 {
4132         static const struct intr_info pmtx_intr_info[] = {
4133                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4134                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4135                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4136                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4137                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4138                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4139                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4140                   -1, 1 },
4141                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4142                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4143                 { 0 }
4144         };
4145
4146         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4147                 t4_fatal_err(adapter);
4148 }
4149
4150 /*
4151  * PM RX interrupt handler.
4152  */
4153 static void pmrx_intr_handler(struct adapter *adapter)
4154 {
4155         static const struct intr_info pmrx_intr_info[] = {
4156                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4157                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4158                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4159                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4160                   -1, 1 },
4161                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4162                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4163                 { 0 }
4164         };
4165
4166         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4167                 t4_fatal_err(adapter);
4168 }
4169
4170 /*
4171  * CPL switch interrupt handler.
4172  */
4173 static void cplsw_intr_handler(struct adapter *adapter)
4174 {
4175         static const struct intr_info cplsw_intr_info[] = {
4176                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4177                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4178                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4179                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4180                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4181                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4182                 { 0 }
4183         };
4184
4185         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4186                 t4_fatal_err(adapter);
4187 }
4188
4189 /*
4190  * LE interrupt handler.
4191  */
4192 static void le_intr_handler(struct adapter *adap)
4193 {
4194         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4195         static const struct intr_info le_intr_info[] = {
4196                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4197                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4198                 { PARITYERR_F, "LE parity error", -1, 1 },
4199                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4200                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4201                 { 0 }
4202         };
4203
4204         static struct intr_info t6_le_intr_info[] = {
4205                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4206                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4207                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4208                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4209                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4210                 { 0 }
4211         };
4212
4213         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4214                                   (chip <= CHELSIO_T5) ?
4215                                   le_intr_info : t6_le_intr_info))
4216                 t4_fatal_err(adap);
4217 }
4218
4219 /*
4220  * MPS interrupt handler.
4221  */
4222 static void mps_intr_handler(struct adapter *adapter)
4223 {
4224         static const struct intr_info mps_rx_intr_info[] = {
4225                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4226                 { 0 }
4227         };
4228         static const struct intr_info mps_tx_intr_info[] = {
4229                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4230                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4231                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4232                   -1, 1 },
4233                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4234                   -1, 1 },
4235                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4236                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4237                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4238                 { 0 }
4239         };
4240         static const struct intr_info mps_trc_intr_info[] = {
4241                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4242                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4243                   -1, 1 },
4244                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4245                 { 0 }
4246         };
4247         static const struct intr_info mps_stat_sram_intr_info[] = {
4248                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4249                 { 0 }
4250         };
4251         static const struct intr_info mps_stat_tx_intr_info[] = {
4252                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4253                 { 0 }
4254         };
4255         static const struct intr_info mps_stat_rx_intr_info[] = {
4256                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4257                 { 0 }
4258         };
4259         static const struct intr_info mps_cls_intr_info[] = {
4260                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4261                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4262                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4263                 { 0 }
4264         };
4265
4266         int fat;
4267
4268         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4269                                     mps_rx_intr_info) +
4270               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4271                                     mps_tx_intr_info) +
4272               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4273                                     mps_trc_intr_info) +
4274               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4275                                     mps_stat_sram_intr_info) +
4276               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4277                                     mps_stat_tx_intr_info) +
4278               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4279                                     mps_stat_rx_intr_info) +
4280               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4281                                     mps_cls_intr_info);
4282
4283         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4284         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4285         if (fat)
4286                 t4_fatal_err(adapter);
4287 }
4288
4289 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4290                       ECC_UE_INT_CAUSE_F)
4291
4292 /*
4293  * EDC/MC interrupt handler.
4294  */
4295 static void mem_intr_handler(struct adapter *adapter, int idx)
4296 {
4297         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4298
4299         unsigned int addr, cnt_addr, v;
4300
4301         if (idx <= MEM_EDC1) {
4302                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4303                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4304         } else if (idx == MEM_MC) {
4305                 if (is_t4(adapter->params.chip)) {
4306                         addr = MC_INT_CAUSE_A;
4307                         cnt_addr = MC_ECC_STATUS_A;
4308                 } else {
4309                         addr = MC_P_INT_CAUSE_A;
4310                         cnt_addr = MC_P_ECC_STATUS_A;
4311                 }
4312         } else {
4313                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4314                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4315         }
4316
4317         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4318         if (v & PERR_INT_CAUSE_F)
4319                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4320                           name[idx]);
4321         if (v & ECC_CE_INT_CAUSE_F) {
4322                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4323
4324                 t4_edc_err_read(adapter, idx);
4325
4326                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4327                 if (printk_ratelimit())
4328                         dev_warn(adapter->pdev_dev,
4329                                  "%u %s correctable ECC data error%s\n",
4330                                  cnt, name[idx], cnt > 1 ? "s" : "");
4331         }
4332         if (v & ECC_UE_INT_CAUSE_F)
4333                 dev_alert(adapter->pdev_dev,
4334                           "%s uncorrectable ECC data error\n", name[idx]);
4335
4336         t4_write_reg(adapter, addr, v);
4337         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4338                 t4_fatal_err(adapter);
4339 }
4340
4341 /*
4342  * MA interrupt handler.
4343  */
4344 static void ma_intr_handler(struct adapter *adap)
4345 {
4346         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4347
4348         if (status & MEM_PERR_INT_CAUSE_F) {
4349                 dev_alert(adap->pdev_dev,
4350                           "MA parity error, parity status %#x\n",
4351                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4352                 if (is_t5(adap->params.chip))
4353                         dev_alert(adap->pdev_dev,
4354                                   "MA parity error, parity status %#x\n",
4355                                   t4_read_reg(adap,
4356                                               MA_PARITY_ERROR_STATUS2_A));
4357         }
4358         if (status & MEM_WRAP_INT_CAUSE_F) {
4359                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4360                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4361                           "client %u to address %#x\n",
4362                           MEM_WRAP_CLIENT_NUM_G(v),
4363                           MEM_WRAP_ADDRESS_G(v) << 4);
4364         }
4365         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4366         t4_fatal_err(adap);
4367 }
4368
4369 /*
4370  * SMB interrupt handler.
4371  */
4372 static void smb_intr_handler(struct adapter *adap)
4373 {
4374         static const struct intr_info smb_intr_info[] = {
4375                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4376                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4377                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4378                 { 0 }
4379         };
4380
4381         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4382                 t4_fatal_err(adap);
4383 }
4384
4385 /*
4386  * NC-SI interrupt handler.
4387  */
4388 static void ncsi_intr_handler(struct adapter *adap)
4389 {
4390         static const struct intr_info ncsi_intr_info[] = {
4391                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4392                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4393                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4394                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4395                 { 0 }
4396         };
4397
4398         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4399                 t4_fatal_err(adap);
4400 }
4401
4402 /*
4403  * XGMAC interrupt handler.
4404  */
4405 static void xgmac_intr_handler(struct adapter *adap, int port)
4406 {
4407         u32 v, int_cause_reg;
4408
4409         if (is_t4(adap->params.chip))
4410                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4411         else
4412                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4413
4414         v = t4_read_reg(adap, int_cause_reg);
4415
4416         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4417         if (!v)
4418                 return;
4419
4420         if (v & TXFIFO_PRTY_ERR_F)
4421                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4422                           port);
4423         if (v & RXFIFO_PRTY_ERR_F)
4424                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4425                           port);
4426         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4427         t4_fatal_err(adap);
4428 }
4429
4430 /*
4431  * PL interrupt handler.
4432  */
4433 static void pl_intr_handler(struct adapter *adap)
4434 {
4435         static const struct intr_info pl_intr_info[] = {
4436                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4437                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4438                 { 0 }
4439         };
4440
4441         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4442                 t4_fatal_err(adap);
4443 }
4444
4445 #define PF_INTR_MASK (PFSW_F)
4446 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4447                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4448                 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4449
4450 /**
4451  *      t4_slow_intr_handler - control path interrupt handler
4452  *      @adapter: the adapter
4453  *
4454  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4455  *      The designation 'slow' is because it involves register reads, while
4456  *      data interrupts typically don't involve any MMIOs.
4457  */
4458 int t4_slow_intr_handler(struct adapter *adapter)
4459 {
4460         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4461
4462         if (!(cause & GLBL_INTR_MASK))
4463                 return 0;
4464         if (cause & CIM_F)
4465                 cim_intr_handler(adapter);
4466         if (cause & MPS_F)
4467                 mps_intr_handler(adapter);
4468         if (cause & NCSI_F)
4469                 ncsi_intr_handler(adapter);
4470         if (cause & PL_F)
4471                 pl_intr_handler(adapter);
4472         if (cause & SMB_F)
4473                 smb_intr_handler(adapter);
4474         if (cause & XGMAC0_F)
4475                 xgmac_intr_handler(adapter, 0);
4476         if (cause & XGMAC1_F)
4477                 xgmac_intr_handler(adapter, 1);
4478         if (cause & XGMAC_KR0_F)
4479                 xgmac_intr_handler(adapter, 2);
4480         if (cause & XGMAC_KR1_F)
4481                 xgmac_intr_handler(adapter, 3);
4482         if (cause & PCIE_F)
4483                 pcie_intr_handler(adapter);
4484         if (cause & MC_F)
4485                 mem_intr_handler(adapter, MEM_MC);
4486         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4487                 mem_intr_handler(adapter, MEM_MC1);
4488         if (cause & EDC0_F)
4489                 mem_intr_handler(adapter, MEM_EDC0);
4490         if (cause & EDC1_F)
4491                 mem_intr_handler(adapter, MEM_EDC1);
4492         if (cause & LE_F)
4493                 le_intr_handler(adapter);
4494         if (cause & TP_F)
4495                 tp_intr_handler(adapter);
4496         if (cause & MA_F)
4497                 ma_intr_handler(adapter);
4498         if (cause & PM_TX_F)
4499                 pmtx_intr_handler(adapter);
4500         if (cause & PM_RX_F)
4501                 pmrx_intr_handler(adapter);
4502         if (cause & ULP_RX_F)
4503                 ulprx_intr_handler(adapter);
4504         if (cause & CPL_SWITCH_F)
4505                 cplsw_intr_handler(adapter);
4506         if (cause & SGE_F)
4507                 sge_intr_handler(adapter);
4508         if (cause & ULP_TX_F)
4509                 ulptx_intr_handler(adapter);
4510
4511         /* Clear the interrupts just processed for which we are the master. */
4512         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4513         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4514         return 1;
4515 }
4516
4517 /**
4518  *      t4_intr_enable - enable interrupts
4519  *      @adapter: the adapter whose interrupts should be enabled
4520  *
4521  *      Enable PF-specific interrupts for the calling function and the top-level
4522  *      interrupt concentrator for global interrupts.  Interrupts are already
4523  *      enabled at each module, here we just enable the roots of the interrupt
4524  *      hierarchies.
4525  *
4526  *      Note: this function should be called only when the driver manages
4527  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4528  *      function at a time should be doing this.
4529  */
4530 void t4_intr_enable(struct adapter *adapter)
4531 {
4532         u32 val = 0;
4533         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4534         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4535                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4536
4537         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4538                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4539         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4540                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4541                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4542                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4543                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4544                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4545                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4546         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4547         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4548 }
4549
4550 /**
4551  *      t4_intr_disable - disable interrupts
4552  *      @adapter: the adapter whose interrupts should be disabled
4553  *
4554  *      Disable interrupts.  We only disable the top-level interrupt
4555  *      concentrators.  The caller must be a PCI function managing global
4556  *      interrupts.
4557  */
4558 void t4_intr_disable(struct adapter *adapter)
4559 {
4560         u32 whoami, pf;
4561
4562         if (pci_channel_offline(adapter->pdev))
4563                 return;
4564
4565         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4566         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4567                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4568
4569         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4570         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4571 }
4572
4573 /**
4574  *      t4_config_rss_range - configure a portion of the RSS mapping table
4575  *      @adapter: the adapter
4576  *      @mbox: mbox to use for the FW command
4577  *      @viid: virtual interface whose RSS subtable is to be written
4578  *      @start: start entry in the table to write
4579  *      @n: how many table entries to write
4580  *      @rspq: values for the response queue lookup table
4581  *      @nrspq: number of values in @rspq
4582  *
4583  *      Programs the selected part of the VI's RSS mapping table with the
4584  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4585  *      until the full table range is populated.
4586  *
4587  *      The caller must ensure the values in @rspq are in the range allowed for
4588  *      @viid.
4589  */
4590 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4591                         int start, int n, const u16 *rspq, unsigned int nrspq)
4592 {
4593         int ret;
4594         const u16 *rsp = rspq;
4595         const u16 *rsp_end = rspq + nrspq;
4596         struct fw_rss_ind_tbl_cmd cmd;
4597
4598         memset(&cmd, 0, sizeof(cmd));
4599         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4600                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4601                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4602         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4603
4604         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4605         while (n > 0) {
4606                 int nq = min(n, 32);
4607                 __be32 *qp = &cmd.iq0_to_iq2;
4608
4609                 cmd.niqid = cpu_to_be16(nq);
4610                 cmd.startidx = cpu_to_be16(start);
4611
4612                 start += nq;
4613                 n -= nq;
4614
4615                 while (nq > 0) {
4616                         unsigned int v;
4617
4618                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4619                         if (++rsp >= rsp_end)
4620                                 rsp = rspq;
4621                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4622                         if (++rsp >= rsp_end)
4623                                 rsp = rspq;
4624                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4625                         if (++rsp >= rsp_end)
4626                                 rsp = rspq;
4627
4628                         *qp++ = cpu_to_be32(v);
4629                         nq -= 3;
4630                 }
4631
4632                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4633                 if (ret)
4634                         return ret;
4635         }
4636         return 0;
4637 }
4638
4639 /**
4640  *      t4_config_glbl_rss - configure the global RSS mode
4641  *      @adapter: the adapter
4642  *      @mbox: mbox to use for the FW command
4643  *      @mode: global RSS mode
4644  *      @flags: mode-specific flags
4645  *
4646  *      Sets the global RSS mode.
4647  */
4648 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4649                        unsigned int flags)
4650 {
4651         struct fw_rss_glb_config_cmd c;
4652
4653         memset(&c, 0, sizeof(c));
4654         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4655                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4656         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4657         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4658                 c.u.manual.mode_pkd =
4659                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4660         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4661                 c.u.basicvirtual.mode_pkd =
4662                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4663                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4664         } else
4665                 return -EINVAL;
4666         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4667 }
4668
4669 /**
4670  *      t4_config_vi_rss - configure per VI RSS settings
4671  *      @adapter: the adapter
4672  *      @mbox: mbox to use for the FW command
4673  *      @viid: the VI id
4674  *      @flags: RSS flags
4675  *      @defq: id of the default RSS queue for the VI.
4676  *
4677  *      Configures VI-specific RSS properties.
4678  */
4679 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4680                      unsigned int flags, unsigned int defq)
4681 {
4682         struct fw_rss_vi_config_cmd c;
4683
4684         memset(&c, 0, sizeof(c));
4685         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4686                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4687                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4688         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4689         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4690                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4691         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4692 }
4693
4694 /* Read an RSS table row */
4695 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4696 {
4697         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4698         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4699                                    5, 0, val);
4700 }
4701
4702 /**
4703  *      t4_read_rss - read the contents of the RSS mapping table
4704  *      @adapter: the adapter
4705  *      @map: holds the contents of the RSS mapping table
4706  *
4707  *      Reads the contents of the RSS hash->queue mapping table.
4708  */
4709 int t4_read_rss(struct adapter *adapter, u16 *map)
4710 {
4711         u32 val;
4712         int i, ret;
4713
4714         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4715                 ret = rd_rss_row(adapter, i, &val);
4716                 if (ret)
4717                         return ret;
4718                 *map++ = LKPTBLQUEUE0_G(val);
4719                 *map++ = LKPTBLQUEUE1_G(val);
4720         }
4721         return 0;
4722 }
4723
4724 static unsigned int t4_use_ldst(struct adapter *adap)
4725 {
4726         return (adap->flags & FW_OK) || !adap->use_bd;
4727 }
4728
4729 /**
4730  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
4731  *      @adap: the adapter
4732  *      @vals: where the indirect register values are stored/written
4733  *      @nregs: how many indirect registers to read/write
4734  *      @start_idx: index of first indirect register to read/write
4735  *      @rw: Read (1) or Write (0)
4736  *
4737  *      Access TP PIO registers through LDST
4738  */
4739 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4740                             unsigned int start_index, unsigned int rw)
4741 {
4742         int ret, i;
4743         int cmd = FW_LDST_ADDRSPC_TP_PIO;
4744         struct fw_ldst_cmd c;
4745
4746         for (i = 0 ; i < nregs; i++) {
4747                 memset(&c, 0, sizeof(c));
4748                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4749                                                 FW_CMD_REQUEST_F |
4750                                                 (rw ? FW_CMD_READ_F :
4751                                                       FW_CMD_WRITE_F) |
4752                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
4753                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4754
4755                 c.u.addrval.addr = cpu_to_be32(start_index + i);
4756                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4757                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4758                 if (!ret && rw)
4759                         vals[i] = be32_to_cpu(c.u.addrval.val);
4760         }
4761 }
4762
4763 /**
4764  *      t4_read_rss_key - read the global RSS key
4765  *      @adap: the adapter
4766  *      @key: 10-entry array holding the 320-bit RSS key
4767  *
4768  *      Reads the global 320-bit RSS key.
4769  */
4770 void t4_read_rss_key(struct adapter *adap, u32 *key)
4771 {
4772         if (t4_use_ldst(adap))
4773                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4774         else
4775                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4776                                  TP_RSS_SECRET_KEY0_A);
4777 }
4778
4779 /**
4780  *      t4_write_rss_key - program one of the RSS keys
4781  *      @adap: the adapter
4782  *      @key: 10-entry array holding the 320-bit RSS key
4783  *      @idx: which RSS key to write
4784  *
4785  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
4786  *      0..15 the corresponding entry in the RSS key table is written,
4787  *      otherwise the global RSS key is written.
4788  */
4789 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4790 {
4791         u8 rss_key_addr_cnt = 16;
4792         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4793
4794         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4795          * allows access to key addresses 16-63 by using KeyWrAddrX
4796          * as index[5:4](upper 2) into key table
4797          */
4798         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4799             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4800                 rss_key_addr_cnt = 32;
4801
4802         if (t4_use_ldst(adap))
4803                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4804         else
4805                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4806                                   TP_RSS_SECRET_KEY0_A);
4807
4808         if (idx >= 0 && idx < rss_key_addr_cnt) {
4809                 if (rss_key_addr_cnt > 16)
4810                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4811                                      KEYWRADDRX_V(idx >> 4) |
4812                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
4813                 else
4814                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4815                                      KEYWRADDR_V(idx) | KEYWREN_F);
4816         }
4817 }
4818
4819 /**
4820  *      t4_read_rss_pf_config - read PF RSS Configuration Table
4821  *      @adapter: the adapter
4822  *      @index: the entry in the PF RSS table to read
4823  *      @valp: where to store the returned value
4824  *
4825  *      Reads the PF RSS Configuration Table at the specified index and returns
4826  *      the value found there.
4827  */
4828 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4829                            u32 *valp)
4830 {
4831         if (t4_use_ldst(adapter))
4832                 t4_fw_tp_pio_rw(adapter, valp, 1,
4833                                 TP_RSS_PF0_CONFIG_A + index, 1);
4834         else
4835                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4836                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
4837 }
4838
4839 /**
4840  *      t4_read_rss_vf_config - read VF RSS Configuration Table
4841  *      @adapter: the adapter
4842  *      @index: the entry in the VF RSS table to read
4843  *      @vfl: where to store the returned VFL
4844  *      @vfh: where to store the returned VFH
4845  *
4846  *      Reads the VF RSS Configuration Table at the specified index and returns
4847  *      the (VFL, VFH) values found there.
4848  */
4849 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4850                            u32 *vfl, u32 *vfh)
4851 {
4852         u32 vrt, mask, data;
4853
4854         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4855                 mask = VFWRADDR_V(VFWRADDR_M);
4856                 data = VFWRADDR_V(index);
4857         } else {
4858                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
4859                  data = T6_VFWRADDR_V(index);
4860         }
4861
4862         /* Request that the index'th VF Table values be read into VFL/VFH.
4863          */
4864         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4865         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4866         vrt |= data | VFRDEN_F;
4867         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4868
4869         /* Grab the VFL/VFH values ...
4870          */
4871         if (t4_use_ldst(adapter)) {
4872                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4873                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4874         } else {
4875                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4876                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
4877                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4878                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
4879         }
4880 }
4881
4882 /**
4883  *      t4_read_rss_pf_map - read PF RSS Map
4884  *      @adapter: the adapter
4885  *
4886  *      Reads the PF RSS Map register and returns its value.
4887  */
4888 u32 t4_read_rss_pf_map(struct adapter *adapter)
4889 {
4890         u32 pfmap;
4891
4892         if (t4_use_ldst(adapter))
4893                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4894         else
4895                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4896                                  &pfmap, 1, TP_RSS_PF_MAP_A);
4897         return pfmap;
4898 }
4899
4900 /**
4901  *      t4_read_rss_pf_mask - read PF RSS Mask
4902  *      @adapter: the adapter
4903  *
4904  *      Reads the PF RSS Mask register and returns its value.
4905  */
4906 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4907 {
4908         u32 pfmask;
4909
4910         if (t4_use_ldst(adapter))
4911                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4912         else
4913                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4914                                  &pfmask, 1, TP_RSS_PF_MSK_A);
4915         return pfmask;
4916 }
4917
4918 /**
4919  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
4920  *      @adap: the adapter
4921  *      @v4: holds the TCP/IP counter values
4922  *      @v6: holds the TCP/IPv6 counter values
4923  *
4924  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4925  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4926  */
4927 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4928                          struct tp_tcp_stats *v6)
4929 {
4930         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4931
4932 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4933 #define STAT(x)     val[STAT_IDX(x)]
4934 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4935
4936         if (v4) {
4937                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4938                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4939                 v4->tcp_out_rsts = STAT(OUT_RST);
4940                 v4->tcp_in_segs  = STAT64(IN_SEG);
4941                 v4->tcp_out_segs = STAT64(OUT_SEG);
4942                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4943         }
4944         if (v6) {
4945                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4946                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4947                 v6->tcp_out_rsts = STAT(OUT_RST);
4948                 v6->tcp_in_segs  = STAT64(IN_SEG);
4949                 v6->tcp_out_segs = STAT64(OUT_SEG);
4950                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4951         }
4952 #undef STAT64
4953 #undef STAT
4954 #undef STAT_IDX
4955 }
4956
4957 /**
4958  *      t4_tp_get_err_stats - read TP's error MIB counters
4959  *      @adap: the adapter
4960  *      @st: holds the counter values
4961  *
4962  *      Returns the values of TP's error counters.
4963  */
4964 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4965 {
4966         int nchan = adap->params.arch.nchan;
4967
4968         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4969                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4970         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4971                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4972         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4973                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4974         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4975                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4976         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4977                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4978         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4979                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4980         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4981                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4982         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4983                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4984
4985         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4986                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4987 }
4988
4989 /**
4990  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
4991  *      @adap: the adapter
4992  *      @st: holds the counter values
4993  *
4994  *      Returns the values of TP's CPL counters.
4995  */
4996 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4997 {
4998         int nchan = adap->params.arch.nchan;
4999
5000         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5001                          nchan, TP_MIB_CPL_IN_REQ_0_A);
5002         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5003                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
5004
5005 }
5006
5007 /**
5008  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5009  *      @adap: the adapter
5010  *      @st: holds the counter values
5011  *
5012  *      Returns the values of TP's RDMA counters.
5013  */
5014 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5015 {
5016         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5017                          2, TP_MIB_RQE_DFR_PKT_A);
5018 }
5019
5020 /**
5021  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5022  *      @adap: the adapter
5023  *      @idx: the port index
5024  *      @st: holds the counter values
5025  *
5026  *      Returns the values of TP's FCoE counters for the selected port.
5027  */
5028 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5029                        struct tp_fcoe_stats *st)
5030 {
5031         u32 val[2];
5032
5033         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5034                          1, TP_MIB_FCOE_DDP_0_A + idx);
5035         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5036                          1, TP_MIB_FCOE_DROP_0_A + idx);
5037         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5038                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5039         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5040 }
5041
5042 /**
5043  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5044  *      @adap: the adapter
5045  *      @st: holds the counter values
5046  *
5047  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5048  */
5049 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5050 {
5051         u32 val[4];
5052
5053         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5054                          TP_MIB_USM_PKTS_A);
5055         st->frames = val[0];
5056         st->drops = val[1];
5057         st->octets = ((u64)val[2] << 32) | val[3];
5058 }
5059
5060 /**
5061  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5062  *      @adap: the adapter
5063  *      @mtus: where to store the MTU values
5064  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5065  *
5066  *      Reads the HW path MTU table.
5067  */
5068 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5069 {
5070         u32 v;
5071         int i;
5072
5073         for (i = 0; i < NMTUS; ++i) {
5074                 t4_write_reg(adap, TP_MTU_TABLE_A,
5075                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5076                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5077                 mtus[i] = MTUVALUE_G(v);
5078                 if (mtu_log)
5079                         mtu_log[i] = MTUWIDTH_G(v);
5080         }
5081 }
5082
5083 /**
5084  *      t4_read_cong_tbl - reads the congestion control table
5085  *      @adap: the adapter
5086  *      @incr: where to store the alpha values
5087  *
5088  *      Reads the additive increments programmed into the HW congestion
5089  *      control table.
5090  */
5091 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5092 {
5093         unsigned int mtu, w;
5094
5095         for (mtu = 0; mtu < NMTUS; ++mtu)
5096                 for (w = 0; w < NCCTRL_WIN; ++w) {
5097                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5098                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5099                         incr[mtu][w] = (u16)t4_read_reg(adap,
5100                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5101                 }
5102 }
5103
5104 /**
5105  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5106  *      @adap: the adapter
5107  *      @addr: the indirect TP register address
5108  *      @mask: specifies the field within the register to modify
5109  *      @val: new value for the field
5110  *
5111  *      Sets a field of an indirect TP register to the given value.
5112  */
5113 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5114                             unsigned int mask, unsigned int val)
5115 {
5116         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5117         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5118         t4_write_reg(adap, TP_PIO_DATA_A, val);
5119 }
5120
5121 /**
5122  *      init_cong_ctrl - initialize congestion control parameters
5123  *      @a: the alpha values for congestion control
5124  *      @b: the beta values for congestion control
5125  *
5126  *      Initialize the congestion control parameters.
5127  */
5128 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5129 {
5130         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5131         a[9] = 2;
5132         a[10] = 3;
5133         a[11] = 4;
5134         a[12] = 5;
5135         a[13] = 6;
5136         a[14] = 7;
5137         a[15] = 8;
5138         a[16] = 9;
5139         a[17] = 10;
5140         a[18] = 14;
5141         a[19] = 17;
5142         a[20] = 21;
5143         a[21] = 25;
5144         a[22] = 30;
5145         a[23] = 35;
5146         a[24] = 45;
5147         a[25] = 60;
5148         a[26] = 80;
5149         a[27] = 100;
5150         a[28] = 200;
5151         a[29] = 300;
5152         a[30] = 400;
5153         a[31] = 500;
5154
5155         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5156         b[9] = b[10] = 1;
5157         b[11] = b[12] = 2;
5158         b[13] = b[14] = b[15] = b[16] = 3;
5159         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5160         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5161         b[28] = b[29] = 6;
5162         b[30] = b[31] = 7;
5163 }
5164
5165 /* The minimum additive increment value for the congestion control table */
5166 #define CC_MIN_INCR 2U
5167
5168 /**
5169  *      t4_load_mtus - write the MTU and congestion control HW tables
5170  *      @adap: the adapter
5171  *      @mtus: the values for the MTU table
5172  *      @alpha: the values for the congestion control alpha parameter
5173  *      @beta: the values for the congestion control beta parameter
5174  *
5175  *      Write the HW MTU table with the supplied MTUs and the high-speed
5176  *      congestion control table with the supplied alpha, beta, and MTUs.
5177  *      We write the two tables together because the additive increments
5178  *      depend on the MTUs.
5179  */
5180 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5181                   const unsigned short *alpha, const unsigned short *beta)
5182 {
5183         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5184                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5185                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5186                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5187         };
5188
5189         unsigned int i, w;
5190
5191         for (i = 0; i < NMTUS; ++i) {
5192                 unsigned int mtu = mtus[i];
5193                 unsigned int log2 = fls(mtu);
5194
5195                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5196                         log2--;
5197                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5198                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5199
5200                 for (w = 0; w < NCCTRL_WIN; ++w) {
5201                         unsigned int inc;
5202
5203                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5204                                   CC_MIN_INCR);
5205
5206                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5207                                      (w << 16) | (beta[w] << 13) | inc);
5208                 }
5209         }
5210 }
5211
5212 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5213  * clocks.  The formula is
5214  *
5215  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5216  *
5217  * which is equivalent to
5218  *
5219  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5220  */
5221 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5222 {
5223         u64 v = bytes256 * adap->params.vpd.cclk;
5224
5225         return v * 62 + v / 2;
5226 }
5227
5228 /**
5229  *      t4_get_chan_txrate - get the current per channel Tx rates
5230  *      @adap: the adapter
5231  *      @nic_rate: rates for NIC traffic
5232  *      @ofld_rate: rates for offloaded traffic
5233  *
5234  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5235  *      for each channel.
5236  */
5237 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5238 {
5239         u32 v;
5240
5241         v = t4_read_reg(adap, TP_TX_TRATE_A);
5242         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5243         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5244         if (adap->params.arch.nchan == NCHAN) {
5245                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5246                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5247         }
5248
5249         v = t4_read_reg(adap, TP_TX_ORATE_A);
5250         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5251         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5252         if (adap->params.arch.nchan == NCHAN) {
5253                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5254                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5255         }
5256 }
5257
5258 /**
5259  *      t4_set_trace_filter - configure one of the tracing filters
5260  *      @adap: the adapter
5261  *      @tp: the desired trace filter parameters
5262  *      @idx: which filter to configure
5263  *      @enable: whether to enable or disable the filter
5264  *
5265  *      Configures one of the tracing filters available in HW.  If @enable is
5266  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5267  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5268  */
5269 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5270                         int idx, int enable)
5271 {
5272         int i, ofst = idx * 4;
5273         u32 data_reg, mask_reg, cfg;
5274         u32 multitrc = TRCMULTIFILTER_F;
5275
5276         if (!enable) {
5277                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5278                 return 0;
5279         }
5280
5281         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5282         if (cfg & TRCMULTIFILTER_F) {
5283                 /* If multiple tracers are enabled, then maximum
5284                  * capture size is 2.5KB (FIFO size of a single channel)
5285                  * minus 2 flits for CPL_TRACE_PKT header.
5286                  */
5287                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5288                         return -EINVAL;
5289         } else {
5290                 /* If multiple tracers are disabled, to avoid deadlocks
5291                  * maximum packet capture size of 9600 bytes is recommended.
5292                  * Also in this mode, only trace0 can be enabled and running.
5293                  */
5294                 multitrc = 0;
5295                 if (tp->snap_len > 9600 || idx)
5296                         return -EINVAL;
5297         }
5298
5299         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5300             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5301             tp->min_len > TFMINPKTSIZE_M)
5302                 return -EINVAL;
5303
5304         /* stop the tracer we'll be changing */
5305         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5306
5307         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5308         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5309         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5310
5311         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5312                 t4_write_reg(adap, data_reg, tp->data[i]);
5313                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5314         }
5315         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5316                      TFCAPTUREMAX_V(tp->snap_len) |
5317                      TFMINPKTSIZE_V(tp->min_len));
5318         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5319                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5320                      (is_t4(adap->params.chip) ?
5321                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5322                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5323                      T5_TFINVERTMATCH_V(tp->invert)));
5324
5325         return 0;
5326 }
5327
5328 /**
5329  *      t4_get_trace_filter - query one of the tracing filters
5330  *      @adap: the adapter
5331  *      @tp: the current trace filter parameters
5332  *      @idx: which trace filter to query
5333  *      @enabled: non-zero if the filter is enabled
5334  *
5335  *      Returns the current settings of one of the HW tracing filters.
5336  */
5337 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5338                          int *enabled)
5339 {
5340         u32 ctla, ctlb;
5341         int i, ofst = idx * 4;
5342         u32 data_reg, mask_reg;
5343
5344         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5345         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5346
5347         if (is_t4(adap->params.chip)) {
5348                 *enabled = !!(ctla & TFEN_F);
5349                 tp->port =  TFPORT_G(ctla);
5350                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5351         } else {
5352                 *enabled = !!(ctla & T5_TFEN_F);
5353                 tp->port = T5_TFPORT_G(ctla);
5354                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5355         }
5356         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5357         tp->min_len = TFMINPKTSIZE_G(ctlb);
5358         tp->skip_ofst = TFOFFSET_G(ctla);
5359         tp->skip_len = TFLENGTH_G(ctla);
5360
5361         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5362         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5363         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5364
5365         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5366                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5367                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5368         }
5369 }
5370
5371 /**
5372  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5373  *      @adap: the adapter
5374  *      @cnt: where to store the count statistics
5375  *      @cycles: where to store the cycle statistics
5376  *
5377  *      Returns performance statistics from PMTX.
5378  */
5379 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5380 {
5381         int i;
5382         u32 data[2];
5383
5384         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5385                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5386                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5387                 if (is_t4(adap->params.chip)) {
5388                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5389                 } else {
5390                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5391                                          PM_TX_DBG_DATA_A, data, 2,
5392                                          PM_TX_DBG_STAT_MSB_A);
5393                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5394                 }
5395         }
5396 }
5397
5398 /**
5399  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5400  *      @adap: the adapter
5401  *      @cnt: where to store the count statistics
5402  *      @cycles: where to store the cycle statistics
5403  *
5404  *      Returns performance statistics from PMRX.
5405  */
5406 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5407 {
5408         int i;
5409         u32 data[2];
5410
5411         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5412                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5413                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5414                 if (is_t4(adap->params.chip)) {
5415                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5416                 } else {
5417                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5418                                          PM_RX_DBG_DATA_A, data, 2,
5419                                          PM_RX_DBG_STAT_MSB_A);
5420                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5421                 }
5422         }
5423 }
5424
5425 /**
5426  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5427  *      @adap: the adapter
5428  *      @idx: the port index
5429  *
5430  *      Returns a bitmap indicating which MPS buffer groups are associated
5431  *      with the given port.  Bit i is set if buffer group i is used by the
5432  *      port.
5433  */
5434 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5435 {
5436         u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5437
5438         if (n == 0)
5439                 return idx == 0 ? 0xf : 0;
5440         /* In T6 (which is a 2 port card),
5441          * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5442          * For 2 port T4/T5 adapter,
5443          * port 0 is mapped to channel 0 and 1,
5444          * port 1 is mapped to channel 2 and 3.
5445          */
5446         if ((n == 1) &&
5447             (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5448                 return idx < 2 ? (3 << (2 * idx)) : 0;
5449         return 1 << idx;
5450 }
5451
5452 /**
5453  *      t4_get_port_type_description - return Port Type string description
5454  *      @port_type: firmware Port Type enumeration
5455  */
5456 const char *t4_get_port_type_description(enum fw_port_type port_type)
5457 {
5458         static const char *const port_type_description[] = {
5459                 "Fiber_XFI",
5460                 "Fiber_XAUI",
5461                 "BT_SGMII",
5462                 "BT_XFI",
5463                 "BT_XAUI",
5464                 "KX4",
5465                 "CX4",
5466                 "KX",
5467                 "KR",
5468                 "SFP",
5469                 "BP_AP",
5470                 "BP4_AP",
5471                 "QSFP_10G",
5472                 "QSA",
5473                 "QSFP",
5474                 "BP40_BA",
5475                 "KR4_100G",
5476                 "CR4_QSFP",
5477                 "CR_QSFP",
5478                 "CR2_QSFP",
5479                 "SFP28",
5480                 "KR_SFP28",
5481         };
5482
5483         if (port_type < ARRAY_SIZE(port_type_description))
5484                 return port_type_description[port_type];
5485         return "UNKNOWN";
5486 }
5487
5488 /**
5489  *      t4_get_port_stats_offset - collect port stats relative to a previous
5490  *                                 snapshot
5491  *      @adap: The adapter
5492  *      @idx: The port
5493  *      @stats: Current stats to fill
5494  *      @offset: Previous stats snapshot
5495  */
5496 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5497                               struct port_stats *stats,
5498                               struct port_stats *offset)
5499 {
5500         u64 *s, *o;
5501         int i;
5502
5503         t4_get_port_stats(adap, idx, stats);
5504         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5505                         i < (sizeof(struct port_stats) / sizeof(u64));
5506                         i++, s++, o++)
5507                 *s -= *o;
5508 }
5509
5510 /**
5511  *      t4_get_port_stats - collect port statistics
5512  *      @adap: the adapter
5513  *      @idx: the port index
5514  *      @p: the stats structure to fill
5515  *
5516  *      Collect statistics related to the given port from HW.
5517  */
5518 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5519 {
5520         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5521         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5522
5523 #define GET_STAT(name) \
5524         t4_read_reg64(adap, \
5525         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5526         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5527 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5528
5529         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5530         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5531         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5532         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5533         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5534         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5535         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5536         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5537         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5538         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5539         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5540         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5541         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5542         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5543         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5544         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5545         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5546         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5547         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5548         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5549         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
5550         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
5551         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
5552
5553         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5554                 if (stat_ctl & COUNTPAUSESTATTX_F) {
5555                         p->tx_frames -= p->tx_pause;
5556                         p->tx_octets -= p->tx_pause * 64;
5557                 }
5558                 if (stat_ctl & COUNTPAUSEMCTX_F)
5559                         p->tx_mcast_frames -= p->tx_pause;
5560         }
5561         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
5562         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
5563         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
5564         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
5565         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
5566         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
5567         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5568         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
5569         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
5570         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
5571         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
5572         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
5573         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
5574         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
5575         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
5576         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
5577         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5578         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
5579         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
5580         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
5581         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
5582         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
5583         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
5584         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
5585         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
5586         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
5587         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
5588
5589         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5590                 if (stat_ctl & COUNTPAUSESTATRX_F) {
5591                         p->rx_frames -= p->rx_pause;
5592                         p->rx_octets -= p->rx_pause * 64;
5593                 }
5594                 if (stat_ctl & COUNTPAUSEMCRX_F)
5595                         p->rx_mcast_frames -= p->rx_pause;
5596         }
5597
5598         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5599         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5600         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5601         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5602         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5603         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5604         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5605         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5606
5607 #undef GET_STAT
5608 #undef GET_STAT_COM
5609 }
5610
5611 /**
5612  *      t4_get_lb_stats - collect loopback port statistics
5613  *      @adap: the adapter
5614  *      @idx: the loopback port index
5615  *      @p: the stats structure to fill
5616  *
5617  *      Return HW statistics for the given loopback port.
5618  */
5619 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5620 {
5621         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5622
5623 #define GET_STAT(name) \
5624         t4_read_reg64(adap, \
5625         (is_t4(adap->params.chip) ? \
5626         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5627         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5628 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5629
5630         p->octets           = GET_STAT(BYTES);
5631         p->frames           = GET_STAT(FRAMES);
5632         p->bcast_frames     = GET_STAT(BCAST);
5633         p->mcast_frames     = GET_STAT(MCAST);
5634         p->ucast_frames     = GET_STAT(UCAST);
5635         p->error_frames     = GET_STAT(ERROR);
5636
5637         p->frames_64        = GET_STAT(64B);
5638         p->frames_65_127    = GET_STAT(65B_127B);
5639         p->frames_128_255   = GET_STAT(128B_255B);
5640         p->frames_256_511   = GET_STAT(256B_511B);
5641         p->frames_512_1023  = GET_STAT(512B_1023B);
5642         p->frames_1024_1518 = GET_STAT(1024B_1518B);
5643         p->frames_1519_max  = GET_STAT(1519B_MAX);
5644         p->drop             = GET_STAT(DROP_FRAMES);
5645
5646         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5647         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5648         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5649         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5650         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5651         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5652         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5653         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5654
5655 #undef GET_STAT
5656 #undef GET_STAT_COM
5657 }
5658
5659 /*     t4_mk_filtdelwr - create a delete filter WR
5660  *     @ftid: the filter ID
5661  *     @wr: the filter work request to populate
5662  *     @qid: ingress queue to receive the delete notification
5663  *
5664  *     Creates a filter work request to delete the supplied filter.  If @qid is
5665  *     negative the delete notification is suppressed.
5666  */
5667 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5668 {
5669         memset(wr, 0, sizeof(*wr));
5670         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5671         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5672         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5673                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
5674         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5675         if (qid >= 0)
5676                 wr->rx_chan_rx_rpl_iq =
5677                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5678 }
5679
5680 #define INIT_CMD(var, cmd, rd_wr) do { \
5681         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5682                                         FW_CMD_REQUEST_F | \
5683                                         FW_CMD_##rd_wr##_F); \
5684         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5685 } while (0)
5686
5687 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5688                           u32 addr, u32 val)
5689 {
5690         u32 ldst_addrspace;
5691         struct fw_ldst_cmd c;
5692
5693         memset(&c, 0, sizeof(c));
5694         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5695         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5696                                         FW_CMD_REQUEST_F |
5697                                         FW_CMD_WRITE_F |
5698                                         ldst_addrspace);
5699         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5700         c.u.addrval.addr = cpu_to_be32(addr);
5701         c.u.addrval.val = cpu_to_be32(val);
5702
5703         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5704 }
5705
5706 /**
5707  *      t4_mdio_rd - read a PHY register through MDIO
5708  *      @adap: the adapter
5709  *      @mbox: mailbox to use for the FW command
5710  *      @phy_addr: the PHY address
5711  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5712  *      @reg: the register to read
5713  *      @valp: where to store the value
5714  *
5715  *      Issues a FW command through the given mailbox to read a PHY register.
5716  */
5717 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5718                unsigned int mmd, unsigned int reg, u16 *valp)
5719 {
5720         int ret;
5721         u32 ldst_addrspace;
5722         struct fw_ldst_cmd c;
5723
5724         memset(&c, 0, sizeof(c));
5725         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5726         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5727                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5728                                         ldst_addrspace);
5729         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5730         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5731                                          FW_LDST_CMD_MMD_V(mmd));
5732         c.u.mdio.raddr = cpu_to_be16(reg);
5733
5734         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5735         if (ret == 0)
5736                 *valp = be16_to_cpu(c.u.mdio.rval);
5737         return ret;
5738 }
5739
5740 /**
5741  *      t4_mdio_wr - write a PHY register through MDIO
5742  *      @adap: the adapter
5743  *      @mbox: mailbox to use for the FW command
5744  *      @phy_addr: the PHY address
5745  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5746  *      @reg: the register to write
5747  *      @valp: value to write
5748  *
5749  *      Issues a FW command through the given mailbox to write a PHY register.
5750  */
5751 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5752                unsigned int mmd, unsigned int reg, u16 val)
5753 {
5754         u32 ldst_addrspace;
5755         struct fw_ldst_cmd c;
5756
5757         memset(&c, 0, sizeof(c));
5758         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5759         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5760                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5761                                         ldst_addrspace);
5762         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5763         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5764                                          FW_LDST_CMD_MMD_V(mmd));
5765         c.u.mdio.raddr = cpu_to_be16(reg);
5766         c.u.mdio.rval = cpu_to_be16(val);
5767
5768         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5769 }
5770
5771 /**
5772  *      t4_sge_decode_idma_state - decode the idma state
5773  *      @adap: the adapter
5774  *      @state: the state idma is stuck in
5775  */
5776 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5777 {
5778         static const char * const t4_decode[] = {
5779                 "IDMA_IDLE",
5780                 "IDMA_PUSH_MORE_CPL_FIFO",
5781                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5782                 "Not used",
5783                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5784                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5785                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5786                 "IDMA_SEND_FIFO_TO_IMSG",
5787                 "IDMA_FL_REQ_DATA_FL_PREP",
5788                 "IDMA_FL_REQ_DATA_FL",
5789                 "IDMA_FL_DROP",
5790                 "IDMA_FL_H_REQ_HEADER_FL",
5791                 "IDMA_FL_H_SEND_PCIEHDR",
5792                 "IDMA_FL_H_PUSH_CPL_FIFO",
5793                 "IDMA_FL_H_SEND_CPL",
5794                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5795                 "IDMA_FL_H_SEND_IP_HDR",
5796                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5797                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5798                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5799                 "IDMA_FL_D_SEND_PCIEHDR",
5800                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5801                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5802                 "IDMA_FL_SEND_PCIEHDR",
5803                 "IDMA_FL_PUSH_CPL_FIFO",
5804                 "IDMA_FL_SEND_CPL",
5805                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5806                 "IDMA_FL_SEND_PAYLOAD",
5807                 "IDMA_FL_REQ_NEXT_DATA_FL",
5808                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5809                 "IDMA_FL_SEND_PADDING",
5810                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5811                 "IDMA_FL_SEND_FIFO_TO_IMSG",
5812                 "IDMA_FL_REQ_DATAFL_DONE",
5813                 "IDMA_FL_REQ_HEADERFL_DONE",
5814         };
5815         static const char * const t5_decode[] = {
5816                 "IDMA_IDLE",
5817                 "IDMA_ALMOST_IDLE",
5818                 "IDMA_PUSH_MORE_CPL_FIFO",
5819                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5820                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5821                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5822                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5823                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5824                 "IDMA_SEND_FIFO_TO_IMSG",
5825                 "IDMA_FL_REQ_DATA_FL",
5826                 "IDMA_FL_DROP",
5827                 "IDMA_FL_DROP_SEND_INC",
5828                 "IDMA_FL_H_REQ_HEADER_FL",
5829                 "IDMA_FL_H_SEND_PCIEHDR",
5830                 "IDMA_FL_H_PUSH_CPL_FIFO",
5831                 "IDMA_FL_H_SEND_CPL",
5832                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5833                 "IDMA_FL_H_SEND_IP_HDR",
5834                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5835                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5836                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5837                 "IDMA_FL_D_SEND_PCIEHDR",
5838                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5839                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5840                 "IDMA_FL_SEND_PCIEHDR",
5841                 "IDMA_FL_PUSH_CPL_FIFO",
5842                 "IDMA_FL_SEND_CPL",
5843                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5844                 "IDMA_FL_SEND_PAYLOAD",
5845                 "IDMA_FL_REQ_NEXT_DATA_FL",
5846                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5847                 "IDMA_FL_SEND_PADDING",
5848                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5849         };
5850         static const char * const t6_decode[] = {
5851                 "IDMA_IDLE",
5852                 "IDMA_PUSH_MORE_CPL_FIFO",
5853                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5854                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5855                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5856                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5857                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5858                 "IDMA_FL_REQ_DATA_FL",
5859                 "IDMA_FL_DROP",
5860                 "IDMA_FL_DROP_SEND_INC",
5861                 "IDMA_FL_H_REQ_HEADER_FL",
5862                 "IDMA_FL_H_SEND_PCIEHDR",
5863                 "IDMA_FL_H_PUSH_CPL_FIFO",
5864                 "IDMA_FL_H_SEND_CPL",
5865                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5866                 "IDMA_FL_H_SEND_IP_HDR",
5867                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5868                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5869                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5870                 "IDMA_FL_D_SEND_PCIEHDR",
5871                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5872                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5873                 "IDMA_FL_SEND_PCIEHDR",
5874                 "IDMA_FL_PUSH_CPL_FIFO",
5875                 "IDMA_FL_SEND_CPL",
5876                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5877                 "IDMA_FL_SEND_PAYLOAD",
5878                 "IDMA_FL_REQ_NEXT_DATA_FL",
5879                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5880                 "IDMA_FL_SEND_PADDING",
5881                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5882         };
5883         static const u32 sge_regs[] = {
5884                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5885                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5886                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5887         };
5888         const char **sge_idma_decode;
5889         int sge_idma_decode_nstates;
5890         int i;
5891         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5892
5893         /* Select the right set of decode strings to dump depending on the
5894          * adapter chip type.
5895          */
5896         switch (chip_version) {
5897         case CHELSIO_T4:
5898                 sge_idma_decode = (const char **)t4_decode;
5899                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5900                 break;
5901
5902         case CHELSIO_T5:
5903                 sge_idma_decode = (const char **)t5_decode;
5904                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5905                 break;
5906
5907         case CHELSIO_T6:
5908                 sge_idma_decode = (const char **)t6_decode;
5909                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5910                 break;
5911
5912         default:
5913                 dev_err(adapter->pdev_dev,
5914                         "Unsupported chip version %d\n", chip_version);
5915                 return;
5916         }
5917
5918         if (is_t4(adapter->params.chip)) {
5919                 sge_idma_decode = (const char **)t4_decode;
5920                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5921         } else {
5922                 sge_idma_decode = (const char **)t5_decode;
5923                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5924         }
5925
5926         if (state < sge_idma_decode_nstates)
5927                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5928         else
5929                 CH_WARN(adapter, "idma state %d unknown\n", state);
5930
5931         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5932                 CH_WARN(adapter, "SGE register %#x value %#x\n",
5933                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5934 }
5935
5936 /**
5937  *      t4_sge_ctxt_flush - flush the SGE context cache
5938  *      @adap: the adapter
5939  *      @mbox: mailbox to use for the FW command
5940  *
5941  *      Issues a FW command through the given mailbox to flush the
5942  *      SGE context cache.
5943  */
5944 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5945 {
5946         int ret;
5947         u32 ldst_addrspace;
5948         struct fw_ldst_cmd c;
5949
5950         memset(&c, 0, sizeof(c));
5951         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5952         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5953                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
5954                                         ldst_addrspace);
5955         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5956         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5957
5958         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5959         return ret;
5960 }
5961
5962 /**
5963  *      t4_fw_hello - establish communication with FW
5964  *      @adap: the adapter
5965  *      @mbox: mailbox to use for the FW command
5966  *      @evt_mbox: mailbox to receive async FW events
5967  *      @master: specifies the caller's willingness to be the device master
5968  *      @state: returns the current device state (if non-NULL)
5969  *
5970  *      Issues a command to establish communication with FW.  Returns either
5971  *      an error (negative integer) or the mailbox of the Master PF.
5972  */
5973 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5974                 enum dev_master master, enum dev_state *state)
5975 {
5976         int ret;
5977         struct fw_hello_cmd c;
5978         u32 v;
5979         unsigned int master_mbox;
5980         int retries = FW_CMD_HELLO_RETRIES;
5981
5982 retry:
5983         memset(&c, 0, sizeof(c));
5984         INIT_CMD(c, HELLO, WRITE);
5985         c.err_to_clearinit = cpu_to_be32(
5986                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5987                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5988                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5989                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
5990                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5991                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5992                 FW_HELLO_CMD_CLEARINIT_F);
5993
5994         /*
5995          * Issue the HELLO command to the firmware.  If it's not successful
5996          * but indicates that we got a "busy" or "timeout" condition, retry
5997          * the HELLO until we exhaust our retry limit.  If we do exceed our
5998          * retry limit, check to see if the firmware left us any error
5999          * information and report that if so.
6000          */
6001         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6002         if (ret < 0) {
6003                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6004                         goto retry;
6005                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6006                         t4_report_fw_error(adap);
6007                 return ret;
6008         }
6009
6010         v = be32_to_cpu(c.err_to_clearinit);
6011         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6012         if (state) {
6013                 if (v & FW_HELLO_CMD_ERR_F)
6014                         *state = DEV_STATE_ERR;
6015                 else if (v & FW_HELLO_CMD_INIT_F)
6016                         *state = DEV_STATE_INIT;
6017                 else
6018                         *state = DEV_STATE_UNINIT;
6019         }
6020
6021         /*
6022          * If we're not the Master PF then we need to wait around for the
6023          * Master PF Driver to finish setting up the adapter.
6024          *
6025          * Note that we also do this wait if we're a non-Master-capable PF and
6026          * there is no current Master PF; a Master PF may show up momentarily
6027          * and we wouldn't want to fail pointlessly.  (This can happen when an
6028          * OS loads lots of different drivers rapidly at the same time).  In
6029          * this case, the Master PF returned by the firmware will be
6030          * PCIE_FW_MASTER_M so the test below will work ...
6031          */
6032         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6033             master_mbox != mbox) {
6034                 int waiting = FW_CMD_HELLO_TIMEOUT;
6035
6036                 /*
6037                  * Wait for the firmware to either indicate an error or
6038                  * initialized state.  If we see either of these we bail out
6039                  * and report the issue to the caller.  If we exhaust the
6040                  * "hello timeout" and we haven't exhausted our retries, try
6041                  * again.  Otherwise bail with a timeout error.
6042                  */
6043                 for (;;) {
6044                         u32 pcie_fw;
6045
6046                         msleep(50);
6047                         waiting -= 50;
6048
6049                         /*
6050                          * If neither Error nor Initialialized are indicated
6051                          * by the firmware keep waiting till we exaust our
6052                          * timeout ... and then retry if we haven't exhausted
6053                          * our retries ...
6054                          */
6055                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6056                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6057                                 if (waiting <= 0) {
6058                                         if (retries-- > 0)
6059                                                 goto retry;
6060
6061                                         return -ETIMEDOUT;
6062                                 }
6063                                 continue;
6064                         }
6065
6066                         /*
6067                          * We either have an Error or Initialized condition
6068                          * report errors preferentially.
6069                          */
6070                         if (state) {
6071                                 if (pcie_fw & PCIE_FW_ERR_F)
6072                                         *state = DEV_STATE_ERR;
6073                                 else if (pcie_fw & PCIE_FW_INIT_F)
6074                                         *state = DEV_STATE_INIT;
6075                         }
6076
6077                         /*
6078                          * If we arrived before a Master PF was selected and
6079                          * there's not a valid Master PF, grab its identity
6080                          * for our caller.
6081                          */
6082                         if (master_mbox == PCIE_FW_MASTER_M &&
6083                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6084                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6085                         break;
6086                 }
6087         }
6088
6089         return master_mbox;
6090 }
6091
6092 /**
6093  *      t4_fw_bye - end communication with FW
6094  *      @adap: the adapter
6095  *      @mbox: mailbox to use for the FW command
6096  *
6097  *      Issues a command to terminate communication with FW.
6098  */
6099 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6100 {
6101         struct fw_bye_cmd c;
6102
6103         memset(&c, 0, sizeof(c));
6104         INIT_CMD(c, BYE, WRITE);
6105         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6106 }
6107
6108 /**
6109  *      t4_init_cmd - ask FW to initialize the device
6110  *      @adap: the adapter
6111  *      @mbox: mailbox to use for the FW command
6112  *
6113  *      Issues a command to FW to partially initialize the device.  This
6114  *      performs initialization that generally doesn't depend on user input.
6115  */
6116 int t4_early_init(struct adapter *adap, unsigned int mbox)
6117 {
6118         struct fw_initialize_cmd c;
6119
6120         memset(&c, 0, sizeof(c));
6121         INIT_CMD(c, INITIALIZE, WRITE);
6122         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6123 }
6124
6125 /**
6126  *      t4_fw_reset - issue a reset to FW
6127  *      @adap: the adapter
6128  *      @mbox: mailbox to use for the FW command
6129  *      @reset: specifies the type of reset to perform
6130  *
6131  *      Issues a reset command of the specified type to FW.
6132  */
6133 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6134 {
6135         struct fw_reset_cmd c;
6136
6137         memset(&c, 0, sizeof(c));
6138         INIT_CMD(c, RESET, WRITE);
6139         c.val = cpu_to_be32(reset);
6140         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6141 }
6142
6143 /**
6144  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6145  *      @adap: the adapter
6146  *      @mbox: mailbox to use for the FW RESET command (if desired)
6147  *      @force: force uP into RESET even if FW RESET command fails
6148  *
6149  *      Issues a RESET command to firmware (if desired) with a HALT indication
6150  *      and then puts the microprocessor into RESET state.  The RESET command
6151  *      will only be issued if a legitimate mailbox is provided (mbox <=
6152  *      PCIE_FW_MASTER_M).
6153  *
6154  *      This is generally used in order for the host to safely manipulate the
6155  *      adapter without fear of conflicting with whatever the firmware might
6156  *      be doing.  The only way out of this state is to RESTART the firmware
6157  *      ...
6158  */
6159 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6160 {
6161         int ret = 0;
6162
6163         /*
6164          * If a legitimate mailbox is provided, issue a RESET command
6165          * with a HALT indication.
6166          */
6167         if (mbox <= PCIE_FW_MASTER_M) {
6168                 struct fw_reset_cmd c;
6169
6170                 memset(&c, 0, sizeof(c));
6171                 INIT_CMD(c, RESET, WRITE);
6172                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6173                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6174                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6175         }
6176
6177         /*
6178          * Normally we won't complete the operation if the firmware RESET
6179          * command fails but if our caller insists we'll go ahead and put the
6180          * uP into RESET.  This can be useful if the firmware is hung or even
6181          * missing ...  We'll have to take the risk of putting the uP into
6182          * RESET without the cooperation of firmware in that case.
6183          *
6184          * We also force the firmware's HALT flag to be on in case we bypassed
6185          * the firmware RESET command above or we're dealing with old firmware
6186          * which doesn't have the HALT capability.  This will serve as a flag
6187          * for the incoming firmware to know that it's coming out of a HALT
6188          * rather than a RESET ... if it's new enough to understand that ...
6189          */
6190         if (ret == 0 || force) {
6191                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6192                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6193                                  PCIE_FW_HALT_F);
6194         }
6195
6196         /*
6197          * And we always return the result of the firmware RESET command
6198          * even when we force the uP into RESET ...
6199          */
6200         return ret;
6201 }
6202
6203 /**
6204  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6205  *      @adap: the adapter
6206  *      @reset: if we want to do a RESET to restart things
6207  *
6208  *      Restart firmware previously halted by t4_fw_halt().  On successful
6209  *      return the previous PF Master remains as the new PF Master and there
6210  *      is no need to issue a new HELLO command, etc.
6211  *
6212  *      We do this in two ways:
6213  *
6214  *       1. If we're dealing with newer firmware we'll simply want to take
6215  *          the chip's microprocessor out of RESET.  This will cause the
6216  *          firmware to start up from its start vector.  And then we'll loop
6217  *          until the firmware indicates it's started again (PCIE_FW.HALT
6218  *          reset to 0) or we timeout.
6219  *
6220  *       2. If we're dealing with older firmware then we'll need to RESET
6221  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6222  *          flag and automatically RESET itself on startup.
6223  */
6224 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6225 {
6226         if (reset) {
6227                 /*
6228                  * Since we're directing the RESET instead of the firmware
6229                  * doing it automatically, we need to clear the PCIE_FW.HALT
6230                  * bit.
6231                  */
6232                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6233
6234                 /*
6235                  * If we've been given a valid mailbox, first try to get the
6236                  * firmware to do the RESET.  If that works, great and we can
6237                  * return success.  Otherwise, if we haven't been given a
6238                  * valid mailbox or the RESET command failed, fall back to
6239                  * hitting the chip with a hammer.
6240                  */
6241                 if (mbox <= PCIE_FW_MASTER_M) {
6242                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6243                         msleep(100);
6244                         if (t4_fw_reset(adap, mbox,
6245                                         PIORST_F | PIORSTMODE_F) == 0)
6246                                 return 0;
6247                 }
6248
6249                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6250                 msleep(2000);
6251         } else {
6252                 int ms;
6253
6254                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6255                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6256                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6257                                 return 0;
6258                         msleep(100);
6259                         ms += 100;
6260                 }
6261                 return -ETIMEDOUT;
6262         }
6263         return 0;
6264 }
6265
6266 /**
6267  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6268  *      @adap: the adapter
6269  *      @mbox: mailbox to use for the FW RESET command (if desired)
6270  *      @fw_data: the firmware image to write
6271  *      @size: image size
6272  *      @force: force upgrade even if firmware doesn't cooperate
6273  *
6274  *      Perform all of the steps necessary for upgrading an adapter's
6275  *      firmware image.  Normally this requires the cooperation of the
6276  *      existing firmware in order to halt all existing activities
6277  *      but if an invalid mailbox token is passed in we skip that step
6278  *      (though we'll still put the adapter microprocessor into RESET in
6279  *      that case).
6280  *
6281  *      On successful return the new firmware will have been loaded and
6282  *      the adapter will have been fully RESET losing all previous setup
6283  *      state.  On unsuccessful return the adapter may be completely hosed ...
6284  *      positive errno indicates that the adapter is ~probably~ intact, a
6285  *      negative errno indicates that things are looking bad ...
6286  */
6287 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6288                   const u8 *fw_data, unsigned int size, int force)
6289 {
6290         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6291         int reset, ret;
6292
6293         if (!t4_fw_matches_chip(adap, fw_hdr))
6294                 return -EINVAL;
6295
6296         ret = t4_fw_halt(adap, mbox, force);
6297         if (ret < 0 && !force)
6298                 return ret;
6299
6300         ret = t4_load_fw(adap, fw_data, size);
6301         if (ret < 0)
6302                 return ret;
6303
6304         /*
6305          * Older versions of the firmware don't understand the new
6306          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6307          * restart.  So for newly loaded older firmware we'll have to do the
6308          * RESET for it so it starts up on a clean slate.  We can tell if
6309          * the newly loaded firmware will handle this right by checking
6310          * its header flags to see if it advertises the capability.
6311          */
6312         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6313         return t4_fw_restart(adap, mbox, reset);
6314 }
6315
6316 /**
6317  *      t4_fl_pkt_align - return the fl packet alignment
6318  *      @adap: the adapter
6319  *
6320  *      T4 has a single field to specify the packing and padding boundary.
6321  *      T5 onwards has separate fields for this and hence the alignment for
6322  *      next packet offset is maximum of these two.
6323  *
6324  */
6325 int t4_fl_pkt_align(struct adapter *adap)
6326 {
6327         u32 sge_control, sge_control2;
6328         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6329
6330         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6331
6332         /* T4 uses a single control field to specify both the PCIe Padding and
6333          * Packing Boundary.  T5 introduced the ability to specify these
6334          * separately.  The actual Ingress Packet Data alignment boundary
6335          * within Packed Buffer Mode is the maximum of these two
6336          * specifications.  (Note that it makes no real practical sense to
6337          * have the Pading Boudary be larger than the Packing Boundary but you
6338          * could set the chip up that way and, in fact, legacy T4 code would
6339          * end doing this because it would initialize the Padding Boundary and
6340          * leave the Packing Boundary initialized to 0 (16 bytes).)
6341          * Padding Boundary values in T6 starts from 8B,
6342          * where as it is 32B for T4 and T5.
6343          */
6344         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6345                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6346         else
6347                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6348
6349         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6350
6351         fl_align = ingpadboundary;
6352         if (!is_t4(adap->params.chip)) {
6353                 /* T5 has a weird interpretation of one of the PCIe Packing
6354                  * Boundary values.  No idea why ...
6355                  */
6356                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6357                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6358                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6359                         ingpackboundary = 16;
6360                 else
6361                         ingpackboundary = 1 << (ingpackboundary +
6362                                                 INGPACKBOUNDARY_SHIFT_X);
6363
6364                 fl_align = max(ingpadboundary, ingpackboundary);
6365         }
6366         return fl_align;
6367 }
6368
6369 /**
6370  *      t4_fixup_host_params - fix up host-dependent parameters
6371  *      @adap: the adapter
6372  *      @page_size: the host's Base Page Size
6373  *      @cache_line_size: the host's Cache Line Size
6374  *
6375  *      Various registers in T4 contain values which are dependent on the
6376  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6377  *      those registers with the appropriate values as passed in ...
6378  */
6379 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6380                          unsigned int cache_line_size)
6381 {
6382         unsigned int page_shift = fls(page_size) - 1;
6383         unsigned int sge_hps = page_shift - 10;
6384         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6385         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6386         unsigned int fl_align_log = fls(fl_align) - 1;
6387
6388         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6389                      HOSTPAGESIZEPF0_V(sge_hps) |
6390                      HOSTPAGESIZEPF1_V(sge_hps) |
6391                      HOSTPAGESIZEPF2_V(sge_hps) |
6392                      HOSTPAGESIZEPF3_V(sge_hps) |
6393                      HOSTPAGESIZEPF4_V(sge_hps) |
6394                      HOSTPAGESIZEPF5_V(sge_hps) |
6395                      HOSTPAGESIZEPF6_V(sge_hps) |
6396                      HOSTPAGESIZEPF7_V(sge_hps));
6397
6398         if (is_t4(adap->params.chip)) {
6399                 t4_set_reg_field(adap, SGE_CONTROL_A,
6400                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6401                                  EGRSTATUSPAGESIZE_F,
6402                                  INGPADBOUNDARY_V(fl_align_log -
6403                                                   INGPADBOUNDARY_SHIFT_X) |
6404                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6405         } else {
6406                 unsigned int pack_align;
6407                 unsigned int ingpad, ingpack;
6408                 unsigned int pcie_cap;
6409
6410                 /* T5 introduced the separation of the Free List Padding and
6411                  * Packing Boundaries.  Thus, we can select a smaller Padding
6412                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6413                  * Bandwidth, and use a Packing Boundary which is large enough
6414                  * to avoid false sharing between CPUs, etc.
6415                  *
6416                  * For the PCI Link, the smaller the Padding Boundary the
6417                  * better.  For the Memory Controller, a smaller Padding
6418                  * Boundary is better until we cross under the Memory Line
6419                  * Size (the minimum unit of transfer to/from Memory).  If we
6420                  * have a Padding Boundary which is smaller than the Memory
6421                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6422                  * Memory Controller which is never good.
6423                  */
6424
6425                 /* We want the Packing Boundary to be based on the Cache Line
6426                  * Size in order to help avoid False Sharing performance
6427                  * issues between CPUs, etc.  We also want the Packing
6428                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
6429                  * get best performance when the Packing Boundary is a
6430                  * multiple of the Maximum Payload Size.
6431                  */
6432                 pack_align = fl_align;
6433                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6434                 if (pcie_cap) {
6435                         unsigned int mps, mps_log;
6436                         u16 devctl;
6437
6438                         /* The PCIe Device Control Maximum Payload Size field
6439                          * [bits 7:5] encodes sizes as powers of 2 starting at
6440                          * 128 bytes.
6441                          */
6442                         pci_read_config_word(adap->pdev,
6443                                              pcie_cap + PCI_EXP_DEVCTL,
6444                                              &devctl);
6445                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6446                         mps = 1 << mps_log;
6447                         if (mps > pack_align)
6448                                 pack_align = mps;
6449                 }
6450
6451                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6452                  * value for the Packing Boundary.  This corresponds to 16
6453                  * bytes instead of the expected 32 bytes.  So if we want 32
6454                  * bytes, the best we can really do is 64 bytes ...
6455                  */
6456                 if (pack_align <= 16) {
6457                         ingpack = INGPACKBOUNDARY_16B_X;
6458                         fl_align = 16;
6459                 } else if (pack_align == 32) {
6460                         ingpack = INGPACKBOUNDARY_64B_X;
6461                         fl_align = 64;
6462                 } else {
6463                         unsigned int pack_align_log = fls(pack_align) - 1;
6464
6465                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6466                         fl_align = pack_align;
6467                 }
6468
6469                 /* Use the smallest Ingress Padding which isn't smaller than
6470                  * the Memory Controller Read/Write Size.  We'll take that as
6471                  * being 8 bytes since we don't know of any system with a
6472                  * wider Memory Controller Bus Width.
6473                  */
6474                 if (is_t5(adap->params.chip))
6475                         ingpad = INGPADBOUNDARY_32B_X;
6476                 else
6477                         ingpad = T6_INGPADBOUNDARY_8B_X;
6478
6479                 t4_set_reg_field(adap, SGE_CONTROL_A,
6480                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6481                                  EGRSTATUSPAGESIZE_F,
6482                                  INGPADBOUNDARY_V(ingpad) |
6483                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6484                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6485                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6486                                  INGPACKBOUNDARY_V(ingpack));
6487         }
6488         /*
6489          * Adjust various SGE Free List Host Buffer Sizes.
6490          *
6491          * This is something of a crock since we're using fixed indices into
6492          * the array which are also known by the sge.c code and the T4
6493          * Firmware Configuration File.  We need to come up with a much better
6494          * approach to managing this array.  For now, the first four entries
6495          * are:
6496          *
6497          *   0: Host Page Size
6498          *   1: 64KB
6499          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6500          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6501          *
6502          * For the single-MTU buffers in unpacked mode we need to include
6503          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6504          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6505          * Padding boundary.  All of these are accommodated in the Factory
6506          * Default Firmware Configuration File but we need to adjust it for
6507          * this host's cache line size.
6508          */
6509         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6510         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6511                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6512                      & ~(fl_align-1));
6513         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6514                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6515                      & ~(fl_align-1));
6516
6517         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6518
6519         return 0;
6520 }
6521
6522 /**
6523  *      t4_fw_initialize - ask FW to initialize the device
6524  *      @adap: the adapter
6525  *      @mbox: mailbox to use for the FW command
6526  *
6527  *      Issues a command to FW to partially initialize the device.  This
6528  *      performs initialization that generally doesn't depend on user input.
6529  */
6530 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6531 {
6532         struct fw_initialize_cmd c;
6533
6534         memset(&c, 0, sizeof(c));
6535         INIT_CMD(c, INITIALIZE, WRITE);
6536         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6537 }
6538
6539 /**
6540  *      t4_query_params_rw - query FW or device parameters
6541  *      @adap: the adapter
6542  *      @mbox: mailbox to use for the FW command
6543  *      @pf: the PF
6544  *      @vf: the VF
6545  *      @nparams: the number of parameters
6546  *      @params: the parameter names
6547  *      @val: the parameter values
6548  *      @rw: Write and read flag
6549  *
6550  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
6551  *      queried at once.
6552  */
6553 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6554                        unsigned int vf, unsigned int nparams, const u32 *params,
6555                        u32 *val, int rw)
6556 {
6557         int i, ret;
6558         struct fw_params_cmd c;
6559         __be32 *p = &c.param[0].mnem;
6560
6561         if (nparams > 7)
6562                 return -EINVAL;
6563
6564         memset(&c, 0, sizeof(c));
6565         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6566                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
6567                                   FW_PARAMS_CMD_PFN_V(pf) |
6568                                   FW_PARAMS_CMD_VFN_V(vf));
6569         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6570
6571         for (i = 0; i < nparams; i++) {
6572                 *p++ = cpu_to_be32(*params++);
6573                 if (rw)
6574                         *p = cpu_to_be32(*(val + i));
6575                 p++;
6576         }
6577
6578         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6579         if (ret == 0)
6580                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6581                         *val++ = be32_to_cpu(*p);
6582         return ret;
6583 }
6584
6585 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6586                     unsigned int vf, unsigned int nparams, const u32 *params,
6587                     u32 *val)
6588 {
6589         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6590 }
6591
6592 /**
6593  *      t4_set_params_timeout - sets FW or device parameters
6594  *      @adap: the adapter
6595  *      @mbox: mailbox to use for the FW command
6596  *      @pf: the PF
6597  *      @vf: the VF
6598  *      @nparams: the number of parameters
6599  *      @params: the parameter names
6600  *      @val: the parameter values
6601  *      @timeout: the timeout time
6602  *
6603  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6604  *      specified at once.
6605  */
6606 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6607                           unsigned int pf, unsigned int vf,
6608                           unsigned int nparams, const u32 *params,
6609                           const u32 *val, int timeout)
6610 {
6611         struct fw_params_cmd c;
6612         __be32 *p = &c.param[0].mnem;
6613
6614         if (nparams > 7)
6615                 return -EINVAL;
6616
6617         memset(&c, 0, sizeof(c));
6618         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6619                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6620                                   FW_PARAMS_CMD_PFN_V(pf) |
6621                                   FW_PARAMS_CMD_VFN_V(vf));
6622         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6623
6624         while (nparams--) {
6625                 *p++ = cpu_to_be32(*params++);
6626                 *p++ = cpu_to_be32(*val++);
6627         }
6628
6629         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6630 }
6631
6632 /**
6633  *      t4_set_params - sets FW or device parameters
6634  *      @adap: the adapter
6635  *      @mbox: mailbox to use for the FW command
6636  *      @pf: the PF
6637  *      @vf: the VF
6638  *      @nparams: the number of parameters
6639  *      @params: the parameter names
6640  *      @val: the parameter values
6641  *
6642  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6643  *      specified at once.
6644  */
6645 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6646                   unsigned int vf, unsigned int nparams, const u32 *params,
6647                   const u32 *val)
6648 {
6649         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6650                                      FW_CMD_MAX_TIMEOUT);
6651 }
6652
6653 /**
6654  *      t4_cfg_pfvf - configure PF/VF resource limits
6655  *      @adap: the adapter
6656  *      @mbox: mailbox to use for the FW command
6657  *      @pf: the PF being configured
6658  *      @vf: the VF being configured
6659  *      @txq: the max number of egress queues
6660  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
6661  *      @rxqi: the max number of interrupt-capable ingress queues
6662  *      @rxq: the max number of interruptless ingress queues
6663  *      @tc: the PCI traffic class
6664  *      @vi: the max number of virtual interfaces
6665  *      @cmask: the channel access rights mask for the PF/VF
6666  *      @pmask: the port access rights mask for the PF/VF
6667  *      @nexact: the maximum number of exact MPS filters
6668  *      @rcaps: read capabilities
6669  *      @wxcaps: write/execute capabilities
6670  *
6671  *      Configures resource limits and capabilities for a physical or virtual
6672  *      function.
6673  */
6674 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6675                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6676                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6677                 unsigned int vi, unsigned int cmask, unsigned int pmask,
6678                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6679 {
6680         struct fw_pfvf_cmd c;
6681
6682         memset(&c, 0, sizeof(c));
6683         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6684                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6685                                   FW_PFVF_CMD_VFN_V(vf));
6686         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6687         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6688                                      FW_PFVF_CMD_NIQ_V(rxq));
6689         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6690                                     FW_PFVF_CMD_PMASK_V(pmask) |
6691                                     FW_PFVF_CMD_NEQ_V(txq));
6692         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6693                                       FW_PFVF_CMD_NVI_V(vi) |
6694                                       FW_PFVF_CMD_NEXACTF_V(nexact));
6695         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6696                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6697                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6698         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6699 }
6700
6701 /**
6702  *      t4_alloc_vi - allocate a virtual interface
6703  *      @adap: the adapter
6704  *      @mbox: mailbox to use for the FW command
6705  *      @port: physical port associated with the VI
6706  *      @pf: the PF owning the VI
6707  *      @vf: the VF owning the VI
6708  *      @nmac: number of MAC addresses needed (1 to 5)
6709  *      @mac: the MAC addresses of the VI
6710  *      @rss_size: size of RSS table slice associated with this VI
6711  *
6712  *      Allocates a virtual interface for the given physical port.  If @mac is
6713  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
6714  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
6715  *      stored consecutively so the space needed is @nmac * 6 bytes.
6716  *      Returns a negative error number or the non-negative VI id.
6717  */
6718 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6719                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6720                 unsigned int *rss_size)
6721 {
6722         int ret;
6723         struct fw_vi_cmd c;
6724
6725         memset(&c, 0, sizeof(c));
6726         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6727                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6728                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6729         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6730         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6731         c.nmac = nmac - 1;
6732
6733         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6734         if (ret)
6735                 return ret;
6736
6737         if (mac) {
6738                 memcpy(mac, c.mac, sizeof(c.mac));
6739                 switch (nmac) {
6740                 case 5:
6741                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6742                 case 4:
6743                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6744                 case 3:
6745                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6746                 case 2:
6747                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6748                 }
6749         }
6750         if (rss_size)
6751                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6752         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6753 }
6754
6755 /**
6756  *      t4_free_vi - free a virtual interface
6757  *      @adap: the adapter
6758  *      @mbox: mailbox to use for the FW command
6759  *      @pf: the PF owning the VI
6760  *      @vf: the VF owning the VI
6761  *      @viid: virtual interface identifiler
6762  *
6763  *      Free a previously allocated virtual interface.
6764  */
6765 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6766                unsigned int vf, unsigned int viid)
6767 {
6768         struct fw_vi_cmd c;
6769
6770         memset(&c, 0, sizeof(c));
6771         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6772                                   FW_CMD_REQUEST_F |
6773                                   FW_CMD_EXEC_F |
6774                                   FW_VI_CMD_PFN_V(pf) |
6775                                   FW_VI_CMD_VFN_V(vf));
6776         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6777         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6778
6779         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6780 }
6781
6782 /**
6783  *      t4_set_rxmode - set Rx properties of a virtual interface
6784  *      @adap: the adapter
6785  *      @mbox: mailbox to use for the FW command
6786  *      @viid: the VI id
6787  *      @mtu: the new MTU or -1
6788  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6789  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6790  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6791  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6792  *      @sleep_ok: if true we may sleep while awaiting command completion
6793  *
6794  *      Sets Rx properties of a virtual interface.
6795  */
6796 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6797                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
6798                   bool sleep_ok)
6799 {
6800         struct fw_vi_rxmode_cmd c;
6801
6802         /* convert to FW values */
6803         if (mtu < 0)
6804                 mtu = FW_RXMODE_MTU_NO_CHG;
6805         if (promisc < 0)
6806                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6807         if (all_multi < 0)
6808                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6809         if (bcast < 0)
6810                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6811         if (vlanex < 0)
6812                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6813
6814         memset(&c, 0, sizeof(c));
6815         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6816                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6817                                    FW_VI_RXMODE_CMD_VIID_V(viid));
6818         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6819         c.mtu_to_vlanexen =
6820                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6821                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6822                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6823                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6824                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6825         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6826 }
6827
6828 /**
6829  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6830  *      @adap: the adapter
6831  *      @mbox: mailbox to use for the FW command
6832  *      @viid: the VI id
6833  *      @free: if true any existing filters for this VI id are first removed
6834  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6835  *      @addr: the MAC address(es)
6836  *      @idx: where to store the index of each allocated filter
6837  *      @hash: pointer to hash address filter bitmap
6838  *      @sleep_ok: call is allowed to sleep
6839  *
6840  *      Allocates an exact-match filter for each of the supplied addresses and
6841  *      sets it to the corresponding address.  If @idx is not %NULL it should
6842  *      have at least @naddr entries, each of which will be set to the index of
6843  *      the filter allocated for the corresponding MAC address.  If a filter
6844  *      could not be allocated for an address its index is set to 0xffff.
6845  *      If @hash is not %NULL addresses that fail to allocate an exact filter
6846  *      are hashed and update the hash filter bitmap pointed at by @hash.
6847  *
6848  *      Returns a negative error number or the number of filters allocated.
6849  */
6850 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6851                       unsigned int viid, bool free, unsigned int naddr,
6852                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6853 {
6854         int offset, ret = 0;
6855         struct fw_vi_mac_cmd c;
6856         unsigned int nfilters = 0;
6857         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6858         unsigned int rem = naddr;
6859
6860         if (naddr > max_naddr)
6861                 return -EINVAL;
6862
6863         for (offset = 0; offset < naddr ; /**/) {
6864                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6865                                          rem : ARRAY_SIZE(c.u.exact));
6866                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6867                                                      u.exact[fw_naddr]), 16);
6868                 struct fw_vi_mac_exact *p;
6869                 int i;
6870
6871                 memset(&c, 0, sizeof(c));
6872                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6873                                            FW_CMD_REQUEST_F |
6874                                            FW_CMD_WRITE_F |
6875                                            FW_CMD_EXEC_V(free) |
6876                                            FW_VI_MAC_CMD_VIID_V(viid));
6877                 c.freemacs_to_len16 =
6878                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6879                                     FW_CMD_LEN16_V(len16));
6880
6881                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6882                         p->valid_to_idx =
6883                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6884                                             FW_VI_MAC_CMD_IDX_V(
6885                                                     FW_VI_MAC_ADD_MAC));
6886                         memcpy(p->macaddr, addr[offset + i],
6887                                sizeof(p->macaddr));
6888                 }
6889
6890                 /* It's okay if we run out of space in our MAC address arena.
6891                  * Some of the addresses we submit may get stored so we need
6892                  * to run through the reply to see what the results were ...
6893                  */
6894                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6895                 if (ret && ret != -FW_ENOMEM)
6896                         break;
6897
6898                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6899                         u16 index = FW_VI_MAC_CMD_IDX_G(
6900                                         be16_to_cpu(p->valid_to_idx));
6901
6902                         if (idx)
6903                                 idx[offset + i] = (index >= max_naddr ?
6904                                                    0xffff : index);
6905                         if (index < max_naddr)
6906                                 nfilters++;
6907                         else if (hash)
6908                                 *hash |= (1ULL <<
6909                                           hash_mac_addr(addr[offset + i]));
6910                 }
6911
6912                 free = false;
6913                 offset += fw_naddr;
6914                 rem -= fw_naddr;
6915         }
6916
6917         if (ret == 0 || ret == -FW_ENOMEM)
6918                 ret = nfilters;
6919         return ret;
6920 }
6921
6922 /**
6923  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
6924  *      @adap: the adapter
6925  *      @mbox: mailbox to use for the FW command
6926  *      @viid: the VI id
6927  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6928  *      @addr: the MAC address(es)
6929  *      @sleep_ok: call is allowed to sleep
6930  *
6931  *      Frees the exact-match filter for each of the supplied addresses
6932  *
6933  *      Returns a negative error number or the number of filters freed.
6934  */
6935 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6936                      unsigned int viid, unsigned int naddr,
6937                      const u8 **addr, bool sleep_ok)
6938 {
6939         int offset, ret = 0;
6940         struct fw_vi_mac_cmd c;
6941         unsigned int nfilters = 0;
6942         unsigned int max_naddr = is_t4(adap->params.chip) ?
6943                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
6944                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6945         unsigned int rem = naddr;
6946
6947         if (naddr > max_naddr)
6948                 return -EINVAL;
6949
6950         for (offset = 0; offset < (int)naddr ; /**/) {
6951                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6952                                          ? rem
6953                                          : ARRAY_SIZE(c.u.exact));
6954                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6955                                                      u.exact[fw_naddr]), 16);
6956                 struct fw_vi_mac_exact *p;
6957                 int i;
6958
6959                 memset(&c, 0, sizeof(c));
6960                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6961                                      FW_CMD_REQUEST_F |
6962                                      FW_CMD_WRITE_F |
6963                                      FW_CMD_EXEC_V(0) |
6964                                      FW_VI_MAC_CMD_VIID_V(viid));
6965                 c.freemacs_to_len16 =
6966                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6967                                             FW_CMD_LEN16_V(len16));
6968
6969                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6970                         p->valid_to_idx = cpu_to_be16(
6971                                 FW_VI_MAC_CMD_VALID_F |
6972                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6973                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6974                 }
6975
6976                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6977                 if (ret)
6978                         break;
6979
6980                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6981                         u16 index = FW_VI_MAC_CMD_IDX_G(
6982                                                 be16_to_cpu(p->valid_to_idx));
6983
6984                         if (index < max_naddr)
6985                                 nfilters++;
6986                 }
6987
6988                 offset += fw_naddr;
6989                 rem -= fw_naddr;
6990         }
6991
6992         if (ret == 0)
6993                 ret = nfilters;
6994         return ret;
6995 }
6996
6997 /**
6998  *      t4_change_mac - modifies the exact-match filter for a MAC address
6999  *      @adap: the adapter
7000  *      @mbox: mailbox to use for the FW command
7001  *      @viid: the VI id
7002  *      @idx: index of existing filter for old value of MAC address, or -1
7003  *      @addr: the new MAC address value
7004  *      @persist: whether a new MAC allocation should be persistent
7005  *      @add_smt: if true also add the address to the HW SMT
7006  *
7007  *      Modifies an exact-match filter and sets it to the new MAC address.
7008  *      Note that in general it is not possible to modify the value of a given
7009  *      filter so the generic way to modify an address filter is to free the one
7010  *      being used by the old address value and allocate a new filter for the
7011  *      new address value.  @idx can be -1 if the address is a new addition.
7012  *
7013  *      Returns a negative error number or the index of the filter with the new
7014  *      MAC value.
7015  */
7016 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7017                   int idx, const u8 *addr, bool persist, bool add_smt)
7018 {
7019         int ret, mode;
7020         struct fw_vi_mac_cmd c;
7021         struct fw_vi_mac_exact *p = c.u.exact;
7022         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7023
7024         if (idx < 0)                             /* new allocation */
7025                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7026         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7027
7028         memset(&c, 0, sizeof(c));
7029         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7030                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7031                                    FW_VI_MAC_CMD_VIID_V(viid));
7032         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7033         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7034                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7035                                       FW_VI_MAC_CMD_IDX_V(idx));
7036         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7037
7038         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7039         if (ret == 0) {
7040                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7041                 if (ret >= max_mac_addr)
7042                         ret = -ENOMEM;
7043         }
7044         return ret;
7045 }
7046
7047 /**
7048  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7049  *      @adap: the adapter
7050  *      @mbox: mailbox to use for the FW command
7051  *      @viid: the VI id
7052  *      @ucast: whether the hash filter should also match unicast addresses
7053  *      @vec: the value to be written to the hash filter
7054  *      @sleep_ok: call is allowed to sleep
7055  *
7056  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7057  */
7058 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7059                      bool ucast, u64 vec, bool sleep_ok)
7060 {
7061         struct fw_vi_mac_cmd c;
7062
7063         memset(&c, 0, sizeof(c));
7064         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7065                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7066                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7067         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7068                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7069                                           FW_CMD_LEN16_V(1));
7070         c.u.hash.hashvec = cpu_to_be64(vec);
7071         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7072 }
7073
7074 /**
7075  *      t4_enable_vi_params - enable/disable a virtual interface
7076  *      @adap: the adapter
7077  *      @mbox: mailbox to use for the FW command
7078  *      @viid: the VI id
7079  *      @rx_en: 1=enable Rx, 0=disable Rx
7080  *      @tx_en: 1=enable Tx, 0=disable Tx
7081  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7082  *
7083  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7084  *      only makes sense when enabling a Virtual Interface ...
7085  */
7086 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7087                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7088 {
7089         struct fw_vi_enable_cmd c;
7090
7091         memset(&c, 0, sizeof(c));
7092         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7093                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7094                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7095         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7096                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7097                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7098                                      FW_LEN16(c));
7099         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7100 }
7101
7102 /**
7103  *      t4_enable_vi - enable/disable a virtual interface
7104  *      @adap: the adapter
7105  *      @mbox: mailbox to use for the FW command
7106  *      @viid: the VI id
7107  *      @rx_en: 1=enable Rx, 0=disable Rx
7108  *      @tx_en: 1=enable Tx, 0=disable Tx
7109  *
7110  *      Enables/disables a virtual interface.
7111  */
7112 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7113                  bool rx_en, bool tx_en)
7114 {
7115         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7116 }
7117
7118 /**
7119  *      t4_identify_port - identify a VI's port by blinking its LED
7120  *      @adap: the adapter
7121  *      @mbox: mailbox to use for the FW command
7122  *      @viid: the VI id
7123  *      @nblinks: how many times to blink LED at 2.5 Hz
7124  *
7125  *      Identifies a VI's port by blinking its LED.
7126  */
7127 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7128                      unsigned int nblinks)
7129 {
7130         struct fw_vi_enable_cmd c;
7131
7132         memset(&c, 0, sizeof(c));
7133         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7134                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7135                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7136         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7137         c.blinkdur = cpu_to_be16(nblinks);
7138         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7139 }
7140
7141 /**
7142  *      t4_iq_stop - stop an ingress queue and its FLs
7143  *      @adap: the adapter
7144  *      @mbox: mailbox to use for the FW command
7145  *      @pf: the PF owning the queues
7146  *      @vf: the VF owning the queues
7147  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7148  *      @iqid: ingress queue id
7149  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7150  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7151  *
7152  *      Stops an ingress queue and its associated FLs, if any.  This causes
7153  *      any current or future data/messages destined for these queues to be
7154  *      tossed.
7155  */
7156 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7157                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7158                unsigned int fl0id, unsigned int fl1id)
7159 {
7160         struct fw_iq_cmd c;
7161
7162         memset(&c, 0, sizeof(c));
7163         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7164                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7165                                   FW_IQ_CMD_VFN_V(vf));
7166         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7167         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7168         c.iqid = cpu_to_be16(iqid);
7169         c.fl0id = cpu_to_be16(fl0id);
7170         c.fl1id = cpu_to_be16(fl1id);
7171         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7172 }
7173
7174 /**
7175  *      t4_iq_free - free an ingress queue and its FLs
7176  *      @adap: the adapter
7177  *      @mbox: mailbox to use for the FW command
7178  *      @pf: the PF owning the queues
7179  *      @vf: the VF owning the queues
7180  *      @iqtype: the ingress queue type
7181  *      @iqid: ingress queue id
7182  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7183  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7184  *
7185  *      Frees an ingress queue and its associated FLs, if any.
7186  */
7187 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7188                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7189                unsigned int fl0id, unsigned int fl1id)
7190 {
7191         struct fw_iq_cmd c;
7192
7193         memset(&c, 0, sizeof(c));
7194         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7195                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7196                                   FW_IQ_CMD_VFN_V(vf));
7197         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7198         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7199         c.iqid = cpu_to_be16(iqid);
7200         c.fl0id = cpu_to_be16(fl0id);
7201         c.fl1id = cpu_to_be16(fl1id);
7202         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7203 }
7204
7205 /**
7206  *      t4_eth_eq_free - free an Ethernet egress queue
7207  *      @adap: the adapter
7208  *      @mbox: mailbox to use for the FW command
7209  *      @pf: the PF owning the queue
7210  *      @vf: the VF owning the queue
7211  *      @eqid: egress queue id
7212  *
7213  *      Frees an Ethernet egress queue.
7214  */
7215 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7216                    unsigned int vf, unsigned int eqid)
7217 {
7218         struct fw_eq_eth_cmd c;
7219
7220         memset(&c, 0, sizeof(c));
7221         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7222                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7223                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7224                                   FW_EQ_ETH_CMD_VFN_V(vf));
7225         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7226         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7227         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7228 }
7229
7230 /**
7231  *      t4_ctrl_eq_free - free a control egress queue
7232  *      @adap: the adapter
7233  *      @mbox: mailbox to use for the FW command
7234  *      @pf: the PF owning the queue
7235  *      @vf: the VF owning the queue
7236  *      @eqid: egress queue id
7237  *
7238  *      Frees a control egress queue.
7239  */
7240 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7241                     unsigned int vf, unsigned int eqid)
7242 {
7243         struct fw_eq_ctrl_cmd c;
7244
7245         memset(&c, 0, sizeof(c));
7246         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7247                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7248                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7249                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7250         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7251         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7252         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7253 }
7254
7255 /**
7256  *      t4_ofld_eq_free - free an offload egress queue
7257  *      @adap: the adapter
7258  *      @mbox: mailbox to use for the FW command
7259  *      @pf: the PF owning the queue
7260  *      @vf: the VF owning the queue
7261  *      @eqid: egress queue id
7262  *
7263  *      Frees a control egress queue.
7264  */
7265 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7266                     unsigned int vf, unsigned int eqid)
7267 {
7268         struct fw_eq_ofld_cmd c;
7269
7270         memset(&c, 0, sizeof(c));
7271         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7272                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7273                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7274                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7275         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7276         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7277         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7278 }
7279
7280 /**
7281  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7282  *      @adap: the adapter
7283  *      @link_down_rc: Link Down Reason Code
7284  *
7285  *      Returns a string representation of the Link Down Reason Code.
7286  */
7287 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7288 {
7289         static const char * const reason[] = {
7290                 "Link Down",
7291                 "Remote Fault",
7292                 "Auto-negotiation Failure",
7293                 "Reserved",
7294                 "Insufficient Airflow",
7295                 "Unable To Determine Reason",
7296                 "No RX Signal Detected",
7297                 "Reserved",
7298         };
7299
7300         if (link_down_rc >= ARRAY_SIZE(reason))
7301                 return "Bad Reason Code";
7302
7303         return reason[link_down_rc];
7304 }
7305
7306 /**
7307  *      t4_handle_get_port_info - process a FW reply message
7308  *      @pi: the port info
7309  *      @rpl: start of the FW message
7310  *
7311  *      Processes a GET_PORT_INFO FW reply message.
7312  */
7313 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7314 {
7315         const struct fw_port_cmd *p = (const void *)rpl;
7316         struct adapter *adap = pi->adapter;
7317
7318         /* link/module state change message */
7319         int speed = 0, fc = 0;
7320         struct link_config *lc;
7321         u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7322         int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7323         u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7324
7325         if (stat & FW_PORT_CMD_RXPAUSE_F)
7326                 fc |= PAUSE_RX;
7327         if (stat & FW_PORT_CMD_TXPAUSE_F)
7328                 fc |= PAUSE_TX;
7329         if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7330                 speed = 100;
7331         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7332                 speed = 1000;
7333         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7334                 speed = 10000;
7335         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7336                 speed = 25000;
7337         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7338                 speed = 40000;
7339         else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7340                 speed = 100000;
7341
7342         lc = &pi->link_cfg;
7343
7344         if (mod != pi->mod_type) {
7345                 pi->mod_type = mod;
7346                 t4_os_portmod_changed(adap, pi->port_id);
7347         }
7348         if (link_ok != lc->link_ok || speed != lc->speed ||
7349             fc != lc->fc) {     /* something changed */
7350                 if (!link_ok && lc->link_ok) {
7351                         unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7352
7353                         lc->link_down_rc = rc;
7354                         dev_warn(adap->pdev_dev,
7355                                  "Port %d link down, reason: %s\n",
7356                                  pi->port_id, t4_link_down_rc_str(rc));
7357                 }
7358                 lc->link_ok = link_ok;
7359                 lc->speed = speed;
7360                 lc->fc = fc;
7361                 lc->supported = be16_to_cpu(p->u.info.pcap);
7362                 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7363                 t4_os_link_changed(adap, pi->port_id, link_ok);
7364         }
7365 }
7366
7367 /**
7368  *      t4_handle_fw_rpl - process a FW reply message
7369  *      @adap: the adapter
7370  *      @rpl: start of the FW message
7371  *
7372  *      Processes a FW message, such as link state change messages.
7373  */
7374 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7375 {
7376         u8 opcode = *(const u8 *)rpl;
7377
7378         /* This might be a port command ... this simplifies the following
7379          * conditionals ...  We can get away with pre-dereferencing
7380          * action_to_len16 because it's in the first 16 bytes and all messages
7381          * will be at least that long.
7382          */
7383         const struct fw_port_cmd *p = (const void *)rpl;
7384         unsigned int action =
7385                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7386
7387         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7388                 int i;
7389                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7390                 struct port_info *pi = NULL;
7391
7392                 for_each_port(adap, i) {
7393                         pi = adap2pinfo(adap, i);
7394                         if (pi->tx_chan == chan)
7395                                 break;
7396                 }
7397
7398                 t4_handle_get_port_info(pi, rpl);
7399         } else {
7400                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7401                 return -EINVAL;
7402         }
7403         return 0;
7404 }
7405
7406 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7407 {
7408         u16 val;
7409
7410         if (pci_is_pcie(adapter->pdev)) {
7411                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7412                 p->speed = val & PCI_EXP_LNKSTA_CLS;
7413                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7414         }
7415 }
7416
7417 /**
7418  *      init_link_config - initialize a link's SW state
7419  *      @lc: structure holding the link state
7420  *      @caps: link capabilities
7421  *
7422  *      Initializes the SW state maintained for each link, including the link's
7423  *      capabilities and default speed/flow-control/autonegotiation settings.
7424  */
7425 static void init_link_config(struct link_config *lc, unsigned int pcaps,
7426                              unsigned int acaps)
7427 {
7428         lc->supported = pcaps;
7429         lc->lp_advertising = 0;
7430         lc->requested_speed = 0;
7431         lc->speed = 0;
7432         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7433         lc->auto_fec = 0;
7434
7435         /* For Forward Error Control, we default to whatever the Firmware
7436          * tells us the Link is currently advertising.
7437          */
7438         if (acaps & FW_PORT_CAP_FEC_RS)
7439                 lc->auto_fec |= FEC_RS;
7440         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
7441                 lc->auto_fec |= FEC_BASER_RS;
7442         lc->requested_fec = FEC_AUTO;
7443         lc->fec = lc->auto_fec;
7444
7445         if (lc->supported & FW_PORT_CAP_ANEG) {
7446                 lc->advertising = lc->supported & ADVERT_MASK;
7447                 lc->autoneg = AUTONEG_ENABLE;
7448                 lc->requested_fc |= PAUSE_AUTONEG;
7449         } else {
7450                 lc->advertising = 0;
7451                 lc->autoneg = AUTONEG_DISABLE;
7452         }
7453 }
7454
7455 #define CIM_PF_NOACCESS 0xeeeeeeee
7456
7457 int t4_wait_dev_ready(void __iomem *regs)
7458 {
7459         u32 whoami;
7460
7461         whoami = readl(regs + PL_WHOAMI_A);
7462         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7463                 return 0;
7464
7465         msleep(500);
7466         whoami = readl(regs + PL_WHOAMI_A);
7467         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7468 }
7469
7470 struct flash_desc {
7471         u32 vendor_and_model_id;
7472         u32 size_mb;
7473 };
7474
7475 static int get_flash_params(struct adapter *adap)
7476 {
7477         /* Table for non-Numonix supported flash parts.  Numonix parts are left
7478          * to the preexisting code.  All flash parts have 64KB sectors.
7479          */
7480         static struct flash_desc supported_flash[] = {
7481                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7482         };
7483
7484         int ret;
7485         u32 info;
7486
7487         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7488         if (!ret)
7489                 ret = sf1_read(adap, 3, 0, 1, &info);
7490         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
7491         if (ret)
7492                 return ret;
7493
7494         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7495                 if (supported_flash[ret].vendor_and_model_id == info) {
7496                         adap->params.sf_size = supported_flash[ret].size_mb;
7497                         adap->params.sf_nsec =
7498                                 adap->params.sf_size / SF_SEC_SIZE;
7499                         return 0;
7500                 }
7501
7502         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
7503                 return -EINVAL;
7504         info >>= 16;                           /* log2 of size */
7505         if (info >= 0x14 && info < 0x18)
7506                 adap->params.sf_nsec = 1 << (info - 16);
7507         else if (info == 0x18)
7508                 adap->params.sf_nsec = 64;
7509         else
7510                 return -EINVAL;
7511         adap->params.sf_size = 1 << info;
7512         adap->params.sf_fw_start =
7513                 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7514
7515         if (adap->params.sf_size < FLASH_MIN_SIZE)
7516                 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7517                          adap->params.sf_size, FLASH_MIN_SIZE);
7518         return 0;
7519 }
7520
7521 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7522 {
7523         u16 val;
7524         u32 pcie_cap;
7525
7526         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7527         if (pcie_cap) {
7528                 pci_read_config_word(adapter->pdev,
7529                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
7530                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7531                 val |= range;
7532                 pci_write_config_word(adapter->pdev,
7533                                       pcie_cap + PCI_EXP_DEVCTL2, val);
7534         }
7535 }
7536
7537 /**
7538  *      t4_prep_adapter - prepare SW and HW for operation
7539  *      @adapter: the adapter
7540  *      @reset: if true perform a HW reset
7541  *
7542  *      Initialize adapter SW state for the various HW modules, set initial
7543  *      values for some adapter tunables, take PHYs out of reset, and
7544  *      initialize the MDIO interface.
7545  */
7546 int t4_prep_adapter(struct adapter *adapter)
7547 {
7548         int ret, ver;
7549         uint16_t device_id;
7550         u32 pl_rev;
7551
7552         get_pci_mode(adapter, &adapter->params.pci);
7553         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7554
7555         ret = get_flash_params(adapter);
7556         if (ret < 0) {
7557                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7558                 return ret;
7559         }
7560
7561         /* Retrieve adapter's device ID
7562          */
7563         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7564         ver = device_id >> 12;
7565         adapter->params.chip = 0;
7566         switch (ver) {
7567         case CHELSIO_T4:
7568                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7569                 adapter->params.arch.sge_fl_db = DBPRIO_F;
7570                 adapter->params.arch.mps_tcam_size =
7571                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
7572                 adapter->params.arch.mps_rplc_size = 128;
7573                 adapter->params.arch.nchan = NCHAN;
7574                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7575                 adapter->params.arch.vfcount = 128;
7576                 /* Congestion map is for 4 channels so that
7577                  * MPS can have 4 priority per port.
7578                  */
7579                 adapter->params.arch.cng_ch_bits_log = 2;
7580                 break;
7581         case CHELSIO_T5:
7582                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7583                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7584                 adapter->params.arch.mps_tcam_size =
7585                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7586                 adapter->params.arch.mps_rplc_size = 128;
7587                 adapter->params.arch.nchan = NCHAN;
7588                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7589                 adapter->params.arch.vfcount = 128;
7590                 adapter->params.arch.cng_ch_bits_log = 2;
7591                 break;
7592         case CHELSIO_T6:
7593                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7594                 adapter->params.arch.sge_fl_db = 0;
7595                 adapter->params.arch.mps_tcam_size =
7596                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7597                 adapter->params.arch.mps_rplc_size = 256;
7598                 adapter->params.arch.nchan = 2;
7599                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7600                 adapter->params.arch.vfcount = 256;
7601                 /* Congestion map will be for 2 channels so that
7602                  * MPS can have 8 priority per port.
7603                  */
7604                 adapter->params.arch.cng_ch_bits_log = 3;
7605                 break;
7606         default:
7607                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7608                         device_id);
7609                 return -EINVAL;
7610         }
7611
7612         adapter->params.cim_la_size = CIMLA_SIZE;
7613         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7614
7615         /*
7616          * Default port for debugging in case we can't reach FW.
7617          */
7618         adapter->params.nports = 1;
7619         adapter->params.portvec = 1;
7620         adapter->params.vpd.cclk = 50000;
7621
7622         /* Set pci completion timeout value to 4 seconds. */
7623         set_pcie_completion_timeout(adapter, 0xd);
7624         return 0;
7625 }
7626
7627 /**
7628  *      t4_shutdown_adapter - shut down adapter, host & wire
7629  *      @adapter: the adapter
7630  *
7631  *      Perform an emergency shutdown of the adapter and stop it from
7632  *      continuing any further communication on the ports or DMA to the
7633  *      host.  This is typically used when the adapter and/or firmware
7634  *      have crashed and we want to prevent any further accidental
7635  *      communication with the rest of the world.  This will also force
7636  *      the port Link Status to go down -- if register writes work --
7637  *      which should help our peers figure out that we're down.
7638  */
7639 int t4_shutdown_adapter(struct adapter *adapter)
7640 {
7641         int port;
7642
7643         t4_intr_disable(adapter);
7644         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
7645         for_each_port(adapter, port) {
7646                 u32 a_port_cfg = PORT_REG(port,
7647                                           is_t4(adapter->params.chip)
7648                                           ? XGMAC_PORT_CFG_A
7649                                           : MAC_PORT_CFG_A);
7650
7651                 t4_write_reg(adapter, a_port_cfg,
7652                              t4_read_reg(adapter, a_port_cfg)
7653                              & ~SIGNAL_DET_V(1));
7654         }
7655         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
7656
7657         return 0;
7658 }
7659
7660 /**
7661  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7662  *      @adapter: the adapter
7663  *      @qid: the Queue ID
7664  *      @qtype: the Ingress or Egress type for @qid
7665  *      @user: true if this request is for a user mode queue
7666  *      @pbar2_qoffset: BAR2 Queue Offset
7667  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7668  *
7669  *      Returns the BAR2 SGE Queue Registers information associated with the
7670  *      indicated Absolute Queue ID.  These are passed back in return value
7671  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7672  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7673  *
7674  *      This may return an error which indicates that BAR2 SGE Queue
7675  *      registers aren't available.  If an error is not returned, then the
7676  *      following values are returned:
7677  *
7678  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7679  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7680  *
7681  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7682  *      require the "Inferred Queue ID" ability may be used.  E.g. the
7683  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7684  *      then these "Inferred Queue ID" register may not be used.
7685  */
7686 int t4_bar2_sge_qregs(struct adapter *adapter,
7687                       unsigned int qid,
7688                       enum t4_bar2_qtype qtype,
7689                       int user,
7690                       u64 *pbar2_qoffset,
7691                       unsigned int *pbar2_qid)
7692 {
7693         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7694         u64 bar2_page_offset, bar2_qoffset;
7695         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7696
7697         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7698         if (!user && is_t4(adapter->params.chip))
7699                 return -EINVAL;
7700
7701         /* Get our SGE Page Size parameters.
7702          */
7703         page_shift = adapter->params.sge.hps + 10;
7704         page_size = 1 << page_shift;
7705
7706         /* Get the right Queues per Page parameters for our Queue.
7707          */
7708         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7709                      ? adapter->params.sge.eq_qpp
7710                      : adapter->params.sge.iq_qpp);
7711         qpp_mask = (1 << qpp_shift) - 1;
7712
7713         /*  Calculate the basics of the BAR2 SGE Queue register area:
7714          *  o The BAR2 page the Queue registers will be in.
7715          *  o The BAR2 Queue ID.
7716          *  o The BAR2 Queue ID Offset into the BAR2 page.
7717          */
7718         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7719         bar2_qid = qid & qpp_mask;
7720         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7721
7722         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7723          * hardware will infer the Absolute Queue ID simply from the writes to
7724          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7725          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
7726          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7727          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7728          * from the BAR2 Page and BAR2 Queue ID.
7729          *
7730          * One important censequence of this is that some BAR2 SGE registers
7731          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7732          * there.  But other registers synthesize the SGE Queue ID purely
7733          * from the writes to the registers -- the Write Combined Doorbell
7734          * Buffer is a good example.  These BAR2 SGE Registers are only
7735          * available for those BAR2 SGE Register areas where the SGE Absolute
7736          * Queue ID can be inferred from simple writes.
7737          */
7738         bar2_qoffset = bar2_page_offset;
7739         bar2_qinferred = (bar2_qid_offset < page_size);
7740         if (bar2_qinferred) {
7741                 bar2_qoffset += bar2_qid_offset;
7742                 bar2_qid = 0;
7743         }
7744
7745         *pbar2_qoffset = bar2_qoffset;
7746         *pbar2_qid = bar2_qid;
7747         return 0;
7748 }
7749
7750 /**
7751  *      t4_init_devlog_params - initialize adapter->params.devlog
7752  *      @adap: the adapter
7753  *
7754  *      Initialize various fields of the adapter's Firmware Device Log
7755  *      Parameters structure.
7756  */
7757 int t4_init_devlog_params(struct adapter *adap)
7758 {
7759         struct devlog_params *dparams = &adap->params.devlog;
7760         u32 pf_dparams;
7761         unsigned int devlog_meminfo;
7762         struct fw_devlog_cmd devlog_cmd;
7763         int ret;
7764
7765         /* If we're dealing with newer firmware, the Device Log Paramerters
7766          * are stored in a designated register which allows us to access the
7767          * Device Log even if we can't talk to the firmware.
7768          */
7769         pf_dparams =
7770                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7771         if (pf_dparams) {
7772                 unsigned int nentries, nentries128;
7773
7774                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7775                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7776
7777                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7778                 nentries = (nentries128 + 1) * 128;
7779                 dparams->size = nentries * sizeof(struct fw_devlog_e);
7780
7781                 return 0;
7782         }
7783
7784         /* Otherwise, ask the firmware for it's Device Log Parameters.
7785          */
7786         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7787         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7788                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
7789         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7790         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7791                          &devlog_cmd);
7792         if (ret)
7793                 return ret;
7794
7795         devlog_meminfo =
7796                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7797         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7798         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7799         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7800
7801         return 0;
7802 }
7803
7804 /**
7805  *      t4_init_sge_params - initialize adap->params.sge
7806  *      @adapter: the adapter
7807  *
7808  *      Initialize various fields of the adapter's SGE Parameters structure.
7809  */
7810 int t4_init_sge_params(struct adapter *adapter)
7811 {
7812         struct sge_params *sge_params = &adapter->params.sge;
7813         u32 hps, qpp;
7814         unsigned int s_hps, s_qpp;
7815
7816         /* Extract the SGE Page Size for our PF.
7817          */
7818         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7819         s_hps = (HOSTPAGESIZEPF0_S +
7820                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7821         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7822
7823         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7824          */
7825         s_qpp = (QUEUESPERPAGEPF0_S +
7826                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7827         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7828         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7829         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7830         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7831
7832         return 0;
7833 }
7834
7835 /**
7836  *      t4_init_tp_params - initialize adap->params.tp
7837  *      @adap: the adapter
7838  *
7839  *      Initialize various fields of the adapter's TP Parameters structure.
7840  */
7841 int t4_init_tp_params(struct adapter *adap)
7842 {
7843         int chan;
7844         u32 v;
7845
7846         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7847         adap->params.tp.tre = TIMERRESOLUTION_G(v);
7848         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7849
7850         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7851         for (chan = 0; chan < NCHAN; chan++)
7852                 adap->params.tp.tx_modq[chan] = chan;
7853
7854         /* Cache the adapter's Compressed Filter Mode and global Incress
7855          * Configuration.
7856          */
7857         if (t4_use_ldst(adap)) {
7858                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7859                                 TP_VLAN_PRI_MAP_A, 1);
7860                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7861                                 TP_INGRESS_CONFIG_A, 1);
7862         } else {
7863                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7864                                  &adap->params.tp.vlan_pri_map, 1,
7865                                  TP_VLAN_PRI_MAP_A);
7866                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7867                                  &adap->params.tp.ingress_config, 1,
7868                                  TP_INGRESS_CONFIG_A);
7869         }
7870         /* For T6, cache the adapter's compressed error vector
7871          * and passing outer header info for encapsulated packets.
7872          */
7873         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
7874                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
7875                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
7876         }
7877
7878         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7879          * shift positions of several elements of the Compressed Filter Tuple
7880          * for this adapter which we need frequently ...
7881          */
7882         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7883         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7884         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7885         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7886                                                                PROTOCOL_F);
7887
7888         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7889          * represents the presence of an Outer VLAN instead of a VNIC ID.
7890          */
7891         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7892                 adap->params.tp.vnic_shift = -1;
7893
7894         return 0;
7895 }
7896
7897 /**
7898  *      t4_filter_field_shift - calculate filter field shift
7899  *      @adap: the adapter
7900  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7901  *
7902  *      Return the shift position of a filter field within the Compressed
7903  *      Filter Tuple.  The filter field is specified via its selection bit
7904  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
7905  */
7906 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7907 {
7908         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7909         unsigned int sel;
7910         int field_shift;
7911
7912         if ((filter_mode & filter_sel) == 0)
7913                 return -1;
7914
7915         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7916                 switch (filter_mode & sel) {
7917                 case FCOE_F:
7918                         field_shift += FT_FCOE_W;
7919                         break;
7920                 case PORT_F:
7921                         field_shift += FT_PORT_W;
7922                         break;
7923                 case VNIC_ID_F:
7924                         field_shift += FT_VNIC_ID_W;
7925                         break;
7926                 case VLAN_F:
7927                         field_shift += FT_VLAN_W;
7928                         break;
7929                 case TOS_F:
7930                         field_shift += FT_TOS_W;
7931                         break;
7932                 case PROTOCOL_F:
7933                         field_shift += FT_PROTOCOL_W;
7934                         break;
7935                 case ETHERTYPE_F:
7936                         field_shift += FT_ETHERTYPE_W;
7937                         break;
7938                 case MACMATCH_F:
7939                         field_shift += FT_MACMATCH_W;
7940                         break;
7941                 case MPSHITTYPE_F:
7942                         field_shift += FT_MPSHITTYPE_W;
7943                         break;
7944                 case FRAGMENTATION_F:
7945                         field_shift += FT_FRAGMENTATION_W;
7946                         break;
7947                 }
7948         }
7949         return field_shift;
7950 }
7951
7952 int t4_init_rss_mode(struct adapter *adap, int mbox)
7953 {
7954         int i, ret;
7955         struct fw_rss_vi_config_cmd rvc;
7956
7957         memset(&rvc, 0, sizeof(rvc));
7958
7959         for_each_port(adap, i) {
7960                 struct port_info *p = adap2pinfo(adap, i);
7961
7962                 rvc.op_to_viid =
7963                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7964                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
7965                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7966                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7967                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7968                 if (ret)
7969                         return ret;
7970                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7971         }
7972         return 0;
7973 }
7974
7975 /**
7976  *      t4_init_portinfo - allocate a virtual interface amd initialize port_info
7977  *      @pi: the port_info
7978  *      @mbox: mailbox to use for the FW command
7979  *      @port: physical port associated with the VI
7980  *      @pf: the PF owning the VI
7981  *      @vf: the VF owning the VI
7982  *      @mac: the MAC address of the VI
7983  *
7984  *      Allocates a virtual interface for the given physical port.  If @mac is
7985  *      not %NULL it contains the MAC address of the VI as assigned by FW.
7986  *      @mac should be large enough to hold an Ethernet address.
7987  *      Returns < 0 on error.
7988  */
7989 int t4_init_portinfo(struct port_info *pi, int mbox,
7990                      int port, int pf, int vf, u8 mac[])
7991 {
7992         int ret;
7993         struct fw_port_cmd c;
7994         unsigned int rss_size;
7995
7996         memset(&c, 0, sizeof(c));
7997         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7998                                      FW_CMD_REQUEST_F | FW_CMD_READ_F |
7999                                      FW_PORT_CMD_PORTID_V(port));
8000         c.action_to_len16 = cpu_to_be32(
8001                 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
8002                 FW_LEN16(c));
8003         ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
8004         if (ret)
8005                 return ret;
8006
8007         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8008         if (ret < 0)
8009                 return ret;
8010
8011         pi->viid = ret;
8012         pi->tx_chan = port;
8013         pi->lport = port;
8014         pi->rss_size = rss_size;
8015
8016         ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8017         pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
8018                 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
8019         pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
8020         pi->mod_type = FW_PORT_MOD_TYPE_NA;
8021
8022         init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
8023                          be16_to_cpu(c.u.info.acap));
8024         return 0;
8025 }
8026
8027 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8028 {
8029         u8 addr[6];
8030         int ret, i, j = 0;
8031
8032         for_each_port(adap, i) {
8033                 struct port_info *pi = adap2pinfo(adap, i);
8034
8035                 while ((adap->params.portvec & (1 << j)) == 0)
8036                         j++;
8037
8038                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8039                 if (ret)
8040                         return ret;
8041
8042                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8043                 j++;
8044         }
8045         return 0;
8046 }
8047
8048 /**
8049  *      t4_read_cimq_cfg - read CIM queue configuration
8050  *      @adap: the adapter
8051  *      @base: holds the queue base addresses in bytes
8052  *      @size: holds the queue sizes in bytes
8053  *      @thres: holds the queue full thresholds in bytes
8054  *
8055  *      Returns the current configuration of the CIM queues, starting with
8056  *      the IBQs, then the OBQs.
8057  */
8058 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8059 {
8060         unsigned int i, v;
8061         int cim_num_obq = is_t4(adap->params.chip) ?
8062                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8063
8064         for (i = 0; i < CIM_NUM_IBQ; i++) {
8065                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8066                              QUENUMSELECT_V(i));
8067                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8068                 /* value is in 256-byte units */
8069                 *base++ = CIMQBASE_G(v) * 256;
8070                 *size++ = CIMQSIZE_G(v) * 256;
8071                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8072         }
8073         for (i = 0; i < cim_num_obq; i++) {
8074                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8075                              QUENUMSELECT_V(i));
8076                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8077                 /* value is in 256-byte units */
8078                 *base++ = CIMQBASE_G(v) * 256;
8079                 *size++ = CIMQSIZE_G(v) * 256;
8080         }
8081 }
8082
8083 /**
8084  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
8085  *      @adap: the adapter
8086  *      @qid: the queue index
8087  *      @data: where to store the queue contents
8088  *      @n: capacity of @data in 32-bit words
8089  *
8090  *      Reads the contents of the selected CIM queue starting at address 0 up
8091  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8092  *      error and the number of 32-bit words actually read on success.
8093  */
8094 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8095 {
8096         int i, err, attempts;
8097         unsigned int addr;
8098         const unsigned int nwords = CIM_IBQ_SIZE * 4;
8099
8100         if (qid > 5 || (n & 3))
8101                 return -EINVAL;
8102
8103         addr = qid * nwords;
8104         if (n > nwords)
8105                 n = nwords;
8106
8107         /* It might take 3-10ms before the IBQ debug read access is allowed.
8108          * Wait for 1 Sec with a delay of 1 usec.
8109          */
8110         attempts = 1000000;
8111
8112         for (i = 0; i < n; i++, addr++) {
8113                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8114                              IBQDBGEN_F);
8115                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8116                                       attempts, 1);
8117                 if (err)
8118                         return err;
8119                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8120         }
8121         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8122         return i;
8123 }
8124
8125 /**
8126  *      t4_read_cim_obq - read the contents of a CIM outbound queue
8127  *      @adap: the adapter
8128  *      @qid: the queue index
8129  *      @data: where to store the queue contents
8130  *      @n: capacity of @data in 32-bit words
8131  *
8132  *      Reads the contents of the selected CIM queue starting at address 0 up
8133  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8134  *      error and the number of 32-bit words actually read on success.
8135  */
8136 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8137 {
8138         int i, err;
8139         unsigned int addr, v, nwords;
8140         int cim_num_obq = is_t4(adap->params.chip) ?
8141                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8142
8143         if ((qid > (cim_num_obq - 1)) || (n & 3))
8144                 return -EINVAL;
8145
8146         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8147                      QUENUMSELECT_V(qid));
8148         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8149
8150         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
8151         nwords = CIMQSIZE_G(v) * 64;  /* same */
8152         if (n > nwords)
8153                 n = nwords;
8154
8155         for (i = 0; i < n; i++, addr++) {
8156                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8157                              OBQDBGEN_F);
8158                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8159                                       2, 1);
8160                 if (err)
8161                         return err;
8162                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8163         }
8164         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8165         return i;
8166 }
8167
8168 /**
8169  *      t4_cim_read - read a block from CIM internal address space
8170  *      @adap: the adapter
8171  *      @addr: the start address within the CIM address space
8172  *      @n: number of words to read
8173  *      @valp: where to store the result
8174  *
8175  *      Reads a block of 4-byte words from the CIM intenal address space.
8176  */
8177 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8178                 unsigned int *valp)
8179 {
8180         int ret = 0;
8181
8182         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8183                 return -EBUSY;
8184
8185         for ( ; !ret && n--; addr += 4) {
8186                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8187                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8188                                       0, 5, 2);
8189                 if (!ret)
8190                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8191         }
8192         return ret;
8193 }
8194
8195 /**
8196  *      t4_cim_write - write a block into CIM internal address space
8197  *      @adap: the adapter
8198  *      @addr: the start address within the CIM address space
8199  *      @n: number of words to write
8200  *      @valp: set of values to write
8201  *
8202  *      Writes a block of 4-byte words into the CIM intenal address space.
8203  */
8204 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8205                  const unsigned int *valp)
8206 {
8207         int ret = 0;
8208
8209         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8210                 return -EBUSY;
8211
8212         for ( ; !ret && n--; addr += 4) {
8213                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8214                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8215                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8216                                       0, 5, 2);
8217         }
8218         return ret;
8219 }
8220
8221 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8222                          unsigned int val)
8223 {
8224         return t4_cim_write(adap, addr, 1, &val);
8225 }
8226
8227 /**
8228  *      t4_cim_read_la - read CIM LA capture buffer
8229  *      @adap: the adapter
8230  *      @la_buf: where to store the LA data
8231  *      @wrptr: the HW write pointer within the capture buffer
8232  *
8233  *      Reads the contents of the CIM LA buffer with the most recent entry at
8234  *      the end of the returned data and with the entry at @wrptr first.
8235  *      We try to leave the LA in the running state we find it in.
8236  */
8237 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8238 {
8239         int i, ret;
8240         unsigned int cfg, val, idx;
8241
8242         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8243         if (ret)
8244                 return ret;
8245
8246         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
8247                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8248                 if (ret)
8249                         return ret;
8250         }
8251
8252         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8253         if (ret)
8254                 goto restart;
8255
8256         idx = UPDBGLAWRPTR_G(val);
8257         if (wrptr)
8258                 *wrptr = idx;
8259
8260         for (i = 0; i < adap->params.cim_la_size; i++) {
8261                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8262                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8263                 if (ret)
8264                         break;
8265                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8266                 if (ret)
8267                         break;
8268                 if (val & UPDBGLARDEN_F) {
8269                         ret = -ETIMEDOUT;
8270                         break;
8271                 }
8272                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8273                 if (ret)
8274                         break;
8275                 idx = (idx + 1) & UPDBGLARDPTR_M;
8276         }
8277 restart:
8278         if (cfg & UPDBGLAEN_F) {
8279                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8280                                       cfg & ~UPDBGLARDEN_F);
8281                 if (!ret)
8282                         ret = r;
8283         }
8284         return ret;
8285 }
8286
8287 /**
8288  *      t4_tp_read_la - read TP LA capture buffer
8289  *      @adap: the adapter
8290  *      @la_buf: where to store the LA data
8291  *      @wrptr: the HW write pointer within the capture buffer
8292  *
8293  *      Reads the contents of the TP LA buffer with the most recent entry at
8294  *      the end of the returned data and with the entry at @wrptr first.
8295  *      We leave the LA in the running state we find it in.
8296  */
8297 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8298 {
8299         bool last_incomplete;
8300         unsigned int i, cfg, val, idx;
8301
8302         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8303         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
8304                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8305                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8306
8307         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8308         idx = DBGLAWPTR_G(val);
8309         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8310         if (last_incomplete)
8311                 idx = (idx + 1) & DBGLARPTR_M;
8312         if (wrptr)
8313                 *wrptr = idx;
8314
8315         val &= 0xffff;
8316         val &= ~DBGLARPTR_V(DBGLARPTR_M);
8317         val |= adap->params.tp.la_mask;
8318
8319         for (i = 0; i < TPLA_SIZE; i++) {
8320                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8321                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8322                 idx = (idx + 1) & DBGLARPTR_M;
8323         }
8324
8325         /* Wipe out last entry if it isn't valid */
8326         if (last_incomplete)
8327                 la_buf[TPLA_SIZE - 1] = ~0ULL;
8328
8329         if (cfg & DBGLAENABLE_F)                    /* restore running state */
8330                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8331                              cfg | adap->params.tp.la_mask);
8332 }
8333
8334 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8335  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8336  * state for more than the Warning Threshold then we'll issue a warning about
8337  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8338  * appears to be hung every Warning Repeat second till the situation clears.
8339  * If the situation clears, we'll note that as well.
8340  */
8341 #define SGE_IDMA_WARN_THRESH 1
8342 #define SGE_IDMA_WARN_REPEAT 300
8343
8344 /**
8345  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8346  *      @adapter: the adapter
8347  *      @idma: the adapter IDMA Monitor state
8348  *
8349  *      Initialize the state of an SGE Ingress DMA Monitor.
8350  */
8351 void t4_idma_monitor_init(struct adapter *adapter,
8352                           struct sge_idma_monitor_state *idma)
8353 {
8354         /* Initialize the state variables for detecting an SGE Ingress DMA
8355          * hang.  The SGE has internal counters which count up on each clock
8356          * tick whenever the SGE finds its Ingress DMA State Engines in the
8357          * same state they were on the previous clock tick.  The clock used is
8358          * the Core Clock so we have a limit on the maximum "time" they can
8359          * record; typically a very small number of seconds.  For instance,
8360          * with a 600MHz Core Clock, we can only count up to a bit more than
8361          * 7s.  So we'll synthesize a larger counter in order to not run the
8362          * risk of having the "timers" overflow and give us the flexibility to
8363          * maintain a Hung SGE State Machine of our own which operates across
8364          * a longer time frame.
8365          */
8366         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8367         idma->idma_stalled[0] = 0;
8368         idma->idma_stalled[1] = 0;
8369 }
8370
8371 /**
8372  *      t4_idma_monitor - monitor SGE Ingress DMA state
8373  *      @adapter: the adapter
8374  *      @idma: the adapter IDMA Monitor state
8375  *      @hz: number of ticks/second
8376  *      @ticks: number of ticks since the last IDMA Monitor call
8377  */
8378 void t4_idma_monitor(struct adapter *adapter,
8379                      struct sge_idma_monitor_state *idma,
8380                      int hz, int ticks)
8381 {
8382         int i, idma_same_state_cnt[2];
8383
8384          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8385           * are counters inside the SGE which count up on each clock when the
8386           * SGE finds its Ingress DMA State Engines in the same states they
8387           * were in the previous clock.  The counters will peg out at
8388           * 0xffffffff without wrapping around so once they pass the 1s
8389           * threshold they'll stay above that till the IDMA state changes.
8390           */
8391         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8392         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8393         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8394
8395         for (i = 0; i < 2; i++) {
8396                 u32 debug0, debug11;
8397
8398                 /* If the Ingress DMA Same State Counter ("timer") is less
8399                  * than 1s, then we can reset our synthesized Stall Timer and
8400                  * continue.  If we have previously emitted warnings about a
8401                  * potential stalled Ingress Queue, issue a note indicating
8402                  * that the Ingress Queue has resumed forward progress.
8403                  */
8404                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8405                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8406                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8407                                          "resumed after %d seconds\n",
8408                                          i, idma->idma_qid[i],
8409                                          idma->idma_stalled[i] / hz);
8410                         idma->idma_stalled[i] = 0;
8411                         continue;
8412                 }
8413
8414                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8415                  * domain.  The first time we get here it'll be because we
8416                  * passed the 1s Threshold; each additional time it'll be
8417                  * because the RX Timer Callback is being fired on its regular
8418                  * schedule.
8419                  *
8420                  * If the stall is below our Potential Hung Ingress Queue
8421                  * Warning Threshold, continue.
8422                  */
8423                 if (idma->idma_stalled[i] == 0) {
8424                         idma->idma_stalled[i] = hz;
8425                         idma->idma_warn[i] = 0;
8426                 } else {
8427                         idma->idma_stalled[i] += ticks;
8428                         idma->idma_warn[i] -= ticks;
8429                 }
8430
8431                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8432                         continue;
8433
8434                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8435                  */
8436                 if (idma->idma_warn[i] > 0)
8437                         continue;
8438                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8439
8440                 /* Read and save the SGE IDMA State and Queue ID information.
8441                  * We do this every time in case it changes across time ...
8442                  * can't be too careful ...
8443                  */
8444                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8445                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8446                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8447
8448                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8449                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8450                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8451
8452                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8453                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8454                          i, idma->idma_qid[i], idma->idma_state[i],
8455                          idma->idma_stalled[i] / hz,
8456                          debug0, debug11);
8457                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8458         }
8459 }
8460
8461 /**
8462  *      t4_set_vf_mac - Set MAC address for the specified VF
8463  *      @adapter: The adapter
8464  *      @vf: one of the VFs instantiated by the specified PF
8465  *      @naddr: the number of MAC addresses
8466  *      @addr: the MAC address(es) to be set to the specified VF
8467  */
8468 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8469                       unsigned int naddr, u8 *addr)
8470 {
8471         struct fw_acl_mac_cmd cmd;
8472
8473         memset(&cmd, 0, sizeof(cmd));
8474         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8475                                     FW_CMD_REQUEST_F |
8476                                     FW_CMD_WRITE_F |
8477                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8478                                     FW_ACL_MAC_CMD_VFN_V(vf));
8479
8480         /* Note: Do not enable the ACL */
8481         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8482         cmd.nmac = naddr;
8483
8484         switch (adapter->pf) {
8485         case 3:
8486                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8487                 break;
8488         case 2:
8489                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8490                 break;
8491         case 1:
8492                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8493                 break;
8494         case 0:
8495                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8496                 break;
8497         }
8498
8499         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8500 }
8501
8502 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8503                     int rateunit, int ratemode, int channel, int class,
8504                     int minrate, int maxrate, int weight, int pktsize)
8505 {
8506         struct fw_sched_cmd cmd;
8507
8508         memset(&cmd, 0, sizeof(cmd));
8509         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8510                                       FW_CMD_REQUEST_F |
8511                                       FW_CMD_WRITE_F);
8512         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8513
8514         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8515         cmd.u.params.type = type;
8516         cmd.u.params.level = level;
8517         cmd.u.params.mode = mode;
8518         cmd.u.params.ch = channel;
8519         cmd.u.params.cl = class;
8520         cmd.u.params.unit = rateunit;
8521         cmd.u.params.rate = ratemode;
8522         cmd.u.params.min = cpu_to_be32(minrate);
8523         cmd.u.params.max = cpu_to_be32(maxrate);
8524         cmd.u.params.weight = cpu_to_be16(weight);
8525         cmd.u.params.pktsize = cpu_to_be16(pktsize);
8526
8527         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
8528                                NULL, 1);
8529 }