2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
287 struct mbox_list entry;
292 int i, ms, delay_idx, ret;
293 const __be64 *p = cmd;
294 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
295 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
296 __be64 cmd_rpl[MBOX_LEN / 8];
299 if ((size & 15) || size > MBOX_LEN)
303 * If the device is off-line, as in EEH, commands will time out.
304 * Fail them early so we don't waste time waiting.
306 if (adap->pdev->error_state != pci_channel_io_normal)
309 /* If we have a negative timeout, that implies that we can't sleep. */
315 /* Queue ourselves onto the mailbox access list. When our entry is at
316 * the front of the list, we have rights to access the mailbox. So we
317 * wait [for a while] till we're at the front [or bail out with an
320 spin_lock(&adap->mbox_lock);
321 list_add_tail(&entry.list, &adap->mlist.list);
322 spin_unlock(&adap->mbox_lock);
327 for (i = 0; ; i += ms) {
328 /* If we've waited too long, return a busy indication. This
329 * really ought to be based on our initial position in the
330 * mailbox access list but this is a start. We very rearely
331 * contend on access to the mailbox ...
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
334 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
335 spin_lock(&adap->mbox_lock);
336 list_del(&entry.list);
337 spin_unlock(&adap->mbox_lock);
338 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
339 t4_record_mbox(adap, cmd, size, access, ret);
343 /* If we're at the head, break out and start the mailbox
346 if (list_first_entry(&adap->mlist.list, struct mbox_list,
350 /* Delay for a bit before checking again ... */
352 ms = delay[delay_idx]; /* last element may repeat */
353 if (delay_idx < ARRAY_SIZE(delay) - 1)
361 /* Loop trying to get ownership of the mailbox. Return an error
362 * if we can't gain ownership.
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
365 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 if (v != MBOX_OWNER_DRV) {
368 spin_lock(&adap->mbox_lock);
369 list_del(&entry.list);
370 spin_unlock(&adap->mbox_lock);
371 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
372 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
376 /* Copy in the new mailbox command and send it on its way ... */
377 t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
378 for (i = 0; i < size; i += 8)
379 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
381 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
382 t4_read_reg(adap, ctl_reg); /* flush write */
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
392 ms = delay[delay_idx]; /* last element may repeat */
393 if (delay_idx < ARRAY_SIZE(delay) - 1)
399 v = t4_read_reg(adap, ctl_reg);
400 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
401 if (!(v & MBMSGVALID_F)) {
402 t4_write_reg(adap, ctl_reg, 0);
406 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
407 res = be64_to_cpu(cmd_rpl[0]);
409 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
410 fw_asrt(adap, data_reg);
411 res = FW_CMD_RETVAL_V(EIO);
413 memcpy(rpl, cmd_rpl, size);
416 t4_write_reg(adap, ctl_reg, 0);
419 t4_record_mbox(adap, cmd_rpl,
420 MBOX_LEN, access, execute);
421 spin_lock(&adap->mbox_lock);
422 list_del(&entry.list);
423 spin_unlock(&adap->mbox_lock);
424 return -FW_CMD_RETVAL_G((int)res);
428 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
429 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
430 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
431 *(const u8 *)cmd, mbox);
432 t4_report_fw_error(adap);
433 spin_lock(&adap->mbox_lock);
434 list_del(&entry.list);
435 spin_unlock(&adap->mbox_lock);
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441 void *rpl, bool sleep_ok)
443 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
447 static int t4_edc_err_read(struct adapter *adap, int idx)
449 u32 edc_ecc_err_addr_reg;
452 if (is_t4(adap->params.chip)) {
453 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
456 if (idx != 0 && idx != 1) {
457 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
461 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
462 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
465 "edc%d err addr 0x%x: 0x%x.\n",
466 idx, edc_ecc_err_addr_reg,
467 t4_read_reg(adap, edc_ecc_err_addr_reg));
469 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
471 (unsigned long long)t4_read_reg64(adap, rdata_reg),
472 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
473 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
485 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
487 * @win: PCI-E Memory Window to use
488 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
489 * @addr: address within indicated memory type
490 * @len: amount of memory to transfer
491 * @hbuf: host memory buffer
492 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
494 * Reads/writes an [almost] arbitrary memory region in the firmware: the
495 * firmware memory address and host buffer must be aligned on 32-bit
496 * boudaries; the length may be arbitrary. The memory is transferred as
497 * a raw byte sequence from/to the firmware's memory. If this memory
498 * contains data structures which contain multi-byte integers, it's the
499 * caller's responsibility to perform appropriate byte order conversions.
501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
502 u32 len, void *hbuf, int dir)
504 u32 pos, offset, resid, memoffset;
505 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
508 /* Argument sanity checks ...
510 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
514 /* It's convenient to be able to handle lengths which aren't a
515 * multiple of 32-bits because we often end up transferring files to
516 * the firmware. So we'll handle that by normalizing the length here
517 * and then handling any residual transfer at the end.
522 /* Offset into the region of memory which is being accessed
525 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
526 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
529 if (mtype != MEM_MC1)
530 memoffset = (mtype * (edc_size * 1024 * 1024));
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
533 MA_EXT_MEMORY0_BAR_A));
534 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
537 /* Determine the PCIE_MEM_ACCESS_OFFSET */
538 addr = addr + memoffset;
540 /* Each PCI-E Memory Window is programmed with a window size -- or
541 * "aperture" -- which controls the granularity of its mapping onto
542 * adapter memory. We need to grab that aperture in order to know
543 * how to use the specified window. The window is also programmed
544 * with the base address of the Memory Window in BAR0's address
545 * space. For T4 this is an absolute PCI-E Bus Address. For T5
546 * the address is relative to BAR0.
548 mem_reg = t4_read_reg(adap,
549 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
551 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
552 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
553 if (is_t4(adap->params.chip))
554 mem_base -= adap->t4_bar0;
555 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
557 /* Calculate our initial PCI-E Memory Window Position and Offset into
560 pos = addr & ~(mem_aperture-1);
563 /* Set up initial PCI-E Memory Window to cover the start of our
564 * transfer. (Read it back to ensure that changes propagate before we
565 * attempt to use the new value.)
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
573 /* Transfer data to/from the adapter as long as there's an integral
574 * number of 32-bit transfers to complete.
576 * A note on Endianness issues:
578 * The "register" reads and writes below from/to the PCI-E Memory
579 * Window invoke the standard adapter Big-Endian to PCI-E Link
580 * Little-Endian "swizzel." As a result, if we have the following
581 * data in adapter memory:
583 * Memory: ... | b0 | b1 | b2 | b3 | ...
584 * Address: i+0 i+1 i+2 i+3
586 * Then a read of the adapter memory via the PCI-E Memory Window
591 * [ b3 | b2 | b1 | b0 ]
593 * If this value is stored into local memory on a Little-Endian system
594 * it will show up correctly in local memory as:
596 * ( ..., b0, b1, b2, b3, ... )
598 * But on a Big-Endian system, the store will show up in memory
599 * incorrectly swizzled as:
601 * ( ..., b3, b2, b1, b0, ... )
603 * So we need to account for this in the reads and writes to the
604 * PCI-E Memory Window below by undoing the register read/write
608 if (dir == T4_MEMORY_READ)
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
612 t4_write_reg(adap, mem_base + offset,
613 (__force u32)cpu_to_le32(*buf++));
614 offset += sizeof(__be32);
615 len -= sizeof(__be32);
617 /* If we've reached the end of our current window aperture,
618 * move the PCI-E Memory Window on to the next. Note that
619 * doing this here after "len" may be 0 allows us to set up
620 * the PCI-E Memory Window for a possible final residual
623 if (offset == mem_aperture) {
627 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
630 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
635 /* If the original transfer had a length which wasn't a multiple of
636 * 32-bits, now's where we need to finish off the transfer of the
637 * residual amount. The PCI-E Memory Window has already been moved
638 * above (if necessary) to cover this final transfer.
648 if (dir == T4_MEMORY_READ) {
649 last.word = le32_to_cpu(
650 (__force __le32)t4_read_reg(adap,
652 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
653 bp[i] = last.byte[i];
656 for (i = resid; i < 4; i++)
658 t4_write_reg(adap, mem_base + offset,
659 (__force u32)cpu_to_le32(last.word));
666 /* Return the specified PCI-E Configuration Space register from our Physical
667 * Function. We try first via a Firmware LDST Command since we prefer to let
668 * the firmware own all of these registers, but if that fails we go for it
669 * directly ourselves.
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
673 u32 val, ldst_addrspace;
675 /* If fw_attach != 0, construct and send the Firmware LDST Command to
676 * retrieve the specified PCI-E Configuration Space register.
678 struct fw_ldst_cmd ldst_cmd;
681 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
682 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
683 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
687 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
688 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
689 ldst_cmd.u.pcie.ctrl_to_fn =
690 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
691 ldst_cmd.u.pcie.r = reg;
693 /* If the LDST Command succeeds, return the result, otherwise
694 * fall through to reading it directly ourselves ...
696 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
699 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
701 /* Read the desired Configuration Space register via the PCI-E
702 * Backdoor mechanism.
704 t4_hw_pci_read_cfg4(adap, reg, &val);
708 /* Get the window based on base passed to it.
709 * Window aperture is currently unhandled, but there is no use case for it
712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
717 if (is_t4(adap->params.chip)) {
720 /* Truncation intentional: we only read the bottom 32-bits of
721 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
722 * mechanism to read BAR0 instead of using
723 * pci_resource_start() because we could be operating from
724 * within a Virtual Machine which is trapping our accesses to
725 * our Configuration Space and we need to set up the PCI-E
726 * Memory Window decoders with the actual addresses which will
727 * be coming across the PCI-E link.
729 bar0 = t4_read_pcie_cfg4(adap, pci_base);
731 adap->t4_bar0 = bar0;
733 ret = bar0 + memwin_base;
735 /* For T5, only relative offset inside the PCIe BAR is passed */
741 /* Get the default utility window (win0) used by everyone */
742 u32 t4_get_util_window(struct adapter *adap)
744 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
745 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
748 /* Set up memory window for accessing adapter memory ranges. (Read
749 * back MA register to ensure that changes propagate before we attempt
750 * to use the new values.)
752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
755 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
756 memwin_base | BIR_V(0) |
757 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
759 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
763 * t4_get_regs_len - return the size of the chips register set
764 * @adapter: the adapter
766 * Returns the size of the chip's BAR0 register space.
768 unsigned int t4_get_regs_len(struct adapter *adapter)
770 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
772 switch (chip_version) {
774 return T4_REGMAP_SIZE;
778 return T5_REGMAP_SIZE;
781 dev_err(adapter->pdev_dev,
782 "Unsupported chip version %d\n", chip_version);
787 * t4_get_regs - read chip registers into provided buffer
789 * @buf: register buffer
790 * @buf_size: size (in bytes) of register buffer
792 * If the provided register buffer isn't large enough for the chip's
793 * full register range, the register dump will be truncated to the
794 * register buffer's size.
796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
798 static const unsigned int t4_reg_ranges[] = {
1256 static const unsigned int t5_reg_ranges[] = {
2031 static const unsigned int t6_reg_ranges[] = {
2608 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2609 const unsigned int *reg_ranges;
2610 int reg_ranges_size, range;
2611 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2613 /* Select the right set of register ranges to dump depending on the
2614 * adapter chip type.
2616 switch (chip_version) {
2618 reg_ranges = t4_reg_ranges;
2619 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2623 reg_ranges = t5_reg_ranges;
2624 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2628 reg_ranges = t6_reg_ranges;
2629 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2633 dev_err(adap->pdev_dev,
2634 "Unsupported chip version %d\n", chip_version);
2638 /* Clear the register buffer and insert the appropriate register
2639 * values selected by the above register ranges.
2641 memset(buf, 0, buf_size);
2642 for (range = 0; range < reg_ranges_size; range += 2) {
2643 unsigned int reg = reg_ranges[range];
2644 unsigned int last_reg = reg_ranges[range + 1];
2645 u32 *bufp = (u32 *)((char *)buf + reg);
2647 /* Iterate across the register range filling in the register
2648 * buffer but don't write past the end of the register buffer.
2650 while (reg <= last_reg && bufp < buf_end) {
2651 *bufp++ = t4_read_reg(adap, reg);
2657 #define EEPROM_STAT_ADDR 0x7bfc
2658 #define VPD_SIZE 0x800
2659 #define VPD_BASE 0x400
2660 #define VPD_BASE_OLD 0
2661 #define VPD_LEN 1024
2662 #define CHELSIO_VPD_UNIQUE_ID 0x82
2665 * t4_seeprom_wp - enable/disable EEPROM write protection
2666 * @adapter: the adapter
2667 * @enable: whether to enable or disable write protection
2669 * Enables or disables write protection on the serial EEPROM.
2671 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2673 unsigned int v = enable ? 0xc : 0;
2674 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2675 return ret < 0 ? ret : 0;
2679 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2680 * @adapter: adapter to read
2681 * @p: where to store the parameters
2683 * Reads card parameters stored in VPD EEPROM.
2685 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2687 int i, ret = 0, addr;
2690 unsigned int vpdr_len, kw_offset, id_len;
2692 vpd = vmalloc(VPD_LEN);
2696 /* We have two VPD data structures stored in the adapter VPD area.
2697 * By default, Linux calculates the size of the VPD area by traversing
2698 * the first VPD area at offset 0x0, so we need to tell the OS what
2699 * our real VPD size is.
2701 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2705 /* Card information normally starts at VPD_BASE but early cards had
2708 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2712 /* The VPD shall have a unique identifier specified by the PCI SIG.
2713 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2714 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2715 * is expected to automatically put this entry at the
2716 * beginning of the VPD.
2718 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2720 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2724 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2725 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2730 id_len = pci_vpd_lrdt_size(vpd);
2731 if (id_len > ID_LEN)
2734 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2736 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2741 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2742 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2743 if (vpdr_len + kw_offset > VPD_LEN) {
2744 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2749 #define FIND_VPD_KW(var, name) do { \
2750 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2752 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2756 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2759 FIND_VPD_KW(i, "RV");
2760 for (csum = 0; i >= 0; i--)
2764 dev_err(adapter->pdev_dev,
2765 "corrupted VPD EEPROM, actual csum %u\n", csum);
2770 FIND_VPD_KW(ec, "EC");
2771 FIND_VPD_KW(sn, "SN");
2772 FIND_VPD_KW(pn, "PN");
2773 FIND_VPD_KW(na, "NA");
2776 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2778 memcpy(p->ec, vpd + ec, EC_LEN);
2780 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2781 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2783 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2784 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2786 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2787 strim((char *)p->na);
2791 return ret < 0 ? ret : 0;
2795 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2796 * @adapter: adapter to read
2797 * @p: where to store the parameters
2799 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2800 * Clock. This can only be called after a connection to the firmware
2803 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2805 u32 cclk_param, cclk_val;
2808 /* Grab the raw VPD parameters.
2810 ret = t4_get_raw_vpd_params(adapter, p);
2814 /* Ask firmware for the Core Clock since it knows how to translate the
2815 * Reference Clock ('V2') VPD field into a Core Clock value ...
2817 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2818 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2819 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2820 1, &cclk_param, &cclk_val);
2829 /* serial flash and firmware constants */
2831 SF_ATTEMPTS = 10, /* max retries for SF operations */
2833 /* flash command opcodes */
2834 SF_PROG_PAGE = 2, /* program page */
2835 SF_WR_DISABLE = 4, /* disable writes */
2836 SF_RD_STATUS = 5, /* read status register */
2837 SF_WR_ENABLE = 6, /* enable writes */
2838 SF_RD_DATA_FAST = 0xb, /* read flash */
2839 SF_RD_ID = 0x9f, /* read ID */
2840 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2842 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2846 * sf1_read - read data from the serial flash
2847 * @adapter: the adapter
2848 * @byte_cnt: number of bytes to read
2849 * @cont: whether another operation will be chained
2850 * @lock: whether to lock SF for PL access only
2851 * @valp: where to store the read data
2853 * Reads up to 4 bytes of data from the serial flash. The location of
2854 * the read needs to be specified prior to calling this by issuing the
2855 * appropriate commands to the serial flash.
2857 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2858 int lock, u32 *valp)
2862 if (!byte_cnt || byte_cnt > 4)
2864 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2866 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2867 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2868 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2870 *valp = t4_read_reg(adapter, SF_DATA_A);
2875 * sf1_write - write data to the serial flash
2876 * @adapter: the adapter
2877 * @byte_cnt: number of bytes to write
2878 * @cont: whether another operation will be chained
2879 * @lock: whether to lock SF for PL access only
2880 * @val: value to write
2882 * Writes up to 4 bytes of data to the serial flash. The location of
2883 * the write needs to be specified prior to calling this by issuing the
2884 * appropriate commands to the serial flash.
2886 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2889 if (!byte_cnt || byte_cnt > 4)
2891 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2893 t4_write_reg(adapter, SF_DATA_A, val);
2894 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2895 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2896 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2900 * flash_wait_op - wait for a flash operation to complete
2901 * @adapter: the adapter
2902 * @attempts: max number of polls of the status register
2903 * @delay: delay between polls in ms
2905 * Wait for a flash operation to complete by polling the status register.
2907 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2913 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2914 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2918 if (--attempts == 0)
2926 * t4_read_flash - read words from serial flash
2927 * @adapter: the adapter
2928 * @addr: the start address for the read
2929 * @nwords: how many 32-bit words to read
2930 * @data: where to store the read data
2931 * @byte_oriented: whether to store data as bytes or as words
2933 * Read the specified number of 32-bit words from the serial flash.
2934 * If @byte_oriented is set the read data is stored as a byte array
2935 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2936 * natural endianness.
2938 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2939 unsigned int nwords, u32 *data, int byte_oriented)
2943 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2946 addr = swab32(addr) | SF_RD_DATA_FAST;
2948 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2949 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2952 for ( ; nwords; nwords--, data++) {
2953 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2955 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2959 *data = (__force __u32)(cpu_to_be32(*data));
2965 * t4_write_flash - write up to a page of data to the serial flash
2966 * @adapter: the adapter
2967 * @addr: the start address to write
2968 * @n: length of data to write in bytes
2969 * @data: the data to write
2971 * Writes up to a page of data (256 bytes) to the serial flash starting
2972 * at the given address. All the data must be written to the same page.
2974 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2975 unsigned int n, const u8 *data)
2979 unsigned int i, c, left, val, offset = addr & 0xff;
2981 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2984 val = swab32(addr) | SF_PROG_PAGE;
2986 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2987 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2990 for (left = n; left; left -= c) {
2992 for (val = 0, i = 0; i < c; ++i)
2993 val = (val << 8) + *data++;
2995 ret = sf1_write(adapter, c, c != left, 1, val);
2999 ret = flash_wait_op(adapter, 8, 1);
3003 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3005 /* Read the page to verify the write succeeded */
3006 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3010 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3011 dev_err(adapter->pdev_dev,
3012 "failed to correctly write the flash page at %#x\n",
3019 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3024 * t4_get_fw_version - read the firmware version
3025 * @adapter: the adapter
3026 * @vers: where to place the version
3028 * Reads the FW version from flash.
3030 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3032 return t4_read_flash(adapter, FLASH_FW_START +
3033 offsetof(struct fw_hdr, fw_ver), 1,
3038 * t4_get_bs_version - read the firmware bootstrap version
3039 * @adapter: the adapter
3040 * @vers: where to place the version
3042 * Reads the FW Bootstrap version from flash.
3044 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3046 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3047 offsetof(struct fw_hdr, fw_ver), 1,
3052 * t4_get_tp_version - read the TP microcode version
3053 * @adapter: the adapter
3054 * @vers: where to place the version
3056 * Reads the TP microcode version from flash.
3058 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3060 return t4_read_flash(adapter, FLASH_FW_START +
3061 offsetof(struct fw_hdr, tp_microcode_ver),
3066 * t4_get_exprom_version - return the Expansion ROM version (if any)
3067 * @adapter: the adapter
3068 * @vers: where to place the version
3070 * Reads the Expansion ROM header from FLASH and returns the version
3071 * number (if present) through the @vers return value pointer. We return
3072 * this in the Firmware Version Format since it's convenient. Return
3073 * 0 on success, -ENOENT if no Expansion ROM is present.
3075 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3077 struct exprom_header {
3078 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3079 unsigned char hdr_ver[4]; /* Expansion ROM version */
3081 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3085 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3086 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3091 hdr = (struct exprom_header *)exprom_header_buf;
3092 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3095 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3096 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3097 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3098 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3103 * t4_check_fw_version - check if the FW is supported with this driver
3104 * @adap: the adapter
3106 * Checks if an adapter's FW is compatible with the driver. Returns 0
3107 * if there's exact match, a negative error if the version could not be
3108 * read or there's a major version mismatch
3110 int t4_check_fw_version(struct adapter *adap)
3112 int i, ret, major, minor, micro;
3113 int exp_major, exp_minor, exp_micro;
3114 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3116 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3117 /* Try multiple times before returning error */
3118 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3119 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3124 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3125 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3126 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3128 switch (chip_version) {
3130 exp_major = T4FW_MIN_VERSION_MAJOR;
3131 exp_minor = T4FW_MIN_VERSION_MINOR;
3132 exp_micro = T4FW_MIN_VERSION_MICRO;
3135 exp_major = T5FW_MIN_VERSION_MAJOR;
3136 exp_minor = T5FW_MIN_VERSION_MINOR;
3137 exp_micro = T5FW_MIN_VERSION_MICRO;
3140 exp_major = T6FW_MIN_VERSION_MAJOR;
3141 exp_minor = T6FW_MIN_VERSION_MINOR;
3142 exp_micro = T6FW_MIN_VERSION_MICRO;
3145 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3150 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3151 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3152 dev_err(adap->pdev_dev,
3153 "Card has firmware version %u.%u.%u, minimum "
3154 "supported firmware is %u.%u.%u.\n", major, minor,
3155 micro, exp_major, exp_minor, exp_micro);
3161 /* Is the given firmware API compatible with the one the driver was compiled
3164 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3167 /* short circuit if it's the exact same firmware version */
3168 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3171 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3172 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3173 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3180 /* The firmware in the filesystem is usable, but should it be installed?
3181 * This routine explains itself in detail if it indicates the filesystem
3182 * firmware should be installed.
3184 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3189 if (!card_fw_usable) {
3190 reason = "incompatible or unusable";
3195 reason = "older than the version supported with this driver";
3202 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3203 "installing firmware %u.%u.%u.%u on card.\n",
3204 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3205 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3206 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3207 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3212 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3213 const u8 *fw_data, unsigned int fw_size,
3214 struct fw_hdr *card_fw, enum dev_state state,
3217 int ret, card_fw_usable, fs_fw_usable;
3218 const struct fw_hdr *fs_fw;
3219 const struct fw_hdr *drv_fw;
3221 drv_fw = &fw_info->fw_hdr;
3223 /* Read the header of the firmware on the card */
3224 ret = -t4_read_flash(adap, FLASH_FW_START,
3225 sizeof(*card_fw) / sizeof(uint32_t),
3226 (uint32_t *)card_fw, 1);
3228 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3230 dev_err(adap->pdev_dev,
3231 "Unable to read card's firmware header: %d\n", ret);
3235 if (fw_data != NULL) {
3236 fs_fw = (const void *)fw_data;
3237 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3243 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3244 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3245 /* Common case: the firmware on the card is an exact match and
3246 * the filesystem one is an exact match too, or the filesystem
3247 * one is absent/incompatible.
3249 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3250 should_install_fs_fw(adap, card_fw_usable,
3251 be32_to_cpu(fs_fw->fw_ver),
3252 be32_to_cpu(card_fw->fw_ver))) {
3253 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3256 dev_err(adap->pdev_dev,
3257 "failed to install firmware: %d\n", ret);
3261 /* Installed successfully, update the cached header too. */
3264 *reset = 0; /* already reset as part of load_fw */
3267 if (!card_fw_usable) {
3270 d = be32_to_cpu(drv_fw->fw_ver);
3271 c = be32_to_cpu(card_fw->fw_ver);
3272 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3274 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3276 "driver compiled with %d.%d.%d.%d, "
3277 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3279 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3280 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3281 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3282 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3283 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3284 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3289 /* We're using whatever's on the card and it's known to be good. */
3290 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3291 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3298 * t4_flash_erase_sectors - erase a range of flash sectors
3299 * @adapter: the adapter
3300 * @start: the first sector to erase
3301 * @end: the last sector to erase
3303 * Erases the sectors in the given inclusive range.
3305 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3309 if (end >= adapter->params.sf_nsec)
3312 while (start <= end) {
3313 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3314 (ret = sf1_write(adapter, 4, 0, 1,
3315 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3316 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3317 dev_err(adapter->pdev_dev,
3318 "erase of flash sector %d failed, error %d\n",
3324 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3329 * t4_flash_cfg_addr - return the address of the flash configuration file
3330 * @adapter: the adapter
3332 * Return the address within the flash where the Firmware Configuration
3335 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3337 if (adapter->params.sf_size == 0x100000)
3338 return FLASH_FPGA_CFG_START;
3340 return FLASH_CFG_START;
3343 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3344 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3345 * and emit an error message for mismatched firmware to save our caller the
3348 static bool t4_fw_matches_chip(const struct adapter *adap,
3349 const struct fw_hdr *hdr)
3351 /* The expression below will return FALSE for any unsupported adapter
3352 * which will keep us "honest" in the future ...
3354 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3355 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3356 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3359 dev_err(adap->pdev_dev,
3360 "FW image (%d) is not suitable for this adapter (%d)\n",
3361 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3366 * t4_load_fw - download firmware
3367 * @adap: the adapter
3368 * @fw_data: the firmware image to write
3371 * Write the supplied firmware image to the card's serial flash.
3373 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3378 u8 first_page[SF_PAGE_SIZE];
3379 const __be32 *p = (const __be32 *)fw_data;
3380 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3381 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3382 unsigned int fw_img_start = adap->params.sf_fw_start;
3383 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3386 dev_err(adap->pdev_dev, "FW image has no data\n");
3390 dev_err(adap->pdev_dev,
3391 "FW image size not multiple of 512 bytes\n");
3394 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3395 dev_err(adap->pdev_dev,
3396 "FW image size differs from size in FW header\n");
3399 if (size > FW_MAX_SIZE) {
3400 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3404 if (!t4_fw_matches_chip(adap, hdr))
3407 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3408 csum += be32_to_cpu(p[i]);
3410 if (csum != 0xffffffff) {
3411 dev_err(adap->pdev_dev,
3412 "corrupted firmware image, checksum %#x\n", csum);
3416 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3417 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3422 * We write the correct version at the end so the driver can see a bad
3423 * version if the FW write fails. Start by writing a copy of the
3424 * first page with a bad version.
3426 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3427 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3428 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3432 addr = fw_img_start;
3433 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3434 addr += SF_PAGE_SIZE;
3435 fw_data += SF_PAGE_SIZE;
3436 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3441 ret = t4_write_flash(adap,
3442 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3443 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3446 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3449 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3454 * t4_phy_fw_ver - return current PHY firmware version
3455 * @adap: the adapter
3456 * @phy_fw_ver: return value buffer for PHY firmware version
3458 * Returns the current version of external PHY firmware on the
3461 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3466 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3467 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3468 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3469 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3479 * t4_load_phy_fw - download port PHY firmware
3480 * @adap: the adapter
3481 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3482 * @win_lock: the lock to use to guard the memory copy
3483 * @phy_fw_version: function to check PHY firmware versions
3484 * @phy_fw_data: the PHY firmware image to write
3485 * @phy_fw_size: image size
3487 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3488 * @phy_fw_version is supplied, then it will be used to determine if
3489 * it's necessary to perform the transfer by comparing the version
3490 * of any existing adapter PHY firmware with that of the passed in
3491 * PHY firmware image. If @win_lock is non-NULL then it will be used
3492 * around the call to t4_memory_rw() which transfers the PHY firmware
3495 * A negative error number will be returned if an error occurs. If
3496 * version number support is available and there's no need to upgrade
3497 * the firmware, 0 will be returned. If firmware is successfully
3498 * transferred to the adapter, 1 will be retured.
3500 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3501 * a result, a RESET of the adapter would cause that RAM to lose its
3502 * contents. Thus, loading PHY firmware on such adapters must happen
3503 * after any FW_RESET_CMDs ...
3505 int t4_load_phy_fw(struct adapter *adap,
3506 int win, spinlock_t *win_lock,
3507 int (*phy_fw_version)(const u8 *, size_t),
3508 const u8 *phy_fw_data, size_t phy_fw_size)
3510 unsigned long mtype = 0, maddr = 0;
3512 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3515 /* If we have version number support, then check to see if the adapter
3516 * already has up-to-date PHY firmware loaded.
3518 if (phy_fw_version) {
3519 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3520 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3524 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3525 CH_WARN(adap, "PHY Firmware already up-to-date, "
3526 "version %#x\n", cur_phy_fw_ver);
3531 /* Ask the firmware where it wants us to copy the PHY firmware image.
3532 * The size of the file requires a special version of the READ coommand
3533 * which will pass the file size via the values field in PARAMS_CMD and
3534 * retrieve the return value from firmware and place it in the same
3537 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3538 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3539 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3540 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3542 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3547 maddr = (val & 0xff) << 16;
3549 /* Copy the supplied PHY Firmware image to the adapter memory location
3550 * allocated by the adapter firmware.
3553 spin_lock_bh(win_lock);
3554 ret = t4_memory_rw(adap, win, mtype, maddr,
3555 phy_fw_size, (__be32 *)phy_fw_data,
3558 spin_unlock_bh(win_lock);
3562 /* Tell the firmware that the PHY firmware image has been written to
3563 * RAM and it can now start copying it over to the PHYs. The chip
3564 * firmware will RESET the affected PHYs as part of this operation
3565 * leaving them running the new PHY firmware image.
3567 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3568 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3569 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3570 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3571 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3572 ¶m, &val, 30000);
3574 /* If we have version number support, then check to see that the new
3575 * firmware got loaded properly.
3577 if (phy_fw_version) {
3578 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3582 if (cur_phy_fw_ver != new_phy_fw_vers) {
3583 CH_WARN(adap, "PHY Firmware did not update: "
3584 "version on adapter %#x, "
3585 "version flashed %#x\n",
3586 cur_phy_fw_ver, new_phy_fw_vers);
3595 * t4_fwcache - firmware cache operation
3596 * @adap: the adapter
3597 * @op : the operation (flush or flush and invalidate)
3599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3601 struct fw_params_cmd c;
3603 memset(&c, 0, sizeof(c));
3605 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3606 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3607 FW_PARAMS_CMD_PFN_V(adap->pf) |
3608 FW_PARAMS_CMD_VFN_V(0));
3609 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3611 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3612 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3613 c.param[0].val = (__force __be32)op;
3615 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3619 unsigned int *pif_req_wrptr,
3620 unsigned int *pif_rsp_wrptr)
3623 u32 cfg, val, req, rsp;
3625 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3626 if (cfg & LADBGEN_F)
3627 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3629 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3630 req = POLADBGWRPTR_G(val);
3631 rsp = PILADBGWRPTR_G(val);
3633 *pif_req_wrptr = req;
3635 *pif_rsp_wrptr = rsp;
3637 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3638 for (j = 0; j < 6; j++) {
3639 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3640 PILADBGRDPTR_V(rsp));
3641 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3642 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3646 req = (req + 2) & POLADBGRDPTR_M;
3647 rsp = (rsp + 2) & PILADBGRDPTR_M;
3649 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3652 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3657 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3658 if (cfg & LADBGEN_F)
3659 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3661 for (i = 0; i < CIM_MALA_SIZE; i++) {
3662 for (j = 0; j < 5; j++) {
3664 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3665 PILADBGRDPTR_V(idx));
3666 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3667 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3670 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3673 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3677 for (i = 0; i < 8; i++) {
3678 u32 *p = la_buf + i;
3680 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3681 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3682 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3683 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3684 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3688 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3689 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3690 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3694 * t4_link_l1cfg - apply link configuration to MAC/PHY
3695 * @phy: the PHY to setup
3696 * @mac: the MAC to setup
3697 * @lc: the requested link configuration
3699 * Set up a port's MAC and PHY according to a desired link configuration.
3700 * - If the PHY can auto-negotiate first decide what to advertise, then
3701 * enable/disable auto-negotiation as desired, and reset.
3702 * - If the PHY does not auto-negotiate just reset it.
3703 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3704 * otherwise do it later based on the outcome of auto-negotiation.
3706 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3707 struct link_config *lc)
3709 struct fw_port_cmd c;
3710 unsigned int mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3711 unsigned int fc = 0, fec = 0, fw_fec = 0;
3714 if (lc->requested_fc & PAUSE_RX)
3715 fc |= FW_PORT_CAP_FC_RX;
3716 if (lc->requested_fc & PAUSE_TX)
3717 fc |= FW_PORT_CAP_FC_TX;
3719 fec = lc->requested_fec & FEC_AUTO ? lc->auto_fec : lc->requested_fec;
3722 fw_fec |= FW_PORT_CAP_FEC_RS;
3723 if (fec & FEC_BASER_RS)
3724 fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
3726 memset(&c, 0, sizeof(c));
3727 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3728 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3729 FW_PORT_CMD_PORTID_V(port));
3731 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3734 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3735 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3737 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3738 } else if (lc->autoneg == AUTONEG_DISABLE) {
3739 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
3741 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3743 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc |
3746 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3750 * t4_restart_aneg - restart autonegotiation
3751 * @adap: the adapter
3752 * @mbox: mbox to use for the FW command
3753 * @port: the port id
3755 * Restarts autonegotiation for the selected port.
3757 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3759 struct fw_port_cmd c;
3761 memset(&c, 0, sizeof(c));
3762 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3763 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3764 FW_PORT_CMD_PORTID_V(port));
3766 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3768 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3769 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3772 typedef void (*int_handler_t)(struct adapter *adap);
3775 unsigned int mask; /* bits to check in interrupt status */
3776 const char *msg; /* message to print or NULL */
3777 short stat_idx; /* stat counter to increment or -1 */
3778 unsigned short fatal; /* whether the condition reported is fatal */
3779 int_handler_t int_handler; /* platform-specific int handler */
3783 * t4_handle_intr_status - table driven interrupt handler
3784 * @adapter: the adapter that generated the interrupt
3785 * @reg: the interrupt status register to process
3786 * @acts: table of interrupt actions
3788 * A table driven interrupt handler that applies a set of masks to an
3789 * interrupt status word and performs the corresponding actions if the
3790 * interrupts described by the mask have occurred. The actions include
3791 * optionally emitting a warning or alert message. The table is terminated
3792 * by an entry specifying mask 0. Returns the number of fatal interrupt
3795 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3796 const struct intr_info *acts)
3799 unsigned int mask = 0;
3800 unsigned int status = t4_read_reg(adapter, reg);
3802 for ( ; acts->mask; ++acts) {
3803 if (!(status & acts->mask))
3807 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3808 status & acts->mask);
3809 } else if (acts->msg && printk_ratelimit())
3810 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3811 status & acts->mask);
3812 if (acts->int_handler)
3813 acts->int_handler(adapter);
3817 if (status) /* clear processed interrupts */
3818 t4_write_reg(adapter, reg, status);
3823 * Interrupt handler for the PCIE module.
3825 static void pcie_intr_handler(struct adapter *adapter)
3827 static const struct intr_info sysbus_intr_info[] = {
3828 { RNPP_F, "RXNP array parity error", -1, 1 },
3829 { RPCP_F, "RXPC array parity error", -1, 1 },
3830 { RCIP_F, "RXCIF array parity error", -1, 1 },
3831 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3832 { RFTP_F, "RXFT array parity error", -1, 1 },
3835 static const struct intr_info pcie_port_intr_info[] = {
3836 { TPCP_F, "TXPC array parity error", -1, 1 },
3837 { TNPP_F, "TXNP array parity error", -1, 1 },
3838 { TFTP_F, "TXFT array parity error", -1, 1 },
3839 { TCAP_F, "TXCA array parity error", -1, 1 },
3840 { TCIP_F, "TXCIF array parity error", -1, 1 },
3841 { RCAP_F, "RXCA array parity error", -1, 1 },
3842 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3843 { RDPE_F, "Rx data parity error", -1, 1 },
3844 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3847 static const struct intr_info pcie_intr_info[] = {
3848 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3849 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3850 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3851 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3852 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3853 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3854 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3855 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3856 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3857 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3858 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3859 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3860 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3861 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3862 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3863 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3864 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3865 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3866 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3867 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3868 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3869 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3870 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3871 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3872 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3873 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3874 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3875 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3876 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3877 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3882 static struct intr_info t5_pcie_intr_info[] = {
3883 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3885 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3886 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3887 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3888 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3889 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3890 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3891 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3893 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3895 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3896 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3897 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3898 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3899 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3901 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3902 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3903 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3904 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3905 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3906 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3907 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3908 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3909 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3910 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3911 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3913 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3915 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3916 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3917 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3918 { READRSPERR_F, "Outbound read error", -1, 0 },
3924 if (is_t4(adapter->params.chip))
3925 fat = t4_handle_intr_status(adapter,
3926 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3928 t4_handle_intr_status(adapter,
3929 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3930 pcie_port_intr_info) +
3931 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3934 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3938 t4_fatal_err(adapter);
3942 * TP interrupt handler.
3944 static void tp_intr_handler(struct adapter *adapter)
3946 static const struct intr_info tp_intr_info[] = {
3947 { 0x3fffffff, "TP parity error", -1, 1 },
3948 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3952 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3953 t4_fatal_err(adapter);
3957 * SGE interrupt handler.
3959 static void sge_intr_handler(struct adapter *adapter)
3964 static const struct intr_info sge_intr_info[] = {
3965 { ERR_CPL_EXCEED_IQE_SIZE_F,
3966 "SGE received CPL exceeding IQE size", -1, 1 },
3967 { ERR_INVALID_CIDX_INC_F,
3968 "SGE GTS CIDX increment too large", -1, 0 },
3969 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3970 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3971 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3972 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3973 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3975 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3977 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3979 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3981 { ERR_ING_CTXT_PRIO_F,
3982 "SGE too many priority ingress contexts", -1, 0 },
3983 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3984 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3988 static struct intr_info t4t5_sge_intr_info[] = {
3989 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3990 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3991 { ERR_EGR_CTXT_PRIO_F,
3992 "SGE too many priority egress contexts", -1, 0 },
3996 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3997 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3999 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4000 (unsigned long long)v);
4001 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4002 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4005 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4006 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4007 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4008 t4t5_sge_intr_info);
4010 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4011 if (err & ERROR_QID_VALID_F) {
4012 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4014 if (err & UNCAPTURED_ERROR_F)
4015 dev_err(adapter->pdev_dev,
4016 "SGE UNCAPTURED_ERROR set (clearing)\n");
4017 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4018 UNCAPTURED_ERROR_F);
4022 t4_fatal_err(adapter);
4025 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4026 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4027 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4028 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4031 * CIM interrupt handler.
4033 static void cim_intr_handler(struct adapter *adapter)
4035 static const struct intr_info cim_intr_info[] = {
4036 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4037 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4038 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4039 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4040 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4041 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4042 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4045 static const struct intr_info cim_upintr_info[] = {
4046 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4047 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4048 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4049 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4050 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4051 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4052 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4053 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4054 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4055 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4056 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4057 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4058 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4059 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4060 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4061 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4062 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4063 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4064 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4065 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4066 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4067 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4068 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4069 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4070 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4071 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4072 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4073 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4079 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4080 t4_report_fw_error(adapter);
4082 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4084 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4087 t4_fatal_err(adapter);
4091 * ULP RX interrupt handler.
4093 static void ulprx_intr_handler(struct adapter *adapter)
4095 static const struct intr_info ulprx_intr_info[] = {
4096 { 0x1800000, "ULPRX context error", -1, 1 },
4097 { 0x7fffff, "ULPRX parity error", -1, 1 },
4101 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4102 t4_fatal_err(adapter);
4106 * ULP TX interrupt handler.
4108 static void ulptx_intr_handler(struct adapter *adapter)
4110 static const struct intr_info ulptx_intr_info[] = {
4111 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4113 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4115 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4117 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4119 { 0xfffffff, "ULPTX parity error", -1, 1 },
4123 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4124 t4_fatal_err(adapter);
4128 * PM TX interrupt handler.
4130 static void pmtx_intr_handler(struct adapter *adapter)
4132 static const struct intr_info pmtx_intr_info[] = {
4133 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4134 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4135 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4136 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4137 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4138 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4139 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4141 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4142 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4146 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4147 t4_fatal_err(adapter);
4151 * PM RX interrupt handler.
4153 static void pmrx_intr_handler(struct adapter *adapter)
4155 static const struct intr_info pmrx_intr_info[] = {
4156 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4157 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4158 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4159 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4161 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4162 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4166 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4167 t4_fatal_err(adapter);
4171 * CPL switch interrupt handler.
4173 static void cplsw_intr_handler(struct adapter *adapter)
4175 static const struct intr_info cplsw_intr_info[] = {
4176 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4177 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4178 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4179 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4180 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4181 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4185 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4186 t4_fatal_err(adapter);
4190 * LE interrupt handler.
4192 static void le_intr_handler(struct adapter *adap)
4194 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4195 static const struct intr_info le_intr_info[] = {
4196 { LIPMISS_F, "LE LIP miss", -1, 0 },
4197 { LIP0_F, "LE 0 LIP error", -1, 0 },
4198 { PARITYERR_F, "LE parity error", -1, 1 },
4199 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4200 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4204 static struct intr_info t6_le_intr_info[] = {
4205 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4206 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4207 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4208 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4209 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4213 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4214 (chip <= CHELSIO_T5) ?
4215 le_intr_info : t6_le_intr_info))
4220 * MPS interrupt handler.
4222 static void mps_intr_handler(struct adapter *adapter)
4224 static const struct intr_info mps_rx_intr_info[] = {
4225 { 0xffffff, "MPS Rx parity error", -1, 1 },
4228 static const struct intr_info mps_tx_intr_info[] = {
4229 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4230 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4231 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4233 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4235 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4236 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4237 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4240 static const struct intr_info mps_trc_intr_info[] = {
4241 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4242 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4244 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4247 static const struct intr_info mps_stat_sram_intr_info[] = {
4248 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4251 static const struct intr_info mps_stat_tx_intr_info[] = {
4252 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4255 static const struct intr_info mps_stat_rx_intr_info[] = {
4256 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4259 static const struct intr_info mps_cls_intr_info[] = {
4260 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4261 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4262 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4268 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4270 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4272 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4273 mps_trc_intr_info) +
4274 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4275 mps_stat_sram_intr_info) +
4276 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4277 mps_stat_tx_intr_info) +
4278 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4279 mps_stat_rx_intr_info) +
4280 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4283 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4284 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4286 t4_fatal_err(adapter);
4289 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4293 * EDC/MC interrupt handler.
4295 static void mem_intr_handler(struct adapter *adapter, int idx)
4297 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4299 unsigned int addr, cnt_addr, v;
4301 if (idx <= MEM_EDC1) {
4302 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4303 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4304 } else if (idx == MEM_MC) {
4305 if (is_t4(adapter->params.chip)) {
4306 addr = MC_INT_CAUSE_A;
4307 cnt_addr = MC_ECC_STATUS_A;
4309 addr = MC_P_INT_CAUSE_A;
4310 cnt_addr = MC_P_ECC_STATUS_A;
4313 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4314 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4317 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4318 if (v & PERR_INT_CAUSE_F)
4319 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4321 if (v & ECC_CE_INT_CAUSE_F) {
4322 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4324 t4_edc_err_read(adapter, idx);
4326 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4327 if (printk_ratelimit())
4328 dev_warn(adapter->pdev_dev,
4329 "%u %s correctable ECC data error%s\n",
4330 cnt, name[idx], cnt > 1 ? "s" : "");
4332 if (v & ECC_UE_INT_CAUSE_F)
4333 dev_alert(adapter->pdev_dev,
4334 "%s uncorrectable ECC data error\n", name[idx]);
4336 t4_write_reg(adapter, addr, v);
4337 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4338 t4_fatal_err(adapter);
4342 * MA interrupt handler.
4344 static void ma_intr_handler(struct adapter *adap)
4346 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4348 if (status & MEM_PERR_INT_CAUSE_F) {
4349 dev_alert(adap->pdev_dev,
4350 "MA parity error, parity status %#x\n",
4351 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4352 if (is_t5(adap->params.chip))
4353 dev_alert(adap->pdev_dev,
4354 "MA parity error, parity status %#x\n",
4356 MA_PARITY_ERROR_STATUS2_A));
4358 if (status & MEM_WRAP_INT_CAUSE_F) {
4359 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4360 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4361 "client %u to address %#x\n",
4362 MEM_WRAP_CLIENT_NUM_G(v),
4363 MEM_WRAP_ADDRESS_G(v) << 4);
4365 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4370 * SMB interrupt handler.
4372 static void smb_intr_handler(struct adapter *adap)
4374 static const struct intr_info smb_intr_info[] = {
4375 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4376 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4377 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4381 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4386 * NC-SI interrupt handler.
4388 static void ncsi_intr_handler(struct adapter *adap)
4390 static const struct intr_info ncsi_intr_info[] = {
4391 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4392 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4393 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4394 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4398 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4403 * XGMAC interrupt handler.
4405 static void xgmac_intr_handler(struct adapter *adap, int port)
4407 u32 v, int_cause_reg;
4409 if (is_t4(adap->params.chip))
4410 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4412 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4414 v = t4_read_reg(adap, int_cause_reg);
4416 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4420 if (v & TXFIFO_PRTY_ERR_F)
4421 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4423 if (v & RXFIFO_PRTY_ERR_F)
4424 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4426 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4431 * PL interrupt handler.
4433 static void pl_intr_handler(struct adapter *adap)
4435 static const struct intr_info pl_intr_info[] = {
4436 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4437 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4441 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4445 #define PF_INTR_MASK (PFSW_F)
4446 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4447 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4448 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4451 * t4_slow_intr_handler - control path interrupt handler
4452 * @adapter: the adapter
4454 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4455 * The designation 'slow' is because it involves register reads, while
4456 * data interrupts typically don't involve any MMIOs.
4458 int t4_slow_intr_handler(struct adapter *adapter)
4460 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4462 if (!(cause & GLBL_INTR_MASK))
4465 cim_intr_handler(adapter);
4467 mps_intr_handler(adapter);
4469 ncsi_intr_handler(adapter);
4471 pl_intr_handler(adapter);
4473 smb_intr_handler(adapter);
4474 if (cause & XGMAC0_F)
4475 xgmac_intr_handler(adapter, 0);
4476 if (cause & XGMAC1_F)
4477 xgmac_intr_handler(adapter, 1);
4478 if (cause & XGMAC_KR0_F)
4479 xgmac_intr_handler(adapter, 2);
4480 if (cause & XGMAC_KR1_F)
4481 xgmac_intr_handler(adapter, 3);
4483 pcie_intr_handler(adapter);
4485 mem_intr_handler(adapter, MEM_MC);
4486 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4487 mem_intr_handler(adapter, MEM_MC1);
4489 mem_intr_handler(adapter, MEM_EDC0);
4491 mem_intr_handler(adapter, MEM_EDC1);
4493 le_intr_handler(adapter);
4495 tp_intr_handler(adapter);
4497 ma_intr_handler(adapter);
4498 if (cause & PM_TX_F)
4499 pmtx_intr_handler(adapter);
4500 if (cause & PM_RX_F)
4501 pmrx_intr_handler(adapter);
4502 if (cause & ULP_RX_F)
4503 ulprx_intr_handler(adapter);
4504 if (cause & CPL_SWITCH_F)
4505 cplsw_intr_handler(adapter);
4507 sge_intr_handler(adapter);
4508 if (cause & ULP_TX_F)
4509 ulptx_intr_handler(adapter);
4511 /* Clear the interrupts just processed for which we are the master. */
4512 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4513 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4518 * t4_intr_enable - enable interrupts
4519 * @adapter: the adapter whose interrupts should be enabled
4521 * Enable PF-specific interrupts for the calling function and the top-level
4522 * interrupt concentrator for global interrupts. Interrupts are already
4523 * enabled at each module, here we just enable the roots of the interrupt
4526 * Note: this function should be called only when the driver manages
4527 * non PF-specific interrupts from the various HW modules. Only one PCI
4528 * function at a time should be doing this.
4530 void t4_intr_enable(struct adapter *adapter)
4533 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4534 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4535 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4537 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4538 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4539 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4540 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4541 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4542 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4543 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4544 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4545 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4546 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4547 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4551 * t4_intr_disable - disable interrupts
4552 * @adapter: the adapter whose interrupts should be disabled
4554 * Disable interrupts. We only disable the top-level interrupt
4555 * concentrators. The caller must be a PCI function managing global
4558 void t4_intr_disable(struct adapter *adapter)
4562 if (pci_channel_offline(adapter->pdev))
4565 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4566 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4567 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4569 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4570 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4574 * t4_config_rss_range - configure a portion of the RSS mapping table
4575 * @adapter: the adapter
4576 * @mbox: mbox to use for the FW command
4577 * @viid: virtual interface whose RSS subtable is to be written
4578 * @start: start entry in the table to write
4579 * @n: how many table entries to write
4580 * @rspq: values for the response queue lookup table
4581 * @nrspq: number of values in @rspq
4583 * Programs the selected part of the VI's RSS mapping table with the
4584 * provided values. If @nrspq < @n the supplied values are used repeatedly
4585 * until the full table range is populated.
4587 * The caller must ensure the values in @rspq are in the range allowed for
4590 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4591 int start, int n, const u16 *rspq, unsigned int nrspq)
4594 const u16 *rsp = rspq;
4595 const u16 *rsp_end = rspq + nrspq;
4596 struct fw_rss_ind_tbl_cmd cmd;
4598 memset(&cmd, 0, sizeof(cmd));
4599 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4600 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4601 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4602 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4604 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4606 int nq = min(n, 32);
4607 __be32 *qp = &cmd.iq0_to_iq2;
4609 cmd.niqid = cpu_to_be16(nq);
4610 cmd.startidx = cpu_to_be16(start);
4618 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4619 if (++rsp >= rsp_end)
4621 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4622 if (++rsp >= rsp_end)
4624 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4625 if (++rsp >= rsp_end)
4628 *qp++ = cpu_to_be32(v);
4632 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4640 * t4_config_glbl_rss - configure the global RSS mode
4641 * @adapter: the adapter
4642 * @mbox: mbox to use for the FW command
4643 * @mode: global RSS mode
4644 * @flags: mode-specific flags
4646 * Sets the global RSS mode.
4648 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4651 struct fw_rss_glb_config_cmd c;
4653 memset(&c, 0, sizeof(c));
4654 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4655 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4656 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4657 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4658 c.u.manual.mode_pkd =
4659 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4660 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4661 c.u.basicvirtual.mode_pkd =
4662 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4663 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4666 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4670 * t4_config_vi_rss - configure per VI RSS settings
4671 * @adapter: the adapter
4672 * @mbox: mbox to use for the FW command
4675 * @defq: id of the default RSS queue for the VI.
4677 * Configures VI-specific RSS properties.
4679 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4680 unsigned int flags, unsigned int defq)
4682 struct fw_rss_vi_config_cmd c;
4684 memset(&c, 0, sizeof(c));
4685 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4686 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4687 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4688 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4689 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4690 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4691 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4694 /* Read an RSS table row */
4695 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4697 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4698 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4703 * t4_read_rss - read the contents of the RSS mapping table
4704 * @adapter: the adapter
4705 * @map: holds the contents of the RSS mapping table
4707 * Reads the contents of the RSS hash->queue mapping table.
4709 int t4_read_rss(struct adapter *adapter, u16 *map)
4714 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4715 ret = rd_rss_row(adapter, i, &val);
4718 *map++ = LKPTBLQUEUE0_G(val);
4719 *map++ = LKPTBLQUEUE1_G(val);
4724 static unsigned int t4_use_ldst(struct adapter *adap)
4726 return (adap->flags & FW_OK) || !adap->use_bd;
4730 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4731 * @adap: the adapter
4732 * @vals: where the indirect register values are stored/written
4733 * @nregs: how many indirect registers to read/write
4734 * @start_idx: index of first indirect register to read/write
4735 * @rw: Read (1) or Write (0)
4737 * Access TP PIO registers through LDST
4739 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4740 unsigned int start_index, unsigned int rw)
4743 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4744 struct fw_ldst_cmd c;
4746 for (i = 0 ; i < nregs; i++) {
4747 memset(&c, 0, sizeof(c));
4748 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4750 (rw ? FW_CMD_READ_F :
4752 FW_LDST_CMD_ADDRSPACE_V(cmd));
4753 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4755 c.u.addrval.addr = cpu_to_be32(start_index + i);
4756 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4757 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4759 vals[i] = be32_to_cpu(c.u.addrval.val);
4764 * t4_read_rss_key - read the global RSS key
4765 * @adap: the adapter
4766 * @key: 10-entry array holding the 320-bit RSS key
4768 * Reads the global 320-bit RSS key.
4770 void t4_read_rss_key(struct adapter *adap, u32 *key)
4772 if (t4_use_ldst(adap))
4773 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4775 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4776 TP_RSS_SECRET_KEY0_A);
4780 * t4_write_rss_key - program one of the RSS keys
4781 * @adap: the adapter
4782 * @key: 10-entry array holding the 320-bit RSS key
4783 * @idx: which RSS key to write
4785 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4786 * 0..15 the corresponding entry in the RSS key table is written,
4787 * otherwise the global RSS key is written.
4789 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4791 u8 rss_key_addr_cnt = 16;
4792 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4794 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4795 * allows access to key addresses 16-63 by using KeyWrAddrX
4796 * as index[5:4](upper 2) into key table
4798 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4799 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4800 rss_key_addr_cnt = 32;
4802 if (t4_use_ldst(adap))
4803 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4805 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4806 TP_RSS_SECRET_KEY0_A);
4808 if (idx >= 0 && idx < rss_key_addr_cnt) {
4809 if (rss_key_addr_cnt > 16)
4810 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4811 KEYWRADDRX_V(idx >> 4) |
4812 T6_VFWRADDR_V(idx) | KEYWREN_F);
4814 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4815 KEYWRADDR_V(idx) | KEYWREN_F);
4820 * t4_read_rss_pf_config - read PF RSS Configuration Table
4821 * @adapter: the adapter
4822 * @index: the entry in the PF RSS table to read
4823 * @valp: where to store the returned value
4825 * Reads the PF RSS Configuration Table at the specified index and returns
4826 * the value found there.
4828 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4831 if (t4_use_ldst(adapter))
4832 t4_fw_tp_pio_rw(adapter, valp, 1,
4833 TP_RSS_PF0_CONFIG_A + index, 1);
4835 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4836 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4840 * t4_read_rss_vf_config - read VF RSS Configuration Table
4841 * @adapter: the adapter
4842 * @index: the entry in the VF RSS table to read
4843 * @vfl: where to store the returned VFL
4844 * @vfh: where to store the returned VFH
4846 * Reads the VF RSS Configuration Table at the specified index and returns
4847 * the (VFL, VFH) values found there.
4849 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4852 u32 vrt, mask, data;
4854 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4855 mask = VFWRADDR_V(VFWRADDR_M);
4856 data = VFWRADDR_V(index);
4858 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4859 data = T6_VFWRADDR_V(index);
4862 /* Request that the index'th VF Table values be read into VFL/VFH.
4864 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4865 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4866 vrt |= data | VFRDEN_F;
4867 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4869 /* Grab the VFL/VFH values ...
4871 if (t4_use_ldst(adapter)) {
4872 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4873 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4875 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4876 vfl, 1, TP_RSS_VFL_CONFIG_A);
4877 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4878 vfh, 1, TP_RSS_VFH_CONFIG_A);
4883 * t4_read_rss_pf_map - read PF RSS Map
4884 * @adapter: the adapter
4886 * Reads the PF RSS Map register and returns its value.
4888 u32 t4_read_rss_pf_map(struct adapter *adapter)
4892 if (t4_use_ldst(adapter))
4893 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4895 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4896 &pfmap, 1, TP_RSS_PF_MAP_A);
4901 * t4_read_rss_pf_mask - read PF RSS Mask
4902 * @adapter: the adapter
4904 * Reads the PF RSS Mask register and returns its value.
4906 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4910 if (t4_use_ldst(adapter))
4911 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4913 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4914 &pfmask, 1, TP_RSS_PF_MSK_A);
4919 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4920 * @adap: the adapter
4921 * @v4: holds the TCP/IP counter values
4922 * @v6: holds the TCP/IPv6 counter values
4924 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4925 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4927 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4928 struct tp_tcp_stats *v6)
4930 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4932 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4933 #define STAT(x) val[STAT_IDX(x)]
4934 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4937 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4938 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4939 v4->tcp_out_rsts = STAT(OUT_RST);
4940 v4->tcp_in_segs = STAT64(IN_SEG);
4941 v4->tcp_out_segs = STAT64(OUT_SEG);
4942 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4945 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4946 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4947 v6->tcp_out_rsts = STAT(OUT_RST);
4948 v6->tcp_in_segs = STAT64(IN_SEG);
4949 v6->tcp_out_segs = STAT64(OUT_SEG);
4950 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4958 * t4_tp_get_err_stats - read TP's error MIB counters
4959 * @adap: the adapter
4960 * @st: holds the counter values
4962 * Returns the values of TP's error counters.
4964 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4966 int nchan = adap->params.arch.nchan;
4968 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4969 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4970 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4971 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4972 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4973 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4974 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4975 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4976 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4977 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4978 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4979 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4980 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4981 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4982 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4983 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4985 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4986 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4990 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4991 * @adap: the adapter
4992 * @st: holds the counter values
4994 * Returns the values of TP's CPL counters.
4996 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4998 int nchan = adap->params.arch.nchan;
5000 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5001 nchan, TP_MIB_CPL_IN_REQ_0_A);
5002 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5003 nchan, TP_MIB_CPL_OUT_RSP_0_A);
5008 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5009 * @adap: the adapter
5010 * @st: holds the counter values
5012 * Returns the values of TP's RDMA counters.
5014 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5016 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5017 2, TP_MIB_RQE_DFR_PKT_A);
5021 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5022 * @adap: the adapter
5023 * @idx: the port index
5024 * @st: holds the counter values
5026 * Returns the values of TP's FCoE counters for the selected port.
5028 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5029 struct tp_fcoe_stats *st)
5033 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5034 1, TP_MIB_FCOE_DDP_0_A + idx);
5035 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5036 1, TP_MIB_FCOE_DROP_0_A + idx);
5037 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5038 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5039 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5043 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5044 * @adap: the adapter
5045 * @st: holds the counter values
5047 * Returns the values of TP's counters for non-TCP directly-placed packets.
5049 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5053 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5055 st->frames = val[0];
5057 st->octets = ((u64)val[2] << 32) | val[3];
5061 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5062 * @adap: the adapter
5063 * @mtus: where to store the MTU values
5064 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5066 * Reads the HW path MTU table.
5068 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5073 for (i = 0; i < NMTUS; ++i) {
5074 t4_write_reg(adap, TP_MTU_TABLE_A,
5075 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5076 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5077 mtus[i] = MTUVALUE_G(v);
5079 mtu_log[i] = MTUWIDTH_G(v);
5084 * t4_read_cong_tbl - reads the congestion control table
5085 * @adap: the adapter
5086 * @incr: where to store the alpha values
5088 * Reads the additive increments programmed into the HW congestion
5091 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5093 unsigned int mtu, w;
5095 for (mtu = 0; mtu < NMTUS; ++mtu)
5096 for (w = 0; w < NCCTRL_WIN; ++w) {
5097 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5098 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5099 incr[mtu][w] = (u16)t4_read_reg(adap,
5100 TP_CCTRL_TABLE_A) & 0x1fff;
5105 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5106 * @adap: the adapter
5107 * @addr: the indirect TP register address
5108 * @mask: specifies the field within the register to modify
5109 * @val: new value for the field
5111 * Sets a field of an indirect TP register to the given value.
5113 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5114 unsigned int mask, unsigned int val)
5116 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5117 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5118 t4_write_reg(adap, TP_PIO_DATA_A, val);
5122 * init_cong_ctrl - initialize congestion control parameters
5123 * @a: the alpha values for congestion control
5124 * @b: the beta values for congestion control
5126 * Initialize the congestion control parameters.
5128 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5130 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5155 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5158 b[13] = b[14] = b[15] = b[16] = 3;
5159 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5160 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5165 /* The minimum additive increment value for the congestion control table */
5166 #define CC_MIN_INCR 2U
5169 * t4_load_mtus - write the MTU and congestion control HW tables
5170 * @adap: the adapter
5171 * @mtus: the values for the MTU table
5172 * @alpha: the values for the congestion control alpha parameter
5173 * @beta: the values for the congestion control beta parameter
5175 * Write the HW MTU table with the supplied MTUs and the high-speed
5176 * congestion control table with the supplied alpha, beta, and MTUs.
5177 * We write the two tables together because the additive increments
5178 * depend on the MTUs.
5180 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5181 const unsigned short *alpha, const unsigned short *beta)
5183 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5184 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5185 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5186 28672, 40960, 57344, 81920, 114688, 163840, 229376
5191 for (i = 0; i < NMTUS; ++i) {
5192 unsigned int mtu = mtus[i];
5193 unsigned int log2 = fls(mtu);
5195 if (!(mtu & ((1 << log2) >> 2))) /* round */
5197 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5198 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5200 for (w = 0; w < NCCTRL_WIN; ++w) {
5203 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5206 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5207 (w << 16) | (beta[w] << 13) | inc);
5212 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5213 * clocks. The formula is
5215 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5217 * which is equivalent to
5219 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5221 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5223 u64 v = bytes256 * adap->params.vpd.cclk;
5225 return v * 62 + v / 2;
5229 * t4_get_chan_txrate - get the current per channel Tx rates
5230 * @adap: the adapter
5231 * @nic_rate: rates for NIC traffic
5232 * @ofld_rate: rates for offloaded traffic
5234 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5237 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5241 v = t4_read_reg(adap, TP_TX_TRATE_A);
5242 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5243 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5244 if (adap->params.arch.nchan == NCHAN) {
5245 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5246 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5249 v = t4_read_reg(adap, TP_TX_ORATE_A);
5250 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5251 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5252 if (adap->params.arch.nchan == NCHAN) {
5253 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5254 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5259 * t4_set_trace_filter - configure one of the tracing filters
5260 * @adap: the adapter
5261 * @tp: the desired trace filter parameters
5262 * @idx: which filter to configure
5263 * @enable: whether to enable or disable the filter
5265 * Configures one of the tracing filters available in HW. If @enable is
5266 * %0 @tp is not examined and may be %NULL. The user is responsible to
5267 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5269 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5270 int idx, int enable)
5272 int i, ofst = idx * 4;
5273 u32 data_reg, mask_reg, cfg;
5274 u32 multitrc = TRCMULTIFILTER_F;
5277 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5281 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5282 if (cfg & TRCMULTIFILTER_F) {
5283 /* If multiple tracers are enabled, then maximum
5284 * capture size is 2.5KB (FIFO size of a single channel)
5285 * minus 2 flits for CPL_TRACE_PKT header.
5287 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5290 /* If multiple tracers are disabled, to avoid deadlocks
5291 * maximum packet capture size of 9600 bytes is recommended.
5292 * Also in this mode, only trace0 can be enabled and running.
5295 if (tp->snap_len > 9600 || idx)
5299 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5300 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5301 tp->min_len > TFMINPKTSIZE_M)
5304 /* stop the tracer we'll be changing */
5305 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5307 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5308 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5309 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5311 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5312 t4_write_reg(adap, data_reg, tp->data[i]);
5313 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5315 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5316 TFCAPTUREMAX_V(tp->snap_len) |
5317 TFMINPKTSIZE_V(tp->min_len));
5318 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5319 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5320 (is_t4(adap->params.chip) ?
5321 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5322 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5323 T5_TFINVERTMATCH_V(tp->invert)));
5329 * t4_get_trace_filter - query one of the tracing filters
5330 * @adap: the adapter
5331 * @tp: the current trace filter parameters
5332 * @idx: which trace filter to query
5333 * @enabled: non-zero if the filter is enabled
5335 * Returns the current settings of one of the HW tracing filters.
5337 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5341 int i, ofst = idx * 4;
5342 u32 data_reg, mask_reg;
5344 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5345 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5347 if (is_t4(adap->params.chip)) {
5348 *enabled = !!(ctla & TFEN_F);
5349 tp->port = TFPORT_G(ctla);
5350 tp->invert = !!(ctla & TFINVERTMATCH_F);
5352 *enabled = !!(ctla & T5_TFEN_F);
5353 tp->port = T5_TFPORT_G(ctla);
5354 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5356 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5357 tp->min_len = TFMINPKTSIZE_G(ctlb);
5358 tp->skip_ofst = TFOFFSET_G(ctla);
5359 tp->skip_len = TFLENGTH_G(ctla);
5361 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5362 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5363 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5365 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5366 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5367 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5372 * t4_pmtx_get_stats - returns the HW stats from PMTX
5373 * @adap: the adapter
5374 * @cnt: where to store the count statistics
5375 * @cycles: where to store the cycle statistics
5377 * Returns performance statistics from PMTX.
5379 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5384 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5385 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5386 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5387 if (is_t4(adap->params.chip)) {
5388 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5390 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5391 PM_TX_DBG_DATA_A, data, 2,
5392 PM_TX_DBG_STAT_MSB_A);
5393 cycles[i] = (((u64)data[0] << 32) | data[1]);
5399 * t4_pmrx_get_stats - returns the HW stats from PMRX
5400 * @adap: the adapter
5401 * @cnt: where to store the count statistics
5402 * @cycles: where to store the cycle statistics
5404 * Returns performance statistics from PMRX.
5406 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5411 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5412 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5413 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5414 if (is_t4(adap->params.chip)) {
5415 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5417 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5418 PM_RX_DBG_DATA_A, data, 2,
5419 PM_RX_DBG_STAT_MSB_A);
5420 cycles[i] = (((u64)data[0] << 32) | data[1]);
5426 * t4_get_mps_bg_map - return the buffer groups associated with a port
5427 * @adap: the adapter
5428 * @idx: the port index
5430 * Returns a bitmap indicating which MPS buffer groups are associated
5431 * with the given port. Bit i is set if buffer group i is used by the
5434 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5436 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5439 return idx == 0 ? 0xf : 0;
5440 /* In T6 (which is a 2 port card),
5441 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5442 * For 2 port T4/T5 adapter,
5443 * port 0 is mapped to channel 0 and 1,
5444 * port 1 is mapped to channel 2 and 3.
5447 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5448 return idx < 2 ? (3 << (2 * idx)) : 0;
5453 * t4_get_port_type_description - return Port Type string description
5454 * @port_type: firmware Port Type enumeration
5456 const char *t4_get_port_type_description(enum fw_port_type port_type)
5458 static const char *const port_type_description[] = {
5483 if (port_type < ARRAY_SIZE(port_type_description))
5484 return port_type_description[port_type];
5489 * t4_get_port_stats_offset - collect port stats relative to a previous
5491 * @adap: The adapter
5493 * @stats: Current stats to fill
5494 * @offset: Previous stats snapshot
5496 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5497 struct port_stats *stats,
5498 struct port_stats *offset)
5503 t4_get_port_stats(adap, idx, stats);
5504 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5505 i < (sizeof(struct port_stats) / sizeof(u64));
5511 * t4_get_port_stats - collect port statistics
5512 * @adap: the adapter
5513 * @idx: the port index
5514 * @p: the stats structure to fill
5516 * Collect statistics related to the given port from HW.
5518 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5520 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5521 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5523 #define GET_STAT(name) \
5524 t4_read_reg64(adap, \
5525 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5526 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5527 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5529 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5530 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5531 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5532 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5533 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5534 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5535 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5536 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5537 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5538 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5539 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5540 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5541 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5542 p->tx_drop = GET_STAT(TX_PORT_DROP);
5543 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5544 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5545 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5546 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5547 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5548 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5549 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5550 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5551 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5553 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5554 if (stat_ctl & COUNTPAUSESTATTX_F) {
5555 p->tx_frames -= p->tx_pause;
5556 p->tx_octets -= p->tx_pause * 64;
5558 if (stat_ctl & COUNTPAUSEMCTX_F)
5559 p->tx_mcast_frames -= p->tx_pause;
5561 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5562 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5563 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5564 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5565 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5566 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5567 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5568 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5569 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5570 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5571 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5572 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5573 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5574 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5575 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5576 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5577 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5578 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5579 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5580 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5581 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5582 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5583 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5584 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5585 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5586 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5587 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5589 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5590 if (stat_ctl & COUNTPAUSESTATRX_F) {
5591 p->rx_frames -= p->rx_pause;
5592 p->rx_octets -= p->rx_pause * 64;
5594 if (stat_ctl & COUNTPAUSEMCRX_F)
5595 p->rx_mcast_frames -= p->rx_pause;
5598 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5599 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5600 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5601 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5602 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5603 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5604 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5605 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5612 * t4_get_lb_stats - collect loopback port statistics
5613 * @adap: the adapter
5614 * @idx: the loopback port index
5615 * @p: the stats structure to fill
5617 * Return HW statistics for the given loopback port.
5619 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5621 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5623 #define GET_STAT(name) \
5624 t4_read_reg64(adap, \
5625 (is_t4(adap->params.chip) ? \
5626 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5627 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5628 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5630 p->octets = GET_STAT(BYTES);
5631 p->frames = GET_STAT(FRAMES);
5632 p->bcast_frames = GET_STAT(BCAST);
5633 p->mcast_frames = GET_STAT(MCAST);
5634 p->ucast_frames = GET_STAT(UCAST);
5635 p->error_frames = GET_STAT(ERROR);
5637 p->frames_64 = GET_STAT(64B);
5638 p->frames_65_127 = GET_STAT(65B_127B);
5639 p->frames_128_255 = GET_STAT(128B_255B);
5640 p->frames_256_511 = GET_STAT(256B_511B);
5641 p->frames_512_1023 = GET_STAT(512B_1023B);
5642 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5643 p->frames_1519_max = GET_STAT(1519B_MAX);
5644 p->drop = GET_STAT(DROP_FRAMES);
5646 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5647 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5648 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5649 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5650 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5651 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5652 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5653 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5659 /* t4_mk_filtdelwr - create a delete filter WR
5660 * @ftid: the filter ID
5661 * @wr: the filter work request to populate
5662 * @qid: ingress queue to receive the delete notification
5664 * Creates a filter work request to delete the supplied filter. If @qid is
5665 * negative the delete notification is suppressed.
5667 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5669 memset(wr, 0, sizeof(*wr));
5670 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5671 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5672 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5673 FW_FILTER_WR_NOREPLY_V(qid < 0));
5674 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5676 wr->rx_chan_rx_rpl_iq =
5677 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5680 #define INIT_CMD(var, cmd, rd_wr) do { \
5681 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5682 FW_CMD_REQUEST_F | \
5683 FW_CMD_##rd_wr##_F); \
5684 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5687 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5691 struct fw_ldst_cmd c;
5693 memset(&c, 0, sizeof(c));
5694 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5695 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5699 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5700 c.u.addrval.addr = cpu_to_be32(addr);
5701 c.u.addrval.val = cpu_to_be32(val);
5703 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5707 * t4_mdio_rd - read a PHY register through MDIO
5708 * @adap: the adapter
5709 * @mbox: mailbox to use for the FW command
5710 * @phy_addr: the PHY address
5711 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5712 * @reg: the register to read
5713 * @valp: where to store the value
5715 * Issues a FW command through the given mailbox to read a PHY register.
5717 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5718 unsigned int mmd, unsigned int reg, u16 *valp)
5722 struct fw_ldst_cmd c;
5724 memset(&c, 0, sizeof(c));
5725 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5726 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5727 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5729 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5730 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5731 FW_LDST_CMD_MMD_V(mmd));
5732 c.u.mdio.raddr = cpu_to_be16(reg);
5734 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5736 *valp = be16_to_cpu(c.u.mdio.rval);
5741 * t4_mdio_wr - write a PHY register through MDIO
5742 * @adap: the adapter
5743 * @mbox: mailbox to use for the FW command
5744 * @phy_addr: the PHY address
5745 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5746 * @reg: the register to write
5747 * @valp: value to write
5749 * Issues a FW command through the given mailbox to write a PHY register.
5751 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5752 unsigned int mmd, unsigned int reg, u16 val)
5755 struct fw_ldst_cmd c;
5757 memset(&c, 0, sizeof(c));
5758 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5759 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5760 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5762 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5763 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5764 FW_LDST_CMD_MMD_V(mmd));
5765 c.u.mdio.raddr = cpu_to_be16(reg);
5766 c.u.mdio.rval = cpu_to_be16(val);
5768 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5772 * t4_sge_decode_idma_state - decode the idma state
5773 * @adap: the adapter
5774 * @state: the state idma is stuck in
5776 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5778 static const char * const t4_decode[] = {
5780 "IDMA_PUSH_MORE_CPL_FIFO",
5781 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5783 "IDMA_PHYSADDR_SEND_PCIEHDR",
5784 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5785 "IDMA_PHYSADDR_SEND_PAYLOAD",
5786 "IDMA_SEND_FIFO_TO_IMSG",
5787 "IDMA_FL_REQ_DATA_FL_PREP",
5788 "IDMA_FL_REQ_DATA_FL",
5790 "IDMA_FL_H_REQ_HEADER_FL",
5791 "IDMA_FL_H_SEND_PCIEHDR",
5792 "IDMA_FL_H_PUSH_CPL_FIFO",
5793 "IDMA_FL_H_SEND_CPL",
5794 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5795 "IDMA_FL_H_SEND_IP_HDR",
5796 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5797 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5798 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5799 "IDMA_FL_D_SEND_PCIEHDR",
5800 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5801 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5802 "IDMA_FL_SEND_PCIEHDR",
5803 "IDMA_FL_PUSH_CPL_FIFO",
5805 "IDMA_FL_SEND_PAYLOAD_FIRST",
5806 "IDMA_FL_SEND_PAYLOAD",
5807 "IDMA_FL_REQ_NEXT_DATA_FL",
5808 "IDMA_FL_SEND_NEXT_PCIEHDR",
5809 "IDMA_FL_SEND_PADDING",
5810 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5811 "IDMA_FL_SEND_FIFO_TO_IMSG",
5812 "IDMA_FL_REQ_DATAFL_DONE",
5813 "IDMA_FL_REQ_HEADERFL_DONE",
5815 static const char * const t5_decode[] = {
5818 "IDMA_PUSH_MORE_CPL_FIFO",
5819 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5820 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5821 "IDMA_PHYSADDR_SEND_PCIEHDR",
5822 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5823 "IDMA_PHYSADDR_SEND_PAYLOAD",
5824 "IDMA_SEND_FIFO_TO_IMSG",
5825 "IDMA_FL_REQ_DATA_FL",
5827 "IDMA_FL_DROP_SEND_INC",
5828 "IDMA_FL_H_REQ_HEADER_FL",
5829 "IDMA_FL_H_SEND_PCIEHDR",
5830 "IDMA_FL_H_PUSH_CPL_FIFO",
5831 "IDMA_FL_H_SEND_CPL",
5832 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5833 "IDMA_FL_H_SEND_IP_HDR",
5834 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5835 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5836 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5837 "IDMA_FL_D_SEND_PCIEHDR",
5838 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5839 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5840 "IDMA_FL_SEND_PCIEHDR",
5841 "IDMA_FL_PUSH_CPL_FIFO",
5843 "IDMA_FL_SEND_PAYLOAD_FIRST",
5844 "IDMA_FL_SEND_PAYLOAD",
5845 "IDMA_FL_REQ_NEXT_DATA_FL",
5846 "IDMA_FL_SEND_NEXT_PCIEHDR",
5847 "IDMA_FL_SEND_PADDING",
5848 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5850 static const char * const t6_decode[] = {
5852 "IDMA_PUSH_MORE_CPL_FIFO",
5853 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5854 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5855 "IDMA_PHYSADDR_SEND_PCIEHDR",
5856 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5857 "IDMA_PHYSADDR_SEND_PAYLOAD",
5858 "IDMA_FL_REQ_DATA_FL",
5860 "IDMA_FL_DROP_SEND_INC",
5861 "IDMA_FL_H_REQ_HEADER_FL",
5862 "IDMA_FL_H_SEND_PCIEHDR",
5863 "IDMA_FL_H_PUSH_CPL_FIFO",
5864 "IDMA_FL_H_SEND_CPL",
5865 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5866 "IDMA_FL_H_SEND_IP_HDR",
5867 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5868 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5869 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5870 "IDMA_FL_D_SEND_PCIEHDR",
5871 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5872 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5873 "IDMA_FL_SEND_PCIEHDR",
5874 "IDMA_FL_PUSH_CPL_FIFO",
5876 "IDMA_FL_SEND_PAYLOAD_FIRST",
5877 "IDMA_FL_SEND_PAYLOAD",
5878 "IDMA_FL_REQ_NEXT_DATA_FL",
5879 "IDMA_FL_SEND_NEXT_PCIEHDR",
5880 "IDMA_FL_SEND_PADDING",
5881 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5883 static const u32 sge_regs[] = {
5884 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5885 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5886 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5888 const char **sge_idma_decode;
5889 int sge_idma_decode_nstates;
5891 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5893 /* Select the right set of decode strings to dump depending on the
5894 * adapter chip type.
5896 switch (chip_version) {
5898 sge_idma_decode = (const char **)t4_decode;
5899 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5903 sge_idma_decode = (const char **)t5_decode;
5904 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5908 sge_idma_decode = (const char **)t6_decode;
5909 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5913 dev_err(adapter->pdev_dev,
5914 "Unsupported chip version %d\n", chip_version);
5918 if (is_t4(adapter->params.chip)) {
5919 sge_idma_decode = (const char **)t4_decode;
5920 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5922 sge_idma_decode = (const char **)t5_decode;
5923 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5926 if (state < sge_idma_decode_nstates)
5927 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5929 CH_WARN(adapter, "idma state %d unknown\n", state);
5931 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5932 CH_WARN(adapter, "SGE register %#x value %#x\n",
5933 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5937 * t4_sge_ctxt_flush - flush the SGE context cache
5938 * @adap: the adapter
5939 * @mbox: mailbox to use for the FW command
5941 * Issues a FW command through the given mailbox to flush the
5942 * SGE context cache.
5944 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5948 struct fw_ldst_cmd c;
5950 memset(&c, 0, sizeof(c));
5951 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5952 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5953 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5955 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5956 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5958 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5963 * t4_fw_hello - establish communication with FW
5964 * @adap: the adapter
5965 * @mbox: mailbox to use for the FW command
5966 * @evt_mbox: mailbox to receive async FW events
5967 * @master: specifies the caller's willingness to be the device master
5968 * @state: returns the current device state (if non-NULL)
5970 * Issues a command to establish communication with FW. Returns either
5971 * an error (negative integer) or the mailbox of the Master PF.
5973 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5974 enum dev_master master, enum dev_state *state)
5977 struct fw_hello_cmd c;
5979 unsigned int master_mbox;
5980 int retries = FW_CMD_HELLO_RETRIES;
5983 memset(&c, 0, sizeof(c));
5984 INIT_CMD(c, HELLO, WRITE);
5985 c.err_to_clearinit = cpu_to_be32(
5986 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5987 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5988 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5989 mbox : FW_HELLO_CMD_MBMASTER_M) |
5990 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5991 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5992 FW_HELLO_CMD_CLEARINIT_F);
5995 * Issue the HELLO command to the firmware. If it's not successful
5996 * but indicates that we got a "busy" or "timeout" condition, retry
5997 * the HELLO until we exhaust our retry limit. If we do exceed our
5998 * retry limit, check to see if the firmware left us any error
5999 * information and report that if so.
6001 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6003 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6005 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6006 t4_report_fw_error(adap);
6010 v = be32_to_cpu(c.err_to_clearinit);
6011 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6013 if (v & FW_HELLO_CMD_ERR_F)
6014 *state = DEV_STATE_ERR;
6015 else if (v & FW_HELLO_CMD_INIT_F)
6016 *state = DEV_STATE_INIT;
6018 *state = DEV_STATE_UNINIT;
6022 * If we're not the Master PF then we need to wait around for the
6023 * Master PF Driver to finish setting up the adapter.
6025 * Note that we also do this wait if we're a non-Master-capable PF and
6026 * there is no current Master PF; a Master PF may show up momentarily
6027 * and we wouldn't want to fail pointlessly. (This can happen when an
6028 * OS loads lots of different drivers rapidly at the same time). In
6029 * this case, the Master PF returned by the firmware will be
6030 * PCIE_FW_MASTER_M so the test below will work ...
6032 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6033 master_mbox != mbox) {
6034 int waiting = FW_CMD_HELLO_TIMEOUT;
6037 * Wait for the firmware to either indicate an error or
6038 * initialized state. If we see either of these we bail out
6039 * and report the issue to the caller. If we exhaust the
6040 * "hello timeout" and we haven't exhausted our retries, try
6041 * again. Otherwise bail with a timeout error.
6050 * If neither Error nor Initialialized are indicated
6051 * by the firmware keep waiting till we exaust our
6052 * timeout ... and then retry if we haven't exhausted
6055 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6056 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6067 * We either have an Error or Initialized condition
6068 * report errors preferentially.
6071 if (pcie_fw & PCIE_FW_ERR_F)
6072 *state = DEV_STATE_ERR;
6073 else if (pcie_fw & PCIE_FW_INIT_F)
6074 *state = DEV_STATE_INIT;
6078 * If we arrived before a Master PF was selected and
6079 * there's not a valid Master PF, grab its identity
6082 if (master_mbox == PCIE_FW_MASTER_M &&
6083 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6084 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6093 * t4_fw_bye - end communication with FW
6094 * @adap: the adapter
6095 * @mbox: mailbox to use for the FW command
6097 * Issues a command to terminate communication with FW.
6099 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6101 struct fw_bye_cmd c;
6103 memset(&c, 0, sizeof(c));
6104 INIT_CMD(c, BYE, WRITE);
6105 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6109 * t4_init_cmd - ask FW to initialize the device
6110 * @adap: the adapter
6111 * @mbox: mailbox to use for the FW command
6113 * Issues a command to FW to partially initialize the device. This
6114 * performs initialization that generally doesn't depend on user input.
6116 int t4_early_init(struct adapter *adap, unsigned int mbox)
6118 struct fw_initialize_cmd c;
6120 memset(&c, 0, sizeof(c));
6121 INIT_CMD(c, INITIALIZE, WRITE);
6122 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6126 * t4_fw_reset - issue a reset to FW
6127 * @adap: the adapter
6128 * @mbox: mailbox to use for the FW command
6129 * @reset: specifies the type of reset to perform
6131 * Issues a reset command of the specified type to FW.
6133 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6135 struct fw_reset_cmd c;
6137 memset(&c, 0, sizeof(c));
6138 INIT_CMD(c, RESET, WRITE);
6139 c.val = cpu_to_be32(reset);
6140 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6144 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6145 * @adap: the adapter
6146 * @mbox: mailbox to use for the FW RESET command (if desired)
6147 * @force: force uP into RESET even if FW RESET command fails
6149 * Issues a RESET command to firmware (if desired) with a HALT indication
6150 * and then puts the microprocessor into RESET state. The RESET command
6151 * will only be issued if a legitimate mailbox is provided (mbox <=
6152 * PCIE_FW_MASTER_M).
6154 * This is generally used in order for the host to safely manipulate the
6155 * adapter without fear of conflicting with whatever the firmware might
6156 * be doing. The only way out of this state is to RESTART the firmware
6159 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6164 * If a legitimate mailbox is provided, issue a RESET command
6165 * with a HALT indication.
6167 if (mbox <= PCIE_FW_MASTER_M) {
6168 struct fw_reset_cmd c;
6170 memset(&c, 0, sizeof(c));
6171 INIT_CMD(c, RESET, WRITE);
6172 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6173 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6174 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6178 * Normally we won't complete the operation if the firmware RESET
6179 * command fails but if our caller insists we'll go ahead and put the
6180 * uP into RESET. This can be useful if the firmware is hung or even
6181 * missing ... We'll have to take the risk of putting the uP into
6182 * RESET without the cooperation of firmware in that case.
6184 * We also force the firmware's HALT flag to be on in case we bypassed
6185 * the firmware RESET command above or we're dealing with old firmware
6186 * which doesn't have the HALT capability. This will serve as a flag
6187 * for the incoming firmware to know that it's coming out of a HALT
6188 * rather than a RESET ... if it's new enough to understand that ...
6190 if (ret == 0 || force) {
6191 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6192 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6197 * And we always return the result of the firmware RESET command
6198 * even when we force the uP into RESET ...
6204 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6205 * @adap: the adapter
6206 * @reset: if we want to do a RESET to restart things
6208 * Restart firmware previously halted by t4_fw_halt(). On successful
6209 * return the previous PF Master remains as the new PF Master and there
6210 * is no need to issue a new HELLO command, etc.
6212 * We do this in two ways:
6214 * 1. If we're dealing with newer firmware we'll simply want to take
6215 * the chip's microprocessor out of RESET. This will cause the
6216 * firmware to start up from its start vector. And then we'll loop
6217 * until the firmware indicates it's started again (PCIE_FW.HALT
6218 * reset to 0) or we timeout.
6220 * 2. If we're dealing with older firmware then we'll need to RESET
6221 * the chip since older firmware won't recognize the PCIE_FW.HALT
6222 * flag and automatically RESET itself on startup.
6224 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6228 * Since we're directing the RESET instead of the firmware
6229 * doing it automatically, we need to clear the PCIE_FW.HALT
6232 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6235 * If we've been given a valid mailbox, first try to get the
6236 * firmware to do the RESET. If that works, great and we can
6237 * return success. Otherwise, if we haven't been given a
6238 * valid mailbox or the RESET command failed, fall back to
6239 * hitting the chip with a hammer.
6241 if (mbox <= PCIE_FW_MASTER_M) {
6242 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6244 if (t4_fw_reset(adap, mbox,
6245 PIORST_F | PIORSTMODE_F) == 0)
6249 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6254 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6255 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6256 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6267 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6268 * @adap: the adapter
6269 * @mbox: mailbox to use for the FW RESET command (if desired)
6270 * @fw_data: the firmware image to write
6272 * @force: force upgrade even if firmware doesn't cooperate
6274 * Perform all of the steps necessary for upgrading an adapter's
6275 * firmware image. Normally this requires the cooperation of the
6276 * existing firmware in order to halt all existing activities
6277 * but if an invalid mailbox token is passed in we skip that step
6278 * (though we'll still put the adapter microprocessor into RESET in
6281 * On successful return the new firmware will have been loaded and
6282 * the adapter will have been fully RESET losing all previous setup
6283 * state. On unsuccessful return the adapter may be completely hosed ...
6284 * positive errno indicates that the adapter is ~probably~ intact, a
6285 * negative errno indicates that things are looking bad ...
6287 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6288 const u8 *fw_data, unsigned int size, int force)
6290 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6293 if (!t4_fw_matches_chip(adap, fw_hdr))
6296 ret = t4_fw_halt(adap, mbox, force);
6297 if (ret < 0 && !force)
6300 ret = t4_load_fw(adap, fw_data, size);
6305 * Older versions of the firmware don't understand the new
6306 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6307 * restart. So for newly loaded older firmware we'll have to do the
6308 * RESET for it so it starts up on a clean slate. We can tell if
6309 * the newly loaded firmware will handle this right by checking
6310 * its header flags to see if it advertises the capability.
6312 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6313 return t4_fw_restart(adap, mbox, reset);
6317 * t4_fl_pkt_align - return the fl packet alignment
6318 * @adap: the adapter
6320 * T4 has a single field to specify the packing and padding boundary.
6321 * T5 onwards has separate fields for this and hence the alignment for
6322 * next packet offset is maximum of these two.
6325 int t4_fl_pkt_align(struct adapter *adap)
6327 u32 sge_control, sge_control2;
6328 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6330 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6332 /* T4 uses a single control field to specify both the PCIe Padding and
6333 * Packing Boundary. T5 introduced the ability to specify these
6334 * separately. The actual Ingress Packet Data alignment boundary
6335 * within Packed Buffer Mode is the maximum of these two
6336 * specifications. (Note that it makes no real practical sense to
6337 * have the Pading Boudary be larger than the Packing Boundary but you
6338 * could set the chip up that way and, in fact, legacy T4 code would
6339 * end doing this because it would initialize the Padding Boundary and
6340 * leave the Packing Boundary initialized to 0 (16 bytes).)
6341 * Padding Boundary values in T6 starts from 8B,
6342 * where as it is 32B for T4 and T5.
6344 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6345 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6347 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6349 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6351 fl_align = ingpadboundary;
6352 if (!is_t4(adap->params.chip)) {
6353 /* T5 has a weird interpretation of one of the PCIe Packing
6354 * Boundary values. No idea why ...
6356 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6357 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6358 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6359 ingpackboundary = 16;
6361 ingpackboundary = 1 << (ingpackboundary +
6362 INGPACKBOUNDARY_SHIFT_X);
6364 fl_align = max(ingpadboundary, ingpackboundary);
6370 * t4_fixup_host_params - fix up host-dependent parameters
6371 * @adap: the adapter
6372 * @page_size: the host's Base Page Size
6373 * @cache_line_size: the host's Cache Line Size
6375 * Various registers in T4 contain values which are dependent on the
6376 * host's Base Page and Cache Line Sizes. This function will fix all of
6377 * those registers with the appropriate values as passed in ...
6379 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6380 unsigned int cache_line_size)
6382 unsigned int page_shift = fls(page_size) - 1;
6383 unsigned int sge_hps = page_shift - 10;
6384 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6385 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6386 unsigned int fl_align_log = fls(fl_align) - 1;
6388 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6389 HOSTPAGESIZEPF0_V(sge_hps) |
6390 HOSTPAGESIZEPF1_V(sge_hps) |
6391 HOSTPAGESIZEPF2_V(sge_hps) |
6392 HOSTPAGESIZEPF3_V(sge_hps) |
6393 HOSTPAGESIZEPF4_V(sge_hps) |
6394 HOSTPAGESIZEPF5_V(sge_hps) |
6395 HOSTPAGESIZEPF6_V(sge_hps) |
6396 HOSTPAGESIZEPF7_V(sge_hps));
6398 if (is_t4(adap->params.chip)) {
6399 t4_set_reg_field(adap, SGE_CONTROL_A,
6400 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6401 EGRSTATUSPAGESIZE_F,
6402 INGPADBOUNDARY_V(fl_align_log -
6403 INGPADBOUNDARY_SHIFT_X) |
6404 EGRSTATUSPAGESIZE_V(stat_len != 64));
6406 unsigned int pack_align;
6407 unsigned int ingpad, ingpack;
6408 unsigned int pcie_cap;
6410 /* T5 introduced the separation of the Free List Padding and
6411 * Packing Boundaries. Thus, we can select a smaller Padding
6412 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6413 * Bandwidth, and use a Packing Boundary which is large enough
6414 * to avoid false sharing between CPUs, etc.
6416 * For the PCI Link, the smaller the Padding Boundary the
6417 * better. For the Memory Controller, a smaller Padding
6418 * Boundary is better until we cross under the Memory Line
6419 * Size (the minimum unit of transfer to/from Memory). If we
6420 * have a Padding Boundary which is smaller than the Memory
6421 * Line Size, that'll involve a Read-Modify-Write cycle on the
6422 * Memory Controller which is never good.
6425 /* We want the Packing Boundary to be based on the Cache Line
6426 * Size in order to help avoid False Sharing performance
6427 * issues between CPUs, etc. We also want the Packing
6428 * Boundary to incorporate the PCI-E Maximum Payload Size. We
6429 * get best performance when the Packing Boundary is a
6430 * multiple of the Maximum Payload Size.
6432 pack_align = fl_align;
6433 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6435 unsigned int mps, mps_log;
6438 /* The PCIe Device Control Maximum Payload Size field
6439 * [bits 7:5] encodes sizes as powers of 2 starting at
6442 pci_read_config_word(adap->pdev,
6443 pcie_cap + PCI_EXP_DEVCTL,
6445 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6447 if (mps > pack_align)
6451 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6452 * value for the Packing Boundary. This corresponds to 16
6453 * bytes instead of the expected 32 bytes. So if we want 32
6454 * bytes, the best we can really do is 64 bytes ...
6456 if (pack_align <= 16) {
6457 ingpack = INGPACKBOUNDARY_16B_X;
6459 } else if (pack_align == 32) {
6460 ingpack = INGPACKBOUNDARY_64B_X;
6463 unsigned int pack_align_log = fls(pack_align) - 1;
6465 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6466 fl_align = pack_align;
6469 /* Use the smallest Ingress Padding which isn't smaller than
6470 * the Memory Controller Read/Write Size. We'll take that as
6471 * being 8 bytes since we don't know of any system with a
6472 * wider Memory Controller Bus Width.
6474 if (is_t5(adap->params.chip))
6475 ingpad = INGPADBOUNDARY_32B_X;
6477 ingpad = T6_INGPADBOUNDARY_8B_X;
6479 t4_set_reg_field(adap, SGE_CONTROL_A,
6480 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6481 EGRSTATUSPAGESIZE_F,
6482 INGPADBOUNDARY_V(ingpad) |
6483 EGRSTATUSPAGESIZE_V(stat_len != 64));
6484 t4_set_reg_field(adap, SGE_CONTROL2_A,
6485 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6486 INGPACKBOUNDARY_V(ingpack));
6489 * Adjust various SGE Free List Host Buffer Sizes.
6491 * This is something of a crock since we're using fixed indices into
6492 * the array which are also known by the sge.c code and the T4
6493 * Firmware Configuration File. We need to come up with a much better
6494 * approach to managing this array. For now, the first four entries
6499 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6500 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6502 * For the single-MTU buffers in unpacked mode we need to include
6503 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6504 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6505 * Padding boundary. All of these are accommodated in the Factory
6506 * Default Firmware Configuration File but we need to adjust it for
6507 * this host's cache line size.
6509 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6510 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6511 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6513 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6514 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6517 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6523 * t4_fw_initialize - ask FW to initialize the device
6524 * @adap: the adapter
6525 * @mbox: mailbox to use for the FW command
6527 * Issues a command to FW to partially initialize the device. This
6528 * performs initialization that generally doesn't depend on user input.
6530 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6532 struct fw_initialize_cmd c;
6534 memset(&c, 0, sizeof(c));
6535 INIT_CMD(c, INITIALIZE, WRITE);
6536 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6540 * t4_query_params_rw - query FW or device parameters
6541 * @adap: the adapter
6542 * @mbox: mailbox to use for the FW command
6545 * @nparams: the number of parameters
6546 * @params: the parameter names
6547 * @val: the parameter values
6548 * @rw: Write and read flag
6550 * Reads the value of FW or device parameters. Up to 7 parameters can be
6553 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6554 unsigned int vf, unsigned int nparams, const u32 *params,
6558 struct fw_params_cmd c;
6559 __be32 *p = &c.param[0].mnem;
6564 memset(&c, 0, sizeof(c));
6565 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6566 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6567 FW_PARAMS_CMD_PFN_V(pf) |
6568 FW_PARAMS_CMD_VFN_V(vf));
6569 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6571 for (i = 0; i < nparams; i++) {
6572 *p++ = cpu_to_be32(*params++);
6574 *p = cpu_to_be32(*(val + i));
6578 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6580 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6581 *val++ = be32_to_cpu(*p);
6585 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6586 unsigned int vf, unsigned int nparams, const u32 *params,
6589 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6593 * t4_set_params_timeout - sets FW or device parameters
6594 * @adap: the adapter
6595 * @mbox: mailbox to use for the FW command
6598 * @nparams: the number of parameters
6599 * @params: the parameter names
6600 * @val: the parameter values
6601 * @timeout: the timeout time
6603 * Sets the value of FW or device parameters. Up to 7 parameters can be
6604 * specified at once.
6606 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6607 unsigned int pf, unsigned int vf,
6608 unsigned int nparams, const u32 *params,
6609 const u32 *val, int timeout)
6611 struct fw_params_cmd c;
6612 __be32 *p = &c.param[0].mnem;
6617 memset(&c, 0, sizeof(c));
6618 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6619 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6620 FW_PARAMS_CMD_PFN_V(pf) |
6621 FW_PARAMS_CMD_VFN_V(vf));
6622 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6625 *p++ = cpu_to_be32(*params++);
6626 *p++ = cpu_to_be32(*val++);
6629 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6633 * t4_set_params - sets FW or device parameters
6634 * @adap: the adapter
6635 * @mbox: mailbox to use for the FW command
6638 * @nparams: the number of parameters
6639 * @params: the parameter names
6640 * @val: the parameter values
6642 * Sets the value of FW or device parameters. Up to 7 parameters can be
6643 * specified at once.
6645 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6646 unsigned int vf, unsigned int nparams, const u32 *params,
6649 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6650 FW_CMD_MAX_TIMEOUT);
6654 * t4_cfg_pfvf - configure PF/VF resource limits
6655 * @adap: the adapter
6656 * @mbox: mailbox to use for the FW command
6657 * @pf: the PF being configured
6658 * @vf: the VF being configured
6659 * @txq: the max number of egress queues
6660 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6661 * @rxqi: the max number of interrupt-capable ingress queues
6662 * @rxq: the max number of interruptless ingress queues
6663 * @tc: the PCI traffic class
6664 * @vi: the max number of virtual interfaces
6665 * @cmask: the channel access rights mask for the PF/VF
6666 * @pmask: the port access rights mask for the PF/VF
6667 * @nexact: the maximum number of exact MPS filters
6668 * @rcaps: read capabilities
6669 * @wxcaps: write/execute capabilities
6671 * Configures resource limits and capabilities for a physical or virtual
6674 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6675 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6676 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6677 unsigned int vi, unsigned int cmask, unsigned int pmask,
6678 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6680 struct fw_pfvf_cmd c;
6682 memset(&c, 0, sizeof(c));
6683 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6684 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6685 FW_PFVF_CMD_VFN_V(vf));
6686 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6687 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6688 FW_PFVF_CMD_NIQ_V(rxq));
6689 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6690 FW_PFVF_CMD_PMASK_V(pmask) |
6691 FW_PFVF_CMD_NEQ_V(txq));
6692 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6693 FW_PFVF_CMD_NVI_V(vi) |
6694 FW_PFVF_CMD_NEXACTF_V(nexact));
6695 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6696 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6697 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6698 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6702 * t4_alloc_vi - allocate a virtual interface
6703 * @adap: the adapter
6704 * @mbox: mailbox to use for the FW command
6705 * @port: physical port associated with the VI
6706 * @pf: the PF owning the VI
6707 * @vf: the VF owning the VI
6708 * @nmac: number of MAC addresses needed (1 to 5)
6709 * @mac: the MAC addresses of the VI
6710 * @rss_size: size of RSS table slice associated with this VI
6712 * Allocates a virtual interface for the given physical port. If @mac is
6713 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6714 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6715 * stored consecutively so the space needed is @nmac * 6 bytes.
6716 * Returns a negative error number or the non-negative VI id.
6718 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6719 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6720 unsigned int *rss_size)
6725 memset(&c, 0, sizeof(c));
6726 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6727 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6728 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6729 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6730 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6733 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6738 memcpy(mac, c.mac, sizeof(c.mac));
6741 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6743 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6745 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6747 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6751 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6752 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6756 * t4_free_vi - free a virtual interface
6757 * @adap: the adapter
6758 * @mbox: mailbox to use for the FW command
6759 * @pf: the PF owning the VI
6760 * @vf: the VF owning the VI
6761 * @viid: virtual interface identifiler
6763 * Free a previously allocated virtual interface.
6765 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6766 unsigned int vf, unsigned int viid)
6770 memset(&c, 0, sizeof(c));
6771 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6774 FW_VI_CMD_PFN_V(pf) |
6775 FW_VI_CMD_VFN_V(vf));
6776 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6777 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6779 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6783 * t4_set_rxmode - set Rx properties of a virtual interface
6784 * @adap: the adapter
6785 * @mbox: mailbox to use for the FW command
6787 * @mtu: the new MTU or -1
6788 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6789 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6790 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6791 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6792 * @sleep_ok: if true we may sleep while awaiting command completion
6794 * Sets Rx properties of a virtual interface.
6796 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6797 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6800 struct fw_vi_rxmode_cmd c;
6802 /* convert to FW values */
6804 mtu = FW_RXMODE_MTU_NO_CHG;
6806 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6808 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6810 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6812 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6814 memset(&c, 0, sizeof(c));
6815 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6816 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6817 FW_VI_RXMODE_CMD_VIID_V(viid));
6818 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6820 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6821 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6822 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6823 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6824 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6825 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6829 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6830 * @adap: the adapter
6831 * @mbox: mailbox to use for the FW command
6833 * @free: if true any existing filters for this VI id are first removed
6834 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6835 * @addr: the MAC address(es)
6836 * @idx: where to store the index of each allocated filter
6837 * @hash: pointer to hash address filter bitmap
6838 * @sleep_ok: call is allowed to sleep
6840 * Allocates an exact-match filter for each of the supplied addresses and
6841 * sets it to the corresponding address. If @idx is not %NULL it should
6842 * have at least @naddr entries, each of which will be set to the index of
6843 * the filter allocated for the corresponding MAC address. If a filter
6844 * could not be allocated for an address its index is set to 0xffff.
6845 * If @hash is not %NULL addresses that fail to allocate an exact filter
6846 * are hashed and update the hash filter bitmap pointed at by @hash.
6848 * Returns a negative error number or the number of filters allocated.
6850 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6851 unsigned int viid, bool free, unsigned int naddr,
6852 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6854 int offset, ret = 0;
6855 struct fw_vi_mac_cmd c;
6856 unsigned int nfilters = 0;
6857 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6858 unsigned int rem = naddr;
6860 if (naddr > max_naddr)
6863 for (offset = 0; offset < naddr ; /**/) {
6864 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6865 rem : ARRAY_SIZE(c.u.exact));
6866 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6867 u.exact[fw_naddr]), 16);
6868 struct fw_vi_mac_exact *p;
6871 memset(&c, 0, sizeof(c));
6872 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6875 FW_CMD_EXEC_V(free) |
6876 FW_VI_MAC_CMD_VIID_V(viid));
6877 c.freemacs_to_len16 =
6878 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6879 FW_CMD_LEN16_V(len16));
6881 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6883 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6884 FW_VI_MAC_CMD_IDX_V(
6885 FW_VI_MAC_ADD_MAC));
6886 memcpy(p->macaddr, addr[offset + i],
6887 sizeof(p->macaddr));
6890 /* It's okay if we run out of space in our MAC address arena.
6891 * Some of the addresses we submit may get stored so we need
6892 * to run through the reply to see what the results were ...
6894 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6895 if (ret && ret != -FW_ENOMEM)
6898 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6899 u16 index = FW_VI_MAC_CMD_IDX_G(
6900 be16_to_cpu(p->valid_to_idx));
6903 idx[offset + i] = (index >= max_naddr ?
6905 if (index < max_naddr)
6909 hash_mac_addr(addr[offset + i]));
6917 if (ret == 0 || ret == -FW_ENOMEM)
6923 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6924 * @adap: the adapter
6925 * @mbox: mailbox to use for the FW command
6927 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6928 * @addr: the MAC address(es)
6929 * @sleep_ok: call is allowed to sleep
6931 * Frees the exact-match filter for each of the supplied addresses
6933 * Returns a negative error number or the number of filters freed.
6935 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6936 unsigned int viid, unsigned int naddr,
6937 const u8 **addr, bool sleep_ok)
6939 int offset, ret = 0;
6940 struct fw_vi_mac_cmd c;
6941 unsigned int nfilters = 0;
6942 unsigned int max_naddr = is_t4(adap->params.chip) ?
6943 NUM_MPS_CLS_SRAM_L_INSTANCES :
6944 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6945 unsigned int rem = naddr;
6947 if (naddr > max_naddr)
6950 for (offset = 0; offset < (int)naddr ; /**/) {
6951 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6953 : ARRAY_SIZE(c.u.exact));
6954 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6955 u.exact[fw_naddr]), 16);
6956 struct fw_vi_mac_exact *p;
6959 memset(&c, 0, sizeof(c));
6960 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6964 FW_VI_MAC_CMD_VIID_V(viid));
6965 c.freemacs_to_len16 =
6966 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6967 FW_CMD_LEN16_V(len16));
6969 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6970 p->valid_to_idx = cpu_to_be16(
6971 FW_VI_MAC_CMD_VALID_F |
6972 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6973 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6976 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6980 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6981 u16 index = FW_VI_MAC_CMD_IDX_G(
6982 be16_to_cpu(p->valid_to_idx));
6984 if (index < max_naddr)
6998 * t4_change_mac - modifies the exact-match filter for a MAC address
6999 * @adap: the adapter
7000 * @mbox: mailbox to use for the FW command
7002 * @idx: index of existing filter for old value of MAC address, or -1
7003 * @addr: the new MAC address value
7004 * @persist: whether a new MAC allocation should be persistent
7005 * @add_smt: if true also add the address to the HW SMT
7007 * Modifies an exact-match filter and sets it to the new MAC address.
7008 * Note that in general it is not possible to modify the value of a given
7009 * filter so the generic way to modify an address filter is to free the one
7010 * being used by the old address value and allocate a new filter for the
7011 * new address value. @idx can be -1 if the address is a new addition.
7013 * Returns a negative error number or the index of the filter with the new
7016 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7017 int idx, const u8 *addr, bool persist, bool add_smt)
7020 struct fw_vi_mac_cmd c;
7021 struct fw_vi_mac_exact *p = c.u.exact;
7022 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7024 if (idx < 0) /* new allocation */
7025 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7026 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7028 memset(&c, 0, sizeof(c));
7029 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7030 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7031 FW_VI_MAC_CMD_VIID_V(viid));
7032 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7033 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7034 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7035 FW_VI_MAC_CMD_IDX_V(idx));
7036 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7038 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7040 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7041 if (ret >= max_mac_addr)
7048 * t4_set_addr_hash - program the MAC inexact-match hash filter
7049 * @adap: the adapter
7050 * @mbox: mailbox to use for the FW command
7052 * @ucast: whether the hash filter should also match unicast addresses
7053 * @vec: the value to be written to the hash filter
7054 * @sleep_ok: call is allowed to sleep
7056 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7058 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7059 bool ucast, u64 vec, bool sleep_ok)
7061 struct fw_vi_mac_cmd c;
7063 memset(&c, 0, sizeof(c));
7064 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7065 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7066 FW_VI_ENABLE_CMD_VIID_V(viid));
7067 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7068 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7070 c.u.hash.hashvec = cpu_to_be64(vec);
7071 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7075 * t4_enable_vi_params - enable/disable a virtual interface
7076 * @adap: the adapter
7077 * @mbox: mailbox to use for the FW command
7079 * @rx_en: 1=enable Rx, 0=disable Rx
7080 * @tx_en: 1=enable Tx, 0=disable Tx
7081 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7083 * Enables/disables a virtual interface. Note that setting DCB Enable
7084 * only makes sense when enabling a Virtual Interface ...
7086 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7087 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7089 struct fw_vi_enable_cmd c;
7091 memset(&c, 0, sizeof(c));
7092 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7093 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7094 FW_VI_ENABLE_CMD_VIID_V(viid));
7095 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7096 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7097 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7099 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7103 * t4_enable_vi - enable/disable a virtual interface
7104 * @adap: the adapter
7105 * @mbox: mailbox to use for the FW command
7107 * @rx_en: 1=enable Rx, 0=disable Rx
7108 * @tx_en: 1=enable Tx, 0=disable Tx
7110 * Enables/disables a virtual interface.
7112 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7113 bool rx_en, bool tx_en)
7115 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7119 * t4_identify_port - identify a VI's port by blinking its LED
7120 * @adap: the adapter
7121 * @mbox: mailbox to use for the FW command
7123 * @nblinks: how many times to blink LED at 2.5 Hz
7125 * Identifies a VI's port by blinking its LED.
7127 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7128 unsigned int nblinks)
7130 struct fw_vi_enable_cmd c;
7132 memset(&c, 0, sizeof(c));
7133 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7134 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7135 FW_VI_ENABLE_CMD_VIID_V(viid));
7136 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7137 c.blinkdur = cpu_to_be16(nblinks);
7138 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7142 * t4_iq_stop - stop an ingress queue and its FLs
7143 * @adap: the adapter
7144 * @mbox: mailbox to use for the FW command
7145 * @pf: the PF owning the queues
7146 * @vf: the VF owning the queues
7147 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7148 * @iqid: ingress queue id
7149 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7150 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7152 * Stops an ingress queue and its associated FLs, if any. This causes
7153 * any current or future data/messages destined for these queues to be
7156 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7157 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7158 unsigned int fl0id, unsigned int fl1id)
7162 memset(&c, 0, sizeof(c));
7163 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7164 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7165 FW_IQ_CMD_VFN_V(vf));
7166 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7167 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7168 c.iqid = cpu_to_be16(iqid);
7169 c.fl0id = cpu_to_be16(fl0id);
7170 c.fl1id = cpu_to_be16(fl1id);
7171 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7175 * t4_iq_free - free an ingress queue and its FLs
7176 * @adap: the adapter
7177 * @mbox: mailbox to use for the FW command
7178 * @pf: the PF owning the queues
7179 * @vf: the VF owning the queues
7180 * @iqtype: the ingress queue type
7181 * @iqid: ingress queue id
7182 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7183 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7185 * Frees an ingress queue and its associated FLs, if any.
7187 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7188 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7189 unsigned int fl0id, unsigned int fl1id)
7193 memset(&c, 0, sizeof(c));
7194 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7195 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7196 FW_IQ_CMD_VFN_V(vf));
7197 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7198 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7199 c.iqid = cpu_to_be16(iqid);
7200 c.fl0id = cpu_to_be16(fl0id);
7201 c.fl1id = cpu_to_be16(fl1id);
7202 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7206 * t4_eth_eq_free - free an Ethernet egress queue
7207 * @adap: the adapter
7208 * @mbox: mailbox to use for the FW command
7209 * @pf: the PF owning the queue
7210 * @vf: the VF owning the queue
7211 * @eqid: egress queue id
7213 * Frees an Ethernet egress queue.
7215 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7216 unsigned int vf, unsigned int eqid)
7218 struct fw_eq_eth_cmd c;
7220 memset(&c, 0, sizeof(c));
7221 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7222 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7223 FW_EQ_ETH_CMD_PFN_V(pf) |
7224 FW_EQ_ETH_CMD_VFN_V(vf));
7225 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7226 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7227 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7231 * t4_ctrl_eq_free - free a control egress queue
7232 * @adap: the adapter
7233 * @mbox: mailbox to use for the FW command
7234 * @pf: the PF owning the queue
7235 * @vf: the VF owning the queue
7236 * @eqid: egress queue id
7238 * Frees a control egress queue.
7240 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7241 unsigned int vf, unsigned int eqid)
7243 struct fw_eq_ctrl_cmd c;
7245 memset(&c, 0, sizeof(c));
7246 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7247 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7248 FW_EQ_CTRL_CMD_PFN_V(pf) |
7249 FW_EQ_CTRL_CMD_VFN_V(vf));
7250 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7251 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7252 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7256 * t4_ofld_eq_free - free an offload egress queue
7257 * @adap: the adapter
7258 * @mbox: mailbox to use for the FW command
7259 * @pf: the PF owning the queue
7260 * @vf: the VF owning the queue
7261 * @eqid: egress queue id
7263 * Frees a control egress queue.
7265 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7266 unsigned int vf, unsigned int eqid)
7268 struct fw_eq_ofld_cmd c;
7270 memset(&c, 0, sizeof(c));
7271 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7272 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7273 FW_EQ_OFLD_CMD_PFN_V(pf) |
7274 FW_EQ_OFLD_CMD_VFN_V(vf));
7275 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7276 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7277 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7281 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7282 * @adap: the adapter
7283 * @link_down_rc: Link Down Reason Code
7285 * Returns a string representation of the Link Down Reason Code.
7287 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7289 static const char * const reason[] = {
7292 "Auto-negotiation Failure",
7294 "Insufficient Airflow",
7295 "Unable To Determine Reason",
7296 "No RX Signal Detected",
7300 if (link_down_rc >= ARRAY_SIZE(reason))
7301 return "Bad Reason Code";
7303 return reason[link_down_rc];
7307 * t4_handle_get_port_info - process a FW reply message
7308 * @pi: the port info
7309 * @rpl: start of the FW message
7311 * Processes a GET_PORT_INFO FW reply message.
7313 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7315 const struct fw_port_cmd *p = (const void *)rpl;
7316 struct adapter *adap = pi->adapter;
7318 /* link/module state change message */
7319 int speed = 0, fc = 0;
7320 struct link_config *lc;
7321 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7322 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7323 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7325 if (stat & FW_PORT_CMD_RXPAUSE_F)
7327 if (stat & FW_PORT_CMD_TXPAUSE_F)
7329 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7331 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7333 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7335 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7337 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7339 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7344 if (mod != pi->mod_type) {
7346 t4_os_portmod_changed(adap, pi->port_id);
7348 if (link_ok != lc->link_ok || speed != lc->speed ||
7349 fc != lc->fc) { /* something changed */
7350 if (!link_ok && lc->link_ok) {
7351 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7353 lc->link_down_rc = rc;
7354 dev_warn(adap->pdev_dev,
7355 "Port %d link down, reason: %s\n",
7356 pi->port_id, t4_link_down_rc_str(rc));
7358 lc->link_ok = link_ok;
7361 lc->supported = be16_to_cpu(p->u.info.pcap);
7362 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7363 t4_os_link_changed(adap, pi->port_id, link_ok);
7368 * t4_handle_fw_rpl - process a FW reply message
7369 * @adap: the adapter
7370 * @rpl: start of the FW message
7372 * Processes a FW message, such as link state change messages.
7374 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7376 u8 opcode = *(const u8 *)rpl;
7378 /* This might be a port command ... this simplifies the following
7379 * conditionals ... We can get away with pre-dereferencing
7380 * action_to_len16 because it's in the first 16 bytes and all messages
7381 * will be at least that long.
7383 const struct fw_port_cmd *p = (const void *)rpl;
7384 unsigned int action =
7385 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7387 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7389 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7390 struct port_info *pi = NULL;
7392 for_each_port(adap, i) {
7393 pi = adap2pinfo(adap, i);
7394 if (pi->tx_chan == chan)
7398 t4_handle_get_port_info(pi, rpl);
7400 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7406 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7410 if (pci_is_pcie(adapter->pdev)) {
7411 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7412 p->speed = val & PCI_EXP_LNKSTA_CLS;
7413 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7418 * init_link_config - initialize a link's SW state
7419 * @lc: structure holding the link state
7420 * @caps: link capabilities
7422 * Initializes the SW state maintained for each link, including the link's
7423 * capabilities and default speed/flow-control/autonegotiation settings.
7425 static void init_link_config(struct link_config *lc, unsigned int pcaps,
7428 lc->supported = pcaps;
7429 lc->lp_advertising = 0;
7430 lc->requested_speed = 0;
7432 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7435 /* For Forward Error Control, we default to whatever the Firmware
7436 * tells us the Link is currently advertising.
7438 if (acaps & FW_PORT_CAP_FEC_RS)
7439 lc->auto_fec |= FEC_RS;
7440 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
7441 lc->auto_fec |= FEC_BASER_RS;
7442 lc->requested_fec = FEC_AUTO;
7443 lc->fec = lc->auto_fec;
7445 if (lc->supported & FW_PORT_CAP_ANEG) {
7446 lc->advertising = lc->supported & ADVERT_MASK;
7447 lc->autoneg = AUTONEG_ENABLE;
7448 lc->requested_fc |= PAUSE_AUTONEG;
7450 lc->advertising = 0;
7451 lc->autoneg = AUTONEG_DISABLE;
7455 #define CIM_PF_NOACCESS 0xeeeeeeee
7457 int t4_wait_dev_ready(void __iomem *regs)
7461 whoami = readl(regs + PL_WHOAMI_A);
7462 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7466 whoami = readl(regs + PL_WHOAMI_A);
7467 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7471 u32 vendor_and_model_id;
7475 static int get_flash_params(struct adapter *adap)
7477 /* Table for non-Numonix supported flash parts. Numonix parts are left
7478 * to the preexisting code. All flash parts have 64KB sectors.
7480 static struct flash_desc supported_flash[] = {
7481 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7487 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7489 ret = sf1_read(adap, 3, 0, 1, &info);
7490 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7494 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7495 if (supported_flash[ret].vendor_and_model_id == info) {
7496 adap->params.sf_size = supported_flash[ret].size_mb;
7497 adap->params.sf_nsec =
7498 adap->params.sf_size / SF_SEC_SIZE;
7502 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7504 info >>= 16; /* log2 of size */
7505 if (info >= 0x14 && info < 0x18)
7506 adap->params.sf_nsec = 1 << (info - 16);
7507 else if (info == 0x18)
7508 adap->params.sf_nsec = 64;
7511 adap->params.sf_size = 1 << info;
7512 adap->params.sf_fw_start =
7513 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7515 if (adap->params.sf_size < FLASH_MIN_SIZE)
7516 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7517 adap->params.sf_size, FLASH_MIN_SIZE);
7521 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7526 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7528 pci_read_config_word(adapter->pdev,
7529 pcie_cap + PCI_EXP_DEVCTL2, &val);
7530 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7532 pci_write_config_word(adapter->pdev,
7533 pcie_cap + PCI_EXP_DEVCTL2, val);
7538 * t4_prep_adapter - prepare SW and HW for operation
7539 * @adapter: the adapter
7540 * @reset: if true perform a HW reset
7542 * Initialize adapter SW state for the various HW modules, set initial
7543 * values for some adapter tunables, take PHYs out of reset, and
7544 * initialize the MDIO interface.
7546 int t4_prep_adapter(struct adapter *adapter)
7552 get_pci_mode(adapter, &adapter->params.pci);
7553 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7555 ret = get_flash_params(adapter);
7557 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7561 /* Retrieve adapter's device ID
7563 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7564 ver = device_id >> 12;
7565 adapter->params.chip = 0;
7568 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7569 adapter->params.arch.sge_fl_db = DBPRIO_F;
7570 adapter->params.arch.mps_tcam_size =
7571 NUM_MPS_CLS_SRAM_L_INSTANCES;
7572 adapter->params.arch.mps_rplc_size = 128;
7573 adapter->params.arch.nchan = NCHAN;
7574 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7575 adapter->params.arch.vfcount = 128;
7576 /* Congestion map is for 4 channels so that
7577 * MPS can have 4 priority per port.
7579 adapter->params.arch.cng_ch_bits_log = 2;
7582 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7583 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7584 adapter->params.arch.mps_tcam_size =
7585 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7586 adapter->params.arch.mps_rplc_size = 128;
7587 adapter->params.arch.nchan = NCHAN;
7588 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7589 adapter->params.arch.vfcount = 128;
7590 adapter->params.arch.cng_ch_bits_log = 2;
7593 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7594 adapter->params.arch.sge_fl_db = 0;
7595 adapter->params.arch.mps_tcam_size =
7596 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7597 adapter->params.arch.mps_rplc_size = 256;
7598 adapter->params.arch.nchan = 2;
7599 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7600 adapter->params.arch.vfcount = 256;
7601 /* Congestion map will be for 2 channels so that
7602 * MPS can have 8 priority per port.
7604 adapter->params.arch.cng_ch_bits_log = 3;
7607 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7612 adapter->params.cim_la_size = CIMLA_SIZE;
7613 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7616 * Default port for debugging in case we can't reach FW.
7618 adapter->params.nports = 1;
7619 adapter->params.portvec = 1;
7620 adapter->params.vpd.cclk = 50000;
7622 /* Set pci completion timeout value to 4 seconds. */
7623 set_pcie_completion_timeout(adapter, 0xd);
7628 * t4_shutdown_adapter - shut down adapter, host & wire
7629 * @adapter: the adapter
7631 * Perform an emergency shutdown of the adapter and stop it from
7632 * continuing any further communication on the ports or DMA to the
7633 * host. This is typically used when the adapter and/or firmware
7634 * have crashed and we want to prevent any further accidental
7635 * communication with the rest of the world. This will also force
7636 * the port Link Status to go down -- if register writes work --
7637 * which should help our peers figure out that we're down.
7639 int t4_shutdown_adapter(struct adapter *adapter)
7643 t4_intr_disable(adapter);
7644 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
7645 for_each_port(adapter, port) {
7646 u32 a_port_cfg = PORT_REG(port,
7647 is_t4(adapter->params.chip)
7651 t4_write_reg(adapter, a_port_cfg,
7652 t4_read_reg(adapter, a_port_cfg)
7653 & ~SIGNAL_DET_V(1));
7655 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
7661 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7662 * @adapter: the adapter
7663 * @qid: the Queue ID
7664 * @qtype: the Ingress or Egress type for @qid
7665 * @user: true if this request is for a user mode queue
7666 * @pbar2_qoffset: BAR2 Queue Offset
7667 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7669 * Returns the BAR2 SGE Queue Registers information associated with the
7670 * indicated Absolute Queue ID. These are passed back in return value
7671 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7672 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7674 * This may return an error which indicates that BAR2 SGE Queue
7675 * registers aren't available. If an error is not returned, then the
7676 * following values are returned:
7678 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7679 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7681 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7682 * require the "Inferred Queue ID" ability may be used. E.g. the
7683 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7684 * then these "Inferred Queue ID" register may not be used.
7686 int t4_bar2_sge_qregs(struct adapter *adapter,
7688 enum t4_bar2_qtype qtype,
7691 unsigned int *pbar2_qid)
7693 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7694 u64 bar2_page_offset, bar2_qoffset;
7695 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7697 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7698 if (!user && is_t4(adapter->params.chip))
7701 /* Get our SGE Page Size parameters.
7703 page_shift = adapter->params.sge.hps + 10;
7704 page_size = 1 << page_shift;
7706 /* Get the right Queues per Page parameters for our Queue.
7708 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7709 ? adapter->params.sge.eq_qpp
7710 : adapter->params.sge.iq_qpp);
7711 qpp_mask = (1 << qpp_shift) - 1;
7713 /* Calculate the basics of the BAR2 SGE Queue register area:
7714 * o The BAR2 page the Queue registers will be in.
7715 * o The BAR2 Queue ID.
7716 * o The BAR2 Queue ID Offset into the BAR2 page.
7718 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7719 bar2_qid = qid & qpp_mask;
7720 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7722 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7723 * hardware will infer the Absolute Queue ID simply from the writes to
7724 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7725 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7726 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7727 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7728 * from the BAR2 Page and BAR2 Queue ID.
7730 * One important censequence of this is that some BAR2 SGE registers
7731 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7732 * there. But other registers synthesize the SGE Queue ID purely
7733 * from the writes to the registers -- the Write Combined Doorbell
7734 * Buffer is a good example. These BAR2 SGE Registers are only
7735 * available for those BAR2 SGE Register areas where the SGE Absolute
7736 * Queue ID can be inferred from simple writes.
7738 bar2_qoffset = bar2_page_offset;
7739 bar2_qinferred = (bar2_qid_offset < page_size);
7740 if (bar2_qinferred) {
7741 bar2_qoffset += bar2_qid_offset;
7745 *pbar2_qoffset = bar2_qoffset;
7746 *pbar2_qid = bar2_qid;
7751 * t4_init_devlog_params - initialize adapter->params.devlog
7752 * @adap: the adapter
7754 * Initialize various fields of the adapter's Firmware Device Log
7755 * Parameters structure.
7757 int t4_init_devlog_params(struct adapter *adap)
7759 struct devlog_params *dparams = &adap->params.devlog;
7761 unsigned int devlog_meminfo;
7762 struct fw_devlog_cmd devlog_cmd;
7765 /* If we're dealing with newer firmware, the Device Log Paramerters
7766 * are stored in a designated register which allows us to access the
7767 * Device Log even if we can't talk to the firmware.
7770 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7772 unsigned int nentries, nentries128;
7774 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7775 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7777 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7778 nentries = (nentries128 + 1) * 128;
7779 dparams->size = nentries * sizeof(struct fw_devlog_e);
7784 /* Otherwise, ask the firmware for it's Device Log Parameters.
7786 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7787 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7788 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7789 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7790 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7796 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7797 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7798 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7799 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7805 * t4_init_sge_params - initialize adap->params.sge
7806 * @adapter: the adapter
7808 * Initialize various fields of the adapter's SGE Parameters structure.
7810 int t4_init_sge_params(struct adapter *adapter)
7812 struct sge_params *sge_params = &adapter->params.sge;
7814 unsigned int s_hps, s_qpp;
7816 /* Extract the SGE Page Size for our PF.
7818 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7819 s_hps = (HOSTPAGESIZEPF0_S +
7820 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7821 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7823 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7825 s_qpp = (QUEUESPERPAGEPF0_S +
7826 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7827 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7828 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7829 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7830 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7836 * t4_init_tp_params - initialize adap->params.tp
7837 * @adap: the adapter
7839 * Initialize various fields of the adapter's TP Parameters structure.
7841 int t4_init_tp_params(struct adapter *adap)
7846 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7847 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7848 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7850 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7851 for (chan = 0; chan < NCHAN; chan++)
7852 adap->params.tp.tx_modq[chan] = chan;
7854 /* Cache the adapter's Compressed Filter Mode and global Incress
7857 if (t4_use_ldst(adap)) {
7858 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7859 TP_VLAN_PRI_MAP_A, 1);
7860 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7861 TP_INGRESS_CONFIG_A, 1);
7863 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7864 &adap->params.tp.vlan_pri_map, 1,
7866 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7867 &adap->params.tp.ingress_config, 1,
7868 TP_INGRESS_CONFIG_A);
7870 /* For T6, cache the adapter's compressed error vector
7871 * and passing outer header info for encapsulated packets.
7873 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
7874 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
7875 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
7878 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7879 * shift positions of several elements of the Compressed Filter Tuple
7880 * for this adapter which we need frequently ...
7882 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7883 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7884 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7885 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7888 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7889 * represents the presence of an Outer VLAN instead of a VNIC ID.
7891 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7892 adap->params.tp.vnic_shift = -1;
7898 * t4_filter_field_shift - calculate filter field shift
7899 * @adap: the adapter
7900 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7902 * Return the shift position of a filter field within the Compressed
7903 * Filter Tuple. The filter field is specified via its selection bit
7904 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7906 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7908 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7912 if ((filter_mode & filter_sel) == 0)
7915 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7916 switch (filter_mode & sel) {
7918 field_shift += FT_FCOE_W;
7921 field_shift += FT_PORT_W;
7924 field_shift += FT_VNIC_ID_W;
7927 field_shift += FT_VLAN_W;
7930 field_shift += FT_TOS_W;
7933 field_shift += FT_PROTOCOL_W;
7936 field_shift += FT_ETHERTYPE_W;
7939 field_shift += FT_MACMATCH_W;
7942 field_shift += FT_MPSHITTYPE_W;
7944 case FRAGMENTATION_F:
7945 field_shift += FT_FRAGMENTATION_W;
7952 int t4_init_rss_mode(struct adapter *adap, int mbox)
7955 struct fw_rss_vi_config_cmd rvc;
7957 memset(&rvc, 0, sizeof(rvc));
7959 for_each_port(adap, i) {
7960 struct port_info *p = adap2pinfo(adap, i);
7963 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7964 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7965 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7966 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7967 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7970 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7976 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7977 * @pi: the port_info
7978 * @mbox: mailbox to use for the FW command
7979 * @port: physical port associated with the VI
7980 * @pf: the PF owning the VI
7981 * @vf: the VF owning the VI
7982 * @mac: the MAC address of the VI
7984 * Allocates a virtual interface for the given physical port. If @mac is
7985 * not %NULL it contains the MAC address of the VI as assigned by FW.
7986 * @mac should be large enough to hold an Ethernet address.
7987 * Returns < 0 on error.
7989 int t4_init_portinfo(struct port_info *pi, int mbox,
7990 int port, int pf, int vf, u8 mac[])
7993 struct fw_port_cmd c;
7994 unsigned int rss_size;
7996 memset(&c, 0, sizeof(c));
7997 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7998 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7999 FW_PORT_CMD_PORTID_V(port));
8000 c.action_to_len16 = cpu_to_be32(
8001 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
8003 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
8007 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8014 pi->rss_size = rss_size;
8016 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8017 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
8018 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
8019 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
8020 pi->mod_type = FW_PORT_MOD_TYPE_NA;
8022 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
8023 be16_to_cpu(c.u.info.acap));
8027 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8032 for_each_port(adap, i) {
8033 struct port_info *pi = adap2pinfo(adap, i);
8035 while ((adap->params.portvec & (1 << j)) == 0)
8038 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8042 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8049 * t4_read_cimq_cfg - read CIM queue configuration
8050 * @adap: the adapter
8051 * @base: holds the queue base addresses in bytes
8052 * @size: holds the queue sizes in bytes
8053 * @thres: holds the queue full thresholds in bytes
8055 * Returns the current configuration of the CIM queues, starting with
8056 * the IBQs, then the OBQs.
8058 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8061 int cim_num_obq = is_t4(adap->params.chip) ?
8062 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8064 for (i = 0; i < CIM_NUM_IBQ; i++) {
8065 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8067 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8068 /* value is in 256-byte units */
8069 *base++ = CIMQBASE_G(v) * 256;
8070 *size++ = CIMQSIZE_G(v) * 256;
8071 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8073 for (i = 0; i < cim_num_obq; i++) {
8074 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8076 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8077 /* value is in 256-byte units */
8078 *base++ = CIMQBASE_G(v) * 256;
8079 *size++ = CIMQSIZE_G(v) * 256;
8084 * t4_read_cim_ibq - read the contents of a CIM inbound queue
8085 * @adap: the adapter
8086 * @qid: the queue index
8087 * @data: where to store the queue contents
8088 * @n: capacity of @data in 32-bit words
8090 * Reads the contents of the selected CIM queue starting at address 0 up
8091 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8092 * error and the number of 32-bit words actually read on success.
8094 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8096 int i, err, attempts;
8098 const unsigned int nwords = CIM_IBQ_SIZE * 4;
8100 if (qid > 5 || (n & 3))
8103 addr = qid * nwords;
8107 /* It might take 3-10ms before the IBQ debug read access is allowed.
8108 * Wait for 1 Sec with a delay of 1 usec.
8112 for (i = 0; i < n; i++, addr++) {
8113 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8115 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8119 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8121 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8126 * t4_read_cim_obq - read the contents of a CIM outbound queue
8127 * @adap: the adapter
8128 * @qid: the queue index
8129 * @data: where to store the queue contents
8130 * @n: capacity of @data in 32-bit words
8132 * Reads the contents of the selected CIM queue starting at address 0 up
8133 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8134 * error and the number of 32-bit words actually read on success.
8136 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8139 unsigned int addr, v, nwords;
8140 int cim_num_obq = is_t4(adap->params.chip) ?
8141 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8143 if ((qid > (cim_num_obq - 1)) || (n & 3))
8146 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8147 QUENUMSELECT_V(qid));
8148 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8150 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
8151 nwords = CIMQSIZE_G(v) * 64; /* same */
8155 for (i = 0; i < n; i++, addr++) {
8156 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8158 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8162 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8164 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8169 * t4_cim_read - read a block from CIM internal address space
8170 * @adap: the adapter
8171 * @addr: the start address within the CIM address space
8172 * @n: number of words to read
8173 * @valp: where to store the result
8175 * Reads a block of 4-byte words from the CIM intenal address space.
8177 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8182 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8185 for ( ; !ret && n--; addr += 4) {
8186 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8187 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8190 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8196 * t4_cim_write - write a block into CIM internal address space
8197 * @adap: the adapter
8198 * @addr: the start address within the CIM address space
8199 * @n: number of words to write
8200 * @valp: set of values to write
8202 * Writes a block of 4-byte words into the CIM intenal address space.
8204 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8205 const unsigned int *valp)
8209 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8212 for ( ; !ret && n--; addr += 4) {
8213 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8214 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8215 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8221 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8224 return t4_cim_write(adap, addr, 1, &val);
8228 * t4_cim_read_la - read CIM LA capture buffer
8229 * @adap: the adapter
8230 * @la_buf: where to store the LA data
8231 * @wrptr: the HW write pointer within the capture buffer
8233 * Reads the contents of the CIM LA buffer with the most recent entry at
8234 * the end of the returned data and with the entry at @wrptr first.
8235 * We try to leave the LA in the running state we find it in.
8237 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8240 unsigned int cfg, val, idx;
8242 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8246 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8247 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8252 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8256 idx = UPDBGLAWRPTR_G(val);
8260 for (i = 0; i < adap->params.cim_la_size; i++) {
8261 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8262 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8265 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8268 if (val & UPDBGLARDEN_F) {
8272 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8275 idx = (idx + 1) & UPDBGLARDPTR_M;
8278 if (cfg & UPDBGLAEN_F) {
8279 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8280 cfg & ~UPDBGLARDEN_F);
8288 * t4_tp_read_la - read TP LA capture buffer
8289 * @adap: the adapter
8290 * @la_buf: where to store the LA data
8291 * @wrptr: the HW write pointer within the capture buffer
8293 * Reads the contents of the TP LA buffer with the most recent entry at
8294 * the end of the returned data and with the entry at @wrptr first.
8295 * We leave the LA in the running state we find it in.
8297 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8299 bool last_incomplete;
8300 unsigned int i, cfg, val, idx;
8302 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8303 if (cfg & DBGLAENABLE_F) /* freeze LA */
8304 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8305 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8307 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8308 idx = DBGLAWPTR_G(val);
8309 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8310 if (last_incomplete)
8311 idx = (idx + 1) & DBGLARPTR_M;
8316 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8317 val |= adap->params.tp.la_mask;
8319 for (i = 0; i < TPLA_SIZE; i++) {
8320 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8321 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8322 idx = (idx + 1) & DBGLARPTR_M;
8325 /* Wipe out last entry if it isn't valid */
8326 if (last_incomplete)
8327 la_buf[TPLA_SIZE - 1] = ~0ULL;
8329 if (cfg & DBGLAENABLE_F) /* restore running state */
8330 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8331 cfg | adap->params.tp.la_mask);
8334 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8335 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8336 * state for more than the Warning Threshold then we'll issue a warning about
8337 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8338 * appears to be hung every Warning Repeat second till the situation clears.
8339 * If the situation clears, we'll note that as well.
8341 #define SGE_IDMA_WARN_THRESH 1
8342 #define SGE_IDMA_WARN_REPEAT 300
8345 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8346 * @adapter: the adapter
8347 * @idma: the adapter IDMA Monitor state
8349 * Initialize the state of an SGE Ingress DMA Monitor.
8351 void t4_idma_monitor_init(struct adapter *adapter,
8352 struct sge_idma_monitor_state *idma)
8354 /* Initialize the state variables for detecting an SGE Ingress DMA
8355 * hang. The SGE has internal counters which count up on each clock
8356 * tick whenever the SGE finds its Ingress DMA State Engines in the
8357 * same state they were on the previous clock tick. The clock used is
8358 * the Core Clock so we have a limit on the maximum "time" they can
8359 * record; typically a very small number of seconds. For instance,
8360 * with a 600MHz Core Clock, we can only count up to a bit more than
8361 * 7s. So we'll synthesize a larger counter in order to not run the
8362 * risk of having the "timers" overflow and give us the flexibility to
8363 * maintain a Hung SGE State Machine of our own which operates across
8364 * a longer time frame.
8366 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8367 idma->idma_stalled[0] = 0;
8368 idma->idma_stalled[1] = 0;
8372 * t4_idma_monitor - monitor SGE Ingress DMA state
8373 * @adapter: the adapter
8374 * @idma: the adapter IDMA Monitor state
8375 * @hz: number of ticks/second
8376 * @ticks: number of ticks since the last IDMA Monitor call
8378 void t4_idma_monitor(struct adapter *adapter,
8379 struct sge_idma_monitor_state *idma,
8382 int i, idma_same_state_cnt[2];
8384 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8385 * are counters inside the SGE which count up on each clock when the
8386 * SGE finds its Ingress DMA State Engines in the same states they
8387 * were in the previous clock. The counters will peg out at
8388 * 0xffffffff without wrapping around so once they pass the 1s
8389 * threshold they'll stay above that till the IDMA state changes.
8391 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8392 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8393 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8395 for (i = 0; i < 2; i++) {
8396 u32 debug0, debug11;
8398 /* If the Ingress DMA Same State Counter ("timer") is less
8399 * than 1s, then we can reset our synthesized Stall Timer and
8400 * continue. If we have previously emitted warnings about a
8401 * potential stalled Ingress Queue, issue a note indicating
8402 * that the Ingress Queue has resumed forward progress.
8404 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8405 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8406 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8407 "resumed after %d seconds\n",
8408 i, idma->idma_qid[i],
8409 idma->idma_stalled[i] / hz);
8410 idma->idma_stalled[i] = 0;
8414 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8415 * domain. The first time we get here it'll be because we
8416 * passed the 1s Threshold; each additional time it'll be
8417 * because the RX Timer Callback is being fired on its regular
8420 * If the stall is below our Potential Hung Ingress Queue
8421 * Warning Threshold, continue.
8423 if (idma->idma_stalled[i] == 0) {
8424 idma->idma_stalled[i] = hz;
8425 idma->idma_warn[i] = 0;
8427 idma->idma_stalled[i] += ticks;
8428 idma->idma_warn[i] -= ticks;
8431 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8434 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8436 if (idma->idma_warn[i] > 0)
8438 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8440 /* Read and save the SGE IDMA State and Queue ID information.
8441 * We do this every time in case it changes across time ...
8442 * can't be too careful ...
8444 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8445 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8446 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8448 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8449 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8450 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8452 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8453 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8454 i, idma->idma_qid[i], idma->idma_state[i],
8455 idma->idma_stalled[i] / hz,
8457 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8462 * t4_set_vf_mac - Set MAC address for the specified VF
8463 * @adapter: The adapter
8464 * @vf: one of the VFs instantiated by the specified PF
8465 * @naddr: the number of MAC addresses
8466 * @addr: the MAC address(es) to be set to the specified VF
8468 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8469 unsigned int naddr, u8 *addr)
8471 struct fw_acl_mac_cmd cmd;
8473 memset(&cmd, 0, sizeof(cmd));
8474 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8477 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8478 FW_ACL_MAC_CMD_VFN_V(vf));
8480 /* Note: Do not enable the ACL */
8481 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8484 switch (adapter->pf) {
8486 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8489 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8492 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8495 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8499 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8502 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8503 int rateunit, int ratemode, int channel, int class,
8504 int minrate, int maxrate, int weight, int pktsize)
8506 struct fw_sched_cmd cmd;
8508 memset(&cmd, 0, sizeof(cmd));
8509 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8512 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8514 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8515 cmd.u.params.type = type;
8516 cmd.u.params.level = level;
8517 cmd.u.params.mode = mode;
8518 cmd.u.params.ch = channel;
8519 cmd.u.params.cl = class;
8520 cmd.u.params.unit = rateunit;
8521 cmd.u.params.rate = ratemode;
8522 cmd.u.params.min = cpu_to_be32(minrate);
8523 cmd.u.params.max = cpu_to_be32(maxrate);
8524 cmd.u.params.weight = cpu_to_be16(weight);
8525 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8527 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),