2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
291 int i, ms, delay_idx, ret;
292 const __be64 *p = cmd;
293 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
294 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
295 __be64 cmd_rpl[MBOX_LEN / 8];
298 if ((size & 15) || size > MBOX_LEN)
302 * If the device is off-line, as in EEH, commands will time out.
303 * Fail them early so we don't waste time waiting.
305 if (adap->pdev->error_state != pci_channel_io_normal)
308 /* If we have a negative timeout, that implies that we can't sleep. */
314 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
315 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
316 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
318 if (v != MBOX_OWNER_DRV) {
319 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
320 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
324 /* Copy in the new mailbox command and send it on its way ... */
325 t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
326 for (i = 0; i < size; i += 8)
327 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
329 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
330 t4_read_reg(adap, ctl_reg); /* flush write */
336 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
340 ms = delay[delay_idx]; /* last element may repeat */
341 if (delay_idx < ARRAY_SIZE(delay) - 1)
347 v = t4_read_reg(adap, ctl_reg);
348 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
349 if (!(v & MBMSGVALID_F)) {
350 t4_write_reg(adap, ctl_reg, 0);
354 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
355 res = be64_to_cpu(cmd_rpl[0]);
357 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
358 fw_asrt(adap, data_reg);
359 res = FW_CMD_RETVAL_V(EIO);
361 memcpy(rpl, cmd_rpl, size);
364 t4_write_reg(adap, ctl_reg, 0);
367 t4_record_mbox(adap, cmd_rpl,
368 MBOX_LEN, access, execute);
369 return -FW_CMD_RETVAL_G((int)res);
373 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
375 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
376 *(const u8 *)cmd, mbox);
377 t4_report_fw_error(adap);
381 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
382 void *rpl, bool sleep_ok)
384 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
388 static int t4_edc_err_read(struct adapter *adap, int idx)
390 u32 edc_ecc_err_addr_reg;
393 if (is_t4(adap->params.chip)) {
394 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
397 if (idx != 0 && idx != 1) {
398 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
402 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
403 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
406 "edc%d err addr 0x%x: 0x%x.\n",
407 idx, edc_ecc_err_addr_reg,
408 t4_read_reg(adap, edc_ecc_err_addr_reg));
410 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
412 (unsigned long long)t4_read_reg64(adap, rdata_reg),
413 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
414 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
415 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
416 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
417 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
418 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
419 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
420 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
426 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
428 * @win: PCI-E Memory Window to use
429 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
430 * @addr: address within indicated memory type
431 * @len: amount of memory to transfer
432 * @hbuf: host memory buffer
433 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
435 * Reads/writes an [almost] arbitrary memory region in the firmware: the
436 * firmware memory address and host buffer must be aligned on 32-bit
437 * boudaries; the length may be arbitrary. The memory is transferred as
438 * a raw byte sequence from/to the firmware's memory. If this memory
439 * contains data structures which contain multi-byte integers, it's the
440 * caller's responsibility to perform appropriate byte order conversions.
442 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
443 u32 len, void *hbuf, int dir)
445 u32 pos, offset, resid, memoffset;
446 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
449 /* Argument sanity checks ...
451 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
455 /* It's convenient to be able to handle lengths which aren't a
456 * multiple of 32-bits because we often end up transferring files to
457 * the firmware. So we'll handle that by normalizing the length here
458 * and then handling any residual transfer at the end.
463 /* Offset into the region of memory which is being accessed
466 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
467 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
469 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
470 if (mtype != MEM_MC1)
471 memoffset = (mtype * (edc_size * 1024 * 1024));
473 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
474 MA_EXT_MEMORY0_BAR_A));
475 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
478 /* Determine the PCIE_MEM_ACCESS_OFFSET */
479 addr = addr + memoffset;
481 /* Each PCI-E Memory Window is programmed with a window size -- or
482 * "aperture" -- which controls the granularity of its mapping onto
483 * adapter memory. We need to grab that aperture in order to know
484 * how to use the specified window. The window is also programmed
485 * with the base address of the Memory Window in BAR0's address
486 * space. For T4 this is an absolute PCI-E Bus Address. For T5
487 * the address is relative to BAR0.
489 mem_reg = t4_read_reg(adap,
490 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
492 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
493 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
494 if (is_t4(adap->params.chip))
495 mem_base -= adap->t4_bar0;
496 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
498 /* Calculate our initial PCI-E Memory Window Position and Offset into
501 pos = addr & ~(mem_aperture-1);
504 /* Set up initial PCI-E Memory Window to cover the start of our
505 * transfer. (Read it back to ensure that changes propagate before we
506 * attempt to use the new value.)
509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
512 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
514 /* Transfer data to/from the adapter as long as there's an integral
515 * number of 32-bit transfers to complete.
517 * A note on Endianness issues:
519 * The "register" reads and writes below from/to the PCI-E Memory
520 * Window invoke the standard adapter Big-Endian to PCI-E Link
521 * Little-Endian "swizzel." As a result, if we have the following
522 * data in adapter memory:
524 * Memory: ... | b0 | b1 | b2 | b3 | ...
525 * Address: i+0 i+1 i+2 i+3
527 * Then a read of the adapter memory via the PCI-E Memory Window
532 * [ b3 | b2 | b1 | b0 ]
534 * If this value is stored into local memory on a Little-Endian system
535 * it will show up correctly in local memory as:
537 * ( ..., b0, b1, b2, b3, ... )
539 * But on a Big-Endian system, the store will show up in memory
540 * incorrectly swizzled as:
542 * ( ..., b3, b2, b1, b0, ... )
544 * So we need to account for this in the reads and writes to the
545 * PCI-E Memory Window below by undoing the register read/write
549 if (dir == T4_MEMORY_READ)
550 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
553 t4_write_reg(adap, mem_base + offset,
554 (__force u32)cpu_to_le32(*buf++));
555 offset += sizeof(__be32);
556 len -= sizeof(__be32);
558 /* If we've reached the end of our current window aperture,
559 * move the PCI-E Memory Window on to the next. Note that
560 * doing this here after "len" may be 0 allows us to set up
561 * the PCI-E Memory Window for a possible final residual
564 if (offset == mem_aperture) {
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
576 /* If the original transfer had a length which wasn't a multiple of
577 * 32-bits, now's where we need to finish off the transfer of the
578 * residual amount. The PCI-E Memory Window has already been moved
579 * above (if necessary) to cover this final transfer.
589 if (dir == T4_MEMORY_READ) {
590 last.word = le32_to_cpu(
591 (__force __le32)t4_read_reg(adap,
593 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
594 bp[i] = last.byte[i];
597 for (i = resid; i < 4; i++)
599 t4_write_reg(adap, mem_base + offset,
600 (__force u32)cpu_to_le32(last.word));
607 /* Return the specified PCI-E Configuration Space register from our Physical
608 * Function. We try first via a Firmware LDST Command since we prefer to let
609 * the firmware own all of these registers, but if that fails we go for it
610 * directly ourselves.
612 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
614 u32 val, ldst_addrspace;
616 /* If fw_attach != 0, construct and send the Firmware LDST Command to
617 * retrieve the specified PCI-E Configuration Space register.
619 struct fw_ldst_cmd ldst_cmd;
622 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
623 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
624 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
628 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
629 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
630 ldst_cmd.u.pcie.ctrl_to_fn =
631 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
632 ldst_cmd.u.pcie.r = reg;
634 /* If the LDST Command succeeds, return the result, otherwise
635 * fall through to reading it directly ourselves ...
637 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
640 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
642 /* Read the desired Configuration Space register via the PCI-E
643 * Backdoor mechanism.
645 t4_hw_pci_read_cfg4(adap, reg, &val);
649 /* Get the window based on base passed to it.
650 * Window aperture is currently unhandled, but there is no use case for it
653 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
658 if (is_t4(adap->params.chip)) {
661 /* Truncation intentional: we only read the bottom 32-bits of
662 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
663 * mechanism to read BAR0 instead of using
664 * pci_resource_start() because we could be operating from
665 * within a Virtual Machine which is trapping our accesses to
666 * our Configuration Space and we need to set up the PCI-E
667 * Memory Window decoders with the actual addresses which will
668 * be coming across the PCI-E link.
670 bar0 = t4_read_pcie_cfg4(adap, pci_base);
672 adap->t4_bar0 = bar0;
674 ret = bar0 + memwin_base;
676 /* For T5, only relative offset inside the PCIe BAR is passed */
682 /* Get the default utility window (win0) used by everyone */
683 u32 t4_get_util_window(struct adapter *adap)
685 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
686 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
689 /* Set up memory window for accessing adapter memory ranges. (Read
690 * back MA register to ensure that changes propagate before we attempt
691 * to use the new values.)
693 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
696 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
697 memwin_base | BIR_V(0) |
698 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
700 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
704 * t4_get_regs_len - return the size of the chips register set
705 * @adapter: the adapter
707 * Returns the size of the chip's BAR0 register space.
709 unsigned int t4_get_regs_len(struct adapter *adapter)
711 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
713 switch (chip_version) {
715 return T4_REGMAP_SIZE;
719 return T5_REGMAP_SIZE;
722 dev_err(adapter->pdev_dev,
723 "Unsupported chip version %d\n", chip_version);
728 * t4_get_regs - read chip registers into provided buffer
730 * @buf: register buffer
731 * @buf_size: size (in bytes) of register buffer
733 * If the provided register buffer isn't large enough for the chip's
734 * full register range, the register dump will be truncated to the
735 * register buffer's size.
737 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
739 static const unsigned int t4_reg_ranges[] = {
1197 static const unsigned int t5_reg_ranges[] = {
1972 static const unsigned int t6_reg_ranges[] = {
2549 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2550 const unsigned int *reg_ranges;
2551 int reg_ranges_size, range;
2552 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2554 /* Select the right set of register ranges to dump depending on the
2555 * adapter chip type.
2557 switch (chip_version) {
2559 reg_ranges = t4_reg_ranges;
2560 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2564 reg_ranges = t5_reg_ranges;
2565 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2569 reg_ranges = t6_reg_ranges;
2570 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2574 dev_err(adap->pdev_dev,
2575 "Unsupported chip version %d\n", chip_version);
2579 /* Clear the register buffer and insert the appropriate register
2580 * values selected by the above register ranges.
2582 memset(buf, 0, buf_size);
2583 for (range = 0; range < reg_ranges_size; range += 2) {
2584 unsigned int reg = reg_ranges[range];
2585 unsigned int last_reg = reg_ranges[range + 1];
2586 u32 *bufp = (u32 *)((char *)buf + reg);
2588 /* Iterate across the register range filling in the register
2589 * buffer but don't write past the end of the register buffer.
2591 while (reg <= last_reg && bufp < buf_end) {
2592 *bufp++ = t4_read_reg(adap, reg);
2598 #define EEPROM_STAT_ADDR 0x7bfc
2599 #define VPD_SIZE 0x800
2600 #define VPD_BASE 0x400
2601 #define VPD_BASE_OLD 0
2602 #define VPD_LEN 1024
2603 #define CHELSIO_VPD_UNIQUE_ID 0x82
2606 * t4_seeprom_wp - enable/disable EEPROM write protection
2607 * @adapter: the adapter
2608 * @enable: whether to enable or disable write protection
2610 * Enables or disables write protection on the serial EEPROM.
2612 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2614 unsigned int v = enable ? 0xc : 0;
2615 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2616 return ret < 0 ? ret : 0;
2620 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2621 * @adapter: adapter to read
2622 * @p: where to store the parameters
2624 * Reads card parameters stored in VPD EEPROM.
2626 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2628 int i, ret = 0, addr;
2631 unsigned int vpdr_len, kw_offset, id_len;
2633 vpd = vmalloc(VPD_LEN);
2637 /* We have two VPD data structures stored in the adapter VPD area.
2638 * By default, Linux calculates the size of the VPD area by traversing
2639 * the first VPD area at offset 0x0, so we need to tell the OS what
2640 * our real VPD size is.
2642 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2646 /* Card information normally starts at VPD_BASE but early cards had
2649 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2653 /* The VPD shall have a unique identifier specified by the PCI SIG.
2654 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2655 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2656 * is expected to automatically put this entry at the
2657 * beginning of the VPD.
2659 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2661 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2665 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2666 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2671 id_len = pci_vpd_lrdt_size(vpd);
2672 if (id_len > ID_LEN)
2675 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2677 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2682 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2683 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2684 if (vpdr_len + kw_offset > VPD_LEN) {
2685 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2690 #define FIND_VPD_KW(var, name) do { \
2691 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2693 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2697 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2700 FIND_VPD_KW(i, "RV");
2701 for (csum = 0; i >= 0; i--)
2705 dev_err(adapter->pdev_dev,
2706 "corrupted VPD EEPROM, actual csum %u\n", csum);
2711 FIND_VPD_KW(ec, "EC");
2712 FIND_VPD_KW(sn, "SN");
2713 FIND_VPD_KW(pn, "PN");
2714 FIND_VPD_KW(na, "NA");
2717 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2719 memcpy(p->ec, vpd + ec, EC_LEN);
2721 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2722 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2724 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2725 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2727 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2728 strim((char *)p->na);
2732 return ret < 0 ? ret : 0;
2736 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2737 * @adapter: adapter to read
2738 * @p: where to store the parameters
2740 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2741 * Clock. This can only be called after a connection to the firmware
2744 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 u32 cclk_param, cclk_val;
2749 /* Grab the raw VPD parameters.
2751 ret = t4_get_raw_vpd_params(adapter, p);
2755 /* Ask firmware for the Core Clock since it knows how to translate the
2756 * Reference Clock ('V2') VPD field into a Core Clock value ...
2758 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2759 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2760 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2761 1, &cclk_param, &cclk_val);
2770 /* serial flash and firmware constants */
2772 SF_ATTEMPTS = 10, /* max retries for SF operations */
2774 /* flash command opcodes */
2775 SF_PROG_PAGE = 2, /* program page */
2776 SF_WR_DISABLE = 4, /* disable writes */
2777 SF_RD_STATUS = 5, /* read status register */
2778 SF_WR_ENABLE = 6, /* enable writes */
2779 SF_RD_DATA_FAST = 0xb, /* read flash */
2780 SF_RD_ID = 0x9f, /* read ID */
2781 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2783 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2787 * sf1_read - read data from the serial flash
2788 * @adapter: the adapter
2789 * @byte_cnt: number of bytes to read
2790 * @cont: whether another operation will be chained
2791 * @lock: whether to lock SF for PL access only
2792 * @valp: where to store the read data
2794 * Reads up to 4 bytes of data from the serial flash. The location of
2795 * the read needs to be specified prior to calling this by issuing the
2796 * appropriate commands to the serial flash.
2798 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2799 int lock, u32 *valp)
2803 if (!byte_cnt || byte_cnt > 4)
2805 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2807 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2808 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2809 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2811 *valp = t4_read_reg(adapter, SF_DATA_A);
2816 * sf1_write - write data to the serial flash
2817 * @adapter: the adapter
2818 * @byte_cnt: number of bytes to write
2819 * @cont: whether another operation will be chained
2820 * @lock: whether to lock SF for PL access only
2821 * @val: value to write
2823 * Writes up to 4 bytes of data to the serial flash. The location of
2824 * the write needs to be specified prior to calling this by issuing the
2825 * appropriate commands to the serial flash.
2827 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2830 if (!byte_cnt || byte_cnt > 4)
2832 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2834 t4_write_reg(adapter, SF_DATA_A, val);
2835 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2836 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2837 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2841 * flash_wait_op - wait for a flash operation to complete
2842 * @adapter: the adapter
2843 * @attempts: max number of polls of the status register
2844 * @delay: delay between polls in ms
2846 * Wait for a flash operation to complete by polling the status register.
2848 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2854 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2855 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2859 if (--attempts == 0)
2867 * t4_read_flash - read words from serial flash
2868 * @adapter: the adapter
2869 * @addr: the start address for the read
2870 * @nwords: how many 32-bit words to read
2871 * @data: where to store the read data
2872 * @byte_oriented: whether to store data as bytes or as words
2874 * Read the specified number of 32-bit words from the serial flash.
2875 * If @byte_oriented is set the read data is stored as a byte array
2876 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2877 * natural endianness.
2879 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2880 unsigned int nwords, u32 *data, int byte_oriented)
2884 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2887 addr = swab32(addr) | SF_RD_DATA_FAST;
2889 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2890 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2893 for ( ; nwords; nwords--, data++) {
2894 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2896 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2900 *data = (__force __u32)(cpu_to_be32(*data));
2906 * t4_write_flash - write up to a page of data to the serial flash
2907 * @adapter: the adapter
2908 * @addr: the start address to write
2909 * @n: length of data to write in bytes
2910 * @data: the data to write
2912 * Writes up to a page of data (256 bytes) to the serial flash starting
2913 * at the given address. All the data must be written to the same page.
2915 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2916 unsigned int n, const u8 *data)
2920 unsigned int i, c, left, val, offset = addr & 0xff;
2922 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2925 val = swab32(addr) | SF_PROG_PAGE;
2927 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2928 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2931 for (left = n; left; left -= c) {
2933 for (val = 0, i = 0; i < c; ++i)
2934 val = (val << 8) + *data++;
2936 ret = sf1_write(adapter, c, c != left, 1, val);
2940 ret = flash_wait_op(adapter, 8, 1);
2944 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2946 /* Read the page to verify the write succeeded */
2947 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2951 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2952 dev_err(adapter->pdev_dev,
2953 "failed to correctly write the flash page at %#x\n",
2960 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2965 * t4_get_fw_version - read the firmware version
2966 * @adapter: the adapter
2967 * @vers: where to place the version
2969 * Reads the FW version from flash.
2971 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2973 return t4_read_flash(adapter, FLASH_FW_START +
2974 offsetof(struct fw_hdr, fw_ver), 1,
2979 * t4_get_bs_version - read the firmware bootstrap version
2980 * @adapter: the adapter
2981 * @vers: where to place the version
2983 * Reads the FW Bootstrap version from flash.
2985 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2987 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2988 offsetof(struct fw_hdr, fw_ver), 1,
2993 * t4_get_tp_version - read the TP microcode version
2994 * @adapter: the adapter
2995 * @vers: where to place the version
2997 * Reads the TP microcode version from flash.
2999 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3001 return t4_read_flash(adapter, FLASH_FW_START +
3002 offsetof(struct fw_hdr, tp_microcode_ver),
3007 * t4_get_exprom_version - return the Expansion ROM version (if any)
3008 * @adapter: the adapter
3009 * @vers: where to place the version
3011 * Reads the Expansion ROM header from FLASH and returns the version
3012 * number (if present) through the @vers return value pointer. We return
3013 * this in the Firmware Version Format since it's convenient. Return
3014 * 0 on success, -ENOENT if no Expansion ROM is present.
3016 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3018 struct exprom_header {
3019 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3020 unsigned char hdr_ver[4]; /* Expansion ROM version */
3022 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3026 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3027 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3032 hdr = (struct exprom_header *)exprom_header_buf;
3033 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3036 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3037 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3038 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3039 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3044 * t4_check_fw_version - check if the FW is supported with this driver
3045 * @adap: the adapter
3047 * Checks if an adapter's FW is compatible with the driver. Returns 0
3048 * if there's exact match, a negative error if the version could not be
3049 * read or there's a major version mismatch
3051 int t4_check_fw_version(struct adapter *adap)
3053 int i, ret, major, minor, micro;
3054 int exp_major, exp_minor, exp_micro;
3055 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3057 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3058 /* Try multiple times before returning error */
3059 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3060 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3065 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3066 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3067 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3069 switch (chip_version) {
3071 exp_major = T4FW_MIN_VERSION_MAJOR;
3072 exp_minor = T4FW_MIN_VERSION_MINOR;
3073 exp_micro = T4FW_MIN_VERSION_MICRO;
3076 exp_major = T5FW_MIN_VERSION_MAJOR;
3077 exp_minor = T5FW_MIN_VERSION_MINOR;
3078 exp_micro = T5FW_MIN_VERSION_MICRO;
3081 exp_major = T6FW_MIN_VERSION_MAJOR;
3082 exp_minor = T6FW_MIN_VERSION_MINOR;
3083 exp_micro = T6FW_MIN_VERSION_MICRO;
3086 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3091 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3092 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3093 dev_err(adap->pdev_dev,
3094 "Card has firmware version %u.%u.%u, minimum "
3095 "supported firmware is %u.%u.%u.\n", major, minor,
3096 micro, exp_major, exp_minor, exp_micro);
3102 /* Is the given firmware API compatible with the one the driver was compiled
3105 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3108 /* short circuit if it's the exact same firmware version */
3109 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3112 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3113 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3114 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3121 /* The firmware in the filesystem is usable, but should it be installed?
3122 * This routine explains itself in detail if it indicates the filesystem
3123 * firmware should be installed.
3125 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3130 if (!card_fw_usable) {
3131 reason = "incompatible or unusable";
3136 reason = "older than the version supported with this driver";
3143 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3144 "installing firmware %u.%u.%u.%u on card.\n",
3145 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3146 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3147 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3148 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3153 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3154 const u8 *fw_data, unsigned int fw_size,
3155 struct fw_hdr *card_fw, enum dev_state state,
3158 int ret, card_fw_usable, fs_fw_usable;
3159 const struct fw_hdr *fs_fw;
3160 const struct fw_hdr *drv_fw;
3162 drv_fw = &fw_info->fw_hdr;
3164 /* Read the header of the firmware on the card */
3165 ret = -t4_read_flash(adap, FLASH_FW_START,
3166 sizeof(*card_fw) / sizeof(uint32_t),
3167 (uint32_t *)card_fw, 1);
3169 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3171 dev_err(adap->pdev_dev,
3172 "Unable to read card's firmware header: %d\n", ret);
3176 if (fw_data != NULL) {
3177 fs_fw = (const void *)fw_data;
3178 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3184 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3185 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3186 /* Common case: the firmware on the card is an exact match and
3187 * the filesystem one is an exact match too, or the filesystem
3188 * one is absent/incompatible.
3190 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3191 should_install_fs_fw(adap, card_fw_usable,
3192 be32_to_cpu(fs_fw->fw_ver),
3193 be32_to_cpu(card_fw->fw_ver))) {
3194 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3197 dev_err(adap->pdev_dev,
3198 "failed to install firmware: %d\n", ret);
3202 /* Installed successfully, update the cached header too. */
3205 *reset = 0; /* already reset as part of load_fw */
3208 if (!card_fw_usable) {
3211 d = be32_to_cpu(drv_fw->fw_ver);
3212 c = be32_to_cpu(card_fw->fw_ver);
3213 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3215 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3217 "driver compiled with %d.%d.%d.%d, "
3218 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3220 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3221 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3222 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3223 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3224 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3225 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3230 /* We're using whatever's on the card and it's known to be good. */
3231 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3232 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3239 * t4_flash_erase_sectors - erase a range of flash sectors
3240 * @adapter: the adapter
3241 * @start: the first sector to erase
3242 * @end: the last sector to erase
3244 * Erases the sectors in the given inclusive range.
3246 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3250 if (end >= adapter->params.sf_nsec)
3253 while (start <= end) {
3254 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3255 (ret = sf1_write(adapter, 4, 0, 1,
3256 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3257 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3258 dev_err(adapter->pdev_dev,
3259 "erase of flash sector %d failed, error %d\n",
3265 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3270 * t4_flash_cfg_addr - return the address of the flash configuration file
3271 * @adapter: the adapter
3273 * Return the address within the flash where the Firmware Configuration
3276 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3278 if (adapter->params.sf_size == 0x100000)
3279 return FLASH_FPGA_CFG_START;
3281 return FLASH_CFG_START;
3284 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3285 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3286 * and emit an error message for mismatched firmware to save our caller the
3289 static bool t4_fw_matches_chip(const struct adapter *adap,
3290 const struct fw_hdr *hdr)
3292 /* The expression below will return FALSE for any unsupported adapter
3293 * which will keep us "honest" in the future ...
3295 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3296 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3297 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3300 dev_err(adap->pdev_dev,
3301 "FW image (%d) is not suitable for this adapter (%d)\n",
3302 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3307 * t4_load_fw - download firmware
3308 * @adap: the adapter
3309 * @fw_data: the firmware image to write
3312 * Write the supplied firmware image to the card's serial flash.
3314 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3319 u8 first_page[SF_PAGE_SIZE];
3320 const __be32 *p = (const __be32 *)fw_data;
3321 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3322 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3323 unsigned int fw_img_start = adap->params.sf_fw_start;
3324 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3327 dev_err(adap->pdev_dev, "FW image has no data\n");
3331 dev_err(adap->pdev_dev,
3332 "FW image size not multiple of 512 bytes\n");
3335 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3336 dev_err(adap->pdev_dev,
3337 "FW image size differs from size in FW header\n");
3340 if (size > FW_MAX_SIZE) {
3341 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3345 if (!t4_fw_matches_chip(adap, hdr))
3348 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3349 csum += be32_to_cpu(p[i]);
3351 if (csum != 0xffffffff) {
3352 dev_err(adap->pdev_dev,
3353 "corrupted firmware image, checksum %#x\n", csum);
3357 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3358 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3363 * We write the correct version at the end so the driver can see a bad
3364 * version if the FW write fails. Start by writing a copy of the
3365 * first page with a bad version.
3367 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3368 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3369 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3373 addr = fw_img_start;
3374 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3375 addr += SF_PAGE_SIZE;
3376 fw_data += SF_PAGE_SIZE;
3377 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3382 ret = t4_write_flash(adap,
3383 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3384 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3387 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3390 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3395 * t4_phy_fw_ver - return current PHY firmware version
3396 * @adap: the adapter
3397 * @phy_fw_ver: return value buffer for PHY firmware version
3399 * Returns the current version of external PHY firmware on the
3402 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3407 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3408 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3409 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3410 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3411 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3420 * t4_load_phy_fw - download port PHY firmware
3421 * @adap: the adapter
3422 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3423 * @win_lock: the lock to use to guard the memory copy
3424 * @phy_fw_version: function to check PHY firmware versions
3425 * @phy_fw_data: the PHY firmware image to write
3426 * @phy_fw_size: image size
3428 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3429 * @phy_fw_version is supplied, then it will be used to determine if
3430 * it's necessary to perform the transfer by comparing the version
3431 * of any existing adapter PHY firmware with that of the passed in
3432 * PHY firmware image. If @win_lock is non-NULL then it will be used
3433 * around the call to t4_memory_rw() which transfers the PHY firmware
3436 * A negative error number will be returned if an error occurs. If
3437 * version number support is available and there's no need to upgrade
3438 * the firmware, 0 will be returned. If firmware is successfully
3439 * transferred to the adapter, 1 will be retured.
3441 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3442 * a result, a RESET of the adapter would cause that RAM to lose its
3443 * contents. Thus, loading PHY firmware on such adapters must happen
3444 * after any FW_RESET_CMDs ...
3446 int t4_load_phy_fw(struct adapter *adap,
3447 int win, spinlock_t *win_lock,
3448 int (*phy_fw_version)(const u8 *, size_t),
3449 const u8 *phy_fw_data, size_t phy_fw_size)
3451 unsigned long mtype = 0, maddr = 0;
3453 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3456 /* If we have version number support, then check to see if the adapter
3457 * already has up-to-date PHY firmware loaded.
3459 if (phy_fw_version) {
3460 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3461 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3465 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3466 CH_WARN(adap, "PHY Firmware already up-to-date, "
3467 "version %#x\n", cur_phy_fw_ver);
3472 /* Ask the firmware where it wants us to copy the PHY firmware image.
3473 * The size of the file requires a special version of the READ coommand
3474 * which will pass the file size via the values field in PARAMS_CMD and
3475 * retrieve the return value from firmware and place it in the same
3478 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3479 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3480 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3481 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3483 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3488 maddr = (val & 0xff) << 16;
3490 /* Copy the supplied PHY Firmware image to the adapter memory location
3491 * allocated by the adapter firmware.
3494 spin_lock_bh(win_lock);
3495 ret = t4_memory_rw(adap, win, mtype, maddr,
3496 phy_fw_size, (__be32 *)phy_fw_data,
3499 spin_unlock_bh(win_lock);
3503 /* Tell the firmware that the PHY firmware image has been written to
3504 * RAM and it can now start copying it over to the PHYs. The chip
3505 * firmware will RESET the affected PHYs as part of this operation
3506 * leaving them running the new PHY firmware image.
3508 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3509 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3510 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3511 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3512 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3513 ¶m, &val, 30000);
3515 /* If we have version number support, then check to see that the new
3516 * firmware got loaded properly.
3518 if (phy_fw_version) {
3519 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3523 if (cur_phy_fw_ver != new_phy_fw_vers) {
3524 CH_WARN(adap, "PHY Firmware did not update: "
3525 "version on adapter %#x, "
3526 "version flashed %#x\n",
3527 cur_phy_fw_ver, new_phy_fw_vers);
3536 * t4_fwcache - firmware cache operation
3537 * @adap: the adapter
3538 * @op : the operation (flush or flush and invalidate)
3540 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3542 struct fw_params_cmd c;
3544 memset(&c, 0, sizeof(c));
3546 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3547 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3548 FW_PARAMS_CMD_PFN_V(adap->pf) |
3549 FW_PARAMS_CMD_VFN_V(0));
3550 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3552 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3553 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3554 c.param[0].val = (__force __be32)op;
3556 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3559 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3560 unsigned int *pif_req_wrptr,
3561 unsigned int *pif_rsp_wrptr)
3564 u32 cfg, val, req, rsp;
3566 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3567 if (cfg & LADBGEN_F)
3568 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3570 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3571 req = POLADBGWRPTR_G(val);
3572 rsp = PILADBGWRPTR_G(val);
3574 *pif_req_wrptr = req;
3576 *pif_rsp_wrptr = rsp;
3578 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3579 for (j = 0; j < 6; j++) {
3580 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3581 PILADBGRDPTR_V(rsp));
3582 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3583 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3587 req = (req + 2) & POLADBGRDPTR_M;
3588 rsp = (rsp + 2) & PILADBGRDPTR_M;
3590 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3593 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3598 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3599 if (cfg & LADBGEN_F)
3600 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3602 for (i = 0; i < CIM_MALA_SIZE; i++) {
3603 for (j = 0; j < 5; j++) {
3605 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3606 PILADBGRDPTR_V(idx));
3607 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3608 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3611 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3614 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3618 for (i = 0; i < 8; i++) {
3619 u32 *p = la_buf + i;
3621 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3622 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3623 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3624 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3625 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3629 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3630 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3631 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3635 * t4_link_l1cfg - apply link configuration to MAC/PHY
3636 * @phy: the PHY to setup
3637 * @mac: the MAC to setup
3638 * @lc: the requested link configuration
3640 * Set up a port's MAC and PHY according to a desired link configuration.
3641 * - If the PHY can auto-negotiate first decide what to advertise, then
3642 * enable/disable auto-negotiation as desired, and reset.
3643 * - If the PHY does not auto-negotiate just reset it.
3644 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3645 * otherwise do it later based on the outcome of auto-negotiation.
3647 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3648 struct link_config *lc)
3650 struct fw_port_cmd c;
3651 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3654 if (lc->requested_fc & PAUSE_RX)
3655 fc |= FW_PORT_CAP_FC_RX;
3656 if (lc->requested_fc & PAUSE_TX)
3657 fc |= FW_PORT_CAP_FC_TX;
3659 memset(&c, 0, sizeof(c));
3660 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3661 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3662 FW_PORT_CMD_PORTID_V(port));
3664 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3667 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3668 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3670 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3671 } else if (lc->autoneg == AUTONEG_DISABLE) {
3672 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3673 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3675 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3677 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3681 * t4_restart_aneg - restart autonegotiation
3682 * @adap: the adapter
3683 * @mbox: mbox to use for the FW command
3684 * @port: the port id
3686 * Restarts autonegotiation for the selected port.
3688 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3690 struct fw_port_cmd c;
3692 memset(&c, 0, sizeof(c));
3693 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3694 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3695 FW_PORT_CMD_PORTID_V(port));
3697 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3699 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3700 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3703 typedef void (*int_handler_t)(struct adapter *adap);
3706 unsigned int mask; /* bits to check in interrupt status */
3707 const char *msg; /* message to print or NULL */
3708 short stat_idx; /* stat counter to increment or -1 */
3709 unsigned short fatal; /* whether the condition reported is fatal */
3710 int_handler_t int_handler; /* platform-specific int handler */
3714 * t4_handle_intr_status - table driven interrupt handler
3715 * @adapter: the adapter that generated the interrupt
3716 * @reg: the interrupt status register to process
3717 * @acts: table of interrupt actions
3719 * A table driven interrupt handler that applies a set of masks to an
3720 * interrupt status word and performs the corresponding actions if the
3721 * interrupts described by the mask have occurred. The actions include
3722 * optionally emitting a warning or alert message. The table is terminated
3723 * by an entry specifying mask 0. Returns the number of fatal interrupt
3726 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3727 const struct intr_info *acts)
3730 unsigned int mask = 0;
3731 unsigned int status = t4_read_reg(adapter, reg);
3733 for ( ; acts->mask; ++acts) {
3734 if (!(status & acts->mask))
3738 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3739 status & acts->mask);
3740 } else if (acts->msg && printk_ratelimit())
3741 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3742 status & acts->mask);
3743 if (acts->int_handler)
3744 acts->int_handler(adapter);
3748 if (status) /* clear processed interrupts */
3749 t4_write_reg(adapter, reg, status);
3754 * Interrupt handler for the PCIE module.
3756 static void pcie_intr_handler(struct adapter *adapter)
3758 static const struct intr_info sysbus_intr_info[] = {
3759 { RNPP_F, "RXNP array parity error", -1, 1 },
3760 { RPCP_F, "RXPC array parity error", -1, 1 },
3761 { RCIP_F, "RXCIF array parity error", -1, 1 },
3762 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3763 { RFTP_F, "RXFT array parity error", -1, 1 },
3766 static const struct intr_info pcie_port_intr_info[] = {
3767 { TPCP_F, "TXPC array parity error", -1, 1 },
3768 { TNPP_F, "TXNP array parity error", -1, 1 },
3769 { TFTP_F, "TXFT array parity error", -1, 1 },
3770 { TCAP_F, "TXCA array parity error", -1, 1 },
3771 { TCIP_F, "TXCIF array parity error", -1, 1 },
3772 { RCAP_F, "RXCA array parity error", -1, 1 },
3773 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3774 { RDPE_F, "Rx data parity error", -1, 1 },
3775 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3778 static const struct intr_info pcie_intr_info[] = {
3779 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3780 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3781 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3782 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3783 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3784 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3785 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3786 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3787 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3788 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3789 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3790 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3791 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3792 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3793 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3794 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3795 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3796 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3797 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3798 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3799 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3800 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3801 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3802 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3803 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3804 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3805 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3806 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3807 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3808 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3813 static struct intr_info t5_pcie_intr_info[] = {
3814 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3816 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3817 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3818 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3819 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3820 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3821 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3822 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3824 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3826 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3827 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3828 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3829 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3830 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3832 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3833 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3834 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3835 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3836 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3837 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3838 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3839 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3840 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3841 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3842 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3844 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3846 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3847 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3848 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3849 { READRSPERR_F, "Outbound read error", -1, 0 },
3855 if (is_t4(adapter->params.chip))
3856 fat = t4_handle_intr_status(adapter,
3857 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3859 t4_handle_intr_status(adapter,
3860 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3861 pcie_port_intr_info) +
3862 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3865 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3869 t4_fatal_err(adapter);
3873 * TP interrupt handler.
3875 static void tp_intr_handler(struct adapter *adapter)
3877 static const struct intr_info tp_intr_info[] = {
3878 { 0x3fffffff, "TP parity error", -1, 1 },
3879 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3883 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3884 t4_fatal_err(adapter);
3888 * SGE interrupt handler.
3890 static void sge_intr_handler(struct adapter *adapter)
3895 static const struct intr_info sge_intr_info[] = {
3896 { ERR_CPL_EXCEED_IQE_SIZE_F,
3897 "SGE received CPL exceeding IQE size", -1, 1 },
3898 { ERR_INVALID_CIDX_INC_F,
3899 "SGE GTS CIDX increment too large", -1, 0 },
3900 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3901 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3902 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3903 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3904 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3906 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3908 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3910 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3912 { ERR_ING_CTXT_PRIO_F,
3913 "SGE too many priority ingress contexts", -1, 0 },
3914 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3915 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3919 static struct intr_info t4t5_sge_intr_info[] = {
3920 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3921 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3922 { ERR_EGR_CTXT_PRIO_F,
3923 "SGE too many priority egress contexts", -1, 0 },
3927 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3928 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3930 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3931 (unsigned long long)v);
3932 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3933 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3936 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3937 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3938 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3939 t4t5_sge_intr_info);
3941 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3942 if (err & ERROR_QID_VALID_F) {
3943 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3945 if (err & UNCAPTURED_ERROR_F)
3946 dev_err(adapter->pdev_dev,
3947 "SGE UNCAPTURED_ERROR set (clearing)\n");
3948 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3949 UNCAPTURED_ERROR_F);
3953 t4_fatal_err(adapter);
3956 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3957 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3958 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3959 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3962 * CIM interrupt handler.
3964 static void cim_intr_handler(struct adapter *adapter)
3966 static const struct intr_info cim_intr_info[] = {
3967 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3968 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3969 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3970 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3971 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3972 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3973 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3976 static const struct intr_info cim_upintr_info[] = {
3977 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3978 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3979 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3980 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3981 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3982 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3983 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3984 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3985 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3986 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3987 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3988 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3989 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3990 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3991 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3992 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3993 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3994 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3995 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3996 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3997 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3998 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3999 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4000 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4001 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4002 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4003 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4004 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4010 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4011 t4_report_fw_error(adapter);
4013 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4015 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4018 t4_fatal_err(adapter);
4022 * ULP RX interrupt handler.
4024 static void ulprx_intr_handler(struct adapter *adapter)
4026 static const struct intr_info ulprx_intr_info[] = {
4027 { 0x1800000, "ULPRX context error", -1, 1 },
4028 { 0x7fffff, "ULPRX parity error", -1, 1 },
4032 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4033 t4_fatal_err(adapter);
4037 * ULP TX interrupt handler.
4039 static void ulptx_intr_handler(struct adapter *adapter)
4041 static const struct intr_info ulptx_intr_info[] = {
4042 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4044 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4046 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4048 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4050 { 0xfffffff, "ULPTX parity error", -1, 1 },
4054 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4055 t4_fatal_err(adapter);
4059 * PM TX interrupt handler.
4061 static void pmtx_intr_handler(struct adapter *adapter)
4063 static const struct intr_info pmtx_intr_info[] = {
4064 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4065 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4066 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4067 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4068 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4069 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4070 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4072 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4073 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4077 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4078 t4_fatal_err(adapter);
4082 * PM RX interrupt handler.
4084 static void pmrx_intr_handler(struct adapter *adapter)
4086 static const struct intr_info pmrx_intr_info[] = {
4087 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4088 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4089 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4090 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4092 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4093 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4097 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4098 t4_fatal_err(adapter);
4102 * CPL switch interrupt handler.
4104 static void cplsw_intr_handler(struct adapter *adapter)
4106 static const struct intr_info cplsw_intr_info[] = {
4107 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4108 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4109 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4110 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4111 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4112 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4116 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4117 t4_fatal_err(adapter);
4121 * LE interrupt handler.
4123 static void le_intr_handler(struct adapter *adap)
4125 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4126 static const struct intr_info le_intr_info[] = {
4127 { LIPMISS_F, "LE LIP miss", -1, 0 },
4128 { LIP0_F, "LE 0 LIP error", -1, 0 },
4129 { PARITYERR_F, "LE parity error", -1, 1 },
4130 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4131 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4135 static struct intr_info t6_le_intr_info[] = {
4136 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4137 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4138 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4139 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4140 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4144 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4145 (chip <= CHELSIO_T5) ?
4146 le_intr_info : t6_le_intr_info))
4151 * MPS interrupt handler.
4153 static void mps_intr_handler(struct adapter *adapter)
4155 static const struct intr_info mps_rx_intr_info[] = {
4156 { 0xffffff, "MPS Rx parity error", -1, 1 },
4159 static const struct intr_info mps_tx_intr_info[] = {
4160 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4161 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4162 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4164 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4166 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4167 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4168 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4171 static const struct intr_info mps_trc_intr_info[] = {
4172 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4173 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4175 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4178 static const struct intr_info mps_stat_sram_intr_info[] = {
4179 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4182 static const struct intr_info mps_stat_tx_intr_info[] = {
4183 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4186 static const struct intr_info mps_stat_rx_intr_info[] = {
4187 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4190 static const struct intr_info mps_cls_intr_info[] = {
4191 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4192 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4193 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4199 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4201 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4203 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4204 mps_trc_intr_info) +
4205 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4206 mps_stat_sram_intr_info) +
4207 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4208 mps_stat_tx_intr_info) +
4209 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4210 mps_stat_rx_intr_info) +
4211 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4214 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4215 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4217 t4_fatal_err(adapter);
4220 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4224 * EDC/MC interrupt handler.
4226 static void mem_intr_handler(struct adapter *adapter, int idx)
4228 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4230 unsigned int addr, cnt_addr, v;
4232 if (idx <= MEM_EDC1) {
4233 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4234 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4235 } else if (idx == MEM_MC) {
4236 if (is_t4(adapter->params.chip)) {
4237 addr = MC_INT_CAUSE_A;
4238 cnt_addr = MC_ECC_STATUS_A;
4240 addr = MC_P_INT_CAUSE_A;
4241 cnt_addr = MC_P_ECC_STATUS_A;
4244 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4245 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4248 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4249 if (v & PERR_INT_CAUSE_F)
4250 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4252 if (v & ECC_CE_INT_CAUSE_F) {
4253 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4255 t4_edc_err_read(adapter, idx);
4257 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4258 if (printk_ratelimit())
4259 dev_warn(adapter->pdev_dev,
4260 "%u %s correctable ECC data error%s\n",
4261 cnt, name[idx], cnt > 1 ? "s" : "");
4263 if (v & ECC_UE_INT_CAUSE_F)
4264 dev_alert(adapter->pdev_dev,
4265 "%s uncorrectable ECC data error\n", name[idx]);
4267 t4_write_reg(adapter, addr, v);
4268 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4269 t4_fatal_err(adapter);
4273 * MA interrupt handler.
4275 static void ma_intr_handler(struct adapter *adap)
4277 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4279 if (status & MEM_PERR_INT_CAUSE_F) {
4280 dev_alert(adap->pdev_dev,
4281 "MA parity error, parity status %#x\n",
4282 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4283 if (is_t5(adap->params.chip))
4284 dev_alert(adap->pdev_dev,
4285 "MA parity error, parity status %#x\n",
4287 MA_PARITY_ERROR_STATUS2_A));
4289 if (status & MEM_WRAP_INT_CAUSE_F) {
4290 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4291 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4292 "client %u to address %#x\n",
4293 MEM_WRAP_CLIENT_NUM_G(v),
4294 MEM_WRAP_ADDRESS_G(v) << 4);
4296 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4301 * SMB interrupt handler.
4303 static void smb_intr_handler(struct adapter *adap)
4305 static const struct intr_info smb_intr_info[] = {
4306 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4307 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4308 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4312 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4317 * NC-SI interrupt handler.
4319 static void ncsi_intr_handler(struct adapter *adap)
4321 static const struct intr_info ncsi_intr_info[] = {
4322 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4323 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4324 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4325 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4329 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4334 * XGMAC interrupt handler.
4336 static void xgmac_intr_handler(struct adapter *adap, int port)
4338 u32 v, int_cause_reg;
4340 if (is_t4(adap->params.chip))
4341 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4343 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4345 v = t4_read_reg(adap, int_cause_reg);
4347 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4351 if (v & TXFIFO_PRTY_ERR_F)
4352 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4354 if (v & RXFIFO_PRTY_ERR_F)
4355 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4357 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4362 * PL interrupt handler.
4364 static void pl_intr_handler(struct adapter *adap)
4366 static const struct intr_info pl_intr_info[] = {
4367 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4368 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4372 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4376 #define PF_INTR_MASK (PFSW_F)
4377 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4378 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4379 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4382 * t4_slow_intr_handler - control path interrupt handler
4383 * @adapter: the adapter
4385 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4386 * The designation 'slow' is because it involves register reads, while
4387 * data interrupts typically don't involve any MMIOs.
4389 int t4_slow_intr_handler(struct adapter *adapter)
4391 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4393 if (!(cause & GLBL_INTR_MASK))
4396 cim_intr_handler(adapter);
4398 mps_intr_handler(adapter);
4400 ncsi_intr_handler(adapter);
4402 pl_intr_handler(adapter);
4404 smb_intr_handler(adapter);
4405 if (cause & XGMAC0_F)
4406 xgmac_intr_handler(adapter, 0);
4407 if (cause & XGMAC1_F)
4408 xgmac_intr_handler(adapter, 1);
4409 if (cause & XGMAC_KR0_F)
4410 xgmac_intr_handler(adapter, 2);
4411 if (cause & XGMAC_KR1_F)
4412 xgmac_intr_handler(adapter, 3);
4414 pcie_intr_handler(adapter);
4416 mem_intr_handler(adapter, MEM_MC);
4417 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4418 mem_intr_handler(adapter, MEM_MC1);
4420 mem_intr_handler(adapter, MEM_EDC0);
4422 mem_intr_handler(adapter, MEM_EDC1);
4424 le_intr_handler(adapter);
4426 tp_intr_handler(adapter);
4428 ma_intr_handler(adapter);
4429 if (cause & PM_TX_F)
4430 pmtx_intr_handler(adapter);
4431 if (cause & PM_RX_F)
4432 pmrx_intr_handler(adapter);
4433 if (cause & ULP_RX_F)
4434 ulprx_intr_handler(adapter);
4435 if (cause & CPL_SWITCH_F)
4436 cplsw_intr_handler(adapter);
4438 sge_intr_handler(adapter);
4439 if (cause & ULP_TX_F)
4440 ulptx_intr_handler(adapter);
4442 /* Clear the interrupts just processed for which we are the master. */
4443 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4444 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4449 * t4_intr_enable - enable interrupts
4450 * @adapter: the adapter whose interrupts should be enabled
4452 * Enable PF-specific interrupts for the calling function and the top-level
4453 * interrupt concentrator for global interrupts. Interrupts are already
4454 * enabled at each module, here we just enable the roots of the interrupt
4457 * Note: this function should be called only when the driver manages
4458 * non PF-specific interrupts from the various HW modules. Only one PCI
4459 * function at a time should be doing this.
4461 void t4_intr_enable(struct adapter *adapter)
4464 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4465 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4466 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4468 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4469 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4470 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4471 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4472 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4473 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4474 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4475 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4476 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4477 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4478 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4482 * t4_intr_disable - disable interrupts
4483 * @adapter: the adapter whose interrupts should be disabled
4485 * Disable interrupts. We only disable the top-level interrupt
4486 * concentrators. The caller must be a PCI function managing global
4489 void t4_intr_disable(struct adapter *adapter)
4491 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4492 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4493 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4495 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4496 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4500 * t4_config_rss_range - configure a portion of the RSS mapping table
4501 * @adapter: the adapter
4502 * @mbox: mbox to use for the FW command
4503 * @viid: virtual interface whose RSS subtable is to be written
4504 * @start: start entry in the table to write
4505 * @n: how many table entries to write
4506 * @rspq: values for the response queue lookup table
4507 * @nrspq: number of values in @rspq
4509 * Programs the selected part of the VI's RSS mapping table with the
4510 * provided values. If @nrspq < @n the supplied values are used repeatedly
4511 * until the full table range is populated.
4513 * The caller must ensure the values in @rspq are in the range allowed for
4516 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4517 int start, int n, const u16 *rspq, unsigned int nrspq)
4520 const u16 *rsp = rspq;
4521 const u16 *rsp_end = rspq + nrspq;
4522 struct fw_rss_ind_tbl_cmd cmd;
4524 memset(&cmd, 0, sizeof(cmd));
4525 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4526 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4527 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4528 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4530 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4532 int nq = min(n, 32);
4533 __be32 *qp = &cmd.iq0_to_iq2;
4535 cmd.niqid = cpu_to_be16(nq);
4536 cmd.startidx = cpu_to_be16(start);
4544 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4545 if (++rsp >= rsp_end)
4547 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4548 if (++rsp >= rsp_end)
4550 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4551 if (++rsp >= rsp_end)
4554 *qp++ = cpu_to_be32(v);
4558 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4566 * t4_config_glbl_rss - configure the global RSS mode
4567 * @adapter: the adapter
4568 * @mbox: mbox to use for the FW command
4569 * @mode: global RSS mode
4570 * @flags: mode-specific flags
4572 * Sets the global RSS mode.
4574 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4577 struct fw_rss_glb_config_cmd c;
4579 memset(&c, 0, sizeof(c));
4580 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4581 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4582 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4583 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4584 c.u.manual.mode_pkd =
4585 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4586 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4587 c.u.basicvirtual.mode_pkd =
4588 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4589 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4592 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4596 * t4_config_vi_rss - configure per VI RSS settings
4597 * @adapter: the adapter
4598 * @mbox: mbox to use for the FW command
4601 * @defq: id of the default RSS queue for the VI.
4603 * Configures VI-specific RSS properties.
4605 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4606 unsigned int flags, unsigned int defq)
4608 struct fw_rss_vi_config_cmd c;
4610 memset(&c, 0, sizeof(c));
4611 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4612 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4613 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4614 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4615 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4616 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4617 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4620 /* Read an RSS table row */
4621 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4623 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4624 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4629 * t4_read_rss - read the contents of the RSS mapping table
4630 * @adapter: the adapter
4631 * @map: holds the contents of the RSS mapping table
4633 * Reads the contents of the RSS hash->queue mapping table.
4635 int t4_read_rss(struct adapter *adapter, u16 *map)
4640 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4641 ret = rd_rss_row(adapter, i, &val);
4644 *map++ = LKPTBLQUEUE0_G(val);
4645 *map++ = LKPTBLQUEUE1_G(val);
4650 static unsigned int t4_use_ldst(struct adapter *adap)
4652 return (adap->flags & FW_OK) || !adap->use_bd;
4656 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4657 * @adap: the adapter
4658 * @vals: where the indirect register values are stored/written
4659 * @nregs: how many indirect registers to read/write
4660 * @start_idx: index of first indirect register to read/write
4661 * @rw: Read (1) or Write (0)
4663 * Access TP PIO registers through LDST
4665 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4666 unsigned int start_index, unsigned int rw)
4669 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4670 struct fw_ldst_cmd c;
4672 for (i = 0 ; i < nregs; i++) {
4673 memset(&c, 0, sizeof(c));
4674 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4676 (rw ? FW_CMD_READ_F :
4678 FW_LDST_CMD_ADDRSPACE_V(cmd));
4679 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4681 c.u.addrval.addr = cpu_to_be32(start_index + i);
4682 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4683 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4685 vals[i] = be32_to_cpu(c.u.addrval.val);
4690 * t4_read_rss_key - read the global RSS key
4691 * @adap: the adapter
4692 * @key: 10-entry array holding the 320-bit RSS key
4694 * Reads the global 320-bit RSS key.
4696 void t4_read_rss_key(struct adapter *adap, u32 *key)
4698 if (t4_use_ldst(adap))
4699 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4701 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4702 TP_RSS_SECRET_KEY0_A);
4706 * t4_write_rss_key - program one of the RSS keys
4707 * @adap: the adapter
4708 * @key: 10-entry array holding the 320-bit RSS key
4709 * @idx: which RSS key to write
4711 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4712 * 0..15 the corresponding entry in the RSS key table is written,
4713 * otherwise the global RSS key is written.
4715 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4717 u8 rss_key_addr_cnt = 16;
4718 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4720 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4721 * allows access to key addresses 16-63 by using KeyWrAddrX
4722 * as index[5:4](upper 2) into key table
4724 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4725 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4726 rss_key_addr_cnt = 32;
4728 if (t4_use_ldst(adap))
4729 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4731 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4732 TP_RSS_SECRET_KEY0_A);
4734 if (idx >= 0 && idx < rss_key_addr_cnt) {
4735 if (rss_key_addr_cnt > 16)
4736 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4737 KEYWRADDRX_V(idx >> 4) |
4738 T6_VFWRADDR_V(idx) | KEYWREN_F);
4740 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4741 KEYWRADDR_V(idx) | KEYWREN_F);
4746 * t4_read_rss_pf_config - read PF RSS Configuration Table
4747 * @adapter: the adapter
4748 * @index: the entry in the PF RSS table to read
4749 * @valp: where to store the returned value
4751 * Reads the PF RSS Configuration Table at the specified index and returns
4752 * the value found there.
4754 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4757 if (t4_use_ldst(adapter))
4758 t4_fw_tp_pio_rw(adapter, valp, 1,
4759 TP_RSS_PF0_CONFIG_A + index, 1);
4761 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4762 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4766 * t4_read_rss_vf_config - read VF RSS Configuration Table
4767 * @adapter: the adapter
4768 * @index: the entry in the VF RSS table to read
4769 * @vfl: where to store the returned VFL
4770 * @vfh: where to store the returned VFH
4772 * Reads the VF RSS Configuration Table at the specified index and returns
4773 * the (VFL, VFH) values found there.
4775 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4778 u32 vrt, mask, data;
4780 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4781 mask = VFWRADDR_V(VFWRADDR_M);
4782 data = VFWRADDR_V(index);
4784 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4785 data = T6_VFWRADDR_V(index);
4788 /* Request that the index'th VF Table values be read into VFL/VFH.
4790 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4791 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4792 vrt |= data | VFRDEN_F;
4793 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4795 /* Grab the VFL/VFH values ...
4797 if (t4_use_ldst(adapter)) {
4798 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4799 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4801 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4802 vfl, 1, TP_RSS_VFL_CONFIG_A);
4803 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4804 vfh, 1, TP_RSS_VFH_CONFIG_A);
4809 * t4_read_rss_pf_map - read PF RSS Map
4810 * @adapter: the adapter
4812 * Reads the PF RSS Map register and returns its value.
4814 u32 t4_read_rss_pf_map(struct adapter *adapter)
4818 if (t4_use_ldst(adapter))
4819 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4821 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4822 &pfmap, 1, TP_RSS_PF_MAP_A);
4827 * t4_read_rss_pf_mask - read PF RSS Mask
4828 * @adapter: the adapter
4830 * Reads the PF RSS Mask register and returns its value.
4832 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4836 if (t4_use_ldst(adapter))
4837 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4839 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4840 &pfmask, 1, TP_RSS_PF_MSK_A);
4845 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4846 * @adap: the adapter
4847 * @v4: holds the TCP/IP counter values
4848 * @v6: holds the TCP/IPv6 counter values
4850 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4851 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4853 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4854 struct tp_tcp_stats *v6)
4856 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4858 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4859 #define STAT(x) val[STAT_IDX(x)]
4860 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4863 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4864 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4865 v4->tcp_out_rsts = STAT(OUT_RST);
4866 v4->tcp_in_segs = STAT64(IN_SEG);
4867 v4->tcp_out_segs = STAT64(OUT_SEG);
4868 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4871 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4872 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4873 v6->tcp_out_rsts = STAT(OUT_RST);
4874 v6->tcp_in_segs = STAT64(IN_SEG);
4875 v6->tcp_out_segs = STAT64(OUT_SEG);
4876 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4884 * t4_tp_get_err_stats - read TP's error MIB counters
4885 * @adap: the adapter
4886 * @st: holds the counter values
4888 * Returns the values of TP's error counters.
4890 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4892 int nchan = adap->params.arch.nchan;
4894 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4895 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4896 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4897 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4898 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4899 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4900 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4901 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4902 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4903 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4904 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4905 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4906 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4907 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4908 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4909 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4911 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4912 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4916 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4917 * @adap: the adapter
4918 * @st: holds the counter values
4920 * Returns the values of TP's CPL counters.
4922 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4924 int nchan = adap->params.arch.nchan;
4926 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4927 nchan, TP_MIB_CPL_IN_REQ_0_A);
4928 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4929 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4934 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4935 * @adap: the adapter
4936 * @st: holds the counter values
4938 * Returns the values of TP's RDMA counters.
4940 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4942 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4943 2, TP_MIB_RQE_DFR_PKT_A);
4947 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4948 * @adap: the adapter
4949 * @idx: the port index
4950 * @st: holds the counter values
4952 * Returns the values of TP's FCoE counters for the selected port.
4954 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4955 struct tp_fcoe_stats *st)
4959 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4960 1, TP_MIB_FCOE_DDP_0_A + idx);
4961 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4962 1, TP_MIB_FCOE_DROP_0_A + idx);
4963 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4964 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4965 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4969 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4970 * @adap: the adapter
4971 * @st: holds the counter values
4973 * Returns the values of TP's counters for non-TCP directly-placed packets.
4975 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4979 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4981 st->frames = val[0];
4983 st->octets = ((u64)val[2] << 32) | val[3];
4987 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4988 * @adap: the adapter
4989 * @mtus: where to store the MTU values
4990 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4992 * Reads the HW path MTU table.
4994 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4999 for (i = 0; i < NMTUS; ++i) {
5000 t4_write_reg(adap, TP_MTU_TABLE_A,
5001 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5002 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5003 mtus[i] = MTUVALUE_G(v);
5005 mtu_log[i] = MTUWIDTH_G(v);
5010 * t4_read_cong_tbl - reads the congestion control table
5011 * @adap: the adapter
5012 * @incr: where to store the alpha values
5014 * Reads the additive increments programmed into the HW congestion
5017 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5019 unsigned int mtu, w;
5021 for (mtu = 0; mtu < NMTUS; ++mtu)
5022 for (w = 0; w < NCCTRL_WIN; ++w) {
5023 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5024 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5025 incr[mtu][w] = (u16)t4_read_reg(adap,
5026 TP_CCTRL_TABLE_A) & 0x1fff;
5031 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5032 * @adap: the adapter
5033 * @addr: the indirect TP register address
5034 * @mask: specifies the field within the register to modify
5035 * @val: new value for the field
5037 * Sets a field of an indirect TP register to the given value.
5039 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5040 unsigned int mask, unsigned int val)
5042 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5043 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5044 t4_write_reg(adap, TP_PIO_DATA_A, val);
5048 * init_cong_ctrl - initialize congestion control parameters
5049 * @a: the alpha values for congestion control
5050 * @b: the beta values for congestion control
5052 * Initialize the congestion control parameters.
5054 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5056 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5081 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5084 b[13] = b[14] = b[15] = b[16] = 3;
5085 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5086 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5091 /* The minimum additive increment value for the congestion control table */
5092 #define CC_MIN_INCR 2U
5095 * t4_load_mtus - write the MTU and congestion control HW tables
5096 * @adap: the adapter
5097 * @mtus: the values for the MTU table
5098 * @alpha: the values for the congestion control alpha parameter
5099 * @beta: the values for the congestion control beta parameter
5101 * Write the HW MTU table with the supplied MTUs and the high-speed
5102 * congestion control table with the supplied alpha, beta, and MTUs.
5103 * We write the two tables together because the additive increments
5104 * depend on the MTUs.
5106 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5107 const unsigned short *alpha, const unsigned short *beta)
5109 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5110 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5111 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5112 28672, 40960, 57344, 81920, 114688, 163840, 229376
5117 for (i = 0; i < NMTUS; ++i) {
5118 unsigned int mtu = mtus[i];
5119 unsigned int log2 = fls(mtu);
5121 if (!(mtu & ((1 << log2) >> 2))) /* round */
5123 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5124 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5126 for (w = 0; w < NCCTRL_WIN; ++w) {
5129 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5132 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5133 (w << 16) | (beta[w] << 13) | inc);
5138 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5139 * clocks. The formula is
5141 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5143 * which is equivalent to
5145 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5147 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5149 u64 v = bytes256 * adap->params.vpd.cclk;
5151 return v * 62 + v / 2;
5155 * t4_get_chan_txrate - get the current per channel Tx rates
5156 * @adap: the adapter
5157 * @nic_rate: rates for NIC traffic
5158 * @ofld_rate: rates for offloaded traffic
5160 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5163 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5167 v = t4_read_reg(adap, TP_TX_TRATE_A);
5168 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5169 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5170 if (adap->params.arch.nchan == NCHAN) {
5171 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5172 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5175 v = t4_read_reg(adap, TP_TX_ORATE_A);
5176 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5177 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5178 if (adap->params.arch.nchan == NCHAN) {
5179 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5180 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5185 * t4_set_trace_filter - configure one of the tracing filters
5186 * @adap: the adapter
5187 * @tp: the desired trace filter parameters
5188 * @idx: which filter to configure
5189 * @enable: whether to enable or disable the filter
5191 * Configures one of the tracing filters available in HW. If @enable is
5192 * %0 @tp is not examined and may be %NULL. The user is responsible to
5193 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5195 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5196 int idx, int enable)
5198 int i, ofst = idx * 4;
5199 u32 data_reg, mask_reg, cfg;
5200 u32 multitrc = TRCMULTIFILTER_F;
5203 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5207 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5208 if (cfg & TRCMULTIFILTER_F) {
5209 /* If multiple tracers are enabled, then maximum
5210 * capture size is 2.5KB (FIFO size of a single channel)
5211 * minus 2 flits for CPL_TRACE_PKT header.
5213 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5216 /* If multiple tracers are disabled, to avoid deadlocks
5217 * maximum packet capture size of 9600 bytes is recommended.
5218 * Also in this mode, only trace0 can be enabled and running.
5221 if (tp->snap_len > 9600 || idx)
5225 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5226 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5227 tp->min_len > TFMINPKTSIZE_M)
5230 /* stop the tracer we'll be changing */
5231 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5233 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5234 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5235 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5237 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5238 t4_write_reg(adap, data_reg, tp->data[i]);
5239 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5241 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5242 TFCAPTUREMAX_V(tp->snap_len) |
5243 TFMINPKTSIZE_V(tp->min_len));
5244 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5245 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5246 (is_t4(adap->params.chip) ?
5247 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5248 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5249 T5_TFINVERTMATCH_V(tp->invert)));
5255 * t4_get_trace_filter - query one of the tracing filters
5256 * @adap: the adapter
5257 * @tp: the current trace filter parameters
5258 * @idx: which trace filter to query
5259 * @enabled: non-zero if the filter is enabled
5261 * Returns the current settings of one of the HW tracing filters.
5263 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5267 int i, ofst = idx * 4;
5268 u32 data_reg, mask_reg;
5270 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5271 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5273 if (is_t4(adap->params.chip)) {
5274 *enabled = !!(ctla & TFEN_F);
5275 tp->port = TFPORT_G(ctla);
5276 tp->invert = !!(ctla & TFINVERTMATCH_F);
5278 *enabled = !!(ctla & T5_TFEN_F);
5279 tp->port = T5_TFPORT_G(ctla);
5280 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5282 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5283 tp->min_len = TFMINPKTSIZE_G(ctlb);
5284 tp->skip_ofst = TFOFFSET_G(ctla);
5285 tp->skip_len = TFLENGTH_G(ctla);
5287 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5288 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5289 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5291 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5292 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5293 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5298 * t4_pmtx_get_stats - returns the HW stats from PMTX
5299 * @adap: the adapter
5300 * @cnt: where to store the count statistics
5301 * @cycles: where to store the cycle statistics
5303 * Returns performance statistics from PMTX.
5305 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5310 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5311 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5312 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5313 if (is_t4(adap->params.chip)) {
5314 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5316 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5317 PM_TX_DBG_DATA_A, data, 2,
5318 PM_TX_DBG_STAT_MSB_A);
5319 cycles[i] = (((u64)data[0] << 32) | data[1]);
5325 * t4_pmrx_get_stats - returns the HW stats from PMRX
5326 * @adap: the adapter
5327 * @cnt: where to store the count statistics
5328 * @cycles: where to store the cycle statistics
5330 * Returns performance statistics from PMRX.
5332 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5337 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5338 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5339 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5340 if (is_t4(adap->params.chip)) {
5341 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5343 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5344 PM_RX_DBG_DATA_A, data, 2,
5345 PM_RX_DBG_STAT_MSB_A);
5346 cycles[i] = (((u64)data[0] << 32) | data[1]);
5352 * t4_get_mps_bg_map - return the buffer groups associated with a port
5353 * @adap: the adapter
5354 * @idx: the port index
5356 * Returns a bitmap indicating which MPS buffer groups are associated
5357 * with the given port. Bit i is set if buffer group i is used by the
5360 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5362 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5365 return idx == 0 ? 0xf : 0;
5366 /* In T6 (which is a 2 port card),
5367 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5368 * For 2 port T4/T5 adapter,
5369 * port 0 is mapped to channel 0 and 1,
5370 * port 1 is mapped to channel 2 and 3.
5373 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5374 return idx < 2 ? (3 << (2 * idx)) : 0;
5379 * t4_get_port_type_description - return Port Type string description
5380 * @port_type: firmware Port Type enumeration
5382 const char *t4_get_port_type_description(enum fw_port_type port_type)
5384 static const char *const port_type_description[] = {
5403 if (port_type < ARRAY_SIZE(port_type_description))
5404 return port_type_description[port_type];
5409 * t4_get_port_stats_offset - collect port stats relative to a previous
5411 * @adap: The adapter
5413 * @stats: Current stats to fill
5414 * @offset: Previous stats snapshot
5416 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5417 struct port_stats *stats,
5418 struct port_stats *offset)
5423 t4_get_port_stats(adap, idx, stats);
5424 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5425 i < (sizeof(struct port_stats) / sizeof(u64));
5431 * t4_get_port_stats - collect port statistics
5432 * @adap: the adapter
5433 * @idx: the port index
5434 * @p: the stats structure to fill
5436 * Collect statistics related to the given port from HW.
5438 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5440 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5442 #define GET_STAT(name) \
5443 t4_read_reg64(adap, \
5444 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5445 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5446 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5448 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5449 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5450 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5451 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5452 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5453 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5454 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5455 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5456 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5457 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5458 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5459 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5460 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5461 p->tx_drop = GET_STAT(TX_PORT_DROP);
5462 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5463 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5464 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5465 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5466 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5467 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5468 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5469 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5470 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5472 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5473 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5474 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5475 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5476 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5477 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5478 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5479 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5480 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5481 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5482 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5483 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5484 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5485 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5486 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5487 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5488 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5489 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5490 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5491 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5492 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5493 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5494 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5495 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5496 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5497 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5498 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5500 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5501 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5502 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5503 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5504 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5505 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5506 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5507 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5514 * t4_get_lb_stats - collect loopback port statistics
5515 * @adap: the adapter
5516 * @idx: the loopback port index
5517 * @p: the stats structure to fill
5519 * Return HW statistics for the given loopback port.
5521 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5523 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5525 #define GET_STAT(name) \
5526 t4_read_reg64(adap, \
5527 (is_t4(adap->params.chip) ? \
5528 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5529 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5530 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5532 p->octets = GET_STAT(BYTES);
5533 p->frames = GET_STAT(FRAMES);
5534 p->bcast_frames = GET_STAT(BCAST);
5535 p->mcast_frames = GET_STAT(MCAST);
5536 p->ucast_frames = GET_STAT(UCAST);
5537 p->error_frames = GET_STAT(ERROR);
5539 p->frames_64 = GET_STAT(64B);
5540 p->frames_65_127 = GET_STAT(65B_127B);
5541 p->frames_128_255 = GET_STAT(128B_255B);
5542 p->frames_256_511 = GET_STAT(256B_511B);
5543 p->frames_512_1023 = GET_STAT(512B_1023B);
5544 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5545 p->frames_1519_max = GET_STAT(1519B_MAX);
5546 p->drop = GET_STAT(DROP_FRAMES);
5548 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5549 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5550 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5551 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5552 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5553 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5554 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5555 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5561 /* t4_mk_filtdelwr - create a delete filter WR
5562 * @ftid: the filter ID
5563 * @wr: the filter work request to populate
5564 * @qid: ingress queue to receive the delete notification
5566 * Creates a filter work request to delete the supplied filter. If @qid is
5567 * negative the delete notification is suppressed.
5569 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5571 memset(wr, 0, sizeof(*wr));
5572 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5573 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5574 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5575 FW_FILTER_WR_NOREPLY_V(qid < 0));
5576 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5578 wr->rx_chan_rx_rpl_iq =
5579 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5582 #define INIT_CMD(var, cmd, rd_wr) do { \
5583 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5584 FW_CMD_REQUEST_F | \
5585 FW_CMD_##rd_wr##_F); \
5586 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5589 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5593 struct fw_ldst_cmd c;
5595 memset(&c, 0, sizeof(c));
5596 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5597 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5601 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5602 c.u.addrval.addr = cpu_to_be32(addr);
5603 c.u.addrval.val = cpu_to_be32(val);
5605 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5609 * t4_mdio_rd - read a PHY register through MDIO
5610 * @adap: the adapter
5611 * @mbox: mailbox to use for the FW command
5612 * @phy_addr: the PHY address
5613 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5614 * @reg: the register to read
5615 * @valp: where to store the value
5617 * Issues a FW command through the given mailbox to read a PHY register.
5619 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5620 unsigned int mmd, unsigned int reg, u16 *valp)
5624 struct fw_ldst_cmd c;
5626 memset(&c, 0, sizeof(c));
5627 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5628 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5629 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5631 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5632 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5633 FW_LDST_CMD_MMD_V(mmd));
5634 c.u.mdio.raddr = cpu_to_be16(reg);
5636 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5638 *valp = be16_to_cpu(c.u.mdio.rval);
5643 * t4_mdio_wr - write a PHY register through MDIO
5644 * @adap: the adapter
5645 * @mbox: mailbox to use for the FW command
5646 * @phy_addr: the PHY address
5647 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5648 * @reg: the register to write
5649 * @valp: value to write
5651 * Issues a FW command through the given mailbox to write a PHY register.
5653 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5654 unsigned int mmd, unsigned int reg, u16 val)
5657 struct fw_ldst_cmd c;
5659 memset(&c, 0, sizeof(c));
5660 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5661 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5662 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5664 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5665 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5666 FW_LDST_CMD_MMD_V(mmd));
5667 c.u.mdio.raddr = cpu_to_be16(reg);
5668 c.u.mdio.rval = cpu_to_be16(val);
5670 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5674 * t4_sge_decode_idma_state - decode the idma state
5675 * @adap: the adapter
5676 * @state: the state idma is stuck in
5678 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5680 static const char * const t4_decode[] = {
5682 "IDMA_PUSH_MORE_CPL_FIFO",
5683 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5685 "IDMA_PHYSADDR_SEND_PCIEHDR",
5686 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5687 "IDMA_PHYSADDR_SEND_PAYLOAD",
5688 "IDMA_SEND_FIFO_TO_IMSG",
5689 "IDMA_FL_REQ_DATA_FL_PREP",
5690 "IDMA_FL_REQ_DATA_FL",
5692 "IDMA_FL_H_REQ_HEADER_FL",
5693 "IDMA_FL_H_SEND_PCIEHDR",
5694 "IDMA_FL_H_PUSH_CPL_FIFO",
5695 "IDMA_FL_H_SEND_CPL",
5696 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5697 "IDMA_FL_H_SEND_IP_HDR",
5698 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5699 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5700 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5701 "IDMA_FL_D_SEND_PCIEHDR",
5702 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5703 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5704 "IDMA_FL_SEND_PCIEHDR",
5705 "IDMA_FL_PUSH_CPL_FIFO",
5707 "IDMA_FL_SEND_PAYLOAD_FIRST",
5708 "IDMA_FL_SEND_PAYLOAD",
5709 "IDMA_FL_REQ_NEXT_DATA_FL",
5710 "IDMA_FL_SEND_NEXT_PCIEHDR",
5711 "IDMA_FL_SEND_PADDING",
5712 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5713 "IDMA_FL_SEND_FIFO_TO_IMSG",
5714 "IDMA_FL_REQ_DATAFL_DONE",
5715 "IDMA_FL_REQ_HEADERFL_DONE",
5717 static const char * const t5_decode[] = {
5720 "IDMA_PUSH_MORE_CPL_FIFO",
5721 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5722 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5723 "IDMA_PHYSADDR_SEND_PCIEHDR",
5724 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5725 "IDMA_PHYSADDR_SEND_PAYLOAD",
5726 "IDMA_SEND_FIFO_TO_IMSG",
5727 "IDMA_FL_REQ_DATA_FL",
5729 "IDMA_FL_DROP_SEND_INC",
5730 "IDMA_FL_H_REQ_HEADER_FL",
5731 "IDMA_FL_H_SEND_PCIEHDR",
5732 "IDMA_FL_H_PUSH_CPL_FIFO",
5733 "IDMA_FL_H_SEND_CPL",
5734 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5735 "IDMA_FL_H_SEND_IP_HDR",
5736 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5737 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5738 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5739 "IDMA_FL_D_SEND_PCIEHDR",
5740 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5741 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5742 "IDMA_FL_SEND_PCIEHDR",
5743 "IDMA_FL_PUSH_CPL_FIFO",
5745 "IDMA_FL_SEND_PAYLOAD_FIRST",
5746 "IDMA_FL_SEND_PAYLOAD",
5747 "IDMA_FL_REQ_NEXT_DATA_FL",
5748 "IDMA_FL_SEND_NEXT_PCIEHDR",
5749 "IDMA_FL_SEND_PADDING",
5750 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5752 static const char * const t6_decode[] = {
5754 "IDMA_PUSH_MORE_CPL_FIFO",
5755 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5756 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5757 "IDMA_PHYSADDR_SEND_PCIEHDR",
5758 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5759 "IDMA_PHYSADDR_SEND_PAYLOAD",
5760 "IDMA_FL_REQ_DATA_FL",
5762 "IDMA_FL_DROP_SEND_INC",
5763 "IDMA_FL_H_REQ_HEADER_FL",
5764 "IDMA_FL_H_SEND_PCIEHDR",
5765 "IDMA_FL_H_PUSH_CPL_FIFO",
5766 "IDMA_FL_H_SEND_CPL",
5767 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5768 "IDMA_FL_H_SEND_IP_HDR",
5769 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5770 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5771 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5772 "IDMA_FL_D_SEND_PCIEHDR",
5773 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5774 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5775 "IDMA_FL_SEND_PCIEHDR",
5776 "IDMA_FL_PUSH_CPL_FIFO",
5778 "IDMA_FL_SEND_PAYLOAD_FIRST",
5779 "IDMA_FL_SEND_PAYLOAD",
5780 "IDMA_FL_REQ_NEXT_DATA_FL",
5781 "IDMA_FL_SEND_NEXT_PCIEHDR",
5782 "IDMA_FL_SEND_PADDING",
5783 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5785 static const u32 sge_regs[] = {
5786 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5787 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5788 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5790 const char **sge_idma_decode;
5791 int sge_idma_decode_nstates;
5793 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5795 /* Select the right set of decode strings to dump depending on the
5796 * adapter chip type.
5798 switch (chip_version) {
5800 sge_idma_decode = (const char **)t4_decode;
5801 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5805 sge_idma_decode = (const char **)t5_decode;
5806 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5810 sge_idma_decode = (const char **)t6_decode;
5811 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5815 dev_err(adapter->pdev_dev,
5816 "Unsupported chip version %d\n", chip_version);
5820 if (is_t4(adapter->params.chip)) {
5821 sge_idma_decode = (const char **)t4_decode;
5822 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5824 sge_idma_decode = (const char **)t5_decode;
5825 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5828 if (state < sge_idma_decode_nstates)
5829 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5831 CH_WARN(adapter, "idma state %d unknown\n", state);
5833 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5834 CH_WARN(adapter, "SGE register %#x value %#x\n",
5835 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5839 * t4_sge_ctxt_flush - flush the SGE context cache
5840 * @adap: the adapter
5841 * @mbox: mailbox to use for the FW command
5843 * Issues a FW command through the given mailbox to flush the
5844 * SGE context cache.
5846 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5850 struct fw_ldst_cmd c;
5852 memset(&c, 0, sizeof(c));
5853 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5854 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5855 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5857 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5858 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5860 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5865 * t4_fw_hello - establish communication with FW
5866 * @adap: the adapter
5867 * @mbox: mailbox to use for the FW command
5868 * @evt_mbox: mailbox to receive async FW events
5869 * @master: specifies the caller's willingness to be the device master
5870 * @state: returns the current device state (if non-NULL)
5872 * Issues a command to establish communication with FW. Returns either
5873 * an error (negative integer) or the mailbox of the Master PF.
5875 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5876 enum dev_master master, enum dev_state *state)
5879 struct fw_hello_cmd c;
5881 unsigned int master_mbox;
5882 int retries = FW_CMD_HELLO_RETRIES;
5885 memset(&c, 0, sizeof(c));
5886 INIT_CMD(c, HELLO, WRITE);
5887 c.err_to_clearinit = cpu_to_be32(
5888 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5889 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5890 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5891 mbox : FW_HELLO_CMD_MBMASTER_M) |
5892 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5893 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5894 FW_HELLO_CMD_CLEARINIT_F);
5897 * Issue the HELLO command to the firmware. If it's not successful
5898 * but indicates that we got a "busy" or "timeout" condition, retry
5899 * the HELLO until we exhaust our retry limit. If we do exceed our
5900 * retry limit, check to see if the firmware left us any error
5901 * information and report that if so.
5903 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5905 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5907 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5908 t4_report_fw_error(adap);
5912 v = be32_to_cpu(c.err_to_clearinit);
5913 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5915 if (v & FW_HELLO_CMD_ERR_F)
5916 *state = DEV_STATE_ERR;
5917 else if (v & FW_HELLO_CMD_INIT_F)
5918 *state = DEV_STATE_INIT;
5920 *state = DEV_STATE_UNINIT;
5924 * If we're not the Master PF then we need to wait around for the
5925 * Master PF Driver to finish setting up the adapter.
5927 * Note that we also do this wait if we're a non-Master-capable PF and
5928 * there is no current Master PF; a Master PF may show up momentarily
5929 * and we wouldn't want to fail pointlessly. (This can happen when an
5930 * OS loads lots of different drivers rapidly at the same time). In
5931 * this case, the Master PF returned by the firmware will be
5932 * PCIE_FW_MASTER_M so the test below will work ...
5934 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5935 master_mbox != mbox) {
5936 int waiting = FW_CMD_HELLO_TIMEOUT;
5939 * Wait for the firmware to either indicate an error or
5940 * initialized state. If we see either of these we bail out
5941 * and report the issue to the caller. If we exhaust the
5942 * "hello timeout" and we haven't exhausted our retries, try
5943 * again. Otherwise bail with a timeout error.
5952 * If neither Error nor Initialialized are indicated
5953 * by the firmware keep waiting till we exaust our
5954 * timeout ... and then retry if we haven't exhausted
5957 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5958 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5969 * We either have an Error or Initialized condition
5970 * report errors preferentially.
5973 if (pcie_fw & PCIE_FW_ERR_F)
5974 *state = DEV_STATE_ERR;
5975 else if (pcie_fw & PCIE_FW_INIT_F)
5976 *state = DEV_STATE_INIT;
5980 * If we arrived before a Master PF was selected and
5981 * there's not a valid Master PF, grab its identity
5984 if (master_mbox == PCIE_FW_MASTER_M &&
5985 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5986 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5995 * t4_fw_bye - end communication with FW
5996 * @adap: the adapter
5997 * @mbox: mailbox to use for the FW command
5999 * Issues a command to terminate communication with FW.
6001 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6003 struct fw_bye_cmd c;
6005 memset(&c, 0, sizeof(c));
6006 INIT_CMD(c, BYE, WRITE);
6007 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6011 * t4_init_cmd - ask FW to initialize the device
6012 * @adap: the adapter
6013 * @mbox: mailbox to use for the FW command
6015 * Issues a command to FW to partially initialize the device. This
6016 * performs initialization that generally doesn't depend on user input.
6018 int t4_early_init(struct adapter *adap, unsigned int mbox)
6020 struct fw_initialize_cmd c;
6022 memset(&c, 0, sizeof(c));
6023 INIT_CMD(c, INITIALIZE, WRITE);
6024 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6028 * t4_fw_reset - issue a reset to FW
6029 * @adap: the adapter
6030 * @mbox: mailbox to use for the FW command
6031 * @reset: specifies the type of reset to perform
6033 * Issues a reset command of the specified type to FW.
6035 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6037 struct fw_reset_cmd c;
6039 memset(&c, 0, sizeof(c));
6040 INIT_CMD(c, RESET, WRITE);
6041 c.val = cpu_to_be32(reset);
6042 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6046 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6047 * @adap: the adapter
6048 * @mbox: mailbox to use for the FW RESET command (if desired)
6049 * @force: force uP into RESET even if FW RESET command fails
6051 * Issues a RESET command to firmware (if desired) with a HALT indication
6052 * and then puts the microprocessor into RESET state. The RESET command
6053 * will only be issued if a legitimate mailbox is provided (mbox <=
6054 * PCIE_FW_MASTER_M).
6056 * This is generally used in order for the host to safely manipulate the
6057 * adapter without fear of conflicting with whatever the firmware might
6058 * be doing. The only way out of this state is to RESTART the firmware
6061 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6066 * If a legitimate mailbox is provided, issue a RESET command
6067 * with a HALT indication.
6069 if (mbox <= PCIE_FW_MASTER_M) {
6070 struct fw_reset_cmd c;
6072 memset(&c, 0, sizeof(c));
6073 INIT_CMD(c, RESET, WRITE);
6074 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6075 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6076 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6080 * Normally we won't complete the operation if the firmware RESET
6081 * command fails but if our caller insists we'll go ahead and put the
6082 * uP into RESET. This can be useful if the firmware is hung or even
6083 * missing ... We'll have to take the risk of putting the uP into
6084 * RESET without the cooperation of firmware in that case.
6086 * We also force the firmware's HALT flag to be on in case we bypassed
6087 * the firmware RESET command above or we're dealing with old firmware
6088 * which doesn't have the HALT capability. This will serve as a flag
6089 * for the incoming firmware to know that it's coming out of a HALT
6090 * rather than a RESET ... if it's new enough to understand that ...
6092 if (ret == 0 || force) {
6093 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6094 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6099 * And we always return the result of the firmware RESET command
6100 * even when we force the uP into RESET ...
6106 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6107 * @adap: the adapter
6108 * @reset: if we want to do a RESET to restart things
6110 * Restart firmware previously halted by t4_fw_halt(). On successful
6111 * return the previous PF Master remains as the new PF Master and there
6112 * is no need to issue a new HELLO command, etc.
6114 * We do this in two ways:
6116 * 1. If we're dealing with newer firmware we'll simply want to take
6117 * the chip's microprocessor out of RESET. This will cause the
6118 * firmware to start up from its start vector. And then we'll loop
6119 * until the firmware indicates it's started again (PCIE_FW.HALT
6120 * reset to 0) or we timeout.
6122 * 2. If we're dealing with older firmware then we'll need to RESET
6123 * the chip since older firmware won't recognize the PCIE_FW.HALT
6124 * flag and automatically RESET itself on startup.
6126 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6130 * Since we're directing the RESET instead of the firmware
6131 * doing it automatically, we need to clear the PCIE_FW.HALT
6134 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6137 * If we've been given a valid mailbox, first try to get the
6138 * firmware to do the RESET. If that works, great and we can
6139 * return success. Otherwise, if we haven't been given a
6140 * valid mailbox or the RESET command failed, fall back to
6141 * hitting the chip with a hammer.
6143 if (mbox <= PCIE_FW_MASTER_M) {
6144 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6146 if (t4_fw_reset(adap, mbox,
6147 PIORST_F | PIORSTMODE_F) == 0)
6151 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6156 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6157 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6158 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6169 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6170 * @adap: the adapter
6171 * @mbox: mailbox to use for the FW RESET command (if desired)
6172 * @fw_data: the firmware image to write
6174 * @force: force upgrade even if firmware doesn't cooperate
6176 * Perform all of the steps necessary for upgrading an adapter's
6177 * firmware image. Normally this requires the cooperation of the
6178 * existing firmware in order to halt all existing activities
6179 * but if an invalid mailbox token is passed in we skip that step
6180 * (though we'll still put the adapter microprocessor into RESET in
6183 * On successful return the new firmware will have been loaded and
6184 * the adapter will have been fully RESET losing all previous setup
6185 * state. On unsuccessful return the adapter may be completely hosed ...
6186 * positive errno indicates that the adapter is ~probably~ intact, a
6187 * negative errno indicates that things are looking bad ...
6189 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6190 const u8 *fw_data, unsigned int size, int force)
6192 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6195 if (!t4_fw_matches_chip(adap, fw_hdr))
6198 ret = t4_fw_halt(adap, mbox, force);
6199 if (ret < 0 && !force)
6202 ret = t4_load_fw(adap, fw_data, size);
6207 * Older versions of the firmware don't understand the new
6208 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6209 * restart. So for newly loaded older firmware we'll have to do the
6210 * RESET for it so it starts up on a clean slate. We can tell if
6211 * the newly loaded firmware will handle this right by checking
6212 * its header flags to see if it advertises the capability.
6214 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6215 return t4_fw_restart(adap, mbox, reset);
6219 * t4_fl_pkt_align - return the fl packet alignment
6220 * @adap: the adapter
6222 * T4 has a single field to specify the packing and padding boundary.
6223 * T5 onwards has separate fields for this and hence the alignment for
6224 * next packet offset is maximum of these two.
6227 int t4_fl_pkt_align(struct adapter *adap)
6229 u32 sge_control, sge_control2;
6230 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6232 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6234 /* T4 uses a single control field to specify both the PCIe Padding and
6235 * Packing Boundary. T5 introduced the ability to specify these
6236 * separately. The actual Ingress Packet Data alignment boundary
6237 * within Packed Buffer Mode is the maximum of these two
6238 * specifications. (Note that it makes no real practical sense to
6239 * have the Pading Boudary be larger than the Packing Boundary but you
6240 * could set the chip up that way and, in fact, legacy T4 code would
6241 * end doing this because it would initialize the Padding Boundary and
6242 * leave the Packing Boundary initialized to 0 (16 bytes).)
6243 * Padding Boundary values in T6 starts from 8B,
6244 * where as it is 32B for T4 and T5.
6246 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6247 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6249 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6251 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6253 fl_align = ingpadboundary;
6254 if (!is_t4(adap->params.chip)) {
6255 /* T5 has a weird interpretation of one of the PCIe Packing
6256 * Boundary values. No idea why ...
6258 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6259 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6260 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6261 ingpackboundary = 16;
6263 ingpackboundary = 1 << (ingpackboundary +
6264 INGPACKBOUNDARY_SHIFT_X);
6266 fl_align = max(ingpadboundary, ingpackboundary);
6272 * t4_fixup_host_params - fix up host-dependent parameters
6273 * @adap: the adapter
6274 * @page_size: the host's Base Page Size
6275 * @cache_line_size: the host's Cache Line Size
6277 * Various registers in T4 contain values which are dependent on the
6278 * host's Base Page and Cache Line Sizes. This function will fix all of
6279 * those registers with the appropriate values as passed in ...
6281 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6282 unsigned int cache_line_size)
6284 unsigned int page_shift = fls(page_size) - 1;
6285 unsigned int sge_hps = page_shift - 10;
6286 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6287 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6288 unsigned int fl_align_log = fls(fl_align) - 1;
6289 unsigned int ingpad;
6291 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6292 HOSTPAGESIZEPF0_V(sge_hps) |
6293 HOSTPAGESIZEPF1_V(sge_hps) |
6294 HOSTPAGESIZEPF2_V(sge_hps) |
6295 HOSTPAGESIZEPF3_V(sge_hps) |
6296 HOSTPAGESIZEPF4_V(sge_hps) |
6297 HOSTPAGESIZEPF5_V(sge_hps) |
6298 HOSTPAGESIZEPF6_V(sge_hps) |
6299 HOSTPAGESIZEPF7_V(sge_hps));
6301 if (is_t4(adap->params.chip)) {
6302 t4_set_reg_field(adap, SGE_CONTROL_A,
6303 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6304 EGRSTATUSPAGESIZE_F,
6305 INGPADBOUNDARY_V(fl_align_log -
6306 INGPADBOUNDARY_SHIFT_X) |
6307 EGRSTATUSPAGESIZE_V(stat_len != 64));
6309 /* T5 introduced the separation of the Free List Padding and
6310 * Packing Boundaries. Thus, we can select a smaller Padding
6311 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6312 * Bandwidth, and use a Packing Boundary which is large enough
6313 * to avoid false sharing between CPUs, etc.
6315 * For the PCI Link, the smaller the Padding Boundary the
6316 * better. For the Memory Controller, a smaller Padding
6317 * Boundary is better until we cross under the Memory Line
6318 * Size (the minimum unit of transfer to/from Memory). If we
6319 * have a Padding Boundary which is smaller than the Memory
6320 * Line Size, that'll involve a Read-Modify-Write cycle on the
6321 * Memory Controller which is never good. For T5 the smallest
6322 * Padding Boundary which we can select is 32 bytes which is
6323 * larger than any known Memory Controller Line Size so we'll
6326 * T5 has a different interpretation of the "0" value for the
6327 * Packing Boundary. This corresponds to 16 bytes instead of
6328 * the expected 32 bytes. We never have a Packing Boundary
6329 * less than 32 bytes so we can't use that special value but
6330 * on the other hand, if we wanted 32 bytes, the best we can
6331 * really do is 64 bytes.
6333 if (fl_align <= 32) {
6338 if (is_t5(adap->params.chip))
6339 ingpad = INGPCIEBOUNDARY_32B_X;
6341 ingpad = T6_INGPADBOUNDARY_32B_X;
6343 t4_set_reg_field(adap, SGE_CONTROL_A,
6344 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6345 EGRSTATUSPAGESIZE_F,
6346 INGPADBOUNDARY_V(ingpad) |
6347 EGRSTATUSPAGESIZE_V(stat_len != 64));
6348 t4_set_reg_field(adap, SGE_CONTROL2_A,
6349 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6350 INGPACKBOUNDARY_V(fl_align_log -
6351 INGPACKBOUNDARY_SHIFT_X));
6354 * Adjust various SGE Free List Host Buffer Sizes.
6356 * This is something of a crock since we're using fixed indices into
6357 * the array which are also known by the sge.c code and the T4
6358 * Firmware Configuration File. We need to come up with a much better
6359 * approach to managing this array. For now, the first four entries
6364 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6365 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6367 * For the single-MTU buffers in unpacked mode we need to include
6368 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6369 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6370 * Padding boundary. All of these are accommodated in the Factory
6371 * Default Firmware Configuration File but we need to adjust it for
6372 * this host's cache line size.
6374 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6375 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6376 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6378 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6379 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6382 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6388 * t4_fw_initialize - ask FW to initialize the device
6389 * @adap: the adapter
6390 * @mbox: mailbox to use for the FW command
6392 * Issues a command to FW to partially initialize the device. This
6393 * performs initialization that generally doesn't depend on user input.
6395 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6397 struct fw_initialize_cmd c;
6399 memset(&c, 0, sizeof(c));
6400 INIT_CMD(c, INITIALIZE, WRITE);
6401 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6405 * t4_query_params_rw - query FW or device parameters
6406 * @adap: the adapter
6407 * @mbox: mailbox to use for the FW command
6410 * @nparams: the number of parameters
6411 * @params: the parameter names
6412 * @val: the parameter values
6413 * @rw: Write and read flag
6415 * Reads the value of FW or device parameters. Up to 7 parameters can be
6418 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6419 unsigned int vf, unsigned int nparams, const u32 *params,
6423 struct fw_params_cmd c;
6424 __be32 *p = &c.param[0].mnem;
6429 memset(&c, 0, sizeof(c));
6430 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6431 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6432 FW_PARAMS_CMD_PFN_V(pf) |
6433 FW_PARAMS_CMD_VFN_V(vf));
6434 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6436 for (i = 0; i < nparams; i++) {
6437 *p++ = cpu_to_be32(*params++);
6439 *p = cpu_to_be32(*(val + i));
6443 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6445 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6446 *val++ = be32_to_cpu(*p);
6450 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6451 unsigned int vf, unsigned int nparams, const u32 *params,
6454 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6458 * t4_set_params_timeout - sets FW or device parameters
6459 * @adap: the adapter
6460 * @mbox: mailbox to use for the FW command
6463 * @nparams: the number of parameters
6464 * @params: the parameter names
6465 * @val: the parameter values
6466 * @timeout: the timeout time
6468 * Sets the value of FW or device parameters. Up to 7 parameters can be
6469 * specified at once.
6471 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6472 unsigned int pf, unsigned int vf,
6473 unsigned int nparams, const u32 *params,
6474 const u32 *val, int timeout)
6476 struct fw_params_cmd c;
6477 __be32 *p = &c.param[0].mnem;
6482 memset(&c, 0, sizeof(c));
6483 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6484 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6485 FW_PARAMS_CMD_PFN_V(pf) |
6486 FW_PARAMS_CMD_VFN_V(vf));
6487 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6490 *p++ = cpu_to_be32(*params++);
6491 *p++ = cpu_to_be32(*val++);
6494 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6498 * t4_set_params - sets FW or device parameters
6499 * @adap: the adapter
6500 * @mbox: mailbox to use for the FW command
6503 * @nparams: the number of parameters
6504 * @params: the parameter names
6505 * @val: the parameter values
6507 * Sets the value of FW or device parameters. Up to 7 parameters can be
6508 * specified at once.
6510 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6511 unsigned int vf, unsigned int nparams, const u32 *params,
6514 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6515 FW_CMD_MAX_TIMEOUT);
6519 * t4_cfg_pfvf - configure PF/VF resource limits
6520 * @adap: the adapter
6521 * @mbox: mailbox to use for the FW command
6522 * @pf: the PF being configured
6523 * @vf: the VF being configured
6524 * @txq: the max number of egress queues
6525 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6526 * @rxqi: the max number of interrupt-capable ingress queues
6527 * @rxq: the max number of interruptless ingress queues
6528 * @tc: the PCI traffic class
6529 * @vi: the max number of virtual interfaces
6530 * @cmask: the channel access rights mask for the PF/VF
6531 * @pmask: the port access rights mask for the PF/VF
6532 * @nexact: the maximum number of exact MPS filters
6533 * @rcaps: read capabilities
6534 * @wxcaps: write/execute capabilities
6536 * Configures resource limits and capabilities for a physical or virtual
6539 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6540 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6541 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6542 unsigned int vi, unsigned int cmask, unsigned int pmask,
6543 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6545 struct fw_pfvf_cmd c;
6547 memset(&c, 0, sizeof(c));
6548 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6549 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6550 FW_PFVF_CMD_VFN_V(vf));
6551 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6552 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6553 FW_PFVF_CMD_NIQ_V(rxq));
6554 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6555 FW_PFVF_CMD_PMASK_V(pmask) |
6556 FW_PFVF_CMD_NEQ_V(txq));
6557 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6558 FW_PFVF_CMD_NVI_V(vi) |
6559 FW_PFVF_CMD_NEXACTF_V(nexact));
6560 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6561 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6562 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6563 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6567 * t4_alloc_vi - allocate a virtual interface
6568 * @adap: the adapter
6569 * @mbox: mailbox to use for the FW command
6570 * @port: physical port associated with the VI
6571 * @pf: the PF owning the VI
6572 * @vf: the VF owning the VI
6573 * @nmac: number of MAC addresses needed (1 to 5)
6574 * @mac: the MAC addresses of the VI
6575 * @rss_size: size of RSS table slice associated with this VI
6577 * Allocates a virtual interface for the given physical port. If @mac is
6578 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6579 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6580 * stored consecutively so the space needed is @nmac * 6 bytes.
6581 * Returns a negative error number or the non-negative VI id.
6583 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6584 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6585 unsigned int *rss_size)
6590 memset(&c, 0, sizeof(c));
6591 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6592 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6593 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6594 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6595 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6598 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6603 memcpy(mac, c.mac, sizeof(c.mac));
6606 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6608 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6610 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6612 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6616 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6617 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6621 * t4_free_vi - free a virtual interface
6622 * @adap: the adapter
6623 * @mbox: mailbox to use for the FW command
6624 * @pf: the PF owning the VI
6625 * @vf: the VF owning the VI
6626 * @viid: virtual interface identifiler
6628 * Free a previously allocated virtual interface.
6630 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6631 unsigned int vf, unsigned int viid)
6635 memset(&c, 0, sizeof(c));
6636 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6639 FW_VI_CMD_PFN_V(pf) |
6640 FW_VI_CMD_VFN_V(vf));
6641 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6642 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6644 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6648 * t4_set_rxmode - set Rx properties of a virtual interface
6649 * @adap: the adapter
6650 * @mbox: mailbox to use for the FW command
6652 * @mtu: the new MTU or -1
6653 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6654 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6655 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6656 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6657 * @sleep_ok: if true we may sleep while awaiting command completion
6659 * Sets Rx properties of a virtual interface.
6661 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6662 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6665 struct fw_vi_rxmode_cmd c;
6667 /* convert to FW values */
6669 mtu = FW_RXMODE_MTU_NO_CHG;
6671 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6673 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6675 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6677 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6679 memset(&c, 0, sizeof(c));
6680 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6681 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6682 FW_VI_RXMODE_CMD_VIID_V(viid));
6683 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6685 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6686 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6687 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6688 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6689 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6690 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6694 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6695 * @adap: the adapter
6696 * @mbox: mailbox to use for the FW command
6698 * @free: if true any existing filters for this VI id are first removed
6699 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6700 * @addr: the MAC address(es)
6701 * @idx: where to store the index of each allocated filter
6702 * @hash: pointer to hash address filter bitmap
6703 * @sleep_ok: call is allowed to sleep
6705 * Allocates an exact-match filter for each of the supplied addresses and
6706 * sets it to the corresponding address. If @idx is not %NULL it should
6707 * have at least @naddr entries, each of which will be set to the index of
6708 * the filter allocated for the corresponding MAC address. If a filter
6709 * could not be allocated for an address its index is set to 0xffff.
6710 * If @hash is not %NULL addresses that fail to allocate an exact filter
6711 * are hashed and update the hash filter bitmap pointed at by @hash.
6713 * Returns a negative error number or the number of filters allocated.
6715 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6716 unsigned int viid, bool free, unsigned int naddr,
6717 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6719 int offset, ret = 0;
6720 struct fw_vi_mac_cmd c;
6721 unsigned int nfilters = 0;
6722 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6723 unsigned int rem = naddr;
6725 if (naddr > max_naddr)
6728 for (offset = 0; offset < naddr ; /**/) {
6729 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6730 rem : ARRAY_SIZE(c.u.exact));
6731 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6732 u.exact[fw_naddr]), 16);
6733 struct fw_vi_mac_exact *p;
6736 memset(&c, 0, sizeof(c));
6737 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6740 FW_CMD_EXEC_V(free) |
6741 FW_VI_MAC_CMD_VIID_V(viid));
6742 c.freemacs_to_len16 =
6743 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6744 FW_CMD_LEN16_V(len16));
6746 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6748 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6749 FW_VI_MAC_CMD_IDX_V(
6750 FW_VI_MAC_ADD_MAC));
6751 memcpy(p->macaddr, addr[offset + i],
6752 sizeof(p->macaddr));
6755 /* It's okay if we run out of space in our MAC address arena.
6756 * Some of the addresses we submit may get stored so we need
6757 * to run through the reply to see what the results were ...
6759 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6760 if (ret && ret != -FW_ENOMEM)
6763 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6764 u16 index = FW_VI_MAC_CMD_IDX_G(
6765 be16_to_cpu(p->valid_to_idx));
6768 idx[offset + i] = (index >= max_naddr ?
6770 if (index < max_naddr)
6774 hash_mac_addr(addr[offset + i]));
6782 if (ret == 0 || ret == -FW_ENOMEM)
6788 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6789 * @adap: the adapter
6790 * @mbox: mailbox to use for the FW command
6792 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6793 * @addr: the MAC address(es)
6794 * @sleep_ok: call is allowed to sleep
6796 * Frees the exact-match filter for each of the supplied addresses
6798 * Returns a negative error number or the number of filters freed.
6800 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6801 unsigned int viid, unsigned int naddr,
6802 const u8 **addr, bool sleep_ok)
6804 int offset, ret = 0;
6805 struct fw_vi_mac_cmd c;
6806 unsigned int nfilters = 0;
6807 unsigned int max_naddr = is_t4(adap->params.chip) ?
6808 NUM_MPS_CLS_SRAM_L_INSTANCES :
6809 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6810 unsigned int rem = naddr;
6812 if (naddr > max_naddr)
6815 for (offset = 0; offset < (int)naddr ; /**/) {
6816 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6818 : ARRAY_SIZE(c.u.exact));
6819 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6820 u.exact[fw_naddr]), 16);
6821 struct fw_vi_mac_exact *p;
6824 memset(&c, 0, sizeof(c));
6825 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6829 FW_VI_MAC_CMD_VIID_V(viid));
6830 c.freemacs_to_len16 =
6831 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6832 FW_CMD_LEN16_V(len16));
6834 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6835 p->valid_to_idx = cpu_to_be16(
6836 FW_VI_MAC_CMD_VALID_F |
6837 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6838 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6841 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6845 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6846 u16 index = FW_VI_MAC_CMD_IDX_G(
6847 be16_to_cpu(p->valid_to_idx));
6849 if (index < max_naddr)
6863 * t4_change_mac - modifies the exact-match filter for a MAC address
6864 * @adap: the adapter
6865 * @mbox: mailbox to use for the FW command
6867 * @idx: index of existing filter for old value of MAC address, or -1
6868 * @addr: the new MAC address value
6869 * @persist: whether a new MAC allocation should be persistent
6870 * @add_smt: if true also add the address to the HW SMT
6872 * Modifies an exact-match filter and sets it to the new MAC address.
6873 * Note that in general it is not possible to modify the value of a given
6874 * filter so the generic way to modify an address filter is to free the one
6875 * being used by the old address value and allocate a new filter for the
6876 * new address value. @idx can be -1 if the address is a new addition.
6878 * Returns a negative error number or the index of the filter with the new
6881 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6882 int idx, const u8 *addr, bool persist, bool add_smt)
6885 struct fw_vi_mac_cmd c;
6886 struct fw_vi_mac_exact *p = c.u.exact;
6887 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6889 if (idx < 0) /* new allocation */
6890 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6891 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6893 memset(&c, 0, sizeof(c));
6894 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6895 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6896 FW_VI_MAC_CMD_VIID_V(viid));
6897 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6898 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6899 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6900 FW_VI_MAC_CMD_IDX_V(idx));
6901 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6903 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6905 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6906 if (ret >= max_mac_addr)
6913 * t4_set_addr_hash - program the MAC inexact-match hash filter
6914 * @adap: the adapter
6915 * @mbox: mailbox to use for the FW command
6917 * @ucast: whether the hash filter should also match unicast addresses
6918 * @vec: the value to be written to the hash filter
6919 * @sleep_ok: call is allowed to sleep
6921 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6923 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6924 bool ucast, u64 vec, bool sleep_ok)
6926 struct fw_vi_mac_cmd c;
6928 memset(&c, 0, sizeof(c));
6929 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6930 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6931 FW_VI_ENABLE_CMD_VIID_V(viid));
6932 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6933 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6935 c.u.hash.hashvec = cpu_to_be64(vec);
6936 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6940 * t4_enable_vi_params - enable/disable a virtual interface
6941 * @adap: the adapter
6942 * @mbox: mailbox to use for the FW command
6944 * @rx_en: 1=enable Rx, 0=disable Rx
6945 * @tx_en: 1=enable Tx, 0=disable Tx
6946 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6948 * Enables/disables a virtual interface. Note that setting DCB Enable
6949 * only makes sense when enabling a Virtual Interface ...
6951 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6952 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6954 struct fw_vi_enable_cmd c;
6956 memset(&c, 0, sizeof(c));
6957 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6958 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6959 FW_VI_ENABLE_CMD_VIID_V(viid));
6960 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6961 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6962 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6964 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6968 * t4_enable_vi - enable/disable a virtual interface
6969 * @adap: the adapter
6970 * @mbox: mailbox to use for the FW command
6972 * @rx_en: 1=enable Rx, 0=disable Rx
6973 * @tx_en: 1=enable Tx, 0=disable Tx
6975 * Enables/disables a virtual interface.
6977 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6978 bool rx_en, bool tx_en)
6980 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6984 * t4_identify_port - identify a VI's port by blinking its LED
6985 * @adap: the adapter
6986 * @mbox: mailbox to use for the FW command
6988 * @nblinks: how many times to blink LED at 2.5 Hz
6990 * Identifies a VI's port by blinking its LED.
6992 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6993 unsigned int nblinks)
6995 struct fw_vi_enable_cmd c;
6997 memset(&c, 0, sizeof(c));
6998 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6999 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7000 FW_VI_ENABLE_CMD_VIID_V(viid));
7001 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7002 c.blinkdur = cpu_to_be16(nblinks);
7003 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7007 * t4_iq_stop - stop an ingress queue and its FLs
7008 * @adap: the adapter
7009 * @mbox: mailbox to use for the FW command
7010 * @pf: the PF owning the queues
7011 * @vf: the VF owning the queues
7012 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7013 * @iqid: ingress queue id
7014 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7015 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7017 * Stops an ingress queue and its associated FLs, if any. This causes
7018 * any current or future data/messages destined for these queues to be
7021 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7022 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7023 unsigned int fl0id, unsigned int fl1id)
7027 memset(&c, 0, sizeof(c));
7028 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7029 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7030 FW_IQ_CMD_VFN_V(vf));
7031 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7032 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7033 c.iqid = cpu_to_be16(iqid);
7034 c.fl0id = cpu_to_be16(fl0id);
7035 c.fl1id = cpu_to_be16(fl1id);
7036 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7040 * t4_iq_free - free an ingress queue and its FLs
7041 * @adap: the adapter
7042 * @mbox: mailbox to use for the FW command
7043 * @pf: the PF owning the queues
7044 * @vf: the VF owning the queues
7045 * @iqtype: the ingress queue type
7046 * @iqid: ingress queue id
7047 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7048 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7050 * Frees an ingress queue and its associated FLs, if any.
7052 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7053 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7054 unsigned int fl0id, unsigned int fl1id)
7058 memset(&c, 0, sizeof(c));
7059 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7060 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7061 FW_IQ_CMD_VFN_V(vf));
7062 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7063 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7064 c.iqid = cpu_to_be16(iqid);
7065 c.fl0id = cpu_to_be16(fl0id);
7066 c.fl1id = cpu_to_be16(fl1id);
7067 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7071 * t4_eth_eq_free - free an Ethernet egress queue
7072 * @adap: the adapter
7073 * @mbox: mailbox to use for the FW command
7074 * @pf: the PF owning the queue
7075 * @vf: the VF owning the queue
7076 * @eqid: egress queue id
7078 * Frees an Ethernet egress queue.
7080 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7081 unsigned int vf, unsigned int eqid)
7083 struct fw_eq_eth_cmd c;
7085 memset(&c, 0, sizeof(c));
7086 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7087 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7088 FW_EQ_ETH_CMD_PFN_V(pf) |
7089 FW_EQ_ETH_CMD_VFN_V(vf));
7090 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7091 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7092 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7096 * t4_ctrl_eq_free - free a control egress queue
7097 * @adap: the adapter
7098 * @mbox: mailbox to use for the FW command
7099 * @pf: the PF owning the queue
7100 * @vf: the VF owning the queue
7101 * @eqid: egress queue id
7103 * Frees a control egress queue.
7105 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7106 unsigned int vf, unsigned int eqid)
7108 struct fw_eq_ctrl_cmd c;
7110 memset(&c, 0, sizeof(c));
7111 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7112 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7113 FW_EQ_CTRL_CMD_PFN_V(pf) |
7114 FW_EQ_CTRL_CMD_VFN_V(vf));
7115 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7116 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7117 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7121 * t4_ofld_eq_free - free an offload egress queue
7122 * @adap: the adapter
7123 * @mbox: mailbox to use for the FW command
7124 * @pf: the PF owning the queue
7125 * @vf: the VF owning the queue
7126 * @eqid: egress queue id
7128 * Frees a control egress queue.
7130 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7131 unsigned int vf, unsigned int eqid)
7133 struct fw_eq_ofld_cmd c;
7135 memset(&c, 0, sizeof(c));
7136 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7137 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7138 FW_EQ_OFLD_CMD_PFN_V(pf) |
7139 FW_EQ_OFLD_CMD_VFN_V(vf));
7140 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7141 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7142 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7146 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7147 * @adap: the adapter
7148 * @link_down_rc: Link Down Reason Code
7150 * Returns a string representation of the Link Down Reason Code.
7152 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7154 static const char * const reason[] = {
7157 "Auto-negotiation Failure",
7159 "Insufficient Airflow",
7160 "Unable To Determine Reason",
7161 "No RX Signal Detected",
7165 if (link_down_rc >= ARRAY_SIZE(reason))
7166 return "Bad Reason Code";
7168 return reason[link_down_rc];
7172 * t4_handle_get_port_info - process a FW reply message
7173 * @pi: the port info
7174 * @rpl: start of the FW message
7176 * Processes a GET_PORT_INFO FW reply message.
7178 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7180 const struct fw_port_cmd *p = (const void *)rpl;
7181 struct adapter *adap = pi->adapter;
7183 /* link/module state change message */
7184 int speed = 0, fc = 0;
7185 struct link_config *lc;
7186 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7187 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7188 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7190 if (stat & FW_PORT_CMD_RXPAUSE_F)
7192 if (stat & FW_PORT_CMD_TXPAUSE_F)
7194 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7196 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7198 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7200 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7202 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7204 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7209 if (mod != pi->mod_type) {
7211 t4_os_portmod_changed(adap, pi->port_id);
7213 if (link_ok != lc->link_ok || speed != lc->speed ||
7214 fc != lc->fc) { /* something changed */
7215 if (!link_ok && lc->link_ok) {
7216 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7218 lc->link_down_rc = rc;
7219 dev_warn(adap->pdev_dev,
7220 "Port %d link down, reason: %s\n",
7221 pi->port_id, t4_link_down_rc_str(rc));
7223 lc->link_ok = link_ok;
7226 lc->supported = be16_to_cpu(p->u.info.pcap);
7227 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7228 t4_os_link_changed(adap, pi->port_id, link_ok);
7233 * t4_handle_fw_rpl - process a FW reply message
7234 * @adap: the adapter
7235 * @rpl: start of the FW message
7237 * Processes a FW message, such as link state change messages.
7239 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7241 u8 opcode = *(const u8 *)rpl;
7243 /* This might be a port command ... this simplifies the following
7244 * conditionals ... We can get away with pre-dereferencing
7245 * action_to_len16 because it's in the first 16 bytes and all messages
7246 * will be at least that long.
7248 const struct fw_port_cmd *p = (const void *)rpl;
7249 unsigned int action =
7250 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7252 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7254 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7255 struct port_info *pi = NULL;
7257 for_each_port(adap, i) {
7258 pi = adap2pinfo(adap, i);
7259 if (pi->tx_chan == chan)
7263 t4_handle_get_port_info(pi, rpl);
7265 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7271 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7275 if (pci_is_pcie(adapter->pdev)) {
7276 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7277 p->speed = val & PCI_EXP_LNKSTA_CLS;
7278 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7283 * init_link_config - initialize a link's SW state
7284 * @lc: structure holding the link state
7285 * @caps: link capabilities
7287 * Initializes the SW state maintained for each link, including the link's
7288 * capabilities and default speed/flow-control/autonegotiation settings.
7290 static void init_link_config(struct link_config *lc, unsigned int caps)
7292 lc->supported = caps;
7293 lc->lp_advertising = 0;
7294 lc->requested_speed = 0;
7296 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7297 if (lc->supported & FW_PORT_CAP_ANEG) {
7298 lc->advertising = lc->supported & ADVERT_MASK;
7299 lc->autoneg = AUTONEG_ENABLE;
7300 lc->requested_fc |= PAUSE_AUTONEG;
7302 lc->advertising = 0;
7303 lc->autoneg = AUTONEG_DISABLE;
7307 #define CIM_PF_NOACCESS 0xeeeeeeee
7309 int t4_wait_dev_ready(void __iomem *regs)
7313 whoami = readl(regs + PL_WHOAMI_A);
7314 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7318 whoami = readl(regs + PL_WHOAMI_A);
7319 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7323 u32 vendor_and_model_id;
7327 static int get_flash_params(struct adapter *adap)
7329 /* Table for non-Numonix supported flash parts. Numonix parts are left
7330 * to the preexisting code. All flash parts have 64KB sectors.
7332 static struct flash_desc supported_flash[] = {
7333 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7339 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7341 ret = sf1_read(adap, 3, 0, 1, &info);
7342 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7346 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7347 if (supported_flash[ret].vendor_and_model_id == info) {
7348 adap->params.sf_size = supported_flash[ret].size_mb;
7349 adap->params.sf_nsec =
7350 adap->params.sf_size / SF_SEC_SIZE;
7354 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7356 info >>= 16; /* log2 of size */
7357 if (info >= 0x14 && info < 0x18)
7358 adap->params.sf_nsec = 1 << (info - 16);
7359 else if (info == 0x18)
7360 adap->params.sf_nsec = 64;
7363 adap->params.sf_size = 1 << info;
7364 adap->params.sf_fw_start =
7365 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7367 if (adap->params.sf_size < FLASH_MIN_SIZE)
7368 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7369 adap->params.sf_size, FLASH_MIN_SIZE);
7373 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7378 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7380 pci_read_config_word(adapter->pdev,
7381 pcie_cap + PCI_EXP_DEVCTL2, &val);
7382 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7384 pci_write_config_word(adapter->pdev,
7385 pcie_cap + PCI_EXP_DEVCTL2, val);
7390 * t4_prep_adapter - prepare SW and HW for operation
7391 * @adapter: the adapter
7392 * @reset: if true perform a HW reset
7394 * Initialize adapter SW state for the various HW modules, set initial
7395 * values for some adapter tunables, take PHYs out of reset, and
7396 * initialize the MDIO interface.
7398 int t4_prep_adapter(struct adapter *adapter)
7404 get_pci_mode(adapter, &adapter->params.pci);
7405 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7407 ret = get_flash_params(adapter);
7409 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7413 /* Retrieve adapter's device ID
7415 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7416 ver = device_id >> 12;
7417 adapter->params.chip = 0;
7420 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7421 adapter->params.arch.sge_fl_db = DBPRIO_F;
7422 adapter->params.arch.mps_tcam_size =
7423 NUM_MPS_CLS_SRAM_L_INSTANCES;
7424 adapter->params.arch.mps_rplc_size = 128;
7425 adapter->params.arch.nchan = NCHAN;
7426 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7427 adapter->params.arch.vfcount = 128;
7428 /* Congestion map is for 4 channels so that
7429 * MPS can have 4 priority per port.
7431 adapter->params.arch.cng_ch_bits_log = 2;
7434 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7435 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7436 adapter->params.arch.mps_tcam_size =
7437 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7438 adapter->params.arch.mps_rplc_size = 128;
7439 adapter->params.arch.nchan = NCHAN;
7440 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7441 adapter->params.arch.vfcount = 128;
7442 adapter->params.arch.cng_ch_bits_log = 2;
7445 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7446 adapter->params.arch.sge_fl_db = 0;
7447 adapter->params.arch.mps_tcam_size =
7448 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7449 adapter->params.arch.mps_rplc_size = 256;
7450 adapter->params.arch.nchan = 2;
7451 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7452 adapter->params.arch.vfcount = 256;
7453 /* Congestion map will be for 2 channels so that
7454 * MPS can have 8 priority per port.
7456 adapter->params.arch.cng_ch_bits_log = 3;
7459 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7464 adapter->params.cim_la_size = CIMLA_SIZE;
7465 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7468 * Default port for debugging in case we can't reach FW.
7470 adapter->params.nports = 1;
7471 adapter->params.portvec = 1;
7472 adapter->params.vpd.cclk = 50000;
7474 /* Set pci completion timeout value to 4 seconds. */
7475 set_pcie_completion_timeout(adapter, 0xd);
7480 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7481 * @adapter: the adapter
7482 * @qid: the Queue ID
7483 * @qtype: the Ingress or Egress type for @qid
7484 * @user: true if this request is for a user mode queue
7485 * @pbar2_qoffset: BAR2 Queue Offset
7486 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7488 * Returns the BAR2 SGE Queue Registers information associated with the
7489 * indicated Absolute Queue ID. These are passed back in return value
7490 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7491 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7493 * This may return an error which indicates that BAR2 SGE Queue
7494 * registers aren't available. If an error is not returned, then the
7495 * following values are returned:
7497 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7498 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7500 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7501 * require the "Inferred Queue ID" ability may be used. E.g. the
7502 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7503 * then these "Inferred Queue ID" register may not be used.
7505 int t4_bar2_sge_qregs(struct adapter *adapter,
7507 enum t4_bar2_qtype qtype,
7510 unsigned int *pbar2_qid)
7512 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7513 u64 bar2_page_offset, bar2_qoffset;
7514 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7516 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7517 if (!user && is_t4(adapter->params.chip))
7520 /* Get our SGE Page Size parameters.
7522 page_shift = adapter->params.sge.hps + 10;
7523 page_size = 1 << page_shift;
7525 /* Get the right Queues per Page parameters for our Queue.
7527 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7528 ? adapter->params.sge.eq_qpp
7529 : adapter->params.sge.iq_qpp);
7530 qpp_mask = (1 << qpp_shift) - 1;
7532 /* Calculate the basics of the BAR2 SGE Queue register area:
7533 * o The BAR2 page the Queue registers will be in.
7534 * o The BAR2 Queue ID.
7535 * o The BAR2 Queue ID Offset into the BAR2 page.
7537 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7538 bar2_qid = qid & qpp_mask;
7539 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7541 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7542 * hardware will infer the Absolute Queue ID simply from the writes to
7543 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7544 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7545 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7546 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7547 * from the BAR2 Page and BAR2 Queue ID.
7549 * One important censequence of this is that some BAR2 SGE registers
7550 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7551 * there. But other registers synthesize the SGE Queue ID purely
7552 * from the writes to the registers -- the Write Combined Doorbell
7553 * Buffer is a good example. These BAR2 SGE Registers are only
7554 * available for those BAR2 SGE Register areas where the SGE Absolute
7555 * Queue ID can be inferred from simple writes.
7557 bar2_qoffset = bar2_page_offset;
7558 bar2_qinferred = (bar2_qid_offset < page_size);
7559 if (bar2_qinferred) {
7560 bar2_qoffset += bar2_qid_offset;
7564 *pbar2_qoffset = bar2_qoffset;
7565 *pbar2_qid = bar2_qid;
7570 * t4_init_devlog_params - initialize adapter->params.devlog
7571 * @adap: the adapter
7573 * Initialize various fields of the adapter's Firmware Device Log
7574 * Parameters structure.
7576 int t4_init_devlog_params(struct adapter *adap)
7578 struct devlog_params *dparams = &adap->params.devlog;
7580 unsigned int devlog_meminfo;
7581 struct fw_devlog_cmd devlog_cmd;
7584 /* If we're dealing with newer firmware, the Device Log Paramerters
7585 * are stored in a designated register which allows us to access the
7586 * Device Log even if we can't talk to the firmware.
7589 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7591 unsigned int nentries, nentries128;
7593 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7594 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7596 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7597 nentries = (nentries128 + 1) * 128;
7598 dparams->size = nentries * sizeof(struct fw_devlog_e);
7603 /* Otherwise, ask the firmware for it's Device Log Parameters.
7605 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7606 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7607 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7608 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7609 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7615 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7616 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7617 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7618 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7624 * t4_init_sge_params - initialize adap->params.sge
7625 * @adapter: the adapter
7627 * Initialize various fields of the adapter's SGE Parameters structure.
7629 int t4_init_sge_params(struct adapter *adapter)
7631 struct sge_params *sge_params = &adapter->params.sge;
7633 unsigned int s_hps, s_qpp;
7635 /* Extract the SGE Page Size for our PF.
7637 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7638 s_hps = (HOSTPAGESIZEPF0_S +
7639 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7640 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7642 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7644 s_qpp = (QUEUESPERPAGEPF0_S +
7645 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7646 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7647 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7648 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7649 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7655 * t4_init_tp_params - initialize adap->params.tp
7656 * @adap: the adapter
7658 * Initialize various fields of the adapter's TP Parameters structure.
7660 int t4_init_tp_params(struct adapter *adap)
7665 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7666 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7667 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7669 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7670 for (chan = 0; chan < NCHAN; chan++)
7671 adap->params.tp.tx_modq[chan] = chan;
7673 /* Cache the adapter's Compressed Filter Mode and global Incress
7676 if (t4_use_ldst(adap)) {
7677 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7678 TP_VLAN_PRI_MAP_A, 1);
7679 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7680 TP_INGRESS_CONFIG_A, 1);
7682 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7683 &adap->params.tp.vlan_pri_map, 1,
7685 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7686 &adap->params.tp.ingress_config, 1,
7687 TP_INGRESS_CONFIG_A);
7690 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7691 * shift positions of several elements of the Compressed Filter Tuple
7692 * for this adapter which we need frequently ...
7694 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7695 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7696 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7697 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7700 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7701 * represents the presence of an Outer VLAN instead of a VNIC ID.
7703 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7704 adap->params.tp.vnic_shift = -1;
7710 * t4_filter_field_shift - calculate filter field shift
7711 * @adap: the adapter
7712 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7714 * Return the shift position of a filter field within the Compressed
7715 * Filter Tuple. The filter field is specified via its selection bit
7716 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7718 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7720 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7724 if ((filter_mode & filter_sel) == 0)
7727 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7728 switch (filter_mode & sel) {
7730 field_shift += FT_FCOE_W;
7733 field_shift += FT_PORT_W;
7736 field_shift += FT_VNIC_ID_W;
7739 field_shift += FT_VLAN_W;
7742 field_shift += FT_TOS_W;
7745 field_shift += FT_PROTOCOL_W;
7748 field_shift += FT_ETHERTYPE_W;
7751 field_shift += FT_MACMATCH_W;
7754 field_shift += FT_MPSHITTYPE_W;
7756 case FRAGMENTATION_F:
7757 field_shift += FT_FRAGMENTATION_W;
7764 int t4_init_rss_mode(struct adapter *adap, int mbox)
7767 struct fw_rss_vi_config_cmd rvc;
7769 memset(&rvc, 0, sizeof(rvc));
7771 for_each_port(adap, i) {
7772 struct port_info *p = adap2pinfo(adap, i);
7775 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7776 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7777 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7778 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7779 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7782 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7788 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7789 * @pi: the port_info
7790 * @mbox: mailbox to use for the FW command
7791 * @port: physical port associated with the VI
7792 * @pf: the PF owning the VI
7793 * @vf: the VF owning the VI
7794 * @mac: the MAC address of the VI
7796 * Allocates a virtual interface for the given physical port. If @mac is
7797 * not %NULL it contains the MAC address of the VI as assigned by FW.
7798 * @mac should be large enough to hold an Ethernet address.
7799 * Returns < 0 on error.
7801 int t4_init_portinfo(struct port_info *pi, int mbox,
7802 int port, int pf, int vf, u8 mac[])
7805 struct fw_port_cmd c;
7806 unsigned int rss_size;
7808 memset(&c, 0, sizeof(c));
7809 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7810 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7811 FW_PORT_CMD_PORTID_V(port));
7812 c.action_to_len16 = cpu_to_be32(
7813 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7815 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7819 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7826 pi->rss_size = rss_size;
7828 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7829 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7830 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7831 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7832 pi->mod_type = FW_PORT_MOD_TYPE_NA;
7834 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7838 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7843 for_each_port(adap, i) {
7844 struct port_info *pi = adap2pinfo(adap, i);
7846 while ((adap->params.portvec & (1 << j)) == 0)
7849 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7853 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7860 * t4_read_cimq_cfg - read CIM queue configuration
7861 * @adap: the adapter
7862 * @base: holds the queue base addresses in bytes
7863 * @size: holds the queue sizes in bytes
7864 * @thres: holds the queue full thresholds in bytes
7866 * Returns the current configuration of the CIM queues, starting with
7867 * the IBQs, then the OBQs.
7869 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7872 int cim_num_obq = is_t4(adap->params.chip) ?
7873 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7875 for (i = 0; i < CIM_NUM_IBQ; i++) {
7876 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7878 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7879 /* value is in 256-byte units */
7880 *base++ = CIMQBASE_G(v) * 256;
7881 *size++ = CIMQSIZE_G(v) * 256;
7882 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7884 for (i = 0; i < cim_num_obq; i++) {
7885 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7887 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7888 /* value is in 256-byte units */
7889 *base++ = CIMQBASE_G(v) * 256;
7890 *size++ = CIMQSIZE_G(v) * 256;
7895 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7896 * @adap: the adapter
7897 * @qid: the queue index
7898 * @data: where to store the queue contents
7899 * @n: capacity of @data in 32-bit words
7901 * Reads the contents of the selected CIM queue starting at address 0 up
7902 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7903 * error and the number of 32-bit words actually read on success.
7905 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7907 int i, err, attempts;
7909 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7911 if (qid > 5 || (n & 3))
7914 addr = qid * nwords;
7918 /* It might take 3-10ms before the IBQ debug read access is allowed.
7919 * Wait for 1 Sec with a delay of 1 usec.
7923 for (i = 0; i < n; i++, addr++) {
7924 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7926 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7930 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7932 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7937 * t4_read_cim_obq - read the contents of a CIM outbound queue
7938 * @adap: the adapter
7939 * @qid: the queue index
7940 * @data: where to store the queue contents
7941 * @n: capacity of @data in 32-bit words
7943 * Reads the contents of the selected CIM queue starting at address 0 up
7944 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7945 * error and the number of 32-bit words actually read on success.
7947 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7950 unsigned int addr, v, nwords;
7951 int cim_num_obq = is_t4(adap->params.chip) ?
7952 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7954 if ((qid > (cim_num_obq - 1)) || (n & 3))
7957 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7958 QUENUMSELECT_V(qid));
7959 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7961 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7962 nwords = CIMQSIZE_G(v) * 64; /* same */
7966 for (i = 0; i < n; i++, addr++) {
7967 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7969 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7973 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7975 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7980 * t4_cim_read - read a block from CIM internal address space
7981 * @adap: the adapter
7982 * @addr: the start address within the CIM address space
7983 * @n: number of words to read
7984 * @valp: where to store the result
7986 * Reads a block of 4-byte words from the CIM intenal address space.
7988 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7993 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7996 for ( ; !ret && n--; addr += 4) {
7997 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7998 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8001 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8007 * t4_cim_write - write a block into CIM internal address space
8008 * @adap: the adapter
8009 * @addr: the start address within the CIM address space
8010 * @n: number of words to write
8011 * @valp: set of values to write
8013 * Writes a block of 4-byte words into the CIM intenal address space.
8015 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8016 const unsigned int *valp)
8020 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8023 for ( ; !ret && n--; addr += 4) {
8024 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8025 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8026 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8032 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8035 return t4_cim_write(adap, addr, 1, &val);
8039 * t4_cim_read_la - read CIM LA capture buffer
8040 * @adap: the adapter
8041 * @la_buf: where to store the LA data
8042 * @wrptr: the HW write pointer within the capture buffer
8044 * Reads the contents of the CIM LA buffer with the most recent entry at
8045 * the end of the returned data and with the entry at @wrptr first.
8046 * We try to leave the LA in the running state we find it in.
8048 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8051 unsigned int cfg, val, idx;
8053 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8057 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8058 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8063 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8067 idx = UPDBGLAWRPTR_G(val);
8071 for (i = 0; i < adap->params.cim_la_size; i++) {
8072 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8073 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8076 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8079 if (val & UPDBGLARDEN_F) {
8083 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8086 idx = (idx + 1) & UPDBGLARDPTR_M;
8089 if (cfg & UPDBGLAEN_F) {
8090 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8091 cfg & ~UPDBGLARDEN_F);
8099 * t4_tp_read_la - read TP LA capture buffer
8100 * @adap: the adapter
8101 * @la_buf: where to store the LA data
8102 * @wrptr: the HW write pointer within the capture buffer
8104 * Reads the contents of the TP LA buffer with the most recent entry at
8105 * the end of the returned data and with the entry at @wrptr first.
8106 * We leave the LA in the running state we find it in.
8108 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8110 bool last_incomplete;
8111 unsigned int i, cfg, val, idx;
8113 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8114 if (cfg & DBGLAENABLE_F) /* freeze LA */
8115 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8116 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8118 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8119 idx = DBGLAWPTR_G(val);
8120 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8121 if (last_incomplete)
8122 idx = (idx + 1) & DBGLARPTR_M;
8127 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8128 val |= adap->params.tp.la_mask;
8130 for (i = 0; i < TPLA_SIZE; i++) {
8131 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8132 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8133 idx = (idx + 1) & DBGLARPTR_M;
8136 /* Wipe out last entry if it isn't valid */
8137 if (last_incomplete)
8138 la_buf[TPLA_SIZE - 1] = ~0ULL;
8140 if (cfg & DBGLAENABLE_F) /* restore running state */
8141 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8142 cfg | adap->params.tp.la_mask);
8145 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8146 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8147 * state for more than the Warning Threshold then we'll issue a warning about
8148 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8149 * appears to be hung every Warning Repeat second till the situation clears.
8150 * If the situation clears, we'll note that as well.
8152 #define SGE_IDMA_WARN_THRESH 1
8153 #define SGE_IDMA_WARN_REPEAT 300
8156 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8157 * @adapter: the adapter
8158 * @idma: the adapter IDMA Monitor state
8160 * Initialize the state of an SGE Ingress DMA Monitor.
8162 void t4_idma_monitor_init(struct adapter *adapter,
8163 struct sge_idma_monitor_state *idma)
8165 /* Initialize the state variables for detecting an SGE Ingress DMA
8166 * hang. The SGE has internal counters which count up on each clock
8167 * tick whenever the SGE finds its Ingress DMA State Engines in the
8168 * same state they were on the previous clock tick. The clock used is
8169 * the Core Clock so we have a limit on the maximum "time" they can
8170 * record; typically a very small number of seconds. For instance,
8171 * with a 600MHz Core Clock, we can only count up to a bit more than
8172 * 7s. So we'll synthesize a larger counter in order to not run the
8173 * risk of having the "timers" overflow and give us the flexibility to
8174 * maintain a Hung SGE State Machine of our own which operates across
8175 * a longer time frame.
8177 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8178 idma->idma_stalled[0] = 0;
8179 idma->idma_stalled[1] = 0;
8183 * t4_idma_monitor - monitor SGE Ingress DMA state
8184 * @adapter: the adapter
8185 * @idma: the adapter IDMA Monitor state
8186 * @hz: number of ticks/second
8187 * @ticks: number of ticks since the last IDMA Monitor call
8189 void t4_idma_monitor(struct adapter *adapter,
8190 struct sge_idma_monitor_state *idma,
8193 int i, idma_same_state_cnt[2];
8195 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8196 * are counters inside the SGE which count up on each clock when the
8197 * SGE finds its Ingress DMA State Engines in the same states they
8198 * were in the previous clock. The counters will peg out at
8199 * 0xffffffff without wrapping around so once they pass the 1s
8200 * threshold they'll stay above that till the IDMA state changes.
8202 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8203 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8204 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8206 for (i = 0; i < 2; i++) {
8207 u32 debug0, debug11;
8209 /* If the Ingress DMA Same State Counter ("timer") is less
8210 * than 1s, then we can reset our synthesized Stall Timer and
8211 * continue. If we have previously emitted warnings about a
8212 * potential stalled Ingress Queue, issue a note indicating
8213 * that the Ingress Queue has resumed forward progress.
8215 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8216 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8217 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8218 "resumed after %d seconds\n",
8219 i, idma->idma_qid[i],
8220 idma->idma_stalled[i] / hz);
8221 idma->idma_stalled[i] = 0;
8225 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8226 * domain. The first time we get here it'll be because we
8227 * passed the 1s Threshold; each additional time it'll be
8228 * because the RX Timer Callback is being fired on its regular
8231 * If the stall is below our Potential Hung Ingress Queue
8232 * Warning Threshold, continue.
8234 if (idma->idma_stalled[i] == 0) {
8235 idma->idma_stalled[i] = hz;
8236 idma->idma_warn[i] = 0;
8238 idma->idma_stalled[i] += ticks;
8239 idma->idma_warn[i] -= ticks;
8242 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8245 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8247 if (idma->idma_warn[i] > 0)
8249 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8251 /* Read and save the SGE IDMA State and Queue ID information.
8252 * We do this every time in case it changes across time ...
8253 * can't be too careful ...
8255 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8256 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8257 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8259 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8260 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8261 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8263 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8264 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8265 i, idma->idma_qid[i], idma->idma_state[i],
8266 idma->idma_stalled[i] / hz,
8268 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8273 * t4_set_vf_mac - Set MAC address for the specified VF
8274 * @adapter: The adapter
8275 * @vf: one of the VFs instantiated by the specified PF
8276 * @naddr: the number of MAC addresses
8277 * @addr: the MAC address(es) to be set to the specified VF
8279 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8280 unsigned int naddr, u8 *addr)
8282 struct fw_acl_mac_cmd cmd;
8284 memset(&cmd, 0, sizeof(cmd));
8285 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8288 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8289 FW_ACL_MAC_CMD_VFN_V(vf));
8291 /* Note: Do not enable the ACL */
8292 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8295 switch (adapter->pf) {
8297 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8300 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8303 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8306 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8310 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8313 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8314 int rateunit, int ratemode, int channel, int class,
8315 int minrate, int maxrate, int weight, int pktsize)
8317 struct fw_sched_cmd cmd;
8319 memset(&cmd, 0, sizeof(cmd));
8320 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8323 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8325 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8326 cmd.u.params.type = type;
8327 cmd.u.params.level = level;
8328 cmd.u.params.mode = mode;
8329 cmd.u.params.ch = channel;
8330 cmd.u.params.cl = class;
8331 cmd.u.params.unit = rateunit;
8332 cmd.u.params.rate = ratemode;
8333 cmd.u.params.min = cpu_to_be32(minrate);
8334 cmd.u.params.max = cpu_to_be32(maxrate);
8335 cmd.u.params.weight = cpu_to_be16(weight);
8336 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8338 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),