2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
287 struct mbox_list entry;
292 int i, ms, delay_idx, ret;
293 const __be64 *p = cmd;
294 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
295 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
296 __be64 cmd_rpl[MBOX_LEN / 8];
299 if ((size & 15) || size > MBOX_LEN)
303 * If the device is off-line, as in EEH, commands will time out.
304 * Fail them early so we don't waste time waiting.
306 if (adap->pdev->error_state != pci_channel_io_normal)
309 /* If we have a negative timeout, that implies that we can't sleep. */
315 /* Queue ourselves onto the mailbox access list. When our entry is at
316 * the front of the list, we have rights to access the mailbox. So we
317 * wait [for a while] till we're at the front [or bail out with an
320 spin_lock(&adap->mbox_lock);
321 list_add_tail(&entry.list, &adap->mlist.list);
322 spin_unlock(&adap->mbox_lock);
327 for (i = 0; ; i += ms) {
328 /* If we've waited too long, return a busy indication. This
329 * really ought to be based on our initial position in the
330 * mailbox access list but this is a start. We very rearely
331 * contend on access to the mailbox ...
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
334 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
335 spin_lock(&adap->mbox_lock);
336 list_del(&entry.list);
337 spin_unlock(&adap->mbox_lock);
338 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
339 t4_record_mbox(adap, cmd, size, access, ret);
343 /* If we're at the head, break out and start the mailbox
346 if (list_first_entry(&adap->mlist.list, struct mbox_list,
350 /* Delay for a bit before checking again ... */
352 ms = delay[delay_idx]; /* last element may repeat */
353 if (delay_idx < ARRAY_SIZE(delay) - 1)
361 /* Loop trying to get ownership of the mailbox. Return an error
362 * if we can't gain ownership.
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
365 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 if (v != MBOX_OWNER_DRV) {
368 spin_lock(&adap->mbox_lock);
369 list_del(&entry.list);
370 spin_unlock(&adap->mbox_lock);
371 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
372 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
376 /* Copy in the new mailbox command and send it on its way ... */
377 t4_record_mbox(adap, cmd, MBOX_LEN, access, 0);
378 for (i = 0; i < size; i += 8)
379 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
381 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
382 t4_read_reg(adap, ctl_reg); /* flush write */
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
392 ms = delay[delay_idx]; /* last element may repeat */
393 if (delay_idx < ARRAY_SIZE(delay) - 1)
399 v = t4_read_reg(adap, ctl_reg);
400 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
401 if (!(v & MBMSGVALID_F)) {
402 t4_write_reg(adap, ctl_reg, 0);
406 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
407 res = be64_to_cpu(cmd_rpl[0]);
409 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
410 fw_asrt(adap, data_reg);
411 res = FW_CMD_RETVAL_V(EIO);
413 memcpy(rpl, cmd_rpl, size);
416 t4_write_reg(adap, ctl_reg, 0);
419 t4_record_mbox(adap, cmd_rpl,
420 MBOX_LEN, access, execute);
421 spin_lock(&adap->mbox_lock);
422 list_del(&entry.list);
423 spin_unlock(&adap->mbox_lock);
424 return -FW_CMD_RETVAL_G((int)res);
428 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
429 t4_record_mbox(adap, cmd, MBOX_LEN, access, ret);
430 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
431 *(const u8 *)cmd, mbox);
432 t4_report_fw_error(adap);
433 spin_lock(&adap->mbox_lock);
434 list_del(&entry.list);
435 spin_unlock(&adap->mbox_lock);
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441 void *rpl, bool sleep_ok)
443 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
447 static int t4_edc_err_read(struct adapter *adap, int idx)
449 u32 edc_ecc_err_addr_reg;
452 if (is_t4(adap->params.chip)) {
453 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
456 if (idx != 0 && idx != 1) {
457 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
461 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
462 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
465 "edc%d err addr 0x%x: 0x%x.\n",
466 idx, edc_ecc_err_addr_reg,
467 t4_read_reg(adap, edc_ecc_err_addr_reg));
469 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
471 (unsigned long long)t4_read_reg64(adap, rdata_reg),
472 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
473 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
485 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
487 * @win: PCI-E Memory Window to use
488 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
489 * @addr: address within indicated memory type
490 * @len: amount of memory to transfer
491 * @hbuf: host memory buffer
492 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
494 * Reads/writes an [almost] arbitrary memory region in the firmware: the
495 * firmware memory address and host buffer must be aligned on 32-bit
496 * boudaries; the length may be arbitrary. The memory is transferred as
497 * a raw byte sequence from/to the firmware's memory. If this memory
498 * contains data structures which contain multi-byte integers, it's the
499 * caller's responsibility to perform appropriate byte order conversions.
501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
502 u32 len, void *hbuf, int dir)
504 u32 pos, offset, resid, memoffset;
505 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
508 /* Argument sanity checks ...
510 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
514 /* It's convenient to be able to handle lengths which aren't a
515 * multiple of 32-bits because we often end up transferring files to
516 * the firmware. So we'll handle that by normalizing the length here
517 * and then handling any residual transfer at the end.
522 /* Offset into the region of memory which is being accessed
525 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
526 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
529 if (mtype != MEM_MC1)
530 memoffset = (mtype * (edc_size * 1024 * 1024));
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
533 MA_EXT_MEMORY0_BAR_A));
534 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
537 /* Determine the PCIE_MEM_ACCESS_OFFSET */
538 addr = addr + memoffset;
540 /* Each PCI-E Memory Window is programmed with a window size -- or
541 * "aperture" -- which controls the granularity of its mapping onto
542 * adapter memory. We need to grab that aperture in order to know
543 * how to use the specified window. The window is also programmed
544 * with the base address of the Memory Window in BAR0's address
545 * space. For T4 this is an absolute PCI-E Bus Address. For T5
546 * the address is relative to BAR0.
548 mem_reg = t4_read_reg(adap,
549 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
551 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
552 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
553 if (is_t4(adap->params.chip))
554 mem_base -= adap->t4_bar0;
555 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
557 /* Calculate our initial PCI-E Memory Window Position and Offset into
560 pos = addr & ~(mem_aperture-1);
563 /* Set up initial PCI-E Memory Window to cover the start of our
564 * transfer. (Read it back to ensure that changes propagate before we
565 * attempt to use the new value.)
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
573 /* Transfer data to/from the adapter as long as there's an integral
574 * number of 32-bit transfers to complete.
576 * A note on Endianness issues:
578 * The "register" reads and writes below from/to the PCI-E Memory
579 * Window invoke the standard adapter Big-Endian to PCI-E Link
580 * Little-Endian "swizzel." As a result, if we have the following
581 * data in adapter memory:
583 * Memory: ... | b0 | b1 | b2 | b3 | ...
584 * Address: i+0 i+1 i+2 i+3
586 * Then a read of the adapter memory via the PCI-E Memory Window
591 * [ b3 | b2 | b1 | b0 ]
593 * If this value is stored into local memory on a Little-Endian system
594 * it will show up correctly in local memory as:
596 * ( ..., b0, b1, b2, b3, ... )
598 * But on a Big-Endian system, the store will show up in memory
599 * incorrectly swizzled as:
601 * ( ..., b3, b2, b1, b0, ... )
603 * So we need to account for this in the reads and writes to the
604 * PCI-E Memory Window below by undoing the register read/write
608 if (dir == T4_MEMORY_READ)
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
612 t4_write_reg(adap, mem_base + offset,
613 (__force u32)cpu_to_le32(*buf++));
614 offset += sizeof(__be32);
615 len -= sizeof(__be32);
617 /* If we've reached the end of our current window aperture,
618 * move the PCI-E Memory Window on to the next. Note that
619 * doing this here after "len" may be 0 allows us to set up
620 * the PCI-E Memory Window for a possible final residual
623 if (offset == mem_aperture) {
627 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
630 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
635 /* If the original transfer had a length which wasn't a multiple of
636 * 32-bits, now's where we need to finish off the transfer of the
637 * residual amount. The PCI-E Memory Window has already been moved
638 * above (if necessary) to cover this final transfer.
648 if (dir == T4_MEMORY_READ) {
649 last.word = le32_to_cpu(
650 (__force __le32)t4_read_reg(adap,
652 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
653 bp[i] = last.byte[i];
656 for (i = resid; i < 4; i++)
658 t4_write_reg(adap, mem_base + offset,
659 (__force u32)cpu_to_le32(last.word));
666 /* Return the specified PCI-E Configuration Space register from our Physical
667 * Function. We try first via a Firmware LDST Command since we prefer to let
668 * the firmware own all of these registers, but if that fails we go for it
669 * directly ourselves.
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
673 u32 val, ldst_addrspace;
675 /* If fw_attach != 0, construct and send the Firmware LDST Command to
676 * retrieve the specified PCI-E Configuration Space register.
678 struct fw_ldst_cmd ldst_cmd;
681 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
682 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
683 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
687 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
688 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
689 ldst_cmd.u.pcie.ctrl_to_fn =
690 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
691 ldst_cmd.u.pcie.r = reg;
693 /* If the LDST Command succeeds, return the result, otherwise
694 * fall through to reading it directly ourselves ...
696 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
699 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
701 /* Read the desired Configuration Space register via the PCI-E
702 * Backdoor mechanism.
704 t4_hw_pci_read_cfg4(adap, reg, &val);
708 /* Get the window based on base passed to it.
709 * Window aperture is currently unhandled, but there is no use case for it
712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
717 if (is_t4(adap->params.chip)) {
720 /* Truncation intentional: we only read the bottom 32-bits of
721 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
722 * mechanism to read BAR0 instead of using
723 * pci_resource_start() because we could be operating from
724 * within a Virtual Machine which is trapping our accesses to
725 * our Configuration Space and we need to set up the PCI-E
726 * Memory Window decoders with the actual addresses which will
727 * be coming across the PCI-E link.
729 bar0 = t4_read_pcie_cfg4(adap, pci_base);
731 adap->t4_bar0 = bar0;
733 ret = bar0 + memwin_base;
735 /* For T5, only relative offset inside the PCIe BAR is passed */
741 /* Get the default utility window (win0) used by everyone */
742 u32 t4_get_util_window(struct adapter *adap)
744 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
745 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
748 /* Set up memory window for accessing adapter memory ranges. (Read
749 * back MA register to ensure that changes propagate before we attempt
750 * to use the new values.)
752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
755 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
756 memwin_base | BIR_V(0) |
757 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
759 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
763 * t4_get_regs_len - return the size of the chips register set
764 * @adapter: the adapter
766 * Returns the size of the chip's BAR0 register space.
768 unsigned int t4_get_regs_len(struct adapter *adapter)
770 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
772 switch (chip_version) {
774 return T4_REGMAP_SIZE;
778 return T5_REGMAP_SIZE;
781 dev_err(adapter->pdev_dev,
782 "Unsupported chip version %d\n", chip_version);
787 * t4_get_regs - read chip registers into provided buffer
789 * @buf: register buffer
790 * @buf_size: size (in bytes) of register buffer
792 * If the provided register buffer isn't large enough for the chip's
793 * full register range, the register dump will be truncated to the
794 * register buffer's size.
796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
798 static const unsigned int t4_reg_ranges[] = {
1256 static const unsigned int t5_reg_ranges[] = {
2031 static const unsigned int t6_reg_ranges[] = {
2608 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2609 const unsigned int *reg_ranges;
2610 int reg_ranges_size, range;
2611 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2613 /* Select the right set of register ranges to dump depending on the
2614 * adapter chip type.
2616 switch (chip_version) {
2618 reg_ranges = t4_reg_ranges;
2619 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2623 reg_ranges = t5_reg_ranges;
2624 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2628 reg_ranges = t6_reg_ranges;
2629 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2633 dev_err(adap->pdev_dev,
2634 "Unsupported chip version %d\n", chip_version);
2638 /* Clear the register buffer and insert the appropriate register
2639 * values selected by the above register ranges.
2641 memset(buf, 0, buf_size);
2642 for (range = 0; range < reg_ranges_size; range += 2) {
2643 unsigned int reg = reg_ranges[range];
2644 unsigned int last_reg = reg_ranges[range + 1];
2645 u32 *bufp = (u32 *)((char *)buf + reg);
2647 /* Iterate across the register range filling in the register
2648 * buffer but don't write past the end of the register buffer.
2650 while (reg <= last_reg && bufp < buf_end) {
2651 *bufp++ = t4_read_reg(adap, reg);
2657 #define EEPROM_STAT_ADDR 0x7bfc
2658 #define VPD_SIZE 0x800
2659 #define VPD_BASE 0x400
2660 #define VPD_BASE_OLD 0
2661 #define VPD_LEN 1024
2662 #define CHELSIO_VPD_UNIQUE_ID 0x82
2665 * t4_seeprom_wp - enable/disable EEPROM write protection
2666 * @adapter: the adapter
2667 * @enable: whether to enable or disable write protection
2669 * Enables or disables write protection on the serial EEPROM.
2671 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2673 unsigned int v = enable ? 0xc : 0;
2674 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2675 return ret < 0 ? ret : 0;
2679 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2680 * @adapter: adapter to read
2681 * @p: where to store the parameters
2683 * Reads card parameters stored in VPD EEPROM.
2685 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2687 int i, ret = 0, addr;
2690 unsigned int vpdr_len, kw_offset, id_len;
2692 vpd = vmalloc(VPD_LEN);
2696 /* We have two VPD data structures stored in the adapter VPD area.
2697 * By default, Linux calculates the size of the VPD area by traversing
2698 * the first VPD area at offset 0x0, so we need to tell the OS what
2699 * our real VPD size is.
2701 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2705 /* Card information normally starts at VPD_BASE but early cards had
2708 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2712 /* The VPD shall have a unique identifier specified by the PCI SIG.
2713 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2714 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2715 * is expected to automatically put this entry at the
2716 * beginning of the VPD.
2718 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2720 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2724 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2725 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2730 id_len = pci_vpd_lrdt_size(vpd);
2731 if (id_len > ID_LEN)
2734 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2736 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2741 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2742 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2743 if (vpdr_len + kw_offset > VPD_LEN) {
2744 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2749 #define FIND_VPD_KW(var, name) do { \
2750 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2752 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2756 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2759 FIND_VPD_KW(i, "RV");
2760 for (csum = 0; i >= 0; i--)
2764 dev_err(adapter->pdev_dev,
2765 "corrupted VPD EEPROM, actual csum %u\n", csum);
2770 FIND_VPD_KW(ec, "EC");
2771 FIND_VPD_KW(sn, "SN");
2772 FIND_VPD_KW(pn, "PN");
2773 FIND_VPD_KW(na, "NA");
2776 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2778 memcpy(p->ec, vpd + ec, EC_LEN);
2780 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2781 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2783 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2784 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2786 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2787 strim((char *)p->na);
2791 return ret < 0 ? ret : 0;
2795 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2796 * @adapter: adapter to read
2797 * @p: where to store the parameters
2799 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2800 * Clock. This can only be called after a connection to the firmware
2803 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2805 u32 cclk_param, cclk_val;
2808 /* Grab the raw VPD parameters.
2810 ret = t4_get_raw_vpd_params(adapter, p);
2814 /* Ask firmware for the Core Clock since it knows how to translate the
2815 * Reference Clock ('V2') VPD field into a Core Clock value ...
2817 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2818 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2819 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2820 1, &cclk_param, &cclk_val);
2829 /* serial flash and firmware constants */
2831 SF_ATTEMPTS = 10, /* max retries for SF operations */
2833 /* flash command opcodes */
2834 SF_PROG_PAGE = 2, /* program page */
2835 SF_WR_DISABLE = 4, /* disable writes */
2836 SF_RD_STATUS = 5, /* read status register */
2837 SF_WR_ENABLE = 6, /* enable writes */
2838 SF_RD_DATA_FAST = 0xb, /* read flash */
2839 SF_RD_ID = 0x9f, /* read ID */
2840 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2842 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2846 * sf1_read - read data from the serial flash
2847 * @adapter: the adapter
2848 * @byte_cnt: number of bytes to read
2849 * @cont: whether another operation will be chained
2850 * @lock: whether to lock SF for PL access only
2851 * @valp: where to store the read data
2853 * Reads up to 4 bytes of data from the serial flash. The location of
2854 * the read needs to be specified prior to calling this by issuing the
2855 * appropriate commands to the serial flash.
2857 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2858 int lock, u32 *valp)
2862 if (!byte_cnt || byte_cnt > 4)
2864 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2866 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2867 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2868 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2870 *valp = t4_read_reg(adapter, SF_DATA_A);
2875 * sf1_write - write data to the serial flash
2876 * @adapter: the adapter
2877 * @byte_cnt: number of bytes to write
2878 * @cont: whether another operation will be chained
2879 * @lock: whether to lock SF for PL access only
2880 * @val: value to write
2882 * Writes up to 4 bytes of data to the serial flash. The location of
2883 * the write needs to be specified prior to calling this by issuing the
2884 * appropriate commands to the serial flash.
2886 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2889 if (!byte_cnt || byte_cnt > 4)
2891 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2893 t4_write_reg(adapter, SF_DATA_A, val);
2894 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2895 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2896 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2900 * flash_wait_op - wait for a flash operation to complete
2901 * @adapter: the adapter
2902 * @attempts: max number of polls of the status register
2903 * @delay: delay between polls in ms
2905 * Wait for a flash operation to complete by polling the status register.
2907 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2913 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2914 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2918 if (--attempts == 0)
2926 * t4_read_flash - read words from serial flash
2927 * @adapter: the adapter
2928 * @addr: the start address for the read
2929 * @nwords: how many 32-bit words to read
2930 * @data: where to store the read data
2931 * @byte_oriented: whether to store data as bytes or as words
2933 * Read the specified number of 32-bit words from the serial flash.
2934 * If @byte_oriented is set the read data is stored as a byte array
2935 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2936 * natural endianness.
2938 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2939 unsigned int nwords, u32 *data, int byte_oriented)
2943 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2946 addr = swab32(addr) | SF_RD_DATA_FAST;
2948 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2949 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2952 for ( ; nwords; nwords--, data++) {
2953 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2955 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2959 *data = (__force __u32)(cpu_to_be32(*data));
2965 * t4_write_flash - write up to a page of data to the serial flash
2966 * @adapter: the adapter
2967 * @addr: the start address to write
2968 * @n: length of data to write in bytes
2969 * @data: the data to write
2971 * Writes up to a page of data (256 bytes) to the serial flash starting
2972 * at the given address. All the data must be written to the same page.
2974 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2975 unsigned int n, const u8 *data)
2979 unsigned int i, c, left, val, offset = addr & 0xff;
2981 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2984 val = swab32(addr) | SF_PROG_PAGE;
2986 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2987 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2990 for (left = n; left; left -= c) {
2992 for (val = 0, i = 0; i < c; ++i)
2993 val = (val << 8) + *data++;
2995 ret = sf1_write(adapter, c, c != left, 1, val);
2999 ret = flash_wait_op(adapter, 8, 1);
3003 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3005 /* Read the page to verify the write succeeded */
3006 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3010 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3011 dev_err(adapter->pdev_dev,
3012 "failed to correctly write the flash page at %#x\n",
3019 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3024 * t4_get_fw_version - read the firmware version
3025 * @adapter: the adapter
3026 * @vers: where to place the version
3028 * Reads the FW version from flash.
3030 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3032 return t4_read_flash(adapter, FLASH_FW_START +
3033 offsetof(struct fw_hdr, fw_ver), 1,
3038 * t4_get_bs_version - read the firmware bootstrap version
3039 * @adapter: the adapter
3040 * @vers: where to place the version
3042 * Reads the FW Bootstrap version from flash.
3044 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3046 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3047 offsetof(struct fw_hdr, fw_ver), 1,
3052 * t4_get_tp_version - read the TP microcode version
3053 * @adapter: the adapter
3054 * @vers: where to place the version
3056 * Reads the TP microcode version from flash.
3058 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3060 return t4_read_flash(adapter, FLASH_FW_START +
3061 offsetof(struct fw_hdr, tp_microcode_ver),
3066 * t4_get_exprom_version - return the Expansion ROM version (if any)
3067 * @adapter: the adapter
3068 * @vers: where to place the version
3070 * Reads the Expansion ROM header from FLASH and returns the version
3071 * number (if present) through the @vers return value pointer. We return
3072 * this in the Firmware Version Format since it's convenient. Return
3073 * 0 on success, -ENOENT if no Expansion ROM is present.
3075 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3077 struct exprom_header {
3078 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3079 unsigned char hdr_ver[4]; /* Expansion ROM version */
3081 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3085 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3086 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3091 hdr = (struct exprom_header *)exprom_header_buf;
3092 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3095 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3096 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3097 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3098 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3103 * t4_check_fw_version - check if the FW is supported with this driver
3104 * @adap: the adapter
3106 * Checks if an adapter's FW is compatible with the driver. Returns 0
3107 * if there's exact match, a negative error if the version could not be
3108 * read or there's a major version mismatch
3110 int t4_check_fw_version(struct adapter *adap)
3112 int i, ret, major, minor, micro;
3113 int exp_major, exp_minor, exp_micro;
3114 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3116 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3117 /* Try multiple times before returning error */
3118 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3119 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3124 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3125 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3126 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3128 switch (chip_version) {
3130 exp_major = T4FW_MIN_VERSION_MAJOR;
3131 exp_minor = T4FW_MIN_VERSION_MINOR;
3132 exp_micro = T4FW_MIN_VERSION_MICRO;
3135 exp_major = T5FW_MIN_VERSION_MAJOR;
3136 exp_minor = T5FW_MIN_VERSION_MINOR;
3137 exp_micro = T5FW_MIN_VERSION_MICRO;
3140 exp_major = T6FW_MIN_VERSION_MAJOR;
3141 exp_minor = T6FW_MIN_VERSION_MINOR;
3142 exp_micro = T6FW_MIN_VERSION_MICRO;
3145 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3150 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3151 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3152 dev_err(adap->pdev_dev,
3153 "Card has firmware version %u.%u.%u, minimum "
3154 "supported firmware is %u.%u.%u.\n", major, minor,
3155 micro, exp_major, exp_minor, exp_micro);
3161 /* Is the given firmware API compatible with the one the driver was compiled
3164 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3167 /* short circuit if it's the exact same firmware version */
3168 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3171 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3172 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3173 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3180 /* The firmware in the filesystem is usable, but should it be installed?
3181 * This routine explains itself in detail if it indicates the filesystem
3182 * firmware should be installed.
3184 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3189 if (!card_fw_usable) {
3190 reason = "incompatible or unusable";
3195 reason = "older than the version supported with this driver";
3202 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3203 "installing firmware %u.%u.%u.%u on card.\n",
3204 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3205 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3206 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3207 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3212 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3213 const u8 *fw_data, unsigned int fw_size,
3214 struct fw_hdr *card_fw, enum dev_state state,
3217 int ret, card_fw_usable, fs_fw_usable;
3218 const struct fw_hdr *fs_fw;
3219 const struct fw_hdr *drv_fw;
3221 drv_fw = &fw_info->fw_hdr;
3223 /* Read the header of the firmware on the card */
3224 ret = -t4_read_flash(adap, FLASH_FW_START,
3225 sizeof(*card_fw) / sizeof(uint32_t),
3226 (uint32_t *)card_fw, 1);
3228 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3230 dev_err(adap->pdev_dev,
3231 "Unable to read card's firmware header: %d\n", ret);
3235 if (fw_data != NULL) {
3236 fs_fw = (const void *)fw_data;
3237 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3243 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3244 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3245 /* Common case: the firmware on the card is an exact match and
3246 * the filesystem one is an exact match too, or the filesystem
3247 * one is absent/incompatible.
3249 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3250 should_install_fs_fw(adap, card_fw_usable,
3251 be32_to_cpu(fs_fw->fw_ver),
3252 be32_to_cpu(card_fw->fw_ver))) {
3253 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3256 dev_err(adap->pdev_dev,
3257 "failed to install firmware: %d\n", ret);
3261 /* Installed successfully, update the cached header too. */
3264 *reset = 0; /* already reset as part of load_fw */
3267 if (!card_fw_usable) {
3270 d = be32_to_cpu(drv_fw->fw_ver);
3271 c = be32_to_cpu(card_fw->fw_ver);
3272 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3274 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3276 "driver compiled with %d.%d.%d.%d, "
3277 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3279 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3280 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3281 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3282 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3283 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3284 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3289 /* We're using whatever's on the card and it's known to be good. */
3290 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3291 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3298 * t4_flash_erase_sectors - erase a range of flash sectors
3299 * @adapter: the adapter
3300 * @start: the first sector to erase
3301 * @end: the last sector to erase
3303 * Erases the sectors in the given inclusive range.
3305 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3309 if (end >= adapter->params.sf_nsec)
3312 while (start <= end) {
3313 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3314 (ret = sf1_write(adapter, 4, 0, 1,
3315 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3316 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3317 dev_err(adapter->pdev_dev,
3318 "erase of flash sector %d failed, error %d\n",
3324 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3329 * t4_flash_cfg_addr - return the address of the flash configuration file
3330 * @adapter: the adapter
3332 * Return the address within the flash where the Firmware Configuration
3335 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3337 if (adapter->params.sf_size == 0x100000)
3338 return FLASH_FPGA_CFG_START;
3340 return FLASH_CFG_START;
3343 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3344 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3345 * and emit an error message for mismatched firmware to save our caller the
3348 static bool t4_fw_matches_chip(const struct adapter *adap,
3349 const struct fw_hdr *hdr)
3351 /* The expression below will return FALSE for any unsupported adapter
3352 * which will keep us "honest" in the future ...
3354 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3355 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3356 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3359 dev_err(adap->pdev_dev,
3360 "FW image (%d) is not suitable for this adapter (%d)\n",
3361 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3366 * t4_load_fw - download firmware
3367 * @adap: the adapter
3368 * @fw_data: the firmware image to write
3371 * Write the supplied firmware image to the card's serial flash.
3373 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3378 u8 first_page[SF_PAGE_SIZE];
3379 const __be32 *p = (const __be32 *)fw_data;
3380 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3381 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3382 unsigned int fw_img_start = adap->params.sf_fw_start;
3383 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3386 dev_err(adap->pdev_dev, "FW image has no data\n");
3390 dev_err(adap->pdev_dev,
3391 "FW image size not multiple of 512 bytes\n");
3394 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3395 dev_err(adap->pdev_dev,
3396 "FW image size differs from size in FW header\n");
3399 if (size > FW_MAX_SIZE) {
3400 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3404 if (!t4_fw_matches_chip(adap, hdr))
3407 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3408 csum += be32_to_cpu(p[i]);
3410 if (csum != 0xffffffff) {
3411 dev_err(adap->pdev_dev,
3412 "corrupted firmware image, checksum %#x\n", csum);
3416 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3417 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3422 * We write the correct version at the end so the driver can see a bad
3423 * version if the FW write fails. Start by writing a copy of the
3424 * first page with a bad version.
3426 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3427 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3428 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3432 addr = fw_img_start;
3433 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3434 addr += SF_PAGE_SIZE;
3435 fw_data += SF_PAGE_SIZE;
3436 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3441 ret = t4_write_flash(adap,
3442 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3443 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3446 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3449 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3454 * t4_phy_fw_ver - return current PHY firmware version
3455 * @adap: the adapter
3456 * @phy_fw_ver: return value buffer for PHY firmware version
3458 * Returns the current version of external PHY firmware on the
3461 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3466 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3467 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3468 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3469 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3479 * t4_load_phy_fw - download port PHY firmware
3480 * @adap: the adapter
3481 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3482 * @win_lock: the lock to use to guard the memory copy
3483 * @phy_fw_version: function to check PHY firmware versions
3484 * @phy_fw_data: the PHY firmware image to write
3485 * @phy_fw_size: image size
3487 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3488 * @phy_fw_version is supplied, then it will be used to determine if
3489 * it's necessary to perform the transfer by comparing the version
3490 * of any existing adapter PHY firmware with that of the passed in
3491 * PHY firmware image. If @win_lock is non-NULL then it will be used
3492 * around the call to t4_memory_rw() which transfers the PHY firmware
3495 * A negative error number will be returned if an error occurs. If
3496 * version number support is available and there's no need to upgrade
3497 * the firmware, 0 will be returned. If firmware is successfully
3498 * transferred to the adapter, 1 will be retured.
3500 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3501 * a result, a RESET of the adapter would cause that RAM to lose its
3502 * contents. Thus, loading PHY firmware on such adapters must happen
3503 * after any FW_RESET_CMDs ...
3505 int t4_load_phy_fw(struct adapter *adap,
3506 int win, spinlock_t *win_lock,
3507 int (*phy_fw_version)(const u8 *, size_t),
3508 const u8 *phy_fw_data, size_t phy_fw_size)
3510 unsigned long mtype = 0, maddr = 0;
3512 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3515 /* If we have version number support, then check to see if the adapter
3516 * already has up-to-date PHY firmware loaded.
3518 if (phy_fw_version) {
3519 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3520 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3524 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3525 CH_WARN(adap, "PHY Firmware already up-to-date, "
3526 "version %#x\n", cur_phy_fw_ver);
3531 /* Ask the firmware where it wants us to copy the PHY firmware image.
3532 * The size of the file requires a special version of the READ coommand
3533 * which will pass the file size via the values field in PARAMS_CMD and
3534 * retrieve the return value from firmware and place it in the same
3537 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3538 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3539 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3540 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3542 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3547 maddr = (val & 0xff) << 16;
3549 /* Copy the supplied PHY Firmware image to the adapter memory location
3550 * allocated by the adapter firmware.
3553 spin_lock_bh(win_lock);
3554 ret = t4_memory_rw(adap, win, mtype, maddr,
3555 phy_fw_size, (__be32 *)phy_fw_data,
3558 spin_unlock_bh(win_lock);
3562 /* Tell the firmware that the PHY firmware image has been written to
3563 * RAM and it can now start copying it over to the PHYs. The chip
3564 * firmware will RESET the affected PHYs as part of this operation
3565 * leaving them running the new PHY firmware image.
3567 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3568 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3569 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3570 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3571 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3572 ¶m, &val, 30000);
3574 /* If we have version number support, then check to see that the new
3575 * firmware got loaded properly.
3577 if (phy_fw_version) {
3578 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3582 if (cur_phy_fw_ver != new_phy_fw_vers) {
3583 CH_WARN(adap, "PHY Firmware did not update: "
3584 "version on adapter %#x, "
3585 "version flashed %#x\n",
3586 cur_phy_fw_ver, new_phy_fw_vers);
3595 * t4_fwcache - firmware cache operation
3596 * @adap: the adapter
3597 * @op : the operation (flush or flush and invalidate)
3599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3601 struct fw_params_cmd c;
3603 memset(&c, 0, sizeof(c));
3605 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3606 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3607 FW_PARAMS_CMD_PFN_V(adap->pf) |
3608 FW_PARAMS_CMD_VFN_V(0));
3609 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3611 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3612 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3613 c.param[0].val = (__force __be32)op;
3615 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3619 unsigned int *pif_req_wrptr,
3620 unsigned int *pif_rsp_wrptr)
3623 u32 cfg, val, req, rsp;
3625 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3626 if (cfg & LADBGEN_F)
3627 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3629 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3630 req = POLADBGWRPTR_G(val);
3631 rsp = PILADBGWRPTR_G(val);
3633 *pif_req_wrptr = req;
3635 *pif_rsp_wrptr = rsp;
3637 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3638 for (j = 0; j < 6; j++) {
3639 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3640 PILADBGRDPTR_V(rsp));
3641 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3642 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3646 req = (req + 2) & POLADBGRDPTR_M;
3647 rsp = (rsp + 2) & PILADBGRDPTR_M;
3649 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3652 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3657 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3658 if (cfg & LADBGEN_F)
3659 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3661 for (i = 0; i < CIM_MALA_SIZE; i++) {
3662 for (j = 0; j < 5; j++) {
3664 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3665 PILADBGRDPTR_V(idx));
3666 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3667 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3670 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3673 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3677 for (i = 0; i < 8; i++) {
3678 u32 *p = la_buf + i;
3680 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3681 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3682 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3683 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3684 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3688 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3689 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3690 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3694 * t4_link_l1cfg - apply link configuration to MAC/PHY
3695 * @phy: the PHY to setup
3696 * @mac: the MAC to setup
3697 * @lc: the requested link configuration
3699 * Set up a port's MAC and PHY according to a desired link configuration.
3700 * - If the PHY can auto-negotiate first decide what to advertise, then
3701 * enable/disable auto-negotiation as desired, and reset.
3702 * - If the PHY does not auto-negotiate just reset it.
3703 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3704 * otherwise do it later based on the outcome of auto-negotiation.
3706 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3707 struct link_config *lc)
3709 struct fw_port_cmd c;
3710 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3713 if (lc->requested_fc & PAUSE_RX)
3714 fc |= FW_PORT_CAP_FC_RX;
3715 if (lc->requested_fc & PAUSE_TX)
3716 fc |= FW_PORT_CAP_FC_TX;
3718 memset(&c, 0, sizeof(c));
3719 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3720 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3721 FW_PORT_CMD_PORTID_V(port));
3723 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3726 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3727 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3729 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3730 } else if (lc->autoneg == AUTONEG_DISABLE) {
3731 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3732 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3734 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3736 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3740 * t4_restart_aneg - restart autonegotiation
3741 * @adap: the adapter
3742 * @mbox: mbox to use for the FW command
3743 * @port: the port id
3745 * Restarts autonegotiation for the selected port.
3747 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3749 struct fw_port_cmd c;
3751 memset(&c, 0, sizeof(c));
3752 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3753 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3754 FW_PORT_CMD_PORTID_V(port));
3756 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3758 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3759 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3762 typedef void (*int_handler_t)(struct adapter *adap);
3765 unsigned int mask; /* bits to check in interrupt status */
3766 const char *msg; /* message to print or NULL */
3767 short stat_idx; /* stat counter to increment or -1 */
3768 unsigned short fatal; /* whether the condition reported is fatal */
3769 int_handler_t int_handler; /* platform-specific int handler */
3773 * t4_handle_intr_status - table driven interrupt handler
3774 * @adapter: the adapter that generated the interrupt
3775 * @reg: the interrupt status register to process
3776 * @acts: table of interrupt actions
3778 * A table driven interrupt handler that applies a set of masks to an
3779 * interrupt status word and performs the corresponding actions if the
3780 * interrupts described by the mask have occurred. The actions include
3781 * optionally emitting a warning or alert message. The table is terminated
3782 * by an entry specifying mask 0. Returns the number of fatal interrupt
3785 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3786 const struct intr_info *acts)
3789 unsigned int mask = 0;
3790 unsigned int status = t4_read_reg(adapter, reg);
3792 for ( ; acts->mask; ++acts) {
3793 if (!(status & acts->mask))
3797 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3798 status & acts->mask);
3799 } else if (acts->msg && printk_ratelimit())
3800 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3801 status & acts->mask);
3802 if (acts->int_handler)
3803 acts->int_handler(adapter);
3807 if (status) /* clear processed interrupts */
3808 t4_write_reg(adapter, reg, status);
3813 * Interrupt handler for the PCIE module.
3815 static void pcie_intr_handler(struct adapter *adapter)
3817 static const struct intr_info sysbus_intr_info[] = {
3818 { RNPP_F, "RXNP array parity error", -1, 1 },
3819 { RPCP_F, "RXPC array parity error", -1, 1 },
3820 { RCIP_F, "RXCIF array parity error", -1, 1 },
3821 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3822 { RFTP_F, "RXFT array parity error", -1, 1 },
3825 static const struct intr_info pcie_port_intr_info[] = {
3826 { TPCP_F, "TXPC array parity error", -1, 1 },
3827 { TNPP_F, "TXNP array parity error", -1, 1 },
3828 { TFTP_F, "TXFT array parity error", -1, 1 },
3829 { TCAP_F, "TXCA array parity error", -1, 1 },
3830 { TCIP_F, "TXCIF array parity error", -1, 1 },
3831 { RCAP_F, "RXCA array parity error", -1, 1 },
3832 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3833 { RDPE_F, "Rx data parity error", -1, 1 },
3834 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3837 static const struct intr_info pcie_intr_info[] = {
3838 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3839 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3840 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3841 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3842 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3843 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3844 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3845 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3846 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3847 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3848 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3849 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3850 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3851 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3852 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3853 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3854 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3855 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3856 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3857 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3858 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3859 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3860 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3861 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3862 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3863 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3864 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3865 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3866 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3867 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3872 static struct intr_info t5_pcie_intr_info[] = {
3873 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3875 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3876 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3877 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3878 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3879 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3880 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3881 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3883 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3885 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3886 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3887 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3888 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3889 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3891 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3892 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3893 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3894 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3895 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3896 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3897 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3898 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3899 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3900 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3901 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3903 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3905 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3906 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3907 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3908 { READRSPERR_F, "Outbound read error", -1, 0 },
3914 if (is_t4(adapter->params.chip))
3915 fat = t4_handle_intr_status(adapter,
3916 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3918 t4_handle_intr_status(adapter,
3919 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3920 pcie_port_intr_info) +
3921 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3924 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3928 t4_fatal_err(adapter);
3932 * TP interrupt handler.
3934 static void tp_intr_handler(struct adapter *adapter)
3936 static const struct intr_info tp_intr_info[] = {
3937 { 0x3fffffff, "TP parity error", -1, 1 },
3938 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3942 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3943 t4_fatal_err(adapter);
3947 * SGE interrupt handler.
3949 static void sge_intr_handler(struct adapter *adapter)
3954 static const struct intr_info sge_intr_info[] = {
3955 { ERR_CPL_EXCEED_IQE_SIZE_F,
3956 "SGE received CPL exceeding IQE size", -1, 1 },
3957 { ERR_INVALID_CIDX_INC_F,
3958 "SGE GTS CIDX increment too large", -1, 0 },
3959 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3960 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3961 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3962 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3963 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3965 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3967 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3969 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3971 { ERR_ING_CTXT_PRIO_F,
3972 "SGE too many priority ingress contexts", -1, 0 },
3973 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3974 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3978 static struct intr_info t4t5_sge_intr_info[] = {
3979 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3980 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3981 { ERR_EGR_CTXT_PRIO_F,
3982 "SGE too many priority egress contexts", -1, 0 },
3986 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3987 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3989 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3990 (unsigned long long)v);
3991 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3992 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3995 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3996 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3997 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3998 t4t5_sge_intr_info);
4000 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4001 if (err & ERROR_QID_VALID_F) {
4002 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4004 if (err & UNCAPTURED_ERROR_F)
4005 dev_err(adapter->pdev_dev,
4006 "SGE UNCAPTURED_ERROR set (clearing)\n");
4007 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4008 UNCAPTURED_ERROR_F);
4012 t4_fatal_err(adapter);
4015 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4016 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4017 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4018 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4021 * CIM interrupt handler.
4023 static void cim_intr_handler(struct adapter *adapter)
4025 static const struct intr_info cim_intr_info[] = {
4026 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4027 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4028 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4029 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4030 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4031 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4032 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4035 static const struct intr_info cim_upintr_info[] = {
4036 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4037 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4038 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4039 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4040 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4041 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4042 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4043 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4044 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4045 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4046 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4047 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4048 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4049 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4050 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4051 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4052 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4053 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4054 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4055 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4056 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4057 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4058 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4059 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4060 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4061 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4062 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4063 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4069 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
4070 t4_report_fw_error(adapter);
4072 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4074 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4077 t4_fatal_err(adapter);
4081 * ULP RX interrupt handler.
4083 static void ulprx_intr_handler(struct adapter *adapter)
4085 static const struct intr_info ulprx_intr_info[] = {
4086 { 0x1800000, "ULPRX context error", -1, 1 },
4087 { 0x7fffff, "ULPRX parity error", -1, 1 },
4091 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4092 t4_fatal_err(adapter);
4096 * ULP TX interrupt handler.
4098 static void ulptx_intr_handler(struct adapter *adapter)
4100 static const struct intr_info ulptx_intr_info[] = {
4101 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4103 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4105 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4107 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4109 { 0xfffffff, "ULPTX parity error", -1, 1 },
4113 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4114 t4_fatal_err(adapter);
4118 * PM TX interrupt handler.
4120 static void pmtx_intr_handler(struct adapter *adapter)
4122 static const struct intr_info pmtx_intr_info[] = {
4123 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4124 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4125 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4126 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4127 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4128 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4129 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4131 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4132 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4136 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4137 t4_fatal_err(adapter);
4141 * PM RX interrupt handler.
4143 static void pmrx_intr_handler(struct adapter *adapter)
4145 static const struct intr_info pmrx_intr_info[] = {
4146 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4147 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4148 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4149 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4151 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4152 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4156 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4157 t4_fatal_err(adapter);
4161 * CPL switch interrupt handler.
4163 static void cplsw_intr_handler(struct adapter *adapter)
4165 static const struct intr_info cplsw_intr_info[] = {
4166 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4167 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4168 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4169 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4170 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4171 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4175 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4176 t4_fatal_err(adapter);
4180 * LE interrupt handler.
4182 static void le_intr_handler(struct adapter *adap)
4184 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4185 static const struct intr_info le_intr_info[] = {
4186 { LIPMISS_F, "LE LIP miss", -1, 0 },
4187 { LIP0_F, "LE 0 LIP error", -1, 0 },
4188 { PARITYERR_F, "LE parity error", -1, 1 },
4189 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4190 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4194 static struct intr_info t6_le_intr_info[] = {
4195 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4196 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4197 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4198 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4199 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4203 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4204 (chip <= CHELSIO_T5) ?
4205 le_intr_info : t6_le_intr_info))
4210 * MPS interrupt handler.
4212 static void mps_intr_handler(struct adapter *adapter)
4214 static const struct intr_info mps_rx_intr_info[] = {
4215 { 0xffffff, "MPS Rx parity error", -1, 1 },
4218 static const struct intr_info mps_tx_intr_info[] = {
4219 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4220 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4221 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4223 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4225 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4226 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4227 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4230 static const struct intr_info mps_trc_intr_info[] = {
4231 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4232 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4234 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4237 static const struct intr_info mps_stat_sram_intr_info[] = {
4238 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4241 static const struct intr_info mps_stat_tx_intr_info[] = {
4242 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4245 static const struct intr_info mps_stat_rx_intr_info[] = {
4246 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4249 static const struct intr_info mps_cls_intr_info[] = {
4250 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4251 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4252 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4258 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4260 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4262 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4263 mps_trc_intr_info) +
4264 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4265 mps_stat_sram_intr_info) +
4266 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4267 mps_stat_tx_intr_info) +
4268 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4269 mps_stat_rx_intr_info) +
4270 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4273 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4274 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4276 t4_fatal_err(adapter);
4279 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4283 * EDC/MC interrupt handler.
4285 static void mem_intr_handler(struct adapter *adapter, int idx)
4287 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4289 unsigned int addr, cnt_addr, v;
4291 if (idx <= MEM_EDC1) {
4292 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4293 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4294 } else if (idx == MEM_MC) {
4295 if (is_t4(adapter->params.chip)) {
4296 addr = MC_INT_CAUSE_A;
4297 cnt_addr = MC_ECC_STATUS_A;
4299 addr = MC_P_INT_CAUSE_A;
4300 cnt_addr = MC_P_ECC_STATUS_A;
4303 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4304 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4307 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4308 if (v & PERR_INT_CAUSE_F)
4309 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4311 if (v & ECC_CE_INT_CAUSE_F) {
4312 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4314 t4_edc_err_read(adapter, idx);
4316 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4317 if (printk_ratelimit())
4318 dev_warn(adapter->pdev_dev,
4319 "%u %s correctable ECC data error%s\n",
4320 cnt, name[idx], cnt > 1 ? "s" : "");
4322 if (v & ECC_UE_INT_CAUSE_F)
4323 dev_alert(adapter->pdev_dev,
4324 "%s uncorrectable ECC data error\n", name[idx]);
4326 t4_write_reg(adapter, addr, v);
4327 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4328 t4_fatal_err(adapter);
4332 * MA interrupt handler.
4334 static void ma_intr_handler(struct adapter *adap)
4336 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4338 if (status & MEM_PERR_INT_CAUSE_F) {
4339 dev_alert(adap->pdev_dev,
4340 "MA parity error, parity status %#x\n",
4341 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4342 if (is_t5(adap->params.chip))
4343 dev_alert(adap->pdev_dev,
4344 "MA parity error, parity status %#x\n",
4346 MA_PARITY_ERROR_STATUS2_A));
4348 if (status & MEM_WRAP_INT_CAUSE_F) {
4349 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4350 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4351 "client %u to address %#x\n",
4352 MEM_WRAP_CLIENT_NUM_G(v),
4353 MEM_WRAP_ADDRESS_G(v) << 4);
4355 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4360 * SMB interrupt handler.
4362 static void smb_intr_handler(struct adapter *adap)
4364 static const struct intr_info smb_intr_info[] = {
4365 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4366 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4367 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4371 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4376 * NC-SI interrupt handler.
4378 static void ncsi_intr_handler(struct adapter *adap)
4380 static const struct intr_info ncsi_intr_info[] = {
4381 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4382 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4383 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4384 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4388 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4393 * XGMAC interrupt handler.
4395 static void xgmac_intr_handler(struct adapter *adap, int port)
4397 u32 v, int_cause_reg;
4399 if (is_t4(adap->params.chip))
4400 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4402 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4404 v = t4_read_reg(adap, int_cause_reg);
4406 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4410 if (v & TXFIFO_PRTY_ERR_F)
4411 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4413 if (v & RXFIFO_PRTY_ERR_F)
4414 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4416 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4421 * PL interrupt handler.
4423 static void pl_intr_handler(struct adapter *adap)
4425 static const struct intr_info pl_intr_info[] = {
4426 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4427 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4431 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4435 #define PF_INTR_MASK (PFSW_F)
4436 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4437 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4438 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4441 * t4_slow_intr_handler - control path interrupt handler
4442 * @adapter: the adapter
4444 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4445 * The designation 'slow' is because it involves register reads, while
4446 * data interrupts typically don't involve any MMIOs.
4448 int t4_slow_intr_handler(struct adapter *adapter)
4450 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4452 if (!(cause & GLBL_INTR_MASK))
4455 cim_intr_handler(adapter);
4457 mps_intr_handler(adapter);
4459 ncsi_intr_handler(adapter);
4461 pl_intr_handler(adapter);
4463 smb_intr_handler(adapter);
4464 if (cause & XGMAC0_F)
4465 xgmac_intr_handler(adapter, 0);
4466 if (cause & XGMAC1_F)
4467 xgmac_intr_handler(adapter, 1);
4468 if (cause & XGMAC_KR0_F)
4469 xgmac_intr_handler(adapter, 2);
4470 if (cause & XGMAC_KR1_F)
4471 xgmac_intr_handler(adapter, 3);
4473 pcie_intr_handler(adapter);
4475 mem_intr_handler(adapter, MEM_MC);
4476 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4477 mem_intr_handler(adapter, MEM_MC1);
4479 mem_intr_handler(adapter, MEM_EDC0);
4481 mem_intr_handler(adapter, MEM_EDC1);
4483 le_intr_handler(adapter);
4485 tp_intr_handler(adapter);
4487 ma_intr_handler(adapter);
4488 if (cause & PM_TX_F)
4489 pmtx_intr_handler(adapter);
4490 if (cause & PM_RX_F)
4491 pmrx_intr_handler(adapter);
4492 if (cause & ULP_RX_F)
4493 ulprx_intr_handler(adapter);
4494 if (cause & CPL_SWITCH_F)
4495 cplsw_intr_handler(adapter);
4497 sge_intr_handler(adapter);
4498 if (cause & ULP_TX_F)
4499 ulptx_intr_handler(adapter);
4501 /* Clear the interrupts just processed for which we are the master. */
4502 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4503 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4508 * t4_intr_enable - enable interrupts
4509 * @adapter: the adapter whose interrupts should be enabled
4511 * Enable PF-specific interrupts for the calling function and the top-level
4512 * interrupt concentrator for global interrupts. Interrupts are already
4513 * enabled at each module, here we just enable the roots of the interrupt
4516 * Note: this function should be called only when the driver manages
4517 * non PF-specific interrupts from the various HW modules. Only one PCI
4518 * function at a time should be doing this.
4520 void t4_intr_enable(struct adapter *adapter)
4523 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4524 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4525 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4527 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4528 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4529 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4530 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4531 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4532 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4533 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4534 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4535 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4536 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4537 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4541 * t4_intr_disable - disable interrupts
4542 * @adapter: the adapter whose interrupts should be disabled
4544 * Disable interrupts. We only disable the top-level interrupt
4545 * concentrators. The caller must be a PCI function managing global
4548 void t4_intr_disable(struct adapter *adapter)
4550 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4551 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4552 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4554 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4555 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4559 * t4_config_rss_range - configure a portion of the RSS mapping table
4560 * @adapter: the adapter
4561 * @mbox: mbox to use for the FW command
4562 * @viid: virtual interface whose RSS subtable is to be written
4563 * @start: start entry in the table to write
4564 * @n: how many table entries to write
4565 * @rspq: values for the response queue lookup table
4566 * @nrspq: number of values in @rspq
4568 * Programs the selected part of the VI's RSS mapping table with the
4569 * provided values. If @nrspq < @n the supplied values are used repeatedly
4570 * until the full table range is populated.
4572 * The caller must ensure the values in @rspq are in the range allowed for
4575 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4576 int start, int n, const u16 *rspq, unsigned int nrspq)
4579 const u16 *rsp = rspq;
4580 const u16 *rsp_end = rspq + nrspq;
4581 struct fw_rss_ind_tbl_cmd cmd;
4583 memset(&cmd, 0, sizeof(cmd));
4584 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4585 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4586 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4587 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4589 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4591 int nq = min(n, 32);
4592 __be32 *qp = &cmd.iq0_to_iq2;
4594 cmd.niqid = cpu_to_be16(nq);
4595 cmd.startidx = cpu_to_be16(start);
4603 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4604 if (++rsp >= rsp_end)
4606 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4607 if (++rsp >= rsp_end)
4609 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4610 if (++rsp >= rsp_end)
4613 *qp++ = cpu_to_be32(v);
4617 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4625 * t4_config_glbl_rss - configure the global RSS mode
4626 * @adapter: the adapter
4627 * @mbox: mbox to use for the FW command
4628 * @mode: global RSS mode
4629 * @flags: mode-specific flags
4631 * Sets the global RSS mode.
4633 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4636 struct fw_rss_glb_config_cmd c;
4638 memset(&c, 0, sizeof(c));
4639 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4640 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4641 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4642 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4643 c.u.manual.mode_pkd =
4644 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4645 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4646 c.u.basicvirtual.mode_pkd =
4647 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4648 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4651 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4655 * t4_config_vi_rss - configure per VI RSS settings
4656 * @adapter: the adapter
4657 * @mbox: mbox to use for the FW command
4660 * @defq: id of the default RSS queue for the VI.
4662 * Configures VI-specific RSS properties.
4664 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4665 unsigned int flags, unsigned int defq)
4667 struct fw_rss_vi_config_cmd c;
4669 memset(&c, 0, sizeof(c));
4670 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4671 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4672 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4673 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4674 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4675 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4676 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4679 /* Read an RSS table row */
4680 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4682 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4683 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4688 * t4_read_rss - read the contents of the RSS mapping table
4689 * @adapter: the adapter
4690 * @map: holds the contents of the RSS mapping table
4692 * Reads the contents of the RSS hash->queue mapping table.
4694 int t4_read_rss(struct adapter *adapter, u16 *map)
4699 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4700 ret = rd_rss_row(adapter, i, &val);
4703 *map++ = LKPTBLQUEUE0_G(val);
4704 *map++ = LKPTBLQUEUE1_G(val);
4709 static unsigned int t4_use_ldst(struct adapter *adap)
4711 return (adap->flags & FW_OK) || !adap->use_bd;
4715 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4716 * @adap: the adapter
4717 * @vals: where the indirect register values are stored/written
4718 * @nregs: how many indirect registers to read/write
4719 * @start_idx: index of first indirect register to read/write
4720 * @rw: Read (1) or Write (0)
4722 * Access TP PIO registers through LDST
4724 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4725 unsigned int start_index, unsigned int rw)
4728 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4729 struct fw_ldst_cmd c;
4731 for (i = 0 ; i < nregs; i++) {
4732 memset(&c, 0, sizeof(c));
4733 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4735 (rw ? FW_CMD_READ_F :
4737 FW_LDST_CMD_ADDRSPACE_V(cmd));
4738 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4740 c.u.addrval.addr = cpu_to_be32(start_index + i);
4741 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4742 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4744 vals[i] = be32_to_cpu(c.u.addrval.val);
4749 * t4_read_rss_key - read the global RSS key
4750 * @adap: the adapter
4751 * @key: 10-entry array holding the 320-bit RSS key
4753 * Reads the global 320-bit RSS key.
4755 void t4_read_rss_key(struct adapter *adap, u32 *key)
4757 if (t4_use_ldst(adap))
4758 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4760 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4761 TP_RSS_SECRET_KEY0_A);
4765 * t4_write_rss_key - program one of the RSS keys
4766 * @adap: the adapter
4767 * @key: 10-entry array holding the 320-bit RSS key
4768 * @idx: which RSS key to write
4770 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4771 * 0..15 the corresponding entry in the RSS key table is written,
4772 * otherwise the global RSS key is written.
4774 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4776 u8 rss_key_addr_cnt = 16;
4777 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4779 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4780 * allows access to key addresses 16-63 by using KeyWrAddrX
4781 * as index[5:4](upper 2) into key table
4783 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4784 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4785 rss_key_addr_cnt = 32;
4787 if (t4_use_ldst(adap))
4788 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4790 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4791 TP_RSS_SECRET_KEY0_A);
4793 if (idx >= 0 && idx < rss_key_addr_cnt) {
4794 if (rss_key_addr_cnt > 16)
4795 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4796 KEYWRADDRX_V(idx >> 4) |
4797 T6_VFWRADDR_V(idx) | KEYWREN_F);
4799 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4800 KEYWRADDR_V(idx) | KEYWREN_F);
4805 * t4_read_rss_pf_config - read PF RSS Configuration Table
4806 * @adapter: the adapter
4807 * @index: the entry in the PF RSS table to read
4808 * @valp: where to store the returned value
4810 * Reads the PF RSS Configuration Table at the specified index and returns
4811 * the value found there.
4813 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4816 if (t4_use_ldst(adapter))
4817 t4_fw_tp_pio_rw(adapter, valp, 1,
4818 TP_RSS_PF0_CONFIG_A + index, 1);
4820 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4821 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4825 * t4_read_rss_vf_config - read VF RSS Configuration Table
4826 * @adapter: the adapter
4827 * @index: the entry in the VF RSS table to read
4828 * @vfl: where to store the returned VFL
4829 * @vfh: where to store the returned VFH
4831 * Reads the VF RSS Configuration Table at the specified index and returns
4832 * the (VFL, VFH) values found there.
4834 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4837 u32 vrt, mask, data;
4839 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4840 mask = VFWRADDR_V(VFWRADDR_M);
4841 data = VFWRADDR_V(index);
4843 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4844 data = T6_VFWRADDR_V(index);
4847 /* Request that the index'th VF Table values be read into VFL/VFH.
4849 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4850 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4851 vrt |= data | VFRDEN_F;
4852 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4854 /* Grab the VFL/VFH values ...
4856 if (t4_use_ldst(adapter)) {
4857 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4858 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4860 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4861 vfl, 1, TP_RSS_VFL_CONFIG_A);
4862 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4863 vfh, 1, TP_RSS_VFH_CONFIG_A);
4868 * t4_read_rss_pf_map - read PF RSS Map
4869 * @adapter: the adapter
4871 * Reads the PF RSS Map register and returns its value.
4873 u32 t4_read_rss_pf_map(struct adapter *adapter)
4877 if (t4_use_ldst(adapter))
4878 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4880 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4881 &pfmap, 1, TP_RSS_PF_MAP_A);
4886 * t4_read_rss_pf_mask - read PF RSS Mask
4887 * @adapter: the adapter
4889 * Reads the PF RSS Mask register and returns its value.
4891 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4895 if (t4_use_ldst(adapter))
4896 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4898 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4899 &pfmask, 1, TP_RSS_PF_MSK_A);
4904 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4905 * @adap: the adapter
4906 * @v4: holds the TCP/IP counter values
4907 * @v6: holds the TCP/IPv6 counter values
4909 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4910 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4912 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4913 struct tp_tcp_stats *v6)
4915 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4917 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4918 #define STAT(x) val[STAT_IDX(x)]
4919 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4922 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4923 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4924 v4->tcp_out_rsts = STAT(OUT_RST);
4925 v4->tcp_in_segs = STAT64(IN_SEG);
4926 v4->tcp_out_segs = STAT64(OUT_SEG);
4927 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4930 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4931 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4932 v6->tcp_out_rsts = STAT(OUT_RST);
4933 v6->tcp_in_segs = STAT64(IN_SEG);
4934 v6->tcp_out_segs = STAT64(OUT_SEG);
4935 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4943 * t4_tp_get_err_stats - read TP's error MIB counters
4944 * @adap: the adapter
4945 * @st: holds the counter values
4947 * Returns the values of TP's error counters.
4949 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4951 int nchan = adap->params.arch.nchan;
4953 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4954 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4955 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4956 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4957 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4958 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4959 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4960 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4961 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4962 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4963 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4964 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4965 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4966 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4967 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4968 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4970 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4971 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4975 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4976 * @adap: the adapter
4977 * @st: holds the counter values
4979 * Returns the values of TP's CPL counters.
4981 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4983 int nchan = adap->params.arch.nchan;
4985 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4986 nchan, TP_MIB_CPL_IN_REQ_0_A);
4987 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4988 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4993 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4994 * @adap: the adapter
4995 * @st: holds the counter values
4997 * Returns the values of TP's RDMA counters.
4999 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5001 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5002 2, TP_MIB_RQE_DFR_PKT_A);
5006 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5007 * @adap: the adapter
5008 * @idx: the port index
5009 * @st: holds the counter values
5011 * Returns the values of TP's FCoE counters for the selected port.
5013 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5014 struct tp_fcoe_stats *st)
5018 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5019 1, TP_MIB_FCOE_DDP_0_A + idx);
5020 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5021 1, TP_MIB_FCOE_DROP_0_A + idx);
5022 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5023 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5024 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5028 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5029 * @adap: the adapter
5030 * @st: holds the counter values
5032 * Returns the values of TP's counters for non-TCP directly-placed packets.
5034 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5038 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5040 st->frames = val[0];
5042 st->octets = ((u64)val[2] << 32) | val[3];
5046 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5047 * @adap: the adapter
5048 * @mtus: where to store the MTU values
5049 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5051 * Reads the HW path MTU table.
5053 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5058 for (i = 0; i < NMTUS; ++i) {
5059 t4_write_reg(adap, TP_MTU_TABLE_A,
5060 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5061 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5062 mtus[i] = MTUVALUE_G(v);
5064 mtu_log[i] = MTUWIDTH_G(v);
5069 * t4_read_cong_tbl - reads the congestion control table
5070 * @adap: the adapter
5071 * @incr: where to store the alpha values
5073 * Reads the additive increments programmed into the HW congestion
5076 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5078 unsigned int mtu, w;
5080 for (mtu = 0; mtu < NMTUS; ++mtu)
5081 for (w = 0; w < NCCTRL_WIN; ++w) {
5082 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5083 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5084 incr[mtu][w] = (u16)t4_read_reg(adap,
5085 TP_CCTRL_TABLE_A) & 0x1fff;
5090 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5091 * @adap: the adapter
5092 * @addr: the indirect TP register address
5093 * @mask: specifies the field within the register to modify
5094 * @val: new value for the field
5096 * Sets a field of an indirect TP register to the given value.
5098 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5099 unsigned int mask, unsigned int val)
5101 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5102 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5103 t4_write_reg(adap, TP_PIO_DATA_A, val);
5107 * init_cong_ctrl - initialize congestion control parameters
5108 * @a: the alpha values for congestion control
5109 * @b: the beta values for congestion control
5111 * Initialize the congestion control parameters.
5113 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5115 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5140 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5143 b[13] = b[14] = b[15] = b[16] = 3;
5144 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5145 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5150 /* The minimum additive increment value for the congestion control table */
5151 #define CC_MIN_INCR 2U
5154 * t4_load_mtus - write the MTU and congestion control HW tables
5155 * @adap: the adapter
5156 * @mtus: the values for the MTU table
5157 * @alpha: the values for the congestion control alpha parameter
5158 * @beta: the values for the congestion control beta parameter
5160 * Write the HW MTU table with the supplied MTUs and the high-speed
5161 * congestion control table with the supplied alpha, beta, and MTUs.
5162 * We write the two tables together because the additive increments
5163 * depend on the MTUs.
5165 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5166 const unsigned short *alpha, const unsigned short *beta)
5168 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5169 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5170 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5171 28672, 40960, 57344, 81920, 114688, 163840, 229376
5176 for (i = 0; i < NMTUS; ++i) {
5177 unsigned int mtu = mtus[i];
5178 unsigned int log2 = fls(mtu);
5180 if (!(mtu & ((1 << log2) >> 2))) /* round */
5182 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5183 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5185 for (w = 0; w < NCCTRL_WIN; ++w) {
5188 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5191 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5192 (w << 16) | (beta[w] << 13) | inc);
5197 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5198 * clocks. The formula is
5200 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5202 * which is equivalent to
5204 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5206 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5208 u64 v = bytes256 * adap->params.vpd.cclk;
5210 return v * 62 + v / 2;
5214 * t4_get_chan_txrate - get the current per channel Tx rates
5215 * @adap: the adapter
5216 * @nic_rate: rates for NIC traffic
5217 * @ofld_rate: rates for offloaded traffic
5219 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5222 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5226 v = t4_read_reg(adap, TP_TX_TRATE_A);
5227 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5228 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5229 if (adap->params.arch.nchan == NCHAN) {
5230 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5231 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5234 v = t4_read_reg(adap, TP_TX_ORATE_A);
5235 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5236 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5237 if (adap->params.arch.nchan == NCHAN) {
5238 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5239 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5244 * t4_set_trace_filter - configure one of the tracing filters
5245 * @adap: the adapter
5246 * @tp: the desired trace filter parameters
5247 * @idx: which filter to configure
5248 * @enable: whether to enable or disable the filter
5250 * Configures one of the tracing filters available in HW. If @enable is
5251 * %0 @tp is not examined and may be %NULL. The user is responsible to
5252 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5254 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5255 int idx, int enable)
5257 int i, ofst = idx * 4;
5258 u32 data_reg, mask_reg, cfg;
5259 u32 multitrc = TRCMULTIFILTER_F;
5262 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5266 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5267 if (cfg & TRCMULTIFILTER_F) {
5268 /* If multiple tracers are enabled, then maximum
5269 * capture size is 2.5KB (FIFO size of a single channel)
5270 * minus 2 flits for CPL_TRACE_PKT header.
5272 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5275 /* If multiple tracers are disabled, to avoid deadlocks
5276 * maximum packet capture size of 9600 bytes is recommended.
5277 * Also in this mode, only trace0 can be enabled and running.
5280 if (tp->snap_len > 9600 || idx)
5284 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5285 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5286 tp->min_len > TFMINPKTSIZE_M)
5289 /* stop the tracer we'll be changing */
5290 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5292 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5293 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5294 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5296 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5297 t4_write_reg(adap, data_reg, tp->data[i]);
5298 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5300 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5301 TFCAPTUREMAX_V(tp->snap_len) |
5302 TFMINPKTSIZE_V(tp->min_len));
5303 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5304 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5305 (is_t4(adap->params.chip) ?
5306 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5307 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5308 T5_TFINVERTMATCH_V(tp->invert)));
5314 * t4_get_trace_filter - query one of the tracing filters
5315 * @adap: the adapter
5316 * @tp: the current trace filter parameters
5317 * @idx: which trace filter to query
5318 * @enabled: non-zero if the filter is enabled
5320 * Returns the current settings of one of the HW tracing filters.
5322 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5326 int i, ofst = idx * 4;
5327 u32 data_reg, mask_reg;
5329 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5330 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5332 if (is_t4(adap->params.chip)) {
5333 *enabled = !!(ctla & TFEN_F);
5334 tp->port = TFPORT_G(ctla);
5335 tp->invert = !!(ctla & TFINVERTMATCH_F);
5337 *enabled = !!(ctla & T5_TFEN_F);
5338 tp->port = T5_TFPORT_G(ctla);
5339 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5341 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5342 tp->min_len = TFMINPKTSIZE_G(ctlb);
5343 tp->skip_ofst = TFOFFSET_G(ctla);
5344 tp->skip_len = TFLENGTH_G(ctla);
5346 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5347 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5348 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5350 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5351 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5352 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5357 * t4_pmtx_get_stats - returns the HW stats from PMTX
5358 * @adap: the adapter
5359 * @cnt: where to store the count statistics
5360 * @cycles: where to store the cycle statistics
5362 * Returns performance statistics from PMTX.
5364 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5369 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5370 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5371 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5372 if (is_t4(adap->params.chip)) {
5373 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5375 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5376 PM_TX_DBG_DATA_A, data, 2,
5377 PM_TX_DBG_STAT_MSB_A);
5378 cycles[i] = (((u64)data[0] << 32) | data[1]);
5384 * t4_pmrx_get_stats - returns the HW stats from PMRX
5385 * @adap: the adapter
5386 * @cnt: where to store the count statistics
5387 * @cycles: where to store the cycle statistics
5389 * Returns performance statistics from PMRX.
5391 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5396 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5397 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5398 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5399 if (is_t4(adap->params.chip)) {
5400 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5402 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5403 PM_RX_DBG_DATA_A, data, 2,
5404 PM_RX_DBG_STAT_MSB_A);
5405 cycles[i] = (((u64)data[0] << 32) | data[1]);
5411 * t4_get_mps_bg_map - return the buffer groups associated with a port
5412 * @adap: the adapter
5413 * @idx: the port index
5415 * Returns a bitmap indicating which MPS buffer groups are associated
5416 * with the given port. Bit i is set if buffer group i is used by the
5419 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5421 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5424 return idx == 0 ? 0xf : 0;
5425 /* In T6 (which is a 2 port card),
5426 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5427 * For 2 port T4/T5 adapter,
5428 * port 0 is mapped to channel 0 and 1,
5429 * port 1 is mapped to channel 2 and 3.
5432 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5433 return idx < 2 ? (3 << (2 * idx)) : 0;
5438 * t4_get_port_type_description - return Port Type string description
5439 * @port_type: firmware Port Type enumeration
5441 const char *t4_get_port_type_description(enum fw_port_type port_type)
5443 static const char *const port_type_description[] = {
5468 if (port_type < ARRAY_SIZE(port_type_description))
5469 return port_type_description[port_type];
5474 * t4_get_port_stats_offset - collect port stats relative to a previous
5476 * @adap: The adapter
5478 * @stats: Current stats to fill
5479 * @offset: Previous stats snapshot
5481 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5482 struct port_stats *stats,
5483 struct port_stats *offset)
5488 t4_get_port_stats(adap, idx, stats);
5489 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5490 i < (sizeof(struct port_stats) / sizeof(u64));
5496 * t4_get_port_stats - collect port statistics
5497 * @adap: the adapter
5498 * @idx: the port index
5499 * @p: the stats structure to fill
5501 * Collect statistics related to the given port from HW.
5503 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5505 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5506 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5508 #define GET_STAT(name) \
5509 t4_read_reg64(adap, \
5510 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5511 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5512 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5514 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5515 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5516 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5517 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5518 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5519 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5520 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5521 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5522 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5523 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5524 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5525 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5526 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5527 p->tx_drop = GET_STAT(TX_PORT_DROP);
5528 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5529 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5530 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5531 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5532 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5533 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5534 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5535 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5536 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5538 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5539 if (stat_ctl & COUNTPAUSESTATTX_F) {
5540 p->tx_frames -= p->tx_pause;
5541 p->tx_octets -= p->tx_pause * 64;
5543 if (stat_ctl & COUNTPAUSEMCTX_F)
5544 p->tx_mcast_frames -= p->tx_pause;
5546 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5547 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5548 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5549 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5550 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5551 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5552 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5553 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5554 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5555 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5556 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5557 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5558 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5559 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5560 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5561 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5562 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5563 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5564 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5565 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5566 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5567 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5568 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5569 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5570 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5571 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5572 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5574 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5575 if (stat_ctl & COUNTPAUSESTATRX_F) {
5576 p->rx_frames -= p->rx_pause;
5577 p->rx_octets -= p->rx_pause * 64;
5579 if (stat_ctl & COUNTPAUSEMCRX_F)
5580 p->rx_mcast_frames -= p->rx_pause;
5583 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5584 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5585 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5586 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5587 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5588 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5589 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5590 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5597 * t4_get_lb_stats - collect loopback port statistics
5598 * @adap: the adapter
5599 * @idx: the loopback port index
5600 * @p: the stats structure to fill
5602 * Return HW statistics for the given loopback port.
5604 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5606 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5608 #define GET_STAT(name) \
5609 t4_read_reg64(adap, \
5610 (is_t4(adap->params.chip) ? \
5611 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5612 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5613 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5615 p->octets = GET_STAT(BYTES);
5616 p->frames = GET_STAT(FRAMES);
5617 p->bcast_frames = GET_STAT(BCAST);
5618 p->mcast_frames = GET_STAT(MCAST);
5619 p->ucast_frames = GET_STAT(UCAST);
5620 p->error_frames = GET_STAT(ERROR);
5622 p->frames_64 = GET_STAT(64B);
5623 p->frames_65_127 = GET_STAT(65B_127B);
5624 p->frames_128_255 = GET_STAT(128B_255B);
5625 p->frames_256_511 = GET_STAT(256B_511B);
5626 p->frames_512_1023 = GET_STAT(512B_1023B);
5627 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5628 p->frames_1519_max = GET_STAT(1519B_MAX);
5629 p->drop = GET_STAT(DROP_FRAMES);
5631 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5632 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5633 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5634 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5635 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5636 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5637 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5638 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5644 /* t4_mk_filtdelwr - create a delete filter WR
5645 * @ftid: the filter ID
5646 * @wr: the filter work request to populate
5647 * @qid: ingress queue to receive the delete notification
5649 * Creates a filter work request to delete the supplied filter. If @qid is
5650 * negative the delete notification is suppressed.
5652 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5654 memset(wr, 0, sizeof(*wr));
5655 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5656 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5657 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5658 FW_FILTER_WR_NOREPLY_V(qid < 0));
5659 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5661 wr->rx_chan_rx_rpl_iq =
5662 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5665 #define INIT_CMD(var, cmd, rd_wr) do { \
5666 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5667 FW_CMD_REQUEST_F | \
5668 FW_CMD_##rd_wr##_F); \
5669 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5672 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5676 struct fw_ldst_cmd c;
5678 memset(&c, 0, sizeof(c));
5679 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5680 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5684 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5685 c.u.addrval.addr = cpu_to_be32(addr);
5686 c.u.addrval.val = cpu_to_be32(val);
5688 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5692 * t4_mdio_rd - read a PHY register through MDIO
5693 * @adap: the adapter
5694 * @mbox: mailbox to use for the FW command
5695 * @phy_addr: the PHY address
5696 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5697 * @reg: the register to read
5698 * @valp: where to store the value
5700 * Issues a FW command through the given mailbox to read a PHY register.
5702 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5703 unsigned int mmd, unsigned int reg, u16 *valp)
5707 struct fw_ldst_cmd c;
5709 memset(&c, 0, sizeof(c));
5710 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5711 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5712 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5714 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5715 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5716 FW_LDST_CMD_MMD_V(mmd));
5717 c.u.mdio.raddr = cpu_to_be16(reg);
5719 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5721 *valp = be16_to_cpu(c.u.mdio.rval);
5726 * t4_mdio_wr - write a PHY register through MDIO
5727 * @adap: the adapter
5728 * @mbox: mailbox to use for the FW command
5729 * @phy_addr: the PHY address
5730 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5731 * @reg: the register to write
5732 * @valp: value to write
5734 * Issues a FW command through the given mailbox to write a PHY register.
5736 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5737 unsigned int mmd, unsigned int reg, u16 val)
5740 struct fw_ldst_cmd c;
5742 memset(&c, 0, sizeof(c));
5743 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5744 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5745 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5747 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5748 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5749 FW_LDST_CMD_MMD_V(mmd));
5750 c.u.mdio.raddr = cpu_to_be16(reg);
5751 c.u.mdio.rval = cpu_to_be16(val);
5753 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5757 * t4_sge_decode_idma_state - decode the idma state
5758 * @adap: the adapter
5759 * @state: the state idma is stuck in
5761 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5763 static const char * const t4_decode[] = {
5765 "IDMA_PUSH_MORE_CPL_FIFO",
5766 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5768 "IDMA_PHYSADDR_SEND_PCIEHDR",
5769 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5770 "IDMA_PHYSADDR_SEND_PAYLOAD",
5771 "IDMA_SEND_FIFO_TO_IMSG",
5772 "IDMA_FL_REQ_DATA_FL_PREP",
5773 "IDMA_FL_REQ_DATA_FL",
5775 "IDMA_FL_H_REQ_HEADER_FL",
5776 "IDMA_FL_H_SEND_PCIEHDR",
5777 "IDMA_FL_H_PUSH_CPL_FIFO",
5778 "IDMA_FL_H_SEND_CPL",
5779 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5780 "IDMA_FL_H_SEND_IP_HDR",
5781 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5782 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5783 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5784 "IDMA_FL_D_SEND_PCIEHDR",
5785 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5786 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5787 "IDMA_FL_SEND_PCIEHDR",
5788 "IDMA_FL_PUSH_CPL_FIFO",
5790 "IDMA_FL_SEND_PAYLOAD_FIRST",
5791 "IDMA_FL_SEND_PAYLOAD",
5792 "IDMA_FL_REQ_NEXT_DATA_FL",
5793 "IDMA_FL_SEND_NEXT_PCIEHDR",
5794 "IDMA_FL_SEND_PADDING",
5795 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5796 "IDMA_FL_SEND_FIFO_TO_IMSG",
5797 "IDMA_FL_REQ_DATAFL_DONE",
5798 "IDMA_FL_REQ_HEADERFL_DONE",
5800 static const char * const t5_decode[] = {
5803 "IDMA_PUSH_MORE_CPL_FIFO",
5804 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5805 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5806 "IDMA_PHYSADDR_SEND_PCIEHDR",
5807 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5808 "IDMA_PHYSADDR_SEND_PAYLOAD",
5809 "IDMA_SEND_FIFO_TO_IMSG",
5810 "IDMA_FL_REQ_DATA_FL",
5812 "IDMA_FL_DROP_SEND_INC",
5813 "IDMA_FL_H_REQ_HEADER_FL",
5814 "IDMA_FL_H_SEND_PCIEHDR",
5815 "IDMA_FL_H_PUSH_CPL_FIFO",
5816 "IDMA_FL_H_SEND_CPL",
5817 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5818 "IDMA_FL_H_SEND_IP_HDR",
5819 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5820 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5821 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5822 "IDMA_FL_D_SEND_PCIEHDR",
5823 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5824 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5825 "IDMA_FL_SEND_PCIEHDR",
5826 "IDMA_FL_PUSH_CPL_FIFO",
5828 "IDMA_FL_SEND_PAYLOAD_FIRST",
5829 "IDMA_FL_SEND_PAYLOAD",
5830 "IDMA_FL_REQ_NEXT_DATA_FL",
5831 "IDMA_FL_SEND_NEXT_PCIEHDR",
5832 "IDMA_FL_SEND_PADDING",
5833 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5835 static const char * const t6_decode[] = {
5837 "IDMA_PUSH_MORE_CPL_FIFO",
5838 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5839 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5840 "IDMA_PHYSADDR_SEND_PCIEHDR",
5841 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5842 "IDMA_PHYSADDR_SEND_PAYLOAD",
5843 "IDMA_FL_REQ_DATA_FL",
5845 "IDMA_FL_DROP_SEND_INC",
5846 "IDMA_FL_H_REQ_HEADER_FL",
5847 "IDMA_FL_H_SEND_PCIEHDR",
5848 "IDMA_FL_H_PUSH_CPL_FIFO",
5849 "IDMA_FL_H_SEND_CPL",
5850 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5851 "IDMA_FL_H_SEND_IP_HDR",
5852 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5853 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5854 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5855 "IDMA_FL_D_SEND_PCIEHDR",
5856 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5857 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5858 "IDMA_FL_SEND_PCIEHDR",
5859 "IDMA_FL_PUSH_CPL_FIFO",
5861 "IDMA_FL_SEND_PAYLOAD_FIRST",
5862 "IDMA_FL_SEND_PAYLOAD",
5863 "IDMA_FL_REQ_NEXT_DATA_FL",
5864 "IDMA_FL_SEND_NEXT_PCIEHDR",
5865 "IDMA_FL_SEND_PADDING",
5866 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5868 static const u32 sge_regs[] = {
5869 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5870 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5871 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5873 const char **sge_idma_decode;
5874 int sge_idma_decode_nstates;
5876 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5878 /* Select the right set of decode strings to dump depending on the
5879 * adapter chip type.
5881 switch (chip_version) {
5883 sge_idma_decode = (const char **)t4_decode;
5884 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5888 sge_idma_decode = (const char **)t5_decode;
5889 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5893 sge_idma_decode = (const char **)t6_decode;
5894 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5898 dev_err(adapter->pdev_dev,
5899 "Unsupported chip version %d\n", chip_version);
5903 if (is_t4(adapter->params.chip)) {
5904 sge_idma_decode = (const char **)t4_decode;
5905 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5907 sge_idma_decode = (const char **)t5_decode;
5908 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5911 if (state < sge_idma_decode_nstates)
5912 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5914 CH_WARN(adapter, "idma state %d unknown\n", state);
5916 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5917 CH_WARN(adapter, "SGE register %#x value %#x\n",
5918 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5922 * t4_sge_ctxt_flush - flush the SGE context cache
5923 * @adap: the adapter
5924 * @mbox: mailbox to use for the FW command
5926 * Issues a FW command through the given mailbox to flush the
5927 * SGE context cache.
5929 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5933 struct fw_ldst_cmd c;
5935 memset(&c, 0, sizeof(c));
5936 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5937 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5938 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5940 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5941 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5943 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5948 * t4_fw_hello - establish communication with FW
5949 * @adap: the adapter
5950 * @mbox: mailbox to use for the FW command
5951 * @evt_mbox: mailbox to receive async FW events
5952 * @master: specifies the caller's willingness to be the device master
5953 * @state: returns the current device state (if non-NULL)
5955 * Issues a command to establish communication with FW. Returns either
5956 * an error (negative integer) or the mailbox of the Master PF.
5958 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5959 enum dev_master master, enum dev_state *state)
5962 struct fw_hello_cmd c;
5964 unsigned int master_mbox;
5965 int retries = FW_CMD_HELLO_RETRIES;
5968 memset(&c, 0, sizeof(c));
5969 INIT_CMD(c, HELLO, WRITE);
5970 c.err_to_clearinit = cpu_to_be32(
5971 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5972 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5973 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5974 mbox : FW_HELLO_CMD_MBMASTER_M) |
5975 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5976 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5977 FW_HELLO_CMD_CLEARINIT_F);
5980 * Issue the HELLO command to the firmware. If it's not successful
5981 * but indicates that we got a "busy" or "timeout" condition, retry
5982 * the HELLO until we exhaust our retry limit. If we do exceed our
5983 * retry limit, check to see if the firmware left us any error
5984 * information and report that if so.
5986 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5988 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5990 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5991 t4_report_fw_error(adap);
5995 v = be32_to_cpu(c.err_to_clearinit);
5996 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5998 if (v & FW_HELLO_CMD_ERR_F)
5999 *state = DEV_STATE_ERR;
6000 else if (v & FW_HELLO_CMD_INIT_F)
6001 *state = DEV_STATE_INIT;
6003 *state = DEV_STATE_UNINIT;
6007 * If we're not the Master PF then we need to wait around for the
6008 * Master PF Driver to finish setting up the adapter.
6010 * Note that we also do this wait if we're a non-Master-capable PF and
6011 * there is no current Master PF; a Master PF may show up momentarily
6012 * and we wouldn't want to fail pointlessly. (This can happen when an
6013 * OS loads lots of different drivers rapidly at the same time). In
6014 * this case, the Master PF returned by the firmware will be
6015 * PCIE_FW_MASTER_M so the test below will work ...
6017 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6018 master_mbox != mbox) {
6019 int waiting = FW_CMD_HELLO_TIMEOUT;
6022 * Wait for the firmware to either indicate an error or
6023 * initialized state. If we see either of these we bail out
6024 * and report the issue to the caller. If we exhaust the
6025 * "hello timeout" and we haven't exhausted our retries, try
6026 * again. Otherwise bail with a timeout error.
6035 * If neither Error nor Initialialized are indicated
6036 * by the firmware keep waiting till we exaust our
6037 * timeout ... and then retry if we haven't exhausted
6040 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6041 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6052 * We either have an Error or Initialized condition
6053 * report errors preferentially.
6056 if (pcie_fw & PCIE_FW_ERR_F)
6057 *state = DEV_STATE_ERR;
6058 else if (pcie_fw & PCIE_FW_INIT_F)
6059 *state = DEV_STATE_INIT;
6063 * If we arrived before a Master PF was selected and
6064 * there's not a valid Master PF, grab its identity
6067 if (master_mbox == PCIE_FW_MASTER_M &&
6068 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6069 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6078 * t4_fw_bye - end communication with FW
6079 * @adap: the adapter
6080 * @mbox: mailbox to use for the FW command
6082 * Issues a command to terminate communication with FW.
6084 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6086 struct fw_bye_cmd c;
6088 memset(&c, 0, sizeof(c));
6089 INIT_CMD(c, BYE, WRITE);
6090 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6094 * t4_init_cmd - ask FW to initialize the device
6095 * @adap: the adapter
6096 * @mbox: mailbox to use for the FW command
6098 * Issues a command to FW to partially initialize the device. This
6099 * performs initialization that generally doesn't depend on user input.
6101 int t4_early_init(struct adapter *adap, unsigned int mbox)
6103 struct fw_initialize_cmd c;
6105 memset(&c, 0, sizeof(c));
6106 INIT_CMD(c, INITIALIZE, WRITE);
6107 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6111 * t4_fw_reset - issue a reset to FW
6112 * @adap: the adapter
6113 * @mbox: mailbox to use for the FW command
6114 * @reset: specifies the type of reset to perform
6116 * Issues a reset command of the specified type to FW.
6118 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6120 struct fw_reset_cmd c;
6122 memset(&c, 0, sizeof(c));
6123 INIT_CMD(c, RESET, WRITE);
6124 c.val = cpu_to_be32(reset);
6125 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6129 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6130 * @adap: the adapter
6131 * @mbox: mailbox to use for the FW RESET command (if desired)
6132 * @force: force uP into RESET even if FW RESET command fails
6134 * Issues a RESET command to firmware (if desired) with a HALT indication
6135 * and then puts the microprocessor into RESET state. The RESET command
6136 * will only be issued if a legitimate mailbox is provided (mbox <=
6137 * PCIE_FW_MASTER_M).
6139 * This is generally used in order for the host to safely manipulate the
6140 * adapter without fear of conflicting with whatever the firmware might
6141 * be doing. The only way out of this state is to RESTART the firmware
6144 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6149 * If a legitimate mailbox is provided, issue a RESET command
6150 * with a HALT indication.
6152 if (mbox <= PCIE_FW_MASTER_M) {
6153 struct fw_reset_cmd c;
6155 memset(&c, 0, sizeof(c));
6156 INIT_CMD(c, RESET, WRITE);
6157 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6158 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6159 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6163 * Normally we won't complete the operation if the firmware RESET
6164 * command fails but if our caller insists we'll go ahead and put the
6165 * uP into RESET. This can be useful if the firmware is hung or even
6166 * missing ... We'll have to take the risk of putting the uP into
6167 * RESET without the cooperation of firmware in that case.
6169 * We also force the firmware's HALT flag to be on in case we bypassed
6170 * the firmware RESET command above or we're dealing with old firmware
6171 * which doesn't have the HALT capability. This will serve as a flag
6172 * for the incoming firmware to know that it's coming out of a HALT
6173 * rather than a RESET ... if it's new enough to understand that ...
6175 if (ret == 0 || force) {
6176 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6177 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6182 * And we always return the result of the firmware RESET command
6183 * even when we force the uP into RESET ...
6189 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6190 * @adap: the adapter
6191 * @reset: if we want to do a RESET to restart things
6193 * Restart firmware previously halted by t4_fw_halt(). On successful
6194 * return the previous PF Master remains as the new PF Master and there
6195 * is no need to issue a new HELLO command, etc.
6197 * We do this in two ways:
6199 * 1. If we're dealing with newer firmware we'll simply want to take
6200 * the chip's microprocessor out of RESET. This will cause the
6201 * firmware to start up from its start vector. And then we'll loop
6202 * until the firmware indicates it's started again (PCIE_FW.HALT
6203 * reset to 0) or we timeout.
6205 * 2. If we're dealing with older firmware then we'll need to RESET
6206 * the chip since older firmware won't recognize the PCIE_FW.HALT
6207 * flag and automatically RESET itself on startup.
6209 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6213 * Since we're directing the RESET instead of the firmware
6214 * doing it automatically, we need to clear the PCIE_FW.HALT
6217 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6220 * If we've been given a valid mailbox, first try to get the
6221 * firmware to do the RESET. If that works, great and we can
6222 * return success. Otherwise, if we haven't been given a
6223 * valid mailbox or the RESET command failed, fall back to
6224 * hitting the chip with a hammer.
6226 if (mbox <= PCIE_FW_MASTER_M) {
6227 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6229 if (t4_fw_reset(adap, mbox,
6230 PIORST_F | PIORSTMODE_F) == 0)
6234 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6239 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6240 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6241 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6252 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6253 * @adap: the adapter
6254 * @mbox: mailbox to use for the FW RESET command (if desired)
6255 * @fw_data: the firmware image to write
6257 * @force: force upgrade even if firmware doesn't cooperate
6259 * Perform all of the steps necessary for upgrading an adapter's
6260 * firmware image. Normally this requires the cooperation of the
6261 * existing firmware in order to halt all existing activities
6262 * but if an invalid mailbox token is passed in we skip that step
6263 * (though we'll still put the adapter microprocessor into RESET in
6266 * On successful return the new firmware will have been loaded and
6267 * the adapter will have been fully RESET losing all previous setup
6268 * state. On unsuccessful return the adapter may be completely hosed ...
6269 * positive errno indicates that the adapter is ~probably~ intact, a
6270 * negative errno indicates that things are looking bad ...
6272 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6273 const u8 *fw_data, unsigned int size, int force)
6275 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6278 if (!t4_fw_matches_chip(adap, fw_hdr))
6281 ret = t4_fw_halt(adap, mbox, force);
6282 if (ret < 0 && !force)
6285 ret = t4_load_fw(adap, fw_data, size);
6290 * Older versions of the firmware don't understand the new
6291 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6292 * restart. So for newly loaded older firmware we'll have to do the
6293 * RESET for it so it starts up on a clean slate. We can tell if
6294 * the newly loaded firmware will handle this right by checking
6295 * its header flags to see if it advertises the capability.
6297 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6298 return t4_fw_restart(adap, mbox, reset);
6302 * t4_fl_pkt_align - return the fl packet alignment
6303 * @adap: the adapter
6305 * T4 has a single field to specify the packing and padding boundary.
6306 * T5 onwards has separate fields for this and hence the alignment for
6307 * next packet offset is maximum of these two.
6310 int t4_fl_pkt_align(struct adapter *adap)
6312 u32 sge_control, sge_control2;
6313 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6315 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6317 /* T4 uses a single control field to specify both the PCIe Padding and
6318 * Packing Boundary. T5 introduced the ability to specify these
6319 * separately. The actual Ingress Packet Data alignment boundary
6320 * within Packed Buffer Mode is the maximum of these two
6321 * specifications. (Note that it makes no real practical sense to
6322 * have the Pading Boudary be larger than the Packing Boundary but you
6323 * could set the chip up that way and, in fact, legacy T4 code would
6324 * end doing this because it would initialize the Padding Boundary and
6325 * leave the Packing Boundary initialized to 0 (16 bytes).)
6326 * Padding Boundary values in T6 starts from 8B,
6327 * where as it is 32B for T4 and T5.
6329 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6330 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6332 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6334 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6336 fl_align = ingpadboundary;
6337 if (!is_t4(adap->params.chip)) {
6338 /* T5 has a weird interpretation of one of the PCIe Packing
6339 * Boundary values. No idea why ...
6341 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6342 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6343 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6344 ingpackboundary = 16;
6346 ingpackboundary = 1 << (ingpackboundary +
6347 INGPACKBOUNDARY_SHIFT_X);
6349 fl_align = max(ingpadboundary, ingpackboundary);
6355 * t4_fixup_host_params - fix up host-dependent parameters
6356 * @adap: the adapter
6357 * @page_size: the host's Base Page Size
6358 * @cache_line_size: the host's Cache Line Size
6360 * Various registers in T4 contain values which are dependent on the
6361 * host's Base Page and Cache Line Sizes. This function will fix all of
6362 * those registers with the appropriate values as passed in ...
6364 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6365 unsigned int cache_line_size)
6367 unsigned int page_shift = fls(page_size) - 1;
6368 unsigned int sge_hps = page_shift - 10;
6369 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6370 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6371 unsigned int fl_align_log = fls(fl_align) - 1;
6373 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6374 HOSTPAGESIZEPF0_V(sge_hps) |
6375 HOSTPAGESIZEPF1_V(sge_hps) |
6376 HOSTPAGESIZEPF2_V(sge_hps) |
6377 HOSTPAGESIZEPF3_V(sge_hps) |
6378 HOSTPAGESIZEPF4_V(sge_hps) |
6379 HOSTPAGESIZEPF5_V(sge_hps) |
6380 HOSTPAGESIZEPF6_V(sge_hps) |
6381 HOSTPAGESIZEPF7_V(sge_hps));
6383 if (is_t4(adap->params.chip)) {
6384 t4_set_reg_field(adap, SGE_CONTROL_A,
6385 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6386 EGRSTATUSPAGESIZE_F,
6387 INGPADBOUNDARY_V(fl_align_log -
6388 INGPADBOUNDARY_SHIFT_X) |
6389 EGRSTATUSPAGESIZE_V(stat_len != 64));
6391 unsigned int pack_align;
6392 unsigned int ingpad, ingpack;
6393 unsigned int pcie_cap;
6395 /* T5 introduced the separation of the Free List Padding and
6396 * Packing Boundaries. Thus, we can select a smaller Padding
6397 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6398 * Bandwidth, and use a Packing Boundary which is large enough
6399 * to avoid false sharing between CPUs, etc.
6401 * For the PCI Link, the smaller the Padding Boundary the
6402 * better. For the Memory Controller, a smaller Padding
6403 * Boundary is better until we cross under the Memory Line
6404 * Size (the minimum unit of transfer to/from Memory). If we
6405 * have a Padding Boundary which is smaller than the Memory
6406 * Line Size, that'll involve a Read-Modify-Write cycle on the
6407 * Memory Controller which is never good.
6410 /* We want the Packing Boundary to be based on the Cache Line
6411 * Size in order to help avoid False Sharing performance
6412 * issues between CPUs, etc. We also want the Packing
6413 * Boundary to incorporate the PCI-E Maximum Payload Size. We
6414 * get best performance when the Packing Boundary is a
6415 * multiple of the Maximum Payload Size.
6417 pack_align = fl_align;
6418 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6420 unsigned int mps, mps_log;
6423 /* The PCIe Device Control Maximum Payload Size field
6424 * [bits 7:5] encodes sizes as powers of 2 starting at
6427 pci_read_config_word(adap->pdev,
6428 pcie_cap + PCI_EXP_DEVCTL,
6430 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6432 if (mps > pack_align)
6436 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6437 * value for the Packing Boundary. This corresponds to 16
6438 * bytes instead of the expected 32 bytes. So if we want 32
6439 * bytes, the best we can really do is 64 bytes ...
6441 if (pack_align <= 16) {
6442 ingpack = INGPACKBOUNDARY_16B_X;
6444 } else if (pack_align == 32) {
6445 ingpack = INGPACKBOUNDARY_64B_X;
6448 unsigned int pack_align_log = fls(pack_align) - 1;
6450 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6451 fl_align = pack_align;
6454 /* Use the smallest Ingress Padding which isn't smaller than
6455 * the Memory Controller Read/Write Size. We'll take that as
6456 * being 8 bytes since we don't know of any system with a
6457 * wider Memory Controller Bus Width.
6459 if (is_t5(adap->params.chip))
6460 ingpad = INGPADBOUNDARY_32B_X;
6462 ingpad = T6_INGPADBOUNDARY_8B_X;
6464 t4_set_reg_field(adap, SGE_CONTROL_A,
6465 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6466 EGRSTATUSPAGESIZE_F,
6467 INGPADBOUNDARY_V(ingpad) |
6468 EGRSTATUSPAGESIZE_V(stat_len != 64));
6469 t4_set_reg_field(adap, SGE_CONTROL2_A,
6470 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6471 INGPACKBOUNDARY_V(ingpack));
6474 * Adjust various SGE Free List Host Buffer Sizes.
6476 * This is something of a crock since we're using fixed indices into
6477 * the array which are also known by the sge.c code and the T4
6478 * Firmware Configuration File. We need to come up with a much better
6479 * approach to managing this array. For now, the first four entries
6484 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6485 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6487 * For the single-MTU buffers in unpacked mode we need to include
6488 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6489 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6490 * Padding boundary. All of these are accommodated in the Factory
6491 * Default Firmware Configuration File but we need to adjust it for
6492 * this host's cache line size.
6494 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6495 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6496 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6498 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6499 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6502 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6508 * t4_fw_initialize - ask FW to initialize the device
6509 * @adap: the adapter
6510 * @mbox: mailbox to use for the FW command
6512 * Issues a command to FW to partially initialize the device. This
6513 * performs initialization that generally doesn't depend on user input.
6515 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6517 struct fw_initialize_cmd c;
6519 memset(&c, 0, sizeof(c));
6520 INIT_CMD(c, INITIALIZE, WRITE);
6521 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6525 * t4_query_params_rw - query FW or device parameters
6526 * @adap: the adapter
6527 * @mbox: mailbox to use for the FW command
6530 * @nparams: the number of parameters
6531 * @params: the parameter names
6532 * @val: the parameter values
6533 * @rw: Write and read flag
6535 * Reads the value of FW or device parameters. Up to 7 parameters can be
6538 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6539 unsigned int vf, unsigned int nparams, const u32 *params,
6543 struct fw_params_cmd c;
6544 __be32 *p = &c.param[0].mnem;
6549 memset(&c, 0, sizeof(c));
6550 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6551 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6552 FW_PARAMS_CMD_PFN_V(pf) |
6553 FW_PARAMS_CMD_VFN_V(vf));
6554 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6556 for (i = 0; i < nparams; i++) {
6557 *p++ = cpu_to_be32(*params++);
6559 *p = cpu_to_be32(*(val + i));
6563 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6565 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6566 *val++ = be32_to_cpu(*p);
6570 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6571 unsigned int vf, unsigned int nparams, const u32 *params,
6574 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6578 * t4_set_params_timeout - sets FW or device parameters
6579 * @adap: the adapter
6580 * @mbox: mailbox to use for the FW command
6583 * @nparams: the number of parameters
6584 * @params: the parameter names
6585 * @val: the parameter values
6586 * @timeout: the timeout time
6588 * Sets the value of FW or device parameters. Up to 7 parameters can be
6589 * specified at once.
6591 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6592 unsigned int pf, unsigned int vf,
6593 unsigned int nparams, const u32 *params,
6594 const u32 *val, int timeout)
6596 struct fw_params_cmd c;
6597 __be32 *p = &c.param[0].mnem;
6602 memset(&c, 0, sizeof(c));
6603 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6604 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6605 FW_PARAMS_CMD_PFN_V(pf) |
6606 FW_PARAMS_CMD_VFN_V(vf));
6607 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6610 *p++ = cpu_to_be32(*params++);
6611 *p++ = cpu_to_be32(*val++);
6614 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6618 * t4_set_params - sets FW or device parameters
6619 * @adap: the adapter
6620 * @mbox: mailbox to use for the FW command
6623 * @nparams: the number of parameters
6624 * @params: the parameter names
6625 * @val: the parameter values
6627 * Sets the value of FW or device parameters. Up to 7 parameters can be
6628 * specified at once.
6630 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6631 unsigned int vf, unsigned int nparams, const u32 *params,
6634 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6635 FW_CMD_MAX_TIMEOUT);
6639 * t4_cfg_pfvf - configure PF/VF resource limits
6640 * @adap: the adapter
6641 * @mbox: mailbox to use for the FW command
6642 * @pf: the PF being configured
6643 * @vf: the VF being configured
6644 * @txq: the max number of egress queues
6645 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6646 * @rxqi: the max number of interrupt-capable ingress queues
6647 * @rxq: the max number of interruptless ingress queues
6648 * @tc: the PCI traffic class
6649 * @vi: the max number of virtual interfaces
6650 * @cmask: the channel access rights mask for the PF/VF
6651 * @pmask: the port access rights mask for the PF/VF
6652 * @nexact: the maximum number of exact MPS filters
6653 * @rcaps: read capabilities
6654 * @wxcaps: write/execute capabilities
6656 * Configures resource limits and capabilities for a physical or virtual
6659 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6660 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6661 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6662 unsigned int vi, unsigned int cmask, unsigned int pmask,
6663 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6665 struct fw_pfvf_cmd c;
6667 memset(&c, 0, sizeof(c));
6668 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6669 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6670 FW_PFVF_CMD_VFN_V(vf));
6671 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6672 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6673 FW_PFVF_CMD_NIQ_V(rxq));
6674 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6675 FW_PFVF_CMD_PMASK_V(pmask) |
6676 FW_PFVF_CMD_NEQ_V(txq));
6677 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6678 FW_PFVF_CMD_NVI_V(vi) |
6679 FW_PFVF_CMD_NEXACTF_V(nexact));
6680 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6681 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6682 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6683 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6687 * t4_alloc_vi - allocate a virtual interface
6688 * @adap: the adapter
6689 * @mbox: mailbox to use for the FW command
6690 * @port: physical port associated with the VI
6691 * @pf: the PF owning the VI
6692 * @vf: the VF owning the VI
6693 * @nmac: number of MAC addresses needed (1 to 5)
6694 * @mac: the MAC addresses of the VI
6695 * @rss_size: size of RSS table slice associated with this VI
6697 * Allocates a virtual interface for the given physical port. If @mac is
6698 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6699 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6700 * stored consecutively so the space needed is @nmac * 6 bytes.
6701 * Returns a negative error number or the non-negative VI id.
6703 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6704 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6705 unsigned int *rss_size)
6710 memset(&c, 0, sizeof(c));
6711 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6712 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6713 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6714 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6715 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6718 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6723 memcpy(mac, c.mac, sizeof(c.mac));
6726 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6728 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6730 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6732 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6736 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6737 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6741 * t4_free_vi - free a virtual interface
6742 * @adap: the adapter
6743 * @mbox: mailbox to use for the FW command
6744 * @pf: the PF owning the VI
6745 * @vf: the VF owning the VI
6746 * @viid: virtual interface identifiler
6748 * Free a previously allocated virtual interface.
6750 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6751 unsigned int vf, unsigned int viid)
6755 memset(&c, 0, sizeof(c));
6756 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6759 FW_VI_CMD_PFN_V(pf) |
6760 FW_VI_CMD_VFN_V(vf));
6761 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6762 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6764 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6768 * t4_set_rxmode - set Rx properties of a virtual interface
6769 * @adap: the adapter
6770 * @mbox: mailbox to use for the FW command
6772 * @mtu: the new MTU or -1
6773 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6774 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6775 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6776 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6777 * @sleep_ok: if true we may sleep while awaiting command completion
6779 * Sets Rx properties of a virtual interface.
6781 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6782 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6785 struct fw_vi_rxmode_cmd c;
6787 /* convert to FW values */
6789 mtu = FW_RXMODE_MTU_NO_CHG;
6791 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6793 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6795 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6797 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6799 memset(&c, 0, sizeof(c));
6800 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6801 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6802 FW_VI_RXMODE_CMD_VIID_V(viid));
6803 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6805 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6806 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6807 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6808 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6809 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6810 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6814 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6815 * @adap: the adapter
6816 * @mbox: mailbox to use for the FW command
6818 * @free: if true any existing filters for this VI id are first removed
6819 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6820 * @addr: the MAC address(es)
6821 * @idx: where to store the index of each allocated filter
6822 * @hash: pointer to hash address filter bitmap
6823 * @sleep_ok: call is allowed to sleep
6825 * Allocates an exact-match filter for each of the supplied addresses and
6826 * sets it to the corresponding address. If @idx is not %NULL it should
6827 * have at least @naddr entries, each of which will be set to the index of
6828 * the filter allocated for the corresponding MAC address. If a filter
6829 * could not be allocated for an address its index is set to 0xffff.
6830 * If @hash is not %NULL addresses that fail to allocate an exact filter
6831 * are hashed and update the hash filter bitmap pointed at by @hash.
6833 * Returns a negative error number or the number of filters allocated.
6835 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6836 unsigned int viid, bool free, unsigned int naddr,
6837 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6839 int offset, ret = 0;
6840 struct fw_vi_mac_cmd c;
6841 unsigned int nfilters = 0;
6842 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6843 unsigned int rem = naddr;
6845 if (naddr > max_naddr)
6848 for (offset = 0; offset < naddr ; /**/) {
6849 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6850 rem : ARRAY_SIZE(c.u.exact));
6851 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6852 u.exact[fw_naddr]), 16);
6853 struct fw_vi_mac_exact *p;
6856 memset(&c, 0, sizeof(c));
6857 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6860 FW_CMD_EXEC_V(free) |
6861 FW_VI_MAC_CMD_VIID_V(viid));
6862 c.freemacs_to_len16 =
6863 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6864 FW_CMD_LEN16_V(len16));
6866 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6868 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6869 FW_VI_MAC_CMD_IDX_V(
6870 FW_VI_MAC_ADD_MAC));
6871 memcpy(p->macaddr, addr[offset + i],
6872 sizeof(p->macaddr));
6875 /* It's okay if we run out of space in our MAC address arena.
6876 * Some of the addresses we submit may get stored so we need
6877 * to run through the reply to see what the results were ...
6879 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6880 if (ret && ret != -FW_ENOMEM)
6883 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6884 u16 index = FW_VI_MAC_CMD_IDX_G(
6885 be16_to_cpu(p->valid_to_idx));
6888 idx[offset + i] = (index >= max_naddr ?
6890 if (index < max_naddr)
6894 hash_mac_addr(addr[offset + i]));
6902 if (ret == 0 || ret == -FW_ENOMEM)
6908 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6909 * @adap: the adapter
6910 * @mbox: mailbox to use for the FW command
6912 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6913 * @addr: the MAC address(es)
6914 * @sleep_ok: call is allowed to sleep
6916 * Frees the exact-match filter for each of the supplied addresses
6918 * Returns a negative error number or the number of filters freed.
6920 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6921 unsigned int viid, unsigned int naddr,
6922 const u8 **addr, bool sleep_ok)
6924 int offset, ret = 0;
6925 struct fw_vi_mac_cmd c;
6926 unsigned int nfilters = 0;
6927 unsigned int max_naddr = is_t4(adap->params.chip) ?
6928 NUM_MPS_CLS_SRAM_L_INSTANCES :
6929 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6930 unsigned int rem = naddr;
6932 if (naddr > max_naddr)
6935 for (offset = 0; offset < (int)naddr ; /**/) {
6936 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6938 : ARRAY_SIZE(c.u.exact));
6939 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6940 u.exact[fw_naddr]), 16);
6941 struct fw_vi_mac_exact *p;
6944 memset(&c, 0, sizeof(c));
6945 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6949 FW_VI_MAC_CMD_VIID_V(viid));
6950 c.freemacs_to_len16 =
6951 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6952 FW_CMD_LEN16_V(len16));
6954 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6955 p->valid_to_idx = cpu_to_be16(
6956 FW_VI_MAC_CMD_VALID_F |
6957 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6958 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6961 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6965 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6966 u16 index = FW_VI_MAC_CMD_IDX_G(
6967 be16_to_cpu(p->valid_to_idx));
6969 if (index < max_naddr)
6983 * t4_change_mac - modifies the exact-match filter for a MAC address
6984 * @adap: the adapter
6985 * @mbox: mailbox to use for the FW command
6987 * @idx: index of existing filter for old value of MAC address, or -1
6988 * @addr: the new MAC address value
6989 * @persist: whether a new MAC allocation should be persistent
6990 * @add_smt: if true also add the address to the HW SMT
6992 * Modifies an exact-match filter and sets it to the new MAC address.
6993 * Note that in general it is not possible to modify the value of a given
6994 * filter so the generic way to modify an address filter is to free the one
6995 * being used by the old address value and allocate a new filter for the
6996 * new address value. @idx can be -1 if the address is a new addition.
6998 * Returns a negative error number or the index of the filter with the new
7001 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7002 int idx, const u8 *addr, bool persist, bool add_smt)
7005 struct fw_vi_mac_cmd c;
7006 struct fw_vi_mac_exact *p = c.u.exact;
7007 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7009 if (idx < 0) /* new allocation */
7010 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7011 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7013 memset(&c, 0, sizeof(c));
7014 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7015 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7016 FW_VI_MAC_CMD_VIID_V(viid));
7017 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7018 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7019 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7020 FW_VI_MAC_CMD_IDX_V(idx));
7021 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7023 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7025 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7026 if (ret >= max_mac_addr)
7033 * t4_set_addr_hash - program the MAC inexact-match hash filter
7034 * @adap: the adapter
7035 * @mbox: mailbox to use for the FW command
7037 * @ucast: whether the hash filter should also match unicast addresses
7038 * @vec: the value to be written to the hash filter
7039 * @sleep_ok: call is allowed to sleep
7041 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7043 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7044 bool ucast, u64 vec, bool sleep_ok)
7046 struct fw_vi_mac_cmd c;
7048 memset(&c, 0, sizeof(c));
7049 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7050 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7051 FW_VI_ENABLE_CMD_VIID_V(viid));
7052 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7053 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7055 c.u.hash.hashvec = cpu_to_be64(vec);
7056 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7060 * t4_enable_vi_params - enable/disable a virtual interface
7061 * @adap: the adapter
7062 * @mbox: mailbox to use for the FW command
7064 * @rx_en: 1=enable Rx, 0=disable Rx
7065 * @tx_en: 1=enable Tx, 0=disable Tx
7066 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7068 * Enables/disables a virtual interface. Note that setting DCB Enable
7069 * only makes sense when enabling a Virtual Interface ...
7071 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7072 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7074 struct fw_vi_enable_cmd c;
7076 memset(&c, 0, sizeof(c));
7077 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7078 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7079 FW_VI_ENABLE_CMD_VIID_V(viid));
7080 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7081 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7082 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7084 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7088 * t4_enable_vi - enable/disable a virtual interface
7089 * @adap: the adapter
7090 * @mbox: mailbox to use for the FW command
7092 * @rx_en: 1=enable Rx, 0=disable Rx
7093 * @tx_en: 1=enable Tx, 0=disable Tx
7095 * Enables/disables a virtual interface.
7097 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7098 bool rx_en, bool tx_en)
7100 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7104 * t4_identify_port - identify a VI's port by blinking its LED
7105 * @adap: the adapter
7106 * @mbox: mailbox to use for the FW command
7108 * @nblinks: how many times to blink LED at 2.5 Hz
7110 * Identifies a VI's port by blinking its LED.
7112 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7113 unsigned int nblinks)
7115 struct fw_vi_enable_cmd c;
7117 memset(&c, 0, sizeof(c));
7118 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7119 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7120 FW_VI_ENABLE_CMD_VIID_V(viid));
7121 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7122 c.blinkdur = cpu_to_be16(nblinks);
7123 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7127 * t4_iq_stop - stop an ingress queue and its FLs
7128 * @adap: the adapter
7129 * @mbox: mailbox to use for the FW command
7130 * @pf: the PF owning the queues
7131 * @vf: the VF owning the queues
7132 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7133 * @iqid: ingress queue id
7134 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7135 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7137 * Stops an ingress queue and its associated FLs, if any. This causes
7138 * any current or future data/messages destined for these queues to be
7141 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7142 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7143 unsigned int fl0id, unsigned int fl1id)
7147 memset(&c, 0, sizeof(c));
7148 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7149 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7150 FW_IQ_CMD_VFN_V(vf));
7151 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7152 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7153 c.iqid = cpu_to_be16(iqid);
7154 c.fl0id = cpu_to_be16(fl0id);
7155 c.fl1id = cpu_to_be16(fl1id);
7156 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7160 * t4_iq_free - free an ingress queue and its FLs
7161 * @adap: the adapter
7162 * @mbox: mailbox to use for the FW command
7163 * @pf: the PF owning the queues
7164 * @vf: the VF owning the queues
7165 * @iqtype: the ingress queue type
7166 * @iqid: ingress queue id
7167 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7168 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7170 * Frees an ingress queue and its associated FLs, if any.
7172 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7173 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7174 unsigned int fl0id, unsigned int fl1id)
7178 memset(&c, 0, sizeof(c));
7179 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7180 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7181 FW_IQ_CMD_VFN_V(vf));
7182 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7183 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7184 c.iqid = cpu_to_be16(iqid);
7185 c.fl0id = cpu_to_be16(fl0id);
7186 c.fl1id = cpu_to_be16(fl1id);
7187 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7191 * t4_eth_eq_free - free an Ethernet egress queue
7192 * @adap: the adapter
7193 * @mbox: mailbox to use for the FW command
7194 * @pf: the PF owning the queue
7195 * @vf: the VF owning the queue
7196 * @eqid: egress queue id
7198 * Frees an Ethernet egress queue.
7200 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7201 unsigned int vf, unsigned int eqid)
7203 struct fw_eq_eth_cmd c;
7205 memset(&c, 0, sizeof(c));
7206 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7207 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7208 FW_EQ_ETH_CMD_PFN_V(pf) |
7209 FW_EQ_ETH_CMD_VFN_V(vf));
7210 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7211 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7212 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7216 * t4_ctrl_eq_free - free a control egress queue
7217 * @adap: the adapter
7218 * @mbox: mailbox to use for the FW command
7219 * @pf: the PF owning the queue
7220 * @vf: the VF owning the queue
7221 * @eqid: egress queue id
7223 * Frees a control egress queue.
7225 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7226 unsigned int vf, unsigned int eqid)
7228 struct fw_eq_ctrl_cmd c;
7230 memset(&c, 0, sizeof(c));
7231 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7232 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7233 FW_EQ_CTRL_CMD_PFN_V(pf) |
7234 FW_EQ_CTRL_CMD_VFN_V(vf));
7235 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7236 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7237 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7241 * t4_ofld_eq_free - free an offload egress queue
7242 * @adap: the adapter
7243 * @mbox: mailbox to use for the FW command
7244 * @pf: the PF owning the queue
7245 * @vf: the VF owning the queue
7246 * @eqid: egress queue id
7248 * Frees a control egress queue.
7250 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7251 unsigned int vf, unsigned int eqid)
7253 struct fw_eq_ofld_cmd c;
7255 memset(&c, 0, sizeof(c));
7256 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7257 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7258 FW_EQ_OFLD_CMD_PFN_V(pf) |
7259 FW_EQ_OFLD_CMD_VFN_V(vf));
7260 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7261 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7262 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7266 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7267 * @adap: the adapter
7268 * @link_down_rc: Link Down Reason Code
7270 * Returns a string representation of the Link Down Reason Code.
7272 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7274 static const char * const reason[] = {
7277 "Auto-negotiation Failure",
7279 "Insufficient Airflow",
7280 "Unable To Determine Reason",
7281 "No RX Signal Detected",
7285 if (link_down_rc >= ARRAY_SIZE(reason))
7286 return "Bad Reason Code";
7288 return reason[link_down_rc];
7292 * t4_handle_get_port_info - process a FW reply message
7293 * @pi: the port info
7294 * @rpl: start of the FW message
7296 * Processes a GET_PORT_INFO FW reply message.
7298 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7300 const struct fw_port_cmd *p = (const void *)rpl;
7301 struct adapter *adap = pi->adapter;
7303 /* link/module state change message */
7304 int speed = 0, fc = 0;
7305 struct link_config *lc;
7306 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7307 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7308 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7310 if (stat & FW_PORT_CMD_RXPAUSE_F)
7312 if (stat & FW_PORT_CMD_TXPAUSE_F)
7314 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7316 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7318 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7320 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7322 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7324 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7329 if (mod != pi->mod_type) {
7331 t4_os_portmod_changed(adap, pi->port_id);
7333 if (link_ok != lc->link_ok || speed != lc->speed ||
7334 fc != lc->fc) { /* something changed */
7335 if (!link_ok && lc->link_ok) {
7336 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7338 lc->link_down_rc = rc;
7339 dev_warn(adap->pdev_dev,
7340 "Port %d link down, reason: %s\n",
7341 pi->port_id, t4_link_down_rc_str(rc));
7343 lc->link_ok = link_ok;
7346 lc->supported = be16_to_cpu(p->u.info.pcap);
7347 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7348 t4_os_link_changed(adap, pi->port_id, link_ok);
7353 * t4_handle_fw_rpl - process a FW reply message
7354 * @adap: the adapter
7355 * @rpl: start of the FW message
7357 * Processes a FW message, such as link state change messages.
7359 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7361 u8 opcode = *(const u8 *)rpl;
7363 /* This might be a port command ... this simplifies the following
7364 * conditionals ... We can get away with pre-dereferencing
7365 * action_to_len16 because it's in the first 16 bytes and all messages
7366 * will be at least that long.
7368 const struct fw_port_cmd *p = (const void *)rpl;
7369 unsigned int action =
7370 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7372 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7374 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7375 struct port_info *pi = NULL;
7377 for_each_port(adap, i) {
7378 pi = adap2pinfo(adap, i);
7379 if (pi->tx_chan == chan)
7383 t4_handle_get_port_info(pi, rpl);
7385 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7391 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7395 if (pci_is_pcie(adapter->pdev)) {
7396 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7397 p->speed = val & PCI_EXP_LNKSTA_CLS;
7398 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7403 * init_link_config - initialize a link's SW state
7404 * @lc: structure holding the link state
7405 * @caps: link capabilities
7407 * Initializes the SW state maintained for each link, including the link's
7408 * capabilities and default speed/flow-control/autonegotiation settings.
7410 static void init_link_config(struct link_config *lc, unsigned int caps)
7412 lc->supported = caps;
7413 lc->lp_advertising = 0;
7414 lc->requested_speed = 0;
7416 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7417 if (lc->supported & FW_PORT_CAP_ANEG) {
7418 lc->advertising = lc->supported & ADVERT_MASK;
7419 lc->autoneg = AUTONEG_ENABLE;
7420 lc->requested_fc |= PAUSE_AUTONEG;
7422 lc->advertising = 0;
7423 lc->autoneg = AUTONEG_DISABLE;
7427 #define CIM_PF_NOACCESS 0xeeeeeeee
7429 int t4_wait_dev_ready(void __iomem *regs)
7433 whoami = readl(regs + PL_WHOAMI_A);
7434 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7438 whoami = readl(regs + PL_WHOAMI_A);
7439 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7443 u32 vendor_and_model_id;
7447 static int get_flash_params(struct adapter *adap)
7449 /* Table for non-Numonix supported flash parts. Numonix parts are left
7450 * to the preexisting code. All flash parts have 64KB sectors.
7452 static struct flash_desc supported_flash[] = {
7453 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7459 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7461 ret = sf1_read(adap, 3, 0, 1, &info);
7462 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7466 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7467 if (supported_flash[ret].vendor_and_model_id == info) {
7468 adap->params.sf_size = supported_flash[ret].size_mb;
7469 adap->params.sf_nsec =
7470 adap->params.sf_size / SF_SEC_SIZE;
7474 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7476 info >>= 16; /* log2 of size */
7477 if (info >= 0x14 && info < 0x18)
7478 adap->params.sf_nsec = 1 << (info - 16);
7479 else if (info == 0x18)
7480 adap->params.sf_nsec = 64;
7483 adap->params.sf_size = 1 << info;
7484 adap->params.sf_fw_start =
7485 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7487 if (adap->params.sf_size < FLASH_MIN_SIZE)
7488 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7489 adap->params.sf_size, FLASH_MIN_SIZE);
7493 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7498 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7500 pci_read_config_word(adapter->pdev,
7501 pcie_cap + PCI_EXP_DEVCTL2, &val);
7502 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7504 pci_write_config_word(adapter->pdev,
7505 pcie_cap + PCI_EXP_DEVCTL2, val);
7510 * t4_prep_adapter - prepare SW and HW for operation
7511 * @adapter: the adapter
7512 * @reset: if true perform a HW reset
7514 * Initialize adapter SW state for the various HW modules, set initial
7515 * values for some adapter tunables, take PHYs out of reset, and
7516 * initialize the MDIO interface.
7518 int t4_prep_adapter(struct adapter *adapter)
7524 get_pci_mode(adapter, &adapter->params.pci);
7525 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7527 ret = get_flash_params(adapter);
7529 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7533 /* Retrieve adapter's device ID
7535 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7536 ver = device_id >> 12;
7537 adapter->params.chip = 0;
7540 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7541 adapter->params.arch.sge_fl_db = DBPRIO_F;
7542 adapter->params.arch.mps_tcam_size =
7543 NUM_MPS_CLS_SRAM_L_INSTANCES;
7544 adapter->params.arch.mps_rplc_size = 128;
7545 adapter->params.arch.nchan = NCHAN;
7546 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7547 adapter->params.arch.vfcount = 128;
7548 /* Congestion map is for 4 channels so that
7549 * MPS can have 4 priority per port.
7551 adapter->params.arch.cng_ch_bits_log = 2;
7554 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7555 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7556 adapter->params.arch.mps_tcam_size =
7557 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7558 adapter->params.arch.mps_rplc_size = 128;
7559 adapter->params.arch.nchan = NCHAN;
7560 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7561 adapter->params.arch.vfcount = 128;
7562 adapter->params.arch.cng_ch_bits_log = 2;
7565 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7566 adapter->params.arch.sge_fl_db = 0;
7567 adapter->params.arch.mps_tcam_size =
7568 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7569 adapter->params.arch.mps_rplc_size = 256;
7570 adapter->params.arch.nchan = 2;
7571 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7572 adapter->params.arch.vfcount = 256;
7573 /* Congestion map will be for 2 channels so that
7574 * MPS can have 8 priority per port.
7576 adapter->params.arch.cng_ch_bits_log = 3;
7579 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7584 adapter->params.cim_la_size = CIMLA_SIZE;
7585 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7588 * Default port for debugging in case we can't reach FW.
7590 adapter->params.nports = 1;
7591 adapter->params.portvec = 1;
7592 adapter->params.vpd.cclk = 50000;
7594 /* Set pci completion timeout value to 4 seconds. */
7595 set_pcie_completion_timeout(adapter, 0xd);
7600 * t4_shutdown_adapter - shut down adapter, host & wire
7601 * @adapter: the adapter
7603 * Perform an emergency shutdown of the adapter and stop it from
7604 * continuing any further communication on the ports or DMA to the
7605 * host. This is typically used when the adapter and/or firmware
7606 * have crashed and we want to prevent any further accidental
7607 * communication with the rest of the world. This will also force
7608 * the port Link Status to go down -- if register writes work --
7609 * which should help our peers figure out that we're down.
7611 int t4_shutdown_adapter(struct adapter *adapter)
7615 t4_intr_disable(adapter);
7616 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
7617 for_each_port(adapter, port) {
7618 u32 a_port_cfg = PORT_REG(port,
7619 is_t4(adapter->params.chip)
7623 t4_write_reg(adapter, a_port_cfg,
7624 t4_read_reg(adapter, a_port_cfg)
7625 & ~SIGNAL_DET_V(1));
7627 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
7633 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7634 * @adapter: the adapter
7635 * @qid: the Queue ID
7636 * @qtype: the Ingress or Egress type for @qid
7637 * @user: true if this request is for a user mode queue
7638 * @pbar2_qoffset: BAR2 Queue Offset
7639 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7641 * Returns the BAR2 SGE Queue Registers information associated with the
7642 * indicated Absolute Queue ID. These are passed back in return value
7643 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7644 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7646 * This may return an error which indicates that BAR2 SGE Queue
7647 * registers aren't available. If an error is not returned, then the
7648 * following values are returned:
7650 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7651 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7653 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7654 * require the "Inferred Queue ID" ability may be used. E.g. the
7655 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7656 * then these "Inferred Queue ID" register may not be used.
7658 int t4_bar2_sge_qregs(struct adapter *adapter,
7660 enum t4_bar2_qtype qtype,
7663 unsigned int *pbar2_qid)
7665 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7666 u64 bar2_page_offset, bar2_qoffset;
7667 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7669 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7670 if (!user && is_t4(adapter->params.chip))
7673 /* Get our SGE Page Size parameters.
7675 page_shift = adapter->params.sge.hps + 10;
7676 page_size = 1 << page_shift;
7678 /* Get the right Queues per Page parameters for our Queue.
7680 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7681 ? adapter->params.sge.eq_qpp
7682 : adapter->params.sge.iq_qpp);
7683 qpp_mask = (1 << qpp_shift) - 1;
7685 /* Calculate the basics of the BAR2 SGE Queue register area:
7686 * o The BAR2 page the Queue registers will be in.
7687 * o The BAR2 Queue ID.
7688 * o The BAR2 Queue ID Offset into the BAR2 page.
7690 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7691 bar2_qid = qid & qpp_mask;
7692 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7694 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7695 * hardware will infer the Absolute Queue ID simply from the writes to
7696 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7697 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7698 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7699 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7700 * from the BAR2 Page and BAR2 Queue ID.
7702 * One important censequence of this is that some BAR2 SGE registers
7703 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7704 * there. But other registers synthesize the SGE Queue ID purely
7705 * from the writes to the registers -- the Write Combined Doorbell
7706 * Buffer is a good example. These BAR2 SGE Registers are only
7707 * available for those BAR2 SGE Register areas where the SGE Absolute
7708 * Queue ID can be inferred from simple writes.
7710 bar2_qoffset = bar2_page_offset;
7711 bar2_qinferred = (bar2_qid_offset < page_size);
7712 if (bar2_qinferred) {
7713 bar2_qoffset += bar2_qid_offset;
7717 *pbar2_qoffset = bar2_qoffset;
7718 *pbar2_qid = bar2_qid;
7723 * t4_init_devlog_params - initialize adapter->params.devlog
7724 * @adap: the adapter
7726 * Initialize various fields of the adapter's Firmware Device Log
7727 * Parameters structure.
7729 int t4_init_devlog_params(struct adapter *adap)
7731 struct devlog_params *dparams = &adap->params.devlog;
7733 unsigned int devlog_meminfo;
7734 struct fw_devlog_cmd devlog_cmd;
7737 /* If we're dealing with newer firmware, the Device Log Paramerters
7738 * are stored in a designated register which allows us to access the
7739 * Device Log even if we can't talk to the firmware.
7742 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7744 unsigned int nentries, nentries128;
7746 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7747 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7749 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7750 nentries = (nentries128 + 1) * 128;
7751 dparams->size = nentries * sizeof(struct fw_devlog_e);
7756 /* Otherwise, ask the firmware for it's Device Log Parameters.
7758 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7759 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7760 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7761 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7762 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7768 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7769 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7770 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7771 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7777 * t4_init_sge_params - initialize adap->params.sge
7778 * @adapter: the adapter
7780 * Initialize various fields of the adapter's SGE Parameters structure.
7782 int t4_init_sge_params(struct adapter *adapter)
7784 struct sge_params *sge_params = &adapter->params.sge;
7786 unsigned int s_hps, s_qpp;
7788 /* Extract the SGE Page Size for our PF.
7790 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7791 s_hps = (HOSTPAGESIZEPF0_S +
7792 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7793 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7795 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7797 s_qpp = (QUEUESPERPAGEPF0_S +
7798 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7799 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7800 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7801 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7802 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7808 * t4_init_tp_params - initialize adap->params.tp
7809 * @adap: the adapter
7811 * Initialize various fields of the adapter's TP Parameters structure.
7813 int t4_init_tp_params(struct adapter *adap)
7818 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7819 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7820 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7822 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7823 for (chan = 0; chan < NCHAN; chan++)
7824 adap->params.tp.tx_modq[chan] = chan;
7826 /* Cache the adapter's Compressed Filter Mode and global Incress
7829 if (t4_use_ldst(adap)) {
7830 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7831 TP_VLAN_PRI_MAP_A, 1);
7832 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7833 TP_INGRESS_CONFIG_A, 1);
7835 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7836 &adap->params.tp.vlan_pri_map, 1,
7838 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7839 &adap->params.tp.ingress_config, 1,
7840 TP_INGRESS_CONFIG_A);
7842 /* For T6, cache the adapter's compressed error vector
7843 * and passing outer header info for encapsulated packets.
7845 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
7846 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
7847 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
7850 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7851 * shift positions of several elements of the Compressed Filter Tuple
7852 * for this adapter which we need frequently ...
7854 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7855 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7856 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7857 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7860 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7861 * represents the presence of an Outer VLAN instead of a VNIC ID.
7863 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7864 adap->params.tp.vnic_shift = -1;
7870 * t4_filter_field_shift - calculate filter field shift
7871 * @adap: the adapter
7872 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7874 * Return the shift position of a filter field within the Compressed
7875 * Filter Tuple. The filter field is specified via its selection bit
7876 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7878 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7880 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7884 if ((filter_mode & filter_sel) == 0)
7887 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7888 switch (filter_mode & sel) {
7890 field_shift += FT_FCOE_W;
7893 field_shift += FT_PORT_W;
7896 field_shift += FT_VNIC_ID_W;
7899 field_shift += FT_VLAN_W;
7902 field_shift += FT_TOS_W;
7905 field_shift += FT_PROTOCOL_W;
7908 field_shift += FT_ETHERTYPE_W;
7911 field_shift += FT_MACMATCH_W;
7914 field_shift += FT_MPSHITTYPE_W;
7916 case FRAGMENTATION_F:
7917 field_shift += FT_FRAGMENTATION_W;
7924 int t4_init_rss_mode(struct adapter *adap, int mbox)
7927 struct fw_rss_vi_config_cmd rvc;
7929 memset(&rvc, 0, sizeof(rvc));
7931 for_each_port(adap, i) {
7932 struct port_info *p = adap2pinfo(adap, i);
7935 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7936 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7937 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7938 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7939 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7942 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7948 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7949 * @pi: the port_info
7950 * @mbox: mailbox to use for the FW command
7951 * @port: physical port associated with the VI
7952 * @pf: the PF owning the VI
7953 * @vf: the VF owning the VI
7954 * @mac: the MAC address of the VI
7956 * Allocates a virtual interface for the given physical port. If @mac is
7957 * not %NULL it contains the MAC address of the VI as assigned by FW.
7958 * @mac should be large enough to hold an Ethernet address.
7959 * Returns < 0 on error.
7961 int t4_init_portinfo(struct port_info *pi, int mbox,
7962 int port, int pf, int vf, u8 mac[])
7965 struct fw_port_cmd c;
7966 unsigned int rss_size;
7968 memset(&c, 0, sizeof(c));
7969 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7970 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7971 FW_PORT_CMD_PORTID_V(port));
7972 c.action_to_len16 = cpu_to_be32(
7973 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7975 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7979 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7986 pi->rss_size = rss_size;
7988 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7989 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7990 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7991 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7992 pi->mod_type = FW_PORT_MOD_TYPE_NA;
7994 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7998 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8003 for_each_port(adap, i) {
8004 struct port_info *pi = adap2pinfo(adap, i);
8006 while ((adap->params.portvec & (1 << j)) == 0)
8009 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8013 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8020 * t4_read_cimq_cfg - read CIM queue configuration
8021 * @adap: the adapter
8022 * @base: holds the queue base addresses in bytes
8023 * @size: holds the queue sizes in bytes
8024 * @thres: holds the queue full thresholds in bytes
8026 * Returns the current configuration of the CIM queues, starting with
8027 * the IBQs, then the OBQs.
8029 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8032 int cim_num_obq = is_t4(adap->params.chip) ?
8033 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8035 for (i = 0; i < CIM_NUM_IBQ; i++) {
8036 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8038 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8039 /* value is in 256-byte units */
8040 *base++ = CIMQBASE_G(v) * 256;
8041 *size++ = CIMQSIZE_G(v) * 256;
8042 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8044 for (i = 0; i < cim_num_obq; i++) {
8045 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8047 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8048 /* value is in 256-byte units */
8049 *base++ = CIMQBASE_G(v) * 256;
8050 *size++ = CIMQSIZE_G(v) * 256;
8055 * t4_read_cim_ibq - read the contents of a CIM inbound queue
8056 * @adap: the adapter
8057 * @qid: the queue index
8058 * @data: where to store the queue contents
8059 * @n: capacity of @data in 32-bit words
8061 * Reads the contents of the selected CIM queue starting at address 0 up
8062 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8063 * error and the number of 32-bit words actually read on success.
8065 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8067 int i, err, attempts;
8069 const unsigned int nwords = CIM_IBQ_SIZE * 4;
8071 if (qid > 5 || (n & 3))
8074 addr = qid * nwords;
8078 /* It might take 3-10ms before the IBQ debug read access is allowed.
8079 * Wait for 1 Sec with a delay of 1 usec.
8083 for (i = 0; i < n; i++, addr++) {
8084 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8086 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8090 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8092 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8097 * t4_read_cim_obq - read the contents of a CIM outbound queue
8098 * @adap: the adapter
8099 * @qid: the queue index
8100 * @data: where to store the queue contents
8101 * @n: capacity of @data in 32-bit words
8103 * Reads the contents of the selected CIM queue starting at address 0 up
8104 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8105 * error and the number of 32-bit words actually read on success.
8107 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8110 unsigned int addr, v, nwords;
8111 int cim_num_obq = is_t4(adap->params.chip) ?
8112 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8114 if ((qid > (cim_num_obq - 1)) || (n & 3))
8117 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8118 QUENUMSELECT_V(qid));
8119 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8121 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
8122 nwords = CIMQSIZE_G(v) * 64; /* same */
8126 for (i = 0; i < n; i++, addr++) {
8127 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8129 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8133 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8135 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8140 * t4_cim_read - read a block from CIM internal address space
8141 * @adap: the adapter
8142 * @addr: the start address within the CIM address space
8143 * @n: number of words to read
8144 * @valp: where to store the result
8146 * Reads a block of 4-byte words from the CIM intenal address space.
8148 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8153 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8156 for ( ; !ret && n--; addr += 4) {
8157 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8158 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8161 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8167 * t4_cim_write - write a block into CIM internal address space
8168 * @adap: the adapter
8169 * @addr: the start address within the CIM address space
8170 * @n: number of words to write
8171 * @valp: set of values to write
8173 * Writes a block of 4-byte words into the CIM intenal address space.
8175 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8176 const unsigned int *valp)
8180 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8183 for ( ; !ret && n--; addr += 4) {
8184 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8185 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8186 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8192 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8195 return t4_cim_write(adap, addr, 1, &val);
8199 * t4_cim_read_la - read CIM LA capture buffer
8200 * @adap: the adapter
8201 * @la_buf: where to store the LA data
8202 * @wrptr: the HW write pointer within the capture buffer
8204 * Reads the contents of the CIM LA buffer with the most recent entry at
8205 * the end of the returned data and with the entry at @wrptr first.
8206 * We try to leave the LA in the running state we find it in.
8208 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8211 unsigned int cfg, val, idx;
8213 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8217 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8218 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8223 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8227 idx = UPDBGLAWRPTR_G(val);
8231 for (i = 0; i < adap->params.cim_la_size; i++) {
8232 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8233 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8236 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8239 if (val & UPDBGLARDEN_F) {
8243 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8246 idx = (idx + 1) & UPDBGLARDPTR_M;
8249 if (cfg & UPDBGLAEN_F) {
8250 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8251 cfg & ~UPDBGLARDEN_F);
8259 * t4_tp_read_la - read TP LA capture buffer
8260 * @adap: the adapter
8261 * @la_buf: where to store the LA data
8262 * @wrptr: the HW write pointer within the capture buffer
8264 * Reads the contents of the TP LA buffer with the most recent entry at
8265 * the end of the returned data and with the entry at @wrptr first.
8266 * We leave the LA in the running state we find it in.
8268 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8270 bool last_incomplete;
8271 unsigned int i, cfg, val, idx;
8273 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8274 if (cfg & DBGLAENABLE_F) /* freeze LA */
8275 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8276 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8278 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8279 idx = DBGLAWPTR_G(val);
8280 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8281 if (last_incomplete)
8282 idx = (idx + 1) & DBGLARPTR_M;
8287 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8288 val |= adap->params.tp.la_mask;
8290 for (i = 0; i < TPLA_SIZE; i++) {
8291 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8292 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8293 idx = (idx + 1) & DBGLARPTR_M;
8296 /* Wipe out last entry if it isn't valid */
8297 if (last_incomplete)
8298 la_buf[TPLA_SIZE - 1] = ~0ULL;
8300 if (cfg & DBGLAENABLE_F) /* restore running state */
8301 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8302 cfg | adap->params.tp.la_mask);
8305 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8306 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8307 * state for more than the Warning Threshold then we'll issue a warning about
8308 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8309 * appears to be hung every Warning Repeat second till the situation clears.
8310 * If the situation clears, we'll note that as well.
8312 #define SGE_IDMA_WARN_THRESH 1
8313 #define SGE_IDMA_WARN_REPEAT 300
8316 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8317 * @adapter: the adapter
8318 * @idma: the adapter IDMA Monitor state
8320 * Initialize the state of an SGE Ingress DMA Monitor.
8322 void t4_idma_monitor_init(struct adapter *adapter,
8323 struct sge_idma_monitor_state *idma)
8325 /* Initialize the state variables for detecting an SGE Ingress DMA
8326 * hang. The SGE has internal counters which count up on each clock
8327 * tick whenever the SGE finds its Ingress DMA State Engines in the
8328 * same state they were on the previous clock tick. The clock used is
8329 * the Core Clock so we have a limit on the maximum "time" they can
8330 * record; typically a very small number of seconds. For instance,
8331 * with a 600MHz Core Clock, we can only count up to a bit more than
8332 * 7s. So we'll synthesize a larger counter in order to not run the
8333 * risk of having the "timers" overflow and give us the flexibility to
8334 * maintain a Hung SGE State Machine of our own which operates across
8335 * a longer time frame.
8337 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8338 idma->idma_stalled[0] = 0;
8339 idma->idma_stalled[1] = 0;
8343 * t4_idma_monitor - monitor SGE Ingress DMA state
8344 * @adapter: the adapter
8345 * @idma: the adapter IDMA Monitor state
8346 * @hz: number of ticks/second
8347 * @ticks: number of ticks since the last IDMA Monitor call
8349 void t4_idma_monitor(struct adapter *adapter,
8350 struct sge_idma_monitor_state *idma,
8353 int i, idma_same_state_cnt[2];
8355 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8356 * are counters inside the SGE which count up on each clock when the
8357 * SGE finds its Ingress DMA State Engines in the same states they
8358 * were in the previous clock. The counters will peg out at
8359 * 0xffffffff without wrapping around so once they pass the 1s
8360 * threshold they'll stay above that till the IDMA state changes.
8362 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8363 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8364 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8366 for (i = 0; i < 2; i++) {
8367 u32 debug0, debug11;
8369 /* If the Ingress DMA Same State Counter ("timer") is less
8370 * than 1s, then we can reset our synthesized Stall Timer and
8371 * continue. If we have previously emitted warnings about a
8372 * potential stalled Ingress Queue, issue a note indicating
8373 * that the Ingress Queue has resumed forward progress.
8375 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8376 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8377 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8378 "resumed after %d seconds\n",
8379 i, idma->idma_qid[i],
8380 idma->idma_stalled[i] / hz);
8381 idma->idma_stalled[i] = 0;
8385 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8386 * domain. The first time we get here it'll be because we
8387 * passed the 1s Threshold; each additional time it'll be
8388 * because the RX Timer Callback is being fired on its regular
8391 * If the stall is below our Potential Hung Ingress Queue
8392 * Warning Threshold, continue.
8394 if (idma->idma_stalled[i] == 0) {
8395 idma->idma_stalled[i] = hz;
8396 idma->idma_warn[i] = 0;
8398 idma->idma_stalled[i] += ticks;
8399 idma->idma_warn[i] -= ticks;
8402 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8405 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8407 if (idma->idma_warn[i] > 0)
8409 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8411 /* Read and save the SGE IDMA State and Queue ID information.
8412 * We do this every time in case it changes across time ...
8413 * can't be too careful ...
8415 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8416 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8417 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8419 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8420 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8421 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8423 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8424 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8425 i, idma->idma_qid[i], idma->idma_state[i],
8426 idma->idma_stalled[i] / hz,
8428 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8433 * t4_set_vf_mac - Set MAC address for the specified VF
8434 * @adapter: The adapter
8435 * @vf: one of the VFs instantiated by the specified PF
8436 * @naddr: the number of MAC addresses
8437 * @addr: the MAC address(es) to be set to the specified VF
8439 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8440 unsigned int naddr, u8 *addr)
8442 struct fw_acl_mac_cmd cmd;
8444 memset(&cmd, 0, sizeof(cmd));
8445 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8448 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8449 FW_ACL_MAC_CMD_VFN_V(vf));
8451 /* Note: Do not enable the ACL */
8452 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8455 switch (adapter->pf) {
8457 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8460 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8463 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8466 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8470 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8473 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8474 int rateunit, int ratemode, int channel, int class,
8475 int minrate, int maxrate, int weight, int pktsize)
8477 struct fw_sched_cmd cmd;
8479 memset(&cmd, 0, sizeof(cmd));
8480 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8483 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8485 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8486 cmd.u.params.type = type;
8487 cmd.u.params.level = level;
8488 cmd.u.params.mode = mode;
8489 cmd.u.params.ch = channel;
8490 cmd.u.params.cl = class;
8491 cmd.u.params.unit = rateunit;
8492 cmd.u.params.rate = ratemode;
8493 cmd.u.params.min = cpu_to_be32(minrate);
8494 cmd.u.params.max = cpu_to_be32(maxrate);
8495 cmd.u.params.weight = cpu_to_be16(weight);
8496 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8498 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),