2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
54 CPL_TX_DATA_ISO = 0x1F,
56 CPL_CLOSE_LISTSRV_RPL = 0x20,
57 CPL_L2T_WRITE_RPL = 0x23,
58 CPL_PASS_OPEN_RPL = 0x24,
59 CPL_ACT_OPEN_RPL = 0x25,
60 CPL_PEER_CLOSE = 0x26,
61 CPL_ABORT_REQ_RSS = 0x2B,
62 CPL_ABORT_RPL_RSS = 0x2D,
64 CPL_RX_PHYS_ADDR = 0x30,
65 CPL_CLOSE_CON_RPL = 0x32,
68 CPL_RDMA_CQE_READ_RSP = 0x36,
69 CPL_RDMA_CQE_ERR = 0x37,
71 CPL_SET_TCB_RPL = 0x3A,
73 CPL_RX_DDP_COMPLETE = 0x3F,
75 CPL_ACT_ESTABLISH = 0x40,
76 CPL_PASS_ESTABLISH = 0x41,
77 CPL_RX_DATA_DDP = 0x42,
78 CPL_PASS_ACCEPT_REQ = 0x44,
79 CPL_RX_ISCSI_CMP = 0x45,
80 CPL_TRACE_PKT_T5 = 0x48,
81 CPL_RX_ISCSI_DDP = 0x49,
83 CPL_RDMA_READ_REQ = 0x60,
85 CPL_PASS_OPEN_REQ6 = 0x81,
86 CPL_ACT_OPEN_REQ6 = 0x83,
88 CPL_TX_TLS_PDU = 0x88,
89 CPL_TX_SEC_PDU = 0x8A,
90 CPL_TX_TLS_ACK = 0x8B,
92 CPL_RDMA_TERMINATE = 0xA2,
93 CPL_RDMA_WRITE = 0xA4,
94 CPL_SGE_EGR_UPDATE = 0xA5,
97 CPL_ISCSI_DATA = 0xB2,
103 CPL_RX_PHYS_DSGL = 0xD0,
107 CPL_TX_PKT_LSO = 0xED,
108 CPL_TX_PKT_XT = 0xEE,
115 CPL_ERR_TCAM_PARITY = 1,
116 CPL_ERR_TCAM_MISS = 2,
117 CPL_ERR_TCAM_FULL = 3,
118 CPL_ERR_BAD_LENGTH = 15,
119 CPL_ERR_BAD_ROUTE = 18,
120 CPL_ERR_CONN_RESET = 20,
121 CPL_ERR_CONN_EXIST_SYNRECV = 21,
122 CPL_ERR_CONN_EXIST = 22,
123 CPL_ERR_ARP_MISS = 23,
124 CPL_ERR_BAD_SYN = 24,
125 CPL_ERR_CONN_TIMEDOUT = 30,
126 CPL_ERR_XMIT_TIMEDOUT = 31,
127 CPL_ERR_PERSIST_TIMEDOUT = 32,
128 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
129 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
130 CPL_ERR_RTX_NEG_ADVICE = 35,
131 CPL_ERR_PERSIST_NEG_ADVICE = 36,
132 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
133 CPL_ERR_ABORT_FAILED = 42,
134 CPL_ERR_IWARP_FLM = 50,
138 CPL_CONN_POLICY_AUTO = 0,
139 CPL_CONN_POLICY_ASK = 1,
140 CPL_CONN_POLICY_FILTER = 2,
141 CPL_CONN_POLICY_DENY = 3
153 ULP_CRC_HEADER = 1 << 0,
154 ULP_CRC_DATA = 1 << 1
158 CPL_ABORT_SEND_RST = 0,
162 enum { /* TX_PKT_XT checksum types */
181 #define CPL_OPCODE_S 24
182 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
183 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
184 #define TID_G(x) ((x) & 0xFFFFFF)
186 /* tid is assumed to be 24-bits */
187 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
189 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
191 /* extract the TID from a CPL command */
192 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
194 /* partitioning of TID fields that also carry a queue id */
196 #define TID_TID_M 0x3fff
197 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
200 #define TID_QID_M 0x3ff
201 #define TID_QID_V(x) ((x) << TID_QID_S)
202 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
206 #if defined(__LITTLE_ENDIAN_BITFIELD)
225 struct work_request_hdr {
233 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
235 #define WR_HDR struct work_request_hdr wr
237 /* option 0 fields */
239 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
242 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
244 #define RCV_BUFSIZ_S 12
245 #define RCV_BUFSIZ_M 0x3FFU
246 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
248 #define SMAC_SEL_S 28
249 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
252 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
254 #define WND_SCALE_S 50
255 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
257 #define KEEP_ALIVE_S 54
258 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
259 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
262 #define MSS_IDX_M 0xF
263 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
264 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
266 /* option 2 fields */
267 #define RSS_QUEUE_S 0
268 #define RSS_QUEUE_M 0x3FF
269 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
270 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
272 #define RSS_QUEUE_VALID_S 10
273 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
274 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
276 #define RX_FC_DISABLE_S 20
277 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
278 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
280 #define RX_FC_VALID_S 22
281 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
282 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
284 #define RX_CHANNEL_S 26
285 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
287 #define WND_SCALE_EN_S 28
288 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
289 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
291 #define T5_OPT_2_VALID_S 31
292 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
293 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
295 struct cpl_pass_open_req {
306 /* option 0 fields */
308 #define NO_CONG_V(x) ((x) << NO_CONG_S)
309 #define NO_CONG_F NO_CONG_V(1U)
312 #define DELACK_V(x) ((x) << DELACK_S)
313 #define DELACK_F DELACK_V(1U)
317 #define DSCP_V(x) ((x) << DSCP_S)
318 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
320 #define TCAM_BYPASS_S 48
321 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
322 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
325 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
326 #define NAGLE_F NAGLE_V(1ULL)
328 /* option 1 fields */
329 #define SYN_RSS_ENABLE_S 0
330 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
331 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
333 #define SYN_RSS_QUEUE_S 2
334 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
336 #define CONN_POLICY_S 22
337 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
339 struct cpl_pass_open_req6 {
352 struct cpl_pass_open_rpl {
361 #if defined(__LITTLE_ENDIAN_BITFIELD)
376 struct cpl_pass_accept_req {
384 struct tcp_options tcpopt;
387 /* cpl_pass_accept_req.hdr_len fields */
388 #define SYN_RX_CHAN_S 0
389 #define SYN_RX_CHAN_M 0xF
390 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
391 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
393 #define TCP_HDR_LEN_S 10
394 #define TCP_HDR_LEN_M 0x3F
395 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
396 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
398 #define IP_HDR_LEN_S 16
399 #define IP_HDR_LEN_M 0x3FF
400 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
401 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
403 #define ETH_HDR_LEN_S 26
404 #define ETH_HDR_LEN_M 0x1F
405 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
406 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
408 /* cpl_pass_accept_req.l2info fields */
409 #define SYN_MAC_IDX_S 0
410 #define SYN_MAC_IDX_M 0x1FF
411 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
412 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
414 #define SYN_XACT_MATCH_S 9
415 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
416 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
418 #define SYN_INTF_S 12
419 #define SYN_INTF_M 0xF
420 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
421 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
423 enum { /* TCP congestion control algorithms */
430 #define CONG_CNTRL_S 14
431 #define CONG_CNTRL_M 0x3
432 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
433 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
436 #define T5_ISS_V(x) ((x) << T5_ISS_S)
437 #define T5_ISS_F T5_ISS_V(1U)
439 struct cpl_pass_accept_rpl {
446 /* option 2 fields */
447 #define RX_COALESCE_VALID_S 11
448 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
449 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
451 #define RX_COALESCE_S 12
452 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
455 #define PACE_V(x) ((x) << PACE_S)
457 #define TX_QUEUE_S 23
458 #define TX_QUEUE_M 0x7
459 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
460 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
462 #define CCTRL_ECN_S 27
463 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
464 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
466 #define TSTAMPS_EN_S 29
467 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
468 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
471 #define SACK_EN_V(x) ((x) << SACK_EN_S)
472 #define SACK_EN_F SACK_EN_V(1U)
474 struct cpl_t5_pass_accept_rpl {
483 struct cpl_act_open_req {
495 #define FILTER_TUPLE_S 24
496 #define FILTER_TUPLE_M 0xFFFFFFFFFF
497 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
498 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
499 struct cpl_t5_act_open_req {
512 struct cpl_t6_act_open_req {
527 struct cpl_act_open_req6 {
541 struct cpl_t5_act_open_req6 {
556 struct cpl_t6_act_open_req6 {
573 struct cpl_act_open_rpl {
578 /* cpl_act_open_rpl.atid_status fields */
579 #define AOPEN_STATUS_S 0
580 #define AOPEN_STATUS_M 0xFF
581 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
583 #define AOPEN_ATID_S 8
584 #define AOPEN_ATID_M 0xFFFFFF
585 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
587 struct cpl_pass_establish {
597 /* cpl_pass_establish.tos_stid fields */
598 #define PASS_OPEN_TID_S 0
599 #define PASS_OPEN_TID_M 0xFFFFFF
600 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
601 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
603 #define PASS_OPEN_TOS_S 24
604 #define PASS_OPEN_TOS_M 0xFF
605 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
606 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
608 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
609 #define TCPOPT_WSCALE_OK_S 5
610 #define TCPOPT_WSCALE_OK_M 0x1
611 #define TCPOPT_WSCALE_OK_G(x) \
612 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
614 #define TCPOPT_SACK_S 6
615 #define TCPOPT_SACK_M 0x1
616 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
618 #define TCPOPT_TSTAMP_S 7
619 #define TCPOPT_TSTAMP_M 0x1
620 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
622 #define TCPOPT_SND_WSCALE_S 8
623 #define TCPOPT_SND_WSCALE_M 0xF
624 #define TCPOPT_SND_WSCALE_G(x) \
625 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
627 #define TCPOPT_MSS_S 12
628 #define TCPOPT_MSS_M 0xF
629 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
631 #define T6_TCP_HDR_LEN_S 8
632 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
633 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
635 #define T6_IP_HDR_LEN_S 14
636 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
637 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
639 #define T6_ETH_HDR_LEN_S 24
640 #define T6_ETH_HDR_LEN_M 0xFF
641 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
642 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
644 struct cpl_act_establish {
661 /* cpl_get_tcb.reply_ctrl fields */
663 #define QUEUENO_V(x) ((x) << QUEUENO_S)
665 #define REPLY_CHAN_S 14
666 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
667 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
669 #define NO_REPLY_S 15
670 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
671 #define NO_REPLY_F NO_REPLY_V(1U)
673 struct cpl_set_tcb_field {
682 /* cpl_set_tcb_field.word_cookie fields */
684 #define TCB_WORD(x) ((x) << TCB_WORD_S)
686 #define TCB_COOKIE_S 5
687 #define TCB_COOKIE_M 0x7
688 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
689 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
691 struct cpl_set_tcb_rpl {
699 struct cpl_close_con_req {
705 struct cpl_close_con_rpl {
713 struct cpl_close_listsvr_req {
720 /* additional cpl_close_listsvr_req.reply_ctrl field */
721 #define LISTSVR_IPV6_S 14
722 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
723 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
725 struct cpl_close_listsvr_rpl {
731 struct cpl_abort_req_rss {
737 struct cpl_abort_req {
746 struct cpl_abort_rpl_rss {
752 struct cpl_abort_rpl {
761 struct cpl_peer_close {
766 struct cpl_tid_release {
772 struct cpl_tx_pkt_core {
781 struct cpl_tx_pkt_core c;
784 #define cpl_tx_pkt_xt cpl_tx_pkt
786 /* cpl_tx_pkt_core.ctrl0 fields */
788 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
791 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
793 #define TXPKT_VF_VLD_S 11
794 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
795 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
797 #define TXPKT_OVLAN_IDX_S 12
798 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
800 #define TXPKT_T5_OVLAN_IDX_S 12
801 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
803 #define TXPKT_INTF_S 16
804 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
806 #define TXPKT_INS_OVLAN_S 21
807 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
808 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
810 #define TXPKT_OPCODE_S 24
811 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
813 /* cpl_tx_pkt_core.ctrl1 fields */
814 #define TXPKT_CSUM_END_S 12
815 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
817 #define TXPKT_CSUM_START_S 20
818 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
820 #define TXPKT_IPHDR_LEN_S 20
821 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
823 #define TXPKT_CSUM_LOC_S 30
824 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
826 #define TXPKT_ETHHDR_LEN_S 34
827 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
829 #define T6_TXPKT_ETHHDR_LEN_S 32
830 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
832 #define TXPKT_CSUM_TYPE_S 40
833 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
835 #define TXPKT_VLAN_S 44
836 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
838 #define TXPKT_VLAN_VLD_S 60
839 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
840 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
842 #define TXPKT_IPCSUM_DIS_S 62
843 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
844 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
846 #define TXPKT_L4CSUM_DIS_S 63
847 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
848 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
850 struct cpl_tx_pkt_lso_core {
856 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
859 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
860 #define LSO_TCPHDR_LEN_S 0
861 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
863 #define LSO_IPHDR_LEN_S 4
864 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
866 #define LSO_ETHHDR_LEN_S 16
867 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
869 #define LSO_IPV6_S 20
870 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
871 #define LSO_IPV6_F LSO_IPV6_V(1U)
873 #define LSO_LAST_SLICE_S 22
874 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
875 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
877 #define LSO_FIRST_SLICE_S 23
878 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
879 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
881 #define LSO_OPCODE_S 24
882 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
884 #define LSO_T5_XFER_SIZE_S 0
885 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
887 struct cpl_tx_pkt_lso {
889 struct cpl_tx_pkt_lso_core c;
890 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
893 struct cpl_iscsi_hdr {
903 /* cpl_iscsi_hdr.pdu_len_ddp fields */
904 #define ISCSI_PDU_LEN_S 0
905 #define ISCSI_PDU_LEN_M 0x7FFF
906 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
907 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
909 #define ISCSI_DDP_S 15
910 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
911 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
913 struct cpl_rx_data_ddp {
926 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
928 struct cpl_iscsi_data {
938 struct cpl_rx_iscsi_cmp {
950 struct cpl_tx_data_iso {
957 __be32 reserved2_seglen_offset;
958 __be32 datasn_offset;
959 __be32 buffer_offset;
962 /* encapsulated CPL_TX_DATA follows here */
965 /* cpl_tx_data_iso.op_to_scsi fields */
966 #define CPL_TX_DATA_ISO_OP_S 24
967 #define CPL_TX_DATA_ISO_OP_M 0xff
968 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
969 #define CPL_TX_DATA_ISO_OP_G(x) \
970 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
972 #define CPL_TX_DATA_ISO_FIRST_S 23
973 #define CPL_TX_DATA_ISO_FIRST_M 0x1
974 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
975 #define CPL_TX_DATA_ISO_FIRST_G(x) \
976 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
977 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
979 #define CPL_TX_DATA_ISO_LAST_S 22
980 #define CPL_TX_DATA_ISO_LAST_M 0x1
981 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
982 #define CPL_TX_DATA_ISO_LAST_G(x) \
983 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
984 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
986 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
987 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
988 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
989 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
990 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
991 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
993 #define CPL_TX_DATA_ISO_HDRCRC_S 20
994 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1
995 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
996 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \
997 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
998 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1000 #define CPL_TX_DATA_ISO_PLDCRC_S 19
1001 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1002 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1003 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1004 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1005 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1007 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1008 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1009 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1010 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1011 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1012 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1014 #define CPL_TX_DATA_ISO_SCSI_S 16
1015 #define CPL_TX_DATA_ISO_SCSI_M 0x3
1016 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1017 #define CPL_TX_DATA_ISO_SCSI_G(x) \
1018 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1020 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1021 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1022 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1023 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1024 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1025 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1026 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1027 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1029 struct cpl_rx_data {
1030 union opcode_tid ot;
1035 #if defined(__LITTLE_ENDIAN_BITFIELD)
1051 struct cpl_rx_data_ack {
1053 union opcode_tid ot;
1057 /* cpl_rx_data_ack.ack_seq fields */
1058 #define RX_CREDITS_S 0
1059 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1061 #define RX_FORCE_ACK_S 28
1062 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1063 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1065 #define RX_DACK_MODE_S 29
1066 #define RX_DACK_MODE_M 0x3
1067 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1068 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1070 #define RX_DACK_CHANGE_S 31
1071 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1072 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1075 struct rss_header rsshdr;
1077 #if defined(__LITTLE_ENDIAN_BITFIELD)
1098 #define RX_T6_ETHHDR_LEN_M 0xFF
1099 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1101 #define RXF_PSH_S 20
1102 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1103 #define RXF_PSH_F RXF_PSH_V(1U)
1105 #define RXF_SYN_S 21
1106 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1107 #define RXF_SYN_F RXF_SYN_V(1U)
1109 #define RXF_UDP_S 22
1110 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1111 #define RXF_UDP_F RXF_UDP_V(1U)
1113 #define RXF_TCP_S 23
1114 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1115 #define RXF_TCP_F RXF_TCP_V(1U)
1118 #define RXF_IP_V(x) ((x) << RXF_IP_S)
1119 #define RXF_IP_F RXF_IP_V(1U)
1121 #define RXF_IP6_S 25
1122 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1123 #define RXF_IP6_F RXF_IP6_V(1U)
1125 #define RXF_SYN_COOKIE_S 26
1126 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1127 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1129 #define RXF_FCOE_S 26
1130 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1131 #define RXF_FCOE_F RXF_FCOE_V(1U)
1133 #define RXF_LRO_S 27
1134 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1135 #define RXF_LRO_F RXF_LRO_V(1U)
1137 /* rx_pkt.l2info fields */
1138 #define RX_ETHHDR_LEN_S 0
1139 #define RX_ETHHDR_LEN_M 0x1F
1140 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1141 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1143 #define RX_T5_ETHHDR_LEN_S 0
1144 #define RX_T5_ETHHDR_LEN_M 0x3F
1145 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1146 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1148 #define RX_MACIDX_S 8
1149 #define RX_MACIDX_M 0x1FF
1150 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1151 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1153 #define RXF_SYN_S 21
1154 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1155 #define RXF_SYN_F RXF_SYN_V(1U)
1157 #define RX_CHAN_S 28
1158 #define RX_CHAN_M 0xF
1159 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1160 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1162 /* rx_pkt.hdr_len fields */
1163 #define RX_TCPHDR_LEN_S 0
1164 #define RX_TCPHDR_LEN_M 0x3F
1165 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1166 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1168 #define RX_IPHDR_LEN_S 6
1169 #define RX_IPHDR_LEN_M 0x3FF
1170 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1171 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1173 /* rx_pkt.err_vec fields */
1174 #define RXERR_CSUM_S 13
1175 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1176 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
1178 struct cpl_trace_pkt {
1181 #if defined(__LITTLE_ENDIAN_BITFIELD)
1199 struct cpl_t5_trace_pkt {
1202 #if defined(__LITTLE_ENDIAN_BITFIELD)
1221 struct cpl_l2t_write_req {
1223 union opcode_tid ot;
1230 /* cpl_l2t_write_req.params fields */
1231 #define L2T_W_INFO_S 2
1232 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1234 #define L2T_W_PORT_S 8
1235 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1237 #define L2T_W_NOREPLY_S 15
1238 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1239 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1241 #define CPL_L2T_VLAN_NONE 0xfff
1243 struct cpl_l2t_write_rpl {
1244 union opcode_tid ot;
1249 struct cpl_rdma_terminate {
1250 union opcode_tid ot;
1255 struct cpl_sge_egr_update {
1261 /* cpl_sge_egr_update.ot fields */
1263 #define EGR_QID_M 0x1FFFF
1264 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1266 /* cpl_fw*.type values */
1268 FW_TYPE_CMD_RPL = 0,
1271 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1275 struct cpl_fw4_pld {
1285 struct cpl_fw6_pld {
1292 struct cpl_fw4_msg {
1300 struct cpl_fw4_ack {
1301 union opcode_tid ot;
1311 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
1312 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
1313 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
1316 struct cpl_fw6_msg {
1324 /* cpl_fw6_msg.type values */
1326 FW6_TYPE_CMD_RPL = 0,
1327 FW6_TYPE_WR_RPL = 1,
1329 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1330 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1333 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1335 __be32 tid; /* or atid in case of active failure */
1341 struct cpl_tx_data {
1342 union opcode_tid ot;
1348 /* cpl_tx_data.flags field */
1349 #define TX_FORCE_S 13
1350 #define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1353 ULP_TX_MEM_READ = 2,
1354 ULP_TX_MEM_WRITE = 3,
1359 ULP_TX_SC_NOOP = 0x80,
1360 ULP_TX_SC_IMM = 0x81,
1361 ULP_TX_SC_DSGL = 0x82,
1362 ULP_TX_SC_ISGL = 0x83
1365 #define ULPTX_CMD_S 24
1366 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1368 struct ulptx_sge_pair {
1377 struct ulptx_sge_pair sge[0];
1380 struct ulptx_idata {
1390 #define ULPTX_CMD_S 24
1391 #define ULPTX_CMD_M 0xFF
1392 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1394 #define ULPTX_NSGE_S 0
1395 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1397 #define ULPTX_MORE_S 23
1398 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1399 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1401 #define ULP_TXPKT_DEST_S 16
1402 #define ULP_TXPKT_DEST_M 0x3
1403 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1405 #define ULP_TXPKT_FID_S 4
1406 #define ULP_TXPKT_FID_M 0x7ff
1407 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1409 #define ULP_TXPKT_RO_S 3
1410 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1411 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1413 #define ULP_TX_SC_MORE_S 23
1414 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1415 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1420 __be32 len16; /* command length */
1421 __be32 dlen; /* data length in 32-byte units */
1425 #define ULP_MEMIO_LOCK_S 31
1426 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1427 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1429 /* additional ulp_mem_io.cmd fields */
1430 #define ULP_MEMIO_ORDER_S 23
1431 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1432 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1434 #define T5_ULP_MEMIO_IMM_S 23
1435 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1436 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1438 #define T5_ULP_MEMIO_ORDER_S 22
1439 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1440 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1442 #define T5_ULP_MEMIO_FID_S 4
1443 #define T5_ULP_MEMIO_FID_M 0x7ff
1444 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1446 /* ulp_mem_io.lock_addr fields */
1447 #define ULP_MEMIO_ADDR_S 0
1448 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1450 /* ulp_mem_io.dlen fields */
1451 #define ULP_MEMIO_DATA_LEN_S 0
1452 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1454 #define ULPTX_NSGE_S 0
1455 #define ULPTX_NSGE_M 0xFFFF
1456 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1457 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1459 struct ulptx_sc_memrd {
1464 #define ULP_TXPKT_DATAMODIFY_S 23
1465 #define ULP_TXPKT_DATAMODIFY_M 0x1
1466 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1467 #define ULP_TXPKT_DATAMODIFY_G(x) \
1468 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1469 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1471 #define ULP_TXPKT_CHANNELID_S 22
1472 #define ULP_TXPKT_CHANNELID_M 0x1
1473 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1474 #define ULP_TXPKT_CHANNELID_G(x) \
1475 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1476 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1478 #define SCMD_SEQ_NO_CTRL_S 29
1479 #define SCMD_SEQ_NO_CTRL_M 0x3
1480 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1481 #define SCMD_SEQ_NO_CTRL_G(x) \
1482 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1484 /* StsFieldPrsnt- Status field at the end of the TLS PDU */
1485 #define SCMD_STATUS_PRESENT_S 28
1486 #define SCMD_STATUS_PRESENT_M 0x1
1487 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1488 #define SCMD_STATUS_PRESENT_G(x) \
1489 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1490 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1492 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1495 #define SCMD_PROTO_VERSION_S 24
1496 #define SCMD_PROTO_VERSION_M 0xf
1497 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1498 #define SCMD_PROTO_VERSION_G(x) \
1499 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1501 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1502 #define SCMD_ENC_DEC_CTRL_S 23
1503 #define SCMD_ENC_DEC_CTRL_M 0x1
1504 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1505 #define SCMD_ENC_DEC_CTRL_G(x) \
1506 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1507 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1509 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1510 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1511 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1512 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1513 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1514 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1515 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1516 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1518 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1519 * 4:Generic-AES, 5-15: Reserved.
1521 #define SCMD_CIPH_MODE_S 18
1522 #define SCMD_CIPH_MODE_M 0xf
1523 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1524 #define SCMD_CIPH_MODE_G(x) \
1525 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1527 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1530 #define SCMD_AUTH_MODE_S 14
1531 #define SCMD_AUTH_MODE_M 0xf
1532 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1533 #define SCMD_AUTH_MODE_G(x) \
1534 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1536 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1537 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1539 #define SCMD_HMAC_CTRL_S 11
1540 #define SCMD_HMAC_CTRL_M 0x7
1541 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1542 #define SCMD_HMAC_CTRL_G(x) \
1543 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1545 /* IvSize - IV size in units of 2 bytes */
1546 #define SCMD_IV_SIZE_S 7
1547 #define SCMD_IV_SIZE_M 0xf
1548 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1549 #define SCMD_IV_SIZE_G(x) \
1550 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1552 /* NumIVs - Number of IVs */
1553 #define SCMD_NUM_IVS_S 0
1554 #define SCMD_NUM_IVS_M 0x7f
1555 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1556 #define SCMD_NUM_IVS_G(x) \
1557 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1559 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1560 * (below) are used as Cid (connection id for debug status), these
1561 * bits are padded to zero for forming the 64 bit
1562 * sequence number for TLS
1564 #define SCMD_ENB_DBGID_S 31
1565 #define SCMD_ENB_DBGID_M 0x1
1566 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1567 #define SCMD_ENB_DBGID_G(x) \
1568 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1570 /* IV generation in SW. */
1571 #define SCMD_IV_GEN_CTRL_S 30
1572 #define SCMD_IV_GEN_CTRL_M 0x1
1573 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1574 #define SCMD_IV_GEN_CTRL_G(x) \
1575 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1576 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1579 #define SCMD_MORE_FRAGS_S 20
1580 #define SCMD_MORE_FRAGS_M 0x1
1581 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1582 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1585 #define SCMD_LAST_FRAG_S 19
1586 #define SCMD_LAST_FRAG_M 0x1
1587 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1588 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1591 #define SCMD_TLS_COMPPDU_S 18
1592 #define SCMD_TLS_COMPPDU_M 0x1
1593 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1594 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1596 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1597 #define SCMD_KEY_CTX_INLINE_S 17
1598 #define SCMD_KEY_CTX_INLINE_M 0x1
1599 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1600 #define SCMD_KEY_CTX_INLINE_G(x) \
1601 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1602 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1604 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1605 #define SCMD_TLS_FRAG_ENABLE_S 16
1606 #define SCMD_TLS_FRAG_ENABLE_M 0x1
1607 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1608 #define SCMD_TLS_FRAG_ENABLE_G(x) \
1609 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1610 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1612 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1613 * modes, in this case TLS_TX will drop the PDU and only
1614 * send back the MAC bytes.
1616 #define SCMD_MAC_ONLY_S 15
1617 #define SCMD_MAC_ONLY_M 0x1
1618 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1619 #define SCMD_MAC_ONLY_G(x) \
1620 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1621 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1623 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1624 * which have complex AAD and IV formations Eg:AES-CCM
1626 #define SCMD_AADIVDROP_S 14
1627 #define SCMD_AADIVDROP_M 0x1
1628 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1629 #define SCMD_AADIVDROP_G(x) \
1630 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1631 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1633 /* HdrLength - Length of all headers excluding TLS header
1634 * present before start of crypto PDU/payload.
1636 #define SCMD_HDR_LEN_S 0
1637 #define SCMD_HDR_LEN_M 0x3fff
1638 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1639 #define SCMD_HDR_LEN_G(x) \
1640 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1642 struct cpl_tx_sec_pdu {
1643 __be32 op_ivinsrtofst;
1645 __be32 aadstart_cipherstop_hi;
1646 __be32 cipherstop_lo_authinsert;
1647 __be32 seqno_numivs;
1648 __be32 ivgen_hdrlen;
1652 #define CPL_TX_SEC_PDU_OPCODE_S 24
1653 #define CPL_TX_SEC_PDU_OPCODE_M 0xff
1654 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1655 #define CPL_TX_SEC_PDU_OPCODE_G(x) \
1656 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1659 #define CPL_TX_SEC_PDU_RXCHID_S 22
1660 #define CPL_TX_SEC_PDU_RXCHID_M 0x1
1661 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1662 #define CPL_TX_SEC_PDU_RXCHID_G(x) \
1663 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1664 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1667 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1668 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1669 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1670 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1671 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1672 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1674 /* Loopback bit in cpl_tx_sec_pdu */
1675 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1676 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1677 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1678 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1679 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1680 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1682 /* Length of cpl header encapsulated */
1683 #define CPL_TX_SEC_PDU_CPLLEN_S 16
1684 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1685 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1686 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1687 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1690 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1691 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1692 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1693 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1694 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1695 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1697 /* IvInsrtOffset: Insertion location for IV */
1698 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1699 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1700 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1701 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1702 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1703 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1705 /* AadStartOffset: Offset in bytes for AAD start from
1706 * the first byte following the pkt headers (0-255 bytes)
1708 #define CPL_TX_SEC_PDU_AADSTART_S 24
1709 #define CPL_TX_SEC_PDU_AADSTART_M 0xff
1710 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1711 #define CPL_TX_SEC_PDU_AADSTART_G(x) \
1712 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1713 CPL_TX_SEC_PDU_AADSTART_M)
1715 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1716 * the pkt headers (0-511 bytes)
1718 #define CPL_TX_SEC_PDU_AADSTOP_S 15
1719 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1720 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1721 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1722 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1724 /* CipherStartOffset: offset in bytes for encryption/decryption start from the
1725 * first byte following the pkt headers (0-1023 bytes)
1727 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1728 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1729 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1730 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1731 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1732 CPL_TX_SEC_PDU_CIPHERSTART_M)
1734 /* CipherStopOffset: offset in bytes for encryption/decryption end
1735 * from end of the payload of this command (0-511 bytes)
1737 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1738 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1739 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1740 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
1741 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
1742 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
1743 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
1745 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
1746 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
1747 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
1748 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
1749 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
1750 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
1751 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
1753 /* AuthStartOffset: offset in bytes for authentication start from
1754 * the first byte following the pkt headers (0-1023)
1756 #define CPL_TX_SEC_PDU_AUTHSTART_S 18
1757 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
1758 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
1759 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
1760 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
1761 CPL_TX_SEC_PDU_AUTHSTART_M)
1763 /* AuthStopOffset: offset in bytes for authentication
1764 * end from end of the payload of this command (0-511 Bytes)
1766 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9
1767 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
1768 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
1769 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
1770 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
1771 CPL_TX_SEC_PDU_AUTHSTOP_M)
1773 /* AuthInsrtOffset: offset in bytes for authentication insertion
1774 * from end of the payload of this command (0-511 bytes)
1776 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0
1777 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
1778 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
1779 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
1780 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
1781 CPL_TX_SEC_PDU_AUTHINSERT_M)
1783 struct cpl_rx_phys_dsgl {
1785 __be32 pcirlxorder_to_noofsgentr;
1786 struct rss_header rss_hdr_int;
1789 #define CPL_RX_PHYS_DSGL_OPCODE_S 24
1790 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
1791 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
1792 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
1793 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
1795 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23
1796 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
1797 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
1798 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
1799 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
1800 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
1802 #define CPL_RX_PHYS_DSGL_RSVD1_S 20
1803 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
1804 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
1805 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
1806 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
1807 CPL_RX_PHYS_DSGL_RSVD1_M)
1809 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
1810 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
1811 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
1812 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
1813 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
1814 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
1815 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
1816 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
1818 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
1819 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
1820 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
1821 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
1822 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
1823 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
1824 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
1826 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
1828 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
1829 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
1830 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
1831 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
1832 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
1833 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
1834 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
1835 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
1837 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
1838 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
1839 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
1840 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
1841 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
1842 CPL_RX_PHYS_DSGL_PCITPHNT_M)
1844 #define CPL_RX_PHYS_DSGL_DCAID_S 16
1845 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
1846 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
1847 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \
1848 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
1849 CPL_RX_PHYS_DSGL_DCAID_M)
1851 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
1852 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
1853 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
1854 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
1855 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
1856 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
1857 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
1859 #endif /* __T4_MSG_H */