2 * Dave DNET Ethernet Controller driver
4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/netdevice.h>
20 #include <linux/etherdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/platform_device.h>
23 #include <linux/phy.h>
29 /* function for reading internal MAC register */
30 static u16 dnet_readw_mac(struct dnet *bp, u16 reg)
35 dnet_writel(bp, reg, MACREG_ADDR);
37 /* since a read/write op to the MAC is very slow,
38 * we must wait before reading the data */
41 /* read data read from the MAC register */
42 data_read = dnet_readl(bp, MACREG_DATA);
48 /* function for writing internal MAC register */
49 static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
51 /* load data to write */
52 dnet_writel(bp, val, MACREG_DATA);
55 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
57 /* since a read/write op to the MAC is very slow,
58 * we must wait before exiting */
62 static void __dnet_set_hwaddr(struct dnet *bp)
66 tmp = be16_to_cpup((__be16 *)bp->dev->dev_addr);
67 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
68 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 2));
69 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
70 tmp = be16_to_cpup((__be16 *)(bp->dev->dev_addr + 4));
71 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
74 static void dnet_get_hwaddr(struct dnet *bp)
81 * "Note that the MAC address is stored in the registers in Hexadecimal
82 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80
83 * would require writing 0xAC (octet 0) to address 0x0B (high byte of
84 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
85 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
86 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
87 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
88 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
91 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
92 *((__be16 *)addr) = cpu_to_be16(tmp);
93 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
94 *((__be16 *)(addr + 2)) = cpu_to_be16(tmp);
95 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
96 *((__be16 *)(addr + 4)) = cpu_to_be16(tmp);
98 if (is_valid_ether_addr(addr))
99 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
102 static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
104 struct dnet *bp = bus->priv;
107 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
108 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
111 /* only 5 bits allowed for phy-addr and reg_offset */
115 /* prepare reg_value for a read */
116 value = (mii_id << 8);
119 /* write control word */
120 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
122 /* wait for end of transfer */
123 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
124 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
127 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
129 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
134 static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
137 struct dnet *bp = bus->priv;
140 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
142 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
143 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
146 /* prepare for a write operation */
149 /* only 5 bits allowed for phy-addr and reg_offset */
153 /* only 16 bits on data */
156 /* prepare reg_value for a write */
157 tmp |= (mii_id << 8);
160 /* write data to write first */
161 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
163 /* write control word */
164 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
166 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
167 & DNET_INTERNAL_GMII_MNG_CMD_FIN))
173 static void dnet_handle_link_change(struct net_device *dev)
175 struct dnet *bp = netdev_priv(dev);
176 struct phy_device *phydev = bp->phy_dev;
178 u32 mode_reg, ctl_reg;
180 int status_change = 0;
182 spin_lock_irqsave(&bp->lock, flags);
184 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
185 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
188 if (bp->duplex != phydev->duplex) {
191 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
194 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
196 bp->duplex = phydev->duplex;
200 if (bp->speed != phydev->speed) {
202 switch (phydev->speed) {
204 mode_reg |= DNET_INTERNAL_MODE_GBITEN;
208 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
212 "%s: Ack! Speed (%d) is not "
213 "10/100/1000!\n", dev->name,
217 bp->speed = phydev->speed;
221 if (phydev->link != bp->link) {
224 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
227 ~(DNET_INTERNAL_MODE_RXEN |
228 DNET_INTERNAL_MODE_TXEN);
232 bp->link = phydev->link;
238 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
239 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
242 spin_unlock_irqrestore(&bp->lock, flags);
246 printk(KERN_INFO "%s: link up (%d/%s)\n",
247 dev->name, phydev->speed,
248 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
250 printk(KERN_INFO "%s: link down\n", dev->name);
254 static int dnet_mii_probe(struct net_device *dev)
256 struct dnet *bp = netdev_priv(dev);
257 struct phy_device *phydev = NULL;
259 /* find the first phy */
260 phydev = phy_find_first(bp->mii_bus);
263 printk(KERN_ERR "%s: no PHY found\n", dev->name);
267 /* TODO : add pin_irq */
269 /* attach the mac to the phy */
270 if (bp->capabilities & DNET_HAS_RMII) {
271 phydev = phy_connect(dev, phydev_name(phydev),
272 &dnet_handle_link_change,
273 PHY_INTERFACE_MODE_RMII);
275 phydev = phy_connect(dev, phydev_name(phydev),
276 &dnet_handle_link_change,
277 PHY_INTERFACE_MODE_MII);
280 if (IS_ERR(phydev)) {
281 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
282 return PTR_ERR(phydev);
285 /* mask with MAC supported features */
286 if (bp->capabilities & DNET_HAS_GIGABIT)
287 phydev->supported &= PHY_GBIT_FEATURES;
289 phydev->supported &= PHY_BASIC_FEATURES;
291 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
293 phydev->advertising = phydev->supported;
298 bp->phy_dev = phydev;
303 static int dnet_mii_init(struct dnet *bp)
307 bp->mii_bus = mdiobus_alloc();
308 if (bp->mii_bus == NULL)
311 bp->mii_bus->name = "dnet_mii_bus";
312 bp->mii_bus->read = &dnet_mdio_read;
313 bp->mii_bus->write = &dnet_mdio_write;
315 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
316 bp->pdev->name, bp->pdev->id);
318 bp->mii_bus->priv = bp;
320 bp->mii_bus->irq = devm_kmalloc(&bp->pdev->dev,
321 sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
322 if (!bp->mii_bus->irq) {
327 for (i = 0; i < PHY_MAX_ADDR; i++)
328 bp->mii_bus->irq[i] = PHY_POLL;
330 if (mdiobus_register(bp->mii_bus)) {
335 if (dnet_mii_probe(bp->dev) != 0) {
337 goto err_out_unregister_bus;
342 err_out_unregister_bus:
343 mdiobus_unregister(bp->mii_bus);
345 mdiobus_free(bp->mii_bus);
349 /* For Neptune board: LINK1000 as Link LED and TX as activity LED */
350 static int dnet_phy_marvell_fixup(struct phy_device *phydev)
352 return phy_write(phydev, 0x18, 0x4148);
355 static void dnet_update_stats(struct dnet *bp)
357 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
358 u32 *p = &bp->hw_stats.rx_pkt_ignr;
359 u32 *end = &bp->hw_stats.rx_byte + 1;
361 WARN_ON((unsigned long)(end - p - 1) !=
362 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
364 for (; p < end; p++, reg++)
367 reg = bp->regs + DNET_TX_UNICAST_CNT;
368 p = &bp->hw_stats.tx_unicast;
369 end = &bp->hw_stats.tx_byte + 1;
371 WARN_ON((unsigned long)(end - p - 1) !=
372 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
374 for (; p < end; p++, reg++)
378 static int dnet_poll(struct napi_struct *napi, int budget)
380 struct dnet *bp = container_of(napi, struct dnet, napi);
381 struct net_device *dev = bp->dev;
383 unsigned int pkt_len;
385 unsigned int *data_ptr;
390 while (npackets < budget) {
392 * break out of while loop if there are no more
395 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16))
398 cmd_word = dnet_readl(bp, RX_LEN_FIFO);
399 pkt_len = cmd_word & 0xFFFF;
401 if (cmd_word & 0xDF180000)
402 printk(KERN_ERR "%s packet receive error %x\n",
405 skb = netdev_alloc_skb(dev, pkt_len + 5);
407 /* Align IP on 16 byte boundaries */
410 * 'skb_put()' points to the start of sk_buff
413 data_ptr = (unsigned int *)skb_put(skb, pkt_len);
414 for (i = 0; i < (pkt_len + 3) >> 2; i++)
415 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
416 skb->protocol = eth_type_trans(skb, dev);
417 netif_receive_skb(skb);
421 "%s: No memory to allocate a sk_buff of "
422 "size %u.\n", dev->name, pkt_len);
425 if (npackets < budget) {
426 /* We processed all packets available. Tell NAPI it can
427 * stop polling then re-enable rx interrupts.
430 int_enable = dnet_readl(bp, INTR_ENB);
431 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
432 dnet_writel(bp, int_enable, INTR_ENB);
438 static irqreturn_t dnet_interrupt(int irq, void *dev_id)
440 struct net_device *dev = dev_id;
441 struct dnet *bp = netdev_priv(dev);
442 u32 int_src, int_enable, int_current;
444 unsigned int handled = 0;
446 spin_lock_irqsave(&bp->lock, flags);
448 /* read and clear the DNET irq (clear on read) */
449 int_src = dnet_readl(bp, INTR_SRC);
450 int_enable = dnet_readl(bp, INTR_ENB);
451 int_current = int_src & int_enable;
453 /* restart the queue if we had stopped it for TX fifo almost full */
454 if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
455 int_enable = dnet_readl(bp, INTR_ENB);
456 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
457 dnet_writel(bp, int_enable, INTR_ENB);
458 netif_wake_queue(dev);
462 /* RX FIFO error checking */
464 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
465 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
466 dnet_readl(bp, RX_STATUS), int_current);
467 /* we can only flush the RX FIFOs */
468 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
470 dnet_writel(bp, 0, SYS_CTL);
474 /* TX FIFO error checking */
476 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
477 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
478 dnet_readl(bp, TX_STATUS), int_current);
479 /* we can only flush the TX FIFOs */
480 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
482 dnet_writel(bp, 0, SYS_CTL);
486 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
487 if (napi_schedule_prep(&bp->napi)) {
489 * There's no point taking any more interrupts
490 * until we have processed the buffers
492 /* Disable Rx interrupts and schedule NAPI poll */
493 int_enable = dnet_readl(bp, INTR_ENB);
494 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
495 dnet_writel(bp, int_enable, INTR_ENB);
496 __napi_schedule(&bp->napi);
502 pr_debug("%s: irq %x remains\n", __func__, int_current);
504 spin_unlock_irqrestore(&bp->lock, flags);
506 return IRQ_RETVAL(handled);
510 static inline void dnet_print_skb(struct sk_buff *skb)
513 printk(KERN_DEBUG PFX "data:");
514 for (k = 0; k < skb->len; k++)
515 printk(" %02x", (unsigned int)skb->data[k]);
519 #define dnet_print_skb(skb) do {} while (0)
522 static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
525 struct dnet *bp = netdev_priv(dev);
526 u32 tx_status, irq_enable;
527 unsigned int len, i, tx_cmd, wrsz;
531 tx_status = dnet_readl(bp, TX_STATUS);
533 pr_debug("start_xmit: len %u head %p data %p\n",
534 skb->len, skb->head, skb->data);
537 /* frame size (words) */
538 len = (skb->len + 3) >> 2;
540 spin_lock_irqsave(&bp->lock, flags);
542 tx_status = dnet_readl(bp, TX_STATUS);
544 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
545 wrsz = (u32) skb->len + 3;
546 wrsz += ((unsigned long) skb->data) & 0x3;
548 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
550 /* check if there is enough room for the current frame */
551 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
552 for (i = 0; i < wrsz; i++)
553 dnet_writel(bp, *bufp++, TX_DATA_FIFO);
556 * inform MAC that a packet's written and ready to be
559 dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
562 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
563 netif_stop_queue(dev);
564 tx_status = dnet_readl(bp, INTR_SRC);
565 irq_enable = dnet_readl(bp, INTR_ENB);
566 irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
567 dnet_writel(bp, irq_enable, INTR_ENB);
570 skb_tx_timestamp(skb);
572 /* free the buffer */
575 spin_unlock_irqrestore(&bp->lock, flags);
580 static void dnet_reset_hw(struct dnet *bp)
582 /* put ts_mac in IDLE state i.e. disable rx/tx */
583 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
586 * RX FIFO almost full threshold: only cmd FIFO almost full is
587 * implemented for RX side
589 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
591 * TX FIFO almost empty threshold: only data FIFO almost empty
592 * is implemented for TX side
594 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
596 /* flush rx/tx fifos */
597 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
600 dnet_writel(bp, 0, SYS_CTL);
603 static void dnet_init_hw(struct dnet *bp)
608 __dnet_set_hwaddr(bp);
610 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
612 if (bp->dev->flags & IFF_PROMISC)
613 /* Copy All Frames */
614 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
615 if (!(bp->dev->flags & IFF_BROADCAST))
617 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
619 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
620 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
621 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
622 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
624 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
626 /* clear irq before enabling them */
627 config = dnet_readl(bp, INTR_SRC);
629 /* enable RX/TX interrupt, recv packet ready interrupt */
630 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
631 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
632 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
633 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
634 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
637 static int dnet_open(struct net_device *dev)
639 struct dnet *bp = netdev_priv(dev);
641 /* if the phy is not yet register, retry later */
645 napi_enable(&bp->napi);
648 phy_start_aneg(bp->phy_dev);
650 /* schedule a link state check */
651 phy_start(bp->phy_dev);
653 netif_start_queue(dev);
658 static int dnet_close(struct net_device *dev)
660 struct dnet *bp = netdev_priv(dev);
662 netif_stop_queue(dev);
663 napi_disable(&bp->napi);
666 phy_stop(bp->phy_dev);
669 netif_carrier_off(dev);
674 static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
676 pr_debug("%s\n", __func__);
677 pr_debug("----------------------------- RX statistics "
678 "-------------------------------\n");
679 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
680 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
681 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
682 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
683 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
684 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
685 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
686 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
687 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
688 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
689 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
690 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
691 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
692 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
693 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
694 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
695 pr_debug("----------------------------- TX statistics "
696 "-------------------------------\n");
697 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
698 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
699 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
700 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
701 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
702 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
703 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
704 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
707 static struct net_device_stats *dnet_get_stats(struct net_device *dev)
710 struct dnet *bp = netdev_priv(dev);
711 struct net_device_stats *nstat = &dev->stats;
712 struct dnet_stats *hwstat = &bp->hw_stats;
714 /* read stats from hardware */
715 dnet_update_stats(bp);
717 /* Convert HW stats into netdevice stats */
718 nstat->rx_errors = (hwstat->rx_len_chk_err +
719 hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
720 /* ignore IGP violation error
721 hwstat->rx_ipg_viol + */
723 hwstat->rx_pre_shrink +
724 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
725 nstat->tx_errors = hwstat->tx_bad_fcs;
726 nstat->rx_length_errors = (hwstat->rx_len_chk_err +
728 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
729 nstat->rx_crc_errors = hwstat->rx_crc_err;
730 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
731 nstat->rx_packets = hwstat->rx_ok_pkt;
732 nstat->tx_packets = (hwstat->tx_unicast +
733 hwstat->tx_multicast + hwstat->tx_brdcast);
734 nstat->rx_bytes = hwstat->rx_byte;
735 nstat->tx_bytes = hwstat->tx_byte;
736 nstat->multicast = hwstat->rx_multicast;
737 nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
739 dnet_print_pretty_hwstats(hwstat);
744 static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
746 struct dnet *bp = netdev_priv(dev);
747 struct phy_device *phydev = bp->phy_dev;
752 return phy_ethtool_gset(phydev, cmd);
755 static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
757 struct dnet *bp = netdev_priv(dev);
758 struct phy_device *phydev = bp->phy_dev;
763 return phy_ethtool_sset(phydev, cmd);
766 static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
768 struct dnet *bp = netdev_priv(dev);
769 struct phy_device *phydev = bp->phy_dev;
771 if (!netif_running(dev))
777 return phy_mii_ioctl(phydev, rq, cmd);
780 static void dnet_get_drvinfo(struct net_device *dev,
781 struct ethtool_drvinfo *info)
783 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
784 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
785 strlcpy(info->bus_info, "0", sizeof(info->bus_info));
788 static const struct ethtool_ops dnet_ethtool_ops = {
789 .get_settings = dnet_get_settings,
790 .set_settings = dnet_set_settings,
791 .get_drvinfo = dnet_get_drvinfo,
792 .get_link = ethtool_op_get_link,
793 .get_ts_info = ethtool_op_get_ts_info,
796 static const struct net_device_ops dnet_netdev_ops = {
797 .ndo_open = dnet_open,
798 .ndo_stop = dnet_close,
799 .ndo_get_stats = dnet_get_stats,
800 .ndo_start_xmit = dnet_start_xmit,
801 .ndo_do_ioctl = dnet_ioctl,
802 .ndo_set_mac_address = eth_mac_addr,
803 .ndo_validate_addr = eth_validate_addr,
804 .ndo_change_mtu = eth_change_mtu,
807 static int dnet_probe(struct platform_device *pdev)
809 struct resource *res;
810 struct net_device *dev;
812 struct phy_device *phydev;
816 irq = platform_get_irq(pdev, 0);
818 dev = alloc_etherdev(sizeof(*bp));
822 /* TODO: Actually, we have some interesting features... */
825 bp = netdev_priv(dev);
828 platform_set_drvdata(pdev, dev);
829 SET_NETDEV_DEV(dev, &pdev->dev);
831 spin_lock_init(&bp->lock);
833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 bp->regs = devm_ioremap_resource(&pdev->dev, res);
835 if (IS_ERR(bp->regs)) {
836 err = PTR_ERR(bp->regs);
837 goto err_out_free_dev;
841 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
843 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
845 goto err_out_free_dev;
848 dev->netdev_ops = &dnet_netdev_ops;
849 netif_napi_add(dev, &bp->napi, dnet_poll, 64);
850 dev->ethtool_ops = &dnet_ethtool_ops;
852 dev->base_addr = (unsigned long)bp->regs;
854 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
858 if (!is_valid_ether_addr(dev->dev_addr)) {
859 /* choose a random ethernet address */
860 eth_hw_addr_random(dev);
861 __dnet_set_hwaddr(bp);
864 err = register_netdev(dev);
866 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
867 goto err_out_free_irq;
870 /* register the PHY board fixup (for Marvell 88E1111) */
871 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
872 dnet_phy_marvell_fixup);
873 /* we can live without it, so just issue a warning */
875 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
877 err = dnet_mii_init(bp);
879 goto err_out_unregister_netdev;
881 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
882 bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr);
883 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
884 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
885 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
886 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
887 (bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
888 phydev = bp->phy_dev;
889 dev_info(&pdev->dev, "attached PHY driver [%s] "
890 "(mii_bus:phy_addr=%s, irq=%d)\n",
891 phydev->drv->name, phydev_name(phydev), phydev->irq);
895 err_out_unregister_netdev:
896 unregister_netdev(dev);
898 free_irq(dev->irq, dev);
904 static int dnet_remove(struct platform_device *pdev)
907 struct net_device *dev;
910 dev = platform_get_drvdata(pdev);
913 bp = netdev_priv(dev);
915 phy_disconnect(bp->phy_dev);
916 mdiobus_unregister(bp->mii_bus);
917 mdiobus_free(bp->mii_bus);
918 unregister_netdev(dev);
919 free_irq(dev->irq, dev);
926 static struct platform_driver dnet_driver = {
928 .remove = dnet_remove,
934 module_platform_driver(dnet_driver);
936 MODULE_LICENSE("GPL");
937 MODULE_DESCRIPTION("Dave DNET Ethernet driver");
938 MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
939 "Matteo Vit <matteo.vit@dave.eu>");