2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/delay.h>
27 #include <linux/if_vlan.h>
28 #include <linux/workqueue.h>
29 #include <linux/interrupt.h>
30 #include <linux/firmware.h>
31 #include <linux/slab.h>
32 #include <linux/u64_stats_sync.h>
36 #define DRV_VER "4.2.220u"
37 #define DRV_NAME "be2net"
38 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
39 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
40 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
41 #define OC_NAME_BE OC_NAME "(be3)"
42 #define OC_NAME_LANCER OC_NAME "(Lancer)"
43 #define OC_NAME_SH OC_NAME "(Skyhawk)"
44 #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
46 #define BE_VENDOR_ID 0x19a2
47 #define EMULEX_VENDOR_ID 0x10df
48 #define BE_DEVICE_ID1 0x211
49 #define BE_DEVICE_ID2 0x221
50 #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
51 #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
52 #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
53 #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
54 #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
55 #define OC_SUBSYS_DEVICE_ID1 0xE602
56 #define OC_SUBSYS_DEVICE_ID2 0xE642
57 #define OC_SUBSYS_DEVICE_ID3 0xE612
58 #define OC_SUBSYS_DEVICE_ID4 0xE652
60 static inline char *nic_name(struct pci_dev *pdev)
62 switch (pdev->device) {
69 return OC_NAME_LANCER;
79 /* Number of bytes of an RX frame that are copied to skb->data */
80 #define BE_HDR_LEN ((u16) 64)
81 /* allocate extra space to allow tunneling decapsulation without head reallocation */
82 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
84 #define BE_MAX_JUMBO_FRAME_SIZE 9018
85 #define BE_MIN_MTU 256
87 #define BE_NUM_VLANS_SUPPORTED 64
88 #define BE_MAX_EQD 96u
89 #define BE_MAX_TX_FRAG_COUNT 30
91 #define EVNT_Q_LEN 1024
93 #define TX_CQ_LEN 1024
94 #define RX_Q_LEN 1024 /* Does not support any other value */
95 #define RX_CQ_LEN 1024
96 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
97 #define MCC_CQ_LEN 256
99 #define BE3_MAX_RSS_QS 8
100 #define BE2_MAX_RSS_QS 4
101 #define MAX_RSS_QS BE3_MAX_RSS_QS
102 #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
105 #define MAX_MSIX_VECTORS MAX_RSS_QS
106 #define BE_TX_BUDGET 256
107 #define BE_NAPI_WEIGHT 64
108 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
109 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
111 #define FW_VER_LEN 32
119 struct be_queue_info {
120 struct be_dma_mem dma_mem;
122 u16 entry_size; /* Size of an element in the queue */
126 atomic_t used; /* Number of valid elements in the queue */
129 static inline u32 MODULO(u16 val, u16 limit)
131 BUG_ON(limit & (limit - 1));
132 return val & (limit - 1);
135 static inline void index_adv(u16 *index, u16 val, u16 limit)
137 *index = MODULO((*index + val), limit);
140 static inline void index_inc(u16 *index, u16 limit)
142 *index = MODULO((*index + 1), limit);
145 static inline void *queue_head_node(struct be_queue_info *q)
147 return q->dma_mem.va + q->head * q->entry_size;
150 static inline void *queue_tail_node(struct be_queue_info *q)
152 return q->dma_mem.va + q->tail * q->entry_size;
155 static inline void *queue_index_node(struct be_queue_info *q, u16 index)
157 return q->dma_mem.va + index * q->entry_size;
160 static inline void queue_head_inc(struct be_queue_info *q)
162 index_inc(&q->head, q->len);
165 static inline void index_dec(u16 *index, u16 limit)
167 *index = MODULO((*index - 1), limit);
170 static inline void queue_tail_inc(struct be_queue_info *q)
172 index_inc(&q->tail, q->len);
176 struct be_queue_info q;
179 /* Adaptive interrupt coalescing (AIC) info */
181 u32 min_eqd; /* in usecs */
182 u32 max_eqd; /* in usecs */
183 u32 eqd; /* configured val when aic is off */
184 u32 cur_eqd; /* in usecs */
186 u8 idx; /* array index */
188 struct napi_struct napi;
189 struct be_adapter *adapter;
190 } ____cacheline_aligned_in_smp;
193 struct be_queue_info q;
194 struct be_queue_info cq;
206 struct u64_stats_sync sync;
207 struct u64_stats_sync sync_compl;
211 struct be_queue_info q;
212 struct be_queue_info cq;
213 /* Remember the skbs that were transmitted */
214 struct sk_buff *sent_skb_list[TX_Q_LEN];
215 struct be_tx_stats stats;
216 } ____cacheline_aligned_in_smp;
218 /* Struct to remember the pages posted for rx frags */
219 struct be_rx_page_info {
221 DEFINE_DMA_UNMAP_ADDR(bus);
231 u32 rx_drops_no_skbs; /* skb allocation errors */
232 u32 rx_drops_no_frags; /* HW has no fetched frags */
233 u32 rx_post_fail; /* page post alloc failures */
236 u32 rx_compl_err; /* completions with err set */
237 u32 rx_pps; /* pkts per second */
238 struct u64_stats_sync sync;
241 struct be_rx_compl_info {
261 struct be_adapter *adapter;
262 struct be_queue_info q;
263 struct be_queue_info cq;
264 struct be_rx_compl_info rxcp;
265 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
266 struct be_rx_stats stats;
268 bool rx_post_starved; /* Zero rx frags have been posted to BE */
269 } ____cacheline_aligned_in_smp;
271 struct be_drv_stats {
272 u32 be_on_die_temperature;
274 u32 rx_drops_no_pbuf;
275 u32 rx_drops_no_txpb;
276 u32 rx_drops_no_erx_descr;
277 u32 rx_drops_no_tpre_descr;
278 u32 rx_drops_too_many_frags;
279 u32 forwarded_packets;
282 u32 rx_alignment_symbol_errors;
284 u32 rx_priority_pause_frames;
285 u32 rx_control_frames;
286 u32 rx_in_range_errors;
287 u32 rx_out_range_errors;
288 u32 rx_frame_too_long;
289 u32 rx_address_mismatch_drops;
290 u32 rx_dropped_too_small;
291 u32 rx_dropped_too_short;
292 u32 rx_dropped_header_too_small;
293 u32 rx_dropped_tcp_length;
295 u32 rx_ip_checksum_errs;
296 u32 rx_tcp_checksum_errs;
297 u32 rx_udp_checksum_errs;
299 u32 tx_priority_pauseframes;
300 u32 tx_controlframes;
301 u32 rxpp_fifo_overflow_drop;
302 u32 rx_input_fifo_overflow_drop;
303 u32 pmem_fifo_overflow_drop;
308 unsigned char mac_addr[ETH_ALEN];
321 #define BE_FLAGS_LINK_STATUS_INIT 1
322 #define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
323 #define BE_UC_PMAC_COUNT 30
324 #define BE_VF_UC_PMAC_COUNT 2
334 u16 auto_speeds_supported;
335 u16 fixed_speeds_supported;
337 int forced_port_speed;
344 struct pci_dev *pdev;
345 struct net_device *netdev;
348 u8 __iomem *db; /* Door Bell */
350 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
351 struct be_dma_mem mbox_mem;
352 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
353 * is stored for freeing purpose */
354 struct be_dma_mem mbox_mem_alloced;
356 struct be_mcc_obj mcc_obj;
357 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
358 spinlock_t mcc_cq_lock;
362 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
363 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
368 struct be_tx_obj tx_obj[MAX_TX_QS];
372 struct be_rx_obj rx_obj[MAX_RX_QS];
373 u32 big_page_size; /* Compounded page size shared by rx wrbs */
376 struct be_drv_stats drv_stats;
379 u16 max_vlans; /* Number of vlans supported */
380 u8 vlan_tag[VLAN_N_VID];
381 u8 vlan_prio_bmap; /* Available Priority BitMap */
382 u16 recommended_prio; /* Recommended Priority */
383 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
385 struct be_dma_mem stats_cmd;
386 /* Work queue used to perform periodic tasks like getting statistics */
387 struct delayed_work work;
391 /* Ethtool knobs and info */
392 char fw_ver[FW_VER_LEN];
393 int if_handle; /* Used to configure filtering */
394 u32 *pmac_id; /* MAC addr handle used by BE card */
395 u32 beacon_state; /* for set_phys_id */
404 u32 rx_fc; /* Rx flow control */
405 u32 tx_fc; /* Tx flow control */
407 u8 generation; /* BladeEngine ASIC generation */
409 struct completion flash_compl;
411 u32 num_vfs; /* Number of VFs provisioned by PF driver */
412 u32 dev_num_vfs; /* Number of VFs supported by HW */
414 struct be_vf_cfg *vf_cfg;
422 u32 max_pmac_cnt; /* Max secondary UC MACs programmable */
423 u32 uc_macs; /* Count of secondary UC MAC programmed */
427 #define be_physfn(adapter) (!adapter->virtfn)
428 #define sriov_enabled(adapter) (adapter->num_vfs > 0)
429 #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
431 #define for_all_vfs(adapter, vf_cfg, i) \
432 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
435 /* BladeEngine Generation numbers */
441 #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \
442 (adapter->pdev->device == OC_DEVICE_ID4))
444 extern const struct ethtool_ops be_ethtool_ops;
446 #define msix_enabled(adapter) (adapter->num_msix_vec > 0)
447 #define num_irqs(adapter) (msix_enabled(adapter) ? \
448 adapter->num_msix_vec : 1)
449 #define tx_stats(txo) (&(txo)->stats)
450 #define rx_stats(rxo) (&(rxo)->stats)
452 /* The default RXQ is the last RXQ */
453 #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
455 #define for_all_rx_queues(adapter, rxo, i) \
456 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
459 /* Skip the default non-rss queue (last one)*/
460 #define for_all_rss_queues(adapter, rxo, i) \
461 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
464 #define for_all_tx_queues(adapter, txo, i) \
465 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
468 #define for_all_evt_queues(adapter, eqo, i) \
469 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
472 #define is_mcc_eqo(eqo) (eqo->idx == 0)
473 #define mcc_eqo(adapter) (&adapter->eq_obj[0])
475 #define PAGE_SHIFT_4K 12
476 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
478 /* Returns number of pages spanned by the data starting at the given addr */
479 #define PAGES_4K_SPANNED(_address, size) \
480 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
481 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
483 /* Returns bit offset within a DWORD of a bitfield */
484 #define AMAP_BIT_OFFSET(_struct, field) \
485 (((size_t)&(((_struct *)0)->field))%32)
487 /* Returns the bit mask of the field that is NOT shifted into location. */
488 static inline u32 amap_mask(u32 bitsize)
490 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
494 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
496 u32 *dw = (u32 *) ptr + dw_offset;
497 *dw &= ~(mask << offset);
498 *dw |= (mask & value) << offset;
501 #define AMAP_SET_BITS(_struct, field, ptr, val) \
503 offsetof(_struct, field)/32, \
504 amap_mask(sizeof(((_struct *)0)->field)), \
505 AMAP_BIT_OFFSET(_struct, field), \
508 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
510 u32 *dw = (u32 *) ptr;
511 return mask & (*(dw + dw_offset) >> offset);
514 #define AMAP_GET_BITS(_struct, field, ptr) \
516 offsetof(_struct, field)/32, \
517 amap_mask(sizeof(((_struct *)0)->field)), \
518 AMAP_BIT_OFFSET(_struct, field))
520 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
521 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
522 static inline void swap_dws(void *wrb, int len)
528 *dw = cpu_to_le32(*dw);
532 #endif /* __BIG_ENDIAN */
535 static inline u8 is_tcp_pkt(struct sk_buff *skb)
539 if (ip_hdr(skb)->version == 4)
540 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
541 else if (ip_hdr(skb)->version == 6)
542 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
547 static inline u8 is_udp_pkt(struct sk_buff *skb)
551 if (ip_hdr(skb)->version == 4)
552 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
553 else if (ip_hdr(skb)->version == 6)
554 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
559 static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
563 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
565 mac[5] = (u8)(addr & 0xFF);
566 mac[4] = (u8)((addr >> 8) & 0xFF);
567 mac[3] = (u8)((addr >> 16) & 0xFF);
568 /* Use the OUI from the current MAC address */
569 memcpy(mac, adapter->netdev->dev_addr, 3);
572 static inline bool be_multi_rxq(const struct be_adapter *adapter)
574 return adapter->num_rx_qs > 1;
577 static inline bool be_error(struct be_adapter *adapter)
579 return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
582 static inline bool be_is_wol_excluded(struct be_adapter *adapter)
584 struct pci_dev *pdev = adapter->pdev;
586 if (!be_physfn(adapter))
589 switch (pdev->subsystem_device) {
590 case OC_SUBSYS_DEVICE_ID1:
591 case OC_SUBSYS_DEVICE_ID2:
592 case OC_SUBSYS_DEVICE_ID3:
593 case OC_SUBSYS_DEVICE_ID4:
600 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
602 extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
603 extern void be_parse_stats(struct be_adapter *adapter);
604 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
605 extern bool be_is_wol_supported(struct be_adapter *adapter);
606 extern bool be_pause_supported(struct be_adapter *adapter);
607 extern u32 be_get_fw_log_level(struct be_adapter *adapter);