2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 64;
24 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
26 return wrb->payload.embedded_payload;
29 static void be_mcc_notify(struct be_adapter *adapter)
31 struct be_queue_info *mccq = &adapter->mcc_obj.q;
34 if (be_error(adapter))
37 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
38 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
41 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
44 /* To check if valid bit is set, check the entire word as we don't know
45 * the endianness of the data (old entry is host endian while a new entry is
47 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
49 if (compl->flags != 0) {
50 compl->flags = le32_to_cpu(compl->flags);
51 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
58 /* Need to reset the entire word that houses the valid bit */
59 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
64 static int be_mcc_compl_process(struct be_adapter *adapter,
65 struct be_mcc_compl *compl)
67 u16 compl_status, extd_status;
69 /* Just swap the status to host endian; mcc tag is opaquely copied
71 be_dws_le_to_cpu(compl, 4);
73 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
74 CQE_STATUS_COMPL_MASK;
76 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
77 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
78 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
79 adapter->flash_status = compl_status;
80 complete(&adapter->flash_compl);
83 if (compl_status == MCC_STATUS_SUCCESS) {
84 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
85 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
86 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
87 be_parse_stats(adapter);
88 adapter->stats_cmd_sent = false;
91 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
92 struct be_mcc_wrb *mcc_wrb =
93 queue_index_node(&adapter->mcc_obj.q,
95 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
96 embedded_payload(mcc_wrb);
97 adapter->drv_stats.be_on_die_temperature =
98 resp->on_die_temperature;
101 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
102 be_get_temp_freq = 0;
104 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
105 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
108 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
109 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
110 "permitted to execute this cmd (opcode %d)\n",
113 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
114 CQE_STATUS_EXTD_MASK;
115 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
116 "status %d, extd-status %d\n",
117 compl->tag0, compl_status, extd_status);
124 /* Link state evt is a string of bytes; no need for endian swapping */
125 static void be_async_link_state_process(struct be_adapter *adapter,
126 struct be_async_event_link_state *evt)
128 /* When link status changes, link speed must be re-queried from FW */
129 adapter->link_speed = -1;
131 /* For the initial link status do not rely on the ASYNC event as
132 * it may not be received in some cases.
134 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
135 be_link_status_update(adapter, evt->port_link_status);
138 /* Grp5 CoS Priority evt */
139 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
140 struct be_async_event_grp5_cos_priority *evt)
143 adapter->vlan_prio_bmap = evt->available_priority_bmap;
144 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
145 adapter->recommended_prio =
146 evt->reco_default_priority << VLAN_PRIO_SHIFT;
150 /* Grp5 QOS Speed evt */
151 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
152 struct be_async_event_grp5_qos_link_speed *evt)
154 if (evt->physical_port == adapter->port_num) {
155 /* qos_link_speed is in units of 10 Mbps */
156 adapter->link_speed = evt->qos_link_speed * 10;
161 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
162 struct be_async_event_grp5_pvid_state *evt)
165 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
170 static void be_async_grp5_evt_process(struct be_adapter *adapter,
171 u32 trailer, struct be_mcc_compl *evt)
175 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
176 ASYNC_TRAILER_EVENT_TYPE_MASK;
178 switch (event_type) {
179 case ASYNC_EVENT_COS_PRIORITY:
180 be_async_grp5_cos_priority_process(adapter,
181 (struct be_async_event_grp5_cos_priority *)evt);
183 case ASYNC_EVENT_QOS_SPEED:
184 be_async_grp5_qos_speed_process(adapter,
185 (struct be_async_event_grp5_qos_link_speed *)evt);
187 case ASYNC_EVENT_PVID_STATE:
188 be_async_grp5_pvid_state_process(adapter,
189 (struct be_async_event_grp5_pvid_state *)evt);
192 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
197 static inline bool is_link_state_evt(u32 trailer)
199 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
200 ASYNC_TRAILER_EVENT_CODE_MASK) ==
201 ASYNC_EVENT_CODE_LINK_STATE;
204 static inline bool is_grp5_evt(u32 trailer)
206 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
207 ASYNC_TRAILER_EVENT_CODE_MASK) ==
208 ASYNC_EVENT_CODE_GRP_5);
211 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
213 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
214 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
216 if (be_mcc_compl_is_new(compl)) {
217 queue_tail_inc(mcc_cq);
223 void be_async_mcc_enable(struct be_adapter *adapter)
225 spin_lock_bh(&adapter->mcc_cq_lock);
227 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
228 adapter->mcc_obj.rearm_cq = true;
230 spin_unlock_bh(&adapter->mcc_cq_lock);
233 void be_async_mcc_disable(struct be_adapter *adapter)
235 adapter->mcc_obj.rearm_cq = false;
238 int be_process_mcc(struct be_adapter *adapter, int *status)
240 struct be_mcc_compl *compl;
242 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
244 spin_lock_bh(&adapter->mcc_cq_lock);
245 while ((compl = be_mcc_compl_get(adapter))) {
246 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
247 /* Interpret flags as an async trailer */
248 if (is_link_state_evt(compl->flags))
249 be_async_link_state_process(adapter,
250 (struct be_async_event_link_state *) compl);
251 else if (is_grp5_evt(compl->flags))
252 be_async_grp5_evt_process(adapter,
253 compl->flags, compl);
254 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
255 *status = be_mcc_compl_process(adapter, compl);
256 atomic_dec(&mcc_obj->q.used);
258 be_mcc_compl_use(compl);
262 spin_unlock_bh(&adapter->mcc_cq_lock);
266 /* Wait till no more pending mcc requests are present */
267 static int be_mcc_wait_compl(struct be_adapter *adapter)
269 #define mcc_timeout 120000 /* 12s timeout */
270 int i, num, status = 0;
271 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
273 for (i = 0; i < mcc_timeout; i++) {
274 if (be_error(adapter))
277 num = be_process_mcc(adapter, &status);
279 be_cq_notify(adapter, mcc_obj->cq.id,
280 mcc_obj->rearm_cq, num);
282 if (atomic_read(&mcc_obj->q.used) == 0)
286 if (i == mcc_timeout) {
287 dev_err(&adapter->pdev->dev, "FW not responding\n");
288 adapter->fw_timeout = true;
294 /* Notify MCC requests and wait for completion */
295 static int be_mcc_notify_wait(struct be_adapter *adapter)
297 be_mcc_notify(adapter);
298 return be_mcc_wait_compl(adapter);
301 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
307 if (be_error(adapter))
310 ready = ioread32(db);
311 if (ready == 0xffffffff)
314 ready &= MPU_MAILBOX_DB_RDY_MASK;
319 dev_err(&adapter->pdev->dev, "FW not responding\n");
320 adapter->fw_timeout = true;
321 be_detect_dump_ue(adapter);
333 * Insert the mailbox address into the doorbell in two steps
334 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
336 static int be_mbox_notify_wait(struct be_adapter *adapter)
340 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
341 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
342 struct be_mcc_mailbox *mbox = mbox_mem->va;
343 struct be_mcc_compl *compl = &mbox->compl;
345 /* wait for ready to be set */
346 status = be_mbox_db_ready_wait(adapter, db);
350 val |= MPU_MAILBOX_DB_HI_MASK;
351 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
352 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
355 /* wait for ready to be set */
356 status = be_mbox_db_ready_wait(adapter, db);
361 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
362 val |= (u32)(mbox_mem->dma >> 4) << 2;
365 status = be_mbox_db_ready_wait(adapter, db);
369 /* A cq entry has been made now */
370 if (be_mcc_compl_is_new(compl)) {
371 status = be_mcc_compl_process(adapter, &mbox->compl);
372 be_mcc_compl_use(compl);
376 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
382 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
386 if (lancer_chip(adapter))
387 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
389 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
391 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
392 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
398 int be_cmd_POST(struct be_adapter *adapter)
401 int status, timeout = 0;
402 struct device *dev = &adapter->pdev->dev;
405 status = be_POST_stage_get(adapter, &stage);
407 dev_err(dev, "POST error; stage=0x%x\n", stage);
409 } else if (stage != POST_STAGE_ARMFW_RDY) {
410 if (msleep_interruptible(2000)) {
411 dev_err(dev, "Waiting for POST aborted\n");
418 } while (timeout < 60);
420 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
425 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
427 return &wrb->payload.sgl[0];
431 /* Don't touch the hdr after it's prepared */
432 /* mem will be NULL for embedded commands */
433 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
434 u8 subsystem, u8 opcode, int cmd_len,
435 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
439 req_hdr->opcode = opcode;
440 req_hdr->subsystem = subsystem;
441 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
442 req_hdr->version = 0;
445 wrb->tag1 = subsystem;
446 wrb->payload_length = cmd_len;
448 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
449 MCC_WRB_SGE_CNT_SHIFT;
450 sge = nonembedded_sgl(wrb);
451 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
452 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
453 sge->len = cpu_to_le32(mem->size);
455 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
456 be_dws_cpu_to_le(wrb, 8);
459 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
460 struct be_dma_mem *mem)
462 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
463 u64 dma = (u64)mem->dma;
465 for (i = 0; i < buf_pages; i++) {
466 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
467 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
472 /* Converts interrupt delay in microseconds to multiplier value */
473 static u32 eq_delay_to_mult(u32 usec_delay)
475 #define MAX_INTR_RATE 651042
476 const u32 round = 10;
482 u32 interrupt_rate = 1000000 / usec_delay;
483 /* Max delay, corresponding to the lowest interrupt rate */
484 if (interrupt_rate == 0)
487 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
488 multiplier /= interrupt_rate;
489 /* Round the multiplier to the closest value.*/
490 multiplier = (multiplier + round/2) / round;
491 multiplier = min(multiplier, (u32)1023);
497 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
499 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
500 struct be_mcc_wrb *wrb
501 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
502 memset(wrb, 0, sizeof(*wrb));
506 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
508 struct be_queue_info *mccq = &adapter->mcc_obj.q;
509 struct be_mcc_wrb *wrb;
511 if (atomic_read(&mccq->used) >= mccq->len) {
512 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
516 wrb = queue_head_node(mccq);
517 queue_head_inc(mccq);
518 atomic_inc(&mccq->used);
519 memset(wrb, 0, sizeof(*wrb));
523 /* Tell fw we're about to start firing cmds by writing a
524 * special pattern across the wrb hdr; uses mbox
526 int be_cmd_fw_init(struct be_adapter *adapter)
531 if (mutex_lock_interruptible(&adapter->mbox_lock))
534 wrb = (u8 *)wrb_from_mbox(adapter);
544 status = be_mbox_notify_wait(adapter);
546 mutex_unlock(&adapter->mbox_lock);
550 /* Tell fw we're done with firing cmds by writing a
551 * special pattern across the wrb hdr; uses mbox
553 int be_cmd_fw_clean(struct be_adapter *adapter)
558 if (mutex_lock_interruptible(&adapter->mbox_lock))
561 wrb = (u8 *)wrb_from_mbox(adapter);
571 status = be_mbox_notify_wait(adapter);
573 mutex_unlock(&adapter->mbox_lock);
576 int be_cmd_eq_create(struct be_adapter *adapter,
577 struct be_queue_info *eq, int eq_delay)
579 struct be_mcc_wrb *wrb;
580 struct be_cmd_req_eq_create *req;
581 struct be_dma_mem *q_mem = &eq->dma_mem;
584 if (mutex_lock_interruptible(&adapter->mbox_lock))
587 wrb = wrb_from_mbox(adapter);
588 req = embedded_payload(wrb);
590 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
591 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
593 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
595 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
597 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
598 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
599 __ilog2_u32(eq->len/256));
600 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
601 eq_delay_to_mult(eq_delay));
602 be_dws_cpu_to_le(req->context, sizeof(req->context));
604 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
606 status = be_mbox_notify_wait(adapter);
608 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
609 eq->id = le16_to_cpu(resp->eq_id);
613 mutex_unlock(&adapter->mbox_lock);
618 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
619 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
621 struct be_mcc_wrb *wrb;
622 struct be_cmd_req_mac_query *req;
625 spin_lock_bh(&adapter->mcc_lock);
627 wrb = wrb_from_mccq(adapter);
632 req = embedded_payload(wrb);
634 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
635 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
640 req->if_id = cpu_to_le16((u16) if_handle);
641 req->pmac_id = cpu_to_le32(pmac_id);
645 status = be_mcc_notify_wait(adapter);
647 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
648 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
652 spin_unlock_bh(&adapter->mcc_lock);
656 /* Uses synchronous MCCQ */
657 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
658 u32 if_id, u32 *pmac_id, u32 domain)
660 struct be_mcc_wrb *wrb;
661 struct be_cmd_req_pmac_add *req;
664 spin_lock_bh(&adapter->mcc_lock);
666 wrb = wrb_from_mccq(adapter);
671 req = embedded_payload(wrb);
673 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
674 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
676 req->hdr.domain = domain;
677 req->if_id = cpu_to_le32(if_id);
678 memcpy(req->mac_address, mac_addr, ETH_ALEN);
680 status = be_mcc_notify_wait(adapter);
682 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
683 *pmac_id = le32_to_cpu(resp->pmac_id);
687 spin_unlock_bh(&adapter->mcc_lock);
689 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
695 /* Uses synchronous MCCQ */
696 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
698 struct be_mcc_wrb *wrb;
699 struct be_cmd_req_pmac_del *req;
705 spin_lock_bh(&adapter->mcc_lock);
707 wrb = wrb_from_mccq(adapter);
712 req = embedded_payload(wrb);
714 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
715 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
717 req->hdr.domain = dom;
718 req->if_id = cpu_to_le32(if_id);
719 req->pmac_id = cpu_to_le32(pmac_id);
721 status = be_mcc_notify_wait(adapter);
724 spin_unlock_bh(&adapter->mcc_lock);
729 int be_cmd_cq_create(struct be_adapter *adapter,
730 struct be_queue_info *cq, struct be_queue_info *eq,
731 bool sol_evts, bool no_delay, int coalesce_wm)
733 struct be_mcc_wrb *wrb;
734 struct be_cmd_req_cq_create *req;
735 struct be_dma_mem *q_mem = &cq->dma_mem;
739 if (mutex_lock_interruptible(&adapter->mbox_lock))
742 wrb = wrb_from_mbox(adapter);
743 req = embedded_payload(wrb);
744 ctxt = &req->context;
746 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
747 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
749 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
750 if (lancer_chip(adapter)) {
751 req->hdr.version = 2;
752 req->page_size = 1; /* 1 for 4K */
753 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
755 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
756 __ilog2_u32(cq->len/256));
757 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
758 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
760 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
762 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
764 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
766 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
768 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
769 __ilog2_u32(cq->len/256));
770 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
771 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
773 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
774 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
775 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
778 be_dws_cpu_to_le(ctxt, sizeof(req->context));
780 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
782 status = be_mbox_notify_wait(adapter);
784 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
785 cq->id = le16_to_cpu(resp->cq_id);
789 mutex_unlock(&adapter->mbox_lock);
794 static u32 be_encoded_q_len(int q_len)
796 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
797 if (len_encoded == 16)
802 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
803 struct be_queue_info *mccq,
804 struct be_queue_info *cq)
806 struct be_mcc_wrb *wrb;
807 struct be_cmd_req_mcc_ext_create *req;
808 struct be_dma_mem *q_mem = &mccq->dma_mem;
812 if (mutex_lock_interruptible(&adapter->mbox_lock))
815 wrb = wrb_from_mbox(adapter);
816 req = embedded_payload(wrb);
817 ctxt = &req->context;
819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
820 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
822 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
823 if (lancer_chip(adapter)) {
824 req->hdr.version = 1;
825 req->cq_id = cpu_to_le16(cq->id);
827 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
828 be_encoded_q_len(mccq->len));
829 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
830 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
832 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
836 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
837 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
838 be_encoded_q_len(mccq->len));
839 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
842 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
843 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
844 be_dws_cpu_to_le(ctxt, sizeof(req->context));
846 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
848 status = be_mbox_notify_wait(adapter);
850 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
851 mccq->id = le16_to_cpu(resp->id);
852 mccq->created = true;
854 mutex_unlock(&adapter->mbox_lock);
859 int be_cmd_mccq_org_create(struct be_adapter *adapter,
860 struct be_queue_info *mccq,
861 struct be_queue_info *cq)
863 struct be_mcc_wrb *wrb;
864 struct be_cmd_req_mcc_create *req;
865 struct be_dma_mem *q_mem = &mccq->dma_mem;
869 if (mutex_lock_interruptible(&adapter->mbox_lock))
872 wrb = wrb_from_mbox(adapter);
873 req = embedded_payload(wrb);
874 ctxt = &req->context;
876 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
877 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
879 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
881 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
882 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
883 be_encoded_q_len(mccq->len));
884 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
886 be_dws_cpu_to_le(ctxt, sizeof(req->context));
888 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
890 status = be_mbox_notify_wait(adapter);
892 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
893 mccq->id = le16_to_cpu(resp->id);
894 mccq->created = true;
897 mutex_unlock(&adapter->mbox_lock);
901 int be_cmd_mccq_create(struct be_adapter *adapter,
902 struct be_queue_info *mccq,
903 struct be_queue_info *cq)
907 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
908 if (status && !lancer_chip(adapter)) {
909 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
910 "or newer to avoid conflicting priorities between NIC "
912 status = be_cmd_mccq_org_create(adapter, mccq, cq);
917 int be_cmd_txq_create(struct be_adapter *adapter,
918 struct be_queue_info *txq,
919 struct be_queue_info *cq)
921 struct be_mcc_wrb *wrb;
922 struct be_cmd_req_eth_tx_create *req;
923 struct be_dma_mem *q_mem = &txq->dma_mem;
927 spin_lock_bh(&adapter->mcc_lock);
929 wrb = wrb_from_mccq(adapter);
935 req = embedded_payload(wrb);
936 ctxt = &req->context;
938 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
939 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
941 if (lancer_chip(adapter)) {
942 req->hdr.version = 1;
943 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
947 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
948 req->ulp_num = BE_ULP1_NUM;
949 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
951 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
952 be_encoded_q_len(txq->len));
953 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
954 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
956 be_dws_cpu_to_le(ctxt, sizeof(req->context));
958 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
960 status = be_mcc_notify_wait(adapter);
962 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
963 txq->id = le16_to_cpu(resp->cid);
968 spin_unlock_bh(&adapter->mcc_lock);
974 int be_cmd_rxq_create(struct be_adapter *adapter,
975 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
976 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
978 struct be_mcc_wrb *wrb;
979 struct be_cmd_req_eth_rx_create *req;
980 struct be_dma_mem *q_mem = &rxq->dma_mem;
983 spin_lock_bh(&adapter->mcc_lock);
985 wrb = wrb_from_mccq(adapter);
990 req = embedded_payload(wrb);
992 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
993 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
995 req->cq_id = cpu_to_le16(cq_id);
996 req->frag_size = fls(frag_size) - 1;
998 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
999 req->interface_id = cpu_to_le32(if_id);
1000 req->max_frame_size = cpu_to_le16(max_frame_size);
1001 req->rss_queue = cpu_to_le32(rss);
1003 status = be_mcc_notify_wait(adapter);
1005 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1006 rxq->id = le16_to_cpu(resp->id);
1007 rxq->created = true;
1008 *rss_id = resp->rss_id;
1012 spin_unlock_bh(&adapter->mcc_lock);
1016 /* Generic destroyer function for all types of queues
1019 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1022 struct be_mcc_wrb *wrb;
1023 struct be_cmd_req_q_destroy *req;
1024 u8 subsys = 0, opcode = 0;
1027 if (mutex_lock_interruptible(&adapter->mbox_lock))
1030 wrb = wrb_from_mbox(adapter);
1031 req = embedded_payload(wrb);
1033 switch (queue_type) {
1035 subsys = CMD_SUBSYSTEM_COMMON;
1036 opcode = OPCODE_COMMON_EQ_DESTROY;
1039 subsys = CMD_SUBSYSTEM_COMMON;
1040 opcode = OPCODE_COMMON_CQ_DESTROY;
1043 subsys = CMD_SUBSYSTEM_ETH;
1044 opcode = OPCODE_ETH_TX_DESTROY;
1047 subsys = CMD_SUBSYSTEM_ETH;
1048 opcode = OPCODE_ETH_RX_DESTROY;
1051 subsys = CMD_SUBSYSTEM_COMMON;
1052 opcode = OPCODE_COMMON_MCC_DESTROY;
1058 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1060 req->id = cpu_to_le16(q->id);
1062 status = be_mbox_notify_wait(adapter);
1066 mutex_unlock(&adapter->mbox_lock);
1071 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1073 struct be_mcc_wrb *wrb;
1074 struct be_cmd_req_q_destroy *req;
1077 spin_lock_bh(&adapter->mcc_lock);
1079 wrb = wrb_from_mccq(adapter);
1084 req = embedded_payload(wrb);
1086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1087 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1088 req->id = cpu_to_le16(q->id);
1090 status = be_mcc_notify_wait(adapter);
1095 spin_unlock_bh(&adapter->mcc_lock);
1099 /* Create an rx filtering policy configuration on an i/f
1102 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1103 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
1105 struct be_mcc_wrb *wrb;
1106 struct be_cmd_req_if_create *req;
1109 spin_lock_bh(&adapter->mcc_lock);
1111 wrb = wrb_from_mccq(adapter);
1116 req = embedded_payload(wrb);
1118 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1119 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1120 req->hdr.domain = domain;
1121 req->capability_flags = cpu_to_le32(cap_flags);
1122 req->enable_flags = cpu_to_le32(en_flags);
1124 memcpy(req->mac_addr, mac, ETH_ALEN);
1126 req->pmac_invalid = true;
1128 status = be_mcc_notify_wait(adapter);
1130 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1131 *if_handle = le32_to_cpu(resp->interface_id);
1133 *pmac_id = le32_to_cpu(resp->pmac_id);
1137 spin_unlock_bh(&adapter->mcc_lock);
1142 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1144 struct be_mcc_wrb *wrb;
1145 struct be_cmd_req_if_destroy *req;
1148 if (interface_id == -1)
1151 spin_lock_bh(&adapter->mcc_lock);
1153 wrb = wrb_from_mccq(adapter);
1158 req = embedded_payload(wrb);
1160 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1162 req->hdr.domain = domain;
1163 req->interface_id = cpu_to_le32(interface_id);
1165 status = be_mcc_notify_wait(adapter);
1167 spin_unlock_bh(&adapter->mcc_lock);
1171 /* Get stats is a non embedded command: the request is not embedded inside
1172 * WRB but is a separate dma memory block
1173 * Uses asynchronous MCC
1175 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1177 struct be_mcc_wrb *wrb;
1178 struct be_cmd_req_hdr *hdr;
1181 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1182 be_cmd_get_die_temperature(adapter);
1184 spin_lock_bh(&adapter->mcc_lock);
1186 wrb = wrb_from_mccq(adapter);
1191 hdr = nonemb_cmd->va;
1193 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1194 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1196 if (adapter->generation == BE_GEN3)
1199 be_mcc_notify(adapter);
1200 adapter->stats_cmd_sent = true;
1203 spin_unlock_bh(&adapter->mcc_lock);
1208 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209 struct be_dma_mem *nonemb_cmd)
1212 struct be_mcc_wrb *wrb;
1213 struct lancer_cmd_req_pport_stats *req;
1216 spin_lock_bh(&adapter->mcc_lock);
1218 wrb = wrb_from_mccq(adapter);
1223 req = nonemb_cmd->va;
1225 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1226 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1229 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1230 req->cmd_params.params.reset_stats = 0;
1232 be_mcc_notify(adapter);
1233 adapter->stats_cmd_sent = true;
1236 spin_unlock_bh(&adapter->mcc_lock);
1240 /* Uses synchronous mcc */
1241 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1242 u16 *link_speed, u8 *link_status, u32 dom)
1244 struct be_mcc_wrb *wrb;
1245 struct be_cmd_req_link_status *req;
1248 spin_lock_bh(&adapter->mcc_lock);
1251 *link_status = LINK_DOWN;
1253 wrb = wrb_from_mccq(adapter);
1258 req = embedded_payload(wrb);
1260 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1261 req->hdr.version = 1;
1263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1264 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1266 status = be_mcc_notify_wait(adapter);
1268 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1269 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1271 *link_speed = le16_to_cpu(resp->link_speed);
1273 *mac_speed = resp->mac_speed;
1276 *link_status = resp->logical_link_status;
1280 spin_unlock_bh(&adapter->mcc_lock);
1284 /* Uses synchronous mcc */
1285 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1287 struct be_mcc_wrb *wrb;
1288 struct be_cmd_req_get_cntl_addnl_attribs *req;
1292 spin_lock_bh(&adapter->mcc_lock);
1294 mccq_index = adapter->mcc_obj.q.head;
1296 wrb = wrb_from_mccq(adapter);
1301 req = embedded_payload(wrb);
1303 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1304 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1307 wrb->tag1 = mccq_index;
1309 be_mcc_notify(adapter);
1312 spin_unlock_bh(&adapter->mcc_lock);
1316 /* Uses synchronous mcc */
1317 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1319 struct be_mcc_wrb *wrb;
1320 struct be_cmd_req_get_fat *req;
1323 spin_lock_bh(&adapter->mcc_lock);
1325 wrb = wrb_from_mccq(adapter);
1330 req = embedded_payload(wrb);
1332 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1333 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1334 req->fat_operation = cpu_to_le32(QUERY_FAT);
1335 status = be_mcc_notify_wait(adapter);
1337 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1338 if (log_size && resp->log_size)
1339 *log_size = le32_to_cpu(resp->log_size) -
1343 spin_unlock_bh(&adapter->mcc_lock);
1347 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1349 struct be_dma_mem get_fat_cmd;
1350 struct be_mcc_wrb *wrb;
1351 struct be_cmd_req_get_fat *req;
1352 u32 offset = 0, total_size, buf_size,
1353 log_offset = sizeof(u32), payload_len;
1359 total_size = buf_len;
1361 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1362 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1365 if (!get_fat_cmd.va) {
1367 dev_err(&adapter->pdev->dev,
1368 "Memory allocation failure while retrieving FAT data\n");
1372 spin_lock_bh(&adapter->mcc_lock);
1374 while (total_size) {
1375 buf_size = min(total_size, (u32)60*1024);
1376 total_size -= buf_size;
1378 wrb = wrb_from_mccq(adapter);
1383 req = get_fat_cmd.va;
1385 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1387 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1390 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1391 req->read_log_offset = cpu_to_le32(log_offset);
1392 req->read_log_length = cpu_to_le32(buf_size);
1393 req->data_buffer_size = cpu_to_le32(buf_size);
1395 status = be_mcc_notify_wait(adapter);
1397 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1398 memcpy(buf + offset,
1400 le32_to_cpu(resp->read_log_length));
1402 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1406 log_offset += buf_size;
1409 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1412 spin_unlock_bh(&adapter->mcc_lock);
1415 /* Uses synchronous mcc */
1416 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1419 struct be_mcc_wrb *wrb;
1420 struct be_cmd_req_get_fw_version *req;
1423 spin_lock_bh(&adapter->mcc_lock);
1425 wrb = wrb_from_mccq(adapter);
1431 req = embedded_payload(wrb);
1433 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1434 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1435 status = be_mcc_notify_wait(adapter);
1437 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1438 strcpy(fw_ver, resp->firmware_version_string);
1440 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1443 spin_unlock_bh(&adapter->mcc_lock);
1447 /* set the EQ delay interval of an EQ to specified value
1450 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1452 struct be_mcc_wrb *wrb;
1453 struct be_cmd_req_modify_eq_delay *req;
1456 spin_lock_bh(&adapter->mcc_lock);
1458 wrb = wrb_from_mccq(adapter);
1463 req = embedded_payload(wrb);
1465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1466 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1468 req->num_eq = cpu_to_le32(1);
1469 req->delay[0].eq_id = cpu_to_le32(eq_id);
1470 req->delay[0].phase = 0;
1471 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1473 be_mcc_notify(adapter);
1476 spin_unlock_bh(&adapter->mcc_lock);
1480 /* Uses sycnhronous mcc */
1481 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1482 u32 num, bool untagged, bool promiscuous)
1484 struct be_mcc_wrb *wrb;
1485 struct be_cmd_req_vlan_config *req;
1488 spin_lock_bh(&adapter->mcc_lock);
1490 wrb = wrb_from_mccq(adapter);
1495 req = embedded_payload(wrb);
1497 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1498 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1500 req->interface_id = if_id;
1501 req->promiscuous = promiscuous;
1502 req->untagged = untagged;
1503 req->num_vlan = num;
1505 memcpy(req->normal_vlan, vtag_array,
1506 req->num_vlan * sizeof(vtag_array[0]));
1509 status = be_mcc_notify_wait(adapter);
1512 spin_unlock_bh(&adapter->mcc_lock);
1516 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1518 struct be_mcc_wrb *wrb;
1519 struct be_dma_mem *mem = &adapter->rx_filter;
1520 struct be_cmd_req_rx_filter *req = mem->va;
1523 spin_lock_bh(&adapter->mcc_lock);
1525 wrb = wrb_from_mccq(adapter);
1530 memset(req, 0, sizeof(*req));
1531 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1532 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1535 req->if_id = cpu_to_le32(adapter->if_handle);
1536 if (flags & IFF_PROMISC) {
1537 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1538 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1540 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1541 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1542 } else if (flags & IFF_ALLMULTI) {
1543 req->if_flags_mask = req->if_flags =
1544 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1546 struct netdev_hw_addr *ha;
1549 req->if_flags_mask = req->if_flags =
1550 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1552 /* Reset mcast promisc mode if already set by setting mask
1553 * and not setting flags field
1555 req->if_flags_mask |=
1556 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1558 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1559 netdev_for_each_mc_addr(ha, adapter->netdev)
1560 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1563 status = be_mcc_notify_wait(adapter);
1565 spin_unlock_bh(&adapter->mcc_lock);
1569 /* Uses synchrounous mcc */
1570 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1572 struct be_mcc_wrb *wrb;
1573 struct be_cmd_req_set_flow_control *req;
1576 spin_lock_bh(&adapter->mcc_lock);
1578 wrb = wrb_from_mccq(adapter);
1583 req = embedded_payload(wrb);
1585 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1586 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1588 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1589 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1591 status = be_mcc_notify_wait(adapter);
1594 spin_unlock_bh(&adapter->mcc_lock);
1599 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1601 struct be_mcc_wrb *wrb;
1602 struct be_cmd_req_get_flow_control *req;
1605 spin_lock_bh(&adapter->mcc_lock);
1607 wrb = wrb_from_mccq(adapter);
1612 req = embedded_payload(wrb);
1614 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1615 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1617 status = be_mcc_notify_wait(adapter);
1619 struct be_cmd_resp_get_flow_control *resp =
1620 embedded_payload(wrb);
1621 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1622 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1626 spin_unlock_bh(&adapter->mcc_lock);
1631 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1632 u32 *mode, u32 *caps)
1634 struct be_mcc_wrb *wrb;
1635 struct be_cmd_req_query_fw_cfg *req;
1638 if (mutex_lock_interruptible(&adapter->mbox_lock))
1641 wrb = wrb_from_mbox(adapter);
1642 req = embedded_payload(wrb);
1644 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1645 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1647 status = be_mbox_notify_wait(adapter);
1649 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1650 *port_num = le32_to_cpu(resp->phys_port);
1651 *mode = le32_to_cpu(resp->function_mode);
1652 *caps = le32_to_cpu(resp->function_caps);
1655 mutex_unlock(&adapter->mbox_lock);
1660 int be_cmd_reset_function(struct be_adapter *adapter)
1662 struct be_mcc_wrb *wrb;
1663 struct be_cmd_req_hdr *req;
1666 if (mutex_lock_interruptible(&adapter->mbox_lock))
1669 wrb = wrb_from_mbox(adapter);
1670 req = embedded_payload(wrb);
1672 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1673 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1675 status = be_mbox_notify_wait(adapter);
1677 mutex_unlock(&adapter->mbox_lock);
1681 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1683 struct be_mcc_wrb *wrb;
1684 struct be_cmd_req_rss_config *req;
1685 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1686 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1687 0x3ea83c02, 0x4a110304};
1690 if (mutex_lock_interruptible(&adapter->mbox_lock))
1693 wrb = wrb_from_mbox(adapter);
1694 req = embedded_payload(wrb);
1696 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1697 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1699 req->if_id = cpu_to_le32(adapter->if_handle);
1700 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1701 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1702 memcpy(req->cpu_table, rsstable, table_size);
1703 memcpy(req->hash, myhash, sizeof(myhash));
1704 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1706 status = be_mbox_notify_wait(adapter);
1708 mutex_unlock(&adapter->mbox_lock);
1713 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1714 u8 bcn, u8 sts, u8 state)
1716 struct be_mcc_wrb *wrb;
1717 struct be_cmd_req_enable_disable_beacon *req;
1720 spin_lock_bh(&adapter->mcc_lock);
1722 wrb = wrb_from_mccq(adapter);
1727 req = embedded_payload(wrb);
1729 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1730 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1732 req->port_num = port_num;
1733 req->beacon_state = state;
1734 req->beacon_duration = bcn;
1735 req->status_duration = sts;
1737 status = be_mcc_notify_wait(adapter);
1740 spin_unlock_bh(&adapter->mcc_lock);
1745 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1747 struct be_mcc_wrb *wrb;
1748 struct be_cmd_req_get_beacon_state *req;
1751 spin_lock_bh(&adapter->mcc_lock);
1753 wrb = wrb_from_mccq(adapter);
1758 req = embedded_payload(wrb);
1760 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1761 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1763 req->port_num = port_num;
1765 status = be_mcc_notify_wait(adapter);
1767 struct be_cmd_resp_get_beacon_state *resp =
1768 embedded_payload(wrb);
1769 *state = resp->beacon_state;
1773 spin_unlock_bh(&adapter->mcc_lock);
1777 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1778 u32 data_size, u32 data_offset, const char *obj_name,
1779 u32 *data_written, u8 *addn_status)
1781 struct be_mcc_wrb *wrb;
1782 struct lancer_cmd_req_write_object *req;
1783 struct lancer_cmd_resp_write_object *resp;
1787 spin_lock_bh(&adapter->mcc_lock);
1788 adapter->flash_status = 0;
1790 wrb = wrb_from_mccq(adapter);
1796 req = embedded_payload(wrb);
1798 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1799 OPCODE_COMMON_WRITE_OBJECT,
1800 sizeof(struct lancer_cmd_req_write_object), wrb,
1803 ctxt = &req->context;
1804 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1805 write_length, ctxt, data_size);
1808 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1811 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1814 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1815 req->write_offset = cpu_to_le32(data_offset);
1816 strcpy(req->object_name, obj_name);
1817 req->descriptor_count = cpu_to_le32(1);
1818 req->buf_len = cpu_to_le32(data_size);
1819 req->addr_low = cpu_to_le32((cmd->dma +
1820 sizeof(struct lancer_cmd_req_write_object))
1822 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1823 sizeof(struct lancer_cmd_req_write_object)));
1825 be_mcc_notify(adapter);
1826 spin_unlock_bh(&adapter->mcc_lock);
1828 if (!wait_for_completion_timeout(&adapter->flash_compl,
1829 msecs_to_jiffies(12000)))
1832 status = adapter->flash_status;
1834 resp = embedded_payload(wrb);
1836 *data_written = le32_to_cpu(resp->actual_write_len);
1838 *addn_status = resp->additional_status;
1839 status = resp->status;
1845 spin_unlock_bh(&adapter->mcc_lock);
1849 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1850 u32 data_size, u32 data_offset, const char *obj_name,
1851 u32 *data_read, u32 *eof, u8 *addn_status)
1853 struct be_mcc_wrb *wrb;
1854 struct lancer_cmd_req_read_object *req;
1855 struct lancer_cmd_resp_read_object *resp;
1858 spin_lock_bh(&adapter->mcc_lock);
1860 wrb = wrb_from_mccq(adapter);
1866 req = embedded_payload(wrb);
1868 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1869 OPCODE_COMMON_READ_OBJECT,
1870 sizeof(struct lancer_cmd_req_read_object), wrb,
1873 req->desired_read_len = cpu_to_le32(data_size);
1874 req->read_offset = cpu_to_le32(data_offset);
1875 strcpy(req->object_name, obj_name);
1876 req->descriptor_count = cpu_to_le32(1);
1877 req->buf_len = cpu_to_le32(data_size);
1878 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1879 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1881 status = be_mcc_notify_wait(adapter);
1883 resp = embedded_payload(wrb);
1885 *data_read = le32_to_cpu(resp->actual_read_len);
1886 *eof = le32_to_cpu(resp->eof);
1888 *addn_status = resp->additional_status;
1892 spin_unlock_bh(&adapter->mcc_lock);
1896 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1897 u32 flash_type, u32 flash_opcode, u32 buf_size)
1899 struct be_mcc_wrb *wrb;
1900 struct be_cmd_write_flashrom *req;
1903 spin_lock_bh(&adapter->mcc_lock);
1904 adapter->flash_status = 0;
1906 wrb = wrb_from_mccq(adapter);
1913 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1914 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1916 req->params.op_type = cpu_to_le32(flash_type);
1917 req->params.op_code = cpu_to_le32(flash_opcode);
1918 req->params.data_buf_size = cpu_to_le32(buf_size);
1920 be_mcc_notify(adapter);
1921 spin_unlock_bh(&adapter->mcc_lock);
1923 if (!wait_for_completion_timeout(&adapter->flash_compl,
1924 msecs_to_jiffies(40000)))
1927 status = adapter->flash_status;
1932 spin_unlock_bh(&adapter->mcc_lock);
1936 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1939 struct be_mcc_wrb *wrb;
1940 struct be_cmd_write_flashrom *req;
1943 spin_lock_bh(&adapter->mcc_lock);
1945 wrb = wrb_from_mccq(adapter);
1950 req = embedded_payload(wrb);
1952 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1953 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
1955 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1956 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1957 req->params.offset = cpu_to_le32(offset);
1958 req->params.data_buf_size = cpu_to_le32(0x4);
1960 status = be_mcc_notify_wait(adapter);
1962 memcpy(flashed_crc, req->params.data_buf, 4);
1965 spin_unlock_bh(&adapter->mcc_lock);
1969 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1970 struct be_dma_mem *nonemb_cmd)
1972 struct be_mcc_wrb *wrb;
1973 struct be_cmd_req_acpi_wol_magic_config *req;
1976 spin_lock_bh(&adapter->mcc_lock);
1978 wrb = wrb_from_mccq(adapter);
1983 req = nonemb_cmd->va;
1985 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1986 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1988 memcpy(req->magic_mac, mac, ETH_ALEN);
1990 status = be_mcc_notify_wait(adapter);
1993 spin_unlock_bh(&adapter->mcc_lock);
1997 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1998 u8 loopback_type, u8 enable)
2000 struct be_mcc_wrb *wrb;
2001 struct be_cmd_req_set_lmode *req;
2004 spin_lock_bh(&adapter->mcc_lock);
2006 wrb = wrb_from_mccq(adapter);
2012 req = embedded_payload(wrb);
2014 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2015 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2018 req->src_port = port_num;
2019 req->dest_port = port_num;
2020 req->loopback_type = loopback_type;
2021 req->loopback_state = enable;
2023 status = be_mcc_notify_wait(adapter);
2025 spin_unlock_bh(&adapter->mcc_lock);
2029 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2030 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2032 struct be_mcc_wrb *wrb;
2033 struct be_cmd_req_loopback_test *req;
2036 spin_lock_bh(&adapter->mcc_lock);
2038 wrb = wrb_from_mccq(adapter);
2044 req = embedded_payload(wrb);
2046 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2047 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2048 req->hdr.timeout = cpu_to_le32(4);
2050 req->pattern = cpu_to_le64(pattern);
2051 req->src_port = cpu_to_le32(port_num);
2052 req->dest_port = cpu_to_le32(port_num);
2053 req->pkt_size = cpu_to_le32(pkt_size);
2054 req->num_pkts = cpu_to_le32(num_pkts);
2055 req->loopback_type = cpu_to_le32(loopback_type);
2057 status = be_mcc_notify_wait(adapter);
2059 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2060 status = le32_to_cpu(resp->status);
2064 spin_unlock_bh(&adapter->mcc_lock);
2068 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2069 u32 byte_cnt, struct be_dma_mem *cmd)
2071 struct be_mcc_wrb *wrb;
2072 struct be_cmd_req_ddrdma_test *req;
2076 spin_lock_bh(&adapter->mcc_lock);
2078 wrb = wrb_from_mccq(adapter);
2084 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2085 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2087 req->pattern = cpu_to_le64(pattern);
2088 req->byte_count = cpu_to_le32(byte_cnt);
2089 for (i = 0; i < byte_cnt; i++) {
2090 req->snd_buff[i] = (u8)(pattern >> (j*8));
2096 status = be_mcc_notify_wait(adapter);
2099 struct be_cmd_resp_ddrdma_test *resp;
2101 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2108 spin_unlock_bh(&adapter->mcc_lock);
2112 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2113 struct be_dma_mem *nonemb_cmd)
2115 struct be_mcc_wrb *wrb;
2116 struct be_cmd_req_seeprom_read *req;
2120 spin_lock_bh(&adapter->mcc_lock);
2122 wrb = wrb_from_mccq(adapter);
2127 req = nonemb_cmd->va;
2128 sge = nonembedded_sgl(wrb);
2130 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2131 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2134 status = be_mcc_notify_wait(adapter);
2137 spin_unlock_bh(&adapter->mcc_lock);
2141 int be_cmd_get_phy_info(struct be_adapter *adapter,
2142 struct be_phy_info *phy_info)
2144 struct be_mcc_wrb *wrb;
2145 struct be_cmd_req_get_phy_info *req;
2146 struct be_dma_mem cmd;
2149 spin_lock_bh(&adapter->mcc_lock);
2151 wrb = wrb_from_mccq(adapter);
2156 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2157 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2160 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2167 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2168 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2171 status = be_mcc_notify_wait(adapter);
2173 struct be_phy_info *resp_phy_info =
2174 cmd.va + sizeof(struct be_cmd_req_hdr);
2175 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2176 phy_info->interface_type =
2177 le16_to_cpu(resp_phy_info->interface_type);
2179 pci_free_consistent(adapter->pdev, cmd.size,
2182 spin_unlock_bh(&adapter->mcc_lock);
2186 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2188 struct be_mcc_wrb *wrb;
2189 struct be_cmd_req_set_qos *req;
2192 spin_lock_bh(&adapter->mcc_lock);
2194 wrb = wrb_from_mccq(adapter);
2200 req = embedded_payload(wrb);
2202 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2203 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2205 req->hdr.domain = domain;
2206 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2207 req->max_bps_nic = cpu_to_le32(bps);
2209 status = be_mcc_notify_wait(adapter);
2212 spin_unlock_bh(&adapter->mcc_lock);
2216 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2218 struct be_mcc_wrb *wrb;
2219 struct be_cmd_req_cntl_attribs *req;
2220 struct be_cmd_resp_cntl_attribs *resp;
2222 int payload_len = max(sizeof(*req), sizeof(*resp));
2223 struct mgmt_controller_attrib *attribs;
2224 struct be_dma_mem attribs_cmd;
2226 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2227 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2228 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2230 if (!attribs_cmd.va) {
2231 dev_err(&adapter->pdev->dev,
2232 "Memory allocation failure\n");
2236 if (mutex_lock_interruptible(&adapter->mbox_lock))
2239 wrb = wrb_from_mbox(adapter);
2244 req = attribs_cmd.va;
2246 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2247 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2250 status = be_mbox_notify_wait(adapter);
2252 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2253 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2257 mutex_unlock(&adapter->mbox_lock);
2258 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2264 int be_cmd_req_native_mode(struct be_adapter *adapter)
2266 struct be_mcc_wrb *wrb;
2267 struct be_cmd_req_set_func_cap *req;
2270 if (mutex_lock_interruptible(&adapter->mbox_lock))
2273 wrb = wrb_from_mbox(adapter);
2279 req = embedded_payload(wrb);
2281 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2282 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2284 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2285 CAPABILITY_BE3_NATIVE_ERX_API);
2286 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2288 status = be_mbox_notify_wait(adapter);
2290 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2291 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2292 CAPABILITY_BE3_NATIVE_ERX_API;
2295 mutex_unlock(&adapter->mbox_lock);
2299 /* Uses synchronous MCCQ */
2300 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain,
2303 struct be_mcc_wrb *wrb;
2304 struct be_cmd_req_get_mac_list *req;
2308 spin_lock_bh(&adapter->mcc_lock);
2310 wrb = wrb_from_mccq(adapter);
2315 req = embedded_payload(wrb);
2317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2318 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2321 req->hdr.domain = domain;
2323 status = be_mcc_notify_wait(adapter);
2325 struct be_cmd_resp_get_mac_list *resp =
2326 embedded_payload(wrb);
2328 u8 *ctxt = &resp->context[0][0];
2330 mac_count = resp->mac_count;
2331 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
2332 for (i = 0; i < mac_count; i++) {
2333 if (!AMAP_GET_BITS(struct amap_get_mac_list_context,
2335 *pmac_id = AMAP_GET_BITS
2336 (struct amap_get_mac_list_context,
2341 ctxt += sizeof(struct amap_get_mac_list_context) / 8;
2346 spin_unlock_bh(&adapter->mcc_lock);
2350 /* Uses synchronous MCCQ */
2351 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2352 u8 mac_count, u32 domain)
2354 struct be_mcc_wrb *wrb;
2355 struct be_cmd_req_set_mac_list *req;
2357 struct be_dma_mem cmd;
2359 memset(&cmd, 0, sizeof(struct be_dma_mem));
2360 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2361 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2362 &cmd.dma, GFP_KERNEL);
2364 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2368 spin_lock_bh(&adapter->mcc_lock);
2370 wrb = wrb_from_mccq(adapter);
2377 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2378 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2381 req->hdr.domain = domain;
2382 req->mac_count = mac_count;
2384 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2386 status = be_mcc_notify_wait(adapter);
2389 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2391 spin_unlock_bh(&adapter->mcc_lock);