drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2015 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static char *be_port_misconfig_evt_desc[] = {
  23         "A valid SFP module detected",
  24         "Optics faulted/ incorrectly installed/ not installed.",
  25         "Optics of two types installed.",
  26         "Incompatible optics.",
  27         "Unknown port SFP status"
  28 };
  29
  30 static char *be_port_misconfig_remedy_desc[] = {
  31         "",
  32         "Reseat optics. If issue not resolved, replace",
  33         "Remove one optic or install matching pair of optics",
  34         "Replace with compatible optics for card to function",
  35         ""
  36 };
  37
  38 static struct be_cmd_priv_map cmd_priv_map[] = {
  39         {
  40                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  41                 CMD_SUBSYSTEM_ETH,
  42                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  43                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  44         },
  45         {
  46                 OPCODE_COMMON_GET_FLOW_CONTROL,
  47                 CMD_SUBSYSTEM_COMMON,
  48                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_SET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_ETH_GET_PPORT_STATS,
  59                 CMD_SUBSYSTEM_ETH,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_COMMON_GET_PHY_DETAILS,
  65                 CMD_SUBSYSTEM_COMMON,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         },
  69         {
  70                 OPCODE_LOWLEVEL_HOST_DDR_DMA,
  71                 CMD_SUBSYSTEM_LOWLEVEL,
  72                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  73         },
  74         {
  75                 OPCODE_LOWLEVEL_LOOPBACK_TEST,
  76                 CMD_SUBSYSTEM_LOWLEVEL,
  77                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  78         },
  79         {
  80                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  81                 CMD_SUBSYSTEM_LOWLEVEL,
  82                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  83         },
  84 };
  85
  86 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  87 {
  88         int i;
  89         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  90         u32 cmd_privileges = adapter->cmd_privileges;
  91
  92         for (i = 0; i < num_entries; i++)
  93                 if (opcode == cmd_priv_map[i].opcode &&
  94                     subsystem == cmd_priv_map[i].subsystem)
  95                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  96                                 return false;
  97
  98         return true;
  99 }
 100
 101 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 102 {
 103         return wrb->payload.embedded_payload;
 104 }
 105
 106 static int be_mcc_notify(struct be_adapter *adapter)
 107 {
 108         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 109         u32 val = 0;
 110
 111         if (be_check_error(adapter, BE_ERROR_ANY))
 112                 return -EIO;
 113
 114         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 115         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 116
 117         wmb();
 118         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 119
 120         return 0;
 121 }
 122
 123 /* To check if valid bit is set, check the entire word as we don't know
 124  * the endianness of the data (old entry is host endian while a new entry is
 125  * little endian) */
 126 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 127 {
 128         u32 flags;
 129
 130         if (compl->flags != 0) {
 131                 flags = le32_to_cpu(compl->flags);
 132                 if (flags & CQE_FLAGS_VALID_MASK) {
 133                         compl->flags = flags;
 134                         return true;
 135                 }
 136         }
 137         return false;
 138 }
 139
 140 /* Need to reset the entire word that houses the valid bit */
 141 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 142 {
 143         compl->flags = 0;
 144 }
 145
 146 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 147 {
 148         unsigned long addr;
 149
 150         addr = tag1;
 151         addr = ((addr << 16) << 16) | tag0;
 152         return (void *)addr;
 153 }
 154
 155 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 156 {
 157         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 158             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 159             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 160             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 161             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 162             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 163              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 164                 return true;
 165         else
 166                 return false;
 167 }
 168
 169 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 170  * loop (has not issued be_mcc_notify_wait())
 171  */
 172 static void be_async_cmd_process(struct be_adapter *adapter,
 173                                  struct be_mcc_compl *compl,
 174                                  struct be_cmd_resp_hdr *resp_hdr)
 175 {
 176         enum mcc_base_status base_status = base_status(compl->status);
 177         u8 opcode = 0, subsystem = 0;
 178
 179         if (resp_hdr) {
 180                 opcode = resp_hdr->opcode;
 181                 subsystem = resp_hdr->subsystem;
 182         }
 183
 184         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 185             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 186                 complete(&adapter->et_cmd_compl);
 187                 return;
 188         }
 189
 190         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 191             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 192                 complete(&adapter->et_cmd_compl);
 193                 return;
 194         }
 195
 196         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 197              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 198             subsystem == CMD_SUBSYSTEM_COMMON) {
 199                 adapter->flash_status = compl->status;
 200                 complete(&adapter->et_cmd_compl);
 201                 return;
 202         }
 203
 204         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 205              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 206             subsystem == CMD_SUBSYSTEM_ETH &&
 207             base_status == MCC_STATUS_SUCCESS) {
 208                 be_parse_stats(adapter);
 209                 adapter->stats_cmd_sent = false;
 210                 return;
 211         }
 212
 213         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 214             subsystem == CMD_SUBSYSTEM_COMMON) {
 215                 if (base_status == MCC_STATUS_SUCCESS) {
 216                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 217                                                         (void *)resp_hdr;
 218                         adapter->hwmon_info.be_on_die_temp =
 219                                                 resp->on_die_temperature;
 220                 } else {
 221                         adapter->be_get_temp_freq = 0;
 222                         adapter->hwmon_info.be_on_die_temp =
 223                                                 BE_INVALID_DIE_TEMP;
 224                 }
 225                 return;
 226         }
 227 }
 228
 229 static int be_mcc_compl_process(struct be_adapter *adapter,
 230                                 struct be_mcc_compl *compl)
 231 {
 232         enum mcc_base_status base_status;
 233         enum mcc_addl_status addl_status;
 234         struct be_cmd_resp_hdr *resp_hdr;
 235         u8 opcode = 0, subsystem = 0;
 236
 237         /* Just swap the status to host endian; mcc tag is opaquely copied
 238          * from mcc_wrb */
 239         be_dws_le_to_cpu(compl, 4);
 240
 241         base_status = base_status(compl->status);
 242         addl_status = addl_status(compl->status);
 243
 244         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 245         if (resp_hdr) {
 246                 opcode = resp_hdr->opcode;
 247                 subsystem = resp_hdr->subsystem;
 248         }
 249
 250         be_async_cmd_process(adapter, compl, resp_hdr);
 251
 252         if (base_status != MCC_STATUS_SUCCESS &&
 253             !be_skip_err_log(opcode, base_status, addl_status)) {
 254                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
 255                     addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
 256                         dev_warn(&adapter->pdev->dev,
 257                                  "VF is not privileged to issue opcode %d-%d\n",
 258                                  opcode, subsystem);
 259                 } else {
 260                         dev_err(&adapter->pdev->dev,
 261                                 "opcode %d-%d failed:status %d-%d\n",
 262                                 opcode, subsystem, base_status, addl_status);
 263                 }
 264         }
 265         return compl->status;
 266 }
 267
 268 /* Link state evt is a string of bytes; no need for endian swapping */
 269 static void be_async_link_state_process(struct be_adapter *adapter,
 270                                         struct be_mcc_compl *compl)
 271 {
 272         struct be_async_event_link_state *evt =
 273                         (struct be_async_event_link_state *)compl;
 274
 275         /* When link status changes, link speed must be re-queried from FW */
 276         adapter->phy.link_speed = -1;
 277
 278         /* On BEx the FW does not send a separate link status
 279          * notification for physical and logical link.
 280          * On other chips just process the logical link
 281          * status notification
 282          */
 283         if (!BEx_chip(adapter) &&
 284             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 285                 return;
 286
 287         /* For the initial link status do not rely on the ASYNC event as
 288          * it may not be received in some cases.
 289          */
 290         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 291                 be_link_status_update(adapter,
 292                                       evt->port_link_status & LINK_STATUS_MASK);
 293 }
 294
 295 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 296                                                   struct be_mcc_compl *compl)
 297 {
 298         struct be_async_event_misconfig_port *evt =
 299                         (struct be_async_event_misconfig_port *)compl;
 300         u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
 301         struct device *dev = &adapter->pdev->dev;
 302         u8 port_misconfig_evt;
 303
 304         port_misconfig_evt =
 305                 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
 306
 307         /* Log an error message that would allow a user to determine
 308          * whether the SFPs have an issue
 309          */
 310         dev_info(dev, "Port %c: %s %s", adapter->port_name,
 311                  be_port_misconfig_evt_desc[port_misconfig_evt],
 312                  be_port_misconfig_remedy_desc[port_misconfig_evt]);
 313
 314         if (port_misconfig_evt == INCOMPATIBLE_SFP)
 315                 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
 316 }
 317
 318 /* Grp5 CoS Priority evt */
 319 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 320                                                struct be_mcc_compl *compl)
 321 {
 322         struct be_async_event_grp5_cos_priority *evt =
 323                         (struct be_async_event_grp5_cos_priority *)compl;
 324
 325         if (evt->valid) {
 326                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 327                 adapter->recommended_prio_bits =
 328                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 329         }
 330 }
 331
 332 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 333 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 334                                             struct be_mcc_compl *compl)
 335 {
 336         struct be_async_event_grp5_qos_link_speed *evt =
 337                         (struct be_async_event_grp5_qos_link_speed *)compl;
 338
 339         if (adapter->phy.link_speed >= 0 &&
 340             evt->physical_port == adapter->port_num)
 341                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 342 }
 343
 344 /*Grp5 PVID evt*/
 345 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 346                                              struct be_mcc_compl *compl)
 347 {
 348         struct be_async_event_grp5_pvid_state *evt =
 349                         (struct be_async_event_grp5_pvid_state *)compl;
 350
 351         if (evt->enabled) {
 352                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 353                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 354         } else {
 355                 adapter->pvid = 0;
 356         }
 357 }
 358
 359 #define MGMT_ENABLE_MASK        0x4
 360 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 361                                              struct be_mcc_compl *compl)
 362 {
 363         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 364         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 365
 366         if (evt_dw1 & MGMT_ENABLE_MASK) {
 367                 adapter->flags |= BE_FLAGS_OS2BMC;
 368                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 369         } else {
 370                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 371         }
 372 }
 373
 374 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 375                                       struct be_mcc_compl *compl)
 376 {
 377         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 378                                 ASYNC_EVENT_TYPE_MASK;
 379
 380         switch (event_type) {
 381         case ASYNC_EVENT_COS_PRIORITY:
 382                 be_async_grp5_cos_priority_process(adapter, compl);
 383                 break;
 384         case ASYNC_EVENT_QOS_SPEED:
 385                 be_async_grp5_qos_speed_process(adapter, compl);
 386                 break;
 387         case ASYNC_EVENT_PVID_STATE:
 388                 be_async_grp5_pvid_state_process(adapter, compl);
 389                 break;
 390         /* Async event to disable/enable os2bmc and/or mac-learning */
 391         case ASYNC_EVENT_FW_CONTROL:
 392                 be_async_grp5_fw_control_process(adapter, compl);
 393                 break;
 394         default:
 395                 break;
 396         }
 397 }
 398
 399 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 400                                      struct be_mcc_compl *cmp)
 401 {
 402         u8 event_type = 0;
 403         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 404
 405         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 406                         ASYNC_EVENT_TYPE_MASK;
 407
 408         switch (event_type) {
 409         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 410                 if (evt->valid)
 411                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 412                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 413         break;
 414         default:
 415                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 416                          event_type);
 417         break;
 418         }
 419 }
 420
 421 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 422                                          struct be_mcc_compl *cmp)
 423 {
 424         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 425                         ASYNC_EVENT_TYPE_MASK;
 426
 427         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 428                 be_async_port_misconfig_event_process(adapter, cmp);
 429 }
 430
 431 static inline bool is_link_state_evt(u32 flags)
 432 {
 433         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 434                         ASYNC_EVENT_CODE_LINK_STATE;
 435 }
 436
 437 static inline bool is_grp5_evt(u32 flags)
 438 {
 439         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 440                         ASYNC_EVENT_CODE_GRP_5;
 441 }
 442
 443 static inline bool is_dbg_evt(u32 flags)
 444 {
 445         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 446                         ASYNC_EVENT_CODE_QNQ;
 447 }
 448
 449 static inline bool is_sliport_evt(u32 flags)
 450 {
 451         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 452                 ASYNC_EVENT_CODE_SLIPORT;
 453 }
 454
 455 static void be_mcc_event_process(struct be_adapter *adapter,
 456                                  struct be_mcc_compl *compl)
 457 {
 458         if (is_link_state_evt(compl->flags))
 459                 be_async_link_state_process(adapter, compl);
 460         else if (is_grp5_evt(compl->flags))
 461                 be_async_grp5_evt_process(adapter, compl);
 462         else if (is_dbg_evt(compl->flags))
 463                 be_async_dbg_evt_process(adapter, compl);
 464         else if (is_sliport_evt(compl->flags))
 465                 be_async_sliport_evt_process(adapter, compl);
 466 }
 467
 468 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 469 {
 470         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 471         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 472
 473         if (be_mcc_compl_is_new(compl)) {
 474                 queue_tail_inc(mcc_cq);
 475                 return compl;
 476         }
 477         return NULL;
 478 }
 479
 480 void be_async_mcc_enable(struct be_adapter *adapter)
 481 {
 482         spin_lock_bh(&adapter->mcc_cq_lock);
 483
 484         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 485         adapter->mcc_obj.rearm_cq = true;
 486
 487         spin_unlock_bh(&adapter->mcc_cq_lock);
 488 }
 489
 490 void be_async_mcc_disable(struct be_adapter *adapter)
 491 {
 492         spin_lock_bh(&adapter->mcc_cq_lock);
 493
 494         adapter->mcc_obj.rearm_cq = false;
 495         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 496
 497         spin_unlock_bh(&adapter->mcc_cq_lock);
 498 }
 499
 500 int be_process_mcc(struct be_adapter *adapter)
 501 {
 502         struct be_mcc_compl *compl;
 503         int num = 0, status = 0;
 504         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 505
 506         spin_lock(&adapter->mcc_cq_lock);
 507
 508         while ((compl = be_mcc_compl_get(adapter))) {
 509                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 510                         be_mcc_event_process(adapter, compl);
 511                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 512                         status = be_mcc_compl_process(adapter, compl);
 513                         atomic_dec(&mcc_obj->q.used);
 514                 }
 515                 be_mcc_compl_use(compl);
 516                 num++;
 517         }
 518
 519         if (num)
 520                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 521
 522         spin_unlock(&adapter->mcc_cq_lock);
 523         return status;
 524 }
 525
 526 /* Wait till no more pending mcc requests are present */
 527 static int be_mcc_wait_compl(struct be_adapter *adapter)
 528 {
 529 #define mcc_timeout             120000 /* 12s timeout */
 530         int i, status = 0;
 531         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 532
 533         for (i = 0; i < mcc_timeout; i++) {
 534                 if (be_check_error(adapter, BE_ERROR_ANY))
 535                         return -EIO;
 536
 537                 local_bh_disable();
 538                 status = be_process_mcc(adapter);
 539                 local_bh_enable();
 540
 541                 if (atomic_read(&mcc_obj->q.used) == 0)
 542                         break;
 543                 udelay(100);
 544         }
 545         if (i == mcc_timeout) {
 546                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 547                 be_set_error(adapter, BE_ERROR_FW);
 548                 return -EIO;
 549         }
 550         return status;
 551 }
 552
 553 /* Notify MCC requests and wait for completion */
 554 static int be_mcc_notify_wait(struct be_adapter *adapter)
 555 {
 556         int status;
 557         struct be_mcc_wrb *wrb;
 558         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 559         u16 index = mcc_obj->q.head;
 560         struct be_cmd_resp_hdr *resp;
 561
 562         index_dec(&index, mcc_obj->q.len);
 563         wrb = queue_index_node(&mcc_obj->q, index);
 564
 565         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 566
 567         status = be_mcc_notify(adapter);
 568         if (status)
 569                 goto out;
 570
 571         status = be_mcc_wait_compl(adapter);
 572         if (status == -EIO)
 573                 goto out;
 574
 575         status = (resp->base_status |
 576                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 577                    CQE_ADDL_STATUS_SHIFT));
 578 out:
 579         return status;
 580 }
 581
 582 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 583 {
 584         int msecs = 0;
 585         u32 ready;
 586
 587         do {
 588                 if (be_check_error(adapter, BE_ERROR_ANY))
 589                         return -EIO;
 590
 591                 ready = ioread32(db);
 592                 if (ready == 0xffffffff)
 593                         return -1;
 594
 595                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 596                 if (ready)
 597                         break;
 598
 599                 if (msecs > 4000) {
 600                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 601                         be_set_error(adapter, BE_ERROR_FW);
 602                         be_detect_error(adapter);
 603                         return -1;
 604                 }
 605
 606                 msleep(1);
 607                 msecs++;
 608         } while (true);
 609
 610         return 0;
 611 }
 612
 613 /*
 614  * Insert the mailbox address into the doorbell in two steps
 615  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 616  */
 617 static int be_mbox_notify_wait(struct be_adapter *adapter)
 618 {
 619         int status;
 620         u32 val = 0;
 621         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 622         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 623         struct be_mcc_mailbox *mbox = mbox_mem->va;
 624         struct be_mcc_compl *compl = &mbox->compl;
 625
 626         /* wait for ready to be set */
 627         status = be_mbox_db_ready_wait(adapter, db);
 628         if (status != 0)
 629                 return status;
 630
 631         val |= MPU_MAILBOX_DB_HI_MASK;
 632         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 633         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 634         iowrite32(val, db);
 635
 636         /* wait for ready to be set */
 637         status = be_mbox_db_ready_wait(adapter, db);
 638         if (status != 0)
 639                 return status;
 640
 641         val = 0;
 642         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 643         val |= (u32)(mbox_mem->dma >> 4) << 2;
 644         iowrite32(val, db);
 645
 646         status = be_mbox_db_ready_wait(adapter, db);
 647         if (status != 0)
 648                 return status;
 649
 650         /* A cq entry has been made now */
 651         if (be_mcc_compl_is_new(compl)) {
 652                 status = be_mcc_compl_process(adapter, &mbox->compl);
 653                 be_mcc_compl_use(compl);
 654                 if (status)
 655                         return status;
 656         } else {
 657                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 658                 return -1;
 659         }
 660         return 0;
 661 }
 662
 663 static u16 be_POST_stage_get(struct be_adapter *adapter)
 664 {
 665         u32 sem;
 666
 667         if (BEx_chip(adapter))
 668                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 669         else
 670                 pci_read_config_dword(adapter->pdev,
 671                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 672
 673         return sem & POST_STAGE_MASK;
 674 }
 675
 676 static int lancer_wait_ready(struct be_adapter *adapter)
 677 {
 678 #define SLIPORT_READY_TIMEOUT 30
 679         u32 sliport_status;
 680         int i;
 681
 682         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 683                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 684                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 685                         return 0;
 686
 687                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 688                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 689                         return -EIO;
 690
 691                 msleep(1000);
 692         }
 693
 694         return sliport_status ? : -1;
 695 }
 696
 697 int be_fw_wait_ready(struct be_adapter *adapter)
 698 {
 699         u16 stage;
 700         int status, timeout = 0;
 701         struct device *dev = &adapter->pdev->dev;
 702
 703         if (lancer_chip(adapter)) {
 704                 status = lancer_wait_ready(adapter);
 705                 if (status) {
 706                         stage = status;
 707                         goto err;
 708                 }
 709                 return 0;
 710         }
 711
 712         do {
 713                 /* There's no means to poll POST state on BE2/3 VFs */
 714                 if (BEx_chip(adapter) && be_virtfn(adapter))
 715                         return 0;
 716
 717                 stage = be_POST_stage_get(adapter);
 718                 if (stage == POST_STAGE_ARMFW_RDY)
 719                         return 0;
 720
 721                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 722                 if (msleep_interruptible(2000)) {
 723                         dev_err(dev, "Waiting for POST aborted\n");
 724                         return -EINTR;
 725                 }
 726                 timeout += 2;
 727         } while (timeout < 60);
 728
 729 err:
 730         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 731         return -ETIMEDOUT;
 732 }
 733
 734 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 735 {
 736         return &wrb->payload.sgl[0];
 737 }
 738
 739 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 740 {
 741         wrb->tag0 = addr & 0xFFFFFFFF;
 742         wrb->tag1 = upper_32_bits(addr);
 743 }
 744
 745 /* Don't touch the hdr after it's prepared */
 746 /* mem will be NULL for embedded commands */
 747 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 748                                    u8 subsystem, u8 opcode, int cmd_len,
 749                                    struct be_mcc_wrb *wrb,
 750                                    struct be_dma_mem *mem)
 751 {
 752         struct be_sge *sge;
 753
 754         req_hdr->opcode = opcode;
 755         req_hdr->subsystem = subsystem;
 756         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 757         req_hdr->version = 0;
 758         fill_wrb_tags(wrb, (ulong) req_hdr);
 759         wrb->payload_length = cmd_len;
 760         if (mem) {
 761                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 762                         MCC_WRB_SGE_CNT_SHIFT;
 763                 sge = nonembedded_sgl(wrb);
 764                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 765                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 766                 sge->len = cpu_to_le32(mem->size);
 767         } else
 768                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 769         be_dws_cpu_to_le(wrb, 8);
 770 }
 771
 772 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 773                                       struct be_dma_mem *mem)
 774 {
 775         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 776         u64 dma = (u64)mem->dma;
 777
 778         for (i = 0; i < buf_pages; i++) {
 779                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 780                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 781                 dma += PAGE_SIZE_4K;
 782         }
 783 }
 784
 785 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 786 {
 787         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 788         struct be_mcc_wrb *wrb
 789                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 790         memset(wrb, 0, sizeof(*wrb));
 791         return wrb;
 792 }
 793
 794 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 795 {
 796         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 797         struct be_mcc_wrb *wrb;
 798
 799         if (!mccq->created)
 800                 return NULL;
 801
 802         if (atomic_read(&mccq->used) >= mccq->len)
 803                 return NULL;
 804
 805         wrb = queue_head_node(mccq);
 806         queue_head_inc(mccq);
 807         atomic_inc(&mccq->used);
 808         memset(wrb, 0, sizeof(*wrb));
 809         return wrb;
 810 }
 811
 812 static bool use_mcc(struct be_adapter *adapter)
 813 {
 814         return adapter->mcc_obj.q.created;
 815 }
 816
 817 /* Must be used only in process context */
 818 static int be_cmd_lock(struct be_adapter *adapter)
 819 {
 820         if (use_mcc(adapter)) {
 821                 spin_lock_bh(&adapter->mcc_lock);
 822                 return 0;
 823         } else {
 824                 return mutex_lock_interruptible(&adapter->mbox_lock);
 825         }
 826 }
 827
 828 /* Must be used only in process context */
 829 static void be_cmd_unlock(struct be_adapter *adapter)
 830 {
 831         if (use_mcc(adapter))
 832                 spin_unlock_bh(&adapter->mcc_lock);
 833         else
 834                 return mutex_unlock(&adapter->mbox_lock);
 835 }
 836
 837 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 838                                       struct be_mcc_wrb *wrb)
 839 {
 840         struct be_mcc_wrb *dest_wrb;
 841
 842         if (use_mcc(adapter)) {
 843                 dest_wrb = wrb_from_mccq(adapter);
 844                 if (!dest_wrb)
 845                         return NULL;
 846         } else {
 847                 dest_wrb = wrb_from_mbox(adapter);
 848         }
 849
 850         memcpy(dest_wrb, wrb, sizeof(*wrb));
 851         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 852                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 853
 854         return dest_wrb;
 855 }
 856
 857 /* Must be used only in process context */
 858 static int be_cmd_notify_wait(struct be_adapter *adapter,
 859                               struct be_mcc_wrb *wrb)
 860 {
 861         struct be_mcc_wrb *dest_wrb;
 862         int status;
 863
 864         status = be_cmd_lock(adapter);
 865         if (status)
 866                 return status;
 867
 868         dest_wrb = be_cmd_copy(adapter, wrb);
 869         if (!dest_wrb) {
 870                 status = -EBUSY;
 871                 goto unlock;
 872         }
 873
 874         if (use_mcc(adapter))
 875                 status = be_mcc_notify_wait(adapter);
 876         else
 877                 status = be_mbox_notify_wait(adapter);
 878
 879         if (!status)
 880                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 881
 882 unlock:
 883         be_cmd_unlock(adapter);
 884         return status;
 885 }
 886
 887 /* Tell fw we're about to start firing cmds by writing a
 888  * special pattern across the wrb hdr; uses mbox
 889  */
 890 int be_cmd_fw_init(struct be_adapter *adapter)
 891 {
 892         u8 *wrb;
 893         int status;
 894
 895         if (lancer_chip(adapter))
 896                 return 0;
 897
 898         if (mutex_lock_interruptible(&adapter->mbox_lock))
 899                 return -1;
 900
 901         wrb = (u8 *)wrb_from_mbox(adapter);
 902         *wrb++ = 0xFF;
 903         *wrb++ = 0x12;
 904         *wrb++ = 0x34;
 905         *wrb++ = 0xFF;
 906         *wrb++ = 0xFF;
 907         *wrb++ = 0x56;
 908         *wrb++ = 0x78;
 909         *wrb = 0xFF;
 910
 911         status = be_mbox_notify_wait(adapter);
 912
 913         mutex_unlock(&adapter->mbox_lock);
 914         return status;
 915 }
 916
 917 /* Tell fw we're done with firing cmds by writing a
 918  * special pattern across the wrb hdr; uses mbox
 919  */
 920 int be_cmd_fw_clean(struct be_adapter *adapter)
 921 {
 922         u8 *wrb;
 923         int status;
 924
 925         if (lancer_chip(adapter))
 926                 return 0;
 927
 928         if (mutex_lock_interruptible(&adapter->mbox_lock))
 929                 return -1;
 930
 931         wrb = (u8 *)wrb_from_mbox(adapter);
 932         *wrb++ = 0xFF;
 933         *wrb++ = 0xAA;
 934         *wrb++ = 0xBB;
 935         *wrb++ = 0xFF;
 936         *wrb++ = 0xFF;
 937         *wrb++ = 0xCC;
 938         *wrb++ = 0xDD;
 939         *wrb = 0xFF;
 940
 941         status = be_mbox_notify_wait(adapter);
 942
 943         mutex_unlock(&adapter->mbox_lock);
 944         return status;
 945 }
 946
 947 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 948 {
 949         struct be_mcc_wrb *wrb;
 950         struct be_cmd_req_eq_create *req;
 951         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 952         int status, ver = 0;
 953
 954         if (mutex_lock_interruptible(&adapter->mbox_lock))
 955                 return -1;
 956
 957         wrb = wrb_from_mbox(adapter);
 958         req = embedded_payload(wrb);
 959
 960         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 961                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
 962                                NULL);
 963
 964         /* Support for EQ_CREATEv2 available only SH-R onwards */
 965         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 966                 ver = 2;
 967
 968         req->hdr.version = ver;
 969         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 970
 971         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 972         /* 4byte eqe*/
 973         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 974         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 975                       __ilog2_u32(eqo->q.len / 256));
 976         be_dws_cpu_to_le(req->context, sizeof(req->context));
 977
 978         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 979
 980         status = be_mbox_notify_wait(adapter);
 981         if (!status) {
 982                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 983
 984                 eqo->q.id = le16_to_cpu(resp->eq_id);
 985                 eqo->msix_idx =
 986                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 987                 eqo->q.created = true;
 988         }
 989
 990         mutex_unlock(&adapter->mbox_lock);
 991         return status;
 992 }
 993
 994 /* Use MCC */
 995 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 996                           bool permanent, u32 if_handle, u32 pmac_id)
 997 {
 998         struct be_mcc_wrb *wrb;
 999         struct be_cmd_req_mac_query *req;
1000         int status;
1001
1002         spin_lock_bh(&adapter->mcc_lock);
1003
1004         wrb = wrb_from_mccq(adapter);
1005         if (!wrb) {
1006                 status = -EBUSY;
1007                 goto err;
1008         }
1009         req = embedded_payload(wrb);
1010
1011         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1012                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1013                                NULL);
1014         req->type = MAC_ADDRESS_TYPE_NETWORK;
1015         if (permanent) {
1016                 req->permanent = 1;
1017         } else {
1018                 req->if_id = cpu_to_le16((u16)if_handle);
1019                 req->pmac_id = cpu_to_le32(pmac_id);
1020                 req->permanent = 0;
1021         }
1022
1023         status = be_mcc_notify_wait(adapter);
1024         if (!status) {
1025                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1026
1027                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1028         }
1029
1030 err:
1031         spin_unlock_bh(&adapter->mcc_lock);
1032         return status;
1033 }
1034
1035 /* Uses synchronous MCCQ */
1036 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1037                     u32 if_id, u32 *pmac_id, u32 domain)
1038 {
1039         struct be_mcc_wrb *wrb;
1040         struct be_cmd_req_pmac_add *req;
1041         int status;
1042
1043         spin_lock_bh(&adapter->mcc_lock);
1044
1045         wrb = wrb_from_mccq(adapter);
1046         if (!wrb) {
1047                 status = -EBUSY;
1048                 goto err;
1049         }
1050         req = embedded_payload(wrb);
1051
1052         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1053                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1054                                NULL);
1055
1056         req->hdr.domain = domain;
1057         req->if_id = cpu_to_le32(if_id);
1058         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1059
1060         status = be_mcc_notify_wait(adapter);
1061         if (!status) {
1062                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1063
1064                 *pmac_id = le32_to_cpu(resp->pmac_id);
1065         }
1066
1067 err:
1068         spin_unlock_bh(&adapter->mcc_lock);
1069
1070          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1071                 status = -EPERM;
1072
1073         return status;
1074 }
1075
1076 /* Uses synchronous MCCQ */
1077 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1078 {
1079         struct be_mcc_wrb *wrb;
1080         struct be_cmd_req_pmac_del *req;
1081         int status;
1082
1083         if (pmac_id == -1)
1084                 return 0;
1085
1086         spin_lock_bh(&adapter->mcc_lock);
1087
1088         wrb = wrb_from_mccq(adapter);
1089         if (!wrb) {
1090                 status = -EBUSY;
1091                 goto err;
1092         }
1093         req = embedded_payload(wrb);
1094
1095         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1096                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1097                                wrb, NULL);
1098
1099         req->hdr.domain = dom;
1100         req->if_id = cpu_to_le32(if_id);
1101         req->pmac_id = cpu_to_le32(pmac_id);
1102
1103         status = be_mcc_notify_wait(adapter);
1104
1105 err:
1106         spin_unlock_bh(&adapter->mcc_lock);
1107         return status;
1108 }
1109
1110 /* Uses Mbox */
1111 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1112                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1113 {
1114         struct be_mcc_wrb *wrb;
1115         struct be_cmd_req_cq_create *req;
1116         struct be_dma_mem *q_mem = &cq->dma_mem;
1117         void *ctxt;
1118         int status;
1119
1120         if (mutex_lock_interruptible(&adapter->mbox_lock))
1121                 return -1;
1122
1123         wrb = wrb_from_mbox(adapter);
1124         req = embedded_payload(wrb);
1125         ctxt = &req->context;
1126
1127         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1128                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1129                                NULL);
1130
1131         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1132
1133         if (BEx_chip(adapter)) {
1134                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1135                               coalesce_wm);
1136                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1137                               ctxt, no_delay);
1138                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1139                               __ilog2_u32(cq->len / 256));
1140                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1141                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1142                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1143         } else {
1144                 req->hdr.version = 2;
1145                 req->page_size = 1; /* 1 for 4K */
1146
1147                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1148                  * Lancer uses COMMON_MODIFY_CQ to set this field
1149                  */
1150                 if (!lancer_chip(adapter))
1151                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1152                                       ctxt, coalesce_wm);
1153                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1154                               no_delay);
1155                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1156                               __ilog2_u32(cq->len / 256));
1157                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1158                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1159                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1160         }
1161
1162         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1163
1164         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1165
1166         status = be_mbox_notify_wait(adapter);
1167         if (!status) {
1168                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1169
1170                 cq->id = le16_to_cpu(resp->cq_id);
1171                 cq->created = true;
1172         }
1173
1174         mutex_unlock(&adapter->mbox_lock);
1175
1176         return status;
1177 }
1178
1179 static u32 be_encoded_q_len(int q_len)
1180 {
1181         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1182
1183         if (len_encoded == 16)
1184                 len_encoded = 0;
1185         return len_encoded;
1186 }
1187
1188 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1189                                   struct be_queue_info *mccq,
1190                                   struct be_queue_info *cq)
1191 {
1192         struct be_mcc_wrb *wrb;
1193         struct be_cmd_req_mcc_ext_create *req;
1194         struct be_dma_mem *q_mem = &mccq->dma_mem;
1195         void *ctxt;
1196         int status;
1197
1198         if (mutex_lock_interruptible(&adapter->mbox_lock))
1199                 return -1;
1200
1201         wrb = wrb_from_mbox(adapter);
1202         req = embedded_payload(wrb);
1203         ctxt = &req->context;
1204
1205         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1206                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1207                                NULL);
1208
1209         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1210         if (BEx_chip(adapter)) {
1211                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1212                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1213                               be_encoded_q_len(mccq->len));
1214                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1215         } else {
1216                 req->hdr.version = 1;
1217                 req->cq_id = cpu_to_le16(cq->id);
1218
1219                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1220                               be_encoded_q_len(mccq->len));
1221                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1222                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1223                               ctxt, cq->id);
1224                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1225                               ctxt, 1);
1226         }
1227
1228         /* Subscribe to Link State, Sliport Event and Group 5 Events
1229          * (bits 1, 5 and 17 set)
1230          */
1231         req->async_event_bitmap[0] =
1232                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1233                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1234                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1235                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1236
1237         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1238
1239         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1240
1241         status = be_mbox_notify_wait(adapter);
1242         if (!status) {
1243                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1244
1245                 mccq->id = le16_to_cpu(resp->id);
1246                 mccq->created = true;
1247         }
1248         mutex_unlock(&adapter->mbox_lock);
1249
1250         return status;
1251 }
1252
1253 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1254                                   struct be_queue_info *mccq,
1255                                   struct be_queue_info *cq)
1256 {
1257         struct be_mcc_wrb *wrb;
1258         struct be_cmd_req_mcc_create *req;
1259         struct be_dma_mem *q_mem = &mccq->dma_mem;
1260         void *ctxt;
1261         int status;
1262
1263         if (mutex_lock_interruptible(&adapter->mbox_lock))
1264                 return -1;
1265
1266         wrb = wrb_from_mbox(adapter);
1267         req = embedded_payload(wrb);
1268         ctxt = &req->context;
1269
1270         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1271                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1272                                NULL);
1273
1274         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1275
1276         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1277         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1278                       be_encoded_q_len(mccq->len));
1279         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1280
1281         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1282
1283         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1284
1285         status = be_mbox_notify_wait(adapter);
1286         if (!status) {
1287                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1288
1289                 mccq->id = le16_to_cpu(resp->id);
1290                 mccq->created = true;
1291         }
1292
1293         mutex_unlock(&adapter->mbox_lock);
1294         return status;
1295 }
1296
1297 int be_cmd_mccq_create(struct be_adapter *adapter,
1298                        struct be_queue_info *mccq, struct be_queue_info *cq)
1299 {
1300         int status;
1301
1302         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1303         if (status && BEx_chip(adapter)) {
1304                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1305                         "or newer to avoid conflicting priorities between NIC "
1306                         "and FCoE traffic");
1307                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1308         }
1309         return status;
1310 }
1311
1312 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1313 {
1314         struct be_mcc_wrb wrb = {0};
1315         struct be_cmd_req_eth_tx_create *req;
1316         struct be_queue_info *txq = &txo->q;
1317         struct be_queue_info *cq = &txo->cq;
1318         struct be_dma_mem *q_mem = &txq->dma_mem;
1319         int status, ver = 0;
1320
1321         req = embedded_payload(&wrb);
1322         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1323                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1324
1325         if (lancer_chip(adapter)) {
1326                 req->hdr.version = 1;
1327         } else if (BEx_chip(adapter)) {
1328                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1329                         req->hdr.version = 2;
1330         } else { /* For SH */
1331                 req->hdr.version = 2;
1332         }
1333
1334         if (req->hdr.version > 0)
1335                 req->if_id = cpu_to_le16(adapter->if_handle);
1336         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1337         req->ulp_num = BE_ULP1_NUM;
1338         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1339         req->cq_id = cpu_to_le16(cq->id);
1340         req->queue_size = be_encoded_q_len(txq->len);
1341         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1342         ver = req->hdr.version;
1343
1344         status = be_cmd_notify_wait(adapter, &wrb);
1345         if (!status) {
1346                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1347
1348                 txq->id = le16_to_cpu(resp->cid);
1349                 if (ver == 2)
1350                         txo->db_offset = le32_to_cpu(resp->db_offset);
1351                 else
1352                         txo->db_offset = DB_TXULP1_OFFSET;
1353                 txq->created = true;
1354         }
1355
1356         return status;
1357 }
1358
1359 /* Uses MCC */
1360 int be_cmd_rxq_create(struct be_adapter *adapter,
1361                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1362                       u32 if_id, u32 rss, u8 *rss_id)
1363 {
1364         struct be_mcc_wrb *wrb;
1365         struct be_cmd_req_eth_rx_create *req;
1366         struct be_dma_mem *q_mem = &rxq->dma_mem;
1367         int status;
1368
1369         spin_lock_bh(&adapter->mcc_lock);
1370
1371         wrb = wrb_from_mccq(adapter);
1372         if (!wrb) {
1373                 status = -EBUSY;
1374                 goto err;
1375         }
1376         req = embedded_payload(wrb);
1377
1378         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1379                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1380
1381         req->cq_id = cpu_to_le16(cq_id);
1382         req->frag_size = fls(frag_size) - 1;
1383         req->num_pages = 2;
1384         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1385         req->interface_id = cpu_to_le32(if_id);
1386         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1387         req->rss_queue = cpu_to_le32(rss);
1388
1389         status = be_mcc_notify_wait(adapter);
1390         if (!status) {
1391                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1392
1393                 rxq->id = le16_to_cpu(resp->id);
1394                 rxq->created = true;
1395                 *rss_id = resp->rss_id;
1396         }
1397
1398 err:
1399         spin_unlock_bh(&adapter->mcc_lock);
1400         return status;
1401 }
1402
1403 /* Generic destroyer function for all types of queues
1404  * Uses Mbox
1405  */
1406 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1407                      int queue_type)
1408 {
1409         struct be_mcc_wrb *wrb;
1410         struct be_cmd_req_q_destroy *req;
1411         u8 subsys = 0, opcode = 0;
1412         int status;
1413
1414         if (mutex_lock_interruptible(&adapter->mbox_lock))
1415                 return -1;
1416
1417         wrb = wrb_from_mbox(adapter);
1418         req = embedded_payload(wrb);
1419
1420         switch (queue_type) {
1421         case QTYPE_EQ:
1422                 subsys = CMD_SUBSYSTEM_COMMON;
1423                 opcode = OPCODE_COMMON_EQ_DESTROY;
1424                 break;
1425         case QTYPE_CQ:
1426                 subsys = CMD_SUBSYSTEM_COMMON;
1427                 opcode = OPCODE_COMMON_CQ_DESTROY;
1428                 break;
1429         case QTYPE_TXQ:
1430                 subsys = CMD_SUBSYSTEM_ETH;
1431                 opcode = OPCODE_ETH_TX_DESTROY;
1432                 break;
1433         case QTYPE_RXQ:
1434                 subsys = CMD_SUBSYSTEM_ETH;
1435                 opcode = OPCODE_ETH_RX_DESTROY;
1436                 break;
1437         case QTYPE_MCCQ:
1438                 subsys = CMD_SUBSYSTEM_COMMON;
1439                 opcode = OPCODE_COMMON_MCC_DESTROY;
1440                 break;
1441         default:
1442                 BUG();
1443         }
1444
1445         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1446                                NULL);
1447         req->id = cpu_to_le16(q->id);
1448
1449         status = be_mbox_notify_wait(adapter);
1450         q->created = false;
1451
1452         mutex_unlock(&adapter->mbox_lock);
1453         return status;
1454 }
1455
1456 /* Uses MCC */
1457 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1458 {
1459         struct be_mcc_wrb *wrb;
1460         struct be_cmd_req_q_destroy *req;
1461         int status;
1462
1463         spin_lock_bh(&adapter->mcc_lock);
1464
1465         wrb = wrb_from_mccq(adapter);
1466         if (!wrb) {
1467                 status = -EBUSY;
1468                 goto err;
1469         }
1470         req = embedded_payload(wrb);
1471
1472         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1473                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1474         req->id = cpu_to_le16(q->id);
1475
1476         status = be_mcc_notify_wait(adapter);
1477         q->created = false;
1478
1479 err:
1480         spin_unlock_bh(&adapter->mcc_lock);
1481         return status;
1482 }
1483
1484 /* Create an rx filtering policy configuration on an i/f
1485  * Will use MBOX only if MCCQ has not been created.
1486  */
1487 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1488                      u32 *if_handle, u32 domain)
1489 {
1490         struct be_mcc_wrb wrb = {0};
1491         struct be_cmd_req_if_create *req;
1492         int status;
1493
1494         req = embedded_payload(&wrb);
1495         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1496                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1497                                sizeof(*req), &wrb, NULL);
1498         req->hdr.domain = domain;
1499         req->capability_flags = cpu_to_le32(cap_flags);
1500         req->enable_flags = cpu_to_le32(en_flags);
1501         req->pmac_invalid = true;
1502
1503         status = be_cmd_notify_wait(adapter, &wrb);
1504         if (!status) {
1505                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1506
1507                 *if_handle = le32_to_cpu(resp->interface_id);
1508
1509                 /* Hack to retrieve VF's pmac-id on BE3 */
1510                 if (BE3_chip(adapter) && be_virtfn(adapter))
1511                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1512         }
1513         return status;
1514 }
1515
1516 /* Uses MCCQ */
1517 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1518 {
1519         struct be_mcc_wrb *wrb;
1520         struct be_cmd_req_if_destroy *req;
1521         int status;
1522
1523         if (interface_id == -1)
1524                 return 0;
1525
1526         spin_lock_bh(&adapter->mcc_lock);
1527
1528         wrb = wrb_from_mccq(adapter);
1529         if (!wrb) {
1530                 status = -EBUSY;
1531                 goto err;
1532         }
1533         req = embedded_payload(wrb);
1534
1535         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1536                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1537                                sizeof(*req), wrb, NULL);
1538         req->hdr.domain = domain;
1539         req->interface_id = cpu_to_le32(interface_id);
1540
1541         status = be_mcc_notify_wait(adapter);
1542 err:
1543         spin_unlock_bh(&adapter->mcc_lock);
1544         return status;
1545 }
1546
1547 /* Get stats is a non embedded command: the request is not embedded inside
1548  * WRB but is a separate dma memory block
1549  * Uses asynchronous MCC
1550  */
1551 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1552 {
1553         struct be_mcc_wrb *wrb;
1554         struct be_cmd_req_hdr *hdr;
1555         int status = 0;
1556
1557         spin_lock_bh(&adapter->mcc_lock);
1558
1559         wrb = wrb_from_mccq(adapter);
1560         if (!wrb) {
1561                 status = -EBUSY;
1562                 goto err;
1563         }
1564         hdr = nonemb_cmd->va;
1565
1566         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1567                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1568                                nonemb_cmd);
1569
1570         /* version 1 of the cmd is not supported only by BE2 */
1571         if (BE2_chip(adapter))
1572                 hdr->version = 0;
1573         if (BE3_chip(adapter) || lancer_chip(adapter))
1574                 hdr->version = 1;
1575         else
1576                 hdr->version = 2;
1577
1578         status = be_mcc_notify(adapter);
1579         if (status)
1580                 goto err;
1581
1582         adapter->stats_cmd_sent = true;
1583
1584 err:
1585         spin_unlock_bh(&adapter->mcc_lock);
1586         return status;
1587 }
1588
1589 /* Lancer Stats */
1590 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1591                                struct be_dma_mem *nonemb_cmd)
1592 {
1593         struct be_mcc_wrb *wrb;
1594         struct lancer_cmd_req_pport_stats *req;
1595         int status = 0;
1596
1597         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1598                             CMD_SUBSYSTEM_ETH))
1599                 return -EPERM;
1600
1601         spin_lock_bh(&adapter->mcc_lock);
1602
1603         wrb = wrb_from_mccq(adapter);
1604         if (!wrb) {
1605                 status = -EBUSY;
1606                 goto err;
1607         }
1608         req = nonemb_cmd->va;
1609
1610         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1611                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1612                                wrb, nonemb_cmd);
1613
1614         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1615         req->cmd_params.params.reset_stats = 0;
1616
1617         status = be_mcc_notify(adapter);
1618         if (status)
1619                 goto err;
1620
1621         adapter->stats_cmd_sent = true;
1622
1623 err:
1624         spin_unlock_bh(&adapter->mcc_lock);
1625         return status;
1626 }
1627
1628 static int be_mac_to_link_speed(int mac_speed)
1629 {
1630         switch (mac_speed) {
1631         case PHY_LINK_SPEED_ZERO:
1632                 return 0;
1633         case PHY_LINK_SPEED_10MBPS:
1634                 return 10;
1635         case PHY_LINK_SPEED_100MBPS:
1636                 return 100;
1637         case PHY_LINK_SPEED_1GBPS:
1638                 return 1000;
1639         case PHY_LINK_SPEED_10GBPS:
1640                 return 10000;
1641         case PHY_LINK_SPEED_20GBPS:
1642                 return 20000;
1643         case PHY_LINK_SPEED_25GBPS:
1644                 return 25000;
1645         case PHY_LINK_SPEED_40GBPS:
1646                 return 40000;
1647         }
1648         return 0;
1649 }
1650
1651 /* Uses synchronous mcc
1652  * Returns link_speed in Mbps
1653  */
1654 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1655                              u8 *link_status, u32 dom)
1656 {
1657         struct be_mcc_wrb *wrb;
1658         struct be_cmd_req_link_status *req;
1659         int status;
1660
1661         spin_lock_bh(&adapter->mcc_lock);
1662
1663         if (link_status)
1664                 *link_status = LINK_DOWN;
1665
1666         wrb = wrb_from_mccq(adapter);
1667         if (!wrb) {
1668                 status = -EBUSY;
1669                 goto err;
1670         }
1671         req = embedded_payload(wrb);
1672
1673         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1674                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1675                                sizeof(*req), wrb, NULL);
1676
1677         /* version 1 of the cmd is not supported only by BE2 */
1678         if (!BE2_chip(adapter))
1679                 req->hdr.version = 1;
1680
1681         req->hdr.domain = dom;
1682
1683         status = be_mcc_notify_wait(adapter);
1684         if (!status) {
1685                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1686
1687                 if (link_speed) {
1688                         *link_speed = resp->link_speed ?
1689                                       le16_to_cpu(resp->link_speed) * 10 :
1690                                       be_mac_to_link_speed(resp->mac_speed);
1691
1692                         if (!resp->logical_link_status)
1693                                 *link_speed = 0;
1694                 }
1695                 if (link_status)
1696                         *link_status = resp->logical_link_status;
1697         }
1698
1699 err:
1700         spin_unlock_bh(&adapter->mcc_lock);
1701         return status;
1702 }
1703
1704 /* Uses synchronous mcc */
1705 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1706 {
1707         struct be_mcc_wrb *wrb;
1708         struct be_cmd_req_get_cntl_addnl_attribs *req;
1709         int status = 0;
1710
1711         spin_lock_bh(&adapter->mcc_lock);
1712
1713         wrb = wrb_from_mccq(adapter);
1714         if (!wrb) {
1715                 status = -EBUSY;
1716                 goto err;
1717         }
1718         req = embedded_payload(wrb);
1719
1720         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1721                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1722                                sizeof(*req), wrb, NULL);
1723
1724         status = be_mcc_notify(adapter);
1725 err:
1726         spin_unlock_bh(&adapter->mcc_lock);
1727         return status;
1728 }
1729
1730 /* Uses synchronous mcc */
1731 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1732 {
1733         struct be_mcc_wrb wrb = {0};
1734         struct be_cmd_req_get_fat *req;
1735         int status;
1736
1737         req = embedded_payload(&wrb);
1738
1739         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1740                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1741                                &wrb, NULL);
1742         req->fat_operation = cpu_to_le32(QUERY_FAT);
1743         status = be_cmd_notify_wait(adapter, &wrb);
1744         if (!status) {
1745                 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1746
1747                 if (dump_size && resp->log_size)
1748                         *dump_size = le32_to_cpu(resp->log_size) -
1749                                         sizeof(u32);
1750         }
1751         return status;
1752 }
1753
1754 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1755 {
1756         struct be_dma_mem get_fat_cmd;
1757         struct be_mcc_wrb *wrb;
1758         struct be_cmd_req_get_fat *req;
1759         u32 offset = 0, total_size, buf_size,
1760                                 log_offset = sizeof(u32), payload_len;
1761         int status;
1762
1763         if (buf_len == 0)
1764                 return 0;
1765
1766         total_size = buf_len;
1767
1768         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1769         get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1770                                              get_fat_cmd.size,
1771                                              &get_fat_cmd.dma, GFP_ATOMIC);
1772         if (!get_fat_cmd.va)
1773                 return -ENOMEM;
1774
1775         spin_lock_bh(&adapter->mcc_lock);
1776
1777         while (total_size) {
1778                 buf_size = min(total_size, (u32)60*1024);
1779                 total_size -= buf_size;
1780
1781                 wrb = wrb_from_mccq(adapter);
1782                 if (!wrb) {
1783                         status = -EBUSY;
1784                         goto err;
1785                 }
1786                 req = get_fat_cmd.va;
1787
1788                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1789                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1790                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1791                                        wrb, &get_fat_cmd);
1792
1793                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1794                 req->read_log_offset = cpu_to_le32(log_offset);
1795                 req->read_log_length = cpu_to_le32(buf_size);
1796                 req->data_buffer_size = cpu_to_le32(buf_size);
1797
1798                 status = be_mcc_notify_wait(adapter);
1799                 if (!status) {
1800                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1801
1802                         memcpy(buf + offset,
1803                                resp->data_buffer,
1804                                le32_to_cpu(resp->read_log_length));
1805                 } else {
1806                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1807                         goto err;
1808                 }
1809                 offset += buf_size;
1810                 log_offset += buf_size;
1811         }
1812 err:
1813         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1814                           get_fat_cmd.va, get_fat_cmd.dma);
1815         spin_unlock_bh(&adapter->mcc_lock);
1816         return status;
1817 }
1818
1819 /* Uses synchronous mcc */
1820 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1821 {
1822         struct be_mcc_wrb *wrb;
1823         struct be_cmd_req_get_fw_version *req;
1824         int status;
1825
1826         spin_lock_bh(&adapter->mcc_lock);
1827
1828         wrb = wrb_from_mccq(adapter);
1829         if (!wrb) {
1830                 status = -EBUSY;
1831                 goto err;
1832         }
1833
1834         req = embedded_payload(wrb);
1835
1836         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1837                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1838                                NULL);
1839         status = be_mcc_notify_wait(adapter);
1840         if (!status) {
1841                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1842
1843                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1844                         sizeof(adapter->fw_ver));
1845                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1846                         sizeof(adapter->fw_on_flash));
1847         }
1848 err:
1849         spin_unlock_bh(&adapter->mcc_lock);
1850         return status;
1851 }
1852
1853 /* set the EQ delay interval of an EQ to specified value
1854  * Uses async mcc
1855  */
1856 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1857                                struct be_set_eqd *set_eqd, int num)
1858 {
1859         struct be_mcc_wrb *wrb;
1860         struct be_cmd_req_modify_eq_delay *req;
1861         int status = 0, i;
1862
1863         spin_lock_bh(&adapter->mcc_lock);
1864
1865         wrb = wrb_from_mccq(adapter);
1866         if (!wrb) {
1867                 status = -EBUSY;
1868                 goto err;
1869         }
1870         req = embedded_payload(wrb);
1871
1872         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1873                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1874                                NULL);
1875
1876         req->num_eq = cpu_to_le32(num);
1877         for (i = 0; i < num; i++) {
1878                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1879                 req->set_eqd[i].phase = 0;
1880                 req->set_eqd[i].delay_multiplier =
1881                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1882         }
1883
1884         status = be_mcc_notify(adapter);
1885 err:
1886         spin_unlock_bh(&adapter->mcc_lock);
1887         return status;
1888 }
1889
1890 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1891                       int num)
1892 {
1893         int num_eqs, i = 0;
1894
1895         while (num) {
1896                 num_eqs = min(num, 8);
1897                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1898                 i += num_eqs;
1899                 num -= num_eqs;
1900         }
1901
1902         return 0;
1903 }
1904
1905 /* Uses sycnhronous mcc */
1906 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1907                        u32 num, u32 domain)
1908 {
1909         struct be_mcc_wrb *wrb;
1910         struct be_cmd_req_vlan_config *req;
1911         int status;
1912
1913         spin_lock_bh(&adapter->mcc_lock);
1914
1915         wrb = wrb_from_mccq(adapter);
1916         if (!wrb) {
1917                 status = -EBUSY;
1918                 goto err;
1919         }
1920         req = embedded_payload(wrb);
1921
1922         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1923                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1924                                wrb, NULL);
1925         req->hdr.domain = domain;
1926
1927         req->interface_id = if_id;
1928         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1929         req->num_vlan = num;
1930         memcpy(req->normal_vlan, vtag_array,
1931                req->num_vlan * sizeof(vtag_array[0]));
1932
1933         status = be_mcc_notify_wait(adapter);
1934 err:
1935         spin_unlock_bh(&adapter->mcc_lock);
1936         return status;
1937 }
1938
1939 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1940 {
1941         struct be_mcc_wrb *wrb;
1942         struct be_dma_mem *mem = &adapter->rx_filter;
1943         struct be_cmd_req_rx_filter *req = mem->va;
1944         int status;
1945
1946         spin_lock_bh(&adapter->mcc_lock);
1947
1948         wrb = wrb_from_mccq(adapter);
1949         if (!wrb) {
1950                 status = -EBUSY;
1951                 goto err;
1952         }
1953         memset(req, 0, sizeof(*req));
1954         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1955                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1956                                wrb, mem);
1957
1958         req->if_id = cpu_to_le32(adapter->if_handle);
1959         req->if_flags_mask = cpu_to_le32(flags);
1960         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1961
1962         if (flags & BE_IF_FLAGS_MULTICAST) {
1963                 struct netdev_hw_addr *ha;
1964                 int i = 0;
1965
1966                 /* Reset mcast promisc mode if already set by setting mask
1967                  * and not setting flags field
1968                  */
1969                 req->if_flags_mask |=
1970                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1971                                     be_if_cap_flags(adapter));
1972                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1973                 netdev_for_each_mc_addr(ha, adapter->netdev)
1974                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1975         }
1976
1977         status = be_mcc_notify_wait(adapter);
1978 err:
1979         spin_unlock_bh(&adapter->mcc_lock);
1980         return status;
1981 }
1982
1983 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1984 {
1985         struct device *dev = &adapter->pdev->dev;
1986
1987         if ((flags & be_if_cap_flags(adapter)) != flags) {
1988                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1989                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1990                          be_if_cap_flags(adapter));
1991         }
1992         flags &= be_if_cap_flags(adapter);
1993         if (!flags)
1994                 return -ENOTSUPP;
1995
1996         return __be_cmd_rx_filter(adapter, flags, value);
1997 }
1998
1999 /* Uses synchrounous mcc */
2000 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2001 {
2002         struct be_mcc_wrb *wrb;
2003         struct be_cmd_req_set_flow_control *req;
2004         int status;
2005
2006         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2007                             CMD_SUBSYSTEM_COMMON))
2008                 return -EPERM;
2009
2010         spin_lock_bh(&adapter->mcc_lock);
2011
2012         wrb = wrb_from_mccq(adapter);
2013         if (!wrb) {
2014                 status = -EBUSY;
2015                 goto err;
2016         }
2017         req = embedded_payload(wrb);
2018
2019         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2020                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2021                                wrb, NULL);
2022
2023         req->hdr.version = 1;
2024         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2025         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2026
2027         status = be_mcc_notify_wait(adapter);
2028
2029 err:
2030         spin_unlock_bh(&adapter->mcc_lock);
2031
2032         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2033                 return  -EOPNOTSUPP;
2034
2035         return status;
2036 }
2037
2038 /* Uses sycn mcc */
2039 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2040 {
2041         struct be_mcc_wrb *wrb;
2042         struct be_cmd_req_get_flow_control *req;
2043         int status;
2044
2045         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2046                             CMD_SUBSYSTEM_COMMON))
2047                 return -EPERM;
2048
2049         spin_lock_bh(&adapter->mcc_lock);
2050
2051         wrb = wrb_from_mccq(adapter);
2052         if (!wrb) {
2053                 status = -EBUSY;
2054                 goto err;
2055         }
2056         req = embedded_payload(wrb);
2057
2058         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2059                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2060                                wrb, NULL);
2061
2062         status = be_mcc_notify_wait(adapter);
2063         if (!status) {
2064                 struct be_cmd_resp_get_flow_control *resp =
2065                                                 embedded_payload(wrb);
2066
2067                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2068                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2069         }
2070
2071 err:
2072         spin_unlock_bh(&adapter->mcc_lock);
2073         return status;
2074 }
2075
2076 /* Uses mbox */
2077 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2078 {
2079         struct be_mcc_wrb *wrb;
2080         struct be_cmd_req_query_fw_cfg *req;
2081         int status;
2082
2083         if (mutex_lock_interruptible(&adapter->mbox_lock))
2084                 return -1;
2085
2086         wrb = wrb_from_mbox(adapter);
2087         req = embedded_payload(wrb);
2088
2089         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2090                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2091                                sizeof(*req), wrb, NULL);
2092
2093         status = be_mbox_notify_wait(adapter);
2094         if (!status) {
2095                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2096
2097                 adapter->port_num = le32_to_cpu(resp->phys_port);
2098                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2099                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2100                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2101                 dev_info(&adapter->pdev->dev,
2102                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2103                          adapter->function_mode, adapter->function_caps);
2104         }
2105
2106         mutex_unlock(&adapter->mbox_lock);
2107         return status;
2108 }
2109
2110 /* Uses mbox */
2111 int be_cmd_reset_function(struct be_adapter *adapter)
2112 {
2113         struct be_mcc_wrb *wrb;
2114         struct be_cmd_req_hdr *req;
2115         int status;
2116
2117         if (lancer_chip(adapter)) {
2118                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2119                           adapter->db + SLIPORT_CONTROL_OFFSET);
2120                 status = lancer_wait_ready(adapter);
2121                 if (status)
2122                         dev_err(&adapter->pdev->dev,
2123                                 "Adapter in non recoverable error\n");
2124                 return status;
2125         }
2126
2127         if (mutex_lock_interruptible(&adapter->mbox_lock))
2128                 return -1;
2129
2130         wrb = wrb_from_mbox(adapter);
2131         req = embedded_payload(wrb);
2132
2133         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2134                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2135                                NULL);
2136
2137         status = be_mbox_notify_wait(adapter);
2138
2139         mutex_unlock(&adapter->mbox_lock);
2140         return status;
2141 }
2142
2143 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2144                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2145 {
2146         struct be_mcc_wrb *wrb;
2147         struct be_cmd_req_rss_config *req;
2148         int status;
2149
2150         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2151                 return 0;
2152
2153         spin_lock_bh(&adapter->mcc_lock);
2154
2155         wrb = wrb_from_mccq(adapter);
2156         if (!wrb) {
2157                 status = -EBUSY;
2158                 goto err;
2159         }
2160         req = embedded_payload(wrb);
2161
2162         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2163                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2164
2165         req->if_id = cpu_to_le32(adapter->if_handle);
2166         req->enable_rss = cpu_to_le16(rss_hash_opts);
2167         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2168
2169         if (!BEx_chip(adapter))
2170                 req->hdr.version = 1;
2171
2172         memcpy(req->cpu_table, rsstable, table_size);
2173         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2174         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2175
2176         status = be_mcc_notify_wait(adapter);
2177 err:
2178         spin_unlock_bh(&adapter->mcc_lock);
2179         return status;
2180 }
2181
2182 /* Uses sync mcc */
2183 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2184                             u8 bcn, u8 sts, u8 state)
2185 {
2186         struct be_mcc_wrb *wrb;
2187         struct be_cmd_req_enable_disable_beacon *req;
2188         int status;
2189
2190         spin_lock_bh(&adapter->mcc_lock);
2191
2192         wrb = wrb_from_mccq(adapter);
2193         if (!wrb) {
2194                 status = -EBUSY;
2195                 goto err;
2196         }
2197         req = embedded_payload(wrb);
2198
2199         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2200                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2201                                sizeof(*req), wrb, NULL);
2202
2203         req->port_num = port_num;
2204         req->beacon_state = state;
2205         req->beacon_duration = bcn;
2206         req->status_duration = sts;
2207
2208         status = be_mcc_notify_wait(adapter);
2209
2210 err:
2211         spin_unlock_bh(&adapter->mcc_lock);
2212         return status;
2213 }
2214
2215 /* Uses sync mcc */
2216 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2217 {
2218         struct be_mcc_wrb *wrb;
2219         struct be_cmd_req_get_beacon_state *req;
2220         int status;
2221
2222         spin_lock_bh(&adapter->mcc_lock);
2223
2224         wrb = wrb_from_mccq(adapter);
2225         if (!wrb) {
2226                 status = -EBUSY;
2227                 goto err;
2228         }
2229         req = embedded_payload(wrb);
2230
2231         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2232                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2233                                wrb, NULL);
2234
2235         req->port_num = port_num;
2236
2237         status = be_mcc_notify_wait(adapter);
2238         if (!status) {
2239                 struct be_cmd_resp_get_beacon_state *resp =
2240                                                 embedded_payload(wrb);
2241
2242                 *state = resp->beacon_state;
2243         }
2244
2245 err:
2246         spin_unlock_bh(&adapter->mcc_lock);
2247         return status;
2248 }
2249
2250 /* Uses sync mcc */
2251 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2252                                       u8 page_num, u8 *data)
2253 {
2254         struct be_dma_mem cmd;
2255         struct be_mcc_wrb *wrb;
2256         struct be_cmd_req_port_type *req;
2257         int status;
2258
2259         if (page_num > TR_PAGE_A2)
2260                 return -EINVAL;
2261
2262         cmd.size = sizeof(struct be_cmd_resp_port_type);
2263         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2264                                      GFP_ATOMIC);
2265         if (!cmd.va) {
2266                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2267                 return -ENOMEM;
2268         }
2269
2270         spin_lock_bh(&adapter->mcc_lock);
2271
2272         wrb = wrb_from_mccq(adapter);
2273         if (!wrb) {
2274                 status = -EBUSY;
2275                 goto err;
2276         }
2277         req = cmd.va;
2278
2279         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2280                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2281                                cmd.size, wrb, &cmd);
2282
2283         req->port = cpu_to_le32(adapter->hba_port_num);
2284         req->page_num = cpu_to_le32(page_num);
2285         status = be_mcc_notify_wait(adapter);
2286         if (!status) {
2287                 struct be_cmd_resp_port_type *resp = cmd.va;
2288
2289                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2290         }
2291 err:
2292         spin_unlock_bh(&adapter->mcc_lock);
2293         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2294         return status;
2295 }
2296
2297 static int lancer_cmd_write_object(struct be_adapter *adapter,
2298                                    struct be_dma_mem *cmd, u32 data_size,
2299                                    u32 data_offset, const char *obj_name,
2300                                    u32 *data_written, u8 *change_status,
2301                                    u8 *addn_status)
2302 {
2303         struct be_mcc_wrb *wrb;
2304         struct lancer_cmd_req_write_object *req;
2305         struct lancer_cmd_resp_write_object *resp;
2306         void *ctxt = NULL;
2307         int status;
2308
2309         spin_lock_bh(&adapter->mcc_lock);
2310         adapter->flash_status = 0;
2311
2312         wrb = wrb_from_mccq(adapter);
2313         if (!wrb) {
2314                 status = -EBUSY;
2315                 goto err_unlock;
2316         }
2317
2318         req = embedded_payload(wrb);
2319
2320         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2321                                OPCODE_COMMON_WRITE_OBJECT,
2322                                sizeof(struct lancer_cmd_req_write_object), wrb,
2323                                NULL);
2324
2325         ctxt = &req->context;
2326         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2327                       write_length, ctxt, data_size);
2328
2329         if (data_size == 0)
2330                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2331                               eof, ctxt, 1);
2332         else
2333                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2334                               eof, ctxt, 0);
2335
2336         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2337         req->write_offset = cpu_to_le32(data_offset);
2338         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2339         req->descriptor_count = cpu_to_le32(1);
2340         req->buf_len = cpu_to_le32(data_size);
2341         req->addr_low = cpu_to_le32((cmd->dma +
2342                                      sizeof(struct lancer_cmd_req_write_object))
2343                                     & 0xFFFFFFFF);
2344         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2345                                 sizeof(struct lancer_cmd_req_write_object)));
2346
2347         status = be_mcc_notify(adapter);
2348         if (status)
2349                 goto err_unlock;
2350
2351         spin_unlock_bh(&adapter->mcc_lock);
2352
2353         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2354                                          msecs_to_jiffies(60000)))
2355                 status = -ETIMEDOUT;
2356         else
2357                 status = adapter->flash_status;
2358
2359         resp = embedded_payload(wrb);
2360         if (!status) {
2361                 *data_written = le32_to_cpu(resp->actual_write_len);
2362                 *change_status = resp->change_status;
2363         } else {
2364                 *addn_status = resp->additional_status;
2365         }
2366
2367         return status;
2368
2369 err_unlock:
2370         spin_unlock_bh(&adapter->mcc_lock);
2371         return status;
2372 }
2373
2374 int be_cmd_query_cable_type(struct be_adapter *adapter)
2375 {
2376         u8 page_data[PAGE_DATA_LEN];
2377         int status;
2378
2379         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2380                                                    page_data);
2381         if (!status) {
2382                 switch (adapter->phy.interface_type) {
2383                 case PHY_TYPE_QSFP:
2384                         adapter->phy.cable_type =
2385                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2386                         break;
2387                 case PHY_TYPE_SFP_PLUS_10GB:
2388                         adapter->phy.cable_type =
2389                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2390                         break;
2391                 default:
2392                         adapter->phy.cable_type = 0;
2393                         break;
2394                 }
2395         }
2396         return status;
2397 }
2398
2399 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2400 {
2401         u8 page_data[PAGE_DATA_LEN];
2402         int status;
2403
2404         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2405                                                    page_data);
2406         if (!status) {
2407                 strlcpy(adapter->phy.vendor_name, page_data +
2408                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2409                 strlcpy(adapter->phy.vendor_pn,
2410                         page_data + SFP_VENDOR_PN_OFFSET,
2411                         SFP_VENDOR_NAME_LEN - 1);
2412         }
2413
2414         return status;
2415 }
2416
2417 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2418                                     const char *obj_name)
2419 {
2420         struct lancer_cmd_req_delete_object *req;
2421         struct be_mcc_wrb *wrb;
2422         int status;
2423
2424         spin_lock_bh(&adapter->mcc_lock);
2425
2426         wrb = wrb_from_mccq(adapter);
2427         if (!wrb) {
2428                 status = -EBUSY;
2429                 goto err;
2430         }
2431
2432         req = embedded_payload(wrb);
2433
2434         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2435                                OPCODE_COMMON_DELETE_OBJECT,
2436                                sizeof(*req), wrb, NULL);
2437
2438         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2439
2440         status = be_mcc_notify_wait(adapter);
2441 err:
2442         spin_unlock_bh(&adapter->mcc_lock);
2443         return status;
2444 }
2445
2446 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2447                            u32 data_size, u32 data_offset, const char *obj_name,
2448                            u32 *data_read, u32 *eof, u8 *addn_status)
2449 {
2450         struct be_mcc_wrb *wrb;
2451         struct lancer_cmd_req_read_object *req;
2452         struct lancer_cmd_resp_read_object *resp;
2453         int status;
2454
2455         spin_lock_bh(&adapter->mcc_lock);
2456
2457         wrb = wrb_from_mccq(adapter);
2458         if (!wrb) {
2459                 status = -EBUSY;
2460                 goto err_unlock;
2461         }
2462
2463         req = embedded_payload(wrb);
2464
2465         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2466                                OPCODE_COMMON_READ_OBJECT,
2467                                sizeof(struct lancer_cmd_req_read_object), wrb,
2468                                NULL);
2469
2470         req->desired_read_len = cpu_to_le32(data_size);
2471         req->read_offset = cpu_to_le32(data_offset);
2472         strcpy(req->object_name, obj_name);
2473         req->descriptor_count = cpu_to_le32(1);
2474         req->buf_len = cpu_to_le32(data_size);
2475         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2476         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2477
2478         status = be_mcc_notify_wait(adapter);
2479
2480         resp = embedded_payload(wrb);
2481         if (!status) {
2482                 *data_read = le32_to_cpu(resp->actual_read_len);
2483                 *eof = le32_to_cpu(resp->eof);
2484         } else {
2485                 *addn_status = resp->additional_status;
2486         }
2487
2488 err_unlock:
2489         spin_unlock_bh(&adapter->mcc_lock);
2490         return status;
2491 }
2492
2493 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2494                                  struct be_dma_mem *cmd, u32 flash_type,
2495                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2496 {
2497         struct be_mcc_wrb *wrb;
2498         struct be_cmd_write_flashrom *req;
2499         int status;
2500
2501         spin_lock_bh(&adapter->mcc_lock);
2502         adapter->flash_status = 0;
2503
2504         wrb = wrb_from_mccq(adapter);
2505         if (!wrb) {
2506                 status = -EBUSY;
2507                 goto err_unlock;
2508         }
2509         req = cmd->va;
2510
2511         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2512                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2513                                cmd);
2514
2515         req->params.op_type = cpu_to_le32(flash_type);
2516         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2517                 req->params.offset = cpu_to_le32(img_offset);
2518
2519         req->params.op_code = cpu_to_le32(flash_opcode);
2520         req->params.data_buf_size = cpu_to_le32(buf_size);
2521
2522         status = be_mcc_notify(adapter);
2523         if (status)
2524                 goto err_unlock;
2525
2526         spin_unlock_bh(&adapter->mcc_lock);
2527
2528         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2529                                          msecs_to_jiffies(40000)))
2530                 status = -ETIMEDOUT;
2531         else
2532                 status = adapter->flash_status;
2533
2534         return status;
2535
2536 err_unlock:
2537         spin_unlock_bh(&adapter->mcc_lock);
2538         return status;
2539 }
2540
2541 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2542                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2543 {
2544         struct be_cmd_read_flash_crc *req;
2545         struct be_mcc_wrb *wrb;
2546         int status;
2547
2548         spin_lock_bh(&adapter->mcc_lock);
2549
2550         wrb = wrb_from_mccq(adapter);
2551         if (!wrb) {
2552                 status = -EBUSY;
2553                 goto err;
2554         }
2555         req = embedded_payload(wrb);
2556
2557         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2558                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2559                                wrb, NULL);
2560
2561         req->params.op_type = cpu_to_le32(img_optype);
2562         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2563                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2564         else
2565                 req->params.offset = cpu_to_le32(crc_offset);
2566
2567         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2568         req->params.data_buf_size = cpu_to_le32(0x4);
2569
2570         status = be_mcc_notify_wait(adapter);
2571         if (!status)
2572                 memcpy(flashed_crc, req->crc, 4);
2573
2574 err:
2575         spin_unlock_bh(&adapter->mcc_lock);
2576         return status;
2577 }
2578
2579 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2580
2581 static bool phy_flashing_required(struct be_adapter *adapter)
2582 {
2583         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2584                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2585 }
2586
2587 static bool is_comp_in_ufi(struct be_adapter *adapter,
2588                            struct flash_section_info *fsec, int type)
2589 {
2590         int i = 0, img_type = 0;
2591         struct flash_section_info_g2 *fsec_g2 = NULL;
2592
2593         if (BE2_chip(adapter))
2594                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2595
2596         for (i = 0; i < MAX_FLASH_COMP; i++) {
2597                 if (fsec_g2)
2598                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2599                 else
2600                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2601
2602                 if (img_type == type)
2603                         return true;
2604         }
2605         return false;
2606 }
2607
2608 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2609                                                 int header_size,
2610                                                 const struct firmware *fw)
2611 {
2612         struct flash_section_info *fsec = NULL;
2613         const u8 *p = fw->data;
2614
2615         p += header_size;
2616         while (p < (fw->data + fw->size)) {
2617                 fsec = (struct flash_section_info *)p;
2618                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2619                         return fsec;
2620                 p += 32;
2621         }
2622         return NULL;
2623 }
2624
2625 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2626                               u32 img_offset, u32 img_size, int hdr_size,
2627                               u16 img_optype, bool *crc_match)
2628 {
2629         u32 crc_offset;
2630         int status;
2631         u8 crc[4];
2632
2633         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2634                                       img_size - 4);
2635         if (status)
2636                 return status;
2637
2638         crc_offset = hdr_size + img_offset + img_size - 4;
2639
2640         /* Skip flashing, if crc of flashed region matches */
2641         if (!memcmp(crc, p + crc_offset, 4))
2642                 *crc_match = true;
2643         else
2644                 *crc_match = false;
2645
2646         return status;
2647 }
2648
2649 static int be_flash(struct be_adapter *adapter, const u8 *img,
2650                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2651                     u32 img_offset)
2652 {
2653         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2654         struct be_cmd_write_flashrom *req = flash_cmd->va;
2655         int status;
2656
2657         while (total_bytes) {
2658                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2659
2660                 total_bytes -= num_bytes;
2661
2662                 if (!total_bytes) {
2663                         if (optype == OPTYPE_PHY_FW)
2664                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2665                         else
2666                                 flash_op = FLASHROM_OPER_FLASH;
2667                 } else {
2668                         if (optype == OPTYPE_PHY_FW)
2669                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2670                         else
2671                                 flash_op = FLASHROM_OPER_SAVE;
2672                 }
2673
2674                 memcpy(req->data_buf, img, num_bytes);
2675                 img += num_bytes;
2676                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2677                                                flash_op, img_offset +
2678                                                bytes_sent, num_bytes);
2679                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2680                     optype == OPTYPE_PHY_FW)
2681                         break;
2682                 else if (status)
2683                         return status;
2684
2685                 bytes_sent += num_bytes;
2686         }
2687         return 0;
2688 }
2689
2690 /* For BE2, BE3 and BE3-R */
2691 static int be_flash_BEx(struct be_adapter *adapter,
2692                         const struct firmware *fw,
2693                         struct be_dma_mem *flash_cmd, int num_of_images)
2694 {
2695         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2696         struct device *dev = &adapter->pdev->dev;
2697         struct flash_section_info *fsec = NULL;
2698         int status, i, filehdr_size, num_comp;
2699         const struct flash_comp *pflashcomp;
2700         bool crc_match;
2701         const u8 *p;
2702
2703         struct flash_comp gen3_flash_types[] = {
2704                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2705                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2706                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2707                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2708                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2709                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2710                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2711                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2712                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2713                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2714                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2715                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2716                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2717                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2718                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2719                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2720                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2721                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2722                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2723                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2724         };
2725
2726         struct flash_comp gen2_flash_types[] = {
2727                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2728                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2729                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2730                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2731                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2732                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2733                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2734                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2735                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2736                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2737                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2738                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2739                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2740                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2741                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2742                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2743         };
2744
2745         if (BE3_chip(adapter)) {
2746                 pflashcomp = gen3_flash_types;
2747                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2748                 num_comp = ARRAY_SIZE(gen3_flash_types);
2749         } else {
2750                 pflashcomp = gen2_flash_types;
2751                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2752                 num_comp = ARRAY_SIZE(gen2_flash_types);
2753                 img_hdrs_size = 0;
2754         }
2755
2756         /* Get flash section info*/
2757         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2758         if (!fsec) {
2759                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2760                 return -1;
2761         }
2762         for (i = 0; i < num_comp; i++) {
2763                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2764                         continue;
2765
2766                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2767                     memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2768                         continue;
2769
2770                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2771                     !phy_flashing_required(adapter))
2772                         continue;
2773
2774                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2775                         status = be_check_flash_crc(adapter, fw->data,
2776                                                     pflashcomp[i].offset,
2777                                                     pflashcomp[i].size,
2778                                                     filehdr_size +
2779                                                     img_hdrs_size,
2780                                                     OPTYPE_REDBOOT, &crc_match);
2781                         if (status) {
2782                                 dev_err(dev,
2783                                         "Could not get CRC for 0x%x region\n",
2784                                         pflashcomp[i].optype);
2785                                 continue;
2786                         }
2787
2788                         if (crc_match)
2789                                 continue;
2790                 }
2791
2792                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2793                         img_hdrs_size;
2794                 if (p + pflashcomp[i].size > fw->data + fw->size)
2795                         return -1;
2796
2797                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2798                                   pflashcomp[i].size, 0);
2799                 if (status) {
2800                         dev_err(dev, "Flashing section type 0x%x failed\n",
2801                                 pflashcomp[i].img_type);
2802                         return status;
2803                 }
2804         }
2805         return 0;
2806 }
2807
2808 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2809 {
2810         u32 img_type = le32_to_cpu(fsec_entry.type);
2811         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2812
2813         if (img_optype != 0xFFFF)
2814                 return img_optype;
2815
2816         switch (img_type) {
2817         case IMAGE_FIRMWARE_ISCSI:
2818                 img_optype = OPTYPE_ISCSI_ACTIVE;
2819                 break;
2820         case IMAGE_BOOT_CODE:
2821                 img_optype = OPTYPE_REDBOOT;
2822                 break;
2823         case IMAGE_OPTION_ROM_ISCSI:
2824                 img_optype = OPTYPE_BIOS;
2825                 break;
2826         case IMAGE_OPTION_ROM_PXE:
2827                 img_optype = OPTYPE_PXE_BIOS;
2828                 break;
2829         case IMAGE_OPTION_ROM_FCOE:
2830                 img_optype = OPTYPE_FCOE_BIOS;
2831                 break;
2832         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2833                 img_optype = OPTYPE_ISCSI_BACKUP;
2834                 break;
2835         case IMAGE_NCSI:
2836                 img_optype = OPTYPE_NCSI_FW;
2837                 break;
2838         case IMAGE_FLASHISM_JUMPVECTOR:
2839                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2840                 break;
2841         case IMAGE_FIRMWARE_PHY:
2842                 img_optype = OPTYPE_SH_PHY_FW;
2843                 break;
2844         case IMAGE_REDBOOT_DIR:
2845                 img_optype = OPTYPE_REDBOOT_DIR;
2846                 break;
2847         case IMAGE_REDBOOT_CONFIG:
2848                 img_optype = OPTYPE_REDBOOT_CONFIG;
2849                 break;
2850         case IMAGE_UFI_DIR:
2851                 img_optype = OPTYPE_UFI_DIR;
2852                 break;
2853         default:
2854                 break;
2855         }
2856
2857         return img_optype;
2858 }
2859
2860 static int be_flash_skyhawk(struct be_adapter *adapter,
2861                             const struct firmware *fw,
2862                             struct be_dma_mem *flash_cmd, int num_of_images)
2863 {
2864         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2865         bool crc_match, old_fw_img, flash_offset_support = true;
2866         struct device *dev = &adapter->pdev->dev;
2867         struct flash_section_info *fsec = NULL;
2868         u32 img_offset, img_size, img_type;
2869         u16 img_optype, flash_optype;
2870         int status, i, filehdr_size;
2871         const u8 *p;
2872
2873         filehdr_size = sizeof(struct flash_file_hdr_g3);
2874         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2875         if (!fsec) {
2876                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2877                 return -EINVAL;
2878         }
2879
2880 retry_flash:
2881         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2882                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2883                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2884                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2885                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2886                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2887
2888                 if (img_optype == 0xFFFF)
2889                         continue;
2890
2891                 if (flash_offset_support)
2892                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2893                 else
2894                         flash_optype = img_optype;
2895
2896                 /* Don't bother verifying CRC if an old FW image is being
2897                  * flashed
2898                  */
2899                 if (old_fw_img)
2900                         goto flash;
2901
2902                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2903                                             img_size, filehdr_size +
2904                                             img_hdrs_size, flash_optype,
2905                                             &crc_match);
2906                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2907                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2908                         /* The current FW image on the card does not support
2909                          * OFFSET based flashing. Retry using older mechanism
2910                          * of OPTYPE based flashing
2911                          */
2912                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2913                                 flash_offset_support = false;
2914                                 goto retry_flash;
2915                         }
2916
2917                         /* The current FW image on the card does not recognize
2918                          * the new FLASH op_type. The FW download is partially
2919                          * complete. Reboot the server now to enable FW image
2920                          * to recognize the new FLASH op_type. To complete the
2921                          * remaining process, download the same FW again after
2922                          * the reboot.
2923                          */
2924                         dev_err(dev, "Flash incomplete. Reset the server\n");
2925                         dev_err(dev, "Download FW image again after reset\n");
2926                         return -EAGAIN;
2927                 } else if (status) {
2928                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2929                                 img_optype);
2930                         return -EFAULT;
2931                 }
2932
2933                 if (crc_match)
2934                         continue;
2935
2936 flash:
2937                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2938                 if (p + img_size > fw->data + fw->size)
2939                         return -1;
2940
2941                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2942                                   img_offset);
2943
2944                 /* The current FW image on the card does not support OFFSET
2945                  * based flashing. Retry using older mechanism of OPTYPE based
2946                  * flashing
2947                  */
2948                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2949                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2950                         flash_offset_support = false;
2951                         goto retry_flash;
2952                 }
2953
2954                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2955                  * UFI_DIR region
2956                  */
2957                 if (old_fw_img &&
2958                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2959                      (img_optype == OPTYPE_UFI_DIR &&
2960                       base_status(status) == MCC_STATUS_FAILED))) {
2961                         continue;
2962                 } else if (status) {
2963                         dev_err(dev, "Flashing section type 0x%x failed\n",
2964                                 img_type);
2965
2966                         switch (addl_status(status)) {
2967                         case MCC_ADDL_STATUS_MISSING_SIGNATURE:
2968                                 dev_err(dev,
2969                                         "Digital signature missing in FW\n");
2970                                 return -EINVAL;
2971                         case MCC_ADDL_STATUS_INVALID_SIGNATURE:
2972                                 dev_err(dev,
2973                                         "Invalid digital signature in FW\n");
2974                                 return -EINVAL;
2975                         default:
2976                                 return -EFAULT;
2977                         }
2978                 }
2979         }
2980         return 0;
2981 }
2982
2983 int lancer_fw_download(struct be_adapter *adapter,
2984                        const struct firmware *fw)
2985 {
2986         struct device *dev = &adapter->pdev->dev;
2987         struct be_dma_mem flash_cmd;
2988         const u8 *data_ptr = NULL;
2989         u8 *dest_image_ptr = NULL;
2990         size_t image_size = 0;
2991         u32 chunk_size = 0;
2992         u32 data_written = 0;
2993         u32 offset = 0;
2994         int status = 0;
2995         u8 add_status = 0;
2996         u8 change_status;
2997
2998         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
2999                 dev_err(dev, "FW image size should be multiple of 4\n");
3000                 return -EINVAL;
3001         }
3002
3003         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3004                                 + LANCER_FW_DOWNLOAD_CHUNK;
3005         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3006                                            &flash_cmd.dma, GFP_KERNEL);
3007         if (!flash_cmd.va)
3008                 return -ENOMEM;
3009
3010         dest_image_ptr = flash_cmd.va +
3011                                 sizeof(struct lancer_cmd_req_write_object);
3012         image_size = fw->size;
3013         data_ptr = fw->data;
3014
3015         while (image_size) {
3016                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3017
3018                 /* Copy the image chunk content. */
3019                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3020
3021                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3022                                                  chunk_size, offset,
3023                                                  LANCER_FW_DOWNLOAD_LOCATION,
3024                                                  &data_written, &change_status,
3025                                                  &add_status);
3026                 if (status)
3027                         break;
3028
3029                 offset += data_written;
3030                 data_ptr += data_written;
3031                 image_size -= data_written;
3032         }
3033
3034         if (!status) {
3035                 /* Commit the FW written */
3036                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3037                                                  0, offset,
3038                                                  LANCER_FW_DOWNLOAD_LOCATION,
3039                                                  &data_written, &change_status,
3040                                                  &add_status);
3041         }
3042
3043         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3044         if (status) {
3045                 dev_err(dev, "Firmware load error\n");
3046                 return be_cmd_status(status);
3047         }
3048
3049         dev_info(dev, "Firmware flashed successfully\n");
3050
3051         if (change_status == LANCER_FW_RESET_NEEDED) {
3052                 dev_info(dev, "Resetting adapter to activate new FW\n");
3053                 status = lancer_physdev_ctrl(adapter,
3054                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3055                 if (status) {
3056                         dev_err(dev, "Adapter busy, could not reset FW\n");
3057                         dev_err(dev, "Reboot server to activate new FW\n");
3058                 }
3059         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3060                 dev_info(dev, "Reboot server to activate new FW\n");
3061         }
3062
3063         return 0;
3064 }
3065
3066 /* Check if the flash image file is compatible with the adapter that
3067  * is being flashed.
3068  */
3069 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3070                                        struct flash_file_hdr_g3 *fhdr)
3071 {
3072         if (!fhdr) {
3073                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3074                 return false;
3075         }
3076
3077         /* First letter of the build version is used to identify
3078          * which chip this image file is meant for.
3079          */
3080         switch (fhdr->build[0]) {
3081         case BLD_STR_UFI_TYPE_SH:
3082                 if (!skyhawk_chip(adapter))
3083                         return false;
3084                 break;
3085         case BLD_STR_UFI_TYPE_BE3:
3086                 if (!BE3_chip(adapter))
3087                         return false;
3088                 break;
3089         case BLD_STR_UFI_TYPE_BE2:
3090                 if (!BE2_chip(adapter))
3091                         return false;
3092                 break;
3093         default:
3094                 return false;
3095         }
3096
3097         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3098          * asic_rev of the chips it is compatible with.
3099          * When asic_type_rev is 0 the image is compatible only with
3100          * pre-BE3-R chips (asic_rev < 0x10)
3101          */
3102         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3103                 return adapter->asic_rev < 0x10;
3104         else
3105                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3106 }
3107
3108 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3109 {
3110         struct device *dev = &adapter->pdev->dev;
3111         struct flash_file_hdr_g3 *fhdr3;
3112         struct image_hdr *img_hdr_ptr;
3113         int status = 0, i, num_imgs;
3114         struct be_dma_mem flash_cmd;
3115
3116         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3117         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3118                 dev_err(dev, "Flash image is not compatible with adapter\n");
3119                 return -EINVAL;
3120         }
3121
3122         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3123         flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3124                                            GFP_KERNEL);
3125         if (!flash_cmd.va)
3126                 return -ENOMEM;
3127
3128         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3129         for (i = 0; i < num_imgs; i++) {
3130                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3131                                 (sizeof(struct flash_file_hdr_g3) +
3132                                  i * sizeof(struct image_hdr)));
3133                 if (!BE2_chip(adapter) &&
3134                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3135                         continue;
3136
3137                 if (skyhawk_chip(adapter))
3138                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3139                                                   num_imgs);
3140                 else
3141                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3142                                               num_imgs);
3143         }
3144
3145         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3146         if (!status)
3147                 dev_info(dev, "Firmware flashed successfully\n");
3148
3149         return status;
3150 }
3151
3152 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3153                             struct be_dma_mem *nonemb_cmd)
3154 {
3155         struct be_mcc_wrb *wrb;
3156         struct be_cmd_req_acpi_wol_magic_config *req;
3157         int status;
3158
3159         spin_lock_bh(&adapter->mcc_lock);
3160
3161         wrb = wrb_from_mccq(adapter);
3162         if (!wrb) {
3163                 status = -EBUSY;
3164                 goto err;
3165         }
3166         req = nonemb_cmd->va;
3167
3168         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3169                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3170                                wrb, nonemb_cmd);
3171         memcpy(req->magic_mac, mac, ETH_ALEN);
3172
3173         status = be_mcc_notify_wait(adapter);
3174
3175 err:
3176         spin_unlock_bh(&adapter->mcc_lock);
3177         return status;
3178 }
3179
3180 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3181                         u8 loopback_type, u8 enable)
3182 {
3183         struct be_mcc_wrb *wrb;
3184         struct be_cmd_req_set_lmode *req;
3185         int status;
3186
3187         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3188                             CMD_SUBSYSTEM_LOWLEVEL))
3189                 return -EPERM;
3190
3191         spin_lock_bh(&adapter->mcc_lock);
3192
3193         wrb = wrb_from_mccq(adapter);
3194         if (!wrb) {
3195                 status = -EBUSY;
3196                 goto err_unlock;
3197         }
3198
3199         req = embedded_payload(wrb);
3200
3201         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3202                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3203                                wrb, NULL);
3204
3205         req->src_port = port_num;
3206         req->dest_port = port_num;
3207         req->loopback_type = loopback_type;
3208         req->loopback_state = enable;
3209
3210         status = be_mcc_notify(adapter);
3211         if (status)
3212                 goto err_unlock;
3213
3214         spin_unlock_bh(&adapter->mcc_lock);
3215
3216         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3217                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3218                 status = -ETIMEDOUT;
3219
3220         return status;
3221
3222 err_unlock:
3223         spin_unlock_bh(&adapter->mcc_lock);
3224         return status;
3225 }
3226
3227 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3228                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3229                          u64 pattern)
3230 {
3231         struct be_mcc_wrb *wrb;
3232         struct be_cmd_req_loopback_test *req;
3233         struct be_cmd_resp_loopback_test *resp;
3234         int status;
3235
3236         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3237                             CMD_SUBSYSTEM_LOWLEVEL))
3238                 return -EPERM;
3239
3240         spin_lock_bh(&adapter->mcc_lock);
3241
3242         wrb = wrb_from_mccq(adapter);
3243         if (!wrb) {
3244                 status = -EBUSY;
3245                 goto err;
3246         }
3247
3248         req = embedded_payload(wrb);
3249
3250         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3251                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3252                                NULL);
3253
3254         req->hdr.timeout = cpu_to_le32(15);
3255         req->pattern = cpu_to_le64(pattern);
3256         req->src_port = cpu_to_le32(port_num);
3257         req->dest_port = cpu_to_le32(port_num);
3258         req->pkt_size = cpu_to_le32(pkt_size);
3259         req->num_pkts = cpu_to_le32(num_pkts);
3260         req->loopback_type = cpu_to_le32(loopback_type);
3261
3262         status = be_mcc_notify(adapter);
3263         if (status)
3264                 goto err;
3265
3266         spin_unlock_bh(&adapter->mcc_lock);
3267
3268         wait_for_completion(&adapter->et_cmd_compl);
3269         resp = embedded_payload(wrb);
3270         status = le32_to_cpu(resp->status);
3271
3272         return status;
3273 err:
3274         spin_unlock_bh(&adapter->mcc_lock);
3275         return status;
3276 }
3277
3278 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3279                         u32 byte_cnt, struct be_dma_mem *cmd)
3280 {
3281         struct be_mcc_wrb *wrb;
3282         struct be_cmd_req_ddrdma_test *req;
3283         int status;
3284         int i, j = 0;
3285
3286         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3287                             CMD_SUBSYSTEM_LOWLEVEL))
3288                 return -EPERM;
3289
3290         spin_lock_bh(&adapter->mcc_lock);
3291
3292         wrb = wrb_from_mccq(adapter);
3293         if (!wrb) {
3294                 status = -EBUSY;
3295                 goto err;
3296         }
3297         req = cmd->va;
3298         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3299                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3300                                cmd);
3301
3302         req->pattern = cpu_to_le64(pattern);
3303         req->byte_count = cpu_to_le32(byte_cnt);
3304         for (i = 0; i < byte_cnt; i++) {
3305                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3306                 j++;
3307                 if (j > 7)
3308                         j = 0;
3309         }
3310
3311         status = be_mcc_notify_wait(adapter);
3312
3313         if (!status) {
3314                 struct be_cmd_resp_ddrdma_test *resp;
3315
3316                 resp = cmd->va;
3317                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3318                     resp->snd_err) {
3319                         status = -1;
3320                 }
3321         }
3322
3323 err:
3324         spin_unlock_bh(&adapter->mcc_lock);
3325         return status;
3326 }
3327
3328 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3329                             struct be_dma_mem *nonemb_cmd)
3330 {
3331         struct be_mcc_wrb *wrb;
3332         struct be_cmd_req_seeprom_read *req;
3333         int status;
3334
3335         spin_lock_bh(&adapter->mcc_lock);
3336
3337         wrb = wrb_from_mccq(adapter);
3338         if (!wrb) {
3339                 status = -EBUSY;
3340                 goto err;
3341         }
3342         req = nonemb_cmd->va;
3343
3344         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3345                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3346                                nonemb_cmd);
3347
3348         status = be_mcc_notify_wait(adapter);
3349
3350 err:
3351         spin_unlock_bh(&adapter->mcc_lock);
3352         return status;
3353 }
3354
3355 int be_cmd_get_phy_info(struct be_adapter *adapter)
3356 {
3357         struct be_mcc_wrb *wrb;
3358         struct be_cmd_req_get_phy_info *req;
3359         struct be_dma_mem cmd;
3360         int status;
3361
3362         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3363                             CMD_SUBSYSTEM_COMMON))
3364                 return -EPERM;
3365
3366         spin_lock_bh(&adapter->mcc_lock);
3367
3368         wrb = wrb_from_mccq(adapter);
3369         if (!wrb) {
3370                 status = -EBUSY;
3371                 goto err;
3372         }
3373         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3374         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3375                                      GFP_ATOMIC);
3376         if (!cmd.va) {
3377                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3378                 status = -ENOMEM;
3379                 goto err;
3380         }
3381
3382         req = cmd.va;
3383
3384         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3385                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3386                                wrb, &cmd);
3387
3388         status = be_mcc_notify_wait(adapter);
3389         if (!status) {
3390                 struct be_phy_info *resp_phy_info =
3391                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3392
3393                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3394                 adapter->phy.interface_type =
3395                         le16_to_cpu(resp_phy_info->interface_type);
3396                 adapter->phy.auto_speeds_supported =
3397                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3398                 adapter->phy.fixed_speeds_supported =
3399                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3400                 adapter->phy.misc_params =
3401                         le32_to_cpu(resp_phy_info->misc_params);
3402
3403                 if (BE2_chip(adapter)) {
3404                         adapter->phy.fixed_speeds_supported =
3405                                 BE_SUPPORTED_SPEED_10GBPS |
3406                                 BE_SUPPORTED_SPEED_1GBPS;
3407                 }
3408         }
3409         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3410 err:
3411         spin_unlock_bh(&adapter->mcc_lock);
3412         return status;
3413 }
3414
3415 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3416 {
3417         struct be_mcc_wrb *wrb;
3418         struct be_cmd_req_set_qos *req;
3419         int status;
3420
3421         spin_lock_bh(&adapter->mcc_lock);
3422
3423         wrb = wrb_from_mccq(adapter);
3424         if (!wrb) {
3425                 status = -EBUSY;
3426                 goto err;
3427         }
3428
3429         req = embedded_payload(wrb);
3430
3431         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3432                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3433
3434         req->hdr.domain = domain;
3435         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3436         req->max_bps_nic = cpu_to_le32(bps);
3437
3438         status = be_mcc_notify_wait(adapter);
3439
3440 err:
3441         spin_unlock_bh(&adapter->mcc_lock);
3442         return status;
3443 }
3444
3445 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3446 {
3447         struct be_mcc_wrb *wrb;
3448         struct be_cmd_req_cntl_attribs *req;
3449         struct be_cmd_resp_cntl_attribs *resp;
3450         int status, i;
3451         int payload_len = max(sizeof(*req), sizeof(*resp));
3452         struct mgmt_controller_attrib *attribs;
3453         struct be_dma_mem attribs_cmd;
3454         u32 *serial_num;
3455
3456         if (mutex_lock_interruptible(&adapter->mbox_lock))
3457                 return -1;
3458
3459         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3460         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3461         attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3462                                              attribs_cmd.size,
3463                                              &attribs_cmd.dma, GFP_ATOMIC);
3464         if (!attribs_cmd.va) {
3465                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3466                 status = -ENOMEM;
3467                 goto err;
3468         }
3469
3470         wrb = wrb_from_mbox(adapter);
3471         if (!wrb) {
3472                 status = -EBUSY;
3473                 goto err;
3474         }
3475         req = attribs_cmd.va;
3476
3477         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3478                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3479                                wrb, &attribs_cmd);
3480
3481         status = be_mbox_notify_wait(adapter);
3482         if (!status) {
3483                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3484                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3485                 serial_num = attribs->hba_attribs.controller_serial_number;
3486                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3487                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3488                                 (BIT_MASK(16) - 1);
3489         }
3490
3491 err:
3492         mutex_unlock(&adapter->mbox_lock);
3493         if (attribs_cmd.va)
3494                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3495                                   attribs_cmd.va, attribs_cmd.dma);
3496         return status;
3497 }
3498
3499 /* Uses mbox */
3500 int be_cmd_req_native_mode(struct be_adapter *adapter)
3501 {
3502         struct be_mcc_wrb *wrb;
3503         struct be_cmd_req_set_func_cap *req;
3504         int status;
3505
3506         if (mutex_lock_interruptible(&adapter->mbox_lock))
3507                 return -1;
3508
3509         wrb = wrb_from_mbox(adapter);
3510         if (!wrb) {
3511                 status = -EBUSY;
3512                 goto err;
3513         }
3514
3515         req = embedded_payload(wrb);
3516
3517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3518                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3519                                sizeof(*req), wrb, NULL);
3520
3521         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3522                                 CAPABILITY_BE3_NATIVE_ERX_API);
3523         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3524
3525         status = be_mbox_notify_wait(adapter);
3526         if (!status) {
3527                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3528
3529                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3530                                         CAPABILITY_BE3_NATIVE_ERX_API;
3531                 if (!adapter->be3_native)
3532                         dev_warn(&adapter->pdev->dev,
3533                                  "adapter not in advanced mode\n");
3534         }
3535 err:
3536         mutex_unlock(&adapter->mbox_lock);
3537         return status;
3538 }
3539
3540 /* Get privilege(s) for a function */
3541 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3542                              u32 domain)
3543 {
3544         struct be_mcc_wrb *wrb;
3545         struct be_cmd_req_get_fn_privileges *req;
3546         int status;
3547
3548         spin_lock_bh(&adapter->mcc_lock);
3549
3550         wrb = wrb_from_mccq(adapter);
3551         if (!wrb) {
3552                 status = -EBUSY;
3553                 goto err;
3554         }
3555
3556         req = embedded_payload(wrb);
3557
3558         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3559                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3560                                wrb, NULL);
3561
3562         req->hdr.domain = domain;
3563
3564         status = be_mcc_notify_wait(adapter);
3565         if (!status) {
3566                 struct be_cmd_resp_get_fn_privileges *resp =
3567                                                 embedded_payload(wrb);
3568
3569                 *privilege = le32_to_cpu(resp->privilege_mask);
3570
3571                 /* In UMC mode FW does not return right privileges.
3572                  * Override with correct privilege equivalent to PF.
3573                  */
3574                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3575                     be_physfn(adapter))
3576                         *privilege = MAX_PRIVILEGES;
3577         }
3578
3579 err:
3580         spin_unlock_bh(&adapter->mcc_lock);
3581         return status;
3582 }
3583
3584 /* Set privilege(s) for a function */
3585 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3586                              u32 domain)
3587 {
3588         struct be_mcc_wrb *wrb;
3589         struct be_cmd_req_set_fn_privileges *req;
3590         int status;
3591
3592         spin_lock_bh(&adapter->mcc_lock);
3593
3594         wrb = wrb_from_mccq(adapter);
3595         if (!wrb) {
3596                 status = -EBUSY;
3597                 goto err;
3598         }
3599
3600         req = embedded_payload(wrb);
3601         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3602                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3603                                wrb, NULL);
3604         req->hdr.domain = domain;
3605         if (lancer_chip(adapter))
3606                 req->privileges_lancer = cpu_to_le32(privileges);
3607         else
3608                 req->privileges = cpu_to_le32(privileges);
3609
3610         status = be_mcc_notify_wait(adapter);
3611 err:
3612         spin_unlock_bh(&adapter->mcc_lock);
3613         return status;
3614 }
3615
3616 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3617  * pmac_id_valid: false => pmac_id or MAC address is requested.
3618  *                If pmac_id is returned, pmac_id_valid is returned as true
3619  */
3620 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3621                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3622                              u8 domain)
3623 {
3624         struct be_mcc_wrb *wrb;
3625         struct be_cmd_req_get_mac_list *req;
3626         int status;
3627         int mac_count;
3628         struct be_dma_mem get_mac_list_cmd;
3629         int i;
3630
3631         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3632         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3633         get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3634                                                   get_mac_list_cmd.size,
3635                                                   &get_mac_list_cmd.dma,
3636                                                   GFP_ATOMIC);
3637
3638         if (!get_mac_list_cmd.va) {
3639                 dev_err(&adapter->pdev->dev,
3640                         "Memory allocation failure during GET_MAC_LIST\n");
3641                 return -ENOMEM;
3642         }
3643
3644         spin_lock_bh(&adapter->mcc_lock);
3645
3646         wrb = wrb_from_mccq(adapter);
3647         if (!wrb) {
3648                 status = -EBUSY;
3649                 goto out;
3650         }
3651
3652         req = get_mac_list_cmd.va;
3653
3654         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3655                                OPCODE_COMMON_GET_MAC_LIST,
3656                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3657         req->hdr.domain = domain;
3658         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3659         if (*pmac_id_valid) {
3660                 req->mac_id = cpu_to_le32(*pmac_id);
3661                 req->iface_id = cpu_to_le16(if_handle);
3662                 req->perm_override = 0;
3663         } else {
3664                 req->perm_override = 1;
3665         }
3666
3667         status = be_mcc_notify_wait(adapter);
3668         if (!status) {
3669                 struct be_cmd_resp_get_mac_list *resp =
3670                                                 get_mac_list_cmd.va;
3671
3672                 if (*pmac_id_valid) {
3673                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3674                                ETH_ALEN);
3675                         goto out;
3676                 }
3677
3678                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3679                 /* Mac list returned could contain one or more active mac_ids
3680                  * or one or more true or pseudo permanent mac addresses.
3681                  * If an active mac_id is present, return first active mac_id
3682                  * found.
3683                  */
3684                 for (i = 0; i < mac_count; i++) {
3685                         struct get_list_macaddr *mac_entry;
3686                         u16 mac_addr_size;
3687                         u32 mac_id;
3688
3689                         mac_entry = &resp->macaddr_list[i];
3690                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3691                         /* mac_id is a 32 bit value and mac_addr size
3692                          * is 6 bytes
3693                          */
3694                         if (mac_addr_size == sizeof(u32)) {
3695                                 *pmac_id_valid = true;
3696                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3697                                 *pmac_id = le32_to_cpu(mac_id);
3698                                 goto out;
3699                         }
3700                 }
3701                 /* If no active mac_id found, return first mac addr */
3702                 *pmac_id_valid = false;
3703                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3704                        ETH_ALEN);
3705         }
3706
3707 out:
3708         spin_unlock_bh(&adapter->mcc_lock);
3709         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3710                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3711         return status;
3712 }
3713
3714 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3715                           u8 *mac, u32 if_handle, bool active, u32 domain)
3716 {
3717         if (!active)
3718                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3719                                          if_handle, domain);
3720         if (BEx_chip(adapter))
3721                 return be_cmd_mac_addr_query(adapter, mac, false,
3722                                              if_handle, curr_pmac_id);
3723         else
3724                 /* Fetch the MAC address using pmac_id */
3725                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3726                                                 &curr_pmac_id,
3727                                                 if_handle, domain);
3728 }
3729
3730 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3731 {
3732         int status;
3733         bool pmac_valid = false;
3734
3735         eth_zero_addr(mac);
3736
3737         if (BEx_chip(adapter)) {
3738                 if (be_physfn(adapter))
3739                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3740                                                        0);
3741                 else
3742                         status = be_cmd_mac_addr_query(adapter, mac, false,
3743                                                        adapter->if_handle, 0);
3744         } else {
3745                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3746                                                   NULL, adapter->if_handle, 0);
3747         }
3748
3749         return status;
3750 }
3751
3752 /* Uses synchronous MCCQ */
3753 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3754                         u8 mac_count, u32 domain)
3755 {
3756         struct be_mcc_wrb *wrb;
3757         struct be_cmd_req_set_mac_list *req;
3758         int status;
3759         struct be_dma_mem cmd;
3760
3761         memset(&cmd, 0, sizeof(struct be_dma_mem));
3762         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3763         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3764                                      GFP_KERNEL);
3765         if (!cmd.va)
3766                 return -ENOMEM;
3767
3768         spin_lock_bh(&adapter->mcc_lock);
3769
3770         wrb = wrb_from_mccq(adapter);
3771         if (!wrb) {
3772                 status = -EBUSY;
3773                 goto err;
3774         }
3775
3776         req = cmd.va;
3777         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3778                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3779                                wrb, &cmd);
3780
3781         req->hdr.domain = domain;
3782         req->mac_count = mac_count;
3783         if (mac_count)
3784                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3785
3786         status = be_mcc_notify_wait(adapter);
3787
3788 err:
3789         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3790         spin_unlock_bh(&adapter->mcc_lock);
3791         return status;
3792 }
3793
3794 /* Wrapper to delete any active MACs and provision the new mac.
3795  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3796  * current list are active.
3797  */
3798 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3799 {
3800         bool active_mac = false;
3801         u8 old_mac[ETH_ALEN];
3802         u32 pmac_id;
3803         int status;
3804
3805         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3806                                           &pmac_id, if_id, dom);
3807
3808         if (!status && active_mac)
3809                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3810
3811         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3812 }
3813
3814 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3815                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3816 {
3817         struct be_mcc_wrb *wrb;
3818         struct be_cmd_req_set_hsw_config *req;
3819         void *ctxt;
3820         int status;
3821
3822         spin_lock_bh(&adapter->mcc_lock);
3823
3824         wrb = wrb_from_mccq(adapter);
3825         if (!wrb) {
3826                 status = -EBUSY;
3827                 goto err;
3828         }
3829
3830         req = embedded_payload(wrb);
3831         ctxt = &req->context;
3832
3833         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3834                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3835                                NULL);
3836
3837         req->hdr.domain = domain;
3838         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3839         if (pvid) {
3840                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3841                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3842         }
3843         if (!BEx_chip(adapter) && hsw_mode) {
3844                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3845                               ctxt, adapter->hba_port_num);
3846                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3847                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3848                               ctxt, hsw_mode);
3849         }
3850
3851         /* Enable/disable both mac and vlan spoof checking */
3852         if (!BEx_chip(adapter) && spoofchk) {
3853                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3854                               ctxt, spoofchk);
3855                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3856                               ctxt, spoofchk);
3857         }
3858
3859         be_dws_cpu_to_le(req->context, sizeof(req->context));
3860         status = be_mcc_notify_wait(adapter);
3861
3862 err:
3863         spin_unlock_bh(&adapter->mcc_lock);
3864         return status;
3865 }
3866
3867 /* Get Hyper switch config */
3868 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3869                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3870 {
3871         struct be_mcc_wrb *wrb;
3872         struct be_cmd_req_get_hsw_config *req;
3873         void *ctxt;
3874         int status;
3875         u16 vid;
3876
3877         spin_lock_bh(&adapter->mcc_lock);
3878
3879         wrb = wrb_from_mccq(adapter);
3880         if (!wrb) {
3881                 status = -EBUSY;
3882                 goto err;
3883         }
3884
3885         req = embedded_payload(wrb);
3886         ctxt = &req->context;
3887
3888         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3889                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3890                                NULL);
3891
3892         req->hdr.domain = domain;
3893         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3894                       ctxt, intf_id);
3895         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3896
3897         if (!BEx_chip(adapter) && mode) {
3898                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3899                               ctxt, adapter->hba_port_num);
3900                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3901         }
3902         be_dws_cpu_to_le(req->context, sizeof(req->context));
3903
3904         status = be_mcc_notify_wait(adapter);
3905         if (!status) {
3906                 struct be_cmd_resp_get_hsw_config *resp =
3907                                                 embedded_payload(wrb);
3908
3909                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3910                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3911                                     pvid, &resp->context);
3912                 if (pvid)
3913                         *pvid = le16_to_cpu(vid);
3914                 if (mode)
3915                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3916                                               port_fwd_type, &resp->context);
3917                 if (spoofchk)
3918                         *spoofchk =
3919                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3920                                               spoofchk, &resp->context);
3921         }
3922
3923 err:
3924         spin_unlock_bh(&adapter->mcc_lock);
3925         return status;
3926 }
3927
3928 static bool be_is_wol_excluded(struct be_adapter *adapter)
3929 {
3930         struct pci_dev *pdev = adapter->pdev;
3931
3932         if (be_virtfn(adapter))
3933                 return true;
3934
3935         switch (pdev->subsystem_device) {
3936         case OC_SUBSYS_DEVICE_ID1:
3937         case OC_SUBSYS_DEVICE_ID2:
3938         case OC_SUBSYS_DEVICE_ID3:
3939         case OC_SUBSYS_DEVICE_ID4:
3940                 return true;
3941         default:
3942                 return false;
3943         }
3944 }
3945
3946 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3947 {
3948         struct be_mcc_wrb *wrb;
3949         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3950         int status = 0;
3951         struct be_dma_mem cmd;
3952
3953         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3954                             CMD_SUBSYSTEM_ETH))
3955                 return -EPERM;
3956
3957         if (be_is_wol_excluded(adapter))
3958                 return status;
3959
3960         if (mutex_lock_interruptible(&adapter->mbox_lock))
3961                 return -1;
3962
3963         memset(&cmd, 0, sizeof(struct be_dma_mem));
3964         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3965         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3966                                      GFP_ATOMIC);
3967         if (!cmd.va) {
3968                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3969                 status = -ENOMEM;
3970                 goto err;
3971         }
3972
3973         wrb = wrb_from_mbox(adapter);
3974         if (!wrb) {
3975                 status = -EBUSY;
3976                 goto err;
3977         }
3978
3979         req = cmd.va;
3980
3981         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3982                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3983                                sizeof(*req), wrb, &cmd);
3984
3985         req->hdr.version = 1;
3986         req->query_options = BE_GET_WOL_CAP;
3987
3988         status = be_mbox_notify_wait(adapter);
3989         if (!status) {
3990                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3991
3992                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3993
3994                 adapter->wol_cap = resp->wol_settings;
3995                 if (adapter->wol_cap & BE_WOL_CAP)
3996                         adapter->wol_en = true;
3997         }
3998 err:
3999         mutex_unlock(&adapter->mbox_lock);
4000         if (cmd.va)
4001                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4002                                   cmd.dma);
4003         return status;
4004
4005 }
4006
4007 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4008 {
4009         struct be_dma_mem extfat_cmd;
4010         struct be_fat_conf_params *cfgs;
4011         int status;
4012         int i, j;
4013
4014         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4015         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4016         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4017                                             extfat_cmd.size, &extfat_cmd.dma,
4018                                             GFP_ATOMIC);
4019         if (!extfat_cmd.va)
4020                 return -ENOMEM;
4021
4022         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4023         if (status)
4024                 goto err;
4025
4026         cfgs = (struct be_fat_conf_params *)
4027                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4028         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4029                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4030
4031                 for (j = 0; j < num_modes; j++) {
4032                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4033                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4034                                                         cpu_to_le32(level);
4035                 }
4036         }
4037
4038         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4039 err:
4040         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4041                           extfat_cmd.dma);
4042         return status;
4043 }
4044
4045 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4046 {
4047         struct be_dma_mem extfat_cmd;
4048         struct be_fat_conf_params *cfgs;
4049         int status, j;
4050         int level = 0;
4051
4052         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4053         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4054         extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4055                                             extfat_cmd.size, &extfat_cmd.dma,
4056                                             GFP_ATOMIC);
4057
4058         if (!extfat_cmd.va) {
4059                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4060                         __func__);
4061                 goto err;
4062         }
4063
4064         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4065         if (!status) {
4066                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4067                                                 sizeof(struct be_cmd_resp_hdr));
4068
4069                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4070                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4071                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4072                 }
4073         }
4074         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4075                           extfat_cmd.dma);
4076 err:
4077         return level;
4078 }
4079
4080 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4081                                    struct be_dma_mem *cmd)
4082 {
4083         struct be_mcc_wrb *wrb;
4084         struct be_cmd_req_get_ext_fat_caps *req;
4085         int status;
4086
4087         if (mutex_lock_interruptible(&adapter->mbox_lock))
4088                 return -1;
4089
4090         wrb = wrb_from_mbox(adapter);
4091         if (!wrb) {
4092                 status = -EBUSY;
4093                 goto err;
4094         }
4095
4096         req = cmd->va;
4097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4098                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4099                                cmd->size, wrb, cmd);
4100         req->parameter_type = cpu_to_le32(1);
4101
4102         status = be_mbox_notify_wait(adapter);
4103 err:
4104         mutex_unlock(&adapter->mbox_lock);
4105         return status;
4106 }
4107
4108 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4109                                    struct be_dma_mem *cmd,
4110                                    struct be_fat_conf_params *configs)
4111 {
4112         struct be_mcc_wrb *wrb;
4113         struct be_cmd_req_set_ext_fat_caps *req;
4114         int status;
4115
4116         spin_lock_bh(&adapter->mcc_lock);
4117
4118         wrb = wrb_from_mccq(adapter);
4119         if (!wrb) {
4120                 status = -EBUSY;
4121                 goto err;
4122         }
4123
4124         req = cmd->va;
4125         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4126         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4127                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4128                                cmd->size, wrb, cmd);
4129
4130         status = be_mcc_notify_wait(adapter);
4131 err:
4132         spin_unlock_bh(&adapter->mcc_lock);
4133         return status;
4134 }
4135
4136 int be_cmd_query_port_name(struct be_adapter *adapter)
4137 {
4138         struct be_cmd_req_get_port_name *req;
4139         struct be_mcc_wrb *wrb;
4140         int status;
4141
4142         if (mutex_lock_interruptible(&adapter->mbox_lock))
4143                 return -1;
4144
4145         wrb = wrb_from_mbox(adapter);
4146         req = embedded_payload(wrb);
4147
4148         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4149                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4150                                NULL);
4151         if (!BEx_chip(adapter))
4152                 req->hdr.version = 1;
4153
4154         status = be_mbox_notify_wait(adapter);
4155         if (!status) {
4156                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4157
4158                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4159         } else {
4160                 adapter->port_name = adapter->hba_port_num + '0';
4161         }
4162
4163         mutex_unlock(&adapter->mbox_lock);
4164         return status;
4165 }
4166
4167 /* When more than 1 NIC descriptor is present in the descriptor list,
4168  * the caller must specify the pf_num to obtain the NIC descriptor
4169  * corresponding to its pci function.
4170  * get_vft must be true when the caller wants the VF-template desc of the
4171  * PF-pool.
4172  * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4173  * that only it's NIC descriptor is present in the descriptor list.
4174  */
4175 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4176                                                bool get_vft, u8 pf_num)
4177 {
4178         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4179         struct be_nic_res_desc *nic;
4180         int i;
4181
4182         for (i = 0; i < desc_count; i++) {
4183                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4184                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4185                         nic = (struct be_nic_res_desc *)hdr;
4186
4187                         if ((pf_num == PF_NUM_IGNORE ||
4188                              nic->pf_num == pf_num) &&
4189                             (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4190                                 return nic;
4191                 }
4192                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4193                 hdr = (void *)hdr + hdr->desc_len;
4194         }
4195         return NULL;
4196 }
4197
4198 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4199                                                u8 pf_num)
4200 {
4201         return be_get_nic_desc(buf, desc_count, true, pf_num);
4202 }
4203
4204 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4205                                                     u8 pf_num)
4206 {
4207         return be_get_nic_desc(buf, desc_count, false, pf_num);
4208 }
4209
4210 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4211                                                  u8 pf_num)
4212 {
4213         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4214         struct be_pcie_res_desc *pcie;
4215         int i;
4216
4217         for (i = 0; i < desc_count; i++) {
4218                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4219                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4220                         pcie = (struct be_pcie_res_desc *)hdr;
4221                         if (pcie->pf_num == pf_num)
4222                                 return pcie;
4223                 }
4224
4225                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4226                 hdr = (void *)hdr + hdr->desc_len;
4227         }
4228         return NULL;
4229 }
4230
4231 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4232 {
4233         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4234         int i;
4235
4236         for (i = 0; i < desc_count; i++) {
4237                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4238                         return (struct be_port_res_desc *)hdr;
4239
4240                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4241                 hdr = (void *)hdr + hdr->desc_len;
4242         }
4243         return NULL;
4244 }
4245
4246 static void be_copy_nic_desc(struct be_resources *res,
4247                              struct be_nic_res_desc *desc)
4248 {
4249         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4250         res->max_vlans = le16_to_cpu(desc->vlan_count);
4251         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4252         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4253         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4254         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4255         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4256         res->max_cq_count = le16_to_cpu(desc->cq_count);
4257         res->max_iface_count = le16_to_cpu(desc->iface_count);
4258         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4259         /* Clear flags that driver is not interested in */
4260         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4261                                 BE_IF_CAP_FLAGS_WANT;
4262 }
4263
4264 /* Uses Mbox */
4265 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4266 {
4267         struct be_mcc_wrb *wrb;
4268         struct be_cmd_req_get_func_config *req;
4269         int status;
4270         struct be_dma_mem cmd;
4271
4272         if (mutex_lock_interruptible(&adapter->mbox_lock))
4273                 return -1;
4274
4275         memset(&cmd, 0, sizeof(struct be_dma_mem));
4276         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4277         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4278                                      GFP_ATOMIC);
4279         if (!cmd.va) {
4280                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4281                 status = -ENOMEM;
4282                 goto err;
4283         }
4284
4285         wrb = wrb_from_mbox(adapter);
4286         if (!wrb) {
4287                 status = -EBUSY;
4288                 goto err;
4289         }
4290
4291         req = cmd.va;
4292
4293         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4294                                OPCODE_COMMON_GET_FUNC_CONFIG,
4295                                cmd.size, wrb, &cmd);
4296
4297         if (skyhawk_chip(adapter))
4298                 req->hdr.version = 1;
4299
4300         status = be_mbox_notify_wait(adapter);
4301         if (!status) {
4302                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4303                 u32 desc_count = le32_to_cpu(resp->desc_count);
4304                 struct be_nic_res_desc *desc;
4305
4306                 /* GET_FUNC_CONFIG returns resource descriptors of the
4307                  * current function only. So, pf_num should be set to
4308                  * PF_NUM_IGNORE.
4309                  */
4310                 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4311                                             PF_NUM_IGNORE);
4312                 if (!desc) {
4313                         status = -EINVAL;
4314                         goto err;
4315                 }
4316
4317                 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4318                 adapter->pf_num = desc->pf_num;
4319                 adapter->vf_num = desc->vf_num;
4320
4321                 if (res)
4322                         be_copy_nic_desc(res, desc);
4323         }
4324 err:
4325         mutex_unlock(&adapter->mbox_lock);
4326         if (cmd.va)
4327                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4328                                   cmd.dma);
4329         return status;
4330 }
4331
4332 /* Will use MBOX only if MCCQ has not been created */
4333 int be_cmd_get_profile_config(struct be_adapter *adapter,
4334                               struct be_resources *res, u8 query, u8 domain)
4335 {
4336         struct be_cmd_resp_get_profile_config *resp;
4337         struct be_cmd_req_get_profile_config *req;
4338         struct be_nic_res_desc *vf_res;
4339         struct be_pcie_res_desc *pcie;
4340         struct be_port_res_desc *port;
4341         struct be_nic_res_desc *nic;
4342         struct be_mcc_wrb wrb = {0};
4343         struct be_dma_mem cmd;
4344         u16 desc_count;
4345         int status;
4346
4347         memset(&cmd, 0, sizeof(struct be_dma_mem));
4348         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4349         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4350                                      GFP_ATOMIC);
4351         if (!cmd.va)
4352                 return -ENOMEM;
4353
4354         req = cmd.va;
4355         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4356                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4357                                cmd.size, &wrb, &cmd);
4358
4359         if (!lancer_chip(adapter))
4360                 req->hdr.version = 1;
4361         req->type = ACTIVE_PROFILE_TYPE;
4362         req->hdr.domain = domain;
4363
4364         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4365          * descriptors with all bits set to "1" for the fields which can be
4366          * modified using SET_PROFILE_CONFIG cmd.
4367          */
4368         if (query == RESOURCE_MODIFIABLE)
4369                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4370
4371         status = be_cmd_notify_wait(adapter, &wrb);
4372         if (status)
4373                 goto err;
4374
4375         resp = cmd.va;
4376         desc_count = le16_to_cpu(resp->desc_count);
4377
4378         pcie = be_get_pcie_desc(resp->func_param, desc_count,
4379                                 adapter->pf_num);
4380         if (pcie)
4381                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4382
4383         port = be_get_port_desc(resp->func_param, desc_count);
4384         if (port)
4385                 adapter->mc_type = port->mc_type;
4386
4387         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4388                                    adapter->pf_num);
4389         if (nic)
4390                 be_copy_nic_desc(res, nic);
4391
4392         vf_res = be_get_vft_desc(resp->func_param, desc_count,
4393                                  adapter->pf_num);
4394         if (vf_res)
4395                 res->vf_if_cap_flags = vf_res->cap_flags;
4396 err:
4397         if (cmd.va)
4398                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4399                                   cmd.dma);
4400         return status;
4401 }
4402
4403 /* Will use MBOX only if MCCQ has not been created */
4404 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4405                                      int size, int count, u8 version, u8 domain)
4406 {
4407         struct be_cmd_req_set_profile_config *req;
4408         struct be_mcc_wrb wrb = {0};
4409         struct be_dma_mem cmd;
4410         int status;
4411
4412         memset(&cmd, 0, sizeof(struct be_dma_mem));
4413         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4414         cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4415                                      GFP_ATOMIC);
4416         if (!cmd.va)
4417                 return -ENOMEM;
4418
4419         req = cmd.va;
4420         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4421                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4422                                &wrb, &cmd);
4423         req->hdr.version = version;
4424         req->hdr.domain = domain;
4425         req->desc_count = cpu_to_le32(count);
4426         memcpy(req->desc, desc, size);
4427
4428         status = be_cmd_notify_wait(adapter, &wrb);
4429
4430         if (cmd.va)
4431                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4432                                   cmd.dma);
4433         return status;
4434 }
4435
4436 /* Mark all fields invalid */
4437 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4438 {
4439         memset(nic, 0, sizeof(*nic));
4440         nic->unicast_mac_count = 0xFFFF;
4441         nic->mcc_count = 0xFFFF;
4442         nic->vlan_count = 0xFFFF;
4443         nic->mcast_mac_count = 0xFFFF;
4444         nic->txq_count = 0xFFFF;
4445         nic->rq_count = 0xFFFF;
4446         nic->rssq_count = 0xFFFF;
4447         nic->lro_count = 0xFFFF;
4448         nic->cq_count = 0xFFFF;
4449         nic->toe_conn_count = 0xFFFF;
4450         nic->eq_count = 0xFFFF;
4451         nic->iface_count = 0xFFFF;
4452         nic->link_param = 0xFF;
4453         nic->channel_id_param = cpu_to_le16(0xF000);
4454         nic->acpi_params = 0xFF;
4455         nic->wol_param = 0x0F;
4456         nic->tunnel_iface_count = 0xFFFF;
4457         nic->direct_tenant_iface_count = 0xFFFF;
4458         nic->bw_min = 0xFFFFFFFF;
4459         nic->bw_max = 0xFFFFFFFF;
4460 }
4461
4462 /* Mark all fields invalid */
4463 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4464 {
4465         memset(pcie, 0, sizeof(*pcie));
4466         pcie->sriov_state = 0xFF;
4467         pcie->pf_state = 0xFF;
4468         pcie->pf_type = 0xFF;
4469         pcie->num_vfs = 0xFFFF;
4470 }
4471
4472 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4473                       u8 domain)
4474 {
4475         struct be_nic_res_desc nic_desc;
4476         u32 bw_percent;
4477         u16 version = 0;
4478
4479         if (BE3_chip(adapter))
4480                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4481
4482         be_reset_nic_desc(&nic_desc);
4483         nic_desc.pf_num = adapter->pf_num;
4484         nic_desc.vf_num = domain;
4485         nic_desc.bw_min = 0;
4486         if (lancer_chip(adapter)) {
4487                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4488                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4489                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4490                                         (1 << NOSV_SHIFT);
4491                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4492         } else {
4493                 version = 1;
4494                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4495                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4496                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4497                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4498                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4499         }
4500
4501         return be_cmd_set_profile_config(adapter, &nic_desc,
4502                                          nic_desc.hdr.desc_len,
4503                                          1, version, domain);
4504 }
4505
4506 static void be_fill_vf_res_template(struct be_adapter *adapter,
4507                                     struct be_resources pool_res,
4508                                     u16 num_vfs, u16 num_vf_qs,
4509                                     struct be_nic_res_desc *nic_vft)
4510 {
4511         u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
4512         struct be_resources res_mod = {0};
4513
4514         /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
4515          * which are modifiable using SET_PROFILE_CONFIG cmd.
4516          */
4517         be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
4518
4519         /* If RSS IFACE capability flags are modifiable for a VF, set the
4520          * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
4521          * more than 1 RSSQ is available for a VF.
4522          * Otherwise, provision only 1 queue pair for VF.
4523          */
4524         if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
4525                 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4526                 if (num_vf_qs > 1) {
4527                         vf_if_cap_flags |= BE_IF_FLAGS_RSS;
4528                         if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
4529                                 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
4530                 } else {
4531                         vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
4532                                              BE_IF_FLAGS_DEFQ_RSS);
4533                 }
4534         } else {
4535                 num_vf_qs = 1;
4536         }
4537
4538         if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
4539                 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4540                 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
4541         }
4542
4543         nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
4544         nic_vft->rq_count = cpu_to_le16(num_vf_qs);
4545         nic_vft->txq_count = cpu_to_le16(num_vf_qs);
4546         nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
4547         nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
4548                                         (num_vfs + 1));
4549
4550         /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
4551          * among the PF and it's VFs, if the fields are changeable
4552          */
4553         if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
4554                 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
4555                                                          (num_vfs + 1));
4556
4557         if (res_mod.max_vlans == FIELD_MODIFIABLE)
4558                 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
4559                                                   (num_vfs + 1));
4560
4561         if (res_mod.max_iface_count == FIELD_MODIFIABLE)
4562                 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
4563                                                    (num_vfs + 1));
4564
4565         if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
4566                 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
4567                                                  (num_vfs + 1));
4568 }
4569
4570 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4571                             struct be_resources pool_res, u16 num_vfs,
4572                             u16 num_vf_qs)
4573 {
4574         struct {
4575                 struct be_pcie_res_desc pcie;
4576                 struct be_nic_res_desc nic_vft;
4577         } __packed desc;
4578
4579         /* PF PCIE descriptor */
4580         be_reset_pcie_desc(&desc.pcie);
4581         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4582         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4583         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4584         desc.pcie.pf_num = adapter->pdev->devfn;
4585         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4586         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4587
4588         /* VF NIC Template descriptor */
4589         be_reset_nic_desc(&desc.nic_vft);
4590         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4591         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4592         desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4593         desc.nic_vft.pf_num = adapter->pdev->devfn;
4594         desc.nic_vft.vf_num = 0;
4595
4596         be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4597                                 &desc.nic_vft);
4598
4599         return be_cmd_set_profile_config(adapter, &desc,
4600                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4601 }
4602
4603 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4604 {
4605         struct be_mcc_wrb *wrb;
4606         struct be_cmd_req_manage_iface_filters *req;
4607         int status;
4608
4609         if (iface == 0xFFFFFFFF)
4610                 return -1;
4611
4612         spin_lock_bh(&adapter->mcc_lock);
4613
4614         wrb = wrb_from_mccq(adapter);
4615         if (!wrb) {
4616                 status = -EBUSY;
4617                 goto err;
4618         }
4619         req = embedded_payload(wrb);
4620
4621         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4622                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4623                                wrb, NULL);
4624         req->op = op;
4625         req->target_iface_id = cpu_to_le32(iface);
4626
4627         status = be_mcc_notify_wait(adapter);
4628 err:
4629         spin_unlock_bh(&adapter->mcc_lock);
4630         return status;
4631 }
4632
4633 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4634 {
4635         struct be_port_res_desc port_desc;
4636
4637         memset(&port_desc, 0, sizeof(port_desc));
4638         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4639         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4640         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4641         port_desc.link_num = adapter->hba_port_num;
4642         if (port) {
4643                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4644                                         (1 << RCVID_SHIFT);
4645                 port_desc.nv_port = swab16(port);
4646         } else {
4647                 port_desc.nv_flags = NV_TYPE_DISABLED;
4648                 port_desc.nv_port = 0;
4649         }
4650
4651         return be_cmd_set_profile_config(adapter, &port_desc,
4652                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4653 }
4654
4655 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4656                      int vf_num)
4657 {
4658         struct be_mcc_wrb *wrb;
4659         struct be_cmd_req_get_iface_list *req;
4660         struct be_cmd_resp_get_iface_list *resp;
4661         int status;
4662
4663         spin_lock_bh(&adapter->mcc_lock);
4664
4665         wrb = wrb_from_mccq(adapter);
4666         if (!wrb) {
4667                 status = -EBUSY;
4668                 goto err;
4669         }
4670         req = embedded_payload(wrb);
4671
4672         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4673                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4674                                wrb, NULL);
4675         req->hdr.domain = vf_num + 1;
4676
4677         status = be_mcc_notify_wait(adapter);
4678         if (!status) {
4679                 resp = (struct be_cmd_resp_get_iface_list *)req;
4680                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4681         }
4682
4683 err:
4684         spin_unlock_bh(&adapter->mcc_lock);
4685         return status;
4686 }
4687
4688 static int lancer_wait_idle(struct be_adapter *adapter)
4689 {
4690 #define SLIPORT_IDLE_TIMEOUT 30
4691         u32 reg_val;
4692         int status = 0, i;
4693
4694         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4695                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4696                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4697                         break;
4698
4699                 ssleep(1);
4700         }
4701
4702         if (i == SLIPORT_IDLE_TIMEOUT)
4703                 status = -1;
4704
4705         return status;
4706 }
4707
4708 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4709 {
4710         int status = 0;
4711
4712         status = lancer_wait_idle(adapter);
4713         if (status)
4714                 return status;
4715
4716         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4717
4718         return status;
4719 }
4720
4721 /* Routine to check whether dump image is present or not */
4722 bool dump_present(struct be_adapter *adapter)
4723 {
4724         u32 sliport_status = 0;
4725
4726         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4727         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4728 }
4729
4730 int lancer_initiate_dump(struct be_adapter *adapter)
4731 {
4732         struct device *dev = &adapter->pdev->dev;
4733         int status;
4734
4735         if (dump_present(adapter)) {
4736                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4737                 return -EEXIST;
4738         }
4739
4740         /* give firmware reset and diagnostic dump */
4741         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4742                                      PHYSDEV_CONTROL_DD_MASK);
4743         if (status < 0) {
4744                 dev_err(dev, "FW reset failed\n");
4745                 return status;
4746         }
4747
4748         status = lancer_wait_idle(adapter);
4749         if (status)
4750                 return status;
4751
4752         if (!dump_present(adapter)) {
4753                 dev_err(dev, "FW dump not generated\n");
4754                 return -EIO;
4755         }
4756
4757         return 0;
4758 }
4759
4760 int lancer_delete_dump(struct be_adapter *adapter)
4761 {
4762         int status;
4763
4764         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4765         return be_cmd_status(status);
4766 }
4767
4768 /* Uses sync mcc */
4769 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4770 {
4771         struct be_mcc_wrb *wrb;
4772         struct be_cmd_enable_disable_vf *req;
4773         int status;
4774
4775         if (BEx_chip(adapter))
4776                 return 0;
4777
4778         spin_lock_bh(&adapter->mcc_lock);
4779
4780         wrb = wrb_from_mccq(adapter);
4781         if (!wrb) {
4782                 status = -EBUSY;
4783                 goto err;
4784         }
4785
4786         req = embedded_payload(wrb);
4787
4788         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4789                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4790                                wrb, NULL);
4791
4792         req->hdr.domain = domain;
4793         req->enable = 1;
4794         status = be_mcc_notify_wait(adapter);
4795 err:
4796         spin_unlock_bh(&adapter->mcc_lock);
4797         return status;
4798 }
4799
4800 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4801 {
4802         struct be_mcc_wrb *wrb;
4803         struct be_cmd_req_intr_set *req;
4804         int status;
4805
4806         if (mutex_lock_interruptible(&adapter->mbox_lock))
4807                 return -1;
4808
4809         wrb = wrb_from_mbox(adapter);
4810
4811         req = embedded_payload(wrb);
4812
4813         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4814                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4815                                wrb, NULL);
4816
4817         req->intr_enabled = intr_enable;
4818
4819         status = be_mbox_notify_wait(adapter);
4820
4821         mutex_unlock(&adapter->mbox_lock);
4822         return status;
4823 }
4824
4825 /* Uses MBOX */
4826 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4827 {
4828         struct be_cmd_req_get_active_profile *req;
4829         struct be_mcc_wrb *wrb;
4830         int status;
4831
4832         if (mutex_lock_interruptible(&adapter->mbox_lock))
4833                 return -1;
4834
4835         wrb = wrb_from_mbox(adapter);
4836         if (!wrb) {
4837                 status = -EBUSY;
4838                 goto err;
4839         }
4840
4841         req = embedded_payload(wrb);
4842
4843         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4844                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4845                                wrb, NULL);
4846
4847         status = be_mbox_notify_wait(adapter);
4848         if (!status) {
4849                 struct be_cmd_resp_get_active_profile *resp =
4850                                                         embedded_payload(wrb);
4851
4852                 *profile_id = le16_to_cpu(resp->active_profile_id);
4853         }
4854
4855 err:
4856         mutex_unlock(&adapter->mbox_lock);
4857         return status;
4858 }
4859
4860 int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4861                                      int link_state, int version, u8 domain)
4862 {
4863         struct be_mcc_wrb *wrb;
4864         struct be_cmd_req_set_ll_link *req;
4865         int status;
4866
4867         spin_lock_bh(&adapter->mcc_lock);
4868
4869         wrb = wrb_from_mccq(adapter);
4870         if (!wrb) {
4871                 status = -EBUSY;
4872                 goto err;
4873         }
4874
4875         req = embedded_payload(wrb);
4876
4877         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4878                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4879                                sizeof(*req), wrb, NULL);
4880
4881         req->hdr.version = version;
4882         req->hdr.domain = domain;
4883
4884         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4885             link_state == IFLA_VF_LINK_STATE_AUTO)
4886                 req->link_config |= PLINK_ENABLE;
4887
4888         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4889                 req->link_config |= PLINK_TRACK;
4890
4891         status = be_mcc_notify_wait(adapter);
4892 err:
4893         spin_unlock_bh(&adapter->mcc_lock);
4894         return status;
4895 }
4896
4897 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4898                                    int link_state, u8 domain)
4899 {
4900         int status;
4901
4902         if (BEx_chip(adapter))
4903                 return -EOPNOTSUPP;
4904
4905         status = __be_cmd_set_logical_link_config(adapter, link_state,
4906                                                   2, domain);
4907
4908         /* Version 2 of the command will not be recognized by older FW.
4909          * On such a failure issue version 1 of the command.
4910          */
4911         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4912                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4913                                                           1, domain);
4914         return status;
4915 }
4916 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4917                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4918 {
4919         struct be_adapter *adapter = netdev_priv(netdev_handle);
4920         struct be_mcc_wrb *wrb;
4921         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4922         struct be_cmd_req_hdr *req;
4923         struct be_cmd_resp_hdr *resp;
4924         int status;
4925
4926         spin_lock_bh(&adapter->mcc_lock);
4927
4928         wrb = wrb_from_mccq(adapter);
4929         if (!wrb) {
4930                 status = -EBUSY;
4931                 goto err;
4932         }
4933         req = embedded_payload(wrb);
4934         resp = embedded_payload(wrb);
4935
4936         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4937                                hdr->opcode, wrb_payload_size, wrb, NULL);
4938         memcpy(req, wrb_payload, wrb_payload_size);
4939         be_dws_cpu_to_le(req, wrb_payload_size);
4940
4941         status = be_mcc_notify_wait(adapter);
4942         if (cmd_status)
4943                 *cmd_status = (status & 0xffff);
4944         if (ext_status)
4945                 *ext_status = 0;
4946         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4947         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4948 err:
4949         spin_unlock_bh(&adapter->mcc_lock);
4950         return status;
4951 }
4952 EXPORT_SYMBOL(be_roce_mcc_cmd);