2 * Copyright (C) 2005 - 2015 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static char *be_port_misconfig_evt_desc[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
30 static char *be_port_misconfig_remedy_desc[] = {
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
38 static struct be_cmd_priv_map cmd_priv_map[] = {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
42 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
43 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
46 OPCODE_COMMON_GET_FLOW_CONTROL,
48 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
49 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
52 OPCODE_COMMON_SET_FLOW_CONTROL,
54 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
55 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
58 OPCODE_ETH_GET_PPORT_STATS,
60 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
61 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
64 OPCODE_COMMON_GET_PHY_DETAILS,
66 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
67 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
70 OPCODE_LOWLEVEL_HOST_DDR_DMA,
71 CMD_SUBSYSTEM_LOWLEVEL,
72 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
75 OPCODE_LOWLEVEL_LOOPBACK_TEST,
76 CMD_SUBSYSTEM_LOWLEVEL,
77 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
80 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
81 CMD_SUBSYSTEM_LOWLEVEL,
82 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
86 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
89 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
90 u32 cmd_privileges = adapter->cmd_privileges;
92 for (i = 0; i < num_entries; i++)
93 if (opcode == cmd_priv_map[i].opcode &&
94 subsystem == cmd_priv_map[i].subsystem)
95 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
101 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
103 return wrb->payload.embedded_payload;
106 static int be_mcc_notify(struct be_adapter *adapter)
108 struct be_queue_info *mccq = &adapter->mcc_obj.q;
111 if (be_check_error(adapter, BE_ERROR_ANY))
114 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
115 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
118 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
123 /* To check if valid bit is set, check the entire word as we don't know
124 * the endianness of the data (old entry is host endian while a new entry is
126 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
130 if (compl->flags != 0) {
131 flags = le32_to_cpu(compl->flags);
132 if (flags & CQE_FLAGS_VALID_MASK) {
133 compl->flags = flags;
140 /* Need to reset the entire word that houses the valid bit */
141 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
146 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
151 addr = ((addr << 16) << 16) | tag0;
155 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
157 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
158 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
159 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
160 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
161 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
162 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
163 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
169 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
170 * loop (has not issued be_mcc_notify_wait())
172 static void be_async_cmd_process(struct be_adapter *adapter,
173 struct be_mcc_compl *compl,
174 struct be_cmd_resp_hdr *resp_hdr)
176 enum mcc_base_status base_status = base_status(compl->status);
177 u8 opcode = 0, subsystem = 0;
180 opcode = resp_hdr->opcode;
181 subsystem = resp_hdr->subsystem;
184 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
185 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
186 complete(&adapter->et_cmd_compl);
190 if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
191 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
192 complete(&adapter->et_cmd_compl);
196 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
197 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
198 subsystem == CMD_SUBSYSTEM_COMMON) {
199 adapter->flash_status = compl->status;
200 complete(&adapter->et_cmd_compl);
204 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
205 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
206 subsystem == CMD_SUBSYSTEM_ETH &&
207 base_status == MCC_STATUS_SUCCESS) {
208 be_parse_stats(adapter);
209 adapter->stats_cmd_sent = false;
213 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
214 subsystem == CMD_SUBSYSTEM_COMMON) {
215 if (base_status == MCC_STATUS_SUCCESS) {
216 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
218 adapter->hwmon_info.be_on_die_temp =
219 resp->on_die_temperature;
221 adapter->be_get_temp_freq = 0;
222 adapter->hwmon_info.be_on_die_temp =
229 static int be_mcc_compl_process(struct be_adapter *adapter,
230 struct be_mcc_compl *compl)
232 enum mcc_base_status base_status;
233 enum mcc_addl_status addl_status;
234 struct be_cmd_resp_hdr *resp_hdr;
235 u8 opcode = 0, subsystem = 0;
237 /* Just swap the status to host endian; mcc tag is opaquely copied
239 be_dws_le_to_cpu(compl, 4);
241 base_status = base_status(compl->status);
242 addl_status = addl_status(compl->status);
244 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
246 opcode = resp_hdr->opcode;
247 subsystem = resp_hdr->subsystem;
250 be_async_cmd_process(adapter, compl, resp_hdr);
252 if (base_status != MCC_STATUS_SUCCESS &&
253 !be_skip_err_log(opcode, base_status, addl_status)) {
254 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
255 addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
256 dev_warn(&adapter->pdev->dev,
257 "VF is not privileged to issue opcode %d-%d\n",
260 dev_err(&adapter->pdev->dev,
261 "opcode %d-%d failed:status %d-%d\n",
262 opcode, subsystem, base_status, addl_status);
265 return compl->status;
268 /* Link state evt is a string of bytes; no need for endian swapping */
269 static void be_async_link_state_process(struct be_adapter *adapter,
270 struct be_mcc_compl *compl)
272 struct be_async_event_link_state *evt =
273 (struct be_async_event_link_state *)compl;
275 /* When link status changes, link speed must be re-queried from FW */
276 adapter->phy.link_speed = -1;
278 /* On BEx the FW does not send a separate link status
279 * notification for physical and logical link.
280 * On other chips just process the logical link
281 * status notification
283 if (!BEx_chip(adapter) &&
284 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
287 /* For the initial link status do not rely on the ASYNC event as
288 * it may not be received in some cases.
290 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
291 be_link_status_update(adapter,
292 evt->port_link_status & LINK_STATUS_MASK);
295 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
296 struct be_mcc_compl *compl)
298 struct be_async_event_misconfig_port *evt =
299 (struct be_async_event_misconfig_port *)compl;
300 u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
301 struct device *dev = &adapter->pdev->dev;
302 u8 port_misconfig_evt;
305 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
307 /* Log an error message that would allow a user to determine
308 * whether the SFPs have an issue
310 dev_info(dev, "Port %c: %s %s", adapter->port_name,
311 be_port_misconfig_evt_desc[port_misconfig_evt],
312 be_port_misconfig_remedy_desc[port_misconfig_evt]);
314 if (port_misconfig_evt == INCOMPATIBLE_SFP)
315 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
318 /* Grp5 CoS Priority evt */
319 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
320 struct be_mcc_compl *compl)
322 struct be_async_event_grp5_cos_priority *evt =
323 (struct be_async_event_grp5_cos_priority *)compl;
326 adapter->vlan_prio_bmap = evt->available_priority_bmap;
327 adapter->recommended_prio_bits =
328 evt->reco_default_priority << VLAN_PRIO_SHIFT;
332 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
333 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
334 struct be_mcc_compl *compl)
336 struct be_async_event_grp5_qos_link_speed *evt =
337 (struct be_async_event_grp5_qos_link_speed *)compl;
339 if (adapter->phy.link_speed >= 0 &&
340 evt->physical_port == adapter->port_num)
341 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
345 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
346 struct be_mcc_compl *compl)
348 struct be_async_event_grp5_pvid_state *evt =
349 (struct be_async_event_grp5_pvid_state *)compl;
352 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
353 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
359 #define MGMT_ENABLE_MASK 0x4
360 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
361 struct be_mcc_compl *compl)
363 struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
364 u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
366 if (evt_dw1 & MGMT_ENABLE_MASK) {
367 adapter->flags |= BE_FLAGS_OS2BMC;
368 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
370 adapter->flags &= ~BE_FLAGS_OS2BMC;
374 static void be_async_grp5_evt_process(struct be_adapter *adapter,
375 struct be_mcc_compl *compl)
377 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
378 ASYNC_EVENT_TYPE_MASK;
380 switch (event_type) {
381 case ASYNC_EVENT_COS_PRIORITY:
382 be_async_grp5_cos_priority_process(adapter, compl);
384 case ASYNC_EVENT_QOS_SPEED:
385 be_async_grp5_qos_speed_process(adapter, compl);
387 case ASYNC_EVENT_PVID_STATE:
388 be_async_grp5_pvid_state_process(adapter, compl);
390 /* Async event to disable/enable os2bmc and/or mac-learning */
391 case ASYNC_EVENT_FW_CONTROL:
392 be_async_grp5_fw_control_process(adapter, compl);
399 static void be_async_dbg_evt_process(struct be_adapter *adapter,
400 struct be_mcc_compl *cmp)
403 struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
405 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
406 ASYNC_EVENT_TYPE_MASK;
408 switch (event_type) {
409 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
411 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
412 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
415 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
421 static void be_async_sliport_evt_process(struct be_adapter *adapter,
422 struct be_mcc_compl *cmp)
424 u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
425 ASYNC_EVENT_TYPE_MASK;
427 if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
428 be_async_port_misconfig_event_process(adapter, cmp);
431 static inline bool is_link_state_evt(u32 flags)
433 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
434 ASYNC_EVENT_CODE_LINK_STATE;
437 static inline bool is_grp5_evt(u32 flags)
439 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
440 ASYNC_EVENT_CODE_GRP_5;
443 static inline bool is_dbg_evt(u32 flags)
445 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
446 ASYNC_EVENT_CODE_QNQ;
449 static inline bool is_sliport_evt(u32 flags)
451 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
452 ASYNC_EVENT_CODE_SLIPORT;
455 static void be_mcc_event_process(struct be_adapter *adapter,
456 struct be_mcc_compl *compl)
458 if (is_link_state_evt(compl->flags))
459 be_async_link_state_process(adapter, compl);
460 else if (is_grp5_evt(compl->flags))
461 be_async_grp5_evt_process(adapter, compl);
462 else if (is_dbg_evt(compl->flags))
463 be_async_dbg_evt_process(adapter, compl);
464 else if (is_sliport_evt(compl->flags))
465 be_async_sliport_evt_process(adapter, compl);
468 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
470 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
471 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
473 if (be_mcc_compl_is_new(compl)) {
474 queue_tail_inc(mcc_cq);
480 void be_async_mcc_enable(struct be_adapter *adapter)
482 spin_lock_bh(&adapter->mcc_cq_lock);
484 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
485 adapter->mcc_obj.rearm_cq = true;
487 spin_unlock_bh(&adapter->mcc_cq_lock);
490 void be_async_mcc_disable(struct be_adapter *adapter)
492 spin_lock_bh(&adapter->mcc_cq_lock);
494 adapter->mcc_obj.rearm_cq = false;
495 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
497 spin_unlock_bh(&adapter->mcc_cq_lock);
500 int be_process_mcc(struct be_adapter *adapter)
502 struct be_mcc_compl *compl;
503 int num = 0, status = 0;
504 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
506 spin_lock(&adapter->mcc_cq_lock);
508 while ((compl = be_mcc_compl_get(adapter))) {
509 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
510 be_mcc_event_process(adapter, compl);
511 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
512 status = be_mcc_compl_process(adapter, compl);
513 atomic_dec(&mcc_obj->q.used);
515 be_mcc_compl_use(compl);
520 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
522 spin_unlock(&adapter->mcc_cq_lock);
526 /* Wait till no more pending mcc requests are present */
527 static int be_mcc_wait_compl(struct be_adapter *adapter)
529 #define mcc_timeout 120000 /* 12s timeout */
531 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
533 for (i = 0; i < mcc_timeout; i++) {
534 if (be_check_error(adapter, BE_ERROR_ANY))
538 status = be_process_mcc(adapter);
541 if (atomic_read(&mcc_obj->q.used) == 0)
545 if (i == mcc_timeout) {
546 dev_err(&adapter->pdev->dev, "FW not responding\n");
547 be_set_error(adapter, BE_ERROR_FW);
553 /* Notify MCC requests and wait for completion */
554 static int be_mcc_notify_wait(struct be_adapter *adapter)
557 struct be_mcc_wrb *wrb;
558 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
559 u16 index = mcc_obj->q.head;
560 struct be_cmd_resp_hdr *resp;
562 index_dec(&index, mcc_obj->q.len);
563 wrb = queue_index_node(&mcc_obj->q, index);
565 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
567 status = be_mcc_notify(adapter);
571 status = be_mcc_wait_compl(adapter);
575 status = (resp->base_status |
576 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
577 CQE_ADDL_STATUS_SHIFT));
582 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
588 if (be_check_error(adapter, BE_ERROR_ANY))
591 ready = ioread32(db);
592 if (ready == 0xffffffff)
595 ready &= MPU_MAILBOX_DB_RDY_MASK;
600 dev_err(&adapter->pdev->dev, "FW not responding\n");
601 be_set_error(adapter, BE_ERROR_FW);
602 be_detect_error(adapter);
614 * Insert the mailbox address into the doorbell in two steps
615 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
617 static int be_mbox_notify_wait(struct be_adapter *adapter)
621 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
622 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
623 struct be_mcc_mailbox *mbox = mbox_mem->va;
624 struct be_mcc_compl *compl = &mbox->compl;
626 /* wait for ready to be set */
627 status = be_mbox_db_ready_wait(adapter, db);
631 val |= MPU_MAILBOX_DB_HI_MASK;
632 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
633 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
636 /* wait for ready to be set */
637 status = be_mbox_db_ready_wait(adapter, db);
642 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
643 val |= (u32)(mbox_mem->dma >> 4) << 2;
646 status = be_mbox_db_ready_wait(adapter, db);
650 /* A cq entry has been made now */
651 if (be_mcc_compl_is_new(compl)) {
652 status = be_mcc_compl_process(adapter, &mbox->compl);
653 be_mcc_compl_use(compl);
657 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
663 static u16 be_POST_stage_get(struct be_adapter *adapter)
667 if (BEx_chip(adapter))
668 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
670 pci_read_config_dword(adapter->pdev,
671 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
673 return sem & POST_STAGE_MASK;
676 static int lancer_wait_ready(struct be_adapter *adapter)
678 #define SLIPORT_READY_TIMEOUT 30
682 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
683 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
684 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
687 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
688 !(sliport_status & SLIPORT_STATUS_RN_MASK))
694 return sliport_status ? : -1;
697 int be_fw_wait_ready(struct be_adapter *adapter)
700 int status, timeout = 0;
701 struct device *dev = &adapter->pdev->dev;
703 if (lancer_chip(adapter)) {
704 status = lancer_wait_ready(adapter);
713 /* There's no means to poll POST state on BE2/3 VFs */
714 if (BEx_chip(adapter) && be_virtfn(adapter))
717 stage = be_POST_stage_get(adapter);
718 if (stage == POST_STAGE_ARMFW_RDY)
721 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
722 if (msleep_interruptible(2000)) {
723 dev_err(dev, "Waiting for POST aborted\n");
727 } while (timeout < 60);
730 dev_err(dev, "POST timeout; stage=%#x\n", stage);
734 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
736 return &wrb->payload.sgl[0];
739 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
741 wrb->tag0 = addr & 0xFFFFFFFF;
742 wrb->tag1 = upper_32_bits(addr);
745 /* Don't touch the hdr after it's prepared */
746 /* mem will be NULL for embedded commands */
747 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
748 u8 subsystem, u8 opcode, int cmd_len,
749 struct be_mcc_wrb *wrb,
750 struct be_dma_mem *mem)
754 req_hdr->opcode = opcode;
755 req_hdr->subsystem = subsystem;
756 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
757 req_hdr->version = 0;
758 fill_wrb_tags(wrb, (ulong) req_hdr);
759 wrb->payload_length = cmd_len;
761 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
762 MCC_WRB_SGE_CNT_SHIFT;
763 sge = nonembedded_sgl(wrb);
764 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
765 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
766 sge->len = cpu_to_le32(mem->size);
768 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
769 be_dws_cpu_to_le(wrb, 8);
772 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
773 struct be_dma_mem *mem)
775 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
776 u64 dma = (u64)mem->dma;
778 for (i = 0; i < buf_pages; i++) {
779 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
780 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
785 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
787 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
788 struct be_mcc_wrb *wrb
789 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
790 memset(wrb, 0, sizeof(*wrb));
794 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
796 struct be_queue_info *mccq = &adapter->mcc_obj.q;
797 struct be_mcc_wrb *wrb;
802 if (atomic_read(&mccq->used) >= mccq->len)
805 wrb = queue_head_node(mccq);
806 queue_head_inc(mccq);
807 atomic_inc(&mccq->used);
808 memset(wrb, 0, sizeof(*wrb));
812 static bool use_mcc(struct be_adapter *adapter)
814 return adapter->mcc_obj.q.created;
817 /* Must be used only in process context */
818 static int be_cmd_lock(struct be_adapter *adapter)
820 if (use_mcc(adapter)) {
821 spin_lock_bh(&adapter->mcc_lock);
824 return mutex_lock_interruptible(&adapter->mbox_lock);
828 /* Must be used only in process context */
829 static void be_cmd_unlock(struct be_adapter *adapter)
831 if (use_mcc(adapter))
832 spin_unlock_bh(&adapter->mcc_lock);
834 return mutex_unlock(&adapter->mbox_lock);
837 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
838 struct be_mcc_wrb *wrb)
840 struct be_mcc_wrb *dest_wrb;
842 if (use_mcc(adapter)) {
843 dest_wrb = wrb_from_mccq(adapter);
847 dest_wrb = wrb_from_mbox(adapter);
850 memcpy(dest_wrb, wrb, sizeof(*wrb));
851 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
852 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
857 /* Must be used only in process context */
858 static int be_cmd_notify_wait(struct be_adapter *adapter,
859 struct be_mcc_wrb *wrb)
861 struct be_mcc_wrb *dest_wrb;
864 status = be_cmd_lock(adapter);
868 dest_wrb = be_cmd_copy(adapter, wrb);
874 if (use_mcc(adapter))
875 status = be_mcc_notify_wait(adapter);
877 status = be_mbox_notify_wait(adapter);
880 memcpy(wrb, dest_wrb, sizeof(*wrb));
883 be_cmd_unlock(adapter);
887 /* Tell fw we're about to start firing cmds by writing a
888 * special pattern across the wrb hdr; uses mbox
890 int be_cmd_fw_init(struct be_adapter *adapter)
895 if (lancer_chip(adapter))
898 if (mutex_lock_interruptible(&adapter->mbox_lock))
901 wrb = (u8 *)wrb_from_mbox(adapter);
911 status = be_mbox_notify_wait(adapter);
913 mutex_unlock(&adapter->mbox_lock);
917 /* Tell fw we're done with firing cmds by writing a
918 * special pattern across the wrb hdr; uses mbox
920 int be_cmd_fw_clean(struct be_adapter *adapter)
925 if (lancer_chip(adapter))
928 if (mutex_lock_interruptible(&adapter->mbox_lock))
931 wrb = (u8 *)wrb_from_mbox(adapter);
941 status = be_mbox_notify_wait(adapter);
943 mutex_unlock(&adapter->mbox_lock);
947 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
949 struct be_mcc_wrb *wrb;
950 struct be_cmd_req_eq_create *req;
951 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
954 if (mutex_lock_interruptible(&adapter->mbox_lock))
957 wrb = wrb_from_mbox(adapter);
958 req = embedded_payload(wrb);
960 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
961 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
964 /* Support for EQ_CREATEv2 available only SH-R onwards */
965 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
968 req->hdr.version = ver;
969 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
971 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
973 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
974 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
975 __ilog2_u32(eqo->q.len / 256));
976 be_dws_cpu_to_le(req->context, sizeof(req->context));
978 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
980 status = be_mbox_notify_wait(adapter);
982 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
984 eqo->q.id = le16_to_cpu(resp->eq_id);
986 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
987 eqo->q.created = true;
990 mutex_unlock(&adapter->mbox_lock);
995 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
996 bool permanent, u32 if_handle, u32 pmac_id)
998 struct be_mcc_wrb *wrb;
999 struct be_cmd_req_mac_query *req;
1002 spin_lock_bh(&adapter->mcc_lock);
1004 wrb = wrb_from_mccq(adapter);
1009 req = embedded_payload(wrb);
1011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1012 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1014 req->type = MAC_ADDRESS_TYPE_NETWORK;
1018 req->if_id = cpu_to_le16((u16)if_handle);
1019 req->pmac_id = cpu_to_le32(pmac_id);
1023 status = be_mcc_notify_wait(adapter);
1025 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1027 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1031 spin_unlock_bh(&adapter->mcc_lock);
1035 /* Uses synchronous MCCQ */
1036 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1037 u32 if_id, u32 *pmac_id, u32 domain)
1039 struct be_mcc_wrb *wrb;
1040 struct be_cmd_req_pmac_add *req;
1043 spin_lock_bh(&adapter->mcc_lock);
1045 wrb = wrb_from_mccq(adapter);
1050 req = embedded_payload(wrb);
1052 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1053 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1056 req->hdr.domain = domain;
1057 req->if_id = cpu_to_le32(if_id);
1058 memcpy(req->mac_address, mac_addr, ETH_ALEN);
1060 status = be_mcc_notify_wait(adapter);
1062 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1064 *pmac_id = le32_to_cpu(resp->pmac_id);
1068 spin_unlock_bh(&adapter->mcc_lock);
1070 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1076 /* Uses synchronous MCCQ */
1077 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1079 struct be_mcc_wrb *wrb;
1080 struct be_cmd_req_pmac_del *req;
1086 spin_lock_bh(&adapter->mcc_lock);
1088 wrb = wrb_from_mccq(adapter);
1093 req = embedded_payload(wrb);
1095 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1096 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1099 req->hdr.domain = dom;
1100 req->if_id = cpu_to_le32(if_id);
1101 req->pmac_id = cpu_to_le32(pmac_id);
1103 status = be_mcc_notify_wait(adapter);
1106 spin_unlock_bh(&adapter->mcc_lock);
1111 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1112 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1114 struct be_mcc_wrb *wrb;
1115 struct be_cmd_req_cq_create *req;
1116 struct be_dma_mem *q_mem = &cq->dma_mem;
1120 if (mutex_lock_interruptible(&adapter->mbox_lock))
1123 wrb = wrb_from_mbox(adapter);
1124 req = embedded_payload(wrb);
1125 ctxt = &req->context;
1127 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1128 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1131 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1133 if (BEx_chip(adapter)) {
1134 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1136 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1138 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1139 __ilog2_u32(cq->len / 256));
1140 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1141 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1142 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1144 req->hdr.version = 2;
1145 req->page_size = 1; /* 1 for 4K */
1147 /* coalesce-wm field in this cmd is not relevant to Lancer.
1148 * Lancer uses COMMON_MODIFY_CQ to set this field
1150 if (!lancer_chip(adapter))
1151 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1153 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1155 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1156 __ilog2_u32(cq->len / 256));
1157 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1158 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1159 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1162 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1164 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1166 status = be_mbox_notify_wait(adapter);
1168 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1170 cq->id = le16_to_cpu(resp->cq_id);
1174 mutex_unlock(&adapter->mbox_lock);
1179 static u32 be_encoded_q_len(int q_len)
1181 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1183 if (len_encoded == 16)
1188 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1189 struct be_queue_info *mccq,
1190 struct be_queue_info *cq)
1192 struct be_mcc_wrb *wrb;
1193 struct be_cmd_req_mcc_ext_create *req;
1194 struct be_dma_mem *q_mem = &mccq->dma_mem;
1198 if (mutex_lock_interruptible(&adapter->mbox_lock))
1201 wrb = wrb_from_mbox(adapter);
1202 req = embedded_payload(wrb);
1203 ctxt = &req->context;
1205 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1206 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1209 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1210 if (BEx_chip(adapter)) {
1211 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1212 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1213 be_encoded_q_len(mccq->len));
1214 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1216 req->hdr.version = 1;
1217 req->cq_id = cpu_to_le16(cq->id);
1219 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1220 be_encoded_q_len(mccq->len));
1221 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1222 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1224 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1228 /* Subscribe to Link State, Sliport Event and Group 5 Events
1229 * (bits 1, 5 and 17 set)
1231 req->async_event_bitmap[0] =
1232 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1233 BIT(ASYNC_EVENT_CODE_GRP_5) |
1234 BIT(ASYNC_EVENT_CODE_QNQ) |
1235 BIT(ASYNC_EVENT_CODE_SLIPORT));
1237 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1239 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1241 status = be_mbox_notify_wait(adapter);
1243 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1245 mccq->id = le16_to_cpu(resp->id);
1246 mccq->created = true;
1248 mutex_unlock(&adapter->mbox_lock);
1253 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1254 struct be_queue_info *mccq,
1255 struct be_queue_info *cq)
1257 struct be_mcc_wrb *wrb;
1258 struct be_cmd_req_mcc_create *req;
1259 struct be_dma_mem *q_mem = &mccq->dma_mem;
1263 if (mutex_lock_interruptible(&adapter->mbox_lock))
1266 wrb = wrb_from_mbox(adapter);
1267 req = embedded_payload(wrb);
1268 ctxt = &req->context;
1270 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1271 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1274 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1276 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1277 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1278 be_encoded_q_len(mccq->len));
1279 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1281 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1283 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1285 status = be_mbox_notify_wait(adapter);
1287 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1289 mccq->id = le16_to_cpu(resp->id);
1290 mccq->created = true;
1293 mutex_unlock(&adapter->mbox_lock);
1297 int be_cmd_mccq_create(struct be_adapter *adapter,
1298 struct be_queue_info *mccq, struct be_queue_info *cq)
1302 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1303 if (status && BEx_chip(adapter)) {
1304 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1305 "or newer to avoid conflicting priorities between NIC "
1306 "and FCoE traffic");
1307 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1312 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1314 struct be_mcc_wrb wrb = {0};
1315 struct be_cmd_req_eth_tx_create *req;
1316 struct be_queue_info *txq = &txo->q;
1317 struct be_queue_info *cq = &txo->cq;
1318 struct be_dma_mem *q_mem = &txq->dma_mem;
1319 int status, ver = 0;
1321 req = embedded_payload(&wrb);
1322 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1323 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1325 if (lancer_chip(adapter)) {
1326 req->hdr.version = 1;
1327 } else if (BEx_chip(adapter)) {
1328 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1329 req->hdr.version = 2;
1330 } else { /* For SH */
1331 req->hdr.version = 2;
1334 if (req->hdr.version > 0)
1335 req->if_id = cpu_to_le16(adapter->if_handle);
1336 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1337 req->ulp_num = BE_ULP1_NUM;
1338 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1339 req->cq_id = cpu_to_le16(cq->id);
1340 req->queue_size = be_encoded_q_len(txq->len);
1341 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1342 ver = req->hdr.version;
1344 status = be_cmd_notify_wait(adapter, &wrb);
1346 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1348 txq->id = le16_to_cpu(resp->cid);
1350 txo->db_offset = le32_to_cpu(resp->db_offset);
1352 txo->db_offset = DB_TXULP1_OFFSET;
1353 txq->created = true;
1360 int be_cmd_rxq_create(struct be_adapter *adapter,
1361 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1362 u32 if_id, u32 rss, u8 *rss_id)
1364 struct be_mcc_wrb *wrb;
1365 struct be_cmd_req_eth_rx_create *req;
1366 struct be_dma_mem *q_mem = &rxq->dma_mem;
1369 spin_lock_bh(&adapter->mcc_lock);
1371 wrb = wrb_from_mccq(adapter);
1376 req = embedded_payload(wrb);
1378 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1379 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1381 req->cq_id = cpu_to_le16(cq_id);
1382 req->frag_size = fls(frag_size) - 1;
1384 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1385 req->interface_id = cpu_to_le32(if_id);
1386 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1387 req->rss_queue = cpu_to_le32(rss);
1389 status = be_mcc_notify_wait(adapter);
1391 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1393 rxq->id = le16_to_cpu(resp->id);
1394 rxq->created = true;
1395 *rss_id = resp->rss_id;
1399 spin_unlock_bh(&adapter->mcc_lock);
1403 /* Generic destroyer function for all types of queues
1406 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1409 struct be_mcc_wrb *wrb;
1410 struct be_cmd_req_q_destroy *req;
1411 u8 subsys = 0, opcode = 0;
1414 if (mutex_lock_interruptible(&adapter->mbox_lock))
1417 wrb = wrb_from_mbox(adapter);
1418 req = embedded_payload(wrb);
1420 switch (queue_type) {
1422 subsys = CMD_SUBSYSTEM_COMMON;
1423 opcode = OPCODE_COMMON_EQ_DESTROY;
1426 subsys = CMD_SUBSYSTEM_COMMON;
1427 opcode = OPCODE_COMMON_CQ_DESTROY;
1430 subsys = CMD_SUBSYSTEM_ETH;
1431 opcode = OPCODE_ETH_TX_DESTROY;
1434 subsys = CMD_SUBSYSTEM_ETH;
1435 opcode = OPCODE_ETH_RX_DESTROY;
1438 subsys = CMD_SUBSYSTEM_COMMON;
1439 opcode = OPCODE_COMMON_MCC_DESTROY;
1445 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1447 req->id = cpu_to_le16(q->id);
1449 status = be_mbox_notify_wait(adapter);
1452 mutex_unlock(&adapter->mbox_lock);
1457 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1459 struct be_mcc_wrb *wrb;
1460 struct be_cmd_req_q_destroy *req;
1463 spin_lock_bh(&adapter->mcc_lock);
1465 wrb = wrb_from_mccq(adapter);
1470 req = embedded_payload(wrb);
1472 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1473 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1474 req->id = cpu_to_le16(q->id);
1476 status = be_mcc_notify_wait(adapter);
1480 spin_unlock_bh(&adapter->mcc_lock);
1484 /* Create an rx filtering policy configuration on an i/f
1485 * Will use MBOX only if MCCQ has not been created.
1487 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1488 u32 *if_handle, u32 domain)
1490 struct be_mcc_wrb wrb = {0};
1491 struct be_cmd_req_if_create *req;
1494 req = embedded_payload(&wrb);
1495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1496 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1497 sizeof(*req), &wrb, NULL);
1498 req->hdr.domain = domain;
1499 req->capability_flags = cpu_to_le32(cap_flags);
1500 req->enable_flags = cpu_to_le32(en_flags);
1501 req->pmac_invalid = true;
1503 status = be_cmd_notify_wait(adapter, &wrb);
1505 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1507 *if_handle = le32_to_cpu(resp->interface_id);
1509 /* Hack to retrieve VF's pmac-id on BE3 */
1510 if (BE3_chip(adapter) && be_virtfn(adapter))
1511 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1517 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1519 struct be_mcc_wrb *wrb;
1520 struct be_cmd_req_if_destroy *req;
1523 if (interface_id == -1)
1526 spin_lock_bh(&adapter->mcc_lock);
1528 wrb = wrb_from_mccq(adapter);
1533 req = embedded_payload(wrb);
1535 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1536 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1537 sizeof(*req), wrb, NULL);
1538 req->hdr.domain = domain;
1539 req->interface_id = cpu_to_le32(interface_id);
1541 status = be_mcc_notify_wait(adapter);
1543 spin_unlock_bh(&adapter->mcc_lock);
1547 /* Get stats is a non embedded command: the request is not embedded inside
1548 * WRB but is a separate dma memory block
1549 * Uses asynchronous MCC
1551 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1553 struct be_mcc_wrb *wrb;
1554 struct be_cmd_req_hdr *hdr;
1557 spin_lock_bh(&adapter->mcc_lock);
1559 wrb = wrb_from_mccq(adapter);
1564 hdr = nonemb_cmd->va;
1566 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1567 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1570 /* version 1 of the cmd is not supported only by BE2 */
1571 if (BE2_chip(adapter))
1573 if (BE3_chip(adapter) || lancer_chip(adapter))
1578 status = be_mcc_notify(adapter);
1582 adapter->stats_cmd_sent = true;
1585 spin_unlock_bh(&adapter->mcc_lock);
1590 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1591 struct be_dma_mem *nonemb_cmd)
1593 struct be_mcc_wrb *wrb;
1594 struct lancer_cmd_req_pport_stats *req;
1597 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1601 spin_lock_bh(&adapter->mcc_lock);
1603 wrb = wrb_from_mccq(adapter);
1608 req = nonemb_cmd->va;
1610 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1611 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1614 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1615 req->cmd_params.params.reset_stats = 0;
1617 status = be_mcc_notify(adapter);
1621 adapter->stats_cmd_sent = true;
1624 spin_unlock_bh(&adapter->mcc_lock);
1628 static int be_mac_to_link_speed(int mac_speed)
1630 switch (mac_speed) {
1631 case PHY_LINK_SPEED_ZERO:
1633 case PHY_LINK_SPEED_10MBPS:
1635 case PHY_LINK_SPEED_100MBPS:
1637 case PHY_LINK_SPEED_1GBPS:
1639 case PHY_LINK_SPEED_10GBPS:
1641 case PHY_LINK_SPEED_20GBPS:
1643 case PHY_LINK_SPEED_25GBPS:
1645 case PHY_LINK_SPEED_40GBPS:
1651 /* Uses synchronous mcc
1652 * Returns link_speed in Mbps
1654 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1655 u8 *link_status, u32 dom)
1657 struct be_mcc_wrb *wrb;
1658 struct be_cmd_req_link_status *req;
1661 spin_lock_bh(&adapter->mcc_lock);
1664 *link_status = LINK_DOWN;
1666 wrb = wrb_from_mccq(adapter);
1671 req = embedded_payload(wrb);
1673 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1674 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1675 sizeof(*req), wrb, NULL);
1677 /* version 1 of the cmd is not supported only by BE2 */
1678 if (!BE2_chip(adapter))
1679 req->hdr.version = 1;
1681 req->hdr.domain = dom;
1683 status = be_mcc_notify_wait(adapter);
1685 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1688 *link_speed = resp->link_speed ?
1689 le16_to_cpu(resp->link_speed) * 10 :
1690 be_mac_to_link_speed(resp->mac_speed);
1692 if (!resp->logical_link_status)
1696 *link_status = resp->logical_link_status;
1700 spin_unlock_bh(&adapter->mcc_lock);
1704 /* Uses synchronous mcc */
1705 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1707 struct be_mcc_wrb *wrb;
1708 struct be_cmd_req_get_cntl_addnl_attribs *req;
1711 spin_lock_bh(&adapter->mcc_lock);
1713 wrb = wrb_from_mccq(adapter);
1718 req = embedded_payload(wrb);
1720 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1721 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1722 sizeof(*req), wrb, NULL);
1724 status = be_mcc_notify(adapter);
1726 spin_unlock_bh(&adapter->mcc_lock);
1730 /* Uses synchronous mcc */
1731 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1733 struct be_mcc_wrb wrb = {0};
1734 struct be_cmd_req_get_fat *req;
1737 req = embedded_payload(&wrb);
1739 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1740 OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1742 req->fat_operation = cpu_to_le32(QUERY_FAT);
1743 status = be_cmd_notify_wait(adapter, &wrb);
1745 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1747 if (dump_size && resp->log_size)
1748 *dump_size = le32_to_cpu(resp->log_size) -
1754 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1756 struct be_dma_mem get_fat_cmd;
1757 struct be_mcc_wrb *wrb;
1758 struct be_cmd_req_get_fat *req;
1759 u32 offset = 0, total_size, buf_size,
1760 log_offset = sizeof(u32), payload_len;
1766 total_size = buf_len;
1768 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1769 get_fat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
1771 &get_fat_cmd.dma, GFP_ATOMIC);
1772 if (!get_fat_cmd.va)
1775 spin_lock_bh(&adapter->mcc_lock);
1777 while (total_size) {
1778 buf_size = min(total_size, (u32)60*1024);
1779 total_size -= buf_size;
1781 wrb = wrb_from_mccq(adapter);
1786 req = get_fat_cmd.va;
1788 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1789 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1790 OPCODE_COMMON_MANAGE_FAT, payload_len,
1793 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1794 req->read_log_offset = cpu_to_le32(log_offset);
1795 req->read_log_length = cpu_to_le32(buf_size);
1796 req->data_buffer_size = cpu_to_le32(buf_size);
1798 status = be_mcc_notify_wait(adapter);
1800 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1802 memcpy(buf + offset,
1804 le32_to_cpu(resp->read_log_length));
1806 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1810 log_offset += buf_size;
1813 dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1814 get_fat_cmd.va, get_fat_cmd.dma);
1815 spin_unlock_bh(&adapter->mcc_lock);
1819 /* Uses synchronous mcc */
1820 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1822 struct be_mcc_wrb *wrb;
1823 struct be_cmd_req_get_fw_version *req;
1826 spin_lock_bh(&adapter->mcc_lock);
1828 wrb = wrb_from_mccq(adapter);
1834 req = embedded_payload(wrb);
1836 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1837 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1839 status = be_mcc_notify_wait(adapter);
1841 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1843 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1844 sizeof(adapter->fw_ver));
1845 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1846 sizeof(adapter->fw_on_flash));
1849 spin_unlock_bh(&adapter->mcc_lock);
1853 /* set the EQ delay interval of an EQ to specified value
1856 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1857 struct be_set_eqd *set_eqd, int num)
1859 struct be_mcc_wrb *wrb;
1860 struct be_cmd_req_modify_eq_delay *req;
1863 spin_lock_bh(&adapter->mcc_lock);
1865 wrb = wrb_from_mccq(adapter);
1870 req = embedded_payload(wrb);
1872 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1873 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1876 req->num_eq = cpu_to_le32(num);
1877 for (i = 0; i < num; i++) {
1878 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1879 req->set_eqd[i].phase = 0;
1880 req->set_eqd[i].delay_multiplier =
1881 cpu_to_le32(set_eqd[i].delay_multiplier);
1884 status = be_mcc_notify(adapter);
1886 spin_unlock_bh(&adapter->mcc_lock);
1890 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1896 num_eqs = min(num, 8);
1897 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1905 /* Uses sycnhronous mcc */
1906 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1907 u32 num, u32 domain)
1909 struct be_mcc_wrb *wrb;
1910 struct be_cmd_req_vlan_config *req;
1913 spin_lock_bh(&adapter->mcc_lock);
1915 wrb = wrb_from_mccq(adapter);
1920 req = embedded_payload(wrb);
1922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1923 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1925 req->hdr.domain = domain;
1927 req->interface_id = if_id;
1928 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1929 req->num_vlan = num;
1930 memcpy(req->normal_vlan, vtag_array,
1931 req->num_vlan * sizeof(vtag_array[0]));
1933 status = be_mcc_notify_wait(adapter);
1935 spin_unlock_bh(&adapter->mcc_lock);
1939 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1941 struct be_mcc_wrb *wrb;
1942 struct be_dma_mem *mem = &adapter->rx_filter;
1943 struct be_cmd_req_rx_filter *req = mem->va;
1946 spin_lock_bh(&adapter->mcc_lock);
1948 wrb = wrb_from_mccq(adapter);
1953 memset(req, 0, sizeof(*req));
1954 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1955 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1958 req->if_id = cpu_to_le32(adapter->if_handle);
1959 req->if_flags_mask = cpu_to_le32(flags);
1960 req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1962 if (flags & BE_IF_FLAGS_MULTICAST) {
1963 struct netdev_hw_addr *ha;
1966 /* Reset mcast promisc mode if already set by setting mask
1967 * and not setting flags field
1969 req->if_flags_mask |=
1970 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1971 be_if_cap_flags(adapter));
1972 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1973 netdev_for_each_mc_addr(ha, adapter->netdev)
1974 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1977 status = be_mcc_notify_wait(adapter);
1979 spin_unlock_bh(&adapter->mcc_lock);
1983 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1985 struct device *dev = &adapter->pdev->dev;
1987 if ((flags & be_if_cap_flags(adapter)) != flags) {
1988 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
1989 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
1990 be_if_cap_flags(adapter));
1992 flags &= be_if_cap_flags(adapter);
1996 return __be_cmd_rx_filter(adapter, flags, value);
1999 /* Uses synchrounous mcc */
2000 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2002 struct be_mcc_wrb *wrb;
2003 struct be_cmd_req_set_flow_control *req;
2006 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2007 CMD_SUBSYSTEM_COMMON))
2010 spin_lock_bh(&adapter->mcc_lock);
2012 wrb = wrb_from_mccq(adapter);
2017 req = embedded_payload(wrb);
2019 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2020 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2023 req->hdr.version = 1;
2024 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2025 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2027 status = be_mcc_notify_wait(adapter);
2030 spin_unlock_bh(&adapter->mcc_lock);
2032 if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2039 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2041 struct be_mcc_wrb *wrb;
2042 struct be_cmd_req_get_flow_control *req;
2045 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2046 CMD_SUBSYSTEM_COMMON))
2049 spin_lock_bh(&adapter->mcc_lock);
2051 wrb = wrb_from_mccq(adapter);
2056 req = embedded_payload(wrb);
2058 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2059 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2062 status = be_mcc_notify_wait(adapter);
2064 struct be_cmd_resp_get_flow_control *resp =
2065 embedded_payload(wrb);
2067 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2068 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2072 spin_unlock_bh(&adapter->mcc_lock);
2077 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2079 struct be_mcc_wrb *wrb;
2080 struct be_cmd_req_query_fw_cfg *req;
2083 if (mutex_lock_interruptible(&adapter->mbox_lock))
2086 wrb = wrb_from_mbox(adapter);
2087 req = embedded_payload(wrb);
2089 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2090 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2091 sizeof(*req), wrb, NULL);
2093 status = be_mbox_notify_wait(adapter);
2095 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2097 adapter->port_num = le32_to_cpu(resp->phys_port);
2098 adapter->function_mode = le32_to_cpu(resp->function_mode);
2099 adapter->function_caps = le32_to_cpu(resp->function_caps);
2100 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2101 dev_info(&adapter->pdev->dev,
2102 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2103 adapter->function_mode, adapter->function_caps);
2106 mutex_unlock(&adapter->mbox_lock);
2111 int be_cmd_reset_function(struct be_adapter *adapter)
2113 struct be_mcc_wrb *wrb;
2114 struct be_cmd_req_hdr *req;
2117 if (lancer_chip(adapter)) {
2118 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2119 adapter->db + SLIPORT_CONTROL_OFFSET);
2120 status = lancer_wait_ready(adapter);
2122 dev_err(&adapter->pdev->dev,
2123 "Adapter in non recoverable error\n");
2127 if (mutex_lock_interruptible(&adapter->mbox_lock))
2130 wrb = wrb_from_mbox(adapter);
2131 req = embedded_payload(wrb);
2133 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2134 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2137 status = be_mbox_notify_wait(adapter);
2139 mutex_unlock(&adapter->mbox_lock);
2143 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2144 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2146 struct be_mcc_wrb *wrb;
2147 struct be_cmd_req_rss_config *req;
2150 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2153 spin_lock_bh(&adapter->mcc_lock);
2155 wrb = wrb_from_mccq(adapter);
2160 req = embedded_payload(wrb);
2162 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2163 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2165 req->if_id = cpu_to_le32(adapter->if_handle);
2166 req->enable_rss = cpu_to_le16(rss_hash_opts);
2167 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2169 if (!BEx_chip(adapter))
2170 req->hdr.version = 1;
2172 memcpy(req->cpu_table, rsstable, table_size);
2173 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2174 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2176 status = be_mcc_notify_wait(adapter);
2178 spin_unlock_bh(&adapter->mcc_lock);
2183 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2184 u8 bcn, u8 sts, u8 state)
2186 struct be_mcc_wrb *wrb;
2187 struct be_cmd_req_enable_disable_beacon *req;
2190 spin_lock_bh(&adapter->mcc_lock);
2192 wrb = wrb_from_mccq(adapter);
2197 req = embedded_payload(wrb);
2199 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2200 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2201 sizeof(*req), wrb, NULL);
2203 req->port_num = port_num;
2204 req->beacon_state = state;
2205 req->beacon_duration = bcn;
2206 req->status_duration = sts;
2208 status = be_mcc_notify_wait(adapter);
2211 spin_unlock_bh(&adapter->mcc_lock);
2216 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2218 struct be_mcc_wrb *wrb;
2219 struct be_cmd_req_get_beacon_state *req;
2222 spin_lock_bh(&adapter->mcc_lock);
2224 wrb = wrb_from_mccq(adapter);
2229 req = embedded_payload(wrb);
2231 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2232 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2235 req->port_num = port_num;
2237 status = be_mcc_notify_wait(adapter);
2239 struct be_cmd_resp_get_beacon_state *resp =
2240 embedded_payload(wrb);
2242 *state = resp->beacon_state;
2246 spin_unlock_bh(&adapter->mcc_lock);
2251 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2252 u8 page_num, u8 *data)
2254 struct be_dma_mem cmd;
2255 struct be_mcc_wrb *wrb;
2256 struct be_cmd_req_port_type *req;
2259 if (page_num > TR_PAGE_A2)
2262 cmd.size = sizeof(struct be_cmd_resp_port_type);
2263 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2266 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2270 spin_lock_bh(&adapter->mcc_lock);
2272 wrb = wrb_from_mccq(adapter);
2279 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2280 OPCODE_COMMON_READ_TRANSRECV_DATA,
2281 cmd.size, wrb, &cmd);
2283 req->port = cpu_to_le32(adapter->hba_port_num);
2284 req->page_num = cpu_to_le32(page_num);
2285 status = be_mcc_notify_wait(adapter);
2287 struct be_cmd_resp_port_type *resp = cmd.va;
2289 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2292 spin_unlock_bh(&adapter->mcc_lock);
2293 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2297 static int lancer_cmd_write_object(struct be_adapter *adapter,
2298 struct be_dma_mem *cmd, u32 data_size,
2299 u32 data_offset, const char *obj_name,
2300 u32 *data_written, u8 *change_status,
2303 struct be_mcc_wrb *wrb;
2304 struct lancer_cmd_req_write_object *req;
2305 struct lancer_cmd_resp_write_object *resp;
2309 spin_lock_bh(&adapter->mcc_lock);
2310 adapter->flash_status = 0;
2312 wrb = wrb_from_mccq(adapter);
2318 req = embedded_payload(wrb);
2320 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2321 OPCODE_COMMON_WRITE_OBJECT,
2322 sizeof(struct lancer_cmd_req_write_object), wrb,
2325 ctxt = &req->context;
2326 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2327 write_length, ctxt, data_size);
2330 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2333 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2336 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2337 req->write_offset = cpu_to_le32(data_offset);
2338 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2339 req->descriptor_count = cpu_to_le32(1);
2340 req->buf_len = cpu_to_le32(data_size);
2341 req->addr_low = cpu_to_le32((cmd->dma +
2342 sizeof(struct lancer_cmd_req_write_object))
2344 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2345 sizeof(struct lancer_cmd_req_write_object)));
2347 status = be_mcc_notify(adapter);
2351 spin_unlock_bh(&adapter->mcc_lock);
2353 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2354 msecs_to_jiffies(60000)))
2355 status = -ETIMEDOUT;
2357 status = adapter->flash_status;
2359 resp = embedded_payload(wrb);
2361 *data_written = le32_to_cpu(resp->actual_write_len);
2362 *change_status = resp->change_status;
2364 *addn_status = resp->additional_status;
2370 spin_unlock_bh(&adapter->mcc_lock);
2374 int be_cmd_query_cable_type(struct be_adapter *adapter)
2376 u8 page_data[PAGE_DATA_LEN];
2379 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2382 switch (adapter->phy.interface_type) {
2384 adapter->phy.cable_type =
2385 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2387 case PHY_TYPE_SFP_PLUS_10GB:
2388 adapter->phy.cable_type =
2389 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2392 adapter->phy.cable_type = 0;
2399 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2401 u8 page_data[PAGE_DATA_LEN];
2404 status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2407 strlcpy(adapter->phy.vendor_name, page_data +
2408 SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2409 strlcpy(adapter->phy.vendor_pn,
2410 page_data + SFP_VENDOR_PN_OFFSET,
2411 SFP_VENDOR_NAME_LEN - 1);
2417 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2418 const char *obj_name)
2420 struct lancer_cmd_req_delete_object *req;
2421 struct be_mcc_wrb *wrb;
2424 spin_lock_bh(&adapter->mcc_lock);
2426 wrb = wrb_from_mccq(adapter);
2432 req = embedded_payload(wrb);
2434 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2435 OPCODE_COMMON_DELETE_OBJECT,
2436 sizeof(*req), wrb, NULL);
2438 strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2440 status = be_mcc_notify_wait(adapter);
2442 spin_unlock_bh(&adapter->mcc_lock);
2446 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2447 u32 data_size, u32 data_offset, const char *obj_name,
2448 u32 *data_read, u32 *eof, u8 *addn_status)
2450 struct be_mcc_wrb *wrb;
2451 struct lancer_cmd_req_read_object *req;
2452 struct lancer_cmd_resp_read_object *resp;
2455 spin_lock_bh(&adapter->mcc_lock);
2457 wrb = wrb_from_mccq(adapter);
2463 req = embedded_payload(wrb);
2465 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2466 OPCODE_COMMON_READ_OBJECT,
2467 sizeof(struct lancer_cmd_req_read_object), wrb,
2470 req->desired_read_len = cpu_to_le32(data_size);
2471 req->read_offset = cpu_to_le32(data_offset);
2472 strcpy(req->object_name, obj_name);
2473 req->descriptor_count = cpu_to_le32(1);
2474 req->buf_len = cpu_to_le32(data_size);
2475 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2476 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2478 status = be_mcc_notify_wait(adapter);
2480 resp = embedded_payload(wrb);
2482 *data_read = le32_to_cpu(resp->actual_read_len);
2483 *eof = le32_to_cpu(resp->eof);
2485 *addn_status = resp->additional_status;
2489 spin_unlock_bh(&adapter->mcc_lock);
2493 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2494 struct be_dma_mem *cmd, u32 flash_type,
2495 u32 flash_opcode, u32 img_offset, u32 buf_size)
2497 struct be_mcc_wrb *wrb;
2498 struct be_cmd_write_flashrom *req;
2501 spin_lock_bh(&adapter->mcc_lock);
2502 adapter->flash_status = 0;
2504 wrb = wrb_from_mccq(adapter);
2511 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2512 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2515 req->params.op_type = cpu_to_le32(flash_type);
2516 if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2517 req->params.offset = cpu_to_le32(img_offset);
2519 req->params.op_code = cpu_to_le32(flash_opcode);
2520 req->params.data_buf_size = cpu_to_le32(buf_size);
2522 status = be_mcc_notify(adapter);
2526 spin_unlock_bh(&adapter->mcc_lock);
2528 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2529 msecs_to_jiffies(40000)))
2530 status = -ETIMEDOUT;
2532 status = adapter->flash_status;
2537 spin_unlock_bh(&adapter->mcc_lock);
2541 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2542 u16 img_optype, u32 img_offset, u32 crc_offset)
2544 struct be_cmd_read_flash_crc *req;
2545 struct be_mcc_wrb *wrb;
2548 spin_lock_bh(&adapter->mcc_lock);
2550 wrb = wrb_from_mccq(adapter);
2555 req = embedded_payload(wrb);
2557 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2558 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2561 req->params.op_type = cpu_to_le32(img_optype);
2562 if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2563 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2565 req->params.offset = cpu_to_le32(crc_offset);
2567 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2568 req->params.data_buf_size = cpu_to_le32(0x4);
2570 status = be_mcc_notify_wait(adapter);
2572 memcpy(flashed_crc, req->crc, 4);
2575 spin_unlock_bh(&adapter->mcc_lock);
2579 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2581 static bool phy_flashing_required(struct be_adapter *adapter)
2583 return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2584 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2587 static bool is_comp_in_ufi(struct be_adapter *adapter,
2588 struct flash_section_info *fsec, int type)
2590 int i = 0, img_type = 0;
2591 struct flash_section_info_g2 *fsec_g2 = NULL;
2593 if (BE2_chip(adapter))
2594 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2596 for (i = 0; i < MAX_FLASH_COMP; i++) {
2598 img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2600 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2602 if (img_type == type)
2608 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2610 const struct firmware *fw)
2612 struct flash_section_info *fsec = NULL;
2613 const u8 *p = fw->data;
2616 while (p < (fw->data + fw->size)) {
2617 fsec = (struct flash_section_info *)p;
2618 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2625 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2626 u32 img_offset, u32 img_size, int hdr_size,
2627 u16 img_optype, bool *crc_match)
2633 status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2638 crc_offset = hdr_size + img_offset + img_size - 4;
2640 /* Skip flashing, if crc of flashed region matches */
2641 if (!memcmp(crc, p + crc_offset, 4))
2649 static int be_flash(struct be_adapter *adapter, const u8 *img,
2650 struct be_dma_mem *flash_cmd, int optype, int img_size,
2653 u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2654 struct be_cmd_write_flashrom *req = flash_cmd->va;
2657 while (total_bytes) {
2658 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2660 total_bytes -= num_bytes;
2663 if (optype == OPTYPE_PHY_FW)
2664 flash_op = FLASHROM_OPER_PHY_FLASH;
2666 flash_op = FLASHROM_OPER_FLASH;
2668 if (optype == OPTYPE_PHY_FW)
2669 flash_op = FLASHROM_OPER_PHY_SAVE;
2671 flash_op = FLASHROM_OPER_SAVE;
2674 memcpy(req->data_buf, img, num_bytes);
2676 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2677 flash_op, img_offset +
2678 bytes_sent, num_bytes);
2679 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2680 optype == OPTYPE_PHY_FW)
2685 bytes_sent += num_bytes;
2690 /* For BE2, BE3 and BE3-R */
2691 static int be_flash_BEx(struct be_adapter *adapter,
2692 const struct firmware *fw,
2693 struct be_dma_mem *flash_cmd, int num_of_images)
2695 int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2696 struct device *dev = &adapter->pdev->dev;
2697 struct flash_section_info *fsec = NULL;
2698 int status, i, filehdr_size, num_comp;
2699 const struct flash_comp *pflashcomp;
2703 struct flash_comp gen3_flash_types[] = {
2704 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2705 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2706 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2707 BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2708 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2709 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2710 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2711 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2712 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2713 BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2714 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2715 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2716 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2717 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2718 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2719 BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2720 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2721 BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2722 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2723 BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2726 struct flash_comp gen2_flash_types[] = {
2727 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2728 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2729 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2730 BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2731 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2732 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2733 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2734 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2735 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2736 BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2737 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2738 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2739 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2740 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2741 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2742 BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2745 if (BE3_chip(adapter)) {
2746 pflashcomp = gen3_flash_types;
2747 filehdr_size = sizeof(struct flash_file_hdr_g3);
2748 num_comp = ARRAY_SIZE(gen3_flash_types);
2750 pflashcomp = gen2_flash_types;
2751 filehdr_size = sizeof(struct flash_file_hdr_g2);
2752 num_comp = ARRAY_SIZE(gen2_flash_types);
2756 /* Get flash section info*/
2757 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2759 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2762 for (i = 0; i < num_comp; i++) {
2763 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2766 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2767 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2770 if (pflashcomp[i].optype == OPTYPE_PHY_FW &&
2771 !phy_flashing_required(adapter))
2774 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2775 status = be_check_flash_crc(adapter, fw->data,
2776 pflashcomp[i].offset,
2780 OPTYPE_REDBOOT, &crc_match);
2783 "Could not get CRC for 0x%x region\n",
2784 pflashcomp[i].optype);
2792 p = fw->data + filehdr_size + pflashcomp[i].offset +
2794 if (p + pflashcomp[i].size > fw->data + fw->size)
2797 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2798 pflashcomp[i].size, 0);
2800 dev_err(dev, "Flashing section type 0x%x failed\n",
2801 pflashcomp[i].img_type);
2808 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2810 u32 img_type = le32_to_cpu(fsec_entry.type);
2811 u16 img_optype = le16_to_cpu(fsec_entry.optype);
2813 if (img_optype != 0xFFFF)
2817 case IMAGE_FIRMWARE_ISCSI:
2818 img_optype = OPTYPE_ISCSI_ACTIVE;
2820 case IMAGE_BOOT_CODE:
2821 img_optype = OPTYPE_REDBOOT;
2823 case IMAGE_OPTION_ROM_ISCSI:
2824 img_optype = OPTYPE_BIOS;
2826 case IMAGE_OPTION_ROM_PXE:
2827 img_optype = OPTYPE_PXE_BIOS;
2829 case IMAGE_OPTION_ROM_FCOE:
2830 img_optype = OPTYPE_FCOE_BIOS;
2832 case IMAGE_FIRMWARE_BACKUP_ISCSI:
2833 img_optype = OPTYPE_ISCSI_BACKUP;
2836 img_optype = OPTYPE_NCSI_FW;
2838 case IMAGE_FLASHISM_JUMPVECTOR:
2839 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2841 case IMAGE_FIRMWARE_PHY:
2842 img_optype = OPTYPE_SH_PHY_FW;
2844 case IMAGE_REDBOOT_DIR:
2845 img_optype = OPTYPE_REDBOOT_DIR;
2847 case IMAGE_REDBOOT_CONFIG:
2848 img_optype = OPTYPE_REDBOOT_CONFIG;
2851 img_optype = OPTYPE_UFI_DIR;
2860 static int be_flash_skyhawk(struct be_adapter *adapter,
2861 const struct firmware *fw,
2862 struct be_dma_mem *flash_cmd, int num_of_images)
2864 int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2865 bool crc_match, old_fw_img, flash_offset_support = true;
2866 struct device *dev = &adapter->pdev->dev;
2867 struct flash_section_info *fsec = NULL;
2868 u32 img_offset, img_size, img_type;
2869 u16 img_optype, flash_optype;
2870 int status, i, filehdr_size;
2873 filehdr_size = sizeof(struct flash_file_hdr_g3);
2874 fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2876 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2881 for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2882 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2883 img_size = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2884 img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2885 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2886 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2888 if (img_optype == 0xFFFF)
2891 if (flash_offset_support)
2892 flash_optype = OPTYPE_OFFSET_SPECIFIED;
2894 flash_optype = img_optype;
2896 /* Don't bother verifying CRC if an old FW image is being
2902 status = be_check_flash_crc(adapter, fw->data, img_offset,
2903 img_size, filehdr_size +
2904 img_hdrs_size, flash_optype,
2906 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2907 base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2908 /* The current FW image on the card does not support
2909 * OFFSET based flashing. Retry using older mechanism
2910 * of OPTYPE based flashing
2912 if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2913 flash_offset_support = false;
2917 /* The current FW image on the card does not recognize
2918 * the new FLASH op_type. The FW download is partially
2919 * complete. Reboot the server now to enable FW image
2920 * to recognize the new FLASH op_type. To complete the
2921 * remaining process, download the same FW again after
2924 dev_err(dev, "Flash incomplete. Reset the server\n");
2925 dev_err(dev, "Download FW image again after reset\n");
2927 } else if (status) {
2928 dev_err(dev, "Could not get CRC for 0x%x region\n",
2937 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2938 if (p + img_size > fw->data + fw->size)
2941 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
2944 /* The current FW image on the card does not support OFFSET
2945 * based flashing. Retry using older mechanism of OPTYPE based
2948 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
2949 flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2950 flash_offset_support = false;
2954 /* For old FW images ignore ILLEGAL_FIELD error or errors on
2958 (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
2959 (img_optype == OPTYPE_UFI_DIR &&
2960 base_status(status) == MCC_STATUS_FAILED))) {
2962 } else if (status) {
2963 dev_err(dev, "Flashing section type 0x%x failed\n",
2966 switch (addl_status(status)) {
2967 case MCC_ADDL_STATUS_MISSING_SIGNATURE:
2969 "Digital signature missing in FW\n");
2971 case MCC_ADDL_STATUS_INVALID_SIGNATURE:
2973 "Invalid digital signature in FW\n");
2983 int lancer_fw_download(struct be_adapter *adapter,
2984 const struct firmware *fw)
2986 struct device *dev = &adapter->pdev->dev;
2987 struct be_dma_mem flash_cmd;
2988 const u8 *data_ptr = NULL;
2989 u8 *dest_image_ptr = NULL;
2990 size_t image_size = 0;
2992 u32 data_written = 0;
2998 if (!IS_ALIGNED(fw->size, sizeof(u32))) {
2999 dev_err(dev, "FW image size should be multiple of 4\n");
3003 flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3004 + LANCER_FW_DOWNLOAD_CHUNK;
3005 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size,
3006 &flash_cmd.dma, GFP_KERNEL);
3010 dest_image_ptr = flash_cmd.va +
3011 sizeof(struct lancer_cmd_req_write_object);
3012 image_size = fw->size;
3013 data_ptr = fw->data;
3015 while (image_size) {
3016 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3018 /* Copy the image chunk content. */
3019 memcpy(dest_image_ptr, data_ptr, chunk_size);
3021 status = lancer_cmd_write_object(adapter, &flash_cmd,
3023 LANCER_FW_DOWNLOAD_LOCATION,
3024 &data_written, &change_status,
3029 offset += data_written;
3030 data_ptr += data_written;
3031 image_size -= data_written;
3035 /* Commit the FW written */
3036 status = lancer_cmd_write_object(adapter, &flash_cmd,
3038 LANCER_FW_DOWNLOAD_LOCATION,
3039 &data_written, &change_status,
3043 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3045 dev_err(dev, "Firmware load error\n");
3046 return be_cmd_status(status);
3049 dev_info(dev, "Firmware flashed successfully\n");
3051 if (change_status == LANCER_FW_RESET_NEEDED) {
3052 dev_info(dev, "Resetting adapter to activate new FW\n");
3053 status = lancer_physdev_ctrl(adapter,
3054 PHYSDEV_CONTROL_FW_RESET_MASK);
3056 dev_err(dev, "Adapter busy, could not reset FW\n");
3057 dev_err(dev, "Reboot server to activate new FW\n");
3059 } else if (change_status != LANCER_NO_RESET_NEEDED) {
3060 dev_info(dev, "Reboot server to activate new FW\n");
3066 /* Check if the flash image file is compatible with the adapter that
3069 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3070 struct flash_file_hdr_g3 *fhdr)
3073 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3077 /* First letter of the build version is used to identify
3078 * which chip this image file is meant for.
3080 switch (fhdr->build[0]) {
3081 case BLD_STR_UFI_TYPE_SH:
3082 if (!skyhawk_chip(adapter))
3085 case BLD_STR_UFI_TYPE_BE3:
3086 if (!BE3_chip(adapter))
3089 case BLD_STR_UFI_TYPE_BE2:
3090 if (!BE2_chip(adapter))
3097 /* In BE3 FW images the "asic_type_rev" field doesn't track the
3098 * asic_rev of the chips it is compatible with.
3099 * When asic_type_rev is 0 the image is compatible only with
3100 * pre-BE3-R chips (asic_rev < 0x10)
3102 if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3103 return adapter->asic_rev < 0x10;
3105 return (fhdr->asic_type_rev >= adapter->asic_rev);
3108 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3110 struct device *dev = &adapter->pdev->dev;
3111 struct flash_file_hdr_g3 *fhdr3;
3112 struct image_hdr *img_hdr_ptr;
3113 int status = 0, i, num_imgs;
3114 struct be_dma_mem flash_cmd;
3116 fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3117 if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3118 dev_err(dev, "Flash image is not compatible with adapter\n");
3122 flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3123 flash_cmd.va = dma_zalloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3128 num_imgs = le32_to_cpu(fhdr3->num_imgs);
3129 for (i = 0; i < num_imgs; i++) {
3130 img_hdr_ptr = (struct image_hdr *)(fw->data +
3131 (sizeof(struct flash_file_hdr_g3) +
3132 i * sizeof(struct image_hdr)));
3133 if (!BE2_chip(adapter) &&
3134 le32_to_cpu(img_hdr_ptr->imageid) != 1)
3137 if (skyhawk_chip(adapter))
3138 status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3141 status = be_flash_BEx(adapter, fw, &flash_cmd,
3145 dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3147 dev_info(dev, "Firmware flashed successfully\n");
3152 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3153 struct be_dma_mem *nonemb_cmd)
3155 struct be_mcc_wrb *wrb;
3156 struct be_cmd_req_acpi_wol_magic_config *req;
3159 spin_lock_bh(&adapter->mcc_lock);
3161 wrb = wrb_from_mccq(adapter);
3166 req = nonemb_cmd->va;
3168 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3169 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3171 memcpy(req->magic_mac, mac, ETH_ALEN);
3173 status = be_mcc_notify_wait(adapter);
3176 spin_unlock_bh(&adapter->mcc_lock);
3180 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3181 u8 loopback_type, u8 enable)
3183 struct be_mcc_wrb *wrb;
3184 struct be_cmd_req_set_lmode *req;
3187 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3188 CMD_SUBSYSTEM_LOWLEVEL))
3191 spin_lock_bh(&adapter->mcc_lock);
3193 wrb = wrb_from_mccq(adapter);
3199 req = embedded_payload(wrb);
3201 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3202 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3205 req->src_port = port_num;
3206 req->dest_port = port_num;
3207 req->loopback_type = loopback_type;
3208 req->loopback_state = enable;
3210 status = be_mcc_notify(adapter);
3214 spin_unlock_bh(&adapter->mcc_lock);
3216 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3217 msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3218 status = -ETIMEDOUT;
3223 spin_unlock_bh(&adapter->mcc_lock);
3227 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3228 u32 loopback_type, u32 pkt_size, u32 num_pkts,
3231 struct be_mcc_wrb *wrb;
3232 struct be_cmd_req_loopback_test *req;
3233 struct be_cmd_resp_loopback_test *resp;
3236 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3237 CMD_SUBSYSTEM_LOWLEVEL))
3240 spin_lock_bh(&adapter->mcc_lock);
3242 wrb = wrb_from_mccq(adapter);
3248 req = embedded_payload(wrb);
3250 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3251 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3254 req->hdr.timeout = cpu_to_le32(15);
3255 req->pattern = cpu_to_le64(pattern);
3256 req->src_port = cpu_to_le32(port_num);
3257 req->dest_port = cpu_to_le32(port_num);
3258 req->pkt_size = cpu_to_le32(pkt_size);
3259 req->num_pkts = cpu_to_le32(num_pkts);
3260 req->loopback_type = cpu_to_le32(loopback_type);
3262 status = be_mcc_notify(adapter);
3266 spin_unlock_bh(&adapter->mcc_lock);
3268 wait_for_completion(&adapter->et_cmd_compl);
3269 resp = embedded_payload(wrb);
3270 status = le32_to_cpu(resp->status);
3274 spin_unlock_bh(&adapter->mcc_lock);
3278 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3279 u32 byte_cnt, struct be_dma_mem *cmd)
3281 struct be_mcc_wrb *wrb;
3282 struct be_cmd_req_ddrdma_test *req;
3286 if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3287 CMD_SUBSYSTEM_LOWLEVEL))
3290 spin_lock_bh(&adapter->mcc_lock);
3292 wrb = wrb_from_mccq(adapter);
3298 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3299 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3302 req->pattern = cpu_to_le64(pattern);
3303 req->byte_count = cpu_to_le32(byte_cnt);
3304 for (i = 0; i < byte_cnt; i++) {
3305 req->snd_buff[i] = (u8)(pattern >> (j*8));
3311 status = be_mcc_notify_wait(adapter);
3314 struct be_cmd_resp_ddrdma_test *resp;
3317 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3324 spin_unlock_bh(&adapter->mcc_lock);
3328 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3329 struct be_dma_mem *nonemb_cmd)
3331 struct be_mcc_wrb *wrb;
3332 struct be_cmd_req_seeprom_read *req;
3335 spin_lock_bh(&adapter->mcc_lock);
3337 wrb = wrb_from_mccq(adapter);
3342 req = nonemb_cmd->va;
3344 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3345 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3348 status = be_mcc_notify_wait(adapter);
3351 spin_unlock_bh(&adapter->mcc_lock);
3355 int be_cmd_get_phy_info(struct be_adapter *adapter)
3357 struct be_mcc_wrb *wrb;
3358 struct be_cmd_req_get_phy_info *req;
3359 struct be_dma_mem cmd;
3362 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3363 CMD_SUBSYSTEM_COMMON))
3366 spin_lock_bh(&adapter->mcc_lock);
3368 wrb = wrb_from_mccq(adapter);
3373 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3374 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3377 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3384 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3385 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3388 status = be_mcc_notify_wait(adapter);
3390 struct be_phy_info *resp_phy_info =
3391 cmd.va + sizeof(struct be_cmd_req_hdr);
3393 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3394 adapter->phy.interface_type =
3395 le16_to_cpu(resp_phy_info->interface_type);
3396 adapter->phy.auto_speeds_supported =
3397 le16_to_cpu(resp_phy_info->auto_speeds_supported);
3398 adapter->phy.fixed_speeds_supported =
3399 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3400 adapter->phy.misc_params =
3401 le32_to_cpu(resp_phy_info->misc_params);
3403 if (BE2_chip(adapter)) {
3404 adapter->phy.fixed_speeds_supported =
3405 BE_SUPPORTED_SPEED_10GBPS |
3406 BE_SUPPORTED_SPEED_1GBPS;
3409 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3411 spin_unlock_bh(&adapter->mcc_lock);
3415 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3417 struct be_mcc_wrb *wrb;
3418 struct be_cmd_req_set_qos *req;
3421 spin_lock_bh(&adapter->mcc_lock);
3423 wrb = wrb_from_mccq(adapter);
3429 req = embedded_payload(wrb);
3431 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3432 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3434 req->hdr.domain = domain;
3435 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3436 req->max_bps_nic = cpu_to_le32(bps);
3438 status = be_mcc_notify_wait(adapter);
3441 spin_unlock_bh(&adapter->mcc_lock);
3445 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3447 struct be_mcc_wrb *wrb;
3448 struct be_cmd_req_cntl_attribs *req;
3449 struct be_cmd_resp_cntl_attribs *resp;
3451 int payload_len = max(sizeof(*req), sizeof(*resp));
3452 struct mgmt_controller_attrib *attribs;
3453 struct be_dma_mem attribs_cmd;
3456 if (mutex_lock_interruptible(&adapter->mbox_lock))
3459 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3460 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3461 attribs_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3463 &attribs_cmd.dma, GFP_ATOMIC);
3464 if (!attribs_cmd.va) {
3465 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3470 wrb = wrb_from_mbox(adapter);
3475 req = attribs_cmd.va;
3477 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3478 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3481 status = be_mbox_notify_wait(adapter);
3483 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3484 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3485 serial_num = attribs->hba_attribs.controller_serial_number;
3486 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3487 adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3492 mutex_unlock(&adapter->mbox_lock);
3494 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3495 attribs_cmd.va, attribs_cmd.dma);
3500 int be_cmd_req_native_mode(struct be_adapter *adapter)
3502 struct be_mcc_wrb *wrb;
3503 struct be_cmd_req_set_func_cap *req;
3506 if (mutex_lock_interruptible(&adapter->mbox_lock))
3509 wrb = wrb_from_mbox(adapter);
3515 req = embedded_payload(wrb);
3517 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3518 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3519 sizeof(*req), wrb, NULL);
3521 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3522 CAPABILITY_BE3_NATIVE_ERX_API);
3523 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3525 status = be_mbox_notify_wait(adapter);
3527 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3529 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3530 CAPABILITY_BE3_NATIVE_ERX_API;
3531 if (!adapter->be3_native)
3532 dev_warn(&adapter->pdev->dev,
3533 "adapter not in advanced mode\n");
3536 mutex_unlock(&adapter->mbox_lock);
3540 /* Get privilege(s) for a function */
3541 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3544 struct be_mcc_wrb *wrb;
3545 struct be_cmd_req_get_fn_privileges *req;
3548 spin_lock_bh(&adapter->mcc_lock);
3550 wrb = wrb_from_mccq(adapter);
3556 req = embedded_payload(wrb);
3558 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3559 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3562 req->hdr.domain = domain;
3564 status = be_mcc_notify_wait(adapter);
3566 struct be_cmd_resp_get_fn_privileges *resp =
3567 embedded_payload(wrb);
3569 *privilege = le32_to_cpu(resp->privilege_mask);
3571 /* In UMC mode FW does not return right privileges.
3572 * Override with correct privilege equivalent to PF.
3574 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3576 *privilege = MAX_PRIVILEGES;
3580 spin_unlock_bh(&adapter->mcc_lock);
3584 /* Set privilege(s) for a function */
3585 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3588 struct be_mcc_wrb *wrb;
3589 struct be_cmd_req_set_fn_privileges *req;
3592 spin_lock_bh(&adapter->mcc_lock);
3594 wrb = wrb_from_mccq(adapter);
3600 req = embedded_payload(wrb);
3601 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3602 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3604 req->hdr.domain = domain;
3605 if (lancer_chip(adapter))
3606 req->privileges_lancer = cpu_to_le32(privileges);
3608 req->privileges = cpu_to_le32(privileges);
3610 status = be_mcc_notify_wait(adapter);
3612 spin_unlock_bh(&adapter->mcc_lock);
3616 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3617 * pmac_id_valid: false => pmac_id or MAC address is requested.
3618 * If pmac_id is returned, pmac_id_valid is returned as true
3620 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3621 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3624 struct be_mcc_wrb *wrb;
3625 struct be_cmd_req_get_mac_list *req;
3628 struct be_dma_mem get_mac_list_cmd;
3631 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3632 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3633 get_mac_list_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
3634 get_mac_list_cmd.size,
3635 &get_mac_list_cmd.dma,
3638 if (!get_mac_list_cmd.va) {
3639 dev_err(&adapter->pdev->dev,
3640 "Memory allocation failure during GET_MAC_LIST\n");
3644 spin_lock_bh(&adapter->mcc_lock);
3646 wrb = wrb_from_mccq(adapter);
3652 req = get_mac_list_cmd.va;
3654 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3655 OPCODE_COMMON_GET_MAC_LIST,
3656 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3657 req->hdr.domain = domain;
3658 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3659 if (*pmac_id_valid) {
3660 req->mac_id = cpu_to_le32(*pmac_id);
3661 req->iface_id = cpu_to_le16(if_handle);
3662 req->perm_override = 0;
3664 req->perm_override = 1;
3667 status = be_mcc_notify_wait(adapter);
3669 struct be_cmd_resp_get_mac_list *resp =
3670 get_mac_list_cmd.va;
3672 if (*pmac_id_valid) {
3673 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3678 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3679 /* Mac list returned could contain one or more active mac_ids
3680 * or one or more true or pseudo permanent mac addresses.
3681 * If an active mac_id is present, return first active mac_id
3684 for (i = 0; i < mac_count; i++) {
3685 struct get_list_macaddr *mac_entry;
3689 mac_entry = &resp->macaddr_list[i];
3690 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3691 /* mac_id is a 32 bit value and mac_addr size
3694 if (mac_addr_size == sizeof(u32)) {
3695 *pmac_id_valid = true;
3696 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3697 *pmac_id = le32_to_cpu(mac_id);
3701 /* If no active mac_id found, return first mac addr */
3702 *pmac_id_valid = false;
3703 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3708 spin_unlock_bh(&adapter->mcc_lock);
3709 dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3710 get_mac_list_cmd.va, get_mac_list_cmd.dma);
3714 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3715 u8 *mac, u32 if_handle, bool active, u32 domain)
3718 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3720 if (BEx_chip(adapter))
3721 return be_cmd_mac_addr_query(adapter, mac, false,
3722 if_handle, curr_pmac_id);
3724 /* Fetch the MAC address using pmac_id */
3725 return be_cmd_get_mac_from_list(adapter, mac, &active,
3730 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3733 bool pmac_valid = false;
3737 if (BEx_chip(adapter)) {
3738 if (be_physfn(adapter))
3739 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3742 status = be_cmd_mac_addr_query(adapter, mac, false,
3743 adapter->if_handle, 0);
3745 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3746 NULL, adapter->if_handle, 0);
3752 /* Uses synchronous MCCQ */
3753 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3754 u8 mac_count, u32 domain)
3756 struct be_mcc_wrb *wrb;
3757 struct be_cmd_req_set_mac_list *req;
3759 struct be_dma_mem cmd;
3761 memset(&cmd, 0, sizeof(struct be_dma_mem));
3762 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3763 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3768 spin_lock_bh(&adapter->mcc_lock);
3770 wrb = wrb_from_mccq(adapter);
3777 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3778 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3781 req->hdr.domain = domain;
3782 req->mac_count = mac_count;
3784 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3786 status = be_mcc_notify_wait(adapter);
3789 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3790 spin_unlock_bh(&adapter->mcc_lock);
3794 /* Wrapper to delete any active MACs and provision the new mac.
3795 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3796 * current list are active.
3798 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3800 bool active_mac = false;
3801 u8 old_mac[ETH_ALEN];
3805 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3806 &pmac_id, if_id, dom);
3808 if (!status && active_mac)
3809 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3811 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3814 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3815 u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3817 struct be_mcc_wrb *wrb;
3818 struct be_cmd_req_set_hsw_config *req;
3822 spin_lock_bh(&adapter->mcc_lock);
3824 wrb = wrb_from_mccq(adapter);
3830 req = embedded_payload(wrb);
3831 ctxt = &req->context;
3833 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3834 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3837 req->hdr.domain = domain;
3838 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3840 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3841 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3843 if (!BEx_chip(adapter) && hsw_mode) {
3844 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3845 ctxt, adapter->hba_port_num);
3846 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3847 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3851 /* Enable/disable both mac and vlan spoof checking */
3852 if (!BEx_chip(adapter) && spoofchk) {
3853 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3855 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3859 be_dws_cpu_to_le(req->context, sizeof(req->context));
3860 status = be_mcc_notify_wait(adapter);
3863 spin_unlock_bh(&adapter->mcc_lock);
3867 /* Get Hyper switch config */
3868 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3869 u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3871 struct be_mcc_wrb *wrb;
3872 struct be_cmd_req_get_hsw_config *req;
3877 spin_lock_bh(&adapter->mcc_lock);
3879 wrb = wrb_from_mccq(adapter);
3885 req = embedded_payload(wrb);
3886 ctxt = &req->context;
3888 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3889 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3892 req->hdr.domain = domain;
3893 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3895 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3897 if (!BEx_chip(adapter) && mode) {
3898 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3899 ctxt, adapter->hba_port_num);
3900 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3902 be_dws_cpu_to_le(req->context, sizeof(req->context));
3904 status = be_mcc_notify_wait(adapter);
3906 struct be_cmd_resp_get_hsw_config *resp =
3907 embedded_payload(wrb);
3909 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3910 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3911 pvid, &resp->context);
3913 *pvid = le16_to_cpu(vid);
3915 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3916 port_fwd_type, &resp->context);
3919 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3920 spoofchk, &resp->context);
3924 spin_unlock_bh(&adapter->mcc_lock);
3928 static bool be_is_wol_excluded(struct be_adapter *adapter)
3930 struct pci_dev *pdev = adapter->pdev;
3932 if (be_virtfn(adapter))
3935 switch (pdev->subsystem_device) {
3936 case OC_SUBSYS_DEVICE_ID1:
3937 case OC_SUBSYS_DEVICE_ID2:
3938 case OC_SUBSYS_DEVICE_ID3:
3939 case OC_SUBSYS_DEVICE_ID4:
3946 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3948 struct be_mcc_wrb *wrb;
3949 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3951 struct be_dma_mem cmd;
3953 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3957 if (be_is_wol_excluded(adapter))
3960 if (mutex_lock_interruptible(&adapter->mbox_lock))
3963 memset(&cmd, 0, sizeof(struct be_dma_mem));
3964 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3965 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3968 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3973 wrb = wrb_from_mbox(adapter);
3981 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3982 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3983 sizeof(*req), wrb, &cmd);
3985 req->hdr.version = 1;
3986 req->query_options = BE_GET_WOL_CAP;
3988 status = be_mbox_notify_wait(adapter);
3990 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3992 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3994 adapter->wol_cap = resp->wol_settings;
3995 if (adapter->wol_cap & BE_WOL_CAP)
3996 adapter->wol_en = true;
3999 mutex_unlock(&adapter->mbox_lock);
4001 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4007 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4009 struct be_dma_mem extfat_cmd;
4010 struct be_fat_conf_params *cfgs;
4014 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4015 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4016 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4017 extfat_cmd.size, &extfat_cmd.dma,
4022 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4026 cfgs = (struct be_fat_conf_params *)
4027 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4028 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4029 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4031 for (j = 0; j < num_modes; j++) {
4032 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4033 cfgs->module[i].trace_lvl[j].dbg_lvl =
4038 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4040 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4045 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4047 struct be_dma_mem extfat_cmd;
4048 struct be_fat_conf_params *cfgs;
4052 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4053 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4054 extfat_cmd.va = dma_zalloc_coherent(&adapter->pdev->dev,
4055 extfat_cmd.size, &extfat_cmd.dma,
4058 if (!extfat_cmd.va) {
4059 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4064 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4066 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4067 sizeof(struct be_cmd_resp_hdr));
4069 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4070 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4071 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4074 dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4080 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4081 struct be_dma_mem *cmd)
4083 struct be_mcc_wrb *wrb;
4084 struct be_cmd_req_get_ext_fat_caps *req;
4087 if (mutex_lock_interruptible(&adapter->mbox_lock))
4090 wrb = wrb_from_mbox(adapter);
4097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4098 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
4099 cmd->size, wrb, cmd);
4100 req->parameter_type = cpu_to_le32(1);
4102 status = be_mbox_notify_wait(adapter);
4104 mutex_unlock(&adapter->mbox_lock);
4108 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4109 struct be_dma_mem *cmd,
4110 struct be_fat_conf_params *configs)
4112 struct be_mcc_wrb *wrb;
4113 struct be_cmd_req_set_ext_fat_caps *req;
4116 spin_lock_bh(&adapter->mcc_lock);
4118 wrb = wrb_from_mccq(adapter);
4125 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4126 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4127 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
4128 cmd->size, wrb, cmd);
4130 status = be_mcc_notify_wait(adapter);
4132 spin_unlock_bh(&adapter->mcc_lock);
4136 int be_cmd_query_port_name(struct be_adapter *adapter)
4138 struct be_cmd_req_get_port_name *req;
4139 struct be_mcc_wrb *wrb;
4142 if (mutex_lock_interruptible(&adapter->mbox_lock))
4145 wrb = wrb_from_mbox(adapter);
4146 req = embedded_payload(wrb);
4148 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4149 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4151 if (!BEx_chip(adapter))
4152 req->hdr.version = 1;
4154 status = be_mbox_notify_wait(adapter);
4156 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4158 adapter->port_name = resp->port_name[adapter->hba_port_num];
4160 adapter->port_name = adapter->hba_port_num + '0';
4163 mutex_unlock(&adapter->mbox_lock);
4167 /* When more than 1 NIC descriptor is present in the descriptor list,
4168 * the caller must specify the pf_num to obtain the NIC descriptor
4169 * corresponding to its pci function.
4170 * get_vft must be true when the caller wants the VF-template desc of the
4172 * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4173 * that only it's NIC descriptor is present in the descriptor list.
4175 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4176 bool get_vft, u8 pf_num)
4178 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4179 struct be_nic_res_desc *nic;
4182 for (i = 0; i < desc_count; i++) {
4183 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4184 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4185 nic = (struct be_nic_res_desc *)hdr;
4187 if ((pf_num == PF_NUM_IGNORE ||
4188 nic->pf_num == pf_num) &&
4189 (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4192 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4193 hdr = (void *)hdr + hdr->desc_len;
4198 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4201 return be_get_nic_desc(buf, desc_count, true, pf_num);
4204 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4207 return be_get_nic_desc(buf, desc_count, false, pf_num);
4210 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4213 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4214 struct be_pcie_res_desc *pcie;
4217 for (i = 0; i < desc_count; i++) {
4218 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4219 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4220 pcie = (struct be_pcie_res_desc *)hdr;
4221 if (pcie->pf_num == pf_num)
4225 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4226 hdr = (void *)hdr + hdr->desc_len;
4231 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4233 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4236 for (i = 0; i < desc_count; i++) {
4237 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4238 return (struct be_port_res_desc *)hdr;
4240 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4241 hdr = (void *)hdr + hdr->desc_len;
4246 static void be_copy_nic_desc(struct be_resources *res,
4247 struct be_nic_res_desc *desc)
4249 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4250 res->max_vlans = le16_to_cpu(desc->vlan_count);
4251 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4252 res->max_tx_qs = le16_to_cpu(desc->txq_count);
4253 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4254 res->max_rx_qs = le16_to_cpu(desc->rq_count);
4255 res->max_evt_qs = le16_to_cpu(desc->eq_count);
4256 res->max_cq_count = le16_to_cpu(desc->cq_count);
4257 res->max_iface_count = le16_to_cpu(desc->iface_count);
4258 res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4259 /* Clear flags that driver is not interested in */
4260 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4261 BE_IF_CAP_FLAGS_WANT;
4265 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4267 struct be_mcc_wrb *wrb;
4268 struct be_cmd_req_get_func_config *req;
4270 struct be_dma_mem cmd;
4272 if (mutex_lock_interruptible(&adapter->mbox_lock))
4275 memset(&cmd, 0, sizeof(struct be_dma_mem));
4276 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4277 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4280 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4285 wrb = wrb_from_mbox(adapter);
4293 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4294 OPCODE_COMMON_GET_FUNC_CONFIG,
4295 cmd.size, wrb, &cmd);
4297 if (skyhawk_chip(adapter))
4298 req->hdr.version = 1;
4300 status = be_mbox_notify_wait(adapter);
4302 struct be_cmd_resp_get_func_config *resp = cmd.va;
4303 u32 desc_count = le32_to_cpu(resp->desc_count);
4304 struct be_nic_res_desc *desc;
4306 /* GET_FUNC_CONFIG returns resource descriptors of the
4307 * current function only. So, pf_num should be set to
4310 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4317 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4318 adapter->pf_num = desc->pf_num;
4319 adapter->vf_num = desc->vf_num;
4322 be_copy_nic_desc(res, desc);
4325 mutex_unlock(&adapter->mbox_lock);
4327 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4332 /* Will use MBOX only if MCCQ has not been created */
4333 int be_cmd_get_profile_config(struct be_adapter *adapter,
4334 struct be_resources *res, u8 query, u8 domain)
4336 struct be_cmd_resp_get_profile_config *resp;
4337 struct be_cmd_req_get_profile_config *req;
4338 struct be_nic_res_desc *vf_res;
4339 struct be_pcie_res_desc *pcie;
4340 struct be_port_res_desc *port;
4341 struct be_nic_res_desc *nic;
4342 struct be_mcc_wrb wrb = {0};
4343 struct be_dma_mem cmd;
4347 memset(&cmd, 0, sizeof(struct be_dma_mem));
4348 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4349 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4355 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4356 OPCODE_COMMON_GET_PROFILE_CONFIG,
4357 cmd.size, &wrb, &cmd);
4359 if (!lancer_chip(adapter))
4360 req->hdr.version = 1;
4361 req->type = ACTIVE_PROFILE_TYPE;
4362 req->hdr.domain = domain;
4364 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4365 * descriptors with all bits set to "1" for the fields which can be
4366 * modified using SET_PROFILE_CONFIG cmd.
4368 if (query == RESOURCE_MODIFIABLE)
4369 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4371 status = be_cmd_notify_wait(adapter, &wrb);
4376 desc_count = le16_to_cpu(resp->desc_count);
4378 pcie = be_get_pcie_desc(resp->func_param, desc_count,
4381 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4383 port = be_get_port_desc(resp->func_param, desc_count);
4385 adapter->mc_type = port->mc_type;
4387 nic = be_get_func_nic_desc(resp->func_param, desc_count,
4390 be_copy_nic_desc(res, nic);
4392 vf_res = be_get_vft_desc(resp->func_param, desc_count,
4395 res->vf_if_cap_flags = vf_res->cap_flags;
4398 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4403 /* Will use MBOX only if MCCQ has not been created */
4404 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4405 int size, int count, u8 version, u8 domain)
4407 struct be_cmd_req_set_profile_config *req;
4408 struct be_mcc_wrb wrb = {0};
4409 struct be_dma_mem cmd;
4412 memset(&cmd, 0, sizeof(struct be_dma_mem));
4413 cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4414 cmd.va = dma_zalloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4420 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4421 OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4423 req->hdr.version = version;
4424 req->hdr.domain = domain;
4425 req->desc_count = cpu_to_le32(count);
4426 memcpy(req->desc, desc, size);
4428 status = be_cmd_notify_wait(adapter, &wrb);
4431 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4436 /* Mark all fields invalid */
4437 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4439 memset(nic, 0, sizeof(*nic));
4440 nic->unicast_mac_count = 0xFFFF;
4441 nic->mcc_count = 0xFFFF;
4442 nic->vlan_count = 0xFFFF;
4443 nic->mcast_mac_count = 0xFFFF;
4444 nic->txq_count = 0xFFFF;
4445 nic->rq_count = 0xFFFF;
4446 nic->rssq_count = 0xFFFF;
4447 nic->lro_count = 0xFFFF;
4448 nic->cq_count = 0xFFFF;
4449 nic->toe_conn_count = 0xFFFF;
4450 nic->eq_count = 0xFFFF;
4451 nic->iface_count = 0xFFFF;
4452 nic->link_param = 0xFF;
4453 nic->channel_id_param = cpu_to_le16(0xF000);
4454 nic->acpi_params = 0xFF;
4455 nic->wol_param = 0x0F;
4456 nic->tunnel_iface_count = 0xFFFF;
4457 nic->direct_tenant_iface_count = 0xFFFF;
4458 nic->bw_min = 0xFFFFFFFF;
4459 nic->bw_max = 0xFFFFFFFF;
4462 /* Mark all fields invalid */
4463 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4465 memset(pcie, 0, sizeof(*pcie));
4466 pcie->sriov_state = 0xFF;
4467 pcie->pf_state = 0xFF;
4468 pcie->pf_type = 0xFF;
4469 pcie->num_vfs = 0xFFFF;
4472 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4475 struct be_nic_res_desc nic_desc;
4479 if (BE3_chip(adapter))
4480 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4482 be_reset_nic_desc(&nic_desc);
4483 nic_desc.pf_num = adapter->pf_num;
4484 nic_desc.vf_num = domain;
4485 nic_desc.bw_min = 0;
4486 if (lancer_chip(adapter)) {
4487 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4488 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4489 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4491 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4494 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4495 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4496 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4497 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4498 nic_desc.bw_max = cpu_to_le32(bw_percent);
4501 return be_cmd_set_profile_config(adapter, &nic_desc,
4502 nic_desc.hdr.desc_len,
4503 1, version, domain);
4506 static void be_fill_vf_res_template(struct be_adapter *adapter,
4507 struct be_resources pool_res,
4508 u16 num_vfs, u16 num_vf_qs,
4509 struct be_nic_res_desc *nic_vft)
4511 u32 vf_if_cap_flags = pool_res.vf_if_cap_flags;
4512 struct be_resources res_mod = {0};
4514 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
4515 * which are modifiable using SET_PROFILE_CONFIG cmd.
4517 be_cmd_get_profile_config(adapter, &res_mod, RESOURCE_MODIFIABLE, 0);
4519 /* If RSS IFACE capability flags are modifiable for a VF, set the
4520 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
4521 * more than 1 RSSQ is available for a VF.
4522 * Otherwise, provision only 1 queue pair for VF.
4524 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
4525 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4526 if (num_vf_qs > 1) {
4527 vf_if_cap_flags |= BE_IF_FLAGS_RSS;
4528 if (pool_res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS)
4529 vf_if_cap_flags |= BE_IF_FLAGS_DEFQ_RSS;
4531 vf_if_cap_flags &= ~(BE_IF_FLAGS_RSS |
4532 BE_IF_FLAGS_DEFQ_RSS);
4538 if (res_mod.vf_if_cap_flags & BE_IF_FLAGS_VLAN_PROMISCUOUS) {
4539 nic_vft->flags |= BIT(IF_CAPS_FLAGS_VALID_SHIFT);
4540 vf_if_cap_flags &= ~BE_IF_FLAGS_VLAN_PROMISCUOUS;
4543 nic_vft->cap_flags = cpu_to_le32(vf_if_cap_flags);
4544 nic_vft->rq_count = cpu_to_le16(num_vf_qs);
4545 nic_vft->txq_count = cpu_to_le16(num_vf_qs);
4546 nic_vft->rssq_count = cpu_to_le16(num_vf_qs);
4547 nic_vft->cq_count = cpu_to_le16(pool_res.max_cq_count /
4550 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
4551 * among the PF and it's VFs, if the fields are changeable
4553 if (res_mod.max_uc_mac == FIELD_MODIFIABLE)
4554 nic_vft->unicast_mac_count = cpu_to_le16(pool_res.max_uc_mac /
4557 if (res_mod.max_vlans == FIELD_MODIFIABLE)
4558 nic_vft->vlan_count = cpu_to_le16(pool_res.max_vlans /
4561 if (res_mod.max_iface_count == FIELD_MODIFIABLE)
4562 nic_vft->iface_count = cpu_to_le16(pool_res.max_iface_count /
4565 if (res_mod.max_mcc_count == FIELD_MODIFIABLE)
4566 nic_vft->mcc_count = cpu_to_le16(pool_res.max_mcc_count /
4570 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4571 struct be_resources pool_res, u16 num_vfs,
4575 struct be_pcie_res_desc pcie;
4576 struct be_nic_res_desc nic_vft;
4579 /* PF PCIE descriptor */
4580 be_reset_pcie_desc(&desc.pcie);
4581 desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4582 desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4583 desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4584 desc.pcie.pf_num = adapter->pdev->devfn;
4585 desc.pcie.sriov_state = num_vfs ? 1 : 0;
4586 desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4588 /* VF NIC Template descriptor */
4589 be_reset_nic_desc(&desc.nic_vft);
4590 desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4591 desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4592 desc.nic_vft.flags = BIT(VFT_SHIFT) | BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4593 desc.nic_vft.pf_num = adapter->pdev->devfn;
4594 desc.nic_vft.vf_num = 0;
4596 be_fill_vf_res_template(adapter, pool_res, num_vfs, num_vf_qs,
4599 return be_cmd_set_profile_config(adapter, &desc,
4600 2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4603 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4605 struct be_mcc_wrb *wrb;
4606 struct be_cmd_req_manage_iface_filters *req;
4609 if (iface == 0xFFFFFFFF)
4612 spin_lock_bh(&adapter->mcc_lock);
4614 wrb = wrb_from_mccq(adapter);
4619 req = embedded_payload(wrb);
4621 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4622 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4625 req->target_iface_id = cpu_to_le32(iface);
4627 status = be_mcc_notify_wait(adapter);
4629 spin_unlock_bh(&adapter->mcc_lock);
4633 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4635 struct be_port_res_desc port_desc;
4637 memset(&port_desc, 0, sizeof(port_desc));
4638 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4639 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4640 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4641 port_desc.link_num = adapter->hba_port_num;
4643 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4645 port_desc.nv_port = swab16(port);
4647 port_desc.nv_flags = NV_TYPE_DISABLED;
4648 port_desc.nv_port = 0;
4651 return be_cmd_set_profile_config(adapter, &port_desc,
4652 RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4655 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4658 struct be_mcc_wrb *wrb;
4659 struct be_cmd_req_get_iface_list *req;
4660 struct be_cmd_resp_get_iface_list *resp;
4663 spin_lock_bh(&adapter->mcc_lock);
4665 wrb = wrb_from_mccq(adapter);
4670 req = embedded_payload(wrb);
4672 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4673 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4675 req->hdr.domain = vf_num + 1;
4677 status = be_mcc_notify_wait(adapter);
4679 resp = (struct be_cmd_resp_get_iface_list *)req;
4680 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4684 spin_unlock_bh(&adapter->mcc_lock);
4688 static int lancer_wait_idle(struct be_adapter *adapter)
4690 #define SLIPORT_IDLE_TIMEOUT 30
4694 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4695 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4696 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4702 if (i == SLIPORT_IDLE_TIMEOUT)
4708 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4712 status = lancer_wait_idle(adapter);
4716 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4721 /* Routine to check whether dump image is present or not */
4722 bool dump_present(struct be_adapter *adapter)
4724 u32 sliport_status = 0;
4726 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4727 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4730 int lancer_initiate_dump(struct be_adapter *adapter)
4732 struct device *dev = &adapter->pdev->dev;
4735 if (dump_present(adapter)) {
4736 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4740 /* give firmware reset and diagnostic dump */
4741 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4742 PHYSDEV_CONTROL_DD_MASK);
4744 dev_err(dev, "FW reset failed\n");
4748 status = lancer_wait_idle(adapter);
4752 if (!dump_present(adapter)) {
4753 dev_err(dev, "FW dump not generated\n");
4760 int lancer_delete_dump(struct be_adapter *adapter)
4764 status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4765 return be_cmd_status(status);
4769 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4771 struct be_mcc_wrb *wrb;
4772 struct be_cmd_enable_disable_vf *req;
4775 if (BEx_chip(adapter))
4778 spin_lock_bh(&adapter->mcc_lock);
4780 wrb = wrb_from_mccq(adapter);
4786 req = embedded_payload(wrb);
4788 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4789 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4792 req->hdr.domain = domain;
4794 status = be_mcc_notify_wait(adapter);
4796 spin_unlock_bh(&adapter->mcc_lock);
4800 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4802 struct be_mcc_wrb *wrb;
4803 struct be_cmd_req_intr_set *req;
4806 if (mutex_lock_interruptible(&adapter->mbox_lock))
4809 wrb = wrb_from_mbox(adapter);
4811 req = embedded_payload(wrb);
4813 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4814 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4817 req->intr_enabled = intr_enable;
4819 status = be_mbox_notify_wait(adapter);
4821 mutex_unlock(&adapter->mbox_lock);
4826 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4828 struct be_cmd_req_get_active_profile *req;
4829 struct be_mcc_wrb *wrb;
4832 if (mutex_lock_interruptible(&adapter->mbox_lock))
4835 wrb = wrb_from_mbox(adapter);
4841 req = embedded_payload(wrb);
4843 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4844 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4847 status = be_mbox_notify_wait(adapter);
4849 struct be_cmd_resp_get_active_profile *resp =
4850 embedded_payload(wrb);
4852 *profile_id = le16_to_cpu(resp->active_profile_id);
4856 mutex_unlock(&adapter->mbox_lock);
4860 int __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4861 int link_state, int version, u8 domain)
4863 struct be_mcc_wrb *wrb;
4864 struct be_cmd_req_set_ll_link *req;
4867 spin_lock_bh(&adapter->mcc_lock);
4869 wrb = wrb_from_mccq(adapter);
4875 req = embedded_payload(wrb);
4877 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4878 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4879 sizeof(*req), wrb, NULL);
4881 req->hdr.version = version;
4882 req->hdr.domain = domain;
4884 if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4885 link_state == IFLA_VF_LINK_STATE_AUTO)
4886 req->link_config |= PLINK_ENABLE;
4888 if (link_state == IFLA_VF_LINK_STATE_AUTO)
4889 req->link_config |= PLINK_TRACK;
4891 status = be_mcc_notify_wait(adapter);
4893 spin_unlock_bh(&adapter->mcc_lock);
4897 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4898 int link_state, u8 domain)
4902 if (BEx_chip(adapter))
4905 status = __be_cmd_set_logical_link_config(adapter, link_state,
4908 /* Version 2 of the command will not be recognized by older FW.
4909 * On such a failure issue version 1 of the command.
4911 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4912 status = __be_cmd_set_logical_link_config(adapter, link_state,
4916 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4917 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4919 struct be_adapter *adapter = netdev_priv(netdev_handle);
4920 struct be_mcc_wrb *wrb;
4921 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4922 struct be_cmd_req_hdr *req;
4923 struct be_cmd_resp_hdr *resp;
4926 spin_lock_bh(&adapter->mcc_lock);
4928 wrb = wrb_from_mccq(adapter);
4933 req = embedded_payload(wrb);
4934 resp = embedded_payload(wrb);
4936 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4937 hdr->opcode, wrb_payload_size, wrb, NULL);
4938 memcpy(req, wrb_payload, wrb_payload_size);
4939 be_dws_cpu_to_le(req, wrb_payload_size);
4941 status = be_mcc_notify_wait(adapter);
4943 *cmd_status = (status & 0xffff);
4946 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4947 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4949 spin_unlock_bh(&adapter->mcc_lock);
4952 EXPORT_SYMBOL(be_roce_mcc_cmd);