drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 64;
  23
  24 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  25 {
  26         return wrb->payload.embedded_payload;
  27 }
  28
  29 static void be_mcc_notify(struct be_adapter *adapter)
  30 {
  31         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  32         u32 val = 0;
  33
  34         if (be_error(adapter))
  35                 return;
  36
  37         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  38         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  39
  40         wmb();
  41         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  42 }
  43
  44 /* To check if valid bit is set, check the entire word as we don't know
  45  * the endianness of the data (old entry is host endian while a new entry is
  46  * little endian) */
  47 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  48 {
  49         if (compl->flags != 0) {
  50                 compl->flags = le32_to_cpu(compl->flags);
  51                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  52                 return true;
  53         } else {
  54                 return false;
  55         }
  56 }
  57
  58 /* Need to reset the entire word that houses the valid bit */
  59 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  60 {
  61         compl->flags = 0;
  62 }
  63
  64 static int be_mcc_compl_process(struct be_adapter *adapter,
  65         struct be_mcc_compl *compl)
  66 {
  67         u16 compl_status, extd_status;
  68
  69         /* Just swap the status to host endian; mcc tag is opaquely copied
  70          * from mcc_wrb */
  71         be_dws_le_to_cpu(compl, 4);
  72
  73         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  74                                 CQE_STATUS_COMPL_MASK;
  75
  76         if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  77                 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  78                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  79                 adapter->flash_status = compl_status;
  80                 complete(&adapter->flash_compl);
  81         }
  82
  83         if (compl_status == MCC_STATUS_SUCCESS) {
  84                 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  85                          (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  86                         (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  87                         be_parse_stats(adapter);
  88                         adapter->stats_cmd_sent = false;
  89                 }
  90                 if (compl->tag0 ==
  91                                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
  92                         struct be_mcc_wrb *mcc_wrb =
  93                                 queue_index_node(&adapter->mcc_obj.q,
  94                                                 compl->tag1);
  95                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
  96                                 embedded_payload(mcc_wrb);
  97                         adapter->drv_stats.be_on_die_temperature =
  98                                 resp->on_die_temperature;
  99                 }
 100         } else {
 101                 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 102                         be_get_temp_freq = 0;
 103
 104                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 105                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 106                         goto done;
 107
 108                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 109                         dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
 110                                 "permitted to execute this cmd (opcode %d)\n",
 111                                 compl->tag0);
 112                 } else {
 113                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 114                                         CQE_STATUS_EXTD_MASK;
 115                         dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
 116                                 "status %d, extd-status %d\n",
 117                                 compl->tag0, compl_status, extd_status);
 118                 }
 119         }
 120 done:
 121         return compl_status;
 122 }
 123
 124 /* Link state evt is a string of bytes; no need for endian swapping */
 125 static void be_async_link_state_process(struct be_adapter *adapter,
 126                 struct be_async_event_link_state *evt)
 127 {
 128         /* When link status changes, link speed must be re-queried from FW */
 129         adapter->link_speed = -1;
 130
 131         /* For the initial link status do not rely on the ASYNC event as
 132          * it may not be received in some cases.
 133          */
 134         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 135                 be_link_status_update(adapter, evt->port_link_status);
 136 }
 137
 138 /* Grp5 CoS Priority evt */
 139 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 140                 struct be_async_event_grp5_cos_priority *evt)
 141 {
 142         if (evt->valid) {
 143                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 144                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 145                 adapter->recommended_prio =
 146                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 147         }
 148 }
 149
 150 /* Grp5 QOS Speed evt */
 151 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 152                 struct be_async_event_grp5_qos_link_speed *evt)
 153 {
 154         if (evt->physical_port == adapter->port_num) {
 155                 /* qos_link_speed is in units of 10 Mbps */
 156                 adapter->link_speed = evt->qos_link_speed * 10;
 157         }
 158 }
 159
 160 /*Grp5 PVID evt*/
 161 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 162                 struct be_async_event_grp5_pvid_state *evt)
 163 {
 164         if (evt->enabled)
 165                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 166         else
 167                 adapter->pvid = 0;
 168 }
 169
 170 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 171                 u32 trailer, struct be_mcc_compl *evt)
 172 {
 173         u8 event_type = 0;
 174
 175         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 176                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 177
 178         switch (event_type) {
 179         case ASYNC_EVENT_COS_PRIORITY:
 180                 be_async_grp5_cos_priority_process(adapter,
 181                 (struct be_async_event_grp5_cos_priority *)evt);
 182         break;
 183         case ASYNC_EVENT_QOS_SPEED:
 184                 be_async_grp5_qos_speed_process(adapter,
 185                 (struct be_async_event_grp5_qos_link_speed *)evt);
 186         break;
 187         case ASYNC_EVENT_PVID_STATE:
 188                 be_async_grp5_pvid_state_process(adapter,
 189                 (struct be_async_event_grp5_pvid_state *)evt);
 190         break;
 191         default:
 192                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 193                 break;
 194         }
 195 }
 196
 197 static inline bool is_link_state_evt(u32 trailer)
 198 {
 199         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 200                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 201                                 ASYNC_EVENT_CODE_LINK_STATE;
 202 }
 203
 204 static inline bool is_grp5_evt(u32 trailer)
 205 {
 206         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 207                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 208                                 ASYNC_EVENT_CODE_GRP_5);
 209 }
 210
 211 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 212 {
 213         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 214         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 215
 216         if (be_mcc_compl_is_new(compl)) {
 217                 queue_tail_inc(mcc_cq);
 218                 return compl;
 219         }
 220         return NULL;
 221 }
 222
 223 void be_async_mcc_enable(struct be_adapter *adapter)
 224 {
 225         spin_lock_bh(&adapter->mcc_cq_lock);
 226
 227         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 228         adapter->mcc_obj.rearm_cq = true;
 229
 230         spin_unlock_bh(&adapter->mcc_cq_lock);
 231 }
 232
 233 void be_async_mcc_disable(struct be_adapter *adapter)
 234 {
 235         adapter->mcc_obj.rearm_cq = false;
 236 }
 237
 238 int be_process_mcc(struct be_adapter *adapter, int *status)
 239 {
 240         struct be_mcc_compl *compl;
 241         int num = 0;
 242         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 243
 244         spin_lock_bh(&adapter->mcc_cq_lock);
 245         while ((compl = be_mcc_compl_get(adapter))) {
 246                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 247                         /* Interpret flags as an async trailer */
 248                         if (is_link_state_evt(compl->flags))
 249                                 be_async_link_state_process(adapter,
 250                                 (struct be_async_event_link_state *) compl);
 251                         else if (is_grp5_evt(compl->flags))
 252                                 be_async_grp5_evt_process(adapter,
 253                                 compl->flags, compl);
 254                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 255                                 *status = be_mcc_compl_process(adapter, compl);
 256                                 atomic_dec(&mcc_obj->q.used);
 257                 }
 258                 be_mcc_compl_use(compl);
 259                 num++;
 260         }
 261
 262         spin_unlock_bh(&adapter->mcc_cq_lock);
 263         return num;
 264 }
 265
 266 /* Wait till no more pending mcc requests are present */
 267 static int be_mcc_wait_compl(struct be_adapter *adapter)
 268 {
 269 #define mcc_timeout             120000 /* 12s timeout */
 270         int i, num, status = 0;
 271         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 272
 273         for (i = 0; i < mcc_timeout; i++) {
 274                 if (be_error(adapter))
 275                         return -EIO;
 276
 277                 num = be_process_mcc(adapter, &status);
 278                 if (num)
 279                         be_cq_notify(adapter, mcc_obj->cq.id,
 280                                 mcc_obj->rearm_cq, num);
 281
 282                 if (atomic_read(&mcc_obj->q.used) == 0)
 283                         break;
 284                 udelay(100);
 285         }
 286         if (i == mcc_timeout) {
 287                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 288                 adapter->fw_timeout = true;
 289                 return -1;
 290         }
 291         return status;
 292 }
 293
 294 /* Notify MCC requests and wait for completion */
 295 static int be_mcc_notify_wait(struct be_adapter *adapter)
 296 {
 297         be_mcc_notify(adapter);
 298         return be_mcc_wait_compl(adapter);
 299 }
 300
 301 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 302 {
 303         int msecs = 0;
 304         u32 ready;
 305
 306         do {
 307                 if (be_error(adapter))
 308                         return -EIO;
 309
 310                 ready = ioread32(db);
 311                 if (ready == 0xffffffff)
 312                         return -1;
 313
 314                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 315                 if (ready)
 316                         break;
 317
 318                 if (msecs > 4000) {
 319                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 320                         adapter->fw_timeout = true;
 321                         be_detect_dump_ue(adapter);
 322                         return -1;
 323                 }
 324
 325                 msleep(1);
 326                 msecs++;
 327         } while (true);
 328
 329         return 0;
 330 }
 331
 332 /*
 333  * Insert the mailbox address into the doorbell in two steps
 334  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 335  */
 336 static int be_mbox_notify_wait(struct be_adapter *adapter)
 337 {
 338         int status;
 339         u32 val = 0;
 340         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 341         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 342         struct be_mcc_mailbox *mbox = mbox_mem->va;
 343         struct be_mcc_compl *compl = &mbox->compl;
 344
 345         /* wait for ready to be set */
 346         status = be_mbox_db_ready_wait(adapter, db);
 347         if (status != 0)
 348                 return status;
 349
 350         val |= MPU_MAILBOX_DB_HI_MASK;
 351         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 352         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 353         iowrite32(val, db);
 354
 355         /* wait for ready to be set */
 356         status = be_mbox_db_ready_wait(adapter, db);
 357         if (status != 0)
 358                 return status;
 359
 360         val = 0;
 361         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 362         val |= (u32)(mbox_mem->dma >> 4) << 2;
 363         iowrite32(val, db);
 364
 365         status = be_mbox_db_ready_wait(adapter, db);
 366         if (status != 0)
 367                 return status;
 368
 369         /* A cq entry has been made now */
 370         if (be_mcc_compl_is_new(compl)) {
 371                 status = be_mcc_compl_process(adapter, &mbox->compl);
 372                 be_mcc_compl_use(compl);
 373                 if (status)
 374                         return status;
 375         } else {
 376                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 377                 return -1;
 378         }
 379         return 0;
 380 }
 381
 382 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 383 {
 384         u32 sem;
 385
 386         if (lancer_chip(adapter))
 387                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 388         else
 389                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 390
 391         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 392         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 393                 return -1;
 394         else
 395                 return 0;
 396 }
 397
 398 int be_cmd_POST(struct be_adapter *adapter)
 399 {
 400         u16 stage;
 401         int status, timeout = 0;
 402         struct device *dev = &adapter->pdev->dev;
 403
 404         do {
 405                 status = be_POST_stage_get(adapter, &stage);
 406                 if (status) {
 407                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 408                         return -1;
 409                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 410                         if (msleep_interruptible(2000)) {
 411                                 dev_err(dev, "Waiting for POST aborted\n");
 412                                 return -EINTR;
 413                         }
 414                         timeout += 2;
 415                 } else {
 416                         return 0;
 417                 }
 418         } while (timeout < 60);
 419
 420         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 421         return -1;
 422 }
 423
 424
 425 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 426 {
 427         return &wrb->payload.sgl[0];
 428 }
 429
 430
 431 /* Don't touch the hdr after it's prepared */
 432 /* mem will be NULL for embedded commands */
 433 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 434                                 u8 subsystem, u8 opcode, int cmd_len,
 435                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 436 {
 437         struct be_sge *sge;
 438
 439         req_hdr->opcode = opcode;
 440         req_hdr->subsystem = subsystem;
 441         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 442         req_hdr->version = 0;
 443
 444         wrb->tag0 = opcode;
 445         wrb->tag1 = subsystem;
 446         wrb->payload_length = cmd_len;
 447         if (mem) {
 448                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 449                         MCC_WRB_SGE_CNT_SHIFT;
 450                 sge = nonembedded_sgl(wrb);
 451                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 452                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 453                 sge->len = cpu_to_le32(mem->size);
 454         } else
 455                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 456         be_dws_cpu_to_le(wrb, 8);
 457 }
 458
 459 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 460                         struct be_dma_mem *mem)
 461 {
 462         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 463         u64 dma = (u64)mem->dma;
 464
 465         for (i = 0; i < buf_pages; i++) {
 466                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 467                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 468                 dma += PAGE_SIZE_4K;
 469         }
 470 }
 471
 472 /* Converts interrupt delay in microseconds to multiplier value */
 473 static u32 eq_delay_to_mult(u32 usec_delay)
 474 {
 475 #define MAX_INTR_RATE                   651042
 476         const u32 round = 10;
 477         u32 multiplier;
 478
 479         if (usec_delay == 0)
 480                 multiplier = 0;
 481         else {
 482                 u32 interrupt_rate = 1000000 / usec_delay;
 483                 /* Max delay, corresponding to the lowest interrupt rate */
 484                 if (interrupt_rate == 0)
 485                         multiplier = 1023;
 486                 else {
 487                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 488                         multiplier /= interrupt_rate;
 489                         /* Round the multiplier to the closest value.*/
 490                         multiplier = (multiplier + round/2) / round;
 491                         multiplier = min(multiplier, (u32)1023);
 492                 }
 493         }
 494         return multiplier;
 495 }
 496
 497 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 498 {
 499         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 500         struct be_mcc_wrb *wrb
 501                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 502         memset(wrb, 0, sizeof(*wrb));
 503         return wrb;
 504 }
 505
 506 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 507 {
 508         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 509         struct be_mcc_wrb *wrb;
 510
 511         if (atomic_read(&mccq->used) >= mccq->len) {
 512                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 513                 return NULL;
 514         }
 515
 516         wrb = queue_head_node(mccq);
 517         queue_head_inc(mccq);
 518         atomic_inc(&mccq->used);
 519         memset(wrb, 0, sizeof(*wrb));
 520         return wrb;
 521 }
 522
 523 /* Tell fw we're about to start firing cmds by writing a
 524  * special pattern across the wrb hdr; uses mbox
 525  */
 526 int be_cmd_fw_init(struct be_adapter *adapter)
 527 {
 528         u8 *wrb;
 529         int status;
 530
 531         if (mutex_lock_interruptible(&adapter->mbox_lock))
 532                 return -1;
 533
 534         wrb = (u8 *)wrb_from_mbox(adapter);
 535         *wrb++ = 0xFF;
 536         *wrb++ = 0x12;
 537         *wrb++ = 0x34;
 538         *wrb++ = 0xFF;
 539         *wrb++ = 0xFF;
 540         *wrb++ = 0x56;
 541         *wrb++ = 0x78;
 542         *wrb = 0xFF;
 543
 544         status = be_mbox_notify_wait(adapter);
 545
 546         mutex_unlock(&adapter->mbox_lock);
 547         return status;
 548 }
 549
 550 /* Tell fw we're done with firing cmds by writing a
 551  * special pattern across the wrb hdr; uses mbox
 552  */
 553 int be_cmd_fw_clean(struct be_adapter *adapter)
 554 {
 555         u8 *wrb;
 556         int status;
 557
 558         if (mutex_lock_interruptible(&adapter->mbox_lock))
 559                 return -1;
 560
 561         wrb = (u8 *)wrb_from_mbox(adapter);
 562         *wrb++ = 0xFF;
 563         *wrb++ = 0xAA;
 564         *wrb++ = 0xBB;
 565         *wrb++ = 0xFF;
 566         *wrb++ = 0xFF;
 567         *wrb++ = 0xCC;
 568         *wrb++ = 0xDD;
 569         *wrb = 0xFF;
 570
 571         status = be_mbox_notify_wait(adapter);
 572
 573         mutex_unlock(&adapter->mbox_lock);
 574         return status;
 575 }
 576 int be_cmd_eq_create(struct be_adapter *adapter,
 577                 struct be_queue_info *eq, int eq_delay)
 578 {
 579         struct be_mcc_wrb *wrb;
 580         struct be_cmd_req_eq_create *req;
 581         struct be_dma_mem *q_mem = &eq->dma_mem;
 582         int status;
 583
 584         if (mutex_lock_interruptible(&adapter->mbox_lock))
 585                 return -1;
 586
 587         wrb = wrb_from_mbox(adapter);
 588         req = embedded_payload(wrb);
 589
 590         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 591                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 592
 593         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 594
 595         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 596         /* 4byte eqe*/
 597         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 598         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 599                         __ilog2_u32(eq->len/256));
 600         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 601                         eq_delay_to_mult(eq_delay));
 602         be_dws_cpu_to_le(req->context, sizeof(req->context));
 603
 604         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 605
 606         status = be_mbox_notify_wait(adapter);
 607         if (!status) {
 608                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 609                 eq->id = le16_to_cpu(resp->eq_id);
 610                 eq->created = true;
 611         }
 612
 613         mutex_unlock(&adapter->mbox_lock);
 614         return status;
 615 }
 616
 617 /* Use MCC */
 618 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 619                         u8 type, bool permanent, u32 if_handle, u32 pmac_id)
 620 {
 621         struct be_mcc_wrb *wrb;
 622         struct be_cmd_req_mac_query *req;
 623         int status;
 624
 625         spin_lock_bh(&adapter->mcc_lock);
 626
 627         wrb = wrb_from_mccq(adapter);
 628         if (!wrb) {
 629                 status = -EBUSY;
 630                 goto err;
 631         }
 632         req = embedded_payload(wrb);
 633
 634         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 635                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 636         req->type = type;
 637         if (permanent) {
 638                 req->permanent = 1;
 639         } else {
 640                 req->if_id = cpu_to_le16((u16) if_handle);
 641                 req->pmac_id = cpu_to_le32(pmac_id);
 642                 req->permanent = 0;
 643         }
 644
 645         status = be_mcc_notify_wait(adapter);
 646         if (!status) {
 647                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 648                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 649         }
 650
 651 err:
 652         spin_unlock_bh(&adapter->mcc_lock);
 653         return status;
 654 }
 655
 656 /* Uses synchronous MCCQ */
 657 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 658                 u32 if_id, u32 *pmac_id, u32 domain)
 659 {
 660         struct be_mcc_wrb *wrb;
 661         struct be_cmd_req_pmac_add *req;
 662         int status;
 663
 664         spin_lock_bh(&adapter->mcc_lock);
 665
 666         wrb = wrb_from_mccq(adapter);
 667         if (!wrb) {
 668                 status = -EBUSY;
 669                 goto err;
 670         }
 671         req = embedded_payload(wrb);
 672
 673         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 674                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 675
 676         req->hdr.domain = domain;
 677         req->if_id = cpu_to_le32(if_id);
 678         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 679
 680         status = be_mcc_notify_wait(adapter);
 681         if (!status) {
 682                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 683                 *pmac_id = le32_to_cpu(resp->pmac_id);
 684         }
 685
 686 err:
 687         spin_unlock_bh(&adapter->mcc_lock);
 688
 689          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 690                 status = -EPERM;
 691
 692         return status;
 693 }
 694
 695 /* Uses synchronous MCCQ */
 696 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 697 {
 698         struct be_mcc_wrb *wrb;
 699         struct be_cmd_req_pmac_del *req;
 700         int status;
 701
 702         if (pmac_id == -1)
 703                 return 0;
 704
 705         spin_lock_bh(&adapter->mcc_lock);
 706
 707         wrb = wrb_from_mccq(adapter);
 708         if (!wrb) {
 709                 status = -EBUSY;
 710                 goto err;
 711         }
 712         req = embedded_payload(wrb);
 713
 714         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 715                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 716
 717         req->hdr.domain = dom;
 718         req->if_id = cpu_to_le32(if_id);
 719         req->pmac_id = cpu_to_le32(pmac_id);
 720
 721         status = be_mcc_notify_wait(adapter);
 722
 723 err:
 724         spin_unlock_bh(&adapter->mcc_lock);
 725         return status;
 726 }
 727
 728 /* Uses Mbox */
 729 int be_cmd_cq_create(struct be_adapter *adapter,
 730                 struct be_queue_info *cq, struct be_queue_info *eq,
 731                 bool sol_evts, bool no_delay, int coalesce_wm)
 732 {
 733         struct be_mcc_wrb *wrb;
 734         struct be_cmd_req_cq_create *req;
 735         struct be_dma_mem *q_mem = &cq->dma_mem;
 736         void *ctxt;
 737         int status;
 738
 739         if (mutex_lock_interruptible(&adapter->mbox_lock))
 740                 return -1;
 741
 742         wrb = wrb_from_mbox(adapter);
 743         req = embedded_payload(wrb);
 744         ctxt = &req->context;
 745
 746         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 747                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 748
 749         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 750         if (lancer_chip(adapter)) {
 751                 req->hdr.version = 2;
 752                 req->page_size = 1; /* 1 for 4K */
 753                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 754                                                                 no_delay);
 755                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 756                                                 __ilog2_u32(cq->len/256));
 757                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 758                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 759                                                                 ctxt, 1);
 760                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 761                                                                 ctxt, eq->id);
 762                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 763         } else {
 764                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 765                                                                 coalesce_wm);
 766                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 767                                                                 ctxt, no_delay);
 768                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 769                                                 __ilog2_u32(cq->len/256));
 770                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 771                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 772                                                                 ctxt, sol_evts);
 773                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 774                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 775                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 776         }
 777
 778         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 779
 780         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 781
 782         status = be_mbox_notify_wait(adapter);
 783         if (!status) {
 784                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 785                 cq->id = le16_to_cpu(resp->cq_id);
 786                 cq->created = true;
 787         }
 788
 789         mutex_unlock(&adapter->mbox_lock);
 790
 791         return status;
 792 }
 793
 794 static u32 be_encoded_q_len(int q_len)
 795 {
 796         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 797         if (len_encoded == 16)
 798                 len_encoded = 0;
 799         return len_encoded;
 800 }
 801
 802 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 803                         struct be_queue_info *mccq,
 804                         struct be_queue_info *cq)
 805 {
 806         struct be_mcc_wrb *wrb;
 807         struct be_cmd_req_mcc_ext_create *req;
 808         struct be_dma_mem *q_mem = &mccq->dma_mem;
 809         void *ctxt;
 810         int status;
 811
 812         if (mutex_lock_interruptible(&adapter->mbox_lock))
 813                 return -1;
 814
 815         wrb = wrb_from_mbox(adapter);
 816         req = embedded_payload(wrb);
 817         ctxt = &req->context;
 818
 819         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 820                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
 821
 822         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 823         if (lancer_chip(adapter)) {
 824                 req->hdr.version = 1;
 825                 req->cq_id = cpu_to_le16(cq->id);
 826
 827                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 828                                                 be_encoded_q_len(mccq->len));
 829                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 830                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 831                                                                 ctxt, cq->id);
 832                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 833                                                                  ctxt, 1);
 834
 835         } else {
 836                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 837                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 838                                                 be_encoded_q_len(mccq->len));
 839                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 840         }
 841
 842         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 843         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 844         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 845
 846         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 847
 848         status = be_mbox_notify_wait(adapter);
 849         if (!status) {
 850                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 851                 mccq->id = le16_to_cpu(resp->id);
 852                 mccq->created = true;
 853         }
 854         mutex_unlock(&adapter->mbox_lock);
 855
 856         return status;
 857 }
 858
 859 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 860                         struct be_queue_info *mccq,
 861                         struct be_queue_info *cq)
 862 {
 863         struct be_mcc_wrb *wrb;
 864         struct be_cmd_req_mcc_create *req;
 865         struct be_dma_mem *q_mem = &mccq->dma_mem;
 866         void *ctxt;
 867         int status;
 868
 869         if (mutex_lock_interruptible(&adapter->mbox_lock))
 870                 return -1;
 871
 872         wrb = wrb_from_mbox(adapter);
 873         req = embedded_payload(wrb);
 874         ctxt = &req->context;
 875
 876         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 877                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
 878
 879         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 880
 881         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 882         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 883                         be_encoded_q_len(mccq->len));
 884         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 885
 886         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 887
 888         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 889
 890         status = be_mbox_notify_wait(adapter);
 891         if (!status) {
 892                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 893                 mccq->id = le16_to_cpu(resp->id);
 894                 mccq->created = true;
 895         }
 896
 897         mutex_unlock(&adapter->mbox_lock);
 898         return status;
 899 }
 900
 901 int be_cmd_mccq_create(struct be_adapter *adapter,
 902                         struct be_queue_info *mccq,
 903                         struct be_queue_info *cq)
 904 {
 905         int status;
 906
 907         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
 908         if (status && !lancer_chip(adapter)) {
 909                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
 910                         "or newer to avoid conflicting priorities between NIC "
 911                         "and FCoE traffic");
 912                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
 913         }
 914         return status;
 915 }
 916
 917 int be_cmd_txq_create(struct be_adapter *adapter,
 918                         struct be_queue_info *txq,
 919                         struct be_queue_info *cq)
 920 {
 921         struct be_mcc_wrb *wrb;
 922         struct be_cmd_req_eth_tx_create *req;
 923         struct be_dma_mem *q_mem = &txq->dma_mem;
 924         void *ctxt;
 925         int status;
 926
 927         spin_lock_bh(&adapter->mcc_lock);
 928
 929         wrb = wrb_from_mccq(adapter);
 930         if (!wrb) {
 931                 status = -EBUSY;
 932                 goto err;
 933         }
 934
 935         req = embedded_payload(wrb);
 936         ctxt = &req->context;
 937
 938         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 939                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
 940
 941         if (lancer_chip(adapter)) {
 942                 req->hdr.version = 1;
 943                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 944                                         adapter->if_handle);
 945         }
 946
 947         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 948         req->ulp_num = BE_ULP1_NUM;
 949         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 950
 951         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 952                 be_encoded_q_len(txq->len));
 953         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 954         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 955
 956         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 957
 958         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 959
 960         status = be_mcc_notify_wait(adapter);
 961         if (!status) {
 962                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 963                 txq->id = le16_to_cpu(resp->cid);
 964                 txq->created = true;
 965         }
 966
 967 err:
 968         spin_unlock_bh(&adapter->mcc_lock);
 969
 970         return status;
 971 }
 972
 973 /* Uses MCC */
 974 int be_cmd_rxq_create(struct be_adapter *adapter,
 975                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 976                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 977 {
 978         struct be_mcc_wrb *wrb;
 979         struct be_cmd_req_eth_rx_create *req;
 980         struct be_dma_mem *q_mem = &rxq->dma_mem;
 981         int status;
 982
 983         spin_lock_bh(&adapter->mcc_lock);
 984
 985         wrb = wrb_from_mccq(adapter);
 986         if (!wrb) {
 987                 status = -EBUSY;
 988                 goto err;
 989         }
 990         req = embedded_payload(wrb);
 991
 992         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 993                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
 994
 995         req->cq_id = cpu_to_le16(cq_id);
 996         req->frag_size = fls(frag_size) - 1;
 997         req->num_pages = 2;
 998         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 999         req->interface_id = cpu_to_le32(if_id);
1000         req->max_frame_size = cpu_to_le16(max_frame_size);
1001         req->rss_queue = cpu_to_le32(rss);
1002
1003         status = be_mcc_notify_wait(adapter);
1004         if (!status) {
1005                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1006                 rxq->id = le16_to_cpu(resp->id);
1007                 rxq->created = true;
1008                 *rss_id = resp->rss_id;
1009         }
1010
1011 err:
1012         spin_unlock_bh(&adapter->mcc_lock);
1013         return status;
1014 }
1015
1016 /* Generic destroyer function for all types of queues
1017  * Uses Mbox
1018  */
1019 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1020                 int queue_type)
1021 {
1022         struct be_mcc_wrb *wrb;
1023         struct be_cmd_req_q_destroy *req;
1024         u8 subsys = 0, opcode = 0;
1025         int status;
1026
1027         if (mutex_lock_interruptible(&adapter->mbox_lock))
1028                 return -1;
1029
1030         wrb = wrb_from_mbox(adapter);
1031         req = embedded_payload(wrb);
1032
1033         switch (queue_type) {
1034         case QTYPE_EQ:
1035                 subsys = CMD_SUBSYSTEM_COMMON;
1036                 opcode = OPCODE_COMMON_EQ_DESTROY;
1037                 break;
1038         case QTYPE_CQ:
1039                 subsys = CMD_SUBSYSTEM_COMMON;
1040                 opcode = OPCODE_COMMON_CQ_DESTROY;
1041                 break;
1042         case QTYPE_TXQ:
1043                 subsys = CMD_SUBSYSTEM_ETH;
1044                 opcode = OPCODE_ETH_TX_DESTROY;
1045                 break;
1046         case QTYPE_RXQ:
1047                 subsys = CMD_SUBSYSTEM_ETH;
1048                 opcode = OPCODE_ETH_RX_DESTROY;
1049                 break;
1050         case QTYPE_MCCQ:
1051                 subsys = CMD_SUBSYSTEM_COMMON;
1052                 opcode = OPCODE_COMMON_MCC_DESTROY;
1053                 break;
1054         default:
1055                 BUG();
1056         }
1057
1058         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1059                                 NULL);
1060         req->id = cpu_to_le16(q->id);
1061
1062         status = be_mbox_notify_wait(adapter);
1063         if (!status)
1064                 q->created = false;
1065
1066         mutex_unlock(&adapter->mbox_lock);
1067         return status;
1068 }
1069
1070 /* Uses MCC */
1071 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1072 {
1073         struct be_mcc_wrb *wrb;
1074         struct be_cmd_req_q_destroy *req;
1075         int status;
1076
1077         spin_lock_bh(&adapter->mcc_lock);
1078
1079         wrb = wrb_from_mccq(adapter);
1080         if (!wrb) {
1081                 status = -EBUSY;
1082                 goto err;
1083         }
1084         req = embedded_payload(wrb);
1085
1086         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1087                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1088         req->id = cpu_to_le16(q->id);
1089
1090         status = be_mcc_notify_wait(adapter);
1091         if (!status)
1092                 q->created = false;
1093
1094 err:
1095         spin_unlock_bh(&adapter->mcc_lock);
1096         return status;
1097 }
1098
1099 /* Create an rx filtering policy configuration on an i/f
1100  * Uses MCCQ
1101  */
1102 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1103                 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
1104 {
1105         struct be_mcc_wrb *wrb;
1106         struct be_cmd_req_if_create *req;
1107         int status;
1108
1109         spin_lock_bh(&adapter->mcc_lock);
1110
1111         wrb = wrb_from_mccq(adapter);
1112         if (!wrb) {
1113                 status = -EBUSY;
1114                 goto err;
1115         }
1116         req = embedded_payload(wrb);
1117
1118         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1119                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1120         req->hdr.domain = domain;
1121         req->capability_flags = cpu_to_le32(cap_flags);
1122         req->enable_flags = cpu_to_le32(en_flags);
1123         if (mac)
1124                 memcpy(req->mac_addr, mac, ETH_ALEN);
1125         else
1126                 req->pmac_invalid = true;
1127
1128         status = be_mcc_notify_wait(adapter);
1129         if (!status) {
1130                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1131                 *if_handle = le32_to_cpu(resp->interface_id);
1132                 if (mac)
1133                         *pmac_id = le32_to_cpu(resp->pmac_id);
1134         }
1135
1136 err:
1137         spin_unlock_bh(&adapter->mcc_lock);
1138         return status;
1139 }
1140
1141 /* Uses MCCQ */
1142 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1143 {
1144         struct be_mcc_wrb *wrb;
1145         struct be_cmd_req_if_destroy *req;
1146         int status;
1147
1148         if (interface_id == -1)
1149                 return 0;
1150
1151         spin_lock_bh(&adapter->mcc_lock);
1152
1153         wrb = wrb_from_mccq(adapter);
1154         if (!wrb) {
1155                 status = -EBUSY;
1156                 goto err;
1157         }
1158         req = embedded_payload(wrb);
1159
1160         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1162         req->hdr.domain = domain;
1163         req->interface_id = cpu_to_le32(interface_id);
1164
1165         status = be_mcc_notify_wait(adapter);
1166 err:
1167         spin_unlock_bh(&adapter->mcc_lock);
1168         return status;
1169 }
1170
1171 /* Get stats is a non embedded command: the request is not embedded inside
1172  * WRB but is a separate dma memory block
1173  * Uses asynchronous MCC
1174  */
1175 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1176 {
1177         struct be_mcc_wrb *wrb;
1178         struct be_cmd_req_hdr *hdr;
1179         int status = 0;
1180
1181         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1182                 be_cmd_get_die_temperature(adapter);
1183
1184         spin_lock_bh(&adapter->mcc_lock);
1185
1186         wrb = wrb_from_mccq(adapter);
1187         if (!wrb) {
1188                 status = -EBUSY;
1189                 goto err;
1190         }
1191         hdr = nonemb_cmd->va;
1192
1193         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1194                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1195
1196         if (adapter->generation == BE_GEN3)
1197                 hdr->version = 1;
1198
1199         be_mcc_notify(adapter);
1200         adapter->stats_cmd_sent = true;
1201
1202 err:
1203         spin_unlock_bh(&adapter->mcc_lock);
1204         return status;
1205 }
1206
1207 /* Lancer Stats */
1208 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209                                 struct be_dma_mem *nonemb_cmd)
1210 {
1211
1212         struct be_mcc_wrb *wrb;
1213         struct lancer_cmd_req_pport_stats *req;
1214         int status = 0;
1215
1216         spin_lock_bh(&adapter->mcc_lock);
1217
1218         wrb = wrb_from_mccq(adapter);
1219         if (!wrb) {
1220                 status = -EBUSY;
1221                 goto err;
1222         }
1223         req = nonemb_cmd->va;
1224
1225         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1226                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1227                         nonemb_cmd);
1228
1229         req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1230         req->cmd_params.params.reset_stats = 0;
1231
1232         be_mcc_notify(adapter);
1233         adapter->stats_cmd_sent = true;
1234
1235 err:
1236         spin_unlock_bh(&adapter->mcc_lock);
1237         return status;
1238 }
1239
1240 /* Uses synchronous mcc */
1241 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1242                              u16 *link_speed, u8 *link_status, u32 dom)
1243 {
1244         struct be_mcc_wrb *wrb;
1245         struct be_cmd_req_link_status *req;
1246         int status;
1247
1248         spin_lock_bh(&adapter->mcc_lock);
1249
1250         if (link_status)
1251                 *link_status = LINK_DOWN;
1252
1253         wrb = wrb_from_mccq(adapter);
1254         if (!wrb) {
1255                 status = -EBUSY;
1256                 goto err;
1257         }
1258         req = embedded_payload(wrb);
1259
1260         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1261                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1262
1263         if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1264                 req->hdr.version = 1;
1265
1266         req->hdr.domain = dom;
1267
1268         status = be_mcc_notify_wait(adapter);
1269         if (!status) {
1270                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1271                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1272                         if (link_speed)
1273                                 *link_speed = le16_to_cpu(resp->link_speed);
1274                         if (mac_speed)
1275                                 *mac_speed = resp->mac_speed;
1276                 }
1277                 if (link_status)
1278                         *link_status = resp->logical_link_status;
1279         }
1280
1281 err:
1282         spin_unlock_bh(&adapter->mcc_lock);
1283         return status;
1284 }
1285
1286 /* Uses synchronous mcc */
1287 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1288 {
1289         struct be_mcc_wrb *wrb;
1290         struct be_cmd_req_get_cntl_addnl_attribs *req;
1291         u16 mccq_index;
1292         int status;
1293
1294         spin_lock_bh(&adapter->mcc_lock);
1295
1296         mccq_index = adapter->mcc_obj.q.head;
1297
1298         wrb = wrb_from_mccq(adapter);
1299         if (!wrb) {
1300                 status = -EBUSY;
1301                 goto err;
1302         }
1303         req = embedded_payload(wrb);
1304
1305         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1306                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1307                 wrb, NULL);
1308
1309         wrb->tag1 = mccq_index;
1310
1311         be_mcc_notify(adapter);
1312
1313 err:
1314         spin_unlock_bh(&adapter->mcc_lock);
1315         return status;
1316 }
1317
1318 /* Uses synchronous mcc */
1319 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1320 {
1321         struct be_mcc_wrb *wrb;
1322         struct be_cmd_req_get_fat *req;
1323         int status;
1324
1325         spin_lock_bh(&adapter->mcc_lock);
1326
1327         wrb = wrb_from_mccq(adapter);
1328         if (!wrb) {
1329                 status = -EBUSY;
1330                 goto err;
1331         }
1332         req = embedded_payload(wrb);
1333
1334         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1335                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1336         req->fat_operation = cpu_to_le32(QUERY_FAT);
1337         status = be_mcc_notify_wait(adapter);
1338         if (!status) {
1339                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1340                 if (log_size && resp->log_size)
1341                         *log_size = le32_to_cpu(resp->log_size) -
1342                                         sizeof(u32);
1343         }
1344 err:
1345         spin_unlock_bh(&adapter->mcc_lock);
1346         return status;
1347 }
1348
1349 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1350 {
1351         struct be_dma_mem get_fat_cmd;
1352         struct be_mcc_wrb *wrb;
1353         struct be_cmd_req_get_fat *req;
1354         u32 offset = 0, total_size, buf_size,
1355                                 log_offset = sizeof(u32), payload_len;
1356         int status;
1357
1358         if (buf_len == 0)
1359                 return;
1360
1361         total_size = buf_len;
1362
1363         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1364         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1365                         get_fat_cmd.size,
1366                         &get_fat_cmd.dma);
1367         if (!get_fat_cmd.va) {
1368                 status = -ENOMEM;
1369                 dev_err(&adapter->pdev->dev,
1370                 "Memory allocation failure while retrieving FAT data\n");
1371                 return;
1372         }
1373
1374         spin_lock_bh(&adapter->mcc_lock);
1375
1376         while (total_size) {
1377                 buf_size = min(total_size, (u32)60*1024);
1378                 total_size -= buf_size;
1379
1380                 wrb = wrb_from_mccq(adapter);
1381                 if (!wrb) {
1382                         status = -EBUSY;
1383                         goto err;
1384                 }
1385                 req = get_fat_cmd.va;
1386
1387                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1388                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1389                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1390                                 &get_fat_cmd);
1391
1392                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1393                 req->read_log_offset = cpu_to_le32(log_offset);
1394                 req->read_log_length = cpu_to_le32(buf_size);
1395                 req->data_buffer_size = cpu_to_le32(buf_size);
1396
1397                 status = be_mcc_notify_wait(adapter);
1398                 if (!status) {
1399                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1400                         memcpy(buf + offset,
1401                                 resp->data_buffer,
1402                                 le32_to_cpu(resp->read_log_length));
1403                 } else {
1404                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1405                         goto err;
1406                 }
1407                 offset += buf_size;
1408                 log_offset += buf_size;
1409         }
1410 err:
1411         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1412                         get_fat_cmd.va,
1413                         get_fat_cmd.dma);
1414         spin_unlock_bh(&adapter->mcc_lock);
1415 }
1416
1417 /* Uses synchronous mcc */
1418 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1419                         char *fw_on_flash)
1420 {
1421         struct be_mcc_wrb *wrb;
1422         struct be_cmd_req_get_fw_version *req;
1423         int status;
1424
1425         spin_lock_bh(&adapter->mcc_lock);
1426
1427         wrb = wrb_from_mccq(adapter);
1428         if (!wrb) {
1429                 status = -EBUSY;
1430                 goto err;
1431         }
1432
1433         req = embedded_payload(wrb);
1434
1435         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1436                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1437         status = be_mcc_notify_wait(adapter);
1438         if (!status) {
1439                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1440                 strcpy(fw_ver, resp->firmware_version_string);
1441                 if (fw_on_flash)
1442                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1443         }
1444 err:
1445         spin_unlock_bh(&adapter->mcc_lock);
1446         return status;
1447 }
1448
1449 /* set the EQ delay interval of an EQ to specified value
1450  * Uses async mcc
1451  */
1452 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1453 {
1454         struct be_mcc_wrb *wrb;
1455         struct be_cmd_req_modify_eq_delay *req;
1456         int status = 0;
1457
1458         spin_lock_bh(&adapter->mcc_lock);
1459
1460         wrb = wrb_from_mccq(adapter);
1461         if (!wrb) {
1462                 status = -EBUSY;
1463                 goto err;
1464         }
1465         req = embedded_payload(wrb);
1466
1467         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1468                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1469
1470         req->num_eq = cpu_to_le32(1);
1471         req->delay[0].eq_id = cpu_to_le32(eq_id);
1472         req->delay[0].phase = 0;
1473         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1474
1475         be_mcc_notify(adapter);
1476
1477 err:
1478         spin_unlock_bh(&adapter->mcc_lock);
1479         return status;
1480 }
1481
1482 /* Uses sycnhronous mcc */
1483 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1484                         u32 num, bool untagged, bool promiscuous)
1485 {
1486         struct be_mcc_wrb *wrb;
1487         struct be_cmd_req_vlan_config *req;
1488         int status;
1489
1490         spin_lock_bh(&adapter->mcc_lock);
1491
1492         wrb = wrb_from_mccq(adapter);
1493         if (!wrb) {
1494                 status = -EBUSY;
1495                 goto err;
1496         }
1497         req = embedded_payload(wrb);
1498
1499         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1500                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1501
1502         req->interface_id = if_id;
1503         req->promiscuous = promiscuous;
1504         req->untagged = untagged;
1505         req->num_vlan = num;
1506         if (!promiscuous) {
1507                 memcpy(req->normal_vlan, vtag_array,
1508                         req->num_vlan * sizeof(vtag_array[0]));
1509         }
1510
1511         status = be_mcc_notify_wait(adapter);
1512
1513 err:
1514         spin_unlock_bh(&adapter->mcc_lock);
1515         return status;
1516 }
1517
1518 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1519 {
1520         struct be_mcc_wrb *wrb;
1521         struct be_dma_mem *mem = &adapter->rx_filter;
1522         struct be_cmd_req_rx_filter *req = mem->va;
1523         int status;
1524
1525         spin_lock_bh(&adapter->mcc_lock);
1526
1527         wrb = wrb_from_mccq(adapter);
1528         if (!wrb) {
1529                 status = -EBUSY;
1530                 goto err;
1531         }
1532         memset(req, 0, sizeof(*req));
1533         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1534                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1535                                 wrb, mem);
1536
1537         req->if_id = cpu_to_le32(adapter->if_handle);
1538         if (flags & IFF_PROMISC) {
1539                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1540                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1541                 if (value == ON)
1542                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1543                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1544         } else if (flags & IFF_ALLMULTI) {
1545                 req->if_flags_mask = req->if_flags =
1546                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1547         } else {
1548                 struct netdev_hw_addr *ha;
1549                 int i = 0;
1550
1551                 req->if_flags_mask = req->if_flags =
1552                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1553
1554                 /* Reset mcast promisc mode if already set by setting mask
1555                  * and not setting flags field
1556                  */
1557                 req->if_flags_mask |=
1558                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1559
1560                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1561                 netdev_for_each_mc_addr(ha, adapter->netdev)
1562                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1563         }
1564
1565         status = be_mcc_notify_wait(adapter);
1566 err:
1567         spin_unlock_bh(&adapter->mcc_lock);
1568         return status;
1569 }
1570
1571 /* Uses synchrounous mcc */
1572 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1573 {
1574         struct be_mcc_wrb *wrb;
1575         struct be_cmd_req_set_flow_control *req;
1576         int status;
1577
1578         spin_lock_bh(&adapter->mcc_lock);
1579
1580         wrb = wrb_from_mccq(adapter);
1581         if (!wrb) {
1582                 status = -EBUSY;
1583                 goto err;
1584         }
1585         req = embedded_payload(wrb);
1586
1587         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1588                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1589
1590         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1591         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1592
1593         status = be_mcc_notify_wait(adapter);
1594
1595 err:
1596         spin_unlock_bh(&adapter->mcc_lock);
1597         return status;
1598 }
1599
1600 /* Uses sycn mcc */
1601 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1602 {
1603         struct be_mcc_wrb *wrb;
1604         struct be_cmd_req_get_flow_control *req;
1605         int status;
1606
1607         spin_lock_bh(&adapter->mcc_lock);
1608
1609         wrb = wrb_from_mccq(adapter);
1610         if (!wrb) {
1611                 status = -EBUSY;
1612                 goto err;
1613         }
1614         req = embedded_payload(wrb);
1615
1616         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1617                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1618
1619         status = be_mcc_notify_wait(adapter);
1620         if (!status) {
1621                 struct be_cmd_resp_get_flow_control *resp =
1622                                                 embedded_payload(wrb);
1623                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1624                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1625         }
1626
1627 err:
1628         spin_unlock_bh(&adapter->mcc_lock);
1629         return status;
1630 }
1631
1632 /* Uses mbox */
1633 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1634                 u32 *mode, u32 *caps)
1635 {
1636         struct be_mcc_wrb *wrb;
1637         struct be_cmd_req_query_fw_cfg *req;
1638         int status;
1639
1640         if (mutex_lock_interruptible(&adapter->mbox_lock))
1641                 return -1;
1642
1643         wrb = wrb_from_mbox(adapter);
1644         req = embedded_payload(wrb);
1645
1646         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1647                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1648
1649         status = be_mbox_notify_wait(adapter);
1650         if (!status) {
1651                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1652                 *port_num = le32_to_cpu(resp->phys_port);
1653                 *mode = le32_to_cpu(resp->function_mode);
1654                 *caps = le32_to_cpu(resp->function_caps);
1655         }
1656
1657         mutex_unlock(&adapter->mbox_lock);
1658         return status;
1659 }
1660
1661 /* Uses mbox */
1662 int be_cmd_reset_function(struct be_adapter *adapter)
1663 {
1664         struct be_mcc_wrb *wrb;
1665         struct be_cmd_req_hdr *req;
1666         int status;
1667
1668         if (mutex_lock_interruptible(&adapter->mbox_lock))
1669                 return -1;
1670
1671         wrb = wrb_from_mbox(adapter);
1672         req = embedded_payload(wrb);
1673
1674         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1675                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1676
1677         status = be_mbox_notify_wait(adapter);
1678
1679         mutex_unlock(&adapter->mbox_lock);
1680         return status;
1681 }
1682
1683 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1684 {
1685         struct be_mcc_wrb *wrb;
1686         struct be_cmd_req_rss_config *req;
1687         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1688                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1689                         0x3ea83c02, 0x4a110304};
1690         int status;
1691
1692         if (mutex_lock_interruptible(&adapter->mbox_lock))
1693                 return -1;
1694
1695         wrb = wrb_from_mbox(adapter);
1696         req = embedded_payload(wrb);
1697
1698         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1699                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1700
1701         req->if_id = cpu_to_le32(adapter->if_handle);
1702         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1703         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1704         memcpy(req->cpu_table, rsstable, table_size);
1705         memcpy(req->hash, myhash, sizeof(myhash));
1706         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1707
1708         status = be_mbox_notify_wait(adapter);
1709
1710         mutex_unlock(&adapter->mbox_lock);
1711         return status;
1712 }
1713
1714 /* Uses sync mcc */
1715 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1716                         u8 bcn, u8 sts, u8 state)
1717 {
1718         struct be_mcc_wrb *wrb;
1719         struct be_cmd_req_enable_disable_beacon *req;
1720         int status;
1721
1722         spin_lock_bh(&adapter->mcc_lock);
1723
1724         wrb = wrb_from_mccq(adapter);
1725         if (!wrb) {
1726                 status = -EBUSY;
1727                 goto err;
1728         }
1729         req = embedded_payload(wrb);
1730
1731         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1732                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1733
1734         req->port_num = port_num;
1735         req->beacon_state = state;
1736         req->beacon_duration = bcn;
1737         req->status_duration = sts;
1738
1739         status = be_mcc_notify_wait(adapter);
1740
1741 err:
1742         spin_unlock_bh(&adapter->mcc_lock);
1743         return status;
1744 }
1745
1746 /* Uses sync mcc */
1747 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1748 {
1749         struct be_mcc_wrb *wrb;
1750         struct be_cmd_req_get_beacon_state *req;
1751         int status;
1752
1753         spin_lock_bh(&adapter->mcc_lock);
1754
1755         wrb = wrb_from_mccq(adapter);
1756         if (!wrb) {
1757                 status = -EBUSY;
1758                 goto err;
1759         }
1760         req = embedded_payload(wrb);
1761
1762         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1763                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1764
1765         req->port_num = port_num;
1766
1767         status = be_mcc_notify_wait(adapter);
1768         if (!status) {
1769                 struct be_cmd_resp_get_beacon_state *resp =
1770                                                 embedded_payload(wrb);
1771                 *state = resp->beacon_state;
1772         }
1773
1774 err:
1775         spin_unlock_bh(&adapter->mcc_lock);
1776         return status;
1777 }
1778
1779 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1780                         u32 data_size, u32 data_offset, const char *obj_name,
1781                         u32 *data_written, u8 *addn_status)
1782 {
1783         struct be_mcc_wrb *wrb;
1784         struct lancer_cmd_req_write_object *req;
1785         struct lancer_cmd_resp_write_object *resp;
1786         void *ctxt = NULL;
1787         int status;
1788
1789         spin_lock_bh(&adapter->mcc_lock);
1790         adapter->flash_status = 0;
1791
1792         wrb = wrb_from_mccq(adapter);
1793         if (!wrb) {
1794                 status = -EBUSY;
1795                 goto err_unlock;
1796         }
1797
1798         req = embedded_payload(wrb);
1799
1800         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1801                                 OPCODE_COMMON_WRITE_OBJECT,
1802                                 sizeof(struct lancer_cmd_req_write_object), wrb,
1803                                 NULL);
1804
1805         ctxt = &req->context;
1806         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1807                         write_length, ctxt, data_size);
1808
1809         if (data_size == 0)
1810                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1811                                 eof, ctxt, 1);
1812         else
1813                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1814                                 eof, ctxt, 0);
1815
1816         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1817         req->write_offset = cpu_to_le32(data_offset);
1818         strcpy(req->object_name, obj_name);
1819         req->descriptor_count = cpu_to_le32(1);
1820         req->buf_len = cpu_to_le32(data_size);
1821         req->addr_low = cpu_to_le32((cmd->dma +
1822                                 sizeof(struct lancer_cmd_req_write_object))
1823                                 & 0xFFFFFFFF);
1824         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1825                                 sizeof(struct lancer_cmd_req_write_object)));
1826
1827         be_mcc_notify(adapter);
1828         spin_unlock_bh(&adapter->mcc_lock);
1829
1830         if (!wait_for_completion_timeout(&adapter->flash_compl,
1831                         msecs_to_jiffies(12000)))
1832                 status = -1;
1833         else
1834                 status = adapter->flash_status;
1835
1836         resp = embedded_payload(wrb);
1837         if (!status) {
1838                 *data_written = le32_to_cpu(resp->actual_write_len);
1839         } else {
1840                 *addn_status = resp->additional_status;
1841                 status = resp->status;
1842         }
1843
1844         return status;
1845
1846 err_unlock:
1847         spin_unlock_bh(&adapter->mcc_lock);
1848         return status;
1849 }
1850
1851 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1852                 u32 data_size, u32 data_offset, const char *obj_name,
1853                 u32 *data_read, u32 *eof, u8 *addn_status)
1854 {
1855         struct be_mcc_wrb *wrb;
1856         struct lancer_cmd_req_read_object *req;
1857         struct lancer_cmd_resp_read_object *resp;
1858         int status;
1859
1860         spin_lock_bh(&adapter->mcc_lock);
1861
1862         wrb = wrb_from_mccq(adapter);
1863         if (!wrb) {
1864                 status = -EBUSY;
1865                 goto err_unlock;
1866         }
1867
1868         req = embedded_payload(wrb);
1869
1870         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1871                         OPCODE_COMMON_READ_OBJECT,
1872                         sizeof(struct lancer_cmd_req_read_object), wrb,
1873                         NULL);
1874
1875         req->desired_read_len = cpu_to_le32(data_size);
1876         req->read_offset = cpu_to_le32(data_offset);
1877         strcpy(req->object_name, obj_name);
1878         req->descriptor_count = cpu_to_le32(1);
1879         req->buf_len = cpu_to_le32(data_size);
1880         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1881         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1882
1883         status = be_mcc_notify_wait(adapter);
1884
1885         resp = embedded_payload(wrb);
1886         if (!status) {
1887                 *data_read = le32_to_cpu(resp->actual_read_len);
1888                 *eof = le32_to_cpu(resp->eof);
1889         } else {
1890                 *addn_status = resp->additional_status;
1891         }
1892
1893 err_unlock:
1894         spin_unlock_bh(&adapter->mcc_lock);
1895         return status;
1896 }
1897
1898 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1899                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1900 {
1901         struct be_mcc_wrb *wrb;
1902         struct be_cmd_write_flashrom *req;
1903         int status;
1904
1905         spin_lock_bh(&adapter->mcc_lock);
1906         adapter->flash_status = 0;
1907
1908         wrb = wrb_from_mccq(adapter);
1909         if (!wrb) {
1910                 status = -EBUSY;
1911                 goto err_unlock;
1912         }
1913         req = cmd->va;
1914
1915         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1916                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1917
1918         req->params.op_type = cpu_to_le32(flash_type);
1919         req->params.op_code = cpu_to_le32(flash_opcode);
1920         req->params.data_buf_size = cpu_to_le32(buf_size);
1921
1922         be_mcc_notify(adapter);
1923         spin_unlock_bh(&adapter->mcc_lock);
1924
1925         if (!wait_for_completion_timeout(&adapter->flash_compl,
1926                         msecs_to_jiffies(40000)))
1927                 status = -1;
1928         else
1929                 status = adapter->flash_status;
1930
1931         return status;
1932
1933 err_unlock:
1934         spin_unlock_bh(&adapter->mcc_lock);
1935         return status;
1936 }
1937
1938 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1939                          int offset)
1940 {
1941         struct be_mcc_wrb *wrb;
1942         struct be_cmd_write_flashrom *req;
1943         int status;
1944
1945         spin_lock_bh(&adapter->mcc_lock);
1946
1947         wrb = wrb_from_mccq(adapter);
1948         if (!wrb) {
1949                 status = -EBUSY;
1950                 goto err;
1951         }
1952         req = embedded_payload(wrb);
1953
1954         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1955                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
1956
1957         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1958         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1959         req->params.offset = cpu_to_le32(offset);
1960         req->params.data_buf_size = cpu_to_le32(0x4);
1961
1962         status = be_mcc_notify_wait(adapter);
1963         if (!status)
1964                 memcpy(flashed_crc, req->params.data_buf, 4);
1965
1966 err:
1967         spin_unlock_bh(&adapter->mcc_lock);
1968         return status;
1969 }
1970
1971 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1972                                 struct be_dma_mem *nonemb_cmd)
1973 {
1974         struct be_mcc_wrb *wrb;
1975         struct be_cmd_req_acpi_wol_magic_config *req;
1976         int status;
1977
1978         spin_lock_bh(&adapter->mcc_lock);
1979
1980         wrb = wrb_from_mccq(adapter);
1981         if (!wrb) {
1982                 status = -EBUSY;
1983                 goto err;
1984         }
1985         req = nonemb_cmd->va;
1986
1987         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1988                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1989                 nonemb_cmd);
1990         memcpy(req->magic_mac, mac, ETH_ALEN);
1991
1992         status = be_mcc_notify_wait(adapter);
1993
1994 err:
1995         spin_unlock_bh(&adapter->mcc_lock);
1996         return status;
1997 }
1998
1999 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2000                         u8 loopback_type, u8 enable)
2001 {
2002         struct be_mcc_wrb *wrb;
2003         struct be_cmd_req_set_lmode *req;
2004         int status;
2005
2006         spin_lock_bh(&adapter->mcc_lock);
2007
2008         wrb = wrb_from_mccq(adapter);
2009         if (!wrb) {
2010                 status = -EBUSY;
2011                 goto err;
2012         }
2013
2014         req = embedded_payload(wrb);
2015
2016         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2017                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2018                         NULL);
2019
2020         req->src_port = port_num;
2021         req->dest_port = port_num;
2022         req->loopback_type = loopback_type;
2023         req->loopback_state = enable;
2024
2025         status = be_mcc_notify_wait(adapter);
2026 err:
2027         spin_unlock_bh(&adapter->mcc_lock);
2028         return status;
2029 }
2030
2031 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2032                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2033 {
2034         struct be_mcc_wrb *wrb;
2035         struct be_cmd_req_loopback_test *req;
2036         int status;
2037
2038         spin_lock_bh(&adapter->mcc_lock);
2039
2040         wrb = wrb_from_mccq(adapter);
2041         if (!wrb) {
2042                 status = -EBUSY;
2043                 goto err;
2044         }
2045
2046         req = embedded_payload(wrb);
2047
2048         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2049                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2050         req->hdr.timeout = cpu_to_le32(4);
2051
2052         req->pattern = cpu_to_le64(pattern);
2053         req->src_port = cpu_to_le32(port_num);
2054         req->dest_port = cpu_to_le32(port_num);
2055         req->pkt_size = cpu_to_le32(pkt_size);
2056         req->num_pkts = cpu_to_le32(num_pkts);
2057         req->loopback_type = cpu_to_le32(loopback_type);
2058
2059         status = be_mcc_notify_wait(adapter);
2060         if (!status) {
2061                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2062                 status = le32_to_cpu(resp->status);
2063         }
2064
2065 err:
2066         spin_unlock_bh(&adapter->mcc_lock);
2067         return status;
2068 }
2069
2070 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2071                                 u32 byte_cnt, struct be_dma_mem *cmd)
2072 {
2073         struct be_mcc_wrb *wrb;
2074         struct be_cmd_req_ddrdma_test *req;
2075         int status;
2076         int i, j = 0;
2077
2078         spin_lock_bh(&adapter->mcc_lock);
2079
2080         wrb = wrb_from_mccq(adapter);
2081         if (!wrb) {
2082                 status = -EBUSY;
2083                 goto err;
2084         }
2085         req = cmd->va;
2086         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2087                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2088
2089         req->pattern = cpu_to_le64(pattern);
2090         req->byte_count = cpu_to_le32(byte_cnt);
2091         for (i = 0; i < byte_cnt; i++) {
2092                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2093                 j++;
2094                 if (j > 7)
2095                         j = 0;
2096         }
2097
2098         status = be_mcc_notify_wait(adapter);
2099
2100         if (!status) {
2101                 struct be_cmd_resp_ddrdma_test *resp;
2102                 resp = cmd->va;
2103                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2104                                 resp->snd_err) {
2105                         status = -1;
2106                 }
2107         }
2108
2109 err:
2110         spin_unlock_bh(&adapter->mcc_lock);
2111         return status;
2112 }
2113
2114 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2115                                 struct be_dma_mem *nonemb_cmd)
2116 {
2117         struct be_mcc_wrb *wrb;
2118         struct be_cmd_req_seeprom_read *req;
2119         struct be_sge *sge;
2120         int status;
2121
2122         spin_lock_bh(&adapter->mcc_lock);
2123
2124         wrb = wrb_from_mccq(adapter);
2125         if (!wrb) {
2126                 status = -EBUSY;
2127                 goto err;
2128         }
2129         req = nonemb_cmd->va;
2130         sge = nonembedded_sgl(wrb);
2131
2132         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2133                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2134                         nonemb_cmd);
2135
2136         status = be_mcc_notify_wait(adapter);
2137
2138 err:
2139         spin_unlock_bh(&adapter->mcc_lock);
2140         return status;
2141 }
2142
2143 int be_cmd_get_phy_info(struct be_adapter *adapter,
2144                                 struct be_phy_info *phy_info)
2145 {
2146         struct be_mcc_wrb *wrb;
2147         struct be_cmd_req_get_phy_info *req;
2148         struct be_dma_mem cmd;
2149         int status;
2150
2151         spin_lock_bh(&adapter->mcc_lock);
2152
2153         wrb = wrb_from_mccq(adapter);
2154         if (!wrb) {
2155                 status = -EBUSY;
2156                 goto err;
2157         }
2158         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2159         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2160                                         &cmd.dma);
2161         if (!cmd.va) {
2162                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2163                 status = -ENOMEM;
2164                 goto err;
2165         }
2166
2167         req = cmd.va;
2168
2169         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2170                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2171                         wrb, &cmd);
2172
2173         status = be_mcc_notify_wait(adapter);
2174         if (!status) {
2175                 struct be_phy_info *resp_phy_info =
2176                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2177                 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2178                 phy_info->interface_type =
2179                         le16_to_cpu(resp_phy_info->interface_type);
2180         }
2181         pci_free_consistent(adapter->pdev, cmd.size,
2182                                 cmd.va, cmd.dma);
2183 err:
2184         spin_unlock_bh(&adapter->mcc_lock);
2185         return status;
2186 }
2187
2188 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2189 {
2190         struct be_mcc_wrb *wrb;
2191         struct be_cmd_req_set_qos *req;
2192         int status;
2193
2194         spin_lock_bh(&adapter->mcc_lock);
2195
2196         wrb = wrb_from_mccq(adapter);
2197         if (!wrb) {
2198                 status = -EBUSY;
2199                 goto err;
2200         }
2201
2202         req = embedded_payload(wrb);
2203
2204         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2205                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2206
2207         req->hdr.domain = domain;
2208         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2209         req->max_bps_nic = cpu_to_le32(bps);
2210
2211         status = be_mcc_notify_wait(adapter);
2212
2213 err:
2214         spin_unlock_bh(&adapter->mcc_lock);
2215         return status;
2216 }
2217
2218 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2219 {
2220         struct be_mcc_wrb *wrb;
2221         struct be_cmd_req_cntl_attribs *req;
2222         struct be_cmd_resp_cntl_attribs *resp;
2223         int status;
2224         int payload_len = max(sizeof(*req), sizeof(*resp));
2225         struct mgmt_controller_attrib *attribs;
2226         struct be_dma_mem attribs_cmd;
2227
2228         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2229         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2230         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2231                                                 &attribs_cmd.dma);
2232         if (!attribs_cmd.va) {
2233                 dev_err(&adapter->pdev->dev,
2234                                 "Memory allocation failure\n");
2235                 return -ENOMEM;
2236         }
2237
2238         if (mutex_lock_interruptible(&adapter->mbox_lock))
2239                 return -1;
2240
2241         wrb = wrb_from_mbox(adapter);
2242         if (!wrb) {
2243                 status = -EBUSY;
2244                 goto err;
2245         }
2246         req = attribs_cmd.va;
2247
2248         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2249                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2250                         &attribs_cmd);
2251
2252         status = be_mbox_notify_wait(adapter);
2253         if (!status) {
2254                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2255                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2256         }
2257
2258 err:
2259         mutex_unlock(&adapter->mbox_lock);
2260         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2261                                         attribs_cmd.dma);
2262         return status;
2263 }
2264
2265 /* Uses mbox */
2266 int be_cmd_req_native_mode(struct be_adapter *adapter)
2267 {
2268         struct be_mcc_wrb *wrb;
2269         struct be_cmd_req_set_func_cap *req;
2270         int status;
2271
2272         if (mutex_lock_interruptible(&adapter->mbox_lock))
2273                 return -1;
2274
2275         wrb = wrb_from_mbox(adapter);
2276         if (!wrb) {
2277                 status = -EBUSY;
2278                 goto err;
2279         }
2280
2281         req = embedded_payload(wrb);
2282
2283         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2284                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2285
2286         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2287                                 CAPABILITY_BE3_NATIVE_ERX_API);
2288         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2289
2290         status = be_mbox_notify_wait(adapter);
2291         if (!status) {
2292                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2293                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2294                                         CAPABILITY_BE3_NATIVE_ERX_API;
2295         }
2296 err:
2297         mutex_unlock(&adapter->mbox_lock);
2298         return status;
2299 }
2300
2301 /* Uses synchronous MCCQ */
2302 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain,
2303                                                         u32 *pmac_id)
2304 {
2305         struct be_mcc_wrb *wrb;
2306         struct be_cmd_req_get_mac_list *req;
2307         int status;
2308         int mac_count;
2309
2310         spin_lock_bh(&adapter->mcc_lock);
2311
2312         wrb = wrb_from_mccq(adapter);
2313         if (!wrb) {
2314                 status = -EBUSY;
2315                 goto err;
2316         }
2317         req = embedded_payload(wrb);
2318
2319         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2320                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2321                                 wrb, NULL);
2322
2323         req->hdr.domain = domain;
2324
2325         status = be_mcc_notify_wait(adapter);
2326         if (!status) {
2327                 struct be_cmd_resp_get_mac_list *resp =
2328                                                 embedded_payload(wrb);
2329                 int i;
2330                 u8 *ctxt = &resp->context[0][0];
2331                 status = -EIO;
2332                 mac_count = resp->mac_count;
2333                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
2334                 for (i = 0; i < mac_count; i++) {
2335                         if (!AMAP_GET_BITS(struct amap_get_mac_list_context,
2336                                            act, ctxt)) {
2337                                 *pmac_id = AMAP_GET_BITS
2338                                         (struct amap_get_mac_list_context,
2339                                          macid, ctxt);
2340                                 status = 0;
2341                                 break;
2342                         }
2343                         ctxt += sizeof(struct amap_get_mac_list_context) / 8;
2344                 }
2345         }
2346
2347 err:
2348         spin_unlock_bh(&adapter->mcc_lock);
2349         return status;
2350 }
2351
2352 /* Uses synchronous MCCQ */
2353 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2354                         u8 mac_count, u32 domain)
2355 {
2356         struct be_mcc_wrb *wrb;
2357         struct be_cmd_req_set_mac_list *req;
2358         int status;
2359         struct be_dma_mem cmd;
2360
2361         memset(&cmd, 0, sizeof(struct be_dma_mem));
2362         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2363         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2364                         &cmd.dma, GFP_KERNEL);
2365         if (!cmd.va) {
2366                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2367                 return -ENOMEM;
2368         }
2369
2370         spin_lock_bh(&adapter->mcc_lock);
2371
2372         wrb = wrb_from_mccq(adapter);
2373         if (!wrb) {
2374                 status = -EBUSY;
2375                 goto err;
2376         }
2377
2378         req = cmd.va;
2379         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2380                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2381                                 wrb, &cmd);
2382
2383         req->hdr.domain = domain;
2384         req->mac_count = mac_count;
2385         if (mac_count)
2386                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2387
2388         status = be_mcc_notify_wait(adapter);
2389
2390 err:
2391         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2392                                 cmd.va, cmd.dma);
2393         spin_unlock_bh(&adapter->mcc_lock);
2394         return status;
2395 }