2 * Copyright (C) 2005 - 2014 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static struct be_cmd_priv_map cmd_priv_map[] = {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
30 OPCODE_COMMON_GET_FLOW_CONTROL,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
36 OPCODE_COMMON_SET_FLOW_CONTROL,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
42 OPCODE_ETH_GET_PPORT_STATS,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
48 OPCODE_COMMON_GET_PHY_DETAILS,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
58 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
59 u32 cmd_privileges = adapter->cmd_privileges;
61 for (i = 0; i < num_entries; i++)
62 if (opcode == cmd_priv_map[i].opcode &&
63 subsystem == cmd_priv_map[i].subsystem)
64 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
70 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
72 return wrb->payload.embedded_payload;
75 static void be_mcc_notify(struct be_adapter *adapter)
77 struct be_queue_info *mccq = &adapter->mcc_obj.q;
80 if (be_error(adapter))
83 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
84 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
87 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
90 /* To check if valid bit is set, check the entire word as we don't know
91 * the endianness of the data (old entry is host endian while a new entry is
93 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
97 if (compl->flags != 0) {
98 flags = le32_to_cpu(compl->flags);
99 if (flags & CQE_FLAGS_VALID_MASK) {
100 compl->flags = flags;
107 /* Need to reset the entire word that houses the valid bit */
108 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
113 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
118 addr = ((addr << 16) << 16) | tag0;
122 static int be_mcc_compl_process(struct be_adapter *adapter,
123 struct be_mcc_compl *compl)
125 u16 compl_status, extd_status;
126 struct be_cmd_resp_hdr *resp_hdr;
127 u8 opcode = 0, subsystem = 0;
129 /* Just swap the status to host endian; mcc tag is opaquely copied
131 be_dws_le_to_cpu(compl, 4);
133 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
134 CQE_STATUS_COMPL_MASK;
136 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
139 opcode = resp_hdr->opcode;
140 subsystem = resp_hdr->subsystem;
143 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
144 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
145 complete(&adapter->et_cmd_compl);
149 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
150 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
151 (subsystem == CMD_SUBSYSTEM_COMMON)) {
152 adapter->flash_status = compl_status;
153 complete(&adapter->et_cmd_compl);
156 if (compl_status == MCC_STATUS_SUCCESS) {
157 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
158 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
159 (subsystem == CMD_SUBSYSTEM_ETH)) {
160 be_parse_stats(adapter);
161 adapter->stats_cmd_sent = false;
163 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
164 subsystem == CMD_SUBSYSTEM_COMMON) {
165 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
167 adapter->drv_stats.be_on_die_temperature =
168 resp->on_die_temperature;
171 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
172 adapter->be_get_temp_freq = 0;
174 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
175 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
178 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
179 dev_warn(&adapter->pdev->dev,
180 "VF is not privileged to issue opcode %d-%d\n",
183 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
184 CQE_STATUS_EXTD_MASK;
185 dev_err(&adapter->pdev->dev,
186 "opcode %d-%d failed:status %d-%d\n",
187 opcode, subsystem, compl_status, extd_status);
189 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
197 /* Link state evt is a string of bytes; no need for endian swapping */
198 static void be_async_link_state_process(struct be_adapter *adapter,
199 struct be_async_event_link_state *evt)
201 /* When link status changes, link speed must be re-queried from FW */
202 adapter->phy.link_speed = -1;
204 /* On BEx the FW does not send a separate link status
205 * notification for physical and logical link.
206 * On other chips just process the logical link
207 * status notification
209 if (!BEx_chip(adapter) &&
210 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
213 /* For the initial link status do not rely on the ASYNC event as
214 * it may not be received in some cases.
216 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
217 be_link_status_update(adapter,
218 evt->port_link_status & LINK_STATUS_MASK);
221 /* Grp5 CoS Priority evt */
222 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
224 be_async_event_grp5_cos_priority
228 adapter->vlan_prio_bmap = evt->available_priority_bmap;
229 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
230 adapter->recommended_prio =
231 evt->reco_default_priority << VLAN_PRIO_SHIFT;
235 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
236 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
238 be_async_event_grp5_qos_link_speed
241 if (adapter->phy.link_speed >= 0 &&
242 evt->physical_port == adapter->port_num)
243 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
247 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
249 be_async_event_grp5_pvid_state
253 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
254 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
260 static void be_async_grp5_evt_process(struct be_adapter *adapter,
261 u32 trailer, struct be_mcc_compl *evt)
265 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
266 ASYNC_TRAILER_EVENT_TYPE_MASK;
268 switch (event_type) {
269 case ASYNC_EVENT_COS_PRIORITY:
270 be_async_grp5_cos_priority_process(adapter,
271 (struct be_async_event_grp5_cos_priority *)evt);
273 case ASYNC_EVENT_QOS_SPEED:
274 be_async_grp5_qos_speed_process(adapter,
275 (struct be_async_event_grp5_qos_link_speed *)evt);
277 case ASYNC_EVENT_PVID_STATE:
278 be_async_grp5_pvid_state_process(adapter,
279 (struct be_async_event_grp5_pvid_state *)evt);
282 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
288 static void be_async_dbg_evt_process(struct be_adapter *adapter,
289 u32 trailer, struct be_mcc_compl *cmp)
292 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
294 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
295 ASYNC_TRAILER_EVENT_TYPE_MASK;
297 switch (event_type) {
298 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
300 adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
301 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
304 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
310 static inline bool is_link_state_evt(u32 trailer)
312 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
313 ASYNC_TRAILER_EVENT_CODE_MASK) ==
314 ASYNC_EVENT_CODE_LINK_STATE;
317 static inline bool is_grp5_evt(u32 trailer)
319 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
320 ASYNC_TRAILER_EVENT_CODE_MASK) ==
321 ASYNC_EVENT_CODE_GRP_5);
324 static inline bool is_dbg_evt(u32 trailer)
326 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
327 ASYNC_TRAILER_EVENT_CODE_MASK) ==
328 ASYNC_EVENT_CODE_QNQ);
331 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
333 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
334 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
336 if (be_mcc_compl_is_new(compl)) {
337 queue_tail_inc(mcc_cq);
343 void be_async_mcc_enable(struct be_adapter *adapter)
345 spin_lock_bh(&adapter->mcc_cq_lock);
347 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
348 adapter->mcc_obj.rearm_cq = true;
350 spin_unlock_bh(&adapter->mcc_cq_lock);
353 void be_async_mcc_disable(struct be_adapter *adapter)
355 spin_lock_bh(&adapter->mcc_cq_lock);
357 adapter->mcc_obj.rearm_cq = false;
358 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
360 spin_unlock_bh(&adapter->mcc_cq_lock);
363 int be_process_mcc(struct be_adapter *adapter)
365 struct be_mcc_compl *compl;
366 int num = 0, status = 0;
367 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
369 spin_lock(&adapter->mcc_cq_lock);
370 while ((compl = be_mcc_compl_get(adapter))) {
371 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
372 /* Interpret flags as an async trailer */
373 if (is_link_state_evt(compl->flags))
374 be_async_link_state_process(adapter,
375 (struct be_async_event_link_state *) compl);
376 else if (is_grp5_evt(compl->flags))
377 be_async_grp5_evt_process(adapter,
378 compl->flags, compl);
379 else if (is_dbg_evt(compl->flags))
380 be_async_dbg_evt_process(adapter,
381 compl->flags, compl);
382 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
383 status = be_mcc_compl_process(adapter, compl);
384 atomic_dec(&mcc_obj->q.used);
386 be_mcc_compl_use(compl);
391 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
393 spin_unlock(&adapter->mcc_cq_lock);
397 /* Wait till no more pending mcc requests are present */
398 static int be_mcc_wait_compl(struct be_adapter *adapter)
400 #define mcc_timeout 120000 /* 12s timeout */
402 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
404 for (i = 0; i < mcc_timeout; i++) {
405 if (be_error(adapter))
409 status = be_process_mcc(adapter);
412 if (atomic_read(&mcc_obj->q.used) == 0)
416 if (i == mcc_timeout) {
417 dev_err(&adapter->pdev->dev, "FW not responding\n");
418 adapter->fw_timeout = true;
424 /* Notify MCC requests and wait for completion */
425 static int be_mcc_notify_wait(struct be_adapter *adapter)
428 struct be_mcc_wrb *wrb;
429 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
430 u16 index = mcc_obj->q.head;
431 struct be_cmd_resp_hdr *resp;
433 index_dec(&index, mcc_obj->q.len);
434 wrb = queue_index_node(&mcc_obj->q, index);
436 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
438 be_mcc_notify(adapter);
440 status = be_mcc_wait_compl(adapter);
444 status = resp->status;
449 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
455 if (be_error(adapter))
458 ready = ioread32(db);
459 if (ready == 0xffffffff)
462 ready &= MPU_MAILBOX_DB_RDY_MASK;
467 dev_err(&adapter->pdev->dev, "FW not responding\n");
468 adapter->fw_timeout = true;
469 be_detect_error(adapter);
481 * Insert the mailbox address into the doorbell in two steps
482 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
484 static int be_mbox_notify_wait(struct be_adapter *adapter)
488 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
489 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
490 struct be_mcc_mailbox *mbox = mbox_mem->va;
491 struct be_mcc_compl *compl = &mbox->compl;
493 /* wait for ready to be set */
494 status = be_mbox_db_ready_wait(adapter, db);
498 val |= MPU_MAILBOX_DB_HI_MASK;
499 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
500 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
503 /* wait for ready to be set */
504 status = be_mbox_db_ready_wait(adapter, db);
509 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
510 val |= (u32)(mbox_mem->dma >> 4) << 2;
513 status = be_mbox_db_ready_wait(adapter, db);
517 /* A cq entry has been made now */
518 if (be_mcc_compl_is_new(compl)) {
519 status = be_mcc_compl_process(adapter, &mbox->compl);
520 be_mcc_compl_use(compl);
524 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
530 static u16 be_POST_stage_get(struct be_adapter *adapter)
534 if (BEx_chip(adapter))
535 sem = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
537 pci_read_config_dword(adapter->pdev,
538 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
540 return sem & POST_STAGE_MASK;
543 static int lancer_wait_ready(struct be_adapter *adapter)
545 #define SLIPORT_READY_TIMEOUT 30
549 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
550 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
551 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
557 if (i == SLIPORT_READY_TIMEOUT)
563 static bool lancer_provisioning_error(struct be_adapter *adapter)
565 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
566 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
567 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
568 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
569 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
571 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
572 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
578 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
581 u32 sliport_status, err, reset_needed;
584 resource_error = lancer_provisioning_error(adapter);
588 status = lancer_wait_ready(adapter);
590 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
591 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
592 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
593 if (err && reset_needed) {
594 iowrite32(SLI_PORT_CONTROL_IP_MASK,
595 adapter->db + SLIPORT_CONTROL_OFFSET);
597 /* check adapter has corrected the error */
598 status = lancer_wait_ready(adapter);
599 sliport_status = ioread32(adapter->db +
600 SLIPORT_STATUS_OFFSET);
601 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
602 SLIPORT_STATUS_RN_MASK);
603 if (status || sliport_status)
605 } else if (err || reset_needed) {
609 /* Stop error recovery if error is not recoverable.
610 * No resource error is temporary errors and will go away
611 * when PF provisions resources.
613 resource_error = lancer_provisioning_error(adapter);
620 int be_fw_wait_ready(struct be_adapter *adapter)
623 int status, timeout = 0;
624 struct device *dev = &adapter->pdev->dev;
626 if (lancer_chip(adapter)) {
627 status = lancer_wait_ready(adapter);
632 stage = be_POST_stage_get(adapter);
633 if (stage == POST_STAGE_ARMFW_RDY)
636 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
637 if (msleep_interruptible(2000)) {
638 dev_err(dev, "Waiting for POST aborted\n");
642 } while (timeout < 60);
644 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
649 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
651 return &wrb->payload.sgl[0];
654 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
656 wrb->tag0 = addr & 0xFFFFFFFF;
657 wrb->tag1 = upper_32_bits(addr);
660 /* Don't touch the hdr after it's prepared */
661 /* mem will be NULL for embedded commands */
662 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
663 u8 subsystem, u8 opcode, int cmd_len,
664 struct be_mcc_wrb *wrb,
665 struct be_dma_mem *mem)
669 req_hdr->opcode = opcode;
670 req_hdr->subsystem = subsystem;
671 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
672 req_hdr->version = 0;
673 fill_wrb_tags(wrb, (ulong) req_hdr);
674 wrb->payload_length = cmd_len;
676 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
677 MCC_WRB_SGE_CNT_SHIFT;
678 sge = nonembedded_sgl(wrb);
679 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
680 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
681 sge->len = cpu_to_le32(mem->size);
683 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
684 be_dws_cpu_to_le(wrb, 8);
687 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
688 struct be_dma_mem *mem)
690 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
691 u64 dma = (u64)mem->dma;
693 for (i = 0; i < buf_pages; i++) {
694 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
695 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
700 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
702 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
703 struct be_mcc_wrb *wrb
704 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
705 memset(wrb, 0, sizeof(*wrb));
709 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
711 struct be_queue_info *mccq = &adapter->mcc_obj.q;
712 struct be_mcc_wrb *wrb;
717 if (atomic_read(&mccq->used) >= mccq->len)
720 wrb = queue_head_node(mccq);
721 queue_head_inc(mccq);
722 atomic_inc(&mccq->used);
723 memset(wrb, 0, sizeof(*wrb));
727 static bool use_mcc(struct be_adapter *adapter)
729 return adapter->mcc_obj.q.created;
732 /* Must be used only in process context */
733 static int be_cmd_lock(struct be_adapter *adapter)
735 if (use_mcc(adapter)) {
736 spin_lock_bh(&adapter->mcc_lock);
739 return mutex_lock_interruptible(&adapter->mbox_lock);
743 /* Must be used only in process context */
744 static void be_cmd_unlock(struct be_adapter *adapter)
746 if (use_mcc(adapter))
747 spin_unlock_bh(&adapter->mcc_lock);
749 return mutex_unlock(&adapter->mbox_lock);
752 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
753 struct be_mcc_wrb *wrb)
755 struct be_mcc_wrb *dest_wrb;
757 if (use_mcc(adapter)) {
758 dest_wrb = wrb_from_mccq(adapter);
762 dest_wrb = wrb_from_mbox(adapter);
765 memcpy(dest_wrb, wrb, sizeof(*wrb));
766 if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
767 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
772 /* Must be used only in process context */
773 static int be_cmd_notify_wait(struct be_adapter *adapter,
774 struct be_mcc_wrb *wrb)
776 struct be_mcc_wrb *dest_wrb;
779 status = be_cmd_lock(adapter);
783 dest_wrb = be_cmd_copy(adapter, wrb);
787 if (use_mcc(adapter))
788 status = be_mcc_notify_wait(adapter);
790 status = be_mbox_notify_wait(adapter);
793 memcpy(wrb, dest_wrb, sizeof(*wrb));
795 be_cmd_unlock(adapter);
799 /* Tell fw we're about to start firing cmds by writing a
800 * special pattern across the wrb hdr; uses mbox
802 int be_cmd_fw_init(struct be_adapter *adapter)
807 if (lancer_chip(adapter))
810 if (mutex_lock_interruptible(&adapter->mbox_lock))
813 wrb = (u8 *)wrb_from_mbox(adapter);
823 status = be_mbox_notify_wait(adapter);
825 mutex_unlock(&adapter->mbox_lock);
829 /* Tell fw we're done with firing cmds by writing a
830 * special pattern across the wrb hdr; uses mbox
832 int be_cmd_fw_clean(struct be_adapter *adapter)
837 if (lancer_chip(adapter))
840 if (mutex_lock_interruptible(&adapter->mbox_lock))
843 wrb = (u8 *)wrb_from_mbox(adapter);
853 status = be_mbox_notify_wait(adapter);
855 mutex_unlock(&adapter->mbox_lock);
859 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
861 struct be_mcc_wrb *wrb;
862 struct be_cmd_req_eq_create *req;
863 struct be_dma_mem *q_mem = &eqo->q.dma_mem;
866 if (mutex_lock_interruptible(&adapter->mbox_lock))
869 wrb = wrb_from_mbox(adapter);
870 req = embedded_payload(wrb);
872 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
873 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
876 /* Support for EQ_CREATEv2 available only SH-R onwards */
877 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
880 req->hdr.version = ver;
881 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
883 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
885 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
886 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
887 __ilog2_u32(eqo->q.len / 256));
888 be_dws_cpu_to_le(req->context, sizeof(req->context));
890 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
892 status = be_mbox_notify_wait(adapter);
894 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
895 eqo->q.id = le16_to_cpu(resp->eq_id);
897 (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
898 eqo->q.created = true;
901 mutex_unlock(&adapter->mbox_lock);
906 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
907 bool permanent, u32 if_handle, u32 pmac_id)
909 struct be_mcc_wrb *wrb;
910 struct be_cmd_req_mac_query *req;
913 spin_lock_bh(&adapter->mcc_lock);
915 wrb = wrb_from_mccq(adapter);
920 req = embedded_payload(wrb);
922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
923 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
925 req->type = MAC_ADDRESS_TYPE_NETWORK;
929 req->if_id = cpu_to_le16((u16) if_handle);
930 req->pmac_id = cpu_to_le32(pmac_id);
934 status = be_mcc_notify_wait(adapter);
936 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
937 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
941 spin_unlock_bh(&adapter->mcc_lock);
945 /* Uses synchronous MCCQ */
946 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
947 u32 if_id, u32 *pmac_id, u32 domain)
949 struct be_mcc_wrb *wrb;
950 struct be_cmd_req_pmac_add *req;
953 spin_lock_bh(&adapter->mcc_lock);
955 wrb = wrb_from_mccq(adapter);
960 req = embedded_payload(wrb);
962 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
963 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
966 req->hdr.domain = domain;
967 req->if_id = cpu_to_le32(if_id);
968 memcpy(req->mac_address, mac_addr, ETH_ALEN);
970 status = be_mcc_notify_wait(adapter);
972 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
973 *pmac_id = le32_to_cpu(resp->pmac_id);
977 spin_unlock_bh(&adapter->mcc_lock);
979 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
985 /* Uses synchronous MCCQ */
986 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
988 struct be_mcc_wrb *wrb;
989 struct be_cmd_req_pmac_del *req;
995 spin_lock_bh(&adapter->mcc_lock);
997 wrb = wrb_from_mccq(adapter);
1002 req = embedded_payload(wrb);
1004 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1005 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
1007 req->hdr.domain = dom;
1008 req->if_id = cpu_to_le32(if_id);
1009 req->pmac_id = cpu_to_le32(pmac_id);
1011 status = be_mcc_notify_wait(adapter);
1014 spin_unlock_bh(&adapter->mcc_lock);
1019 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1020 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1022 struct be_mcc_wrb *wrb;
1023 struct be_cmd_req_cq_create *req;
1024 struct be_dma_mem *q_mem = &cq->dma_mem;
1028 if (mutex_lock_interruptible(&adapter->mbox_lock))
1031 wrb = wrb_from_mbox(adapter);
1032 req = embedded_payload(wrb);
1033 ctxt = &req->context;
1035 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1036 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1039 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1041 if (BEx_chip(adapter)) {
1042 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1044 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1046 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1047 __ilog2_u32(cq->len / 256));
1048 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1049 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1050 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1052 req->hdr.version = 2;
1053 req->page_size = 1; /* 1 for 4K */
1055 /* coalesce-wm field in this cmd is not relevant to Lancer.
1056 * Lancer uses COMMON_MODIFY_CQ to set this field
1058 if (!lancer_chip(adapter))
1059 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1061 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1063 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1064 __ilog2_u32(cq->len / 256));
1065 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1066 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1067 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1070 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1072 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1074 status = be_mbox_notify_wait(adapter);
1076 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1077 cq->id = le16_to_cpu(resp->cq_id);
1081 mutex_unlock(&adapter->mbox_lock);
1086 static u32 be_encoded_q_len(int q_len)
1088 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1089 if (len_encoded == 16)
1094 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1095 struct be_queue_info *mccq,
1096 struct be_queue_info *cq)
1098 struct be_mcc_wrb *wrb;
1099 struct be_cmd_req_mcc_ext_create *req;
1100 struct be_dma_mem *q_mem = &mccq->dma_mem;
1104 if (mutex_lock_interruptible(&adapter->mbox_lock))
1107 wrb = wrb_from_mbox(adapter);
1108 req = embedded_payload(wrb);
1109 ctxt = &req->context;
1111 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1112 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1115 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1116 if (BEx_chip(adapter)) {
1117 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1118 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1119 be_encoded_q_len(mccq->len));
1120 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1122 req->hdr.version = 1;
1123 req->cq_id = cpu_to_le16(cq->id);
1125 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1126 be_encoded_q_len(mccq->len));
1127 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1128 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1130 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1134 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1135 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1136 req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1137 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1139 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1141 status = be_mbox_notify_wait(adapter);
1143 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1144 mccq->id = le16_to_cpu(resp->id);
1145 mccq->created = true;
1147 mutex_unlock(&adapter->mbox_lock);
1152 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1153 struct be_queue_info *mccq,
1154 struct be_queue_info *cq)
1156 struct be_mcc_wrb *wrb;
1157 struct be_cmd_req_mcc_create *req;
1158 struct be_dma_mem *q_mem = &mccq->dma_mem;
1162 if (mutex_lock_interruptible(&adapter->mbox_lock))
1165 wrb = wrb_from_mbox(adapter);
1166 req = embedded_payload(wrb);
1167 ctxt = &req->context;
1169 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1170 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1173 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1175 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1176 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1177 be_encoded_q_len(mccq->len));
1178 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1180 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1182 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1184 status = be_mbox_notify_wait(adapter);
1186 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1187 mccq->id = le16_to_cpu(resp->id);
1188 mccq->created = true;
1191 mutex_unlock(&adapter->mbox_lock);
1195 int be_cmd_mccq_create(struct be_adapter *adapter,
1196 struct be_queue_info *mccq, struct be_queue_info *cq)
1200 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1201 if (status && BEx_chip(adapter)) {
1202 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1203 "or newer to avoid conflicting priorities between NIC "
1204 "and FCoE traffic");
1205 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1210 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1212 struct be_mcc_wrb wrb = {0};
1213 struct be_cmd_req_eth_tx_create *req;
1214 struct be_queue_info *txq = &txo->q;
1215 struct be_queue_info *cq = &txo->cq;
1216 struct be_dma_mem *q_mem = &txq->dma_mem;
1217 int status, ver = 0;
1219 req = embedded_payload(&wrb);
1220 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1221 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1223 if (lancer_chip(adapter)) {
1224 req->hdr.version = 1;
1225 } else if (BEx_chip(adapter)) {
1226 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1227 req->hdr.version = 2;
1228 } else { /* For SH */
1229 req->hdr.version = 2;
1232 if (req->hdr.version > 0)
1233 req->if_id = cpu_to_le16(adapter->if_handle);
1234 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1235 req->ulp_num = BE_ULP1_NUM;
1236 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1237 req->cq_id = cpu_to_le16(cq->id);
1238 req->queue_size = be_encoded_q_len(txq->len);
1239 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1240 ver = req->hdr.version;
1242 status = be_cmd_notify_wait(adapter, &wrb);
1244 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1245 txq->id = le16_to_cpu(resp->cid);
1247 txo->db_offset = le32_to_cpu(resp->db_offset);
1249 txo->db_offset = DB_TXULP1_OFFSET;
1250 txq->created = true;
1257 int be_cmd_rxq_create(struct be_adapter *adapter,
1258 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1259 u32 if_id, u32 rss, u8 *rss_id)
1261 struct be_mcc_wrb *wrb;
1262 struct be_cmd_req_eth_rx_create *req;
1263 struct be_dma_mem *q_mem = &rxq->dma_mem;
1266 spin_lock_bh(&adapter->mcc_lock);
1268 wrb = wrb_from_mccq(adapter);
1273 req = embedded_payload(wrb);
1275 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1276 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1278 req->cq_id = cpu_to_le16(cq_id);
1279 req->frag_size = fls(frag_size) - 1;
1281 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1282 req->interface_id = cpu_to_le32(if_id);
1283 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1284 req->rss_queue = cpu_to_le32(rss);
1286 status = be_mcc_notify_wait(adapter);
1288 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1289 rxq->id = le16_to_cpu(resp->id);
1290 rxq->created = true;
1291 *rss_id = resp->rss_id;
1295 spin_unlock_bh(&adapter->mcc_lock);
1299 /* Generic destroyer function for all types of queues
1302 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1305 struct be_mcc_wrb *wrb;
1306 struct be_cmd_req_q_destroy *req;
1307 u8 subsys = 0, opcode = 0;
1310 if (mutex_lock_interruptible(&adapter->mbox_lock))
1313 wrb = wrb_from_mbox(adapter);
1314 req = embedded_payload(wrb);
1316 switch (queue_type) {
1318 subsys = CMD_SUBSYSTEM_COMMON;
1319 opcode = OPCODE_COMMON_EQ_DESTROY;
1322 subsys = CMD_SUBSYSTEM_COMMON;
1323 opcode = OPCODE_COMMON_CQ_DESTROY;
1326 subsys = CMD_SUBSYSTEM_ETH;
1327 opcode = OPCODE_ETH_TX_DESTROY;
1330 subsys = CMD_SUBSYSTEM_ETH;
1331 opcode = OPCODE_ETH_RX_DESTROY;
1334 subsys = CMD_SUBSYSTEM_COMMON;
1335 opcode = OPCODE_COMMON_MCC_DESTROY;
1341 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1343 req->id = cpu_to_le16(q->id);
1345 status = be_mbox_notify_wait(adapter);
1348 mutex_unlock(&adapter->mbox_lock);
1353 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1355 struct be_mcc_wrb *wrb;
1356 struct be_cmd_req_q_destroy *req;
1359 spin_lock_bh(&adapter->mcc_lock);
1361 wrb = wrb_from_mccq(adapter);
1366 req = embedded_payload(wrb);
1368 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1369 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1370 req->id = cpu_to_le16(q->id);
1372 status = be_mcc_notify_wait(adapter);
1376 spin_unlock_bh(&adapter->mcc_lock);
1380 /* Create an rx filtering policy configuration on an i/f
1381 * Will use MBOX only if MCCQ has not been created.
1383 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1384 u32 *if_handle, u32 domain)
1386 struct be_mcc_wrb wrb = {0};
1387 struct be_cmd_req_if_create *req;
1390 req = embedded_payload(&wrb);
1391 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1392 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1393 sizeof(*req), &wrb, NULL);
1394 req->hdr.domain = domain;
1395 req->capability_flags = cpu_to_le32(cap_flags);
1396 req->enable_flags = cpu_to_le32(en_flags);
1397 req->pmac_invalid = true;
1399 status = be_cmd_notify_wait(adapter, &wrb);
1401 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1402 *if_handle = le32_to_cpu(resp->interface_id);
1404 /* Hack to retrieve VF's pmac-id on BE3 */
1405 if (BE3_chip(adapter) && !be_physfn(adapter))
1406 adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1412 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1414 struct be_mcc_wrb *wrb;
1415 struct be_cmd_req_if_destroy *req;
1418 if (interface_id == -1)
1421 spin_lock_bh(&adapter->mcc_lock);
1423 wrb = wrb_from_mccq(adapter);
1428 req = embedded_payload(wrb);
1430 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1431 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1432 sizeof(*req), wrb, NULL);
1433 req->hdr.domain = domain;
1434 req->interface_id = cpu_to_le32(interface_id);
1436 status = be_mcc_notify_wait(adapter);
1438 spin_unlock_bh(&adapter->mcc_lock);
1442 /* Get stats is a non embedded command: the request is not embedded inside
1443 * WRB but is a separate dma memory block
1444 * Uses asynchronous MCC
1446 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1448 struct be_mcc_wrb *wrb;
1449 struct be_cmd_req_hdr *hdr;
1452 spin_lock_bh(&adapter->mcc_lock);
1454 wrb = wrb_from_mccq(adapter);
1459 hdr = nonemb_cmd->va;
1461 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1462 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1465 /* version 1 of the cmd is not supported only by BE2 */
1466 if (BE2_chip(adapter))
1468 if (BE3_chip(adapter) || lancer_chip(adapter))
1473 be_mcc_notify(adapter);
1474 adapter->stats_cmd_sent = true;
1477 spin_unlock_bh(&adapter->mcc_lock);
1482 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1483 struct be_dma_mem *nonemb_cmd)
1486 struct be_mcc_wrb *wrb;
1487 struct lancer_cmd_req_pport_stats *req;
1490 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1494 spin_lock_bh(&adapter->mcc_lock);
1496 wrb = wrb_from_mccq(adapter);
1501 req = nonemb_cmd->va;
1503 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1504 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1507 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1508 req->cmd_params.params.reset_stats = 0;
1510 be_mcc_notify(adapter);
1511 adapter->stats_cmd_sent = true;
1514 spin_unlock_bh(&adapter->mcc_lock);
1518 static int be_mac_to_link_speed(int mac_speed)
1520 switch (mac_speed) {
1521 case PHY_LINK_SPEED_ZERO:
1523 case PHY_LINK_SPEED_10MBPS:
1525 case PHY_LINK_SPEED_100MBPS:
1527 case PHY_LINK_SPEED_1GBPS:
1529 case PHY_LINK_SPEED_10GBPS:
1531 case PHY_LINK_SPEED_20GBPS:
1533 case PHY_LINK_SPEED_25GBPS:
1535 case PHY_LINK_SPEED_40GBPS:
1541 /* Uses synchronous mcc
1542 * Returns link_speed in Mbps
1544 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1545 u8 *link_status, u32 dom)
1547 struct be_mcc_wrb *wrb;
1548 struct be_cmd_req_link_status *req;
1551 spin_lock_bh(&adapter->mcc_lock);
1554 *link_status = LINK_DOWN;
1556 wrb = wrb_from_mccq(adapter);
1561 req = embedded_payload(wrb);
1563 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1564 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1565 sizeof(*req), wrb, NULL);
1567 /* version 1 of the cmd is not supported only by BE2 */
1568 if (!BE2_chip(adapter))
1569 req->hdr.version = 1;
1571 req->hdr.domain = dom;
1573 status = be_mcc_notify_wait(adapter);
1575 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1577 *link_speed = resp->link_speed ?
1578 le16_to_cpu(resp->link_speed) * 10 :
1579 be_mac_to_link_speed(resp->mac_speed);
1581 if (!resp->logical_link_status)
1585 *link_status = resp->logical_link_status;
1589 spin_unlock_bh(&adapter->mcc_lock);
1593 /* Uses synchronous mcc */
1594 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1596 struct be_mcc_wrb *wrb;
1597 struct be_cmd_req_get_cntl_addnl_attribs *req;
1600 spin_lock_bh(&adapter->mcc_lock);
1602 wrb = wrb_from_mccq(adapter);
1607 req = embedded_payload(wrb);
1609 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1610 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1611 sizeof(*req), wrb, NULL);
1613 be_mcc_notify(adapter);
1616 spin_unlock_bh(&adapter->mcc_lock);
1620 /* Uses synchronous mcc */
1621 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1623 struct be_mcc_wrb *wrb;
1624 struct be_cmd_req_get_fat *req;
1627 spin_lock_bh(&adapter->mcc_lock);
1629 wrb = wrb_from_mccq(adapter);
1634 req = embedded_payload(wrb);
1636 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1637 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1639 req->fat_operation = cpu_to_le32(QUERY_FAT);
1640 status = be_mcc_notify_wait(adapter);
1642 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1643 if (log_size && resp->log_size)
1644 *log_size = le32_to_cpu(resp->log_size) -
1648 spin_unlock_bh(&adapter->mcc_lock);
1652 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1654 struct be_dma_mem get_fat_cmd;
1655 struct be_mcc_wrb *wrb;
1656 struct be_cmd_req_get_fat *req;
1657 u32 offset = 0, total_size, buf_size,
1658 log_offset = sizeof(u32), payload_len;
1664 total_size = buf_len;
1666 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1667 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1670 if (!get_fat_cmd.va) {
1672 dev_err(&adapter->pdev->dev,
1673 "Memory allocation failure while retrieving FAT data\n");
1677 spin_lock_bh(&adapter->mcc_lock);
1679 while (total_size) {
1680 buf_size = min(total_size, (u32)60*1024);
1681 total_size -= buf_size;
1683 wrb = wrb_from_mccq(adapter);
1688 req = get_fat_cmd.va;
1690 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1691 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1692 OPCODE_COMMON_MANAGE_FAT, payload_len,
1695 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1696 req->read_log_offset = cpu_to_le32(log_offset);
1697 req->read_log_length = cpu_to_le32(buf_size);
1698 req->data_buffer_size = cpu_to_le32(buf_size);
1700 status = be_mcc_notify_wait(adapter);
1702 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1703 memcpy(buf + offset,
1705 le32_to_cpu(resp->read_log_length));
1707 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1711 log_offset += buf_size;
1714 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1715 get_fat_cmd.va, get_fat_cmd.dma);
1716 spin_unlock_bh(&adapter->mcc_lock);
1719 /* Uses synchronous mcc */
1720 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1723 struct be_mcc_wrb *wrb;
1724 struct be_cmd_req_get_fw_version *req;
1727 spin_lock_bh(&adapter->mcc_lock);
1729 wrb = wrb_from_mccq(adapter);
1735 req = embedded_payload(wrb);
1737 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1738 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1740 status = be_mcc_notify_wait(adapter);
1742 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1743 strcpy(fw_ver, resp->firmware_version_string);
1745 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1748 spin_unlock_bh(&adapter->mcc_lock);
1752 /* set the EQ delay interval of an EQ to specified value
1755 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1758 struct be_mcc_wrb *wrb;
1759 struct be_cmd_req_modify_eq_delay *req;
1762 spin_lock_bh(&adapter->mcc_lock);
1764 wrb = wrb_from_mccq(adapter);
1769 req = embedded_payload(wrb);
1771 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1772 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1775 req->num_eq = cpu_to_le32(num);
1776 for (i = 0; i < num; i++) {
1777 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1778 req->set_eqd[i].phase = 0;
1779 req->set_eqd[i].delay_multiplier =
1780 cpu_to_le32(set_eqd[i].delay_multiplier);
1783 be_mcc_notify(adapter);
1785 spin_unlock_bh(&adapter->mcc_lock);
1789 /* Uses sycnhronous mcc */
1790 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1793 struct be_mcc_wrb *wrb;
1794 struct be_cmd_req_vlan_config *req;
1797 spin_lock_bh(&adapter->mcc_lock);
1799 wrb = wrb_from_mccq(adapter);
1804 req = embedded_payload(wrb);
1806 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1807 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1810 req->interface_id = if_id;
1811 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1812 req->num_vlan = num;
1813 memcpy(req->normal_vlan, vtag_array,
1814 req->num_vlan * sizeof(vtag_array[0]));
1816 status = be_mcc_notify_wait(adapter);
1818 spin_unlock_bh(&adapter->mcc_lock);
1822 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1824 struct be_mcc_wrb *wrb;
1825 struct be_dma_mem *mem = &adapter->rx_filter;
1826 struct be_cmd_req_rx_filter *req = mem->va;
1829 spin_lock_bh(&adapter->mcc_lock);
1831 wrb = wrb_from_mccq(adapter);
1836 memset(req, 0, sizeof(*req));
1837 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1838 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1841 req->if_id = cpu_to_le32(adapter->if_handle);
1842 if (flags & IFF_PROMISC) {
1843 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1844 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1845 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1848 cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1849 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1850 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1851 } else if (flags & IFF_ALLMULTI) {
1852 req->if_flags_mask = req->if_flags =
1853 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1854 } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1855 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1859 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1861 struct netdev_hw_addr *ha;
1864 req->if_flags_mask = req->if_flags =
1865 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1867 /* Reset mcast promisc mode if already set by setting mask
1868 * and not setting flags field
1870 req->if_flags_mask |=
1871 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1872 be_if_cap_flags(adapter));
1873 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1874 netdev_for_each_mc_addr(ha, adapter->netdev)
1875 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1878 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1879 req->if_flags_mask) {
1880 dev_warn(&adapter->pdev->dev,
1881 "Cannot set rx filter flags 0x%x\n",
1882 req->if_flags_mask);
1883 dev_warn(&adapter->pdev->dev,
1884 "Interface is capable of 0x%x flags only\n",
1885 be_if_cap_flags(adapter));
1887 req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1889 status = be_mcc_notify_wait(adapter);
1892 spin_unlock_bh(&adapter->mcc_lock);
1896 /* Uses synchrounous mcc */
1897 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1899 struct be_mcc_wrb *wrb;
1900 struct be_cmd_req_set_flow_control *req;
1903 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1904 CMD_SUBSYSTEM_COMMON))
1907 spin_lock_bh(&adapter->mcc_lock);
1909 wrb = wrb_from_mccq(adapter);
1914 req = embedded_payload(wrb);
1916 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1917 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1920 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1921 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1923 status = be_mcc_notify_wait(adapter);
1926 spin_unlock_bh(&adapter->mcc_lock);
1931 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1933 struct be_mcc_wrb *wrb;
1934 struct be_cmd_req_get_flow_control *req;
1937 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1938 CMD_SUBSYSTEM_COMMON))
1941 spin_lock_bh(&adapter->mcc_lock);
1943 wrb = wrb_from_mccq(adapter);
1948 req = embedded_payload(wrb);
1950 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1951 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
1954 status = be_mcc_notify_wait(adapter);
1956 struct be_cmd_resp_get_flow_control *resp =
1957 embedded_payload(wrb);
1958 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1959 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1963 spin_unlock_bh(&adapter->mcc_lock);
1968 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1969 u32 *mode, u32 *caps, u16 *asic_rev)
1971 struct be_mcc_wrb *wrb;
1972 struct be_cmd_req_query_fw_cfg *req;
1975 if (mutex_lock_interruptible(&adapter->mbox_lock))
1978 wrb = wrb_from_mbox(adapter);
1979 req = embedded_payload(wrb);
1981 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1982 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
1983 sizeof(*req), wrb, NULL);
1985 status = be_mbox_notify_wait(adapter);
1987 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1988 *port_num = le32_to_cpu(resp->phys_port);
1989 *mode = le32_to_cpu(resp->function_mode);
1990 *caps = le32_to_cpu(resp->function_caps);
1991 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1994 mutex_unlock(&adapter->mbox_lock);
1999 int be_cmd_reset_function(struct be_adapter *adapter)
2001 struct be_mcc_wrb *wrb;
2002 struct be_cmd_req_hdr *req;
2005 if (lancer_chip(adapter)) {
2006 status = lancer_wait_ready(adapter);
2008 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2009 adapter->db + SLIPORT_CONTROL_OFFSET);
2010 status = lancer_test_and_set_rdy_state(adapter);
2013 dev_err(&adapter->pdev->dev,
2014 "Adapter in non recoverable error\n");
2019 if (mutex_lock_interruptible(&adapter->mbox_lock))
2022 wrb = wrb_from_mbox(adapter);
2023 req = embedded_payload(wrb);
2025 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2026 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2029 status = be_mbox_notify_wait(adapter);
2031 mutex_unlock(&adapter->mbox_lock);
2035 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2036 u32 rss_hash_opts, u16 table_size, u8 *rss_hkey)
2038 struct be_mcc_wrb *wrb;
2039 struct be_cmd_req_rss_config *req;
2042 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2045 spin_lock_bh(&adapter->mcc_lock);
2047 wrb = wrb_from_mccq(adapter);
2052 req = embedded_payload(wrb);
2054 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2055 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2057 req->if_id = cpu_to_le32(adapter->if_handle);
2058 req->enable_rss = cpu_to_le16(rss_hash_opts);
2059 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2061 if (!BEx_chip(adapter))
2062 req->hdr.version = 1;
2064 memcpy(req->cpu_table, rsstable, table_size);
2065 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2066 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2068 status = be_mcc_notify_wait(adapter);
2070 spin_unlock_bh(&adapter->mcc_lock);
2075 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2076 u8 bcn, u8 sts, u8 state)
2078 struct be_mcc_wrb *wrb;
2079 struct be_cmd_req_enable_disable_beacon *req;
2082 spin_lock_bh(&adapter->mcc_lock);
2084 wrb = wrb_from_mccq(adapter);
2089 req = embedded_payload(wrb);
2091 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2092 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2093 sizeof(*req), wrb, NULL);
2095 req->port_num = port_num;
2096 req->beacon_state = state;
2097 req->beacon_duration = bcn;
2098 req->status_duration = sts;
2100 status = be_mcc_notify_wait(adapter);
2103 spin_unlock_bh(&adapter->mcc_lock);
2108 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2110 struct be_mcc_wrb *wrb;
2111 struct be_cmd_req_get_beacon_state *req;
2114 spin_lock_bh(&adapter->mcc_lock);
2116 wrb = wrb_from_mccq(adapter);
2121 req = embedded_payload(wrb);
2123 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2124 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2127 req->port_num = port_num;
2129 status = be_mcc_notify_wait(adapter);
2131 struct be_cmd_resp_get_beacon_state *resp =
2132 embedded_payload(wrb);
2133 *state = resp->beacon_state;
2137 spin_unlock_bh(&adapter->mcc_lock);
2141 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2142 u32 data_size, u32 data_offset,
2143 const char *obj_name, u32 *data_written,
2144 u8 *change_status, u8 *addn_status)
2146 struct be_mcc_wrb *wrb;
2147 struct lancer_cmd_req_write_object *req;
2148 struct lancer_cmd_resp_write_object *resp;
2152 spin_lock_bh(&adapter->mcc_lock);
2153 adapter->flash_status = 0;
2155 wrb = wrb_from_mccq(adapter);
2161 req = embedded_payload(wrb);
2163 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2164 OPCODE_COMMON_WRITE_OBJECT,
2165 sizeof(struct lancer_cmd_req_write_object), wrb,
2168 ctxt = &req->context;
2169 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2170 write_length, ctxt, data_size);
2173 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2176 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2179 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2180 req->write_offset = cpu_to_le32(data_offset);
2181 strcpy(req->object_name, obj_name);
2182 req->descriptor_count = cpu_to_le32(1);
2183 req->buf_len = cpu_to_le32(data_size);
2184 req->addr_low = cpu_to_le32((cmd->dma +
2185 sizeof(struct lancer_cmd_req_write_object))
2187 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2188 sizeof(struct lancer_cmd_req_write_object)));
2190 be_mcc_notify(adapter);
2191 spin_unlock_bh(&adapter->mcc_lock);
2193 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2194 msecs_to_jiffies(60000)))
2197 status = adapter->flash_status;
2199 resp = embedded_payload(wrb);
2201 *data_written = le32_to_cpu(resp->actual_write_len);
2202 *change_status = resp->change_status;
2204 *addn_status = resp->additional_status;
2210 spin_unlock_bh(&adapter->mcc_lock);
2214 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2215 u32 data_size, u32 data_offset, const char *obj_name,
2216 u32 *data_read, u32 *eof, u8 *addn_status)
2218 struct be_mcc_wrb *wrb;
2219 struct lancer_cmd_req_read_object *req;
2220 struct lancer_cmd_resp_read_object *resp;
2223 spin_lock_bh(&adapter->mcc_lock);
2225 wrb = wrb_from_mccq(adapter);
2231 req = embedded_payload(wrb);
2233 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2234 OPCODE_COMMON_READ_OBJECT,
2235 sizeof(struct lancer_cmd_req_read_object), wrb,
2238 req->desired_read_len = cpu_to_le32(data_size);
2239 req->read_offset = cpu_to_le32(data_offset);
2240 strcpy(req->object_name, obj_name);
2241 req->descriptor_count = cpu_to_le32(1);
2242 req->buf_len = cpu_to_le32(data_size);
2243 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2244 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2246 status = be_mcc_notify_wait(adapter);
2248 resp = embedded_payload(wrb);
2250 *data_read = le32_to_cpu(resp->actual_read_len);
2251 *eof = le32_to_cpu(resp->eof);
2253 *addn_status = resp->additional_status;
2257 spin_unlock_bh(&adapter->mcc_lock);
2261 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2262 u32 flash_type, u32 flash_opcode, u32 buf_size)
2264 struct be_mcc_wrb *wrb;
2265 struct be_cmd_write_flashrom *req;
2268 spin_lock_bh(&adapter->mcc_lock);
2269 adapter->flash_status = 0;
2271 wrb = wrb_from_mccq(adapter);
2278 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2279 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2282 req->params.op_type = cpu_to_le32(flash_type);
2283 req->params.op_code = cpu_to_le32(flash_opcode);
2284 req->params.data_buf_size = cpu_to_le32(buf_size);
2286 be_mcc_notify(adapter);
2287 spin_unlock_bh(&adapter->mcc_lock);
2289 if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2290 msecs_to_jiffies(40000)))
2293 status = adapter->flash_status;
2298 spin_unlock_bh(&adapter->mcc_lock);
2302 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2305 struct be_mcc_wrb *wrb;
2306 struct be_cmd_read_flash_crc *req;
2309 spin_lock_bh(&adapter->mcc_lock);
2311 wrb = wrb_from_mccq(adapter);
2316 req = embedded_payload(wrb);
2318 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2319 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2322 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2323 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2324 req->params.offset = cpu_to_le32(offset);
2325 req->params.data_buf_size = cpu_to_le32(0x4);
2327 status = be_mcc_notify_wait(adapter);
2329 memcpy(flashed_crc, req->crc, 4);
2332 spin_unlock_bh(&adapter->mcc_lock);
2336 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2337 struct be_dma_mem *nonemb_cmd)
2339 struct be_mcc_wrb *wrb;
2340 struct be_cmd_req_acpi_wol_magic_config *req;
2343 spin_lock_bh(&adapter->mcc_lock);
2345 wrb = wrb_from_mccq(adapter);
2350 req = nonemb_cmd->va;
2352 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2353 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2355 memcpy(req->magic_mac, mac, ETH_ALEN);
2357 status = be_mcc_notify_wait(adapter);
2360 spin_unlock_bh(&adapter->mcc_lock);
2364 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2365 u8 loopback_type, u8 enable)
2367 struct be_mcc_wrb *wrb;
2368 struct be_cmd_req_set_lmode *req;
2371 spin_lock_bh(&adapter->mcc_lock);
2373 wrb = wrb_from_mccq(adapter);
2379 req = embedded_payload(wrb);
2381 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2382 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2385 req->src_port = port_num;
2386 req->dest_port = port_num;
2387 req->loopback_type = loopback_type;
2388 req->loopback_state = enable;
2390 status = be_mcc_notify_wait(adapter);
2392 spin_unlock_bh(&adapter->mcc_lock);
2396 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2397 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2400 struct be_mcc_wrb *wrb;
2401 struct be_cmd_req_loopback_test *req;
2402 struct be_cmd_resp_loopback_test *resp;
2405 spin_lock_bh(&adapter->mcc_lock);
2407 wrb = wrb_from_mccq(adapter);
2413 req = embedded_payload(wrb);
2415 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2416 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2419 req->hdr.timeout = cpu_to_le32(15);
2420 req->pattern = cpu_to_le64(pattern);
2421 req->src_port = cpu_to_le32(port_num);
2422 req->dest_port = cpu_to_le32(port_num);
2423 req->pkt_size = cpu_to_le32(pkt_size);
2424 req->num_pkts = cpu_to_le32(num_pkts);
2425 req->loopback_type = cpu_to_le32(loopback_type);
2427 be_mcc_notify(adapter);
2429 spin_unlock_bh(&adapter->mcc_lock);
2431 wait_for_completion(&adapter->et_cmd_compl);
2432 resp = embedded_payload(wrb);
2433 status = le32_to_cpu(resp->status);
2437 spin_unlock_bh(&adapter->mcc_lock);
2441 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2442 u32 byte_cnt, struct be_dma_mem *cmd)
2444 struct be_mcc_wrb *wrb;
2445 struct be_cmd_req_ddrdma_test *req;
2449 spin_lock_bh(&adapter->mcc_lock);
2451 wrb = wrb_from_mccq(adapter);
2457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2458 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2461 req->pattern = cpu_to_le64(pattern);
2462 req->byte_count = cpu_to_le32(byte_cnt);
2463 for (i = 0; i < byte_cnt; i++) {
2464 req->snd_buff[i] = (u8)(pattern >> (j*8));
2470 status = be_mcc_notify_wait(adapter);
2473 struct be_cmd_resp_ddrdma_test *resp;
2475 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2482 spin_unlock_bh(&adapter->mcc_lock);
2486 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2487 struct be_dma_mem *nonemb_cmd)
2489 struct be_mcc_wrb *wrb;
2490 struct be_cmd_req_seeprom_read *req;
2493 spin_lock_bh(&adapter->mcc_lock);
2495 wrb = wrb_from_mccq(adapter);
2500 req = nonemb_cmd->va;
2502 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2503 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2506 status = be_mcc_notify_wait(adapter);
2509 spin_unlock_bh(&adapter->mcc_lock);
2513 int be_cmd_get_phy_info(struct be_adapter *adapter)
2515 struct be_mcc_wrb *wrb;
2516 struct be_cmd_req_get_phy_info *req;
2517 struct be_dma_mem cmd;
2520 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2521 CMD_SUBSYSTEM_COMMON))
2524 spin_lock_bh(&adapter->mcc_lock);
2526 wrb = wrb_from_mccq(adapter);
2531 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2532 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2534 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2541 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2542 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2545 status = be_mcc_notify_wait(adapter);
2547 struct be_phy_info *resp_phy_info =
2548 cmd.va + sizeof(struct be_cmd_req_hdr);
2549 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2550 adapter->phy.interface_type =
2551 le16_to_cpu(resp_phy_info->interface_type);
2552 adapter->phy.auto_speeds_supported =
2553 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2554 adapter->phy.fixed_speeds_supported =
2555 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2556 adapter->phy.misc_params =
2557 le32_to_cpu(resp_phy_info->misc_params);
2559 if (BE2_chip(adapter)) {
2560 adapter->phy.fixed_speeds_supported =
2561 BE_SUPPORTED_SPEED_10GBPS |
2562 BE_SUPPORTED_SPEED_1GBPS;
2565 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2567 spin_unlock_bh(&adapter->mcc_lock);
2571 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2573 struct be_mcc_wrb *wrb;
2574 struct be_cmd_req_set_qos *req;
2577 spin_lock_bh(&adapter->mcc_lock);
2579 wrb = wrb_from_mccq(adapter);
2585 req = embedded_payload(wrb);
2587 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2588 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2590 req->hdr.domain = domain;
2591 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2592 req->max_bps_nic = cpu_to_le32(bps);
2594 status = be_mcc_notify_wait(adapter);
2597 spin_unlock_bh(&adapter->mcc_lock);
2601 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2603 struct be_mcc_wrb *wrb;
2604 struct be_cmd_req_cntl_attribs *req;
2605 struct be_cmd_resp_cntl_attribs *resp;
2607 int payload_len = max(sizeof(*req), sizeof(*resp));
2608 struct mgmt_controller_attrib *attribs;
2609 struct be_dma_mem attribs_cmd;
2611 if (mutex_lock_interruptible(&adapter->mbox_lock))
2614 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2615 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2616 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2618 if (!attribs_cmd.va) {
2619 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2624 wrb = wrb_from_mbox(adapter);
2629 req = attribs_cmd.va;
2631 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2632 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2635 status = be_mbox_notify_wait(adapter);
2637 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2638 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2642 mutex_unlock(&adapter->mbox_lock);
2644 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2645 attribs_cmd.va, attribs_cmd.dma);
2650 int be_cmd_req_native_mode(struct be_adapter *adapter)
2652 struct be_mcc_wrb *wrb;
2653 struct be_cmd_req_set_func_cap *req;
2656 if (mutex_lock_interruptible(&adapter->mbox_lock))
2659 wrb = wrb_from_mbox(adapter);
2665 req = embedded_payload(wrb);
2667 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2668 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2669 sizeof(*req), wrb, NULL);
2671 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2672 CAPABILITY_BE3_NATIVE_ERX_API);
2673 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2675 status = be_mbox_notify_wait(adapter);
2677 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2678 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2679 CAPABILITY_BE3_NATIVE_ERX_API;
2680 if (!adapter->be3_native)
2681 dev_warn(&adapter->pdev->dev,
2682 "adapter not in advanced mode\n");
2685 mutex_unlock(&adapter->mbox_lock);
2689 /* Get privilege(s) for a function */
2690 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2693 struct be_mcc_wrb *wrb;
2694 struct be_cmd_req_get_fn_privileges *req;
2697 spin_lock_bh(&adapter->mcc_lock);
2699 wrb = wrb_from_mccq(adapter);
2705 req = embedded_payload(wrb);
2707 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2708 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2711 req->hdr.domain = domain;
2713 status = be_mcc_notify_wait(adapter);
2715 struct be_cmd_resp_get_fn_privileges *resp =
2716 embedded_payload(wrb);
2717 *privilege = le32_to_cpu(resp->privilege_mask);
2719 /* In UMC mode FW does not return right privileges.
2720 * Override with correct privilege equivalent to PF.
2722 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2724 *privilege = MAX_PRIVILEGES;
2728 spin_unlock_bh(&adapter->mcc_lock);
2732 /* Set privilege(s) for a function */
2733 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2736 struct be_mcc_wrb *wrb;
2737 struct be_cmd_req_set_fn_privileges *req;
2740 spin_lock_bh(&adapter->mcc_lock);
2742 wrb = wrb_from_mccq(adapter);
2748 req = embedded_payload(wrb);
2749 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2750 OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2752 req->hdr.domain = domain;
2753 if (lancer_chip(adapter))
2754 req->privileges_lancer = cpu_to_le32(privileges);
2756 req->privileges = cpu_to_le32(privileges);
2758 status = be_mcc_notify_wait(adapter);
2760 spin_unlock_bh(&adapter->mcc_lock);
2764 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2765 * pmac_id_valid: false => pmac_id or MAC address is requested.
2766 * If pmac_id is returned, pmac_id_valid is returned as true
2768 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2769 bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2772 struct be_mcc_wrb *wrb;
2773 struct be_cmd_req_get_mac_list *req;
2776 struct be_dma_mem get_mac_list_cmd;
2779 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2780 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2781 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2782 get_mac_list_cmd.size,
2783 &get_mac_list_cmd.dma);
2785 if (!get_mac_list_cmd.va) {
2786 dev_err(&adapter->pdev->dev,
2787 "Memory allocation failure during GET_MAC_LIST\n");
2791 spin_lock_bh(&adapter->mcc_lock);
2793 wrb = wrb_from_mccq(adapter);
2799 req = get_mac_list_cmd.va;
2801 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2802 OPCODE_COMMON_GET_MAC_LIST,
2803 get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2804 req->hdr.domain = domain;
2805 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2806 if (*pmac_id_valid) {
2807 req->mac_id = cpu_to_le32(*pmac_id);
2808 req->iface_id = cpu_to_le16(if_handle);
2809 req->perm_override = 0;
2811 req->perm_override = 1;
2814 status = be_mcc_notify_wait(adapter);
2816 struct be_cmd_resp_get_mac_list *resp =
2817 get_mac_list_cmd.va;
2819 if (*pmac_id_valid) {
2820 memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2825 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2826 /* Mac list returned could contain one or more active mac_ids
2827 * or one or more true or pseudo permanant mac addresses.
2828 * If an active mac_id is present, return first active mac_id
2831 for (i = 0; i < mac_count; i++) {
2832 struct get_list_macaddr *mac_entry;
2836 mac_entry = &resp->macaddr_list[i];
2837 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2838 /* mac_id is a 32 bit value and mac_addr size
2841 if (mac_addr_size == sizeof(u32)) {
2842 *pmac_id_valid = true;
2843 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2844 *pmac_id = le32_to_cpu(mac_id);
2848 /* If no active mac_id found, return first mac addr */
2849 *pmac_id_valid = false;
2850 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2855 spin_unlock_bh(&adapter->mcc_lock);
2856 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2857 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2861 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
2862 u8 *mac, u32 if_handle, bool active, u32 domain)
2866 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2868 if (BEx_chip(adapter))
2869 return be_cmd_mac_addr_query(adapter, mac, false,
2870 if_handle, curr_pmac_id);
2872 /* Fetch the MAC address using pmac_id */
2873 return be_cmd_get_mac_from_list(adapter, mac, &active,
2878 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2881 bool pmac_valid = false;
2883 memset(mac, 0, ETH_ALEN);
2885 if (BEx_chip(adapter)) {
2886 if (be_physfn(adapter))
2887 status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2890 status = be_cmd_mac_addr_query(adapter, mac, false,
2891 adapter->if_handle, 0);
2893 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2894 NULL, adapter->if_handle, 0);
2900 /* Uses synchronous MCCQ */
2901 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2902 u8 mac_count, u32 domain)
2904 struct be_mcc_wrb *wrb;
2905 struct be_cmd_req_set_mac_list *req;
2907 struct be_dma_mem cmd;
2909 memset(&cmd, 0, sizeof(struct be_dma_mem));
2910 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2911 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2912 &cmd.dma, GFP_KERNEL);
2916 spin_lock_bh(&adapter->mcc_lock);
2918 wrb = wrb_from_mccq(adapter);
2925 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2926 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2929 req->hdr.domain = domain;
2930 req->mac_count = mac_count;
2932 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2934 status = be_mcc_notify_wait(adapter);
2937 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2938 spin_unlock_bh(&adapter->mcc_lock);
2942 /* Wrapper to delete any active MACs and provision the new mac.
2943 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2944 * current list are active.
2946 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2948 bool active_mac = false;
2949 u8 old_mac[ETH_ALEN];
2953 status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2954 &pmac_id, if_id, dom);
2956 if (!status && active_mac)
2957 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2959 return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2962 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2963 u32 domain, u16 intf_id, u16 hsw_mode)
2965 struct be_mcc_wrb *wrb;
2966 struct be_cmd_req_set_hsw_config *req;
2970 spin_lock_bh(&adapter->mcc_lock);
2972 wrb = wrb_from_mccq(adapter);
2978 req = embedded_payload(wrb);
2979 ctxt = &req->context;
2981 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2982 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
2985 req->hdr.domain = domain;
2986 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2988 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2989 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2991 if (!BEx_chip(adapter) && hsw_mode) {
2992 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2993 ctxt, adapter->hba_port_num);
2994 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2995 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2999 be_dws_cpu_to_le(req->context, sizeof(req->context));
3000 status = be_mcc_notify_wait(adapter);
3003 spin_unlock_bh(&adapter->mcc_lock);
3007 /* Get Hyper switch config */
3008 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3009 u32 domain, u16 intf_id, u8 *mode)
3011 struct be_mcc_wrb *wrb;
3012 struct be_cmd_req_get_hsw_config *req;
3017 spin_lock_bh(&adapter->mcc_lock);
3019 wrb = wrb_from_mccq(adapter);
3025 req = embedded_payload(wrb);
3026 ctxt = &req->context;
3028 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3029 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3032 req->hdr.domain = domain;
3033 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3035 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3037 if (!BEx_chip(adapter) && mode) {
3038 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3039 ctxt, adapter->hba_port_num);
3040 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3042 be_dws_cpu_to_le(req->context, sizeof(req->context));
3044 status = be_mcc_notify_wait(adapter);
3046 struct be_cmd_resp_get_hsw_config *resp =
3047 embedded_payload(wrb);
3048 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3049 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3050 pvid, &resp->context);
3052 *pvid = le16_to_cpu(vid);
3054 *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3055 port_fwd_type, &resp->context);
3059 spin_unlock_bh(&adapter->mcc_lock);
3063 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3065 struct be_mcc_wrb *wrb;
3066 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3068 struct be_dma_mem cmd;
3070 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3074 if (be_is_wol_excluded(adapter))
3077 if (mutex_lock_interruptible(&adapter->mbox_lock))
3080 memset(&cmd, 0, sizeof(struct be_dma_mem));
3081 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3082 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3084 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3089 wrb = wrb_from_mbox(adapter);
3097 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3098 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3099 sizeof(*req), wrb, &cmd);
3101 req->hdr.version = 1;
3102 req->query_options = BE_GET_WOL_CAP;
3104 status = be_mbox_notify_wait(adapter);
3106 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3107 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3109 adapter->wol_cap = resp->wol_settings;
3110 if (adapter->wol_cap & BE_WOL_CAP)
3111 adapter->wol_en = true;
3114 mutex_unlock(&adapter->mbox_lock);
3116 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3121 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3123 struct be_dma_mem extfat_cmd;
3124 struct be_fat_conf_params *cfgs;
3128 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3129 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3130 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3135 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3139 cfgs = (struct be_fat_conf_params *)
3140 (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3141 for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3142 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3143 for (j = 0; j < num_modes; j++) {
3144 if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3145 cfgs->module[i].trace_lvl[j].dbg_lvl =
3150 status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3152 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3157 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3159 struct be_dma_mem extfat_cmd;
3160 struct be_fat_conf_params *cfgs;
3164 memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3165 extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3166 extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3169 if (!extfat_cmd.va) {
3170 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3175 status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3177 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3178 sizeof(struct be_cmd_resp_hdr));
3179 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3180 if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3181 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3184 pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3190 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3191 struct be_dma_mem *cmd)
3193 struct be_mcc_wrb *wrb;
3194 struct be_cmd_req_get_ext_fat_caps *req;
3197 if (mutex_lock_interruptible(&adapter->mbox_lock))
3200 wrb = wrb_from_mbox(adapter);
3207 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3208 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3209 cmd->size, wrb, cmd);
3210 req->parameter_type = cpu_to_le32(1);
3212 status = be_mbox_notify_wait(adapter);
3214 mutex_unlock(&adapter->mbox_lock);
3218 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3219 struct be_dma_mem *cmd,
3220 struct be_fat_conf_params *configs)
3222 struct be_mcc_wrb *wrb;
3223 struct be_cmd_req_set_ext_fat_caps *req;
3226 spin_lock_bh(&adapter->mcc_lock);
3228 wrb = wrb_from_mccq(adapter);
3235 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3236 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3237 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3238 cmd->size, wrb, cmd);
3240 status = be_mcc_notify_wait(adapter);
3242 spin_unlock_bh(&adapter->mcc_lock);
3246 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3248 struct be_mcc_wrb *wrb;
3249 struct be_cmd_req_get_port_name *req;
3252 if (!lancer_chip(adapter)) {
3253 *port_name = adapter->hba_port_num + '0';
3257 spin_lock_bh(&adapter->mcc_lock);
3259 wrb = wrb_from_mccq(adapter);
3265 req = embedded_payload(wrb);
3267 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3268 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3270 req->hdr.version = 1;
3272 status = be_mcc_notify_wait(adapter);
3274 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3275 *port_name = resp->port_name[adapter->hba_port_num];
3277 *port_name = adapter->hba_port_num + '0';
3280 spin_unlock_bh(&adapter->mcc_lock);
3284 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3286 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3289 for (i = 0; i < desc_count; i++) {
3290 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3291 hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3292 return (struct be_nic_res_desc *)hdr;
3294 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3295 hdr = (void *)hdr + hdr->desc_len;
3300 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3303 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3304 struct be_pcie_res_desc *pcie;
3307 for (i = 0; i < desc_count; i++) {
3308 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3309 hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3310 pcie = (struct be_pcie_res_desc *)hdr;
3311 if (pcie->pf_num == devfn)
3315 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3316 hdr = (void *)hdr + hdr->desc_len;
3321 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3323 struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3326 for (i = 0; i < desc_count; i++) {
3327 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3328 return (struct be_port_res_desc *)hdr;
3330 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3331 hdr = (void *)hdr + hdr->desc_len;
3336 static void be_copy_nic_desc(struct be_resources *res,
3337 struct be_nic_res_desc *desc)
3339 res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3340 res->max_vlans = le16_to_cpu(desc->vlan_count);
3341 res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3342 res->max_tx_qs = le16_to_cpu(desc->txq_count);
3343 res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3344 res->max_rx_qs = le16_to_cpu(desc->rq_count);
3345 res->max_evt_qs = le16_to_cpu(desc->eq_count);
3346 /* Clear flags that driver is not interested in */
3347 res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3348 BE_IF_CAP_FLAGS_WANT;
3349 /* Need 1 RXQ as the default RXQ */
3350 if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3351 res->max_rss_qs -= 1;
3355 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3357 struct be_mcc_wrb *wrb;
3358 struct be_cmd_req_get_func_config *req;
3360 struct be_dma_mem cmd;
3362 if (mutex_lock_interruptible(&adapter->mbox_lock))
3365 memset(&cmd, 0, sizeof(struct be_dma_mem));
3366 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3367 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3369 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3374 wrb = wrb_from_mbox(adapter);
3382 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3383 OPCODE_COMMON_GET_FUNC_CONFIG,
3384 cmd.size, wrb, &cmd);
3386 if (skyhawk_chip(adapter))
3387 req->hdr.version = 1;
3389 status = be_mbox_notify_wait(adapter);
3391 struct be_cmd_resp_get_func_config *resp = cmd.va;
3392 u32 desc_count = le32_to_cpu(resp->desc_count);
3393 struct be_nic_res_desc *desc;
3395 desc = be_get_nic_desc(resp->func_param, desc_count);
3401 adapter->pf_number = desc->pf_num;
3402 be_copy_nic_desc(res, desc);
3405 mutex_unlock(&adapter->mbox_lock);
3407 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3412 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3413 u8 domain, struct be_dma_mem *cmd)
3415 struct be_mcc_wrb *wrb;
3416 struct be_cmd_req_get_profile_config *req;
3419 if (mutex_lock_interruptible(&adapter->mbox_lock))
3421 wrb = wrb_from_mbox(adapter);
3424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3425 OPCODE_COMMON_GET_PROFILE_CONFIG,
3426 cmd->size, wrb, cmd);
3428 req->type = ACTIVE_PROFILE_TYPE;
3429 req->hdr.domain = domain;
3430 if (!lancer_chip(adapter))
3431 req->hdr.version = 1;
3433 status = be_mbox_notify_wait(adapter);
3435 mutex_unlock(&adapter->mbox_lock);
3440 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3441 u8 domain, struct be_dma_mem *cmd)
3443 struct be_mcc_wrb *wrb;
3444 struct be_cmd_req_get_profile_config *req;
3447 spin_lock_bh(&adapter->mcc_lock);
3449 wrb = wrb_from_mccq(adapter);
3456 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3457 OPCODE_COMMON_GET_PROFILE_CONFIG,
3458 cmd->size, wrb, cmd);
3460 req->type = ACTIVE_PROFILE_TYPE;
3461 req->hdr.domain = domain;
3462 if (!lancer_chip(adapter))
3463 req->hdr.version = 1;
3465 status = be_mcc_notify_wait(adapter);
3468 spin_unlock_bh(&adapter->mcc_lock);
3472 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3473 int be_cmd_get_profile_config(struct be_adapter *adapter,
3474 struct be_resources *res, u8 domain)
3476 struct be_cmd_resp_get_profile_config *resp;
3477 struct be_pcie_res_desc *pcie;
3478 struct be_port_res_desc *port;
3479 struct be_nic_res_desc *nic;
3480 struct be_queue_info *mccq = &adapter->mcc_obj.q;
3481 struct be_dma_mem cmd;
3485 memset(&cmd, 0, sizeof(struct be_dma_mem));
3486 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3487 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3492 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3494 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3499 desc_count = le32_to_cpu(resp->desc_count);
3501 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3504 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3506 port = be_get_port_desc(resp->func_param, desc_count);
3508 adapter->mc_type = port->mc_type;
3510 nic = be_get_nic_desc(resp->func_param, desc_count);
3512 be_copy_nic_desc(res, nic);
3516 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3520 int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3521 int size, u8 version, u8 domain)
3523 struct be_cmd_req_set_profile_config *req;
3524 struct be_mcc_wrb *wrb;
3527 spin_lock_bh(&adapter->mcc_lock);
3529 wrb = wrb_from_mccq(adapter);
3535 req = embedded_payload(wrb);
3536 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3537 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3539 req->hdr.version = version;
3540 req->hdr.domain = domain;
3541 req->desc_count = cpu_to_le32(1);
3542 memcpy(req->desc, desc, size);
3544 status = be_mcc_notify_wait(adapter);
3546 spin_unlock_bh(&adapter->mcc_lock);
3550 /* Mark all fields invalid */
3551 void be_reset_nic_desc(struct be_nic_res_desc *nic)
3553 memset(nic, 0, sizeof(*nic));
3554 nic->unicast_mac_count = 0xFFFF;
3555 nic->mcc_count = 0xFFFF;
3556 nic->vlan_count = 0xFFFF;
3557 nic->mcast_mac_count = 0xFFFF;
3558 nic->txq_count = 0xFFFF;
3559 nic->rq_count = 0xFFFF;
3560 nic->rssq_count = 0xFFFF;
3561 nic->lro_count = 0xFFFF;
3562 nic->cq_count = 0xFFFF;
3563 nic->toe_conn_count = 0xFFFF;
3564 nic->eq_count = 0xFFFF;
3565 nic->iface_count = 0xFFFF;
3566 nic->link_param = 0xFF;
3567 nic->channel_id_param = cpu_to_le16(0xF000);
3568 nic->acpi_params = 0xFF;
3569 nic->wol_param = 0x0F;
3570 nic->tunnel_iface_count = 0xFFFF;
3571 nic->direct_tenant_iface_count = 0xFFFF;
3572 nic->bw_max = 0xFFFFFFFF;
3575 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3578 struct be_nic_res_desc nic_desc;
3582 if (BE3_chip(adapter))
3583 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3585 be_reset_nic_desc(&nic_desc);
3586 nic_desc.pf_num = adapter->pf_number;
3587 nic_desc.vf_num = domain;
3588 if (lancer_chip(adapter)) {
3589 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3590 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3591 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3593 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3596 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3597 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3598 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3599 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3600 nic_desc.bw_max = cpu_to_le32(bw_percent);
3603 return be_cmd_set_profile_config(adapter, &nic_desc,
3604 nic_desc.hdr.desc_len,
3608 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3610 struct be_mcc_wrb *wrb;
3611 struct be_cmd_req_manage_iface_filters *req;
3614 if (iface == 0xFFFFFFFF)
3617 spin_lock_bh(&adapter->mcc_lock);
3619 wrb = wrb_from_mccq(adapter);
3624 req = embedded_payload(wrb);
3626 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3627 OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3630 req->target_iface_id = cpu_to_le32(iface);
3632 status = be_mcc_notify_wait(adapter);
3634 spin_unlock_bh(&adapter->mcc_lock);
3638 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3640 struct be_port_res_desc port_desc;
3642 memset(&port_desc, 0, sizeof(port_desc));
3643 port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3644 port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3645 port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3646 port_desc.link_num = adapter->hba_port_num;
3648 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3650 port_desc.nv_port = swab16(port);
3652 port_desc.nv_flags = NV_TYPE_DISABLED;
3653 port_desc.nv_port = 0;
3656 return be_cmd_set_profile_config(adapter, &port_desc,
3657 RESOURCE_DESC_SIZE_V1, 1, 0);
3660 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3663 struct be_mcc_wrb *wrb;
3664 struct be_cmd_req_get_iface_list *req;
3665 struct be_cmd_resp_get_iface_list *resp;
3668 spin_lock_bh(&adapter->mcc_lock);
3670 wrb = wrb_from_mccq(adapter);
3675 req = embedded_payload(wrb);
3677 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3678 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3680 req->hdr.domain = vf_num + 1;
3682 status = be_mcc_notify_wait(adapter);
3684 resp = (struct be_cmd_resp_get_iface_list *)req;
3685 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3689 spin_unlock_bh(&adapter->mcc_lock);
3693 static int lancer_wait_idle(struct be_adapter *adapter)
3695 #define SLIPORT_IDLE_TIMEOUT 30
3699 for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3700 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3701 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3707 if (i == SLIPORT_IDLE_TIMEOUT)
3713 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3717 status = lancer_wait_idle(adapter);
3721 iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3726 /* Routine to check whether dump image is present or not */
3727 bool dump_present(struct be_adapter *adapter)
3729 u32 sliport_status = 0;
3731 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3732 return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3735 int lancer_initiate_dump(struct be_adapter *adapter)
3739 /* give firmware reset and diagnostic dump */
3740 status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3741 PHYSDEV_CONTROL_DD_MASK);
3743 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3747 status = lancer_wait_idle(adapter);
3751 if (!dump_present(adapter)) {
3752 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3760 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3762 struct be_mcc_wrb *wrb;
3763 struct be_cmd_enable_disable_vf *req;
3766 if (BEx_chip(adapter))
3769 spin_lock_bh(&adapter->mcc_lock);
3771 wrb = wrb_from_mccq(adapter);
3777 req = embedded_payload(wrb);
3779 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3780 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3783 req->hdr.domain = domain;
3785 status = be_mcc_notify_wait(adapter);
3787 spin_unlock_bh(&adapter->mcc_lock);
3791 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3793 struct be_mcc_wrb *wrb;
3794 struct be_cmd_req_intr_set *req;
3797 if (mutex_lock_interruptible(&adapter->mbox_lock))
3800 wrb = wrb_from_mbox(adapter);
3802 req = embedded_payload(wrb);
3804 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3805 OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3808 req->intr_enabled = intr_enable;
3810 status = be_mbox_notify_wait(adapter);
3812 mutex_unlock(&adapter->mbox_lock);
3817 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3819 struct be_cmd_req_get_active_profile *req;
3820 struct be_mcc_wrb *wrb;
3823 if (mutex_lock_interruptible(&adapter->mbox_lock))
3826 wrb = wrb_from_mbox(adapter);
3832 req = embedded_payload(wrb);
3834 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3835 OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
3838 status = be_mbox_notify_wait(adapter);
3840 struct be_cmd_resp_get_active_profile *resp =
3841 embedded_payload(wrb);
3842 *profile_id = le16_to_cpu(resp->active_profile_id);
3846 mutex_unlock(&adapter->mbox_lock);
3850 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
3851 int link_state, u8 domain)
3853 struct be_mcc_wrb *wrb;
3854 struct be_cmd_req_set_ll_link *req;
3857 if (BEx_chip(adapter) || lancer_chip(adapter))
3860 spin_lock_bh(&adapter->mcc_lock);
3862 wrb = wrb_from_mccq(adapter);
3868 req = embedded_payload(wrb);
3870 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3871 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
3872 sizeof(*req), wrb, NULL);
3874 req->hdr.version = 1;
3875 req->hdr.domain = domain;
3877 if (link_state == IFLA_VF_LINK_STATE_ENABLE)
3878 req->link_config |= 1;
3880 if (link_state == IFLA_VF_LINK_STATE_AUTO)
3881 req->link_config |= 1 << PLINK_TRACK_SHIFT;
3883 status = be_mcc_notify_wait(adapter);
3885 spin_unlock_bh(&adapter->mcc_lock);
3889 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3890 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3892 struct be_adapter *adapter = netdev_priv(netdev_handle);
3893 struct be_mcc_wrb *wrb;
3894 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3895 struct be_cmd_req_hdr *req;
3896 struct be_cmd_resp_hdr *resp;
3899 spin_lock_bh(&adapter->mcc_lock);
3901 wrb = wrb_from_mccq(adapter);
3906 req = embedded_payload(wrb);
3907 resp = embedded_payload(wrb);
3909 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3910 hdr->opcode, wrb_payload_size, wrb, NULL);
3911 memcpy(req, wrb_payload, wrb_payload_size);
3912 be_dws_cpu_to_le(req, wrb_payload_size);
3914 status = be_mcc_notify_wait(adapter);
3916 *cmd_status = (status & 0xffff);
3919 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3920 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3922 spin_unlock_bh(&adapter->mcc_lock);
3925 EXPORT_SYMBOL(be_roce_mcc_cmd);