drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2014 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  56 {
  57         int i;
  58         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  59         u32 cmd_privileges = adapter->cmd_privileges;
  60
  61         for (i = 0; i < num_entries; i++)
  62                 if (opcode == cmd_priv_map[i].opcode &&
  63                     subsystem == cmd_priv_map[i].subsystem)
  64                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  65                                 return false;
  66
  67         return true;
  68 }
  69
  70 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  71 {
  72         return wrb->payload.embedded_payload;
  73 }
  74
  75 static void be_mcc_notify(struct be_adapter *adapter)
  76 {
  77         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  78         u32 val = 0;
  79
  80         if (be_error(adapter))
  81                 return;
  82
  83         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  84         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  85
  86         wmb();
  87         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  88 }
  89
  90 /* To check if valid bit is set, check the entire word as we don't know
  91  * the endianness of the data (old entry is host endian while a new entry is
  92  * little endian) */
  93 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  94 {
  95         u32 flags;
  96
  97         if (compl->flags != 0) {
  98                 flags = le32_to_cpu(compl->flags);
  99                 if (flags & CQE_FLAGS_VALID_MASK) {
 100                         compl->flags = flags;
 101                         return true;
 102                 }
 103         }
 104         return false;
 105 }
 106
 107 /* Need to reset the entire word that houses the valid bit */
 108 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 109 {
 110         compl->flags = 0;
 111 }
 112
 113 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 114 {
 115         unsigned long addr;
 116
 117         addr = tag1;
 118         addr = ((addr << 16) << 16) | tag0;
 119         return (void *)addr;
 120 }
 121
 122 static int be_mcc_compl_process(struct be_adapter *adapter,
 123                                 struct be_mcc_compl *compl)
 124 {
 125         u16 compl_status, extd_status;
 126         struct be_cmd_resp_hdr *resp_hdr;
 127         u8 opcode = 0, subsystem = 0;
 128
 129         /* Just swap the status to host endian; mcc tag is opaquely copied
 130          * from mcc_wrb */
 131         be_dws_le_to_cpu(compl, 4);
 132
 133         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 134                                 CQE_STATUS_COMPL_MASK;
 135
 136         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 137
 138         if (resp_hdr) {
 139                 opcode = resp_hdr->opcode;
 140                 subsystem = resp_hdr->subsystem;
 141         }
 142
 143         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 144             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 145                 complete(&adapter->et_cmd_compl);
 146                 return 0;
 147         }
 148
 149         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 150              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 151             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 152                 adapter->flash_status = compl_status;
 153                 complete(&adapter->et_cmd_compl);
 154         }
 155
 156         if (compl_status == MCC_STATUS_SUCCESS) {
 157                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 158                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 159                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 160                         be_parse_stats(adapter);
 161                         adapter->stats_cmd_sent = false;
 162                 }
 163                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 164                     subsystem == CMD_SUBSYSTEM_COMMON) {
 165                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 166                                 (void *)resp_hdr;
 167                         adapter->drv_stats.be_on_die_temperature =
 168                                 resp->on_die_temperature;
 169                 }
 170         } else {
 171                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 172                         adapter->be_get_temp_freq = 0;
 173
 174                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 175                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 176                         goto done;
 177
 178                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 179                         dev_warn(&adapter->pdev->dev,
 180                                  "VF is not privileged to issue opcode %d-%d\n",
 181                                  opcode, subsystem);
 182                 } else {
 183                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 184                                         CQE_STATUS_EXTD_MASK;
 185                         dev_err(&adapter->pdev->dev,
 186                                 "opcode %d-%d failed:status %d-%d\n",
 187                                 opcode, subsystem, compl_status, extd_status);
 188
 189                         if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
 190                                 return extd_status;
 191                 }
 192         }
 193 done:
 194         return compl_status;
 195 }
 196
 197 /* Link state evt is a string of bytes; no need for endian swapping */
 198 static void be_async_link_state_process(struct be_adapter *adapter,
 199                                         struct be_async_event_link_state *evt)
 200 {
 201         /* When link status changes, link speed must be re-queried from FW */
 202         adapter->phy.link_speed = -1;
 203
 204         /* On BEx the FW does not send a separate link status
 205          * notification for physical and logical link.
 206          * On other chips just process the logical link
 207          * status notification
 208          */
 209         if (!BEx_chip(adapter) &&
 210             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 211                 return;
 212
 213         /* For the initial link status do not rely on the ASYNC event as
 214          * it may not be received in some cases.
 215          */
 216         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 217                 be_link_status_update(adapter,
 218                                       evt->port_link_status & LINK_STATUS_MASK);
 219 }
 220
 221 /* Grp5 CoS Priority evt */
 222 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 223                                                struct
 224                                                be_async_event_grp5_cos_priority
 225                                                *evt)
 226 {
 227         if (evt->valid) {
 228                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 229                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 230                 adapter->recommended_prio =
 231                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 232         }
 233 }
 234
 235 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 236 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 237                                             struct
 238                                             be_async_event_grp5_qos_link_speed
 239                                             *evt)
 240 {
 241         if (adapter->phy.link_speed >= 0 &&
 242             evt->physical_port == adapter->port_num)
 243                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 244 }
 245
 246 /*Grp5 PVID evt*/
 247 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 248                                              struct
 249                                              be_async_event_grp5_pvid_state
 250                                              *evt)
 251 {
 252         if (evt->enabled) {
 253                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 254                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 255         } else {
 256                 adapter->pvid = 0;
 257         }
 258 }
 259
 260 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 261                                       u32 trailer, struct be_mcc_compl *evt)
 262 {
 263         u8 event_type = 0;
 264
 265         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 266                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 267
 268         switch (event_type) {
 269         case ASYNC_EVENT_COS_PRIORITY:
 270                 be_async_grp5_cos_priority_process(adapter,
 271                 (struct be_async_event_grp5_cos_priority *)evt);
 272         break;
 273         case ASYNC_EVENT_QOS_SPEED:
 274                 be_async_grp5_qos_speed_process(adapter,
 275                 (struct be_async_event_grp5_qos_link_speed *)evt);
 276         break;
 277         case ASYNC_EVENT_PVID_STATE:
 278                 be_async_grp5_pvid_state_process(adapter,
 279                 (struct be_async_event_grp5_pvid_state *)evt);
 280         break;
 281         default:
 282                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
 283                          event_type);
 284                 break;
 285         }
 286 }
 287
 288 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 289                                      u32 trailer, struct be_mcc_compl *cmp)
 290 {
 291         u8 event_type = 0;
 292         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 293
 294         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 295                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 296
 297         switch (event_type) {
 298         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 299                 if (evt->valid)
 300                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 301                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 302         break;
 303         default:
 304                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 305                          event_type);
 306         break;
 307         }
 308 }
 309
 310 static inline bool is_link_state_evt(u32 trailer)
 311 {
 312         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 313                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 314                                 ASYNC_EVENT_CODE_LINK_STATE;
 315 }
 316
 317 static inline bool is_grp5_evt(u32 trailer)
 318 {
 319         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 320                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 321                                 ASYNC_EVENT_CODE_GRP_5);
 322 }
 323
 324 static inline bool is_dbg_evt(u32 trailer)
 325 {
 326         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 327                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 328                                 ASYNC_EVENT_CODE_QNQ);
 329 }
 330
 331 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 332 {
 333         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 334         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 335
 336         if (be_mcc_compl_is_new(compl)) {
 337                 queue_tail_inc(mcc_cq);
 338                 return compl;
 339         }
 340         return NULL;
 341 }
 342
 343 void be_async_mcc_enable(struct be_adapter *adapter)
 344 {
 345         spin_lock_bh(&adapter->mcc_cq_lock);
 346
 347         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 348         adapter->mcc_obj.rearm_cq = true;
 349
 350         spin_unlock_bh(&adapter->mcc_cq_lock);
 351 }
 352
 353 void be_async_mcc_disable(struct be_adapter *adapter)
 354 {
 355         spin_lock_bh(&adapter->mcc_cq_lock);
 356
 357         adapter->mcc_obj.rearm_cq = false;
 358         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 359
 360         spin_unlock_bh(&adapter->mcc_cq_lock);
 361 }
 362
 363 int be_process_mcc(struct be_adapter *adapter)
 364 {
 365         struct be_mcc_compl *compl;
 366         int num = 0, status = 0;
 367         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 368
 369         spin_lock(&adapter->mcc_cq_lock);
 370         while ((compl = be_mcc_compl_get(adapter))) {
 371                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 372                         /* Interpret flags as an async trailer */
 373                         if (is_link_state_evt(compl->flags))
 374                                 be_async_link_state_process(adapter,
 375                                 (struct be_async_event_link_state *) compl);
 376                         else if (is_grp5_evt(compl->flags))
 377                                 be_async_grp5_evt_process(adapter,
 378                                                           compl->flags, compl);
 379                         else if (is_dbg_evt(compl->flags))
 380                                 be_async_dbg_evt_process(adapter,
 381                                                          compl->flags, compl);
 382                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 383                                 status = be_mcc_compl_process(adapter, compl);
 384                                 atomic_dec(&mcc_obj->q.used);
 385                 }
 386                 be_mcc_compl_use(compl);
 387                 num++;
 388         }
 389
 390         if (num)
 391                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 392
 393         spin_unlock(&adapter->mcc_cq_lock);
 394         return status;
 395 }
 396
 397 /* Wait till no more pending mcc requests are present */
 398 static int be_mcc_wait_compl(struct be_adapter *adapter)
 399 {
 400 #define mcc_timeout             120000 /* 12s timeout */
 401         int i, status = 0;
 402         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 403
 404         for (i = 0; i < mcc_timeout; i++) {
 405                 if (be_error(adapter))
 406                         return -EIO;
 407
 408                 local_bh_disable();
 409                 status = be_process_mcc(adapter);
 410                 local_bh_enable();
 411
 412                 if (atomic_read(&mcc_obj->q.used) == 0)
 413                         break;
 414                 udelay(100);
 415         }
 416         if (i == mcc_timeout) {
 417                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 418                 adapter->fw_timeout = true;
 419                 return -EIO;
 420         }
 421         return status;
 422 }
 423
 424 /* Notify MCC requests and wait for completion */
 425 static int be_mcc_notify_wait(struct be_adapter *adapter)
 426 {
 427         int status;
 428         struct be_mcc_wrb *wrb;
 429         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 430         u16 index = mcc_obj->q.head;
 431         struct be_cmd_resp_hdr *resp;
 432
 433         index_dec(&index, mcc_obj->q.len);
 434         wrb = queue_index_node(&mcc_obj->q, index);
 435
 436         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 437
 438         be_mcc_notify(adapter);
 439
 440         status = be_mcc_wait_compl(adapter);
 441         if (status == -EIO)
 442                 goto out;
 443
 444         status = resp->status;
 445 out:
 446         return status;
 447 }
 448
 449 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 450 {
 451         int msecs = 0;
 452         u32 ready;
 453
 454         do {
 455                 if (be_error(adapter))
 456                         return -EIO;
 457
 458                 ready = ioread32(db);
 459                 if (ready == 0xffffffff)
 460                         return -1;
 461
 462                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 463                 if (ready)
 464                         break;
 465
 466                 if (msecs > 4000) {
 467                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 468                         adapter->fw_timeout = true;
 469                         be_detect_error(adapter);
 470                         return -1;
 471                 }
 472
 473                 msleep(1);
 474                 msecs++;
 475         } while (true);
 476
 477         return 0;
 478 }
 479
 480 /*
 481  * Insert the mailbox address into the doorbell in two steps
 482  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 483  */
 484 static int be_mbox_notify_wait(struct be_adapter *adapter)
 485 {
 486         int status;
 487         u32 val = 0;
 488         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 489         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 490         struct be_mcc_mailbox *mbox = mbox_mem->va;
 491         struct be_mcc_compl *compl = &mbox->compl;
 492
 493         /* wait for ready to be set */
 494         status = be_mbox_db_ready_wait(adapter, db);
 495         if (status != 0)
 496                 return status;
 497
 498         val |= MPU_MAILBOX_DB_HI_MASK;
 499         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 500         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 501         iowrite32(val, db);
 502
 503         /* wait for ready to be set */
 504         status = be_mbox_db_ready_wait(adapter, db);
 505         if (status != 0)
 506                 return status;
 507
 508         val = 0;
 509         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 510         val |= (u32)(mbox_mem->dma >> 4) << 2;
 511         iowrite32(val, db);
 512
 513         status = be_mbox_db_ready_wait(adapter, db);
 514         if (status != 0)
 515                 return status;
 516
 517         /* A cq entry has been made now */
 518         if (be_mcc_compl_is_new(compl)) {
 519                 status = be_mcc_compl_process(adapter, &mbox->compl);
 520                 be_mcc_compl_use(compl);
 521                 if (status)
 522                         return status;
 523         } else {
 524                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 525                 return -1;
 526         }
 527         return 0;
 528 }
 529
 530 static u16 be_POST_stage_get(struct be_adapter *adapter)
 531 {
 532         u32 sem;
 533
 534         if (BEx_chip(adapter))
 535                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 536         else
 537                 pci_read_config_dword(adapter->pdev,
 538                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 539
 540         return sem & POST_STAGE_MASK;
 541 }
 542
 543 static int lancer_wait_ready(struct be_adapter *adapter)
 544 {
 545 #define SLIPORT_READY_TIMEOUT 30
 546         u32 sliport_status;
 547         int status = 0, i;
 548
 549         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 550                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 551                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 552                         break;
 553
 554                 msleep(1000);
 555         }
 556
 557         if (i == SLIPORT_READY_TIMEOUT)
 558                 status = -1;
 559
 560         return status;
 561 }
 562
 563 static bool lancer_provisioning_error(struct be_adapter *adapter)
 564 {
 565         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 566         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 567         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 568                 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
 569                 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
 570
 571                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 572                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 573                         return true;
 574         }
 575         return false;
 576 }
 577
 578 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 579 {
 580         int status;
 581         u32 sliport_status, err, reset_needed;
 582         bool resource_error;
 583
 584         resource_error = lancer_provisioning_error(adapter);
 585         if (resource_error)
 586                 return -EAGAIN;
 587
 588         status = lancer_wait_ready(adapter);
 589         if (!status) {
 590                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 591                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 592                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 593                 if (err && reset_needed) {
 594                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 595                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 596
 597                         /* check adapter has corrected the error */
 598                         status = lancer_wait_ready(adapter);
 599                         sliport_status = ioread32(adapter->db +
 600                                                   SLIPORT_STATUS_OFFSET);
 601                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 602                                                 SLIPORT_STATUS_RN_MASK);
 603                         if (status || sliport_status)
 604                                 status = -1;
 605                 } else if (err || reset_needed) {
 606                         status = -1;
 607                 }
 608         }
 609         /* Stop error recovery if error is not recoverable.
 610          * No resource error is temporary errors and will go away
 611          * when PF provisions resources.
 612          */
 613         resource_error = lancer_provisioning_error(adapter);
 614         if (resource_error)
 615                 status = -EAGAIN;
 616
 617         return status;
 618 }
 619
 620 int be_fw_wait_ready(struct be_adapter *adapter)
 621 {
 622         u16 stage;
 623         int status, timeout = 0;
 624         struct device *dev = &adapter->pdev->dev;
 625
 626         if (lancer_chip(adapter)) {
 627                 status = lancer_wait_ready(adapter);
 628                 return status;
 629         }
 630
 631         do {
 632                 stage = be_POST_stage_get(adapter);
 633                 if (stage == POST_STAGE_ARMFW_RDY)
 634                         return 0;
 635
 636                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 637                 if (msleep_interruptible(2000)) {
 638                         dev_err(dev, "Waiting for POST aborted\n");
 639                         return -EINTR;
 640                 }
 641                 timeout += 2;
 642         } while (timeout < 60);
 643
 644         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 645         return -1;
 646 }
 647
 648
 649 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 650 {
 651         return &wrb->payload.sgl[0];
 652 }
 653
 654 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 655 {
 656         wrb->tag0 = addr & 0xFFFFFFFF;
 657         wrb->tag1 = upper_32_bits(addr);
 658 }
 659
 660 /* Don't touch the hdr after it's prepared */
 661 /* mem will be NULL for embedded commands */
 662 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 663                                    u8 subsystem, u8 opcode, int cmd_len,
 664                                    struct be_mcc_wrb *wrb,
 665                                    struct be_dma_mem *mem)
 666 {
 667         struct be_sge *sge;
 668
 669         req_hdr->opcode = opcode;
 670         req_hdr->subsystem = subsystem;
 671         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 672         req_hdr->version = 0;
 673         fill_wrb_tags(wrb, (ulong) req_hdr);
 674         wrb->payload_length = cmd_len;
 675         if (mem) {
 676                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 677                         MCC_WRB_SGE_CNT_SHIFT;
 678                 sge = nonembedded_sgl(wrb);
 679                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 680                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 681                 sge->len = cpu_to_le32(mem->size);
 682         } else
 683                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 684         be_dws_cpu_to_le(wrb, 8);
 685 }
 686
 687 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 688                                       struct be_dma_mem *mem)
 689 {
 690         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 691         u64 dma = (u64)mem->dma;
 692
 693         for (i = 0; i < buf_pages; i++) {
 694                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 695                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 696                 dma += PAGE_SIZE_4K;
 697         }
 698 }
 699
 700 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 701 {
 702         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 703         struct be_mcc_wrb *wrb
 704                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 705         memset(wrb, 0, sizeof(*wrb));
 706         return wrb;
 707 }
 708
 709 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 710 {
 711         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 712         struct be_mcc_wrb *wrb;
 713
 714         if (!mccq->created)
 715                 return NULL;
 716
 717         if (atomic_read(&mccq->used) >= mccq->len)
 718                 return NULL;
 719
 720         wrb = queue_head_node(mccq);
 721         queue_head_inc(mccq);
 722         atomic_inc(&mccq->used);
 723         memset(wrb, 0, sizeof(*wrb));
 724         return wrb;
 725 }
 726
 727 static bool use_mcc(struct be_adapter *adapter)
 728 {
 729         return adapter->mcc_obj.q.created;
 730 }
 731
 732 /* Must be used only in process context */
 733 static int be_cmd_lock(struct be_adapter *adapter)
 734 {
 735         if (use_mcc(adapter)) {
 736                 spin_lock_bh(&adapter->mcc_lock);
 737                 return 0;
 738         } else {
 739                 return mutex_lock_interruptible(&adapter->mbox_lock);
 740         }
 741 }
 742
 743 /* Must be used only in process context */
 744 static void be_cmd_unlock(struct be_adapter *adapter)
 745 {
 746         if (use_mcc(adapter))
 747                 spin_unlock_bh(&adapter->mcc_lock);
 748         else
 749                 return mutex_unlock(&adapter->mbox_lock);
 750 }
 751
 752 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 753                                       struct be_mcc_wrb *wrb)
 754 {
 755         struct be_mcc_wrb *dest_wrb;
 756
 757         if (use_mcc(adapter)) {
 758                 dest_wrb = wrb_from_mccq(adapter);
 759                 if (!dest_wrb)
 760                         return NULL;
 761         } else {
 762                 dest_wrb = wrb_from_mbox(adapter);
 763         }
 764
 765         memcpy(dest_wrb, wrb, sizeof(*wrb));
 766         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 767                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 768
 769         return dest_wrb;
 770 }
 771
 772 /* Must be used only in process context */
 773 static int be_cmd_notify_wait(struct be_adapter *adapter,
 774                               struct be_mcc_wrb *wrb)
 775 {
 776         struct be_mcc_wrb *dest_wrb;
 777         int status;
 778
 779         status = be_cmd_lock(adapter);
 780         if (status)
 781                 return status;
 782
 783         dest_wrb = be_cmd_copy(adapter, wrb);
 784         if (!dest_wrb)
 785                 return -EBUSY;
 786
 787         if (use_mcc(adapter))
 788                 status = be_mcc_notify_wait(adapter);
 789         else
 790                 status = be_mbox_notify_wait(adapter);
 791
 792         if (!status)
 793                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 794
 795         be_cmd_unlock(adapter);
 796         return status;
 797 }
 798
 799 /* Tell fw we're about to start firing cmds by writing a
 800  * special pattern across the wrb hdr; uses mbox
 801  */
 802 int be_cmd_fw_init(struct be_adapter *adapter)
 803 {
 804         u8 *wrb;
 805         int status;
 806
 807         if (lancer_chip(adapter))
 808                 return 0;
 809
 810         if (mutex_lock_interruptible(&adapter->mbox_lock))
 811                 return -1;
 812
 813         wrb = (u8 *)wrb_from_mbox(adapter);
 814         *wrb++ = 0xFF;
 815         *wrb++ = 0x12;
 816         *wrb++ = 0x34;
 817         *wrb++ = 0xFF;
 818         *wrb++ = 0xFF;
 819         *wrb++ = 0x56;
 820         *wrb++ = 0x78;
 821         *wrb = 0xFF;
 822
 823         status = be_mbox_notify_wait(adapter);
 824
 825         mutex_unlock(&adapter->mbox_lock);
 826         return status;
 827 }
 828
 829 /* Tell fw we're done with firing cmds by writing a
 830  * special pattern across the wrb hdr; uses mbox
 831  */
 832 int be_cmd_fw_clean(struct be_adapter *adapter)
 833 {
 834         u8 *wrb;
 835         int status;
 836
 837         if (lancer_chip(adapter))
 838                 return 0;
 839
 840         if (mutex_lock_interruptible(&adapter->mbox_lock))
 841                 return -1;
 842
 843         wrb = (u8 *)wrb_from_mbox(adapter);
 844         *wrb++ = 0xFF;
 845         *wrb++ = 0xAA;
 846         *wrb++ = 0xBB;
 847         *wrb++ = 0xFF;
 848         *wrb++ = 0xFF;
 849         *wrb++ = 0xCC;
 850         *wrb++ = 0xDD;
 851         *wrb = 0xFF;
 852
 853         status = be_mbox_notify_wait(adapter);
 854
 855         mutex_unlock(&adapter->mbox_lock);
 856         return status;
 857 }
 858
 859 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 860 {
 861         struct be_mcc_wrb *wrb;
 862         struct be_cmd_req_eq_create *req;
 863         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 864         int status, ver = 0;
 865
 866         if (mutex_lock_interruptible(&adapter->mbox_lock))
 867                 return -1;
 868
 869         wrb = wrb_from_mbox(adapter);
 870         req = embedded_payload(wrb);
 871
 872         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 873                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
 874                                NULL);
 875
 876         /* Support for EQ_CREATEv2 available only SH-R onwards */
 877         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 878                 ver = 2;
 879
 880         req->hdr.version = ver;
 881         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 882
 883         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 884         /* 4byte eqe*/
 885         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 886         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 887                       __ilog2_u32(eqo->q.len / 256));
 888         be_dws_cpu_to_le(req->context, sizeof(req->context));
 889
 890         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 891
 892         status = be_mbox_notify_wait(adapter);
 893         if (!status) {
 894                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 895                 eqo->q.id = le16_to_cpu(resp->eq_id);
 896                 eqo->msix_idx =
 897                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 898                 eqo->q.created = true;
 899         }
 900
 901         mutex_unlock(&adapter->mbox_lock);
 902         return status;
 903 }
 904
 905 /* Use MCC */
 906 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 907                           bool permanent, u32 if_handle, u32 pmac_id)
 908 {
 909         struct be_mcc_wrb *wrb;
 910         struct be_cmd_req_mac_query *req;
 911         int status;
 912
 913         spin_lock_bh(&adapter->mcc_lock);
 914
 915         wrb = wrb_from_mccq(adapter);
 916         if (!wrb) {
 917                 status = -EBUSY;
 918                 goto err;
 919         }
 920         req = embedded_payload(wrb);
 921
 922         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 923                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
 924                                NULL);
 925         req->type = MAC_ADDRESS_TYPE_NETWORK;
 926         if (permanent) {
 927                 req->permanent = 1;
 928         } else {
 929                 req->if_id = cpu_to_le16((u16) if_handle);
 930                 req->pmac_id = cpu_to_le32(pmac_id);
 931                 req->permanent = 0;
 932         }
 933
 934         status = be_mcc_notify_wait(adapter);
 935         if (!status) {
 936                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 937                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 938         }
 939
 940 err:
 941         spin_unlock_bh(&adapter->mcc_lock);
 942         return status;
 943 }
 944
 945 /* Uses synchronous MCCQ */
 946 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 947                     u32 if_id, u32 *pmac_id, u32 domain)
 948 {
 949         struct be_mcc_wrb *wrb;
 950         struct be_cmd_req_pmac_add *req;
 951         int status;
 952
 953         spin_lock_bh(&adapter->mcc_lock);
 954
 955         wrb = wrb_from_mccq(adapter);
 956         if (!wrb) {
 957                 status = -EBUSY;
 958                 goto err;
 959         }
 960         req = embedded_payload(wrb);
 961
 962         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 963                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
 964                                NULL);
 965
 966         req->hdr.domain = domain;
 967         req->if_id = cpu_to_le32(if_id);
 968         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 969
 970         status = be_mcc_notify_wait(adapter);
 971         if (!status) {
 972                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 973                 *pmac_id = le32_to_cpu(resp->pmac_id);
 974         }
 975
 976 err:
 977         spin_unlock_bh(&adapter->mcc_lock);
 978
 979          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 980                 status = -EPERM;
 981
 982         return status;
 983 }
 984
 985 /* Uses synchronous MCCQ */
 986 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 987 {
 988         struct be_mcc_wrb *wrb;
 989         struct be_cmd_req_pmac_del *req;
 990         int status;
 991
 992         if (pmac_id == -1)
 993                 return 0;
 994
 995         spin_lock_bh(&adapter->mcc_lock);
 996
 997         wrb = wrb_from_mccq(adapter);
 998         if (!wrb) {
 999                 status = -EBUSY;
1000                 goto err;
1001         }
1002         req = embedded_payload(wrb);
1003
1004         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1005                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
1006
1007         req->hdr.domain = dom;
1008         req->if_id = cpu_to_le32(if_id);
1009         req->pmac_id = cpu_to_le32(pmac_id);
1010
1011         status = be_mcc_notify_wait(adapter);
1012
1013 err:
1014         spin_unlock_bh(&adapter->mcc_lock);
1015         return status;
1016 }
1017
1018 /* Uses Mbox */
1019 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1020                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1021 {
1022         struct be_mcc_wrb *wrb;
1023         struct be_cmd_req_cq_create *req;
1024         struct be_dma_mem *q_mem = &cq->dma_mem;
1025         void *ctxt;
1026         int status;
1027
1028         if (mutex_lock_interruptible(&adapter->mbox_lock))
1029                 return -1;
1030
1031         wrb = wrb_from_mbox(adapter);
1032         req = embedded_payload(wrb);
1033         ctxt = &req->context;
1034
1035         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1036                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1037                                NULL);
1038
1039         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1040
1041         if (BEx_chip(adapter)) {
1042                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1043                               coalesce_wm);
1044                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1045                               ctxt, no_delay);
1046                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1047                               __ilog2_u32(cq->len / 256));
1048                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1049                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1050                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1051         } else {
1052                 req->hdr.version = 2;
1053                 req->page_size = 1; /* 1 for 4K */
1054
1055                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1056                  * Lancer uses COMMON_MODIFY_CQ to set this field
1057                  */
1058                 if (!lancer_chip(adapter))
1059                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1060                                       ctxt, coalesce_wm);
1061                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1062                               no_delay);
1063                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1064                               __ilog2_u32(cq->len / 256));
1065                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1066                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1067                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1068         }
1069
1070         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1071
1072         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1073
1074         status = be_mbox_notify_wait(adapter);
1075         if (!status) {
1076                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1077                 cq->id = le16_to_cpu(resp->cq_id);
1078                 cq->created = true;
1079         }
1080
1081         mutex_unlock(&adapter->mbox_lock);
1082
1083         return status;
1084 }
1085
1086 static u32 be_encoded_q_len(int q_len)
1087 {
1088         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1089         if (len_encoded == 16)
1090                 len_encoded = 0;
1091         return len_encoded;
1092 }
1093
1094 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1095                                   struct be_queue_info *mccq,
1096                                   struct be_queue_info *cq)
1097 {
1098         struct be_mcc_wrb *wrb;
1099         struct be_cmd_req_mcc_ext_create *req;
1100         struct be_dma_mem *q_mem = &mccq->dma_mem;
1101         void *ctxt;
1102         int status;
1103
1104         if (mutex_lock_interruptible(&adapter->mbox_lock))
1105                 return -1;
1106
1107         wrb = wrb_from_mbox(adapter);
1108         req = embedded_payload(wrb);
1109         ctxt = &req->context;
1110
1111         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1112                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1113                                NULL);
1114
1115         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1116         if (BEx_chip(adapter)) {
1117                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1118                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1119                               be_encoded_q_len(mccq->len));
1120                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1121         } else {
1122                 req->hdr.version = 1;
1123                 req->cq_id = cpu_to_le16(cq->id);
1124
1125                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1126                               be_encoded_q_len(mccq->len));
1127                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1128                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1129                               ctxt, cq->id);
1130                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1131                               ctxt, 1);
1132         }
1133
1134         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1135         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1136         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1137         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1138
1139         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1140
1141         status = be_mbox_notify_wait(adapter);
1142         if (!status) {
1143                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1144                 mccq->id = le16_to_cpu(resp->id);
1145                 mccq->created = true;
1146         }
1147         mutex_unlock(&adapter->mbox_lock);
1148
1149         return status;
1150 }
1151
1152 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1153                                   struct be_queue_info *mccq,
1154                                   struct be_queue_info *cq)
1155 {
1156         struct be_mcc_wrb *wrb;
1157         struct be_cmd_req_mcc_create *req;
1158         struct be_dma_mem *q_mem = &mccq->dma_mem;
1159         void *ctxt;
1160         int status;
1161
1162         if (mutex_lock_interruptible(&adapter->mbox_lock))
1163                 return -1;
1164
1165         wrb = wrb_from_mbox(adapter);
1166         req = embedded_payload(wrb);
1167         ctxt = &req->context;
1168
1169         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1170                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1171                                NULL);
1172
1173         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1174
1175         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1176         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1177                       be_encoded_q_len(mccq->len));
1178         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1179
1180         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1181
1182         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1183
1184         status = be_mbox_notify_wait(adapter);
1185         if (!status) {
1186                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1187                 mccq->id = le16_to_cpu(resp->id);
1188                 mccq->created = true;
1189         }
1190
1191         mutex_unlock(&adapter->mbox_lock);
1192         return status;
1193 }
1194
1195 int be_cmd_mccq_create(struct be_adapter *adapter,
1196                        struct be_queue_info *mccq, struct be_queue_info *cq)
1197 {
1198         int status;
1199
1200         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1201         if (status && BEx_chip(adapter)) {
1202                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1203                         "or newer to avoid conflicting priorities between NIC "
1204                         "and FCoE traffic");
1205                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1206         }
1207         return status;
1208 }
1209
1210 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1211 {
1212         struct be_mcc_wrb wrb = {0};
1213         struct be_cmd_req_eth_tx_create *req;
1214         struct be_queue_info *txq = &txo->q;
1215         struct be_queue_info *cq = &txo->cq;
1216         struct be_dma_mem *q_mem = &txq->dma_mem;
1217         int status, ver = 0;
1218
1219         req = embedded_payload(&wrb);
1220         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1221                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1222
1223         if (lancer_chip(adapter)) {
1224                 req->hdr.version = 1;
1225         } else if (BEx_chip(adapter)) {
1226                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1227                         req->hdr.version = 2;
1228         } else { /* For SH */
1229                 req->hdr.version = 2;
1230         }
1231
1232         if (req->hdr.version > 0)
1233                 req->if_id = cpu_to_le16(adapter->if_handle);
1234         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1235         req->ulp_num = BE_ULP1_NUM;
1236         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1237         req->cq_id = cpu_to_le16(cq->id);
1238         req->queue_size = be_encoded_q_len(txq->len);
1239         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1240         ver = req->hdr.version;
1241
1242         status = be_cmd_notify_wait(adapter, &wrb);
1243         if (!status) {
1244                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1245                 txq->id = le16_to_cpu(resp->cid);
1246                 if (ver == 2)
1247                         txo->db_offset = le32_to_cpu(resp->db_offset);
1248                 else
1249                         txo->db_offset = DB_TXULP1_OFFSET;
1250                 txq->created = true;
1251         }
1252
1253         return status;
1254 }
1255
1256 /* Uses MCC */
1257 int be_cmd_rxq_create(struct be_adapter *adapter,
1258                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1259                       u32 if_id, u32 rss, u8 *rss_id)
1260 {
1261         struct be_mcc_wrb *wrb;
1262         struct be_cmd_req_eth_rx_create *req;
1263         struct be_dma_mem *q_mem = &rxq->dma_mem;
1264         int status;
1265
1266         spin_lock_bh(&adapter->mcc_lock);
1267
1268         wrb = wrb_from_mccq(adapter);
1269         if (!wrb) {
1270                 status = -EBUSY;
1271                 goto err;
1272         }
1273         req = embedded_payload(wrb);
1274
1275         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1276                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1277
1278         req->cq_id = cpu_to_le16(cq_id);
1279         req->frag_size = fls(frag_size) - 1;
1280         req->num_pages = 2;
1281         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1282         req->interface_id = cpu_to_le32(if_id);
1283         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1284         req->rss_queue = cpu_to_le32(rss);
1285
1286         status = be_mcc_notify_wait(adapter);
1287         if (!status) {
1288                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1289                 rxq->id = le16_to_cpu(resp->id);
1290                 rxq->created = true;
1291                 *rss_id = resp->rss_id;
1292         }
1293
1294 err:
1295         spin_unlock_bh(&adapter->mcc_lock);
1296         return status;
1297 }
1298
1299 /* Generic destroyer function for all types of queues
1300  * Uses Mbox
1301  */
1302 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1303                      int queue_type)
1304 {
1305         struct be_mcc_wrb *wrb;
1306         struct be_cmd_req_q_destroy *req;
1307         u8 subsys = 0, opcode = 0;
1308         int status;
1309
1310         if (mutex_lock_interruptible(&adapter->mbox_lock))
1311                 return -1;
1312
1313         wrb = wrb_from_mbox(adapter);
1314         req = embedded_payload(wrb);
1315
1316         switch (queue_type) {
1317         case QTYPE_EQ:
1318                 subsys = CMD_SUBSYSTEM_COMMON;
1319                 opcode = OPCODE_COMMON_EQ_DESTROY;
1320                 break;
1321         case QTYPE_CQ:
1322                 subsys = CMD_SUBSYSTEM_COMMON;
1323                 opcode = OPCODE_COMMON_CQ_DESTROY;
1324                 break;
1325         case QTYPE_TXQ:
1326                 subsys = CMD_SUBSYSTEM_ETH;
1327                 opcode = OPCODE_ETH_TX_DESTROY;
1328                 break;
1329         case QTYPE_RXQ:
1330                 subsys = CMD_SUBSYSTEM_ETH;
1331                 opcode = OPCODE_ETH_RX_DESTROY;
1332                 break;
1333         case QTYPE_MCCQ:
1334                 subsys = CMD_SUBSYSTEM_COMMON;
1335                 opcode = OPCODE_COMMON_MCC_DESTROY;
1336                 break;
1337         default:
1338                 BUG();
1339         }
1340
1341         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1342                                NULL);
1343         req->id = cpu_to_le16(q->id);
1344
1345         status = be_mbox_notify_wait(adapter);
1346         q->created = false;
1347
1348         mutex_unlock(&adapter->mbox_lock);
1349         return status;
1350 }
1351
1352 /* Uses MCC */
1353 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1354 {
1355         struct be_mcc_wrb *wrb;
1356         struct be_cmd_req_q_destroy *req;
1357         int status;
1358
1359         spin_lock_bh(&adapter->mcc_lock);
1360
1361         wrb = wrb_from_mccq(adapter);
1362         if (!wrb) {
1363                 status = -EBUSY;
1364                 goto err;
1365         }
1366         req = embedded_payload(wrb);
1367
1368         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1369                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1370         req->id = cpu_to_le16(q->id);
1371
1372         status = be_mcc_notify_wait(adapter);
1373         q->created = false;
1374
1375 err:
1376         spin_unlock_bh(&adapter->mcc_lock);
1377         return status;
1378 }
1379
1380 /* Create an rx filtering policy configuration on an i/f
1381  * Will use MBOX only if MCCQ has not been created.
1382  */
1383 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1384                      u32 *if_handle, u32 domain)
1385 {
1386         struct be_mcc_wrb wrb = {0};
1387         struct be_cmd_req_if_create *req;
1388         int status;
1389
1390         req = embedded_payload(&wrb);
1391         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1392                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1393                                sizeof(*req), &wrb, NULL);
1394         req->hdr.domain = domain;
1395         req->capability_flags = cpu_to_le32(cap_flags);
1396         req->enable_flags = cpu_to_le32(en_flags);
1397         req->pmac_invalid = true;
1398
1399         status = be_cmd_notify_wait(adapter, &wrb);
1400         if (!status) {
1401                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1402                 *if_handle = le32_to_cpu(resp->interface_id);
1403
1404                 /* Hack to retrieve VF's pmac-id on BE3 */
1405                 if (BE3_chip(adapter) && !be_physfn(adapter))
1406                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1407         }
1408         return status;
1409 }
1410
1411 /* Uses MCCQ */
1412 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1413 {
1414         struct be_mcc_wrb *wrb;
1415         struct be_cmd_req_if_destroy *req;
1416         int status;
1417
1418         if (interface_id == -1)
1419                 return 0;
1420
1421         spin_lock_bh(&adapter->mcc_lock);
1422
1423         wrb = wrb_from_mccq(adapter);
1424         if (!wrb) {
1425                 status = -EBUSY;
1426                 goto err;
1427         }
1428         req = embedded_payload(wrb);
1429
1430         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1431                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1432                                sizeof(*req), wrb, NULL);
1433         req->hdr.domain = domain;
1434         req->interface_id = cpu_to_le32(interface_id);
1435
1436         status = be_mcc_notify_wait(adapter);
1437 err:
1438         spin_unlock_bh(&adapter->mcc_lock);
1439         return status;
1440 }
1441
1442 /* Get stats is a non embedded command: the request is not embedded inside
1443  * WRB but is a separate dma memory block
1444  * Uses asynchronous MCC
1445  */
1446 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1447 {
1448         struct be_mcc_wrb *wrb;
1449         struct be_cmd_req_hdr *hdr;
1450         int status = 0;
1451
1452         spin_lock_bh(&adapter->mcc_lock);
1453
1454         wrb = wrb_from_mccq(adapter);
1455         if (!wrb) {
1456                 status = -EBUSY;
1457                 goto err;
1458         }
1459         hdr = nonemb_cmd->va;
1460
1461         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1462                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1463                                nonemb_cmd);
1464
1465         /* version 1 of the cmd is not supported only by BE2 */
1466         if (BE2_chip(adapter))
1467                 hdr->version = 0;
1468         if (BE3_chip(adapter) || lancer_chip(adapter))
1469                 hdr->version = 1;
1470         else
1471                 hdr->version = 2;
1472
1473         be_mcc_notify(adapter);
1474         adapter->stats_cmd_sent = true;
1475
1476 err:
1477         spin_unlock_bh(&adapter->mcc_lock);
1478         return status;
1479 }
1480
1481 /* Lancer Stats */
1482 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1483                                struct be_dma_mem *nonemb_cmd)
1484 {
1485
1486         struct be_mcc_wrb *wrb;
1487         struct lancer_cmd_req_pport_stats *req;
1488         int status = 0;
1489
1490         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1491                             CMD_SUBSYSTEM_ETH))
1492                 return -EPERM;
1493
1494         spin_lock_bh(&adapter->mcc_lock);
1495
1496         wrb = wrb_from_mccq(adapter);
1497         if (!wrb) {
1498                 status = -EBUSY;
1499                 goto err;
1500         }
1501         req = nonemb_cmd->va;
1502
1503         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1504                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1505                                wrb, nonemb_cmd);
1506
1507         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1508         req->cmd_params.params.reset_stats = 0;
1509
1510         be_mcc_notify(adapter);
1511         adapter->stats_cmd_sent = true;
1512
1513 err:
1514         spin_unlock_bh(&adapter->mcc_lock);
1515         return status;
1516 }
1517
1518 static int be_mac_to_link_speed(int mac_speed)
1519 {
1520         switch (mac_speed) {
1521         case PHY_LINK_SPEED_ZERO:
1522                 return 0;
1523         case PHY_LINK_SPEED_10MBPS:
1524                 return 10;
1525         case PHY_LINK_SPEED_100MBPS:
1526                 return 100;
1527         case PHY_LINK_SPEED_1GBPS:
1528                 return 1000;
1529         case PHY_LINK_SPEED_10GBPS:
1530                 return 10000;
1531         case PHY_LINK_SPEED_20GBPS:
1532                 return 20000;
1533         case PHY_LINK_SPEED_25GBPS:
1534                 return 25000;
1535         case PHY_LINK_SPEED_40GBPS:
1536                 return 40000;
1537         }
1538         return 0;
1539 }
1540
1541 /* Uses synchronous mcc
1542  * Returns link_speed in Mbps
1543  */
1544 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1545                              u8 *link_status, u32 dom)
1546 {
1547         struct be_mcc_wrb *wrb;
1548         struct be_cmd_req_link_status *req;
1549         int status;
1550
1551         spin_lock_bh(&adapter->mcc_lock);
1552
1553         if (link_status)
1554                 *link_status = LINK_DOWN;
1555
1556         wrb = wrb_from_mccq(adapter);
1557         if (!wrb) {
1558                 status = -EBUSY;
1559                 goto err;
1560         }
1561         req = embedded_payload(wrb);
1562
1563         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1564                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1565                                sizeof(*req), wrb, NULL);
1566
1567         /* version 1 of the cmd is not supported only by BE2 */
1568         if (!BE2_chip(adapter))
1569                 req->hdr.version = 1;
1570
1571         req->hdr.domain = dom;
1572
1573         status = be_mcc_notify_wait(adapter);
1574         if (!status) {
1575                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1576                 if (link_speed) {
1577                         *link_speed = resp->link_speed ?
1578                                       le16_to_cpu(resp->link_speed) * 10 :
1579                                       be_mac_to_link_speed(resp->mac_speed);
1580
1581                         if (!resp->logical_link_status)
1582                                 *link_speed = 0;
1583                 }
1584                 if (link_status)
1585                         *link_status = resp->logical_link_status;
1586         }
1587
1588 err:
1589         spin_unlock_bh(&adapter->mcc_lock);
1590         return status;
1591 }
1592
1593 /* Uses synchronous mcc */
1594 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1595 {
1596         struct be_mcc_wrb *wrb;
1597         struct be_cmd_req_get_cntl_addnl_attribs *req;
1598         int status = 0;
1599
1600         spin_lock_bh(&adapter->mcc_lock);
1601
1602         wrb = wrb_from_mccq(adapter);
1603         if (!wrb) {
1604                 status = -EBUSY;
1605                 goto err;
1606         }
1607         req = embedded_payload(wrb);
1608
1609         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1610                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1611                                sizeof(*req), wrb, NULL);
1612
1613         be_mcc_notify(adapter);
1614
1615 err:
1616         spin_unlock_bh(&adapter->mcc_lock);
1617         return status;
1618 }
1619
1620 /* Uses synchronous mcc */
1621 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1622 {
1623         struct be_mcc_wrb *wrb;
1624         struct be_cmd_req_get_fat *req;
1625         int status;
1626
1627         spin_lock_bh(&adapter->mcc_lock);
1628
1629         wrb = wrb_from_mccq(adapter);
1630         if (!wrb) {
1631                 status = -EBUSY;
1632                 goto err;
1633         }
1634         req = embedded_payload(wrb);
1635
1636         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1637                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1638                                NULL);
1639         req->fat_operation = cpu_to_le32(QUERY_FAT);
1640         status = be_mcc_notify_wait(adapter);
1641         if (!status) {
1642                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1643                 if (log_size && resp->log_size)
1644                         *log_size = le32_to_cpu(resp->log_size) -
1645                                         sizeof(u32);
1646         }
1647 err:
1648         spin_unlock_bh(&adapter->mcc_lock);
1649         return status;
1650 }
1651
1652 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1653 {
1654         struct be_dma_mem get_fat_cmd;
1655         struct be_mcc_wrb *wrb;
1656         struct be_cmd_req_get_fat *req;
1657         u32 offset = 0, total_size, buf_size,
1658                                 log_offset = sizeof(u32), payload_len;
1659         int status;
1660
1661         if (buf_len == 0)
1662                 return;
1663
1664         total_size = buf_len;
1665
1666         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1667         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1668                                               get_fat_cmd.size,
1669                                               &get_fat_cmd.dma);
1670         if (!get_fat_cmd.va) {
1671                 status = -ENOMEM;
1672                 dev_err(&adapter->pdev->dev,
1673                 "Memory allocation failure while retrieving FAT data\n");
1674                 return;
1675         }
1676
1677         spin_lock_bh(&adapter->mcc_lock);
1678
1679         while (total_size) {
1680                 buf_size = min(total_size, (u32)60*1024);
1681                 total_size -= buf_size;
1682
1683                 wrb = wrb_from_mccq(adapter);
1684                 if (!wrb) {
1685                         status = -EBUSY;
1686                         goto err;
1687                 }
1688                 req = get_fat_cmd.va;
1689
1690                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1691                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1692                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1693                                        wrb, &get_fat_cmd);
1694
1695                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1696                 req->read_log_offset = cpu_to_le32(log_offset);
1697                 req->read_log_length = cpu_to_le32(buf_size);
1698                 req->data_buffer_size = cpu_to_le32(buf_size);
1699
1700                 status = be_mcc_notify_wait(adapter);
1701                 if (!status) {
1702                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1703                         memcpy(buf + offset,
1704                                resp->data_buffer,
1705                                le32_to_cpu(resp->read_log_length));
1706                 } else {
1707                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1708                         goto err;
1709                 }
1710                 offset += buf_size;
1711                 log_offset += buf_size;
1712         }
1713 err:
1714         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1715                             get_fat_cmd.va, get_fat_cmd.dma);
1716         spin_unlock_bh(&adapter->mcc_lock);
1717 }
1718
1719 /* Uses synchronous mcc */
1720 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1721                       char *fw_on_flash)
1722 {
1723         struct be_mcc_wrb *wrb;
1724         struct be_cmd_req_get_fw_version *req;
1725         int status;
1726
1727         spin_lock_bh(&adapter->mcc_lock);
1728
1729         wrb = wrb_from_mccq(adapter);
1730         if (!wrb) {
1731                 status = -EBUSY;
1732                 goto err;
1733         }
1734
1735         req = embedded_payload(wrb);
1736
1737         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1738                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1739                                NULL);
1740         status = be_mcc_notify_wait(adapter);
1741         if (!status) {
1742                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1743                 strcpy(fw_ver, resp->firmware_version_string);
1744                 if (fw_on_flash)
1745                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1746         }
1747 err:
1748         spin_unlock_bh(&adapter->mcc_lock);
1749         return status;
1750 }
1751
1752 /* set the EQ delay interval of an EQ to specified value
1753  * Uses async mcc
1754  */
1755 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1756                       int num)
1757 {
1758         struct be_mcc_wrb *wrb;
1759         struct be_cmd_req_modify_eq_delay *req;
1760         int status = 0, i;
1761
1762         spin_lock_bh(&adapter->mcc_lock);
1763
1764         wrb = wrb_from_mccq(adapter);
1765         if (!wrb) {
1766                 status = -EBUSY;
1767                 goto err;
1768         }
1769         req = embedded_payload(wrb);
1770
1771         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1772                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1773                                NULL);
1774
1775         req->num_eq = cpu_to_le32(num);
1776         for (i = 0; i < num; i++) {
1777                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1778                 req->set_eqd[i].phase = 0;
1779                 req->set_eqd[i].delay_multiplier =
1780                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1781         }
1782
1783         be_mcc_notify(adapter);
1784 err:
1785         spin_unlock_bh(&adapter->mcc_lock);
1786         return status;
1787 }
1788
1789 /* Uses sycnhronous mcc */
1790 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1791                        u32 num)
1792 {
1793         struct be_mcc_wrb *wrb;
1794         struct be_cmd_req_vlan_config *req;
1795         int status;
1796
1797         spin_lock_bh(&adapter->mcc_lock);
1798
1799         wrb = wrb_from_mccq(adapter);
1800         if (!wrb) {
1801                 status = -EBUSY;
1802                 goto err;
1803         }
1804         req = embedded_payload(wrb);
1805
1806         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1807                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1808                                wrb, NULL);
1809
1810         req->interface_id = if_id;
1811         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1812         req->num_vlan = num;
1813         memcpy(req->normal_vlan, vtag_array,
1814                req->num_vlan * sizeof(vtag_array[0]));
1815
1816         status = be_mcc_notify_wait(adapter);
1817 err:
1818         spin_unlock_bh(&adapter->mcc_lock);
1819         return status;
1820 }
1821
1822 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1823 {
1824         struct be_mcc_wrb *wrb;
1825         struct be_dma_mem *mem = &adapter->rx_filter;
1826         struct be_cmd_req_rx_filter *req = mem->va;
1827         int status;
1828
1829         spin_lock_bh(&adapter->mcc_lock);
1830
1831         wrb = wrb_from_mccq(adapter);
1832         if (!wrb) {
1833                 status = -EBUSY;
1834                 goto err;
1835         }
1836         memset(req, 0, sizeof(*req));
1837         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1838                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1839                                wrb, mem);
1840
1841         req->if_id = cpu_to_le32(adapter->if_handle);
1842         if (flags & IFF_PROMISC) {
1843                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1844                                                  BE_IF_FLAGS_VLAN_PROMISCUOUS |
1845                                                  BE_IF_FLAGS_MCAST_PROMISCUOUS);
1846                 if (value == ON)
1847                         req->if_flags =
1848                                 cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1849                                             BE_IF_FLAGS_VLAN_PROMISCUOUS |
1850                                             BE_IF_FLAGS_MCAST_PROMISCUOUS);
1851         } else if (flags & IFF_ALLMULTI) {
1852                 req->if_flags_mask = req->if_flags =
1853                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1854         } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1855                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1856
1857                 if (value == ON)
1858                         req->if_flags =
1859                                 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1860         } else {
1861                 struct netdev_hw_addr *ha;
1862                 int i = 0;
1863
1864                 req->if_flags_mask = req->if_flags =
1865                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1866
1867                 /* Reset mcast promisc mode if already set by setting mask
1868                  * and not setting flags field
1869                  */
1870                 req->if_flags_mask |=
1871                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1872                                     be_if_cap_flags(adapter));
1873                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1874                 netdev_for_each_mc_addr(ha, adapter->netdev)
1875                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1876         }
1877
1878         if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1879             req->if_flags_mask) {
1880                 dev_warn(&adapter->pdev->dev,
1881                          "Cannot set rx filter flags 0x%x\n",
1882                          req->if_flags_mask);
1883                 dev_warn(&adapter->pdev->dev,
1884                          "Interface is capable of 0x%x flags only\n",
1885                          be_if_cap_flags(adapter));
1886         }
1887         req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1888
1889         status = be_mcc_notify_wait(adapter);
1890
1891 err:
1892         spin_unlock_bh(&adapter->mcc_lock);
1893         return status;
1894 }
1895
1896 /* Uses synchrounous mcc */
1897 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1898 {
1899         struct be_mcc_wrb *wrb;
1900         struct be_cmd_req_set_flow_control *req;
1901         int status;
1902
1903         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1904                             CMD_SUBSYSTEM_COMMON))
1905                 return -EPERM;
1906
1907         spin_lock_bh(&adapter->mcc_lock);
1908
1909         wrb = wrb_from_mccq(adapter);
1910         if (!wrb) {
1911                 status = -EBUSY;
1912                 goto err;
1913         }
1914         req = embedded_payload(wrb);
1915
1916         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1917                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1918                                wrb, NULL);
1919
1920         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1921         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1922
1923         status = be_mcc_notify_wait(adapter);
1924
1925 err:
1926         spin_unlock_bh(&adapter->mcc_lock);
1927         return status;
1928 }
1929
1930 /* Uses sycn mcc */
1931 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1932 {
1933         struct be_mcc_wrb *wrb;
1934         struct be_cmd_req_get_flow_control *req;
1935         int status;
1936
1937         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1938                             CMD_SUBSYSTEM_COMMON))
1939                 return -EPERM;
1940
1941         spin_lock_bh(&adapter->mcc_lock);
1942
1943         wrb = wrb_from_mccq(adapter);
1944         if (!wrb) {
1945                 status = -EBUSY;
1946                 goto err;
1947         }
1948         req = embedded_payload(wrb);
1949
1950         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1951                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
1952                                wrb, NULL);
1953
1954         status = be_mcc_notify_wait(adapter);
1955         if (!status) {
1956                 struct be_cmd_resp_get_flow_control *resp =
1957                                                 embedded_payload(wrb);
1958                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1959                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1960         }
1961
1962 err:
1963         spin_unlock_bh(&adapter->mcc_lock);
1964         return status;
1965 }
1966
1967 /* Uses mbox */
1968 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1969                         u32 *mode, u32 *caps, u16 *asic_rev)
1970 {
1971         struct be_mcc_wrb *wrb;
1972         struct be_cmd_req_query_fw_cfg *req;
1973         int status;
1974
1975         if (mutex_lock_interruptible(&adapter->mbox_lock))
1976                 return -1;
1977
1978         wrb = wrb_from_mbox(adapter);
1979         req = embedded_payload(wrb);
1980
1981         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1982                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
1983                                sizeof(*req), wrb, NULL);
1984
1985         status = be_mbox_notify_wait(adapter);
1986         if (!status) {
1987                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1988                 *port_num = le32_to_cpu(resp->phys_port);
1989                 *mode = le32_to_cpu(resp->function_mode);
1990                 *caps = le32_to_cpu(resp->function_caps);
1991                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1992         }
1993
1994         mutex_unlock(&adapter->mbox_lock);
1995         return status;
1996 }
1997
1998 /* Uses mbox */
1999 int be_cmd_reset_function(struct be_adapter *adapter)
2000 {
2001         struct be_mcc_wrb *wrb;
2002         struct be_cmd_req_hdr *req;
2003         int status;
2004
2005         if (lancer_chip(adapter)) {
2006                 status = lancer_wait_ready(adapter);
2007                 if (!status) {
2008                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
2009                                   adapter->db + SLIPORT_CONTROL_OFFSET);
2010                         status = lancer_test_and_set_rdy_state(adapter);
2011                 }
2012                 if (status) {
2013                         dev_err(&adapter->pdev->dev,
2014                                 "Adapter in non recoverable error\n");
2015                 }
2016                 return status;
2017         }
2018
2019         if (mutex_lock_interruptible(&adapter->mbox_lock))
2020                 return -1;
2021
2022         wrb = wrb_from_mbox(adapter);
2023         req = embedded_payload(wrb);
2024
2025         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2026                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2027                                NULL);
2028
2029         status = be_mbox_notify_wait(adapter);
2030
2031         mutex_unlock(&adapter->mbox_lock);
2032         return status;
2033 }
2034
2035 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2036                       u32 rss_hash_opts, u16 table_size, u8 *rss_hkey)
2037 {
2038         struct be_mcc_wrb *wrb;
2039         struct be_cmd_req_rss_config *req;
2040         int status;
2041
2042         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2043                 return 0;
2044
2045         spin_lock_bh(&adapter->mcc_lock);
2046
2047         wrb = wrb_from_mccq(adapter);
2048         if (!wrb) {
2049                 status = -EBUSY;
2050                 goto err;
2051         }
2052         req = embedded_payload(wrb);
2053
2054         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2055                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2056
2057         req->if_id = cpu_to_le32(adapter->if_handle);
2058         req->enable_rss = cpu_to_le16(rss_hash_opts);
2059         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2060
2061         if (!BEx_chip(adapter))
2062                 req->hdr.version = 1;
2063
2064         memcpy(req->cpu_table, rsstable, table_size);
2065         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2066         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2067
2068         status = be_mcc_notify_wait(adapter);
2069 err:
2070         spin_unlock_bh(&adapter->mcc_lock);
2071         return status;
2072 }
2073
2074 /* Uses sync mcc */
2075 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2076                             u8 bcn, u8 sts, u8 state)
2077 {
2078         struct be_mcc_wrb *wrb;
2079         struct be_cmd_req_enable_disable_beacon *req;
2080         int status;
2081
2082         spin_lock_bh(&adapter->mcc_lock);
2083
2084         wrb = wrb_from_mccq(adapter);
2085         if (!wrb) {
2086                 status = -EBUSY;
2087                 goto err;
2088         }
2089         req = embedded_payload(wrb);
2090
2091         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2092                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2093                                sizeof(*req), wrb, NULL);
2094
2095         req->port_num = port_num;
2096         req->beacon_state = state;
2097         req->beacon_duration = bcn;
2098         req->status_duration = sts;
2099
2100         status = be_mcc_notify_wait(adapter);
2101
2102 err:
2103         spin_unlock_bh(&adapter->mcc_lock);
2104         return status;
2105 }
2106
2107 /* Uses sync mcc */
2108 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2109 {
2110         struct be_mcc_wrb *wrb;
2111         struct be_cmd_req_get_beacon_state *req;
2112         int status;
2113
2114         spin_lock_bh(&adapter->mcc_lock);
2115
2116         wrb = wrb_from_mccq(adapter);
2117         if (!wrb) {
2118                 status = -EBUSY;
2119                 goto err;
2120         }
2121         req = embedded_payload(wrb);
2122
2123         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2124                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2125                                wrb, NULL);
2126
2127         req->port_num = port_num;
2128
2129         status = be_mcc_notify_wait(adapter);
2130         if (!status) {
2131                 struct be_cmd_resp_get_beacon_state *resp =
2132                                                 embedded_payload(wrb);
2133                 *state = resp->beacon_state;
2134         }
2135
2136 err:
2137         spin_unlock_bh(&adapter->mcc_lock);
2138         return status;
2139 }
2140
2141 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2142                             u32 data_size, u32 data_offset,
2143                             const char *obj_name, u32 *data_written,
2144                             u8 *change_status, u8 *addn_status)
2145 {
2146         struct be_mcc_wrb *wrb;
2147         struct lancer_cmd_req_write_object *req;
2148         struct lancer_cmd_resp_write_object *resp;
2149         void *ctxt = NULL;
2150         int status;
2151
2152         spin_lock_bh(&adapter->mcc_lock);
2153         adapter->flash_status = 0;
2154
2155         wrb = wrb_from_mccq(adapter);
2156         if (!wrb) {
2157                 status = -EBUSY;
2158                 goto err_unlock;
2159         }
2160
2161         req = embedded_payload(wrb);
2162
2163         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2164                                OPCODE_COMMON_WRITE_OBJECT,
2165                                sizeof(struct lancer_cmd_req_write_object), wrb,
2166                                NULL);
2167
2168         ctxt = &req->context;
2169         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2170                       write_length, ctxt, data_size);
2171
2172         if (data_size == 0)
2173                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2174                               eof, ctxt, 1);
2175         else
2176                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2177                               eof, ctxt, 0);
2178
2179         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2180         req->write_offset = cpu_to_le32(data_offset);
2181         strcpy(req->object_name, obj_name);
2182         req->descriptor_count = cpu_to_le32(1);
2183         req->buf_len = cpu_to_le32(data_size);
2184         req->addr_low = cpu_to_le32((cmd->dma +
2185                                      sizeof(struct lancer_cmd_req_write_object))
2186                                     & 0xFFFFFFFF);
2187         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2188                                 sizeof(struct lancer_cmd_req_write_object)));
2189
2190         be_mcc_notify(adapter);
2191         spin_unlock_bh(&adapter->mcc_lock);
2192
2193         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2194                                          msecs_to_jiffies(60000)))
2195                 status = -1;
2196         else
2197                 status = adapter->flash_status;
2198
2199         resp = embedded_payload(wrb);
2200         if (!status) {
2201                 *data_written = le32_to_cpu(resp->actual_write_len);
2202                 *change_status = resp->change_status;
2203         } else {
2204                 *addn_status = resp->additional_status;
2205         }
2206
2207         return status;
2208
2209 err_unlock:
2210         spin_unlock_bh(&adapter->mcc_lock);
2211         return status;
2212 }
2213
2214 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2215                            u32 data_size, u32 data_offset, const char *obj_name,
2216                            u32 *data_read, u32 *eof, u8 *addn_status)
2217 {
2218         struct be_mcc_wrb *wrb;
2219         struct lancer_cmd_req_read_object *req;
2220         struct lancer_cmd_resp_read_object *resp;
2221         int status;
2222
2223         spin_lock_bh(&adapter->mcc_lock);
2224
2225         wrb = wrb_from_mccq(adapter);
2226         if (!wrb) {
2227                 status = -EBUSY;
2228                 goto err_unlock;
2229         }
2230
2231         req = embedded_payload(wrb);
2232
2233         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2234                                OPCODE_COMMON_READ_OBJECT,
2235                                sizeof(struct lancer_cmd_req_read_object), wrb,
2236                                NULL);
2237
2238         req->desired_read_len = cpu_to_le32(data_size);
2239         req->read_offset = cpu_to_le32(data_offset);
2240         strcpy(req->object_name, obj_name);
2241         req->descriptor_count = cpu_to_le32(1);
2242         req->buf_len = cpu_to_le32(data_size);
2243         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2244         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2245
2246         status = be_mcc_notify_wait(adapter);
2247
2248         resp = embedded_payload(wrb);
2249         if (!status) {
2250                 *data_read = le32_to_cpu(resp->actual_read_len);
2251                 *eof = le32_to_cpu(resp->eof);
2252         } else {
2253                 *addn_status = resp->additional_status;
2254         }
2255
2256 err_unlock:
2257         spin_unlock_bh(&adapter->mcc_lock);
2258         return status;
2259 }
2260
2261 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2262                           u32 flash_type, u32 flash_opcode, u32 buf_size)
2263 {
2264         struct be_mcc_wrb *wrb;
2265         struct be_cmd_write_flashrom *req;
2266         int status;
2267
2268         spin_lock_bh(&adapter->mcc_lock);
2269         adapter->flash_status = 0;
2270
2271         wrb = wrb_from_mccq(adapter);
2272         if (!wrb) {
2273                 status = -EBUSY;
2274                 goto err_unlock;
2275         }
2276         req = cmd->va;
2277
2278         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2279                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2280                                cmd);
2281
2282         req->params.op_type = cpu_to_le32(flash_type);
2283         req->params.op_code = cpu_to_le32(flash_opcode);
2284         req->params.data_buf_size = cpu_to_le32(buf_size);
2285
2286         be_mcc_notify(adapter);
2287         spin_unlock_bh(&adapter->mcc_lock);
2288
2289         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2290                                          msecs_to_jiffies(40000)))
2291                 status = -1;
2292         else
2293                 status = adapter->flash_status;
2294
2295         return status;
2296
2297 err_unlock:
2298         spin_unlock_bh(&adapter->mcc_lock);
2299         return status;
2300 }
2301
2302 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2303                          int offset)
2304 {
2305         struct be_mcc_wrb *wrb;
2306         struct be_cmd_read_flash_crc *req;
2307         int status;
2308
2309         spin_lock_bh(&adapter->mcc_lock);
2310
2311         wrb = wrb_from_mccq(adapter);
2312         if (!wrb) {
2313                 status = -EBUSY;
2314                 goto err;
2315         }
2316         req = embedded_payload(wrb);
2317
2318         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2319                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2320                                wrb, NULL);
2321
2322         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2323         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2324         req->params.offset = cpu_to_le32(offset);
2325         req->params.data_buf_size = cpu_to_le32(0x4);
2326
2327         status = be_mcc_notify_wait(adapter);
2328         if (!status)
2329                 memcpy(flashed_crc, req->crc, 4);
2330
2331 err:
2332         spin_unlock_bh(&adapter->mcc_lock);
2333         return status;
2334 }
2335
2336 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2337                             struct be_dma_mem *nonemb_cmd)
2338 {
2339         struct be_mcc_wrb *wrb;
2340         struct be_cmd_req_acpi_wol_magic_config *req;
2341         int status;
2342
2343         spin_lock_bh(&adapter->mcc_lock);
2344
2345         wrb = wrb_from_mccq(adapter);
2346         if (!wrb) {
2347                 status = -EBUSY;
2348                 goto err;
2349         }
2350         req = nonemb_cmd->va;
2351
2352         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2353                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2354                                wrb, nonemb_cmd);
2355         memcpy(req->magic_mac, mac, ETH_ALEN);
2356
2357         status = be_mcc_notify_wait(adapter);
2358
2359 err:
2360         spin_unlock_bh(&adapter->mcc_lock);
2361         return status;
2362 }
2363
2364 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2365                         u8 loopback_type, u8 enable)
2366 {
2367         struct be_mcc_wrb *wrb;
2368         struct be_cmd_req_set_lmode *req;
2369         int status;
2370
2371         spin_lock_bh(&adapter->mcc_lock);
2372
2373         wrb = wrb_from_mccq(adapter);
2374         if (!wrb) {
2375                 status = -EBUSY;
2376                 goto err;
2377         }
2378
2379         req = embedded_payload(wrb);
2380
2381         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2382                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2383                                wrb, NULL);
2384
2385         req->src_port = port_num;
2386         req->dest_port = port_num;
2387         req->loopback_type = loopback_type;
2388         req->loopback_state = enable;
2389
2390         status = be_mcc_notify_wait(adapter);
2391 err:
2392         spin_unlock_bh(&adapter->mcc_lock);
2393         return status;
2394 }
2395
2396 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2397                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
2398                          u64 pattern)
2399 {
2400         struct be_mcc_wrb *wrb;
2401         struct be_cmd_req_loopback_test *req;
2402         struct be_cmd_resp_loopback_test *resp;
2403         int status;
2404
2405         spin_lock_bh(&adapter->mcc_lock);
2406
2407         wrb = wrb_from_mccq(adapter);
2408         if (!wrb) {
2409                 status = -EBUSY;
2410                 goto err;
2411         }
2412
2413         req = embedded_payload(wrb);
2414
2415         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2416                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2417                                NULL);
2418
2419         req->hdr.timeout = cpu_to_le32(15);
2420         req->pattern = cpu_to_le64(pattern);
2421         req->src_port = cpu_to_le32(port_num);
2422         req->dest_port = cpu_to_le32(port_num);
2423         req->pkt_size = cpu_to_le32(pkt_size);
2424         req->num_pkts = cpu_to_le32(num_pkts);
2425         req->loopback_type = cpu_to_le32(loopback_type);
2426
2427         be_mcc_notify(adapter);
2428
2429         spin_unlock_bh(&adapter->mcc_lock);
2430
2431         wait_for_completion(&adapter->et_cmd_compl);
2432         resp = embedded_payload(wrb);
2433         status = le32_to_cpu(resp->status);
2434
2435         return status;
2436 err:
2437         spin_unlock_bh(&adapter->mcc_lock);
2438         return status;
2439 }
2440
2441 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2442                         u32 byte_cnt, struct be_dma_mem *cmd)
2443 {
2444         struct be_mcc_wrb *wrb;
2445         struct be_cmd_req_ddrdma_test *req;
2446         int status;
2447         int i, j = 0;
2448
2449         spin_lock_bh(&adapter->mcc_lock);
2450
2451         wrb = wrb_from_mccq(adapter);
2452         if (!wrb) {
2453                 status = -EBUSY;
2454                 goto err;
2455         }
2456         req = cmd->va;
2457         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2458                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2459                                cmd);
2460
2461         req->pattern = cpu_to_le64(pattern);
2462         req->byte_count = cpu_to_le32(byte_cnt);
2463         for (i = 0; i < byte_cnt; i++) {
2464                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2465                 j++;
2466                 if (j > 7)
2467                         j = 0;
2468         }
2469
2470         status = be_mcc_notify_wait(adapter);
2471
2472         if (!status) {
2473                 struct be_cmd_resp_ddrdma_test *resp;
2474                 resp = cmd->va;
2475                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2476                                 resp->snd_err) {
2477                         status = -1;
2478                 }
2479         }
2480
2481 err:
2482         spin_unlock_bh(&adapter->mcc_lock);
2483         return status;
2484 }
2485
2486 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2487                             struct be_dma_mem *nonemb_cmd)
2488 {
2489         struct be_mcc_wrb *wrb;
2490         struct be_cmd_req_seeprom_read *req;
2491         int status;
2492
2493         spin_lock_bh(&adapter->mcc_lock);
2494
2495         wrb = wrb_from_mccq(adapter);
2496         if (!wrb) {
2497                 status = -EBUSY;
2498                 goto err;
2499         }
2500         req = nonemb_cmd->va;
2501
2502         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2503                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2504                                nonemb_cmd);
2505
2506         status = be_mcc_notify_wait(adapter);
2507
2508 err:
2509         spin_unlock_bh(&adapter->mcc_lock);
2510         return status;
2511 }
2512
2513 int be_cmd_get_phy_info(struct be_adapter *adapter)
2514 {
2515         struct be_mcc_wrb *wrb;
2516         struct be_cmd_req_get_phy_info *req;
2517         struct be_dma_mem cmd;
2518         int status;
2519
2520         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2521                             CMD_SUBSYSTEM_COMMON))
2522                 return -EPERM;
2523
2524         spin_lock_bh(&adapter->mcc_lock);
2525
2526         wrb = wrb_from_mccq(adapter);
2527         if (!wrb) {
2528                 status = -EBUSY;
2529                 goto err;
2530         }
2531         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2532         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2533         if (!cmd.va) {
2534                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2535                 status = -ENOMEM;
2536                 goto err;
2537         }
2538
2539         req = cmd.va;
2540
2541         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2542                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2543                                wrb, &cmd);
2544
2545         status = be_mcc_notify_wait(adapter);
2546         if (!status) {
2547                 struct be_phy_info *resp_phy_info =
2548                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2549                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2550                 adapter->phy.interface_type =
2551                         le16_to_cpu(resp_phy_info->interface_type);
2552                 adapter->phy.auto_speeds_supported =
2553                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2554                 adapter->phy.fixed_speeds_supported =
2555                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2556                 adapter->phy.misc_params =
2557                         le32_to_cpu(resp_phy_info->misc_params);
2558
2559                 if (BE2_chip(adapter)) {
2560                         adapter->phy.fixed_speeds_supported =
2561                                 BE_SUPPORTED_SPEED_10GBPS |
2562                                 BE_SUPPORTED_SPEED_1GBPS;
2563                 }
2564         }
2565         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2566 err:
2567         spin_unlock_bh(&adapter->mcc_lock);
2568         return status;
2569 }
2570
2571 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2572 {
2573         struct be_mcc_wrb *wrb;
2574         struct be_cmd_req_set_qos *req;
2575         int status;
2576
2577         spin_lock_bh(&adapter->mcc_lock);
2578
2579         wrb = wrb_from_mccq(adapter);
2580         if (!wrb) {
2581                 status = -EBUSY;
2582                 goto err;
2583         }
2584
2585         req = embedded_payload(wrb);
2586
2587         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2588                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2589
2590         req->hdr.domain = domain;
2591         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2592         req->max_bps_nic = cpu_to_le32(bps);
2593
2594         status = be_mcc_notify_wait(adapter);
2595
2596 err:
2597         spin_unlock_bh(&adapter->mcc_lock);
2598         return status;
2599 }
2600
2601 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2602 {
2603         struct be_mcc_wrb *wrb;
2604         struct be_cmd_req_cntl_attribs *req;
2605         struct be_cmd_resp_cntl_attribs *resp;
2606         int status;
2607         int payload_len = max(sizeof(*req), sizeof(*resp));
2608         struct mgmt_controller_attrib *attribs;
2609         struct be_dma_mem attribs_cmd;
2610
2611         if (mutex_lock_interruptible(&adapter->mbox_lock))
2612                 return -1;
2613
2614         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2615         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2616         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2617                                               &attribs_cmd.dma);
2618         if (!attribs_cmd.va) {
2619                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2620                 status = -ENOMEM;
2621                 goto err;
2622         }
2623
2624         wrb = wrb_from_mbox(adapter);
2625         if (!wrb) {
2626                 status = -EBUSY;
2627                 goto err;
2628         }
2629         req = attribs_cmd.va;
2630
2631         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2632                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2633                                wrb, &attribs_cmd);
2634
2635         status = be_mbox_notify_wait(adapter);
2636         if (!status) {
2637                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2638                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2639         }
2640
2641 err:
2642         mutex_unlock(&adapter->mbox_lock);
2643         if (attribs_cmd.va)
2644                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2645                                     attribs_cmd.va, attribs_cmd.dma);
2646         return status;
2647 }
2648
2649 /* Uses mbox */
2650 int be_cmd_req_native_mode(struct be_adapter *adapter)
2651 {
2652         struct be_mcc_wrb *wrb;
2653         struct be_cmd_req_set_func_cap *req;
2654         int status;
2655
2656         if (mutex_lock_interruptible(&adapter->mbox_lock))
2657                 return -1;
2658
2659         wrb = wrb_from_mbox(adapter);
2660         if (!wrb) {
2661                 status = -EBUSY;
2662                 goto err;
2663         }
2664
2665         req = embedded_payload(wrb);
2666
2667         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2668                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2669                                sizeof(*req), wrb, NULL);
2670
2671         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2672                                 CAPABILITY_BE3_NATIVE_ERX_API);
2673         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2674
2675         status = be_mbox_notify_wait(adapter);
2676         if (!status) {
2677                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2678                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2679                                         CAPABILITY_BE3_NATIVE_ERX_API;
2680                 if (!adapter->be3_native)
2681                         dev_warn(&adapter->pdev->dev,
2682                                  "adapter not in advanced mode\n");
2683         }
2684 err:
2685         mutex_unlock(&adapter->mbox_lock);
2686         return status;
2687 }
2688
2689 /* Get privilege(s) for a function */
2690 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2691                              u32 domain)
2692 {
2693         struct be_mcc_wrb *wrb;
2694         struct be_cmd_req_get_fn_privileges *req;
2695         int status;
2696
2697         spin_lock_bh(&adapter->mcc_lock);
2698
2699         wrb = wrb_from_mccq(adapter);
2700         if (!wrb) {
2701                 status = -EBUSY;
2702                 goto err;
2703         }
2704
2705         req = embedded_payload(wrb);
2706
2707         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2708                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2709                                wrb, NULL);
2710
2711         req->hdr.domain = domain;
2712
2713         status = be_mcc_notify_wait(adapter);
2714         if (!status) {
2715                 struct be_cmd_resp_get_fn_privileges *resp =
2716                                                 embedded_payload(wrb);
2717                 *privilege = le32_to_cpu(resp->privilege_mask);
2718
2719                 /* In UMC mode FW does not return right privileges.
2720                  * Override with correct privilege equivalent to PF.
2721                  */
2722                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2723                     be_physfn(adapter))
2724                         *privilege = MAX_PRIVILEGES;
2725         }
2726
2727 err:
2728         spin_unlock_bh(&adapter->mcc_lock);
2729         return status;
2730 }
2731
2732 /* Set privilege(s) for a function */
2733 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2734                              u32 domain)
2735 {
2736         struct be_mcc_wrb *wrb;
2737         struct be_cmd_req_set_fn_privileges *req;
2738         int status;
2739
2740         spin_lock_bh(&adapter->mcc_lock);
2741
2742         wrb = wrb_from_mccq(adapter);
2743         if (!wrb) {
2744                 status = -EBUSY;
2745                 goto err;
2746         }
2747
2748         req = embedded_payload(wrb);
2749         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2750                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2751                                wrb, NULL);
2752         req->hdr.domain = domain;
2753         if (lancer_chip(adapter))
2754                 req->privileges_lancer = cpu_to_le32(privileges);
2755         else
2756                 req->privileges = cpu_to_le32(privileges);
2757
2758         status = be_mcc_notify_wait(adapter);
2759 err:
2760         spin_unlock_bh(&adapter->mcc_lock);
2761         return status;
2762 }
2763
2764 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2765  * pmac_id_valid: false => pmac_id or MAC address is requested.
2766  *                If pmac_id is returned, pmac_id_valid is returned as true
2767  */
2768 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2769                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2770                              u8 domain)
2771 {
2772         struct be_mcc_wrb *wrb;
2773         struct be_cmd_req_get_mac_list *req;
2774         int status;
2775         int mac_count;
2776         struct be_dma_mem get_mac_list_cmd;
2777         int i;
2778
2779         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2780         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2781         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2782                                                    get_mac_list_cmd.size,
2783                                                    &get_mac_list_cmd.dma);
2784
2785         if (!get_mac_list_cmd.va) {
2786                 dev_err(&adapter->pdev->dev,
2787                         "Memory allocation failure during GET_MAC_LIST\n");
2788                 return -ENOMEM;
2789         }
2790
2791         spin_lock_bh(&adapter->mcc_lock);
2792
2793         wrb = wrb_from_mccq(adapter);
2794         if (!wrb) {
2795                 status = -EBUSY;
2796                 goto out;
2797         }
2798
2799         req = get_mac_list_cmd.va;
2800
2801         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2802                                OPCODE_COMMON_GET_MAC_LIST,
2803                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2804         req->hdr.domain = domain;
2805         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2806         if (*pmac_id_valid) {
2807                 req->mac_id = cpu_to_le32(*pmac_id);
2808                 req->iface_id = cpu_to_le16(if_handle);
2809                 req->perm_override = 0;
2810         } else {
2811                 req->perm_override = 1;
2812         }
2813
2814         status = be_mcc_notify_wait(adapter);
2815         if (!status) {
2816                 struct be_cmd_resp_get_mac_list *resp =
2817                                                 get_mac_list_cmd.va;
2818
2819                 if (*pmac_id_valid) {
2820                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2821                                ETH_ALEN);
2822                         goto out;
2823                 }
2824
2825                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2826                 /* Mac list returned could contain one or more active mac_ids
2827                  * or one or more true or pseudo permanant mac addresses.
2828                  * If an active mac_id is present, return first active mac_id
2829                  * found.
2830                  */
2831                 for (i = 0; i < mac_count; i++) {
2832                         struct get_list_macaddr *mac_entry;
2833                         u16 mac_addr_size;
2834                         u32 mac_id;
2835
2836                         mac_entry = &resp->macaddr_list[i];
2837                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2838                         /* mac_id is a 32 bit value and mac_addr size
2839                          * is 6 bytes
2840                          */
2841                         if (mac_addr_size == sizeof(u32)) {
2842                                 *pmac_id_valid = true;
2843                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2844                                 *pmac_id = le32_to_cpu(mac_id);
2845                                 goto out;
2846                         }
2847                 }
2848                 /* If no active mac_id found, return first mac addr */
2849                 *pmac_id_valid = false;
2850                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2851                        ETH_ALEN);
2852         }
2853
2854 out:
2855         spin_unlock_bh(&adapter->mcc_lock);
2856         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2857                             get_mac_list_cmd.va, get_mac_list_cmd.dma);
2858         return status;
2859 }
2860
2861 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
2862                           u8 *mac, u32 if_handle, bool active, u32 domain)
2863 {
2864
2865         if (!active)
2866                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2867                                          if_handle, domain);
2868         if (BEx_chip(adapter))
2869                 return be_cmd_mac_addr_query(adapter, mac, false,
2870                                              if_handle, curr_pmac_id);
2871         else
2872                 /* Fetch the MAC address using pmac_id */
2873                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2874                                                 &curr_pmac_id,
2875                                                 if_handle, domain);
2876 }
2877
2878 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2879 {
2880         int status;
2881         bool pmac_valid = false;
2882
2883         memset(mac, 0, ETH_ALEN);
2884
2885         if (BEx_chip(adapter)) {
2886                 if (be_physfn(adapter))
2887                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2888                                                        0);
2889                 else
2890                         status = be_cmd_mac_addr_query(adapter, mac, false,
2891                                                        adapter->if_handle, 0);
2892         } else {
2893                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2894                                                   NULL, adapter->if_handle, 0);
2895         }
2896
2897         return status;
2898 }
2899
2900 /* Uses synchronous MCCQ */
2901 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2902                         u8 mac_count, u32 domain)
2903 {
2904         struct be_mcc_wrb *wrb;
2905         struct be_cmd_req_set_mac_list *req;
2906         int status;
2907         struct be_dma_mem cmd;
2908
2909         memset(&cmd, 0, sizeof(struct be_dma_mem));
2910         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2911         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2912                                     &cmd.dma, GFP_KERNEL);
2913         if (!cmd.va)
2914                 return -ENOMEM;
2915
2916         spin_lock_bh(&adapter->mcc_lock);
2917
2918         wrb = wrb_from_mccq(adapter);
2919         if (!wrb) {
2920                 status = -EBUSY;
2921                 goto err;
2922         }
2923
2924         req = cmd.va;
2925         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2926                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2927                                wrb, &cmd);
2928
2929         req->hdr.domain = domain;
2930         req->mac_count = mac_count;
2931         if (mac_count)
2932                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2933
2934         status = be_mcc_notify_wait(adapter);
2935
2936 err:
2937         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2938         spin_unlock_bh(&adapter->mcc_lock);
2939         return status;
2940 }
2941
2942 /* Wrapper to delete any active MACs and provision the new mac.
2943  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2944  * current list are active.
2945  */
2946 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2947 {
2948         bool active_mac = false;
2949         u8 old_mac[ETH_ALEN];
2950         u32 pmac_id;
2951         int status;
2952
2953         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2954                                           &pmac_id, if_id, dom);
2955
2956         if (!status && active_mac)
2957                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2958
2959         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2960 }
2961
2962 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2963                           u32 domain, u16 intf_id, u16 hsw_mode)
2964 {
2965         struct be_mcc_wrb *wrb;
2966         struct be_cmd_req_set_hsw_config *req;
2967         void *ctxt;
2968         int status;
2969
2970         spin_lock_bh(&adapter->mcc_lock);
2971
2972         wrb = wrb_from_mccq(adapter);
2973         if (!wrb) {
2974                 status = -EBUSY;
2975                 goto err;
2976         }
2977
2978         req = embedded_payload(wrb);
2979         ctxt = &req->context;
2980
2981         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2982                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
2983                                NULL);
2984
2985         req->hdr.domain = domain;
2986         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2987         if (pvid) {
2988                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2989                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2990         }
2991         if (!BEx_chip(adapter) && hsw_mode) {
2992                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2993                               ctxt, adapter->hba_port_num);
2994                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2995                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2996                               ctxt, hsw_mode);
2997         }
2998
2999         be_dws_cpu_to_le(req->context, sizeof(req->context));
3000         status = be_mcc_notify_wait(adapter);
3001
3002 err:
3003         spin_unlock_bh(&adapter->mcc_lock);
3004         return status;
3005 }
3006
3007 /* Get Hyper switch config */
3008 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3009                           u32 domain, u16 intf_id, u8 *mode)
3010 {
3011         struct be_mcc_wrb *wrb;
3012         struct be_cmd_req_get_hsw_config *req;
3013         void *ctxt;
3014         int status;
3015         u16 vid;
3016
3017         spin_lock_bh(&adapter->mcc_lock);
3018
3019         wrb = wrb_from_mccq(adapter);
3020         if (!wrb) {
3021                 status = -EBUSY;
3022                 goto err;
3023         }
3024
3025         req = embedded_payload(wrb);
3026         ctxt = &req->context;
3027
3028         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3029                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3030                                NULL);
3031
3032         req->hdr.domain = domain;
3033         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3034                       ctxt, intf_id);
3035         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3036
3037         if (!BEx_chip(adapter) && mode) {
3038                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3039                               ctxt, adapter->hba_port_num);
3040                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3041         }
3042         be_dws_cpu_to_le(req->context, sizeof(req->context));
3043
3044         status = be_mcc_notify_wait(adapter);
3045         if (!status) {
3046                 struct be_cmd_resp_get_hsw_config *resp =
3047                                                 embedded_payload(wrb);
3048                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3049                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3050                                     pvid, &resp->context);
3051                 if (pvid)
3052                         *pvid = le16_to_cpu(vid);
3053                 if (mode)
3054                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3055                                               port_fwd_type, &resp->context);
3056         }
3057
3058 err:
3059         spin_unlock_bh(&adapter->mcc_lock);
3060         return status;
3061 }
3062
3063 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3064 {
3065         struct be_mcc_wrb *wrb;
3066         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3067         int status = 0;
3068         struct be_dma_mem cmd;
3069
3070         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3071                             CMD_SUBSYSTEM_ETH))
3072                 return -EPERM;
3073
3074         if (be_is_wol_excluded(adapter))
3075                 return status;
3076
3077         if (mutex_lock_interruptible(&adapter->mbox_lock))
3078                 return -1;
3079
3080         memset(&cmd, 0, sizeof(struct be_dma_mem));
3081         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3082         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3083         if (!cmd.va) {
3084                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3085                 status = -ENOMEM;
3086                 goto err;
3087         }
3088
3089         wrb = wrb_from_mbox(adapter);
3090         if (!wrb) {
3091                 status = -EBUSY;
3092                 goto err;
3093         }
3094
3095         req = cmd.va;
3096
3097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3098                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3099                                sizeof(*req), wrb, &cmd);
3100
3101         req->hdr.version = 1;
3102         req->query_options = BE_GET_WOL_CAP;
3103
3104         status = be_mbox_notify_wait(adapter);
3105         if (!status) {
3106                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3107                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3108
3109                 adapter->wol_cap = resp->wol_settings;
3110                 if (adapter->wol_cap & BE_WOL_CAP)
3111                         adapter->wol_en = true;
3112         }
3113 err:
3114         mutex_unlock(&adapter->mbox_lock);
3115         if (cmd.va)
3116                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3117         return status;
3118
3119 }
3120
3121 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3122 {
3123         struct be_dma_mem extfat_cmd;
3124         struct be_fat_conf_params *cfgs;
3125         int status;
3126         int i, j;
3127
3128         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3129         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3130         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3131                                              &extfat_cmd.dma);
3132         if (!extfat_cmd.va)
3133                 return -ENOMEM;
3134
3135         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3136         if (status)
3137                 goto err;
3138
3139         cfgs = (struct be_fat_conf_params *)
3140                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3141         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3142                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3143                 for (j = 0; j < num_modes; j++) {
3144                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3145                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
3146                                                         cpu_to_le32(level);
3147                 }
3148         }
3149
3150         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3151 err:
3152         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3153                             extfat_cmd.dma);
3154         return status;
3155 }
3156
3157 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3158 {
3159         struct be_dma_mem extfat_cmd;
3160         struct be_fat_conf_params *cfgs;
3161         int status, j;
3162         int level = 0;
3163
3164         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3165         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3166         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3167                                              &extfat_cmd.dma);
3168
3169         if (!extfat_cmd.va) {
3170                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3171                         __func__);
3172                 goto err;
3173         }
3174
3175         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3176         if (!status) {
3177                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3178                                                 sizeof(struct be_cmd_resp_hdr));
3179                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3180                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3181                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3182                 }
3183         }
3184         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3185                             extfat_cmd.dma);
3186 err:
3187         return level;
3188 }
3189
3190 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3191                                    struct be_dma_mem *cmd)
3192 {
3193         struct be_mcc_wrb *wrb;
3194         struct be_cmd_req_get_ext_fat_caps *req;
3195         int status;
3196
3197         if (mutex_lock_interruptible(&adapter->mbox_lock))
3198                 return -1;
3199
3200         wrb = wrb_from_mbox(adapter);
3201         if (!wrb) {
3202                 status = -EBUSY;
3203                 goto err;
3204         }
3205
3206         req = cmd->va;
3207         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3208                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3209                                cmd->size, wrb, cmd);
3210         req->parameter_type = cpu_to_le32(1);
3211
3212         status = be_mbox_notify_wait(adapter);
3213 err:
3214         mutex_unlock(&adapter->mbox_lock);
3215         return status;
3216 }
3217
3218 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3219                                    struct be_dma_mem *cmd,
3220                                    struct be_fat_conf_params *configs)
3221 {
3222         struct be_mcc_wrb *wrb;
3223         struct be_cmd_req_set_ext_fat_caps *req;
3224         int status;
3225
3226         spin_lock_bh(&adapter->mcc_lock);
3227
3228         wrb = wrb_from_mccq(adapter);
3229         if (!wrb) {
3230                 status = -EBUSY;
3231                 goto err;
3232         }
3233
3234         req = cmd->va;
3235         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3236         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3237                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3238                                cmd->size, wrb, cmd);
3239
3240         status = be_mcc_notify_wait(adapter);
3241 err:
3242         spin_unlock_bh(&adapter->mcc_lock);
3243         return status;
3244 }
3245
3246 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3247 {
3248         struct be_mcc_wrb *wrb;
3249         struct be_cmd_req_get_port_name *req;
3250         int status;
3251
3252         if (!lancer_chip(adapter)) {
3253                 *port_name = adapter->hba_port_num + '0';
3254                 return 0;
3255         }
3256
3257         spin_lock_bh(&adapter->mcc_lock);
3258
3259         wrb = wrb_from_mccq(adapter);
3260         if (!wrb) {
3261                 status = -EBUSY;
3262                 goto err;
3263         }
3264
3265         req = embedded_payload(wrb);
3266
3267         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3268                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3269                                NULL);
3270         req->hdr.version = 1;
3271
3272         status = be_mcc_notify_wait(adapter);
3273         if (!status) {
3274                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3275                 *port_name = resp->port_name[adapter->hba_port_num];
3276         } else {
3277                 *port_name = adapter->hba_port_num + '0';
3278         }
3279 err:
3280         spin_unlock_bh(&adapter->mcc_lock);
3281         return status;
3282 }
3283
3284 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3285 {
3286         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3287         int i;
3288
3289         for (i = 0; i < desc_count; i++) {
3290                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3291                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3292                         return (struct be_nic_res_desc *)hdr;
3293
3294                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3295                 hdr = (void *)hdr + hdr->desc_len;
3296         }
3297         return NULL;
3298 }
3299
3300 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3301                                                  u32 desc_count)
3302 {
3303         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3304         struct be_pcie_res_desc *pcie;
3305         int i;
3306
3307         for (i = 0; i < desc_count; i++) {
3308                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3309                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3310                         pcie = (struct be_pcie_res_desc *)hdr;
3311                         if (pcie->pf_num == devfn)
3312                                 return pcie;
3313                 }
3314
3315                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3316                 hdr = (void *)hdr + hdr->desc_len;
3317         }
3318         return NULL;
3319 }
3320
3321 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3322 {
3323         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3324         int i;
3325
3326         for (i = 0; i < desc_count; i++) {
3327                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3328                         return (struct be_port_res_desc *)hdr;
3329
3330                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3331                 hdr = (void *)hdr + hdr->desc_len;
3332         }
3333         return NULL;
3334 }
3335
3336 static void be_copy_nic_desc(struct be_resources *res,
3337                              struct be_nic_res_desc *desc)
3338 {
3339         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3340         res->max_vlans = le16_to_cpu(desc->vlan_count);
3341         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3342         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3343         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3344         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3345         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3346         /* Clear flags that driver is not interested in */
3347         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3348                                 BE_IF_CAP_FLAGS_WANT;
3349         /* Need 1 RXQ as the default RXQ */
3350         if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3351                 res->max_rss_qs -= 1;
3352 }
3353
3354 /* Uses Mbox */
3355 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3356 {
3357         struct be_mcc_wrb *wrb;
3358         struct be_cmd_req_get_func_config *req;
3359         int status;
3360         struct be_dma_mem cmd;
3361
3362         if (mutex_lock_interruptible(&adapter->mbox_lock))
3363                 return -1;
3364
3365         memset(&cmd, 0, sizeof(struct be_dma_mem));
3366         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3367         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3368         if (!cmd.va) {
3369                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3370                 status = -ENOMEM;
3371                 goto err;
3372         }
3373
3374         wrb = wrb_from_mbox(adapter);
3375         if (!wrb) {
3376                 status = -EBUSY;
3377                 goto err;
3378         }
3379
3380         req = cmd.va;
3381
3382         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3383                                OPCODE_COMMON_GET_FUNC_CONFIG,
3384                                cmd.size, wrb, &cmd);
3385
3386         if (skyhawk_chip(adapter))
3387                 req->hdr.version = 1;
3388
3389         status = be_mbox_notify_wait(adapter);
3390         if (!status) {
3391                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3392                 u32 desc_count = le32_to_cpu(resp->desc_count);
3393                 struct be_nic_res_desc *desc;
3394
3395                 desc = be_get_nic_desc(resp->func_param, desc_count);
3396                 if (!desc) {
3397                         status = -EINVAL;
3398                         goto err;
3399                 }
3400
3401                 adapter->pf_number = desc->pf_num;
3402                 be_copy_nic_desc(res, desc);
3403         }
3404 err:
3405         mutex_unlock(&adapter->mbox_lock);
3406         if (cmd.va)
3407                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3408         return status;
3409 }
3410
3411 /* Uses mbox */
3412 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3413                                           u8 domain, struct be_dma_mem *cmd)
3414 {
3415         struct be_mcc_wrb *wrb;
3416         struct be_cmd_req_get_profile_config *req;
3417         int status;
3418
3419         if (mutex_lock_interruptible(&adapter->mbox_lock))
3420                 return -1;
3421         wrb = wrb_from_mbox(adapter);
3422
3423         req = cmd->va;
3424         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3425                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3426                                cmd->size, wrb, cmd);
3427
3428         req->type = ACTIVE_PROFILE_TYPE;
3429         req->hdr.domain = domain;
3430         if (!lancer_chip(adapter))
3431                 req->hdr.version = 1;
3432
3433         status = be_mbox_notify_wait(adapter);
3434
3435         mutex_unlock(&adapter->mbox_lock);
3436         return status;
3437 }
3438
3439 /* Uses sync mcc */
3440 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3441                                           u8 domain, struct be_dma_mem *cmd)
3442 {
3443         struct be_mcc_wrb *wrb;
3444         struct be_cmd_req_get_profile_config *req;
3445         int status;
3446
3447         spin_lock_bh(&adapter->mcc_lock);
3448
3449         wrb = wrb_from_mccq(adapter);
3450         if (!wrb) {
3451                 status = -EBUSY;
3452                 goto err;
3453         }
3454
3455         req = cmd->va;
3456         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3457                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3458                                cmd->size, wrb, cmd);
3459
3460         req->type = ACTIVE_PROFILE_TYPE;
3461         req->hdr.domain = domain;
3462         if (!lancer_chip(adapter))
3463                 req->hdr.version = 1;
3464
3465         status = be_mcc_notify_wait(adapter);
3466
3467 err:
3468         spin_unlock_bh(&adapter->mcc_lock);
3469         return status;
3470 }
3471
3472 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3473 int be_cmd_get_profile_config(struct be_adapter *adapter,
3474                               struct be_resources *res, u8 domain)
3475 {
3476         struct be_cmd_resp_get_profile_config *resp;
3477         struct be_pcie_res_desc *pcie;
3478         struct be_port_res_desc *port;
3479         struct be_nic_res_desc *nic;
3480         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3481         struct be_dma_mem cmd;
3482         u32 desc_count;
3483         int status;
3484
3485         memset(&cmd, 0, sizeof(struct be_dma_mem));
3486         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3487         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3488         if (!cmd.va)
3489                 return -ENOMEM;
3490
3491         if (!mccq->created)
3492                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3493         else
3494                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3495         if (status)
3496                 goto err;
3497
3498         resp = cmd.va;
3499         desc_count = le32_to_cpu(resp->desc_count);
3500
3501         pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3502                                 desc_count);
3503         if (pcie)
3504                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3505
3506         port = be_get_port_desc(resp->func_param, desc_count);
3507         if (port)
3508                 adapter->mc_type = port->mc_type;
3509
3510         nic = be_get_nic_desc(resp->func_param, desc_count);
3511         if (nic)
3512                 be_copy_nic_desc(res, nic);
3513
3514 err:
3515         if (cmd.va)
3516                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3517         return status;
3518 }
3519
3520 int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3521                               int size, u8 version, u8 domain)
3522 {
3523         struct be_cmd_req_set_profile_config *req;
3524         struct be_mcc_wrb *wrb;
3525         int status;
3526
3527         spin_lock_bh(&adapter->mcc_lock);
3528
3529         wrb = wrb_from_mccq(adapter);
3530         if (!wrb) {
3531                 status = -EBUSY;
3532                 goto err;
3533         }
3534
3535         req = embedded_payload(wrb);
3536         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3537                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3538                                wrb, NULL);
3539         req->hdr.version = version;
3540         req->hdr.domain = domain;
3541         req->desc_count = cpu_to_le32(1);
3542         memcpy(req->desc, desc, size);
3543
3544         status = be_mcc_notify_wait(adapter);
3545 err:
3546         spin_unlock_bh(&adapter->mcc_lock);
3547         return status;
3548 }
3549
3550 /* Mark all fields invalid */
3551 void be_reset_nic_desc(struct be_nic_res_desc *nic)
3552 {
3553         memset(nic, 0, sizeof(*nic));
3554         nic->unicast_mac_count = 0xFFFF;
3555         nic->mcc_count = 0xFFFF;
3556         nic->vlan_count = 0xFFFF;
3557         nic->mcast_mac_count = 0xFFFF;
3558         nic->txq_count = 0xFFFF;
3559         nic->rq_count = 0xFFFF;
3560         nic->rssq_count = 0xFFFF;
3561         nic->lro_count = 0xFFFF;
3562         nic->cq_count = 0xFFFF;
3563         nic->toe_conn_count = 0xFFFF;
3564         nic->eq_count = 0xFFFF;
3565         nic->iface_count = 0xFFFF;
3566         nic->link_param = 0xFF;
3567         nic->channel_id_param = cpu_to_le16(0xF000);
3568         nic->acpi_params = 0xFF;
3569         nic->wol_param = 0x0F;
3570         nic->tunnel_iface_count = 0xFFFF;
3571         nic->direct_tenant_iface_count = 0xFFFF;
3572         nic->bw_max = 0xFFFFFFFF;
3573 }
3574
3575 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3576                       u8 domain)
3577 {
3578         struct be_nic_res_desc nic_desc;
3579         u32 bw_percent;
3580         u16 version = 0;
3581
3582         if (BE3_chip(adapter))
3583                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3584
3585         be_reset_nic_desc(&nic_desc);
3586         nic_desc.pf_num = adapter->pf_number;
3587         nic_desc.vf_num = domain;
3588         if (lancer_chip(adapter)) {
3589                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3590                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3591                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3592                                         (1 << NOSV_SHIFT);
3593                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3594         } else {
3595                 version = 1;
3596                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3597                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3598                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3599                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3600                 nic_desc.bw_max = cpu_to_le32(bw_percent);
3601         }
3602
3603         return be_cmd_set_profile_config(adapter, &nic_desc,
3604                                          nic_desc.hdr.desc_len,
3605                                          version, domain);
3606 }
3607
3608 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3609 {
3610         struct be_mcc_wrb *wrb;
3611         struct be_cmd_req_manage_iface_filters *req;
3612         int status;
3613
3614         if (iface == 0xFFFFFFFF)
3615                 return -1;
3616
3617         spin_lock_bh(&adapter->mcc_lock);
3618
3619         wrb = wrb_from_mccq(adapter);
3620         if (!wrb) {
3621                 status = -EBUSY;
3622                 goto err;
3623         }
3624         req = embedded_payload(wrb);
3625
3626         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3627                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3628                                wrb, NULL);
3629         req->op = op;
3630         req->target_iface_id = cpu_to_le32(iface);
3631
3632         status = be_mcc_notify_wait(adapter);
3633 err:
3634         spin_unlock_bh(&adapter->mcc_lock);
3635         return status;
3636 }
3637
3638 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3639 {
3640         struct be_port_res_desc port_desc;
3641
3642         memset(&port_desc, 0, sizeof(port_desc));
3643         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3644         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3645         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3646         port_desc.link_num = adapter->hba_port_num;
3647         if (port) {
3648                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3649                                         (1 << RCVID_SHIFT);
3650                 port_desc.nv_port = swab16(port);
3651         } else {
3652                 port_desc.nv_flags = NV_TYPE_DISABLED;
3653                 port_desc.nv_port = 0;
3654         }
3655
3656         return be_cmd_set_profile_config(adapter, &port_desc,
3657                                          RESOURCE_DESC_SIZE_V1, 1, 0);
3658 }
3659
3660 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3661                      int vf_num)
3662 {
3663         struct be_mcc_wrb *wrb;
3664         struct be_cmd_req_get_iface_list *req;
3665         struct be_cmd_resp_get_iface_list *resp;
3666         int status;
3667
3668         spin_lock_bh(&adapter->mcc_lock);
3669
3670         wrb = wrb_from_mccq(adapter);
3671         if (!wrb) {
3672                 status = -EBUSY;
3673                 goto err;
3674         }
3675         req = embedded_payload(wrb);
3676
3677         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3678                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3679                                wrb, NULL);
3680         req->hdr.domain = vf_num + 1;
3681
3682         status = be_mcc_notify_wait(adapter);
3683         if (!status) {
3684                 resp = (struct be_cmd_resp_get_iface_list *)req;
3685                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3686         }
3687
3688 err:
3689         spin_unlock_bh(&adapter->mcc_lock);
3690         return status;
3691 }
3692
3693 static int lancer_wait_idle(struct be_adapter *adapter)
3694 {
3695 #define SLIPORT_IDLE_TIMEOUT 30
3696         u32 reg_val;
3697         int status = 0, i;
3698
3699         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3700                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3701                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3702                         break;
3703
3704                 ssleep(1);
3705         }
3706
3707         if (i == SLIPORT_IDLE_TIMEOUT)
3708                 status = -1;
3709
3710         return status;
3711 }
3712
3713 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3714 {
3715         int status = 0;
3716
3717         status = lancer_wait_idle(adapter);
3718         if (status)
3719                 return status;
3720
3721         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3722
3723         return status;
3724 }
3725
3726 /* Routine to check whether dump image is present or not */
3727 bool dump_present(struct be_adapter *adapter)
3728 {
3729         u32 sliport_status = 0;
3730
3731         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3732         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3733 }
3734
3735 int lancer_initiate_dump(struct be_adapter *adapter)
3736 {
3737         int status;
3738
3739         /* give firmware reset and diagnostic dump */
3740         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3741                                      PHYSDEV_CONTROL_DD_MASK);
3742         if (status < 0) {
3743                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3744                 return status;
3745         }
3746
3747         status = lancer_wait_idle(adapter);
3748         if (status)
3749                 return status;
3750
3751         if (!dump_present(adapter)) {
3752                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3753                 return -1;
3754         }
3755
3756         return 0;
3757 }
3758
3759 /* Uses sync mcc */
3760 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3761 {
3762         struct be_mcc_wrb *wrb;
3763         struct be_cmd_enable_disable_vf *req;
3764         int status;
3765
3766         if (BEx_chip(adapter))
3767                 return 0;
3768
3769         spin_lock_bh(&adapter->mcc_lock);
3770
3771         wrb = wrb_from_mccq(adapter);
3772         if (!wrb) {
3773                 status = -EBUSY;
3774                 goto err;
3775         }
3776
3777         req = embedded_payload(wrb);
3778
3779         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3780                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3781                                wrb, NULL);
3782
3783         req->hdr.domain = domain;
3784         req->enable = 1;
3785         status = be_mcc_notify_wait(adapter);
3786 err:
3787         spin_unlock_bh(&adapter->mcc_lock);
3788         return status;
3789 }
3790
3791 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3792 {
3793         struct be_mcc_wrb *wrb;
3794         struct be_cmd_req_intr_set *req;
3795         int status;
3796
3797         if (mutex_lock_interruptible(&adapter->mbox_lock))
3798                 return -1;
3799
3800         wrb = wrb_from_mbox(adapter);
3801
3802         req = embedded_payload(wrb);
3803
3804         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3805                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3806                                wrb, NULL);
3807
3808         req->intr_enabled = intr_enable;
3809
3810         status = be_mbox_notify_wait(adapter);
3811
3812         mutex_unlock(&adapter->mbox_lock);
3813         return status;
3814 }
3815
3816 /* Uses MBOX */
3817 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3818 {
3819         struct be_cmd_req_get_active_profile *req;
3820         struct be_mcc_wrb *wrb;
3821         int status;
3822
3823         if (mutex_lock_interruptible(&adapter->mbox_lock))
3824                 return -1;
3825
3826         wrb = wrb_from_mbox(adapter);
3827         if (!wrb) {
3828                 status = -EBUSY;
3829                 goto err;
3830         }
3831
3832         req = embedded_payload(wrb);
3833
3834         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3835                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
3836                                wrb, NULL);
3837
3838         status = be_mbox_notify_wait(adapter);
3839         if (!status) {
3840                 struct be_cmd_resp_get_active_profile *resp =
3841                                                         embedded_payload(wrb);
3842                 *profile_id = le16_to_cpu(resp->active_profile_id);
3843         }
3844
3845 err:
3846         mutex_unlock(&adapter->mbox_lock);
3847         return status;
3848 }
3849
3850 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
3851                                    int link_state, u8 domain)
3852 {
3853         struct be_mcc_wrb *wrb;
3854         struct be_cmd_req_set_ll_link *req;
3855         int status;
3856
3857         if (BEx_chip(adapter) || lancer_chip(adapter))
3858                 return 0;
3859
3860         spin_lock_bh(&adapter->mcc_lock);
3861
3862         wrb = wrb_from_mccq(adapter);
3863         if (!wrb) {
3864                 status = -EBUSY;
3865                 goto err;
3866         }
3867
3868         req = embedded_payload(wrb);
3869
3870         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3871                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
3872                                sizeof(*req), wrb, NULL);
3873
3874         req->hdr.version = 1;
3875         req->hdr.domain = domain;
3876
3877         if (link_state == IFLA_VF_LINK_STATE_ENABLE)
3878                 req->link_config |= 1;
3879
3880         if (link_state == IFLA_VF_LINK_STATE_AUTO)
3881                 req->link_config |= 1 << PLINK_TRACK_SHIFT;
3882
3883         status = be_mcc_notify_wait(adapter);
3884 err:
3885         spin_unlock_bh(&adapter->mcc_lock);
3886         return status;
3887 }
3888
3889 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3890                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3891 {
3892         struct be_adapter *adapter = netdev_priv(netdev_handle);
3893         struct be_mcc_wrb *wrb;
3894         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3895         struct be_cmd_req_hdr *req;
3896         struct be_cmd_resp_hdr *resp;
3897         int status;
3898
3899         spin_lock_bh(&adapter->mcc_lock);
3900
3901         wrb = wrb_from_mccq(adapter);
3902         if (!wrb) {
3903                 status = -EBUSY;
3904                 goto err;
3905         }
3906         req = embedded_payload(wrb);
3907         resp = embedded_payload(wrb);
3908
3909         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3910                                hdr->opcode, wrb_payload_size, wrb, NULL);
3911         memcpy(req, wrb_payload, wrb_payload_size);
3912         be_dws_cpu_to_le(req, wrb_payload_size);
3913
3914         status = be_mcc_notify_wait(adapter);
3915         if (cmd_status)
3916                 *cmd_status = (status & 0xffff);
3917         if (ext_status)
3918                 *ext_status = 0;
3919         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3920         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3921 err:
3922         spin_unlock_bh(&adapter->mcc_lock);
3923         return status;
3924 }
3925 EXPORT_SYMBOL(be_roce_mcc_cmd);