drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2014 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 145             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 146                 complete(&adapter->et_cmd_compl);
 147                 return 0;
 148         }
 149
 150         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 151              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 152             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 153                 adapter->flash_status = compl_status;
 154                 complete(&adapter->et_cmd_compl);
 155         }
 156
 157         if (compl_status == MCC_STATUS_SUCCESS) {
 158                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 159                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 160                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 161                         be_parse_stats(adapter);
 162                         adapter->stats_cmd_sent = false;
 163                 }
 164                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 165                     subsystem == CMD_SUBSYSTEM_COMMON) {
 166                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 167                                 (void *)resp_hdr;
 168                         adapter->drv_stats.be_on_die_temperature =
 169                                 resp->on_die_temperature;
 170                 }
 171         } else {
 172                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 173                         adapter->be_get_temp_freq = 0;
 174
 175                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 176                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 177                         goto done;
 178
 179                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 180                         dev_warn(&adapter->pdev->dev,
 181                                  "VF is not privileged to issue opcode %d-%d\n",
 182                                  opcode, subsystem);
 183                 } else {
 184                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 185                                         CQE_STATUS_EXTD_MASK;
 186                         dev_err(&adapter->pdev->dev,
 187                                 "opcode %d-%d failed:status %d-%d\n",
 188                                 opcode, subsystem, compl_status, extd_status);
 189
 190                         if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
 191                                 return extd_status;
 192                 }
 193         }
 194 done:
 195         return compl_status;
 196 }
 197
 198 /* Link state evt is a string of bytes; no need for endian swapping */
 199 static void be_async_link_state_process(struct be_adapter *adapter,
 200                 struct be_async_event_link_state *evt)
 201 {
 202         /* When link status changes, link speed must be re-queried from FW */
 203         adapter->phy.link_speed = -1;
 204
 205         /* On BEx the FW does not send a separate link status
 206          * notification for physical and logical link.
 207          * On other chips just process the logical link
 208          * status notification
 209          */
 210         if (!BEx_chip(adapter) &&
 211             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 212                 return;
 213
 214         /* For the initial link status do not rely on the ASYNC event as
 215          * it may not be received in some cases.
 216          */
 217         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 218                 be_link_status_update(adapter,
 219                                       evt->port_link_status & LINK_STATUS_MASK);
 220 }
 221
 222 /* Grp5 CoS Priority evt */
 223 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 224                 struct be_async_event_grp5_cos_priority *evt)
 225 {
 226         if (evt->valid) {
 227                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 228                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 229                 adapter->recommended_prio =
 230                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 231         }
 232 }
 233
 234 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 235 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 236                 struct be_async_event_grp5_qos_link_speed *evt)
 237 {
 238         if (adapter->phy.link_speed >= 0 &&
 239             evt->physical_port == adapter->port_num)
 240                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 241 }
 242
 243 /*Grp5 PVID evt*/
 244 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 245                 struct be_async_event_grp5_pvid_state *evt)
 246 {
 247         if (evt->enabled) {
 248                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 249                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 250         } else {
 251                 adapter->pvid = 0;
 252         }
 253 }
 254
 255 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 256                 u32 trailer, struct be_mcc_compl *evt)
 257 {
 258         u8 event_type = 0;
 259
 260         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 261                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 262
 263         switch (event_type) {
 264         case ASYNC_EVENT_COS_PRIORITY:
 265                 be_async_grp5_cos_priority_process(adapter,
 266                 (struct be_async_event_grp5_cos_priority *)evt);
 267         break;
 268         case ASYNC_EVENT_QOS_SPEED:
 269                 be_async_grp5_qos_speed_process(adapter,
 270                 (struct be_async_event_grp5_qos_link_speed *)evt);
 271         break;
 272         case ASYNC_EVENT_PVID_STATE:
 273                 be_async_grp5_pvid_state_process(adapter,
 274                 (struct be_async_event_grp5_pvid_state *)evt);
 275         break;
 276         default:
 277                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
 278                          event_type);
 279                 break;
 280         }
 281 }
 282
 283 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 284                 u32 trailer, struct be_mcc_compl *cmp)
 285 {
 286         u8 event_type = 0;
 287         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 288
 289         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 290                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 291
 292         switch (event_type) {
 293         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 294                 if (evt->valid)
 295                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 296                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 297         break;
 298         default:
 299                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 300                          event_type);
 301         break;
 302         }
 303 }
 304
 305 static inline bool is_link_state_evt(u32 trailer)
 306 {
 307         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 308                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 309                                 ASYNC_EVENT_CODE_LINK_STATE;
 310 }
 311
 312 static inline bool is_grp5_evt(u32 trailer)
 313 {
 314         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 315                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 316                                 ASYNC_EVENT_CODE_GRP_5);
 317 }
 318
 319 static inline bool is_dbg_evt(u32 trailer)
 320 {
 321         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 322                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 323                                 ASYNC_EVENT_CODE_QNQ);
 324 }
 325
 326 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 327 {
 328         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 329         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 330
 331         if (be_mcc_compl_is_new(compl)) {
 332                 queue_tail_inc(mcc_cq);
 333                 return compl;
 334         }
 335         return NULL;
 336 }
 337
 338 void be_async_mcc_enable(struct be_adapter *adapter)
 339 {
 340         spin_lock_bh(&adapter->mcc_cq_lock);
 341
 342         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 343         adapter->mcc_obj.rearm_cq = true;
 344
 345         spin_unlock_bh(&adapter->mcc_cq_lock);
 346 }
 347
 348 void be_async_mcc_disable(struct be_adapter *adapter)
 349 {
 350         spin_lock_bh(&adapter->mcc_cq_lock);
 351
 352         adapter->mcc_obj.rearm_cq = false;
 353         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 354
 355         spin_unlock_bh(&adapter->mcc_cq_lock);
 356 }
 357
 358 int be_process_mcc(struct be_adapter *adapter)
 359 {
 360         struct be_mcc_compl *compl;
 361         int num = 0, status = 0;
 362         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 363
 364         spin_lock(&adapter->mcc_cq_lock);
 365         while ((compl = be_mcc_compl_get(adapter))) {
 366                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 367                         /* Interpret flags as an async trailer */
 368                         if (is_link_state_evt(compl->flags))
 369                                 be_async_link_state_process(adapter,
 370                                 (struct be_async_event_link_state *) compl);
 371                         else if (is_grp5_evt(compl->flags))
 372                                 be_async_grp5_evt_process(adapter,
 373                                 compl->flags, compl);
 374                         else if (is_dbg_evt(compl->flags))
 375                                 be_async_dbg_evt_process(adapter,
 376                                 compl->flags, compl);
 377                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 378                                 status = be_mcc_compl_process(adapter, compl);
 379                                 atomic_dec(&mcc_obj->q.used);
 380                 }
 381                 be_mcc_compl_use(compl);
 382                 num++;
 383         }
 384
 385         if (num)
 386                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 387
 388         spin_unlock(&adapter->mcc_cq_lock);
 389         return status;
 390 }
 391
 392 /* Wait till no more pending mcc requests are present */
 393 static int be_mcc_wait_compl(struct be_adapter *adapter)
 394 {
 395 #define mcc_timeout             120000 /* 12s timeout */
 396         int i, status = 0;
 397         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 398
 399         for (i = 0; i < mcc_timeout; i++) {
 400                 if (be_error(adapter))
 401                         return -EIO;
 402
 403                 local_bh_disable();
 404                 status = be_process_mcc(adapter);
 405                 local_bh_enable();
 406
 407                 if (atomic_read(&mcc_obj->q.used) == 0)
 408                         break;
 409                 udelay(100);
 410         }
 411         if (i == mcc_timeout) {
 412                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 413                 adapter->fw_timeout = true;
 414                 return -EIO;
 415         }
 416         return status;
 417 }
 418
 419 /* Notify MCC requests and wait for completion */
 420 static int be_mcc_notify_wait(struct be_adapter *adapter)
 421 {
 422         int status;
 423         struct be_mcc_wrb *wrb;
 424         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 425         u16 index = mcc_obj->q.head;
 426         struct be_cmd_resp_hdr *resp;
 427
 428         index_dec(&index, mcc_obj->q.len);
 429         wrb = queue_index_node(&mcc_obj->q, index);
 430
 431         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 432
 433         be_mcc_notify(adapter);
 434
 435         status = be_mcc_wait_compl(adapter);
 436         if (status == -EIO)
 437                 goto out;
 438
 439         status = resp->status;
 440 out:
 441         return status;
 442 }
 443
 444 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 445 {
 446         int msecs = 0;
 447         u32 ready;
 448
 449         do {
 450                 if (be_error(adapter))
 451                         return -EIO;
 452
 453                 ready = ioread32(db);
 454                 if (ready == 0xffffffff)
 455                         return -1;
 456
 457                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 458                 if (ready)
 459                         break;
 460
 461                 if (msecs > 4000) {
 462                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 463                         adapter->fw_timeout = true;
 464                         be_detect_error(adapter);
 465                         return -1;
 466                 }
 467
 468                 msleep(1);
 469                 msecs++;
 470         } while (true);
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Insert the mailbox address into the doorbell in two steps
 477  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 478  */
 479 static int be_mbox_notify_wait(struct be_adapter *adapter)
 480 {
 481         int status;
 482         u32 val = 0;
 483         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 484         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 485         struct be_mcc_mailbox *mbox = mbox_mem->va;
 486         struct be_mcc_compl *compl = &mbox->compl;
 487
 488         /* wait for ready to be set */
 489         status = be_mbox_db_ready_wait(adapter, db);
 490         if (status != 0)
 491                 return status;
 492
 493         val |= MPU_MAILBOX_DB_HI_MASK;
 494         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 495         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 496         iowrite32(val, db);
 497
 498         /* wait for ready to be set */
 499         status = be_mbox_db_ready_wait(adapter, db);
 500         if (status != 0)
 501                 return status;
 502
 503         val = 0;
 504         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 505         val |= (u32)(mbox_mem->dma >> 4) << 2;
 506         iowrite32(val, db);
 507
 508         status = be_mbox_db_ready_wait(adapter, db);
 509         if (status != 0)
 510                 return status;
 511
 512         /* A cq entry has been made now */
 513         if (be_mcc_compl_is_new(compl)) {
 514                 status = be_mcc_compl_process(adapter, &mbox->compl);
 515                 be_mcc_compl_use(compl);
 516                 if (status)
 517                         return status;
 518         } else {
 519                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 520                 return -1;
 521         }
 522         return 0;
 523 }
 524
 525 static u16 be_POST_stage_get(struct be_adapter *adapter)
 526 {
 527         u32 sem;
 528
 529         if (BEx_chip(adapter))
 530                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 531         else
 532                 pci_read_config_dword(adapter->pdev,
 533                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 534
 535         return sem & POST_STAGE_MASK;
 536 }
 537
 538 static int lancer_wait_ready(struct be_adapter *adapter)
 539 {
 540 #define SLIPORT_READY_TIMEOUT 30
 541         u32 sliport_status;
 542         int status = 0, i;
 543
 544         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 545                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 546                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 547                         break;
 548
 549                 msleep(1000);
 550         }
 551
 552         if (i == SLIPORT_READY_TIMEOUT)
 553                 status = -1;
 554
 555         return status;
 556 }
 557
 558 static bool lancer_provisioning_error(struct be_adapter *adapter)
 559 {
 560         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 561         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 562         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 563                 sliport_err1 = ioread32(adapter->db +
 564                                         SLIPORT_ERROR1_OFFSET);
 565                 sliport_err2 = ioread32(adapter->db +
 566                                         SLIPORT_ERROR2_OFFSET);
 567
 568                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 569                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 570                         return true;
 571         }
 572         return false;
 573 }
 574
 575 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 576 {
 577         int status;
 578         u32 sliport_status, err, reset_needed;
 579         bool resource_error;
 580
 581         resource_error = lancer_provisioning_error(adapter);
 582         if (resource_error)
 583                 return -EAGAIN;
 584
 585         status = lancer_wait_ready(adapter);
 586         if (!status) {
 587                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 588                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 589                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 590                 if (err && reset_needed) {
 591                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 592                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 593
 594                         /* check adapter has corrected the error */
 595                         status = lancer_wait_ready(adapter);
 596                         sliport_status = ioread32(adapter->db +
 597                                                   SLIPORT_STATUS_OFFSET);
 598                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 599                                                 SLIPORT_STATUS_RN_MASK);
 600                         if (status || sliport_status)
 601                                 status = -1;
 602                 } else if (err || reset_needed) {
 603                         status = -1;
 604                 }
 605         }
 606         /* Stop error recovery if error is not recoverable.
 607          * No resource error is temporary errors and will go away
 608          * when PF provisions resources.
 609          */
 610         resource_error = lancer_provisioning_error(adapter);
 611         if (resource_error)
 612                 status = -EAGAIN;
 613
 614         return status;
 615 }
 616
 617 int be_fw_wait_ready(struct be_adapter *adapter)
 618 {
 619         u16 stage;
 620         int status, timeout = 0;
 621         struct device *dev = &adapter->pdev->dev;
 622
 623         if (lancer_chip(adapter)) {
 624                 status = lancer_wait_ready(adapter);
 625                 return status;
 626         }
 627
 628         do {
 629                 stage = be_POST_stage_get(adapter);
 630                 if (stage == POST_STAGE_ARMFW_RDY)
 631                         return 0;
 632
 633                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 634                          timeout);
 635                 if (msleep_interruptible(2000)) {
 636                         dev_err(dev, "Waiting for POST aborted\n");
 637                         return -EINTR;
 638                 }
 639                 timeout += 2;
 640         } while (timeout < 60);
 641
 642         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 643         return -1;
 644 }
 645
 646
 647 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 648 {
 649         return &wrb->payload.sgl[0];
 650 }
 651
 652 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
 653                                  unsigned long addr)
 654 {
 655         wrb->tag0 = addr & 0xFFFFFFFF;
 656         wrb->tag1 = upper_32_bits(addr);
 657 }
 658
 659 /* Don't touch the hdr after it's prepared */
 660 /* mem will be NULL for embedded commands */
 661 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 662                                 u8 subsystem, u8 opcode, int cmd_len,
 663                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 664 {
 665         struct be_sge *sge;
 666
 667         req_hdr->opcode = opcode;
 668         req_hdr->subsystem = subsystem;
 669         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 670         req_hdr->version = 0;
 671         fill_wrb_tags(wrb, (ulong) req_hdr);
 672         wrb->payload_length = cmd_len;
 673         if (mem) {
 674                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 675                         MCC_WRB_SGE_CNT_SHIFT;
 676                 sge = nonembedded_sgl(wrb);
 677                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 678                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 679                 sge->len = cpu_to_le32(mem->size);
 680         } else
 681                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 682         be_dws_cpu_to_le(wrb, 8);
 683 }
 684
 685 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 686                         struct be_dma_mem *mem)
 687 {
 688         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 689         u64 dma = (u64)mem->dma;
 690
 691         for (i = 0; i < buf_pages; i++) {
 692                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 693                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 694                 dma += PAGE_SIZE_4K;
 695         }
 696 }
 697
 698 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 699 {
 700         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 701         struct be_mcc_wrb *wrb
 702                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 703         memset(wrb, 0, sizeof(*wrb));
 704         return wrb;
 705 }
 706
 707 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 708 {
 709         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 710         struct be_mcc_wrb *wrb;
 711
 712         if (!mccq->created)
 713                 return NULL;
 714
 715         if (atomic_read(&mccq->used) >= mccq->len)
 716                 return NULL;
 717
 718         wrb = queue_head_node(mccq);
 719         queue_head_inc(mccq);
 720         atomic_inc(&mccq->used);
 721         memset(wrb, 0, sizeof(*wrb));
 722         return wrb;
 723 }
 724
 725 static bool use_mcc(struct be_adapter *adapter)
 726 {
 727         return adapter->mcc_obj.q.created;
 728 }
 729
 730 /* Must be used only in process context */
 731 static int be_cmd_lock(struct be_adapter *adapter)
 732 {
 733         if (use_mcc(adapter)) {
 734                 spin_lock_bh(&adapter->mcc_lock);
 735                 return 0;
 736         } else {
 737                 return mutex_lock_interruptible(&adapter->mbox_lock);
 738         }
 739 }
 740
 741 /* Must be used only in process context */
 742 static void be_cmd_unlock(struct be_adapter *adapter)
 743 {
 744         if (use_mcc(adapter))
 745                 spin_unlock_bh(&adapter->mcc_lock);
 746         else
 747                 return mutex_unlock(&adapter->mbox_lock);
 748 }
 749
 750 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 751                                       struct be_mcc_wrb *wrb)
 752 {
 753         struct be_mcc_wrb *dest_wrb;
 754
 755         if (use_mcc(adapter)) {
 756                 dest_wrb = wrb_from_mccq(adapter);
 757                 if (!dest_wrb)
 758                         return NULL;
 759         } else {
 760                 dest_wrb = wrb_from_mbox(adapter);
 761         }
 762
 763         memcpy(dest_wrb, wrb, sizeof(*wrb));
 764         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 765                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 766
 767         return dest_wrb;
 768 }
 769
 770 /* Must be used only in process context */
 771 static int be_cmd_notify_wait(struct be_adapter *adapter,
 772                               struct be_mcc_wrb *wrb)
 773 {
 774         struct be_mcc_wrb *dest_wrb;
 775         int status;
 776
 777         status = be_cmd_lock(adapter);
 778         if (status)
 779                 return status;
 780
 781         dest_wrb = be_cmd_copy(adapter, wrb);
 782         if (!dest_wrb)
 783                 return -EBUSY;
 784
 785         if (use_mcc(adapter))
 786                 status = be_mcc_notify_wait(adapter);
 787         else
 788                 status = be_mbox_notify_wait(adapter);
 789
 790         if (!status)
 791                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 792
 793         be_cmd_unlock(adapter);
 794         return status;
 795 }
 796
 797 /* Tell fw we're about to start firing cmds by writing a
 798  * special pattern across the wrb hdr; uses mbox
 799  */
 800 int be_cmd_fw_init(struct be_adapter *adapter)
 801 {
 802         u8 *wrb;
 803         int status;
 804
 805         if (lancer_chip(adapter))
 806                 return 0;
 807
 808         if (mutex_lock_interruptible(&adapter->mbox_lock))
 809                 return -1;
 810
 811         wrb = (u8 *)wrb_from_mbox(adapter);
 812         *wrb++ = 0xFF;
 813         *wrb++ = 0x12;
 814         *wrb++ = 0x34;
 815         *wrb++ = 0xFF;
 816         *wrb++ = 0xFF;
 817         *wrb++ = 0x56;
 818         *wrb++ = 0x78;
 819         *wrb = 0xFF;
 820
 821         status = be_mbox_notify_wait(adapter);
 822
 823         mutex_unlock(&adapter->mbox_lock);
 824         return status;
 825 }
 826
 827 /* Tell fw we're done with firing cmds by writing a
 828  * special pattern across the wrb hdr; uses mbox
 829  */
 830 int be_cmd_fw_clean(struct be_adapter *adapter)
 831 {
 832         u8 *wrb;
 833         int status;
 834
 835         if (lancer_chip(adapter))
 836                 return 0;
 837
 838         if (mutex_lock_interruptible(&adapter->mbox_lock))
 839                 return -1;
 840
 841         wrb = (u8 *)wrb_from_mbox(adapter);
 842         *wrb++ = 0xFF;
 843         *wrb++ = 0xAA;
 844         *wrb++ = 0xBB;
 845         *wrb++ = 0xFF;
 846         *wrb++ = 0xFF;
 847         *wrb++ = 0xCC;
 848         *wrb++ = 0xDD;
 849         *wrb = 0xFF;
 850
 851         status = be_mbox_notify_wait(adapter);
 852
 853         mutex_unlock(&adapter->mbox_lock);
 854         return status;
 855 }
 856
 857 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 858 {
 859         struct be_mcc_wrb *wrb;
 860         struct be_cmd_req_eq_create *req;
 861         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 862         int status, ver = 0;
 863
 864         if (mutex_lock_interruptible(&adapter->mbox_lock))
 865                 return -1;
 866
 867         wrb = wrb_from_mbox(adapter);
 868         req = embedded_payload(wrb);
 869
 870         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 871                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 872
 873         /* Support for EQ_CREATEv2 available only SH-R onwards */
 874         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 875                 ver = 2;
 876
 877         req->hdr.version = ver;
 878         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 879
 880         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 881         /* 4byte eqe*/
 882         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 883         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 884                       __ilog2_u32(eqo->q.len / 256));
 885         be_dws_cpu_to_le(req->context, sizeof(req->context));
 886
 887         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 888
 889         status = be_mbox_notify_wait(adapter);
 890         if (!status) {
 891                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 892                 eqo->q.id = le16_to_cpu(resp->eq_id);
 893                 eqo->msix_idx =
 894                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 895                 eqo->q.created = true;
 896         }
 897
 898         mutex_unlock(&adapter->mbox_lock);
 899         return status;
 900 }
 901
 902 /* Use MCC */
 903 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 904                           bool permanent, u32 if_handle, u32 pmac_id)
 905 {
 906         struct be_mcc_wrb *wrb;
 907         struct be_cmd_req_mac_query *req;
 908         int status;
 909
 910         spin_lock_bh(&adapter->mcc_lock);
 911
 912         wrb = wrb_from_mccq(adapter);
 913         if (!wrb) {
 914                 status = -EBUSY;
 915                 goto err;
 916         }
 917         req = embedded_payload(wrb);
 918
 919         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 920                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 921         req->type = MAC_ADDRESS_TYPE_NETWORK;
 922         if (permanent) {
 923                 req->permanent = 1;
 924         } else {
 925                 req->if_id = cpu_to_le16((u16) if_handle);
 926                 req->pmac_id = cpu_to_le32(pmac_id);
 927                 req->permanent = 0;
 928         }
 929
 930         status = be_mcc_notify_wait(adapter);
 931         if (!status) {
 932                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 933                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 934         }
 935
 936 err:
 937         spin_unlock_bh(&adapter->mcc_lock);
 938         return status;
 939 }
 940
 941 /* Uses synchronous MCCQ */
 942 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 943                 u32 if_id, u32 *pmac_id, u32 domain)
 944 {
 945         struct be_mcc_wrb *wrb;
 946         struct be_cmd_req_pmac_add *req;
 947         int status;
 948
 949         spin_lock_bh(&adapter->mcc_lock);
 950
 951         wrb = wrb_from_mccq(adapter);
 952         if (!wrb) {
 953                 status = -EBUSY;
 954                 goto err;
 955         }
 956         req = embedded_payload(wrb);
 957
 958         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 959                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 960
 961         req->hdr.domain = domain;
 962         req->if_id = cpu_to_le32(if_id);
 963         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 964
 965         status = be_mcc_notify_wait(adapter);
 966         if (!status) {
 967                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 968                 *pmac_id = le32_to_cpu(resp->pmac_id);
 969         }
 970
 971 err:
 972         spin_unlock_bh(&adapter->mcc_lock);
 973
 974          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 975                 status = -EPERM;
 976
 977         return status;
 978 }
 979
 980 /* Uses synchronous MCCQ */
 981 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 982 {
 983         struct be_mcc_wrb *wrb;
 984         struct be_cmd_req_pmac_del *req;
 985         int status;
 986
 987         if (pmac_id == -1)
 988                 return 0;
 989
 990         spin_lock_bh(&adapter->mcc_lock);
 991
 992         wrb = wrb_from_mccq(adapter);
 993         if (!wrb) {
 994                 status = -EBUSY;
 995                 goto err;
 996         }
 997         req = embedded_payload(wrb);
 998
 999         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1000                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
1001
1002         req->hdr.domain = dom;
1003         req->if_id = cpu_to_le32(if_id);
1004         req->pmac_id = cpu_to_le32(pmac_id);
1005
1006         status = be_mcc_notify_wait(adapter);
1007
1008 err:
1009         spin_unlock_bh(&adapter->mcc_lock);
1010         return status;
1011 }
1012
1013 /* Uses Mbox */
1014 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1015                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1016 {
1017         struct be_mcc_wrb *wrb;
1018         struct be_cmd_req_cq_create *req;
1019         struct be_dma_mem *q_mem = &cq->dma_mem;
1020         void *ctxt;
1021         int status;
1022
1023         if (mutex_lock_interruptible(&adapter->mbox_lock))
1024                 return -1;
1025
1026         wrb = wrb_from_mbox(adapter);
1027         req = embedded_payload(wrb);
1028         ctxt = &req->context;
1029
1030         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1031                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
1032
1033         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1034
1035         if (BEx_chip(adapter)) {
1036                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1037                                                                 coalesce_wm);
1038                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1039                                                                 ctxt, no_delay);
1040                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1041                                                 __ilog2_u32(cq->len/256));
1042                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1043                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1044                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1045         } else {
1046                 req->hdr.version = 2;
1047                 req->page_size = 1; /* 1 for 4K */
1048
1049                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1050                  * Lancer uses COMMON_MODIFY_CQ to set this field
1051                  */
1052                 if (!lancer_chip(adapter))
1053                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1054                                       ctxt, coalesce_wm);
1055                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1056                                                                 no_delay);
1057                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1058                                                 __ilog2_u32(cq->len/256));
1059                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1060                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
1061                                                                 ctxt, 1);
1062                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1063                                                                 ctxt, eq->id);
1064         }
1065
1066         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1067
1068         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1069
1070         status = be_mbox_notify_wait(adapter);
1071         if (!status) {
1072                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1073                 cq->id = le16_to_cpu(resp->cq_id);
1074                 cq->created = true;
1075         }
1076
1077         mutex_unlock(&adapter->mbox_lock);
1078
1079         return status;
1080 }
1081
1082 static u32 be_encoded_q_len(int q_len)
1083 {
1084         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1085         if (len_encoded == 16)
1086                 len_encoded = 0;
1087         return len_encoded;
1088 }
1089
1090 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1091                                 struct be_queue_info *mccq,
1092                                 struct be_queue_info *cq)
1093 {
1094         struct be_mcc_wrb *wrb;
1095         struct be_cmd_req_mcc_ext_create *req;
1096         struct be_dma_mem *q_mem = &mccq->dma_mem;
1097         void *ctxt;
1098         int status;
1099
1100         if (mutex_lock_interruptible(&adapter->mbox_lock))
1101                 return -1;
1102
1103         wrb = wrb_from_mbox(adapter);
1104         req = embedded_payload(wrb);
1105         ctxt = &req->context;
1106
1107         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1109
1110         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1111         if (BEx_chip(adapter)) {
1112                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1113                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1114                                                 be_encoded_q_len(mccq->len));
1115                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1116         } else {
1117                 req->hdr.version = 1;
1118                 req->cq_id = cpu_to_le16(cq->id);
1119
1120                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1121                               be_encoded_q_len(mccq->len));
1122                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1123                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1124                               ctxt, cq->id);
1125                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1126                               ctxt, 1);
1127         }
1128
1129         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1130         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1131         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1132         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1133
1134         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1135
1136         status = be_mbox_notify_wait(adapter);
1137         if (!status) {
1138                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1139                 mccq->id = le16_to_cpu(resp->id);
1140                 mccq->created = true;
1141         }
1142         mutex_unlock(&adapter->mbox_lock);
1143
1144         return status;
1145 }
1146
1147 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1148                                 struct be_queue_info *mccq,
1149                                 struct be_queue_info *cq)
1150 {
1151         struct be_mcc_wrb *wrb;
1152         struct be_cmd_req_mcc_create *req;
1153         struct be_dma_mem *q_mem = &mccq->dma_mem;
1154         void *ctxt;
1155         int status;
1156
1157         if (mutex_lock_interruptible(&adapter->mbox_lock))
1158                 return -1;
1159
1160         wrb = wrb_from_mbox(adapter);
1161         req = embedded_payload(wrb);
1162         ctxt = &req->context;
1163
1164         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1165                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1166
1167         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1168
1169         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1170         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1171                         be_encoded_q_len(mccq->len));
1172         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1173
1174         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1175
1176         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1177
1178         status = be_mbox_notify_wait(adapter);
1179         if (!status) {
1180                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1181                 mccq->id = le16_to_cpu(resp->id);
1182                 mccq->created = true;
1183         }
1184
1185         mutex_unlock(&adapter->mbox_lock);
1186         return status;
1187 }
1188
1189 int be_cmd_mccq_create(struct be_adapter *adapter,
1190                         struct be_queue_info *mccq,
1191                         struct be_queue_info *cq)
1192 {
1193         int status;
1194
1195         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1196         if (status && BEx_chip(adapter)) {
1197                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1198                         "or newer to avoid conflicting priorities between NIC "
1199                         "and FCoE traffic");
1200                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1201         }
1202         return status;
1203 }
1204
1205 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1206 {
1207         struct be_mcc_wrb wrb = {0};
1208         struct be_cmd_req_eth_tx_create *req;
1209         struct be_queue_info *txq = &txo->q;
1210         struct be_queue_info *cq = &txo->cq;
1211         struct be_dma_mem *q_mem = &txq->dma_mem;
1212         int status, ver = 0;
1213
1214         req = embedded_payload(&wrb);
1215         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1216                                 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1217
1218         if (lancer_chip(adapter)) {
1219                 req->hdr.version = 1;
1220         } else if (BEx_chip(adapter)) {
1221                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1222                         req->hdr.version = 2;
1223         } else { /* For SH */
1224                 req->hdr.version = 2;
1225         }
1226
1227         if (req->hdr.version > 0)
1228                 req->if_id = cpu_to_le16(adapter->if_handle);
1229         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1230         req->ulp_num = BE_ULP1_NUM;
1231         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1232         req->cq_id = cpu_to_le16(cq->id);
1233         req->queue_size = be_encoded_q_len(txq->len);
1234         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1235         ver = req->hdr.version;
1236
1237         status = be_cmd_notify_wait(adapter, &wrb);
1238         if (!status) {
1239                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1240                 txq->id = le16_to_cpu(resp->cid);
1241                 if (ver == 2)
1242                         txo->db_offset = le32_to_cpu(resp->db_offset);
1243                 else
1244                         txo->db_offset = DB_TXULP1_OFFSET;
1245                 txq->created = true;
1246         }
1247
1248         return status;
1249 }
1250
1251 /* Uses MCC */
1252 int be_cmd_rxq_create(struct be_adapter *adapter,
1253                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1254                 u32 if_id, u32 rss, u8 *rss_id)
1255 {
1256         struct be_mcc_wrb *wrb;
1257         struct be_cmd_req_eth_rx_create *req;
1258         struct be_dma_mem *q_mem = &rxq->dma_mem;
1259         int status;
1260
1261         spin_lock_bh(&adapter->mcc_lock);
1262
1263         wrb = wrb_from_mccq(adapter);
1264         if (!wrb) {
1265                 status = -EBUSY;
1266                 goto err;
1267         }
1268         req = embedded_payload(wrb);
1269
1270         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1271                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1272
1273         req->cq_id = cpu_to_le16(cq_id);
1274         req->frag_size = fls(frag_size) - 1;
1275         req->num_pages = 2;
1276         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1277         req->interface_id = cpu_to_le32(if_id);
1278         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1279         req->rss_queue = cpu_to_le32(rss);
1280
1281         status = be_mcc_notify_wait(adapter);
1282         if (!status) {
1283                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1284                 rxq->id = le16_to_cpu(resp->id);
1285                 rxq->created = true;
1286                 *rss_id = resp->rss_id;
1287         }
1288
1289 err:
1290         spin_unlock_bh(&adapter->mcc_lock);
1291         return status;
1292 }
1293
1294 /* Generic destroyer function for all types of queues
1295  * Uses Mbox
1296  */
1297 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1298                 int queue_type)
1299 {
1300         struct be_mcc_wrb *wrb;
1301         struct be_cmd_req_q_destroy *req;
1302         u8 subsys = 0, opcode = 0;
1303         int status;
1304
1305         if (mutex_lock_interruptible(&adapter->mbox_lock))
1306                 return -1;
1307
1308         wrb = wrb_from_mbox(adapter);
1309         req = embedded_payload(wrb);
1310
1311         switch (queue_type) {
1312         case QTYPE_EQ:
1313                 subsys = CMD_SUBSYSTEM_COMMON;
1314                 opcode = OPCODE_COMMON_EQ_DESTROY;
1315                 break;
1316         case QTYPE_CQ:
1317                 subsys = CMD_SUBSYSTEM_COMMON;
1318                 opcode = OPCODE_COMMON_CQ_DESTROY;
1319                 break;
1320         case QTYPE_TXQ:
1321                 subsys = CMD_SUBSYSTEM_ETH;
1322                 opcode = OPCODE_ETH_TX_DESTROY;
1323                 break;
1324         case QTYPE_RXQ:
1325                 subsys = CMD_SUBSYSTEM_ETH;
1326                 opcode = OPCODE_ETH_RX_DESTROY;
1327                 break;
1328         case QTYPE_MCCQ:
1329                 subsys = CMD_SUBSYSTEM_COMMON;
1330                 opcode = OPCODE_COMMON_MCC_DESTROY;
1331                 break;
1332         default:
1333                 BUG();
1334         }
1335
1336         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1337                                 NULL);
1338         req->id = cpu_to_le16(q->id);
1339
1340         status = be_mbox_notify_wait(adapter);
1341         q->created = false;
1342
1343         mutex_unlock(&adapter->mbox_lock);
1344         return status;
1345 }
1346
1347 /* Uses MCC */
1348 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1349 {
1350         struct be_mcc_wrb *wrb;
1351         struct be_cmd_req_q_destroy *req;
1352         int status;
1353
1354         spin_lock_bh(&adapter->mcc_lock);
1355
1356         wrb = wrb_from_mccq(adapter);
1357         if (!wrb) {
1358                 status = -EBUSY;
1359                 goto err;
1360         }
1361         req = embedded_payload(wrb);
1362
1363         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1364                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1365         req->id = cpu_to_le16(q->id);
1366
1367         status = be_mcc_notify_wait(adapter);
1368         q->created = false;
1369
1370 err:
1371         spin_unlock_bh(&adapter->mcc_lock);
1372         return status;
1373 }
1374
1375 /* Create an rx filtering policy configuration on an i/f
1376  * Will use MBOX only if MCCQ has not been created.
1377  */
1378 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1379                      u32 *if_handle, u32 domain)
1380 {
1381         struct be_mcc_wrb wrb = {0};
1382         struct be_cmd_req_if_create *req;
1383         int status;
1384
1385         req = embedded_payload(&wrb);
1386         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1387                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL);
1388         req->hdr.domain = domain;
1389         req->capability_flags = cpu_to_le32(cap_flags);
1390         req->enable_flags = cpu_to_le32(en_flags);
1391         req->pmac_invalid = true;
1392
1393         status = be_cmd_notify_wait(adapter, &wrb);
1394         if (!status) {
1395                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1396                 *if_handle = le32_to_cpu(resp->interface_id);
1397
1398                 /* Hack to retrieve VF's pmac-id on BE3 */
1399                 if (BE3_chip(adapter) && !be_physfn(adapter))
1400                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1401         }
1402         return status;
1403 }
1404
1405 /* Uses MCCQ */
1406 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1407 {
1408         struct be_mcc_wrb *wrb;
1409         struct be_cmd_req_if_destroy *req;
1410         int status;
1411
1412         if (interface_id == -1)
1413                 return 0;
1414
1415         spin_lock_bh(&adapter->mcc_lock);
1416
1417         wrb = wrb_from_mccq(adapter);
1418         if (!wrb) {
1419                 status = -EBUSY;
1420                 goto err;
1421         }
1422         req = embedded_payload(wrb);
1423
1424         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1425                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1426         req->hdr.domain = domain;
1427         req->interface_id = cpu_to_le32(interface_id);
1428
1429         status = be_mcc_notify_wait(adapter);
1430 err:
1431         spin_unlock_bh(&adapter->mcc_lock);
1432         return status;
1433 }
1434
1435 /* Get stats is a non embedded command: the request is not embedded inside
1436  * WRB but is a separate dma memory block
1437  * Uses asynchronous MCC
1438  */
1439 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1440 {
1441         struct be_mcc_wrb *wrb;
1442         struct be_cmd_req_hdr *hdr;
1443         int status = 0;
1444
1445         spin_lock_bh(&adapter->mcc_lock);
1446
1447         wrb = wrb_from_mccq(adapter);
1448         if (!wrb) {
1449                 status = -EBUSY;
1450                 goto err;
1451         }
1452         hdr = nonemb_cmd->va;
1453
1454         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1455                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1456
1457         /* version 1 of the cmd is not supported only by BE2 */
1458         if (BE2_chip(adapter))
1459                 hdr->version = 0;
1460         if (BE3_chip(adapter) || lancer_chip(adapter))
1461                 hdr->version = 1;
1462         else
1463                 hdr->version = 2;
1464
1465         be_mcc_notify(adapter);
1466         adapter->stats_cmd_sent = true;
1467
1468 err:
1469         spin_unlock_bh(&adapter->mcc_lock);
1470         return status;
1471 }
1472
1473 /* Lancer Stats */
1474 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1475                                 struct be_dma_mem *nonemb_cmd)
1476 {
1477
1478         struct be_mcc_wrb *wrb;
1479         struct lancer_cmd_req_pport_stats *req;
1480         int status = 0;
1481
1482         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1483                             CMD_SUBSYSTEM_ETH))
1484                 return -EPERM;
1485
1486         spin_lock_bh(&adapter->mcc_lock);
1487
1488         wrb = wrb_from_mccq(adapter);
1489         if (!wrb) {
1490                 status = -EBUSY;
1491                 goto err;
1492         }
1493         req = nonemb_cmd->va;
1494
1495         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1496                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1497                         nonemb_cmd);
1498
1499         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1500         req->cmd_params.params.reset_stats = 0;
1501
1502         be_mcc_notify(adapter);
1503         adapter->stats_cmd_sent = true;
1504
1505 err:
1506         spin_unlock_bh(&adapter->mcc_lock);
1507         return status;
1508 }
1509
1510 static int be_mac_to_link_speed(int mac_speed)
1511 {
1512         switch (mac_speed) {
1513         case PHY_LINK_SPEED_ZERO:
1514                 return 0;
1515         case PHY_LINK_SPEED_10MBPS:
1516                 return 10;
1517         case PHY_LINK_SPEED_100MBPS:
1518                 return 100;
1519         case PHY_LINK_SPEED_1GBPS:
1520                 return 1000;
1521         case PHY_LINK_SPEED_10GBPS:
1522                 return 10000;
1523         case PHY_LINK_SPEED_20GBPS:
1524                 return 20000;
1525         case PHY_LINK_SPEED_25GBPS:
1526                 return 25000;
1527         case PHY_LINK_SPEED_40GBPS:
1528                 return 40000;
1529         }
1530         return 0;
1531 }
1532
1533 /* Uses synchronous mcc
1534  * Returns link_speed in Mbps
1535  */
1536 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1537                              u8 *link_status, u32 dom)
1538 {
1539         struct be_mcc_wrb *wrb;
1540         struct be_cmd_req_link_status *req;
1541         int status;
1542
1543         spin_lock_bh(&adapter->mcc_lock);
1544
1545         if (link_status)
1546                 *link_status = LINK_DOWN;
1547
1548         wrb = wrb_from_mccq(adapter);
1549         if (!wrb) {
1550                 status = -EBUSY;
1551                 goto err;
1552         }
1553         req = embedded_payload(wrb);
1554
1555         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1556                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1557
1558         /* version 1 of the cmd is not supported only by BE2 */
1559         if (!BE2_chip(adapter))
1560                 req->hdr.version = 1;
1561
1562         req->hdr.domain = dom;
1563
1564         status = be_mcc_notify_wait(adapter);
1565         if (!status) {
1566                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1567                 if (link_speed) {
1568                         *link_speed = resp->link_speed ?
1569                                       le16_to_cpu(resp->link_speed) * 10 :
1570                                       be_mac_to_link_speed(resp->mac_speed);
1571
1572                         if (!resp->logical_link_status)
1573                                 *link_speed = 0;
1574                 }
1575                 if (link_status)
1576                         *link_status = resp->logical_link_status;
1577         }
1578
1579 err:
1580         spin_unlock_bh(&adapter->mcc_lock);
1581         return status;
1582 }
1583
1584 /* Uses synchronous mcc */
1585 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1586 {
1587         struct be_mcc_wrb *wrb;
1588         struct be_cmd_req_get_cntl_addnl_attribs *req;
1589         int status = 0;
1590
1591         spin_lock_bh(&adapter->mcc_lock);
1592
1593         wrb = wrb_from_mccq(adapter);
1594         if (!wrb) {
1595                 status = -EBUSY;
1596                 goto err;
1597         }
1598         req = embedded_payload(wrb);
1599
1600         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1601                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1602                 wrb, NULL);
1603
1604         be_mcc_notify(adapter);
1605
1606 err:
1607         spin_unlock_bh(&adapter->mcc_lock);
1608         return status;
1609 }
1610
1611 /* Uses synchronous mcc */
1612 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1613 {
1614         struct be_mcc_wrb *wrb;
1615         struct be_cmd_req_get_fat *req;
1616         int status;
1617
1618         spin_lock_bh(&adapter->mcc_lock);
1619
1620         wrb = wrb_from_mccq(adapter);
1621         if (!wrb) {
1622                 status = -EBUSY;
1623                 goto err;
1624         }
1625         req = embedded_payload(wrb);
1626
1627         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1628                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1629         req->fat_operation = cpu_to_le32(QUERY_FAT);
1630         status = be_mcc_notify_wait(adapter);
1631         if (!status) {
1632                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1633                 if (log_size && resp->log_size)
1634                         *log_size = le32_to_cpu(resp->log_size) -
1635                                         sizeof(u32);
1636         }
1637 err:
1638         spin_unlock_bh(&adapter->mcc_lock);
1639         return status;
1640 }
1641
1642 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1643 {
1644         struct be_dma_mem get_fat_cmd;
1645         struct be_mcc_wrb *wrb;
1646         struct be_cmd_req_get_fat *req;
1647         u32 offset = 0, total_size, buf_size,
1648                                 log_offset = sizeof(u32), payload_len;
1649         int status;
1650
1651         if (buf_len == 0)
1652                 return;
1653
1654         total_size = buf_len;
1655
1656         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1657         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1658                         get_fat_cmd.size,
1659                         &get_fat_cmd.dma);
1660         if (!get_fat_cmd.va) {
1661                 status = -ENOMEM;
1662                 dev_err(&adapter->pdev->dev,
1663                 "Memory allocation failure while retrieving FAT data\n");
1664                 return;
1665         }
1666
1667         spin_lock_bh(&adapter->mcc_lock);
1668
1669         while (total_size) {
1670                 buf_size = min(total_size, (u32)60*1024);
1671                 total_size -= buf_size;
1672
1673                 wrb = wrb_from_mccq(adapter);
1674                 if (!wrb) {
1675                         status = -EBUSY;
1676                         goto err;
1677                 }
1678                 req = get_fat_cmd.va;
1679
1680                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1681                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1682                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1683                                 &get_fat_cmd);
1684
1685                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1686                 req->read_log_offset = cpu_to_le32(log_offset);
1687                 req->read_log_length = cpu_to_le32(buf_size);
1688                 req->data_buffer_size = cpu_to_le32(buf_size);
1689
1690                 status = be_mcc_notify_wait(adapter);
1691                 if (!status) {
1692                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1693                         memcpy(buf + offset,
1694                                 resp->data_buffer,
1695                                 le32_to_cpu(resp->read_log_length));
1696                 } else {
1697                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1698                         goto err;
1699                 }
1700                 offset += buf_size;
1701                 log_offset += buf_size;
1702         }
1703 err:
1704         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1705                         get_fat_cmd.va,
1706                         get_fat_cmd.dma);
1707         spin_unlock_bh(&adapter->mcc_lock);
1708 }
1709
1710 /* Uses synchronous mcc */
1711 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1712                         char *fw_on_flash)
1713 {
1714         struct be_mcc_wrb *wrb;
1715         struct be_cmd_req_get_fw_version *req;
1716         int status;
1717
1718         spin_lock_bh(&adapter->mcc_lock);
1719
1720         wrb = wrb_from_mccq(adapter);
1721         if (!wrb) {
1722                 status = -EBUSY;
1723                 goto err;
1724         }
1725
1726         req = embedded_payload(wrb);
1727
1728         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1729                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1730         status = be_mcc_notify_wait(adapter);
1731         if (!status) {
1732                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1733                 strcpy(fw_ver, resp->firmware_version_string);
1734                 if (fw_on_flash)
1735                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1736         }
1737 err:
1738         spin_unlock_bh(&adapter->mcc_lock);
1739         return status;
1740 }
1741
1742 /* set the EQ delay interval of an EQ to specified value
1743  * Uses async mcc
1744  */
1745 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1746                       int num)
1747 {
1748         struct be_mcc_wrb *wrb;
1749         struct be_cmd_req_modify_eq_delay *req;
1750         int status = 0, i;
1751
1752         spin_lock_bh(&adapter->mcc_lock);
1753
1754         wrb = wrb_from_mccq(adapter);
1755         if (!wrb) {
1756                 status = -EBUSY;
1757                 goto err;
1758         }
1759         req = embedded_payload(wrb);
1760
1761         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1763
1764         req->num_eq = cpu_to_le32(num);
1765         for (i = 0; i < num; i++) {
1766                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1767                 req->set_eqd[i].phase = 0;
1768                 req->set_eqd[i].delay_multiplier =
1769                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1770         }
1771
1772         be_mcc_notify(adapter);
1773 err:
1774         spin_unlock_bh(&adapter->mcc_lock);
1775         return status;
1776 }
1777
1778 /* Uses sycnhronous mcc */
1779 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1780                        u32 num, bool promiscuous)
1781 {
1782         struct be_mcc_wrb *wrb;
1783         struct be_cmd_req_vlan_config *req;
1784         int status;
1785
1786         spin_lock_bh(&adapter->mcc_lock);
1787
1788         wrb = wrb_from_mccq(adapter);
1789         if (!wrb) {
1790                 status = -EBUSY;
1791                 goto err;
1792         }
1793         req = embedded_payload(wrb);
1794
1795         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1796                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1797
1798         req->interface_id = if_id;
1799         req->promiscuous = promiscuous;
1800         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1801         req->num_vlan = num;
1802         if (!promiscuous) {
1803                 memcpy(req->normal_vlan, vtag_array,
1804                         req->num_vlan * sizeof(vtag_array[0]));
1805         }
1806
1807         status = be_mcc_notify_wait(adapter);
1808
1809 err:
1810         spin_unlock_bh(&adapter->mcc_lock);
1811         return status;
1812 }
1813
1814 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1815 {
1816         struct be_mcc_wrb *wrb;
1817         struct be_dma_mem *mem = &adapter->rx_filter;
1818         struct be_cmd_req_rx_filter *req = mem->va;
1819         int status;
1820
1821         spin_lock_bh(&adapter->mcc_lock);
1822
1823         wrb = wrb_from_mccq(adapter);
1824         if (!wrb) {
1825                 status = -EBUSY;
1826                 goto err;
1827         }
1828         memset(req, 0, sizeof(*req));
1829         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1830                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1831                                 wrb, mem);
1832
1833         req->if_id = cpu_to_le32(adapter->if_handle);
1834         if (flags & IFF_PROMISC) {
1835                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1836                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1837                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1838                 if (value == ON)
1839                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1840                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1841                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1842         } else if (flags & IFF_ALLMULTI) {
1843                 req->if_flags_mask = req->if_flags =
1844                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1845         } else if (flags & BE_FLAGS_VLAN_PROMISC) {
1846                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1847
1848                 if (value == ON)
1849                         req->if_flags =
1850                                 cpu_to_le32(BE_IF_FLAGS_VLAN_PROMISCUOUS);
1851         } else {
1852                 struct netdev_hw_addr *ha;
1853                 int i = 0;
1854
1855                 req->if_flags_mask = req->if_flags =
1856                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1857
1858                 /* Reset mcast promisc mode if already set by setting mask
1859                  * and not setting flags field
1860                  */
1861                 req->if_flags_mask |=
1862                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1863                                     be_if_cap_flags(adapter));
1864                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1865                 netdev_for_each_mc_addr(ha, adapter->netdev)
1866                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1867         }
1868
1869         if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1870              req->if_flags_mask) {
1871                 dev_warn(&adapter->pdev->dev,
1872                          "Cannot set rx filter flags 0x%x\n",
1873                          req->if_flags_mask);
1874                 dev_warn(&adapter->pdev->dev,
1875                          "Interface is capable of 0x%x flags only\n",
1876                          be_if_cap_flags(adapter));
1877         }
1878         req->if_flags_mask &= cpu_to_le32(be_if_cap_flags(adapter));
1879
1880         status = be_mcc_notify_wait(adapter);
1881
1882 err:
1883         spin_unlock_bh(&adapter->mcc_lock);
1884         return status;
1885 }
1886
1887 /* Uses synchrounous mcc */
1888 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1889 {
1890         struct be_mcc_wrb *wrb;
1891         struct be_cmd_req_set_flow_control *req;
1892         int status;
1893
1894         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1895                             CMD_SUBSYSTEM_COMMON))
1896                 return -EPERM;
1897
1898         spin_lock_bh(&adapter->mcc_lock);
1899
1900         wrb = wrb_from_mccq(adapter);
1901         if (!wrb) {
1902                 status = -EBUSY;
1903                 goto err;
1904         }
1905         req = embedded_payload(wrb);
1906
1907         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1908                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1909
1910         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1911         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1912
1913         status = be_mcc_notify_wait(adapter);
1914
1915 err:
1916         spin_unlock_bh(&adapter->mcc_lock);
1917         return status;
1918 }
1919
1920 /* Uses sycn mcc */
1921 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1922 {
1923         struct be_mcc_wrb *wrb;
1924         struct be_cmd_req_get_flow_control *req;
1925         int status;
1926
1927         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1928                             CMD_SUBSYSTEM_COMMON))
1929                 return -EPERM;
1930
1931         spin_lock_bh(&adapter->mcc_lock);
1932
1933         wrb = wrb_from_mccq(adapter);
1934         if (!wrb) {
1935                 status = -EBUSY;
1936                 goto err;
1937         }
1938         req = embedded_payload(wrb);
1939
1940         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1941                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1942
1943         status = be_mcc_notify_wait(adapter);
1944         if (!status) {
1945                 struct be_cmd_resp_get_flow_control *resp =
1946                                                 embedded_payload(wrb);
1947                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1948                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1949         }
1950
1951 err:
1952         spin_unlock_bh(&adapter->mcc_lock);
1953         return status;
1954 }
1955
1956 /* Uses mbox */
1957 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1958                         u32 *mode, u32 *caps, u16 *asic_rev)
1959 {
1960         struct be_mcc_wrb *wrb;
1961         struct be_cmd_req_query_fw_cfg *req;
1962         int status;
1963
1964         if (mutex_lock_interruptible(&adapter->mbox_lock))
1965                 return -1;
1966
1967         wrb = wrb_from_mbox(adapter);
1968         req = embedded_payload(wrb);
1969
1970         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1971                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1972
1973         status = be_mbox_notify_wait(adapter);
1974         if (!status) {
1975                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1976                 *port_num = le32_to_cpu(resp->phys_port);
1977                 *mode = le32_to_cpu(resp->function_mode);
1978                 *caps = le32_to_cpu(resp->function_caps);
1979                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1980         }
1981
1982         mutex_unlock(&adapter->mbox_lock);
1983         return status;
1984 }
1985
1986 /* Uses mbox */
1987 int be_cmd_reset_function(struct be_adapter *adapter)
1988 {
1989         struct be_mcc_wrb *wrb;
1990         struct be_cmd_req_hdr *req;
1991         int status;
1992
1993         if (lancer_chip(adapter)) {
1994                 status = lancer_wait_ready(adapter);
1995                 if (!status) {
1996                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1997                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1998                         status = lancer_test_and_set_rdy_state(adapter);
1999                 }
2000                 if (status) {
2001                         dev_err(&adapter->pdev->dev,
2002                                 "Adapter in non recoverable error\n");
2003                 }
2004                 return status;
2005         }
2006
2007         if (mutex_lock_interruptible(&adapter->mbox_lock))
2008                 return -1;
2009
2010         wrb = wrb_from_mbox(adapter);
2011         req = embedded_payload(wrb);
2012
2013         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2014                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
2015
2016         status = be_mbox_notify_wait(adapter);
2017
2018         mutex_unlock(&adapter->mbox_lock);
2019         return status;
2020 }
2021
2022 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2023                         u32 rss_hash_opts, u16 table_size)
2024 {
2025         struct be_mcc_wrb *wrb;
2026         struct be_cmd_req_rss_config *req;
2027         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
2028                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
2029                         0x3ea83c02, 0x4a110304};
2030         int status;
2031
2032         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2033                 return 0;
2034
2035         if (mutex_lock_interruptible(&adapter->mbox_lock))
2036                 return -1;
2037
2038         wrb = wrb_from_mbox(adapter);
2039         req = embedded_payload(wrb);
2040
2041         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2042                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2043
2044         req->if_id = cpu_to_le32(adapter->if_handle);
2045         req->enable_rss = cpu_to_le16(rss_hash_opts);
2046         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2047
2048         if (lancer_chip(adapter) || skyhawk_chip(adapter))
2049                 req->hdr.version = 1;
2050
2051         memcpy(req->cpu_table, rsstable, table_size);
2052         memcpy(req->hash, myhash, sizeof(myhash));
2053         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2054
2055         status = be_mbox_notify_wait(adapter);
2056
2057         mutex_unlock(&adapter->mbox_lock);
2058         return status;
2059 }
2060
2061 /* Uses sync mcc */
2062 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2063                         u8 bcn, u8 sts, u8 state)
2064 {
2065         struct be_mcc_wrb *wrb;
2066         struct be_cmd_req_enable_disable_beacon *req;
2067         int status;
2068
2069         spin_lock_bh(&adapter->mcc_lock);
2070
2071         wrb = wrb_from_mccq(adapter);
2072         if (!wrb) {
2073                 status = -EBUSY;
2074                 goto err;
2075         }
2076         req = embedded_payload(wrb);
2077
2078         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2079                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2080
2081         req->port_num = port_num;
2082         req->beacon_state = state;
2083         req->beacon_duration = bcn;
2084         req->status_duration = sts;
2085
2086         status = be_mcc_notify_wait(adapter);
2087
2088 err:
2089         spin_unlock_bh(&adapter->mcc_lock);
2090         return status;
2091 }
2092
2093 /* Uses sync mcc */
2094 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2095 {
2096         struct be_mcc_wrb *wrb;
2097         struct be_cmd_req_get_beacon_state *req;
2098         int status;
2099
2100         spin_lock_bh(&adapter->mcc_lock);
2101
2102         wrb = wrb_from_mccq(adapter);
2103         if (!wrb) {
2104                 status = -EBUSY;
2105                 goto err;
2106         }
2107         req = embedded_payload(wrb);
2108
2109         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2110                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2111
2112         req->port_num = port_num;
2113
2114         status = be_mcc_notify_wait(adapter);
2115         if (!status) {
2116                 struct be_cmd_resp_get_beacon_state *resp =
2117                                                 embedded_payload(wrb);
2118                 *state = resp->beacon_state;
2119         }
2120
2121 err:
2122         spin_unlock_bh(&adapter->mcc_lock);
2123         return status;
2124 }
2125
2126 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2127                             u32 data_size, u32 data_offset,
2128                             const char *obj_name, u32 *data_written,
2129                             u8 *change_status, u8 *addn_status)
2130 {
2131         struct be_mcc_wrb *wrb;
2132         struct lancer_cmd_req_write_object *req;
2133         struct lancer_cmd_resp_write_object *resp;
2134         void *ctxt = NULL;
2135         int status;
2136
2137         spin_lock_bh(&adapter->mcc_lock);
2138         adapter->flash_status = 0;
2139
2140         wrb = wrb_from_mccq(adapter);
2141         if (!wrb) {
2142                 status = -EBUSY;
2143                 goto err_unlock;
2144         }
2145
2146         req = embedded_payload(wrb);
2147
2148         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2149                                 OPCODE_COMMON_WRITE_OBJECT,
2150                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2151                                 NULL);
2152
2153         ctxt = &req->context;
2154         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2155                         write_length, ctxt, data_size);
2156
2157         if (data_size == 0)
2158                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2159                                 eof, ctxt, 1);
2160         else
2161                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2162                                 eof, ctxt, 0);
2163
2164         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2165         req->write_offset = cpu_to_le32(data_offset);
2166         strcpy(req->object_name, obj_name);
2167         req->descriptor_count = cpu_to_le32(1);
2168         req->buf_len = cpu_to_le32(data_size);
2169         req->addr_low = cpu_to_le32((cmd->dma +
2170                                 sizeof(struct lancer_cmd_req_write_object))
2171                                 & 0xFFFFFFFF);
2172         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2173                                 sizeof(struct lancer_cmd_req_write_object)));
2174
2175         be_mcc_notify(adapter);
2176         spin_unlock_bh(&adapter->mcc_lock);
2177
2178         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2179                                          msecs_to_jiffies(60000)))
2180                 status = -1;
2181         else
2182                 status = adapter->flash_status;
2183
2184         resp = embedded_payload(wrb);
2185         if (!status) {
2186                 *data_written = le32_to_cpu(resp->actual_write_len);
2187                 *change_status = resp->change_status;
2188         } else {
2189                 *addn_status = resp->additional_status;
2190         }
2191
2192         return status;
2193
2194 err_unlock:
2195         spin_unlock_bh(&adapter->mcc_lock);
2196         return status;
2197 }
2198
2199 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2200                 u32 data_size, u32 data_offset, const char *obj_name,
2201                 u32 *data_read, u32 *eof, u8 *addn_status)
2202 {
2203         struct be_mcc_wrb *wrb;
2204         struct lancer_cmd_req_read_object *req;
2205         struct lancer_cmd_resp_read_object *resp;
2206         int status;
2207
2208         spin_lock_bh(&adapter->mcc_lock);
2209
2210         wrb = wrb_from_mccq(adapter);
2211         if (!wrb) {
2212                 status = -EBUSY;
2213                 goto err_unlock;
2214         }
2215
2216         req = embedded_payload(wrb);
2217
2218         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2219                         OPCODE_COMMON_READ_OBJECT,
2220                         sizeof(struct lancer_cmd_req_read_object), wrb,
2221                         NULL);
2222
2223         req->desired_read_len = cpu_to_le32(data_size);
2224         req->read_offset = cpu_to_le32(data_offset);
2225         strcpy(req->object_name, obj_name);
2226         req->descriptor_count = cpu_to_le32(1);
2227         req->buf_len = cpu_to_le32(data_size);
2228         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2229         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2230
2231         status = be_mcc_notify_wait(adapter);
2232
2233         resp = embedded_payload(wrb);
2234         if (!status) {
2235                 *data_read = le32_to_cpu(resp->actual_read_len);
2236                 *eof = le32_to_cpu(resp->eof);
2237         } else {
2238                 *addn_status = resp->additional_status;
2239         }
2240
2241 err_unlock:
2242         spin_unlock_bh(&adapter->mcc_lock);
2243         return status;
2244 }
2245
2246 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2247                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2248 {
2249         struct be_mcc_wrb *wrb;
2250         struct be_cmd_write_flashrom *req;
2251         int status;
2252
2253         spin_lock_bh(&adapter->mcc_lock);
2254         adapter->flash_status = 0;
2255
2256         wrb = wrb_from_mccq(adapter);
2257         if (!wrb) {
2258                 status = -EBUSY;
2259                 goto err_unlock;
2260         }
2261         req = cmd->va;
2262
2263         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2264                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2265
2266         req->params.op_type = cpu_to_le32(flash_type);
2267         req->params.op_code = cpu_to_le32(flash_opcode);
2268         req->params.data_buf_size = cpu_to_le32(buf_size);
2269
2270         be_mcc_notify(adapter);
2271         spin_unlock_bh(&adapter->mcc_lock);
2272
2273         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2274                                          msecs_to_jiffies(40000)))
2275                 status = -1;
2276         else
2277                 status = adapter->flash_status;
2278
2279         return status;
2280
2281 err_unlock:
2282         spin_unlock_bh(&adapter->mcc_lock);
2283         return status;
2284 }
2285
2286 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2287                          int offset)
2288 {
2289         struct be_mcc_wrb *wrb;
2290         struct be_cmd_read_flash_crc *req;
2291         int status;
2292
2293         spin_lock_bh(&adapter->mcc_lock);
2294
2295         wrb = wrb_from_mccq(adapter);
2296         if (!wrb) {
2297                 status = -EBUSY;
2298                 goto err;
2299         }
2300         req = embedded_payload(wrb);
2301
2302         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2303                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2304                                wrb, NULL);
2305
2306         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2307         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2308         req->params.offset = cpu_to_le32(offset);
2309         req->params.data_buf_size = cpu_to_le32(0x4);
2310
2311         status = be_mcc_notify_wait(adapter);
2312         if (!status)
2313                 memcpy(flashed_crc, req->crc, 4);
2314
2315 err:
2316         spin_unlock_bh(&adapter->mcc_lock);
2317         return status;
2318 }
2319
2320 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2321                                 struct be_dma_mem *nonemb_cmd)
2322 {
2323         struct be_mcc_wrb *wrb;
2324         struct be_cmd_req_acpi_wol_magic_config *req;
2325         int status;
2326
2327         spin_lock_bh(&adapter->mcc_lock);
2328
2329         wrb = wrb_from_mccq(adapter);
2330         if (!wrb) {
2331                 status = -EBUSY;
2332                 goto err;
2333         }
2334         req = nonemb_cmd->va;
2335
2336         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2337                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2338                 nonemb_cmd);
2339         memcpy(req->magic_mac, mac, ETH_ALEN);
2340
2341         status = be_mcc_notify_wait(adapter);
2342
2343 err:
2344         spin_unlock_bh(&adapter->mcc_lock);
2345         return status;
2346 }
2347
2348 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2349                         u8 loopback_type, u8 enable)
2350 {
2351         struct be_mcc_wrb *wrb;
2352         struct be_cmd_req_set_lmode *req;
2353         int status;
2354
2355         spin_lock_bh(&adapter->mcc_lock);
2356
2357         wrb = wrb_from_mccq(adapter);
2358         if (!wrb) {
2359                 status = -EBUSY;
2360                 goto err;
2361         }
2362
2363         req = embedded_payload(wrb);
2364
2365         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2366                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2367                         NULL);
2368
2369         req->src_port = port_num;
2370         req->dest_port = port_num;
2371         req->loopback_type = loopback_type;
2372         req->loopback_state = enable;
2373
2374         status = be_mcc_notify_wait(adapter);
2375 err:
2376         spin_unlock_bh(&adapter->mcc_lock);
2377         return status;
2378 }
2379
2380 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2381                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2382 {
2383         struct be_mcc_wrb *wrb;
2384         struct be_cmd_req_loopback_test *req;
2385         struct be_cmd_resp_loopback_test *resp;
2386         int status;
2387
2388         spin_lock_bh(&adapter->mcc_lock);
2389
2390         wrb = wrb_from_mccq(adapter);
2391         if (!wrb) {
2392                 status = -EBUSY;
2393                 goto err;
2394         }
2395
2396         req = embedded_payload(wrb);
2397
2398         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2399                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2400
2401         req->hdr.timeout = cpu_to_le32(15);
2402         req->pattern = cpu_to_le64(pattern);
2403         req->src_port = cpu_to_le32(port_num);
2404         req->dest_port = cpu_to_le32(port_num);
2405         req->pkt_size = cpu_to_le32(pkt_size);
2406         req->num_pkts = cpu_to_le32(num_pkts);
2407         req->loopback_type = cpu_to_le32(loopback_type);
2408
2409         be_mcc_notify(adapter);
2410
2411         spin_unlock_bh(&adapter->mcc_lock);
2412
2413         wait_for_completion(&adapter->et_cmd_compl);
2414         resp = embedded_payload(wrb);
2415         status = le32_to_cpu(resp->status);
2416
2417         return status;
2418 err:
2419         spin_unlock_bh(&adapter->mcc_lock);
2420         return status;
2421 }
2422
2423 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2424                                 u32 byte_cnt, struct be_dma_mem *cmd)
2425 {
2426         struct be_mcc_wrb *wrb;
2427         struct be_cmd_req_ddrdma_test *req;
2428         int status;
2429         int i, j = 0;
2430
2431         spin_lock_bh(&adapter->mcc_lock);
2432
2433         wrb = wrb_from_mccq(adapter);
2434         if (!wrb) {
2435                 status = -EBUSY;
2436                 goto err;
2437         }
2438         req = cmd->va;
2439         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2440                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2441
2442         req->pattern = cpu_to_le64(pattern);
2443         req->byte_count = cpu_to_le32(byte_cnt);
2444         for (i = 0; i < byte_cnt; i++) {
2445                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2446                 j++;
2447                 if (j > 7)
2448                         j = 0;
2449         }
2450
2451         status = be_mcc_notify_wait(adapter);
2452
2453         if (!status) {
2454                 struct be_cmd_resp_ddrdma_test *resp;
2455                 resp = cmd->va;
2456                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2457                                 resp->snd_err) {
2458                         status = -1;
2459                 }
2460         }
2461
2462 err:
2463         spin_unlock_bh(&adapter->mcc_lock);
2464         return status;
2465 }
2466
2467 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2468                                 struct be_dma_mem *nonemb_cmd)
2469 {
2470         struct be_mcc_wrb *wrb;
2471         struct be_cmd_req_seeprom_read *req;
2472         int status;
2473
2474         spin_lock_bh(&adapter->mcc_lock);
2475
2476         wrb = wrb_from_mccq(adapter);
2477         if (!wrb) {
2478                 status = -EBUSY;
2479                 goto err;
2480         }
2481         req = nonemb_cmd->va;
2482
2483         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2484                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2485                         nonemb_cmd);
2486
2487         status = be_mcc_notify_wait(adapter);
2488
2489 err:
2490         spin_unlock_bh(&adapter->mcc_lock);
2491         return status;
2492 }
2493
2494 int be_cmd_get_phy_info(struct be_adapter *adapter)
2495 {
2496         struct be_mcc_wrb *wrb;
2497         struct be_cmd_req_get_phy_info *req;
2498         struct be_dma_mem cmd;
2499         int status;
2500
2501         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2502                             CMD_SUBSYSTEM_COMMON))
2503                 return -EPERM;
2504
2505         spin_lock_bh(&adapter->mcc_lock);
2506
2507         wrb = wrb_from_mccq(adapter);
2508         if (!wrb) {
2509                 status = -EBUSY;
2510                 goto err;
2511         }
2512         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2513         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2514                                         &cmd.dma);
2515         if (!cmd.va) {
2516                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2517                 status = -ENOMEM;
2518                 goto err;
2519         }
2520
2521         req = cmd.va;
2522
2523         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2524                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2525                         wrb, &cmd);
2526
2527         status = be_mcc_notify_wait(adapter);
2528         if (!status) {
2529                 struct be_phy_info *resp_phy_info =
2530                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2531                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2532                 adapter->phy.interface_type =
2533                         le16_to_cpu(resp_phy_info->interface_type);
2534                 adapter->phy.auto_speeds_supported =
2535                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2536                 adapter->phy.fixed_speeds_supported =
2537                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2538                 adapter->phy.misc_params =
2539                         le32_to_cpu(resp_phy_info->misc_params);
2540
2541                 if (BE2_chip(adapter)) {
2542                         adapter->phy.fixed_speeds_supported =
2543                                 BE_SUPPORTED_SPEED_10GBPS |
2544                                 BE_SUPPORTED_SPEED_1GBPS;
2545                 }
2546         }
2547         pci_free_consistent(adapter->pdev, cmd.size,
2548                                 cmd.va, cmd.dma);
2549 err:
2550         spin_unlock_bh(&adapter->mcc_lock);
2551         return status;
2552 }
2553
2554 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2555 {
2556         struct be_mcc_wrb *wrb;
2557         struct be_cmd_req_set_qos *req;
2558         int status;
2559
2560         spin_lock_bh(&adapter->mcc_lock);
2561
2562         wrb = wrb_from_mccq(adapter);
2563         if (!wrb) {
2564                 status = -EBUSY;
2565                 goto err;
2566         }
2567
2568         req = embedded_payload(wrb);
2569
2570         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2571                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2572
2573         req->hdr.domain = domain;
2574         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2575         req->max_bps_nic = cpu_to_le32(bps);
2576
2577         status = be_mcc_notify_wait(adapter);
2578
2579 err:
2580         spin_unlock_bh(&adapter->mcc_lock);
2581         return status;
2582 }
2583
2584 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2585 {
2586         struct be_mcc_wrb *wrb;
2587         struct be_cmd_req_cntl_attribs *req;
2588         struct be_cmd_resp_cntl_attribs *resp;
2589         int status;
2590         int payload_len = max(sizeof(*req), sizeof(*resp));
2591         struct mgmt_controller_attrib *attribs;
2592         struct be_dma_mem attribs_cmd;
2593
2594         if (mutex_lock_interruptible(&adapter->mbox_lock))
2595                 return -1;
2596
2597         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2598         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2599         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2600                                                 &attribs_cmd.dma);
2601         if (!attribs_cmd.va) {
2602                 dev_err(&adapter->pdev->dev,
2603                                 "Memory allocation failure\n");
2604                 status = -ENOMEM;
2605                 goto err;
2606         }
2607
2608         wrb = wrb_from_mbox(adapter);
2609         if (!wrb) {
2610                 status = -EBUSY;
2611                 goto err;
2612         }
2613         req = attribs_cmd.va;
2614
2615         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2616                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2617                         &attribs_cmd);
2618
2619         status = be_mbox_notify_wait(adapter);
2620         if (!status) {
2621                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2622                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2623         }
2624
2625 err:
2626         mutex_unlock(&adapter->mbox_lock);
2627         if (attribs_cmd.va)
2628                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2629                                     attribs_cmd.va, attribs_cmd.dma);
2630         return status;
2631 }
2632
2633 /* Uses mbox */
2634 int be_cmd_req_native_mode(struct be_adapter *adapter)
2635 {
2636         struct be_mcc_wrb *wrb;
2637         struct be_cmd_req_set_func_cap *req;
2638         int status;
2639
2640         if (mutex_lock_interruptible(&adapter->mbox_lock))
2641                 return -1;
2642
2643         wrb = wrb_from_mbox(adapter);
2644         if (!wrb) {
2645                 status = -EBUSY;
2646                 goto err;
2647         }
2648
2649         req = embedded_payload(wrb);
2650
2651         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2652                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2653
2654         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2655                                 CAPABILITY_BE3_NATIVE_ERX_API);
2656         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2657
2658         status = be_mbox_notify_wait(adapter);
2659         if (!status) {
2660                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2661                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2662                                         CAPABILITY_BE3_NATIVE_ERX_API;
2663                 if (!adapter->be3_native)
2664                         dev_warn(&adapter->pdev->dev,
2665                                  "adapter not in advanced mode\n");
2666         }
2667 err:
2668         mutex_unlock(&adapter->mbox_lock);
2669         return status;
2670 }
2671
2672 /* Get privilege(s) for a function */
2673 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2674                              u32 domain)
2675 {
2676         struct be_mcc_wrb *wrb;
2677         struct be_cmd_req_get_fn_privileges *req;
2678         int status;
2679
2680         spin_lock_bh(&adapter->mcc_lock);
2681
2682         wrb = wrb_from_mccq(adapter);
2683         if (!wrb) {
2684                 status = -EBUSY;
2685                 goto err;
2686         }
2687
2688         req = embedded_payload(wrb);
2689
2690         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2691                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2692                                wrb, NULL);
2693
2694         req->hdr.domain = domain;
2695
2696         status = be_mcc_notify_wait(adapter);
2697         if (!status) {
2698                 struct be_cmd_resp_get_fn_privileges *resp =
2699                                                 embedded_payload(wrb);
2700                 *privilege = le32_to_cpu(resp->privilege_mask);
2701
2702                 /* In UMC mode FW does not return right privileges.
2703                  * Override with correct privilege equivalent to PF.
2704                  */
2705                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2706                     be_physfn(adapter))
2707                         *privilege = MAX_PRIVILEGES;
2708         }
2709
2710 err:
2711         spin_unlock_bh(&adapter->mcc_lock);
2712         return status;
2713 }
2714
2715 /* Set privilege(s) for a function */
2716 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2717                              u32 domain)
2718 {
2719         struct be_mcc_wrb *wrb;
2720         struct be_cmd_req_set_fn_privileges *req;
2721         int status;
2722
2723         spin_lock_bh(&adapter->mcc_lock);
2724
2725         wrb = wrb_from_mccq(adapter);
2726         if (!wrb) {
2727                 status = -EBUSY;
2728                 goto err;
2729         }
2730
2731         req = embedded_payload(wrb);
2732         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2733                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2734                                wrb, NULL);
2735         req->hdr.domain = domain;
2736         if (lancer_chip(adapter))
2737                 req->privileges_lancer = cpu_to_le32(privileges);
2738         else
2739                 req->privileges = cpu_to_le32(privileges);
2740
2741         status = be_mcc_notify_wait(adapter);
2742 err:
2743         spin_unlock_bh(&adapter->mcc_lock);
2744         return status;
2745 }
2746
2747 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2748  * pmac_id_valid: false => pmac_id or MAC address is requested.
2749  *                If pmac_id is returned, pmac_id_valid is returned as true
2750  */
2751 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2752                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
2753                              u8 domain)
2754 {
2755         struct be_mcc_wrb *wrb;
2756         struct be_cmd_req_get_mac_list *req;
2757         int status;
2758         int mac_count;
2759         struct be_dma_mem get_mac_list_cmd;
2760         int i;
2761
2762         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2763         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2764         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2765                         get_mac_list_cmd.size,
2766                         &get_mac_list_cmd.dma);
2767
2768         if (!get_mac_list_cmd.va) {
2769                 dev_err(&adapter->pdev->dev,
2770                                 "Memory allocation failure during GET_MAC_LIST\n");
2771                 return -ENOMEM;
2772         }
2773
2774         spin_lock_bh(&adapter->mcc_lock);
2775
2776         wrb = wrb_from_mccq(adapter);
2777         if (!wrb) {
2778                 status = -EBUSY;
2779                 goto out;
2780         }
2781
2782         req = get_mac_list_cmd.va;
2783
2784         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2785                                OPCODE_COMMON_GET_MAC_LIST,
2786                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2787         req->hdr.domain = domain;
2788         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2789         if (*pmac_id_valid) {
2790                 req->mac_id = cpu_to_le32(*pmac_id);
2791                 req->iface_id = cpu_to_le16(if_handle);
2792                 req->perm_override = 0;
2793         } else {
2794                 req->perm_override = 1;
2795         }
2796
2797         status = be_mcc_notify_wait(adapter);
2798         if (!status) {
2799                 struct be_cmd_resp_get_mac_list *resp =
2800                                                 get_mac_list_cmd.va;
2801
2802                 if (*pmac_id_valid) {
2803                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2804                                ETH_ALEN);
2805                         goto out;
2806                 }
2807
2808                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2809                 /* Mac list returned could contain one or more active mac_ids
2810                  * or one or more true or pseudo permanant mac addresses.
2811                  * If an active mac_id is present, return first active mac_id
2812                  * found.
2813                  */
2814                 for (i = 0; i < mac_count; i++) {
2815                         struct get_list_macaddr *mac_entry;
2816                         u16 mac_addr_size;
2817                         u32 mac_id;
2818
2819                         mac_entry = &resp->macaddr_list[i];
2820                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2821                         /* mac_id is a 32 bit value and mac_addr size
2822                          * is 6 bytes
2823                          */
2824                         if (mac_addr_size == sizeof(u32)) {
2825                                 *pmac_id_valid = true;
2826                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2827                                 *pmac_id = le32_to_cpu(mac_id);
2828                                 goto out;
2829                         }
2830                 }
2831                 /* If no active mac_id found, return first mac addr */
2832                 *pmac_id_valid = false;
2833                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2834                                                                 ETH_ALEN);
2835         }
2836
2837 out:
2838         spin_unlock_bh(&adapter->mcc_lock);
2839         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2840                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2841         return status;
2842 }
2843
2844 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac,
2845                           u32 if_handle, bool active, u32 domain)
2846 {
2847
2848         if (!active)
2849                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
2850                                          if_handle, domain);
2851         if (BEx_chip(adapter))
2852                 return be_cmd_mac_addr_query(adapter, mac, false,
2853                                              if_handle, curr_pmac_id);
2854         else
2855                 /* Fetch the MAC address using pmac_id */
2856                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2857                                                 &curr_pmac_id,
2858                                                 if_handle, domain);
2859 }
2860
2861 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2862 {
2863         int status;
2864         bool pmac_valid = false;
2865
2866         memset(mac, 0, ETH_ALEN);
2867
2868         if (BEx_chip(adapter)) {
2869                 if (be_physfn(adapter))
2870                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2871                                                        0);
2872                 else
2873                         status = be_cmd_mac_addr_query(adapter, mac, false,
2874                                                        adapter->if_handle, 0);
2875         } else {
2876                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2877                                                   NULL, adapter->if_handle, 0);
2878         }
2879
2880         return status;
2881 }
2882
2883 /* Uses synchronous MCCQ */
2884 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2885                         u8 mac_count, u32 domain)
2886 {
2887         struct be_mcc_wrb *wrb;
2888         struct be_cmd_req_set_mac_list *req;
2889         int status;
2890         struct be_dma_mem cmd;
2891
2892         memset(&cmd, 0, sizeof(struct be_dma_mem));
2893         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2894         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2895                         &cmd.dma, GFP_KERNEL);
2896         if (!cmd.va)
2897                 return -ENOMEM;
2898
2899         spin_lock_bh(&adapter->mcc_lock);
2900
2901         wrb = wrb_from_mccq(adapter);
2902         if (!wrb) {
2903                 status = -EBUSY;
2904                 goto err;
2905         }
2906
2907         req = cmd.va;
2908         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2909                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2910                                 wrb, &cmd);
2911
2912         req->hdr.domain = domain;
2913         req->mac_count = mac_count;
2914         if (mac_count)
2915                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2916
2917         status = be_mcc_notify_wait(adapter);
2918
2919 err:
2920         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2921                                 cmd.va, cmd.dma);
2922         spin_unlock_bh(&adapter->mcc_lock);
2923         return status;
2924 }
2925
2926 /* Wrapper to delete any active MACs and provision the new mac.
2927  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2928  * current list are active.
2929  */
2930 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2931 {
2932         bool active_mac = false;
2933         u8 old_mac[ETH_ALEN];
2934         u32 pmac_id;
2935         int status;
2936
2937         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2938                                           &pmac_id, if_id, dom);
2939
2940         if (!status && active_mac)
2941                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2942
2943         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2944 }
2945
2946 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2947                           u32 domain, u16 intf_id, u16 hsw_mode)
2948 {
2949         struct be_mcc_wrb *wrb;
2950         struct be_cmd_req_set_hsw_config *req;
2951         void *ctxt;
2952         int status;
2953
2954         spin_lock_bh(&adapter->mcc_lock);
2955
2956         wrb = wrb_from_mccq(adapter);
2957         if (!wrb) {
2958                 status = -EBUSY;
2959                 goto err;
2960         }
2961
2962         req = embedded_payload(wrb);
2963         ctxt = &req->context;
2964
2965         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2966                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2967
2968         req->hdr.domain = domain;
2969         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2970         if (pvid) {
2971                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2972                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2973         }
2974         if (!BEx_chip(adapter) && hsw_mode) {
2975                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
2976                               ctxt, adapter->hba_port_num);
2977                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
2978                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
2979                               ctxt, hsw_mode);
2980         }
2981
2982         be_dws_cpu_to_le(req->context, sizeof(req->context));
2983         status = be_mcc_notify_wait(adapter);
2984
2985 err:
2986         spin_unlock_bh(&adapter->mcc_lock);
2987         return status;
2988 }
2989
2990 /* Get Hyper switch config */
2991 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2992                           u32 domain, u16 intf_id, u8 *mode)
2993 {
2994         struct be_mcc_wrb *wrb;
2995         struct be_cmd_req_get_hsw_config *req;
2996         void *ctxt;
2997         int status;
2998         u16 vid;
2999
3000         spin_lock_bh(&adapter->mcc_lock);
3001
3002         wrb = wrb_from_mccq(adapter);
3003         if (!wrb) {
3004                 status = -EBUSY;
3005                 goto err;
3006         }
3007
3008         req = embedded_payload(wrb);
3009         ctxt = &req->context;
3010
3011         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3012                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
3013
3014         req->hdr.domain = domain;
3015         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3016                       ctxt, intf_id);
3017         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3018
3019         if (!BEx_chip(adapter) && mode) {
3020                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3021                               ctxt, adapter->hba_port_num);
3022                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3023         }
3024         be_dws_cpu_to_le(req->context, sizeof(req->context));
3025
3026         status = be_mcc_notify_wait(adapter);
3027         if (!status) {
3028                 struct be_cmd_resp_get_hsw_config *resp =
3029                                                 embedded_payload(wrb);
3030                 be_dws_le_to_cpu(&resp->context,
3031                                                 sizeof(resp->context));
3032                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3033                                                         pvid, &resp->context);
3034                 if (pvid)
3035                         *pvid = le16_to_cpu(vid);
3036                 if (mode)
3037                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3038                                               port_fwd_type, &resp->context);
3039         }
3040
3041 err:
3042         spin_unlock_bh(&adapter->mcc_lock);
3043         return status;
3044 }
3045
3046 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3047 {
3048         struct be_mcc_wrb *wrb;
3049         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3050         int status = 0;
3051         struct be_dma_mem cmd;
3052
3053         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3054                             CMD_SUBSYSTEM_ETH))
3055                 return -EPERM;
3056
3057         if (be_is_wol_excluded(adapter))
3058                 return status;
3059
3060         if (mutex_lock_interruptible(&adapter->mbox_lock))
3061                 return -1;
3062
3063         memset(&cmd, 0, sizeof(struct be_dma_mem));
3064         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3065         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3066                                                &cmd.dma);
3067         if (!cmd.va) {
3068                 dev_err(&adapter->pdev->dev,
3069                                 "Memory allocation failure\n");
3070                 status = -ENOMEM;
3071                 goto err;
3072         }
3073
3074         wrb = wrb_from_mbox(adapter);
3075         if (!wrb) {
3076                 status = -EBUSY;
3077                 goto err;
3078         }
3079
3080         req = cmd.va;
3081
3082         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3083                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3084                                sizeof(*req), wrb, &cmd);
3085
3086         req->hdr.version = 1;
3087         req->query_options = BE_GET_WOL_CAP;
3088
3089         status = be_mbox_notify_wait(adapter);
3090         if (!status) {
3091                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3092                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
3093
3094                 adapter->wol_cap = resp->wol_settings;
3095                 if (adapter->wol_cap & BE_WOL_CAP)
3096                         adapter->wol_en = true;
3097         }
3098 err:
3099         mutex_unlock(&adapter->mbox_lock);
3100         if (cmd.va)
3101                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3102         return status;
3103
3104 }
3105
3106 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3107 {
3108         struct be_dma_mem extfat_cmd;
3109         struct be_fat_conf_params *cfgs;
3110         int status;
3111         int i, j;
3112
3113         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3114         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3115         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3116                                              &extfat_cmd.dma);
3117         if (!extfat_cmd.va)
3118                 return -ENOMEM;
3119
3120         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3121         if (status)
3122                 goto err;
3123
3124         cfgs = (struct be_fat_conf_params *)
3125                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3126         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3127                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3128                 for (j = 0; j < num_modes; j++) {
3129                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3130                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
3131                                                         cpu_to_le32(level);
3132                 }
3133         }
3134
3135         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3136 err:
3137         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3138                             extfat_cmd.dma);
3139         return status;
3140 }
3141
3142 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3143 {
3144         struct be_dma_mem extfat_cmd;
3145         struct be_fat_conf_params *cfgs;
3146         int status, j;
3147         int level = 0;
3148
3149         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3150         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3151         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3152                                              &extfat_cmd.dma);
3153
3154         if (!extfat_cmd.va) {
3155                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3156                         __func__);
3157                 goto err;
3158         }
3159
3160         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3161         if (!status) {
3162                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3163                                                 sizeof(struct be_cmd_resp_hdr));
3164                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3165                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3166                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3167                 }
3168         }
3169         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3170                             extfat_cmd.dma);
3171 err:
3172         return level;
3173 }
3174
3175 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3176                                    struct be_dma_mem *cmd)
3177 {
3178         struct be_mcc_wrb *wrb;
3179         struct be_cmd_req_get_ext_fat_caps *req;
3180         int status;
3181
3182         if (mutex_lock_interruptible(&adapter->mbox_lock))
3183                 return -1;
3184
3185         wrb = wrb_from_mbox(adapter);
3186         if (!wrb) {
3187                 status = -EBUSY;
3188                 goto err;
3189         }
3190
3191         req = cmd->va;
3192         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3193                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3194                                cmd->size, wrb, cmd);
3195         req->parameter_type = cpu_to_le32(1);
3196
3197         status = be_mbox_notify_wait(adapter);
3198 err:
3199         mutex_unlock(&adapter->mbox_lock);
3200         return status;
3201 }
3202
3203 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3204                                    struct be_dma_mem *cmd,
3205                                    struct be_fat_conf_params *configs)
3206 {
3207         struct be_mcc_wrb *wrb;
3208         struct be_cmd_req_set_ext_fat_caps *req;
3209         int status;
3210
3211         spin_lock_bh(&adapter->mcc_lock);
3212
3213         wrb = wrb_from_mccq(adapter);
3214         if (!wrb) {
3215                 status = -EBUSY;
3216                 goto err;
3217         }
3218
3219         req = cmd->va;
3220         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3221         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3222                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3223                                cmd->size, wrb, cmd);
3224
3225         status = be_mcc_notify_wait(adapter);
3226 err:
3227         spin_unlock_bh(&adapter->mcc_lock);
3228         return status;
3229 }
3230
3231 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3232 {
3233         struct be_mcc_wrb *wrb;
3234         struct be_cmd_req_get_port_name *req;
3235         int status;
3236
3237         if (!lancer_chip(adapter)) {
3238                 *port_name = adapter->hba_port_num + '0';
3239                 return 0;
3240         }
3241
3242         spin_lock_bh(&adapter->mcc_lock);
3243
3244         wrb = wrb_from_mccq(adapter);
3245         if (!wrb) {
3246                 status = -EBUSY;
3247                 goto err;
3248         }
3249
3250         req = embedded_payload(wrb);
3251
3252         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3253                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3254                                NULL);
3255         req->hdr.version = 1;
3256
3257         status = be_mcc_notify_wait(adapter);
3258         if (!status) {
3259                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3260                 *port_name = resp->port_name[adapter->hba_port_num];
3261         } else {
3262                 *port_name = adapter->hba_port_num + '0';
3263         }
3264 err:
3265         spin_unlock_bh(&adapter->mcc_lock);
3266         return status;
3267 }
3268
3269 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count)
3270 {
3271         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3272         int i;
3273
3274         for (i = 0; i < desc_count; i++) {
3275                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3276                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3277                         return (struct be_nic_res_desc *)hdr;
3278
3279                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3280                 hdr = (void *)hdr + hdr->desc_len;
3281         }
3282         return NULL;
3283 }
3284
3285 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3286                                                  u32 desc_count)
3287 {
3288         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3289         struct be_pcie_res_desc *pcie;
3290         int i;
3291
3292         for (i = 0; i < desc_count; i++) {
3293                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3294                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3295                         pcie = (struct be_pcie_res_desc *)hdr;
3296                         if (pcie->pf_num == devfn)
3297                                 return pcie;
3298                 }
3299
3300                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3301                 hdr = (void *)hdr + hdr->desc_len;
3302         }
3303         return NULL;
3304 }
3305
3306 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3307 {
3308         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3309         int i;
3310
3311         for (i = 0; i < desc_count; i++) {
3312                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3313                         return (struct be_port_res_desc *)hdr;
3314
3315                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3316                 hdr = (void *)hdr + hdr->desc_len;
3317         }
3318         return NULL;
3319 }
3320
3321 static void be_copy_nic_desc(struct be_resources *res,
3322                              struct be_nic_res_desc *desc)
3323 {
3324         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3325         res->max_vlans = le16_to_cpu(desc->vlan_count);
3326         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3327         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3328         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3329         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3330         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3331         /* Clear flags that driver is not interested in */
3332         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3333                                 BE_IF_CAP_FLAGS_WANT;
3334         /* Need 1 RXQ as the default RXQ */
3335         if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3336                 res->max_rss_qs -= 1;
3337 }
3338
3339 /* Uses Mbox */
3340 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3341 {
3342         struct be_mcc_wrb *wrb;
3343         struct be_cmd_req_get_func_config *req;
3344         int status;
3345         struct be_dma_mem cmd;
3346
3347         if (mutex_lock_interruptible(&adapter->mbox_lock))
3348                 return -1;
3349
3350         memset(&cmd, 0, sizeof(struct be_dma_mem));
3351         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3352         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3353                                       &cmd.dma);
3354         if (!cmd.va) {
3355                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3356                 status = -ENOMEM;
3357                 goto err;
3358         }
3359
3360         wrb = wrb_from_mbox(adapter);
3361         if (!wrb) {
3362                 status = -EBUSY;
3363                 goto err;
3364         }
3365
3366         req = cmd.va;
3367
3368         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3369                                OPCODE_COMMON_GET_FUNC_CONFIG,
3370                                cmd.size, wrb, &cmd);
3371
3372         if (skyhawk_chip(adapter))
3373                 req->hdr.version = 1;
3374
3375         status = be_mbox_notify_wait(adapter);
3376         if (!status) {
3377                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3378                 u32 desc_count = le32_to_cpu(resp->desc_count);
3379                 struct be_nic_res_desc *desc;
3380
3381                 desc = be_get_nic_desc(resp->func_param, desc_count);
3382                 if (!desc) {
3383                         status = -EINVAL;
3384                         goto err;
3385                 }
3386
3387                 adapter->pf_number = desc->pf_num;
3388                 be_copy_nic_desc(res, desc);
3389         }
3390 err:
3391         mutex_unlock(&adapter->mbox_lock);
3392         if (cmd.va)
3393                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3394         return status;
3395 }
3396
3397 /* Uses mbox */
3398 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3399                                         u8 domain, struct be_dma_mem *cmd)
3400 {
3401         struct be_mcc_wrb *wrb;
3402         struct be_cmd_req_get_profile_config *req;
3403         int status;
3404
3405         if (mutex_lock_interruptible(&adapter->mbox_lock))
3406                 return -1;
3407         wrb = wrb_from_mbox(adapter);
3408
3409         req = cmd->va;
3410         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3411                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3412                                cmd->size, wrb, cmd);
3413
3414         req->type = ACTIVE_PROFILE_TYPE;
3415         req->hdr.domain = domain;
3416         if (!lancer_chip(adapter))
3417                 req->hdr.version = 1;
3418
3419         status = be_mbox_notify_wait(adapter);
3420
3421         mutex_unlock(&adapter->mbox_lock);
3422         return status;
3423 }
3424
3425 /* Uses sync mcc */
3426 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3427                                         u8 domain, struct be_dma_mem *cmd)
3428 {
3429         struct be_mcc_wrb *wrb;
3430         struct be_cmd_req_get_profile_config *req;
3431         int status;
3432
3433         spin_lock_bh(&adapter->mcc_lock);
3434
3435         wrb = wrb_from_mccq(adapter);
3436         if (!wrb) {
3437                 status = -EBUSY;
3438                 goto err;
3439         }
3440
3441         req = cmd->va;
3442         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3443                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3444                                cmd->size, wrb, cmd);
3445
3446         req->type = ACTIVE_PROFILE_TYPE;
3447         req->hdr.domain = domain;
3448         if (!lancer_chip(adapter))
3449                 req->hdr.version = 1;
3450
3451         status = be_mcc_notify_wait(adapter);
3452
3453 err:
3454         spin_unlock_bh(&adapter->mcc_lock);
3455         return status;
3456 }
3457
3458 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3459 int be_cmd_get_profile_config(struct be_adapter *adapter,
3460                               struct be_resources *res, u8 domain)
3461 {
3462         struct be_cmd_resp_get_profile_config *resp;
3463         struct be_pcie_res_desc *pcie;
3464         struct be_port_res_desc *port;
3465         struct be_nic_res_desc *nic;
3466         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3467         struct be_dma_mem cmd;
3468         u32 desc_count;
3469         int status;
3470
3471         memset(&cmd, 0, sizeof(struct be_dma_mem));
3472         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3473         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3474         if (!cmd.va)
3475                 return -ENOMEM;
3476
3477         if (!mccq->created)
3478                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3479         else
3480                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3481         if (status)
3482                 goto err;
3483
3484         resp = cmd.va;
3485         desc_count = le32_to_cpu(resp->desc_count);
3486
3487         pcie =  be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3488                                  desc_count);
3489         if (pcie)
3490                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3491
3492         port = be_get_port_desc(resp->func_param, desc_count);
3493         if (port)
3494                 adapter->mc_type = port->mc_type;
3495
3496         nic = be_get_nic_desc(resp->func_param, desc_count);
3497         if (nic)
3498                 be_copy_nic_desc(res, nic);
3499
3500 err:
3501         if (cmd.va)
3502                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3503         return status;
3504 }
3505
3506 int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3507                               int size, u8 version, u8 domain)
3508 {
3509         struct be_cmd_req_set_profile_config *req;
3510         struct be_mcc_wrb *wrb;
3511         int status;
3512
3513         spin_lock_bh(&adapter->mcc_lock);
3514
3515         wrb = wrb_from_mccq(adapter);
3516         if (!wrb) {
3517                 status = -EBUSY;
3518                 goto err;
3519         }
3520
3521         req = embedded_payload(wrb);
3522         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3523                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3524                                wrb, NULL);
3525         req->hdr.version = version;
3526         req->hdr.domain = domain;
3527         req->desc_count = cpu_to_le32(1);
3528         memcpy(req->desc, desc, size);
3529
3530         status = be_mcc_notify_wait(adapter);
3531 err:
3532         spin_unlock_bh(&adapter->mcc_lock);
3533         return status;
3534 }
3535
3536 /* Mark all fields invalid */
3537 void be_reset_nic_desc(struct be_nic_res_desc *nic)
3538 {
3539         memset(nic, 0, sizeof(*nic));
3540         nic->unicast_mac_count = 0xFFFF;
3541         nic->mcc_count = 0xFFFF;
3542         nic->vlan_count = 0xFFFF;
3543         nic->mcast_mac_count = 0xFFFF;
3544         nic->txq_count = 0xFFFF;
3545         nic->rq_count = 0xFFFF;
3546         nic->rssq_count = 0xFFFF;
3547         nic->lro_count = 0xFFFF;
3548         nic->cq_count = 0xFFFF;
3549         nic->toe_conn_count = 0xFFFF;
3550         nic->eq_count = 0xFFFF;
3551         nic->link_param = 0xFF;
3552         nic->acpi_params = 0xFF;
3553         nic->wol_param = 0x0F;
3554         nic->bw_min = 0xFFFFFFFF;
3555         nic->bw_max = 0xFFFFFFFF;
3556 }
3557
3558 int be_cmd_config_qos(struct be_adapter *adapter, u32 bps, u8 domain)
3559 {
3560         if (lancer_chip(adapter)) {
3561                 struct be_nic_res_desc nic_desc;
3562
3563                 be_reset_nic_desc(&nic_desc);
3564                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3565                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3566                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3567                                         (1 << NOSV_SHIFT);
3568                 nic_desc.pf_num = adapter->pf_number;
3569                 nic_desc.vf_num = domain;
3570                 nic_desc.bw_max = cpu_to_le32(bps);
3571
3572                 return be_cmd_set_profile_config(adapter, &nic_desc,
3573                                                  RESOURCE_DESC_SIZE_V0,
3574                                                  0, domain);
3575         } else {
3576                 return be_cmd_set_qos(adapter, bps, domain);
3577         }
3578 }
3579
3580 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3581 {
3582         struct be_mcc_wrb *wrb;
3583         struct be_cmd_req_manage_iface_filters *req;
3584         int status;
3585
3586         if (iface == 0xFFFFFFFF)
3587                 return -1;
3588
3589         spin_lock_bh(&adapter->mcc_lock);
3590
3591         wrb = wrb_from_mccq(adapter);
3592         if (!wrb) {
3593                 status = -EBUSY;
3594                 goto err;
3595         }
3596         req = embedded_payload(wrb);
3597
3598         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3599                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3600                                wrb, NULL);
3601         req->op = op;
3602         req->target_iface_id = cpu_to_le32(iface);
3603
3604         status = be_mcc_notify_wait(adapter);
3605 err:
3606         spin_unlock_bh(&adapter->mcc_lock);
3607         return status;
3608 }
3609
3610 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3611 {
3612         struct be_port_res_desc port_desc;
3613
3614         memset(&port_desc, 0, sizeof(port_desc));
3615         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3616         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3617         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3618         port_desc.link_num = adapter->hba_port_num;
3619         if (port) {
3620                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3621                                         (1 << RCVID_SHIFT);
3622                 port_desc.nv_port = swab16(port);
3623         } else {
3624                 port_desc.nv_flags = NV_TYPE_DISABLED;
3625                 port_desc.nv_port = 0;
3626         }
3627
3628         return be_cmd_set_profile_config(adapter, &port_desc,
3629                                          RESOURCE_DESC_SIZE_V1, 1, 0);
3630 }
3631
3632 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3633                      int vf_num)
3634 {
3635         struct be_mcc_wrb *wrb;
3636         struct be_cmd_req_get_iface_list *req;
3637         struct be_cmd_resp_get_iface_list *resp;
3638         int status;
3639
3640         spin_lock_bh(&adapter->mcc_lock);
3641
3642         wrb = wrb_from_mccq(adapter);
3643         if (!wrb) {
3644                 status = -EBUSY;
3645                 goto err;
3646         }
3647         req = embedded_payload(wrb);
3648
3649         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3650                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3651                                wrb, NULL);
3652         req->hdr.domain = vf_num + 1;
3653
3654         status = be_mcc_notify_wait(adapter);
3655         if (!status) {
3656                 resp = (struct be_cmd_resp_get_iface_list *)req;
3657                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3658         }
3659
3660 err:
3661         spin_unlock_bh(&adapter->mcc_lock);
3662         return status;
3663 }
3664
3665 static int lancer_wait_idle(struct be_adapter *adapter)
3666 {
3667 #define SLIPORT_IDLE_TIMEOUT 30
3668         u32 reg_val;
3669         int status = 0, i;
3670
3671         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3672                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3673                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3674                         break;
3675
3676                 ssleep(1);
3677         }
3678
3679         if (i == SLIPORT_IDLE_TIMEOUT)
3680                 status = -1;
3681
3682         return status;
3683 }
3684
3685 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3686 {
3687         int status = 0;
3688
3689         status = lancer_wait_idle(adapter);
3690         if (status)
3691                 return status;
3692
3693         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3694
3695         return status;
3696 }
3697
3698 /* Routine to check whether dump image is present or not */
3699 bool dump_present(struct be_adapter *adapter)
3700 {
3701         u32 sliport_status = 0;
3702
3703         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3704         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3705 }
3706
3707 int lancer_initiate_dump(struct be_adapter *adapter)
3708 {
3709         int status;
3710
3711         /* give firmware reset and diagnostic dump */
3712         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3713                                      PHYSDEV_CONTROL_DD_MASK);
3714         if (status < 0) {
3715                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3716                 return status;
3717         }
3718
3719         status = lancer_wait_idle(adapter);
3720         if (status)
3721                 return status;
3722
3723         if (!dump_present(adapter)) {
3724                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3725                 return -1;
3726         }
3727
3728         return 0;
3729 }
3730
3731 /* Uses sync mcc */
3732 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3733 {
3734         struct be_mcc_wrb *wrb;
3735         struct be_cmd_enable_disable_vf *req;
3736         int status;
3737
3738         if (BEx_chip(adapter))
3739                 return 0;
3740
3741         spin_lock_bh(&adapter->mcc_lock);
3742
3743         wrb = wrb_from_mccq(adapter);
3744         if (!wrb) {
3745                 status = -EBUSY;
3746                 goto err;
3747         }
3748
3749         req = embedded_payload(wrb);
3750
3751         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3752                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3753                                wrb, NULL);
3754
3755         req->hdr.domain = domain;
3756         req->enable = 1;
3757         status = be_mcc_notify_wait(adapter);
3758 err:
3759         spin_unlock_bh(&adapter->mcc_lock);
3760         return status;
3761 }
3762
3763 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3764 {
3765         struct be_mcc_wrb *wrb;
3766         struct be_cmd_req_intr_set *req;
3767         int status;
3768
3769         if (mutex_lock_interruptible(&adapter->mbox_lock))
3770                 return -1;
3771
3772         wrb = wrb_from_mbox(adapter);
3773
3774         req = embedded_payload(wrb);
3775
3776         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3777                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3778                                wrb, NULL);
3779
3780         req->intr_enabled = intr_enable;
3781
3782         status = be_mbox_notify_wait(adapter);
3783
3784         mutex_unlock(&adapter->mbox_lock);
3785         return status;
3786 }
3787
3788 /* Uses MBOX */
3789 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
3790 {
3791         struct be_cmd_req_get_active_profile *req;
3792         struct be_mcc_wrb *wrb;
3793         int status;
3794
3795         if (mutex_lock_interruptible(&adapter->mbox_lock))
3796                 return -1;
3797
3798         wrb = wrb_from_mbox(adapter);
3799         if (!wrb) {
3800                 status = -EBUSY;
3801                 goto err;
3802         }
3803
3804         req = embedded_payload(wrb);
3805
3806         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3807                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
3808                                wrb, NULL);
3809
3810         status = be_mbox_notify_wait(adapter);
3811         if (!status) {
3812                 struct be_cmd_resp_get_active_profile *resp =
3813                                                         embedded_payload(wrb);
3814                 *profile_id = le16_to_cpu(resp->active_profile_id);
3815         }
3816
3817 err:
3818         mutex_unlock(&adapter->mbox_lock);
3819         return status;
3820 }
3821
3822 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
3823                                    int link_state, u8 domain)
3824 {
3825         struct be_mcc_wrb *wrb;
3826         struct be_cmd_req_set_ll_link *req;
3827         int status;
3828
3829         if (BEx_chip(adapter) || lancer_chip(adapter))
3830                 return 0;
3831
3832         spin_lock_bh(&adapter->mcc_lock);
3833
3834         wrb = wrb_from_mccq(adapter);
3835         if (!wrb) {
3836                 status = -EBUSY;
3837                 goto err;
3838         }
3839
3840         req = embedded_payload(wrb);
3841
3842         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3843                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
3844                                sizeof(*req), wrb, NULL);
3845
3846         req->hdr.version = 1;
3847         req->hdr.domain = domain;
3848
3849         if (link_state == IFLA_VF_LINK_STATE_ENABLE)
3850                 req->link_config |= 1;
3851
3852         if (link_state == IFLA_VF_LINK_STATE_AUTO)
3853                 req->link_config |= 1 << PLINK_TRACK_SHIFT;
3854
3855         status = be_mcc_notify_wait(adapter);
3856 err:
3857         spin_unlock_bh(&adapter->mcc_lock);
3858         return status;
3859 }
3860
3861 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3862                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3863 {
3864         struct be_adapter *adapter = netdev_priv(netdev_handle);
3865         struct be_mcc_wrb *wrb;
3866         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3867         struct be_cmd_req_hdr *req;
3868         struct be_cmd_resp_hdr *resp;
3869         int status;
3870
3871         spin_lock_bh(&adapter->mcc_lock);
3872
3873         wrb = wrb_from_mccq(adapter);
3874         if (!wrb) {
3875                 status = -EBUSY;
3876                 goto err;
3877         }
3878         req = embedded_payload(wrb);
3879         resp = embedded_payload(wrb);
3880
3881         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3882                                hdr->opcode, wrb_payload_size, wrb, NULL);
3883         memcpy(req, wrb_payload, wrb_payload_size);
3884         be_dws_cpu_to_le(req, wrb_payload_size);
3885
3886         status = be_mcc_notify_wait(adapter);
3887         if (cmd_status)
3888                 *cmd_status = (status & 0xffff);
3889         if (ext_status)
3890                 *ext_status = 0;
3891         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3892         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3893 err:
3894         spin_unlock_bh(&adapter->mcc_lock);
3895         return status;
3896 }
3897 EXPORT_SYMBOL(be_roce_mcc_cmd);