2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 /* Arbitrary values, I am not sure the HW has limits */
44 #define MAX_RX_QUEUE_ENTRIES 1024
45 #define MAX_TX_QUEUE_ENTRIES 1024
46 #define MIN_RX_QUEUE_ENTRIES 32
47 #define MIN_TX_QUEUE_ENTRIES 32
50 #define DEF_RX_QUEUE_ENTRIES 128
51 #define DEF_TX_QUEUE_ENTRIES 128
53 #define MAX_PKT_SIZE 1536
54 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
56 /* Min number of tx ring entries before stopping queue */
57 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
65 unsigned int rx_q_entries;
66 struct ftgmac100_rxdes *rxdes;
68 struct sk_buff **rx_skbs;
69 unsigned int rx_pointer;
70 u32 rxdes0_edorr_mask;
73 unsigned int tx_q_entries;
74 struct ftgmac100_txdes *txdes;
76 struct sk_buff **tx_skbs;
77 unsigned int tx_clean_pointer;
78 unsigned int tx_pointer;
79 u32 txdes0_edotr_mask;
81 /* Used to signal the reset task of ring change request */
82 unsigned int new_rx_q_entries;
83 unsigned int new_tx_q_entries;
85 /* Scratch page to use when rx skb alloc fails */
87 dma_addr_t rx_scratch_dma;
89 /* Component structures */
90 struct net_device *netdev;
92 struct ncsi_dev *ndev;
93 struct napi_struct napi;
94 struct work_struct reset_task;
95 struct mii_bus *mii_bus;
103 bool need_mac_restart;
107 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
109 struct net_device *netdev = priv->netdev;
112 /* NOTE: reset clears all registers */
113 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
114 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
115 priv->base + FTGMAC100_OFFSET_MACCR);
116 for (i = 0; i < 50; i++) {
119 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
120 if (!(maccr & FTGMAC100_MACCR_SW_RST))
126 netdev_err(netdev, "Hardware reset failed\n");
130 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
134 switch (priv->cur_speed) {
136 case 0: /* no link */
140 maccr |= FTGMAC100_MACCR_FAST_MODE;
144 maccr |= FTGMAC100_MACCR_GIGA_MODE;
147 netdev_err(priv->netdev, "Unknown speed %d !\n",
152 /* (Re)initialize the queue pointers */
153 priv->rx_pointer = 0;
154 priv->tx_clean_pointer = 0;
155 priv->tx_pointer = 0;
157 /* The doc says reset twice with 10us interval */
158 if (ftgmac100_reset_mac(priv, maccr))
160 usleep_range(10, 1000);
161 return ftgmac100_reset_mac(priv, maccr);
164 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
166 unsigned int maddr = mac[0] << 8 | mac[1];
167 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
169 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
170 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
173 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
180 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
182 ether_addr_copy(priv->netdev->dev_addr, mac);
183 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
188 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
189 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
191 mac[0] = (m >> 8) & 0xff;
193 mac[2] = (l >> 24) & 0xff;
194 mac[3] = (l >> 16) & 0xff;
195 mac[4] = (l >> 8) & 0xff;
198 if (is_valid_ether_addr(mac)) {
199 ether_addr_copy(priv->netdev->dev_addr, mac);
200 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
202 eth_hw_addr_random(priv->netdev);
203 dev_info(priv->dev, "Generated random MAC address %pM\n",
204 priv->netdev->dev_addr);
208 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
212 ret = eth_prepare_mac_addr_change(dev, p);
216 eth_commit_mac_addr_change(dev, p);
217 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
222 static void ftgmac100_init_hw(struct ftgmac100 *priv)
224 u32 reg, rfifo_sz, tfifo_sz;
226 /* Clear stale interrupts */
227 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
228 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
230 /* Setup RX ring buffer base */
231 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
233 /* Setup TX ring buffer base */
234 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
236 /* Configure RX buffer size */
237 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
238 priv->base + FTGMAC100_OFFSET_RBSR);
240 /* Set RX descriptor autopoll */
241 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
242 priv->base + FTGMAC100_OFFSET_APTC);
244 /* Write MAC address */
245 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
247 /* Configure descriptor sizes and increase burst sizes according
248 * to values in Aspeed SDK. The FIFO arbitration is enabled and
249 * the thresholds set based on the recommended values in the
250 * AST2400 specification.
252 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
253 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
254 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
255 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
256 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
257 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
258 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
259 priv->base + FTGMAC100_OFFSET_DBLAC);
261 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
262 * mitigation doesn't seem to provide any benefit with NAPI so leave
265 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
266 FTGMAC100_ITC_TXINT_THR(1),
267 priv->base + FTGMAC100_OFFSET_ITC);
269 /* Configure FIFO sizes in the TPAFCR register */
270 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
271 rfifo_sz = reg & 0x00000007;
272 tfifo_sz = (reg >> 3) & 0x00000007;
273 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
275 reg |= (tfifo_sz << 27);
276 reg |= (rfifo_sz << 24);
277 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
280 static void ftgmac100_start_hw(struct ftgmac100 *priv)
282 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
284 /* Keep the original GMAC and FAST bits */
285 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
287 /* Add all the main enable bits */
288 maccr |= FTGMAC100_MACCR_TXDMA_EN |
289 FTGMAC100_MACCR_RXDMA_EN |
290 FTGMAC100_MACCR_TXMAC_EN |
291 FTGMAC100_MACCR_RXMAC_EN |
292 FTGMAC100_MACCR_CRC_APD |
293 FTGMAC100_MACCR_PHY_LINK_LEVEL |
294 FTGMAC100_MACCR_RX_RUNT |
295 FTGMAC100_MACCR_RX_BROADPKT;
297 /* Add other bits as needed */
298 if (priv->cur_duplex == DUPLEX_FULL)
299 maccr |= FTGMAC100_MACCR_FULLDUP;
302 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
305 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
307 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
310 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
311 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
313 struct net_device *netdev = priv->netdev;
318 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
319 if (unlikely(!skb)) {
321 netdev_warn(netdev, "failed to allocate rx skb\n");
323 map = priv->rx_scratch_dma;
325 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
327 if (unlikely(dma_mapping_error(priv->dev, map))) {
329 netdev_err(netdev, "failed to map rx page\n");
330 dev_kfree_skb_any(skb);
331 map = priv->rx_scratch_dma;
338 priv->rx_skbs[entry] = skb;
340 /* Store DMA address into RX desc */
341 rxdes->rxdes3 = cpu_to_le32(map);
343 /* Ensure the above is ordered vs clearing the OWN bit */
346 /* Clean status (which resets own bit) */
347 if (entry == (priv->rx_q_entries - 1))
348 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
355 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
356 unsigned int pointer)
358 return (pointer + 1) & (priv->rx_q_entries - 1);
361 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
363 struct net_device *netdev = priv->netdev;
365 if (status & FTGMAC100_RXDES0_RX_ERR)
366 netdev->stats.rx_errors++;
368 if (status & FTGMAC100_RXDES0_CRC_ERR)
369 netdev->stats.rx_crc_errors++;
371 if (status & (FTGMAC100_RXDES0_FTL |
372 FTGMAC100_RXDES0_RUNT |
373 FTGMAC100_RXDES0_RX_ODD_NB))
374 netdev->stats.rx_length_errors++;
377 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
379 struct net_device *netdev = priv->netdev;
380 struct ftgmac100_rxdes *rxdes;
382 unsigned int pointer, size;
383 u32 status, csum_vlan;
386 /* Grab next RX descriptor */
387 pointer = priv->rx_pointer;
388 rxdes = &priv->rxdes[pointer];
390 /* Grab descriptor status */
391 status = le32_to_cpu(rxdes->rxdes0);
393 /* Do we have a packet ? */
394 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
397 /* Order subsequent reads with the test for the ready bit */
400 /* We don't cope with fragmented RX packets */
401 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
402 !(status & FTGMAC100_RXDES0_LRS)))
405 /* Grab received size and csum vlan field in the descriptor */
406 size = status & FTGMAC100_RXDES0_VDBC;
407 csum_vlan = le32_to_cpu(rxdes->rxdes1);
409 /* Any error (other than csum offload) flagged ? */
410 if (unlikely(status & RXDES0_ANY_ERROR)) {
411 /* Correct for incorrect flagging of runt packets
412 * with vlan tags... Just accept a runt packet that
413 * has been flagged as vlan and whose size is at
416 if ((status & FTGMAC100_RXDES0_RUNT) &&
417 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
419 status &= ~FTGMAC100_RXDES0_RUNT;
421 /* Any error still in there ? */
422 if (status & RXDES0_ANY_ERROR) {
423 ftgmac100_rx_packet_error(priv, status);
428 /* If the packet had no skb (failed to allocate earlier)
429 * then try to allocate one and skip
431 skb = priv->rx_skbs[pointer];
432 if (!unlikely(skb)) {
433 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
437 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
438 netdev->stats.multicast++;
440 /* If the HW found checksum errors, bounce it to software.
442 * If we didn't, we need to see if the packet was recognized
443 * by HW as one of the supported checksummed protocols before
444 * we accept the HW test results.
446 if (netdev->features & NETIF_F_RXCSUM) {
447 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
448 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
449 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
450 if ((csum_vlan & err_bits) ||
451 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
452 skb->ip_summed = CHECKSUM_NONE;
454 skb->ip_summed = CHECKSUM_UNNECESSARY;
457 /* Transfer received size to skb */
460 /* Tear down DMA mapping, do necessary cache management */
461 map = le32_to_cpu(rxdes->rxdes3);
463 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
464 /* When we don't have an iommu, we can save cycles by not
465 * invalidating the cache for the part of the packet that
468 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
470 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
474 /* Resplenish rx ring */
475 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
476 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
478 skb->protocol = eth_type_trans(skb, netdev);
480 netdev->stats.rx_packets++;
481 netdev->stats.rx_bytes += size;
483 /* push packet to protocol stack */
484 if (skb->ip_summed == CHECKSUM_NONE)
485 netif_receive_skb(skb);
487 napi_gro_receive(&priv->napi, skb);
493 /* Clean rxdes0 (which resets own bit) */
494 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
495 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
496 netdev->stats.rx_dropped++;
500 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
503 if (index == (priv->tx_q_entries - 1))
504 return priv->txdes0_edotr_mask;
509 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
510 unsigned int pointer)
512 return (pointer + 1) & (priv->tx_q_entries - 1);
515 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
517 /* Returns the number of available slots in the TX queue
519 * This always leaves one free slot so we don't have to
520 * worry about empty vs. full, and this simplifies the
521 * test for ftgmac100_tx_buf_cleanable() below
523 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
524 (priv->tx_q_entries - 1);
527 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
529 return priv->tx_pointer != priv->tx_clean_pointer;
532 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
533 unsigned int pointer,
535 struct ftgmac100_txdes *txdes,
538 dma_addr_t map = le32_to_cpu(txdes->txdes3);
541 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
542 len = skb_headlen(skb);
543 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
545 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
546 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
549 /* Free SKB on last segment */
550 if (ctl_stat & FTGMAC100_TXDES0_LTS)
552 priv->tx_skbs[pointer] = NULL;
555 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
557 struct net_device *netdev = priv->netdev;
558 struct ftgmac100_txdes *txdes;
560 unsigned int pointer;
563 pointer = priv->tx_clean_pointer;
564 txdes = &priv->txdes[pointer];
566 ctl_stat = le32_to_cpu(txdes->txdes0);
567 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
570 skb = priv->tx_skbs[pointer];
571 netdev->stats.tx_packets++;
572 netdev->stats.tx_bytes += skb->len;
573 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
574 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
576 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
581 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
583 struct net_device *netdev = priv->netdev;
585 /* Process all completed packets */
586 while (ftgmac100_tx_buf_cleanable(priv) &&
587 ftgmac100_tx_complete_packet(priv))
590 /* Restart queue if needed */
592 if (unlikely(netif_queue_stopped(netdev) &&
593 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
594 struct netdev_queue *txq;
596 txq = netdev_get_tx_queue(netdev, 0);
597 __netif_tx_lock(txq, smp_processor_id());
598 if (netif_queue_stopped(netdev) &&
599 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
600 netif_wake_queue(netdev);
601 __netif_tx_unlock(txq);
605 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
607 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
608 u8 ip_proto = ip_hdr(skb)->protocol;
610 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
613 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
616 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
622 return skb_checksum_help(skb) == 0;
625 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
626 struct net_device *netdev)
628 struct ftgmac100 *priv = netdev_priv(netdev);
629 struct ftgmac100_txdes *txdes, *first;
630 unsigned int pointer, nfrags, len, i, j;
631 u32 f_ctl_stat, ctl_stat, csum_vlan;
634 /* The HW doesn't pad small frames */
635 if (eth_skb_pad(skb)) {
636 netdev->stats.tx_dropped++;
640 /* Reject oversize packets */
641 if (unlikely(skb->len > MAX_PKT_SIZE)) {
643 netdev_dbg(netdev, "tx packet too big\n");
647 /* Do we have a limit on #fragments ? I yet have to get a reply
648 * from Aspeed. If there's one I haven't hit it.
650 nfrags = skb_shinfo(skb)->nr_frags;
653 len = skb_headlen(skb);
655 /* Map the packet head */
656 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
657 if (dma_mapping_error(priv->dev, map)) {
659 netdev_err(netdev, "map tx packet head failed\n");
663 /* Grab the next free tx descriptor */
664 pointer = priv->tx_pointer;
665 txdes = first = &priv->txdes[pointer];
667 /* Setup it up with the packet head. Don't write the head to the
670 priv->tx_skbs[pointer] = skb;
671 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
672 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
673 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
674 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
676 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
677 txdes->txdes3 = cpu_to_le32(map);
679 /* Setup HW checksumming */
681 if (skb->ip_summed == CHECKSUM_PARTIAL &&
682 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
684 txdes->txdes1 = cpu_to_le32(csum_vlan);
686 /* Next descriptor */
687 pointer = ftgmac100_next_tx_pointer(priv, pointer);
689 /* Add the fragments */
690 for (i = 0; i < nfrags; i++) {
691 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
696 map = skb_frag_dma_map(priv->dev, frag, 0, len,
698 if (dma_mapping_error(priv->dev, map))
701 /* Setup descriptor */
702 priv->tx_skbs[pointer] = skb;
703 txdes = &priv->txdes[pointer];
704 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
705 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
706 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
707 if (i == (nfrags - 1))
708 ctl_stat |= FTGMAC100_TXDES0_LTS;
709 txdes->txdes0 = cpu_to_le32(ctl_stat);
711 txdes->txdes3 = cpu_to_le32(map);
714 pointer = ftgmac100_next_tx_pointer(priv, pointer);
717 /* Order the previous packet and descriptor udpates
718 * before setting the OWN bit on the first descriptor.
721 first->txdes0 = cpu_to_le32(f_ctl_stat);
723 /* Update next TX pointer */
724 priv->tx_pointer = pointer;
726 /* If there isn't enough room for all the fragments of a new packet
727 * in the TX ring, stop the queue. The sequence below is race free
728 * vs. a concurrent restart in ftgmac100_poll()
730 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
731 netif_stop_queue(netdev);
732 /* Order the queue stop with the test below */
734 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
735 netif_wake_queue(netdev);
738 /* Poke transmitter to read the updated TX descriptors */
739 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
745 netdev_err(netdev, "map tx fragment failed\n");
748 pointer = priv->tx_pointer;
749 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
750 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
752 /* Then all fragments */
753 for (j = 0; j < i; j++) {
754 pointer = ftgmac100_next_tx_pointer(priv, pointer);
755 txdes = &priv->txdes[pointer];
756 ctl_stat = le32_to_cpu(txdes->txdes0);
757 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
758 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
761 /* This cannot be reached if we successfully mapped the
762 * last fragment, so we know ftgmac100_free_tx_packet()
763 * hasn't freed the skb yet.
766 /* Drop the packet */
767 dev_kfree_skb_any(skb);
768 netdev->stats.tx_dropped++;
773 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
777 /* Free all RX buffers */
778 for (i = 0; i < priv->rx_q_entries; i++) {
779 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
780 struct sk_buff *skb = priv->rx_skbs[i];
781 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
786 priv->rx_skbs[i] = NULL;
787 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
788 dev_kfree_skb_any(skb);
791 /* Free all TX buffers */
792 for (i = 0; i < priv->tx_q_entries; i++) {
793 struct ftgmac100_txdes *txdes = &priv->txdes[i];
794 struct sk_buff *skb = priv->tx_skbs[i];
798 ftgmac100_free_tx_packet(priv, i, skb, txdes,
799 le32_to_cpu(txdes->txdes0));
803 static void ftgmac100_free_rings(struct ftgmac100 *priv)
805 /* Free skb arrays */
806 kfree(priv->rx_skbs);
807 kfree(priv->tx_skbs);
809 /* Free descriptors */
811 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
812 sizeof(struct ftgmac100_rxdes),
813 priv->rxdes, priv->rxdes_dma);
817 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
818 sizeof(struct ftgmac100_txdes),
819 priv->txdes, priv->txdes_dma);
822 /* Free scratch packet buffer */
823 if (priv->rx_scratch)
824 dma_free_coherent(priv->dev, RX_BUF_SIZE,
825 priv->rx_scratch, priv->rx_scratch_dma);
828 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
830 /* Allocate skb arrays */
831 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
835 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
840 /* Allocate descriptors */
841 priv->rxdes = dma_zalloc_coherent(priv->dev,
842 MAX_RX_QUEUE_ENTRIES *
843 sizeof(struct ftgmac100_rxdes),
844 &priv->rxdes_dma, GFP_KERNEL);
847 priv->txdes = dma_zalloc_coherent(priv->dev,
848 MAX_TX_QUEUE_ENTRIES *
849 sizeof(struct ftgmac100_txdes),
850 &priv->txdes_dma, GFP_KERNEL);
854 /* Allocate scratch packet buffer */
855 priv->rx_scratch = dma_alloc_coherent(priv->dev,
857 &priv->rx_scratch_dma,
859 if (!priv->rx_scratch)
865 static void ftgmac100_init_rings(struct ftgmac100 *priv)
867 struct ftgmac100_rxdes *rxdes = NULL;
868 struct ftgmac100_txdes *txdes = NULL;
871 /* Update entries counts */
872 priv->rx_q_entries = priv->new_rx_q_entries;
873 priv->tx_q_entries = priv->new_tx_q_entries;
875 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
878 /* Initialize RX ring */
879 for (i = 0; i < priv->rx_q_entries; i++) {
880 rxdes = &priv->rxdes[i];
882 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
884 /* Mark the end of the ring */
885 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
887 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
890 /* Initialize TX ring */
891 for (i = 0; i < priv->tx_q_entries; i++) {
892 txdes = &priv->txdes[i];
895 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
898 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
902 for (i = 0; i < priv->rx_q_entries; i++) {
903 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
905 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
911 static void ftgmac100_adjust_link(struct net_device *netdev)
913 struct ftgmac100 *priv = netdev_priv(netdev);
914 struct phy_device *phydev = netdev->phydev;
917 /* We store "no link" as speed 0 */
921 new_speed = phydev->speed;
923 if (phydev->speed == priv->cur_speed &&
924 phydev->duplex == priv->cur_duplex)
927 /* Print status if we have a link or we had one and just lost it,
928 * don't print otherwise.
930 if (new_speed || priv->cur_speed)
931 phy_print_status(phydev);
933 priv->cur_speed = new_speed;
934 priv->cur_duplex = phydev->duplex;
936 /* Link is down, do nothing else */
940 /* Disable all interrupts */
941 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
943 /* Reset the adapter asynchronously */
944 schedule_work(&priv->reset_task);
947 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
949 struct net_device *netdev = priv->netdev;
950 struct phy_device *phydev;
952 phydev = phy_find_first(priv->mii_bus);
954 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
958 phydev = phy_connect(netdev, phydev_name(phydev),
959 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
961 if (IS_ERR(phydev)) {
962 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
963 return PTR_ERR(phydev);
969 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
971 struct net_device *netdev = bus->priv;
972 struct ftgmac100 *priv = netdev_priv(netdev);
976 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
978 /* preserve MDC cycle threshold */
979 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
981 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
982 FTGMAC100_PHYCR_REGAD(regnum) |
983 FTGMAC100_PHYCR_MIIRD;
985 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
987 for (i = 0; i < 10; i++) {
988 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
990 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
993 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
994 return FTGMAC100_PHYDATA_MIIRDATA(data);
1000 netdev_err(netdev, "mdio read timed out\n");
1004 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1005 int regnum, u16 value)
1007 struct net_device *netdev = bus->priv;
1008 struct ftgmac100 *priv = netdev_priv(netdev);
1013 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1015 /* preserve MDC cycle threshold */
1016 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1018 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1019 FTGMAC100_PHYCR_REGAD(regnum) |
1020 FTGMAC100_PHYCR_MIIWR;
1022 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1024 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1025 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1027 for (i = 0; i < 10; i++) {
1028 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1030 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1036 netdev_err(netdev, "mdio write timed out\n");
1040 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1041 struct ethtool_drvinfo *info)
1043 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1044 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1045 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1048 static void ftgmac100_get_ringparam(struct net_device *netdev,
1049 struct ethtool_ringparam *ering)
1051 struct ftgmac100 *priv = netdev_priv(netdev);
1053 memset(ering, 0, sizeof(*ering));
1054 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1055 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1056 ering->rx_pending = priv->rx_q_entries;
1057 ering->tx_pending = priv->tx_q_entries;
1060 static int ftgmac100_set_ringparam(struct net_device *netdev,
1061 struct ethtool_ringparam *ering)
1063 struct ftgmac100 *priv = netdev_priv(netdev);
1065 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1066 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1067 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1068 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1069 !is_power_of_2(ering->rx_pending) ||
1070 !is_power_of_2(ering->tx_pending))
1073 priv->new_rx_q_entries = ering->rx_pending;
1074 priv->new_tx_q_entries = ering->tx_pending;
1075 if (netif_running(netdev))
1076 schedule_work(&priv->reset_task);
1081 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1082 .get_drvinfo = ftgmac100_get_drvinfo,
1083 .get_link = ethtool_op_get_link,
1084 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1085 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1086 .nway_reset = phy_ethtool_nway_reset,
1087 .get_ringparam = ftgmac100_get_ringparam,
1088 .set_ringparam = ftgmac100_set_ringparam,
1091 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1093 struct net_device *netdev = dev_id;
1094 struct ftgmac100 *priv = netdev_priv(netdev);
1095 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1097 /* Fetch and clear interrupt bits, process abnormal ones */
1098 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1099 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1100 if (unlikely(status & FTGMAC100_INT_BAD)) {
1102 /* RX buffer unavailable */
1103 if (status & FTGMAC100_INT_NO_RXBUF)
1104 netdev->stats.rx_over_errors++;
1106 /* received packet lost due to RX FIFO full */
1107 if (status & FTGMAC100_INT_RPKT_LOST)
1108 netdev->stats.rx_fifo_errors++;
1110 /* sent packet lost due to excessive TX collision */
1111 if (status & FTGMAC100_INT_XPKT_LOST)
1112 netdev->stats.tx_fifo_errors++;
1114 /* AHB error -> Reset the chip */
1115 if (status & FTGMAC100_INT_AHB_ERR) {
1116 if (net_ratelimit())
1118 "AHB bus error ! Resetting chip.\n");
1119 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1120 schedule_work(&priv->reset_task);
1124 /* We may need to restart the MAC after such errors, delay
1125 * this until after we have freed some Rx buffers though
1127 priv->need_mac_restart = true;
1129 /* Disable those errors until we restart */
1130 new_mask &= ~status;
1133 /* Only enable "bad" interrupts while NAPI is on */
1134 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1136 /* Schedule NAPI bh */
1137 napi_schedule_irqoff(&priv->napi);
1142 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1144 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1146 /* Do we have a packet ? */
1147 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1150 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1152 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1156 /* Handle TX completions */
1157 if (ftgmac100_tx_buf_cleanable(priv))
1158 ftgmac100_tx_complete(priv);
1160 /* Handle RX packets */
1162 more = ftgmac100_rx_packet(priv, &work_done);
1163 } while (more && work_done < budget);
1166 /* The interrupt is telling us to kick the MAC back to life
1167 * after an RX overflow
1169 if (unlikely(priv->need_mac_restart)) {
1170 ftgmac100_start_hw(priv);
1172 /* Re-enable "bad" interrupts */
1173 iowrite32(FTGMAC100_INT_BAD,
1174 priv->base + FTGMAC100_OFFSET_IER);
1177 /* As long as we are waiting for transmit packets to be
1178 * completed we keep NAPI going
1180 if (ftgmac100_tx_buf_cleanable(priv))
1183 if (work_done < budget) {
1184 /* We are about to re-enable all interrupts. However
1185 * the HW has been latching RX/TX packet interrupts while
1186 * they were masked. So we clear them first, then we need
1187 * to re-check if there's something to process
1189 iowrite32(FTGMAC100_INT_RXTX,
1190 priv->base + FTGMAC100_OFFSET_ISR);
1191 if (ftgmac100_check_rx(priv) ||
1192 ftgmac100_tx_buf_cleanable(priv))
1195 /* deschedule NAPI */
1196 napi_complete(napi);
1198 /* enable all interrupts */
1199 iowrite32(FTGMAC100_INT_ALL,
1200 priv->base + FTGMAC100_OFFSET_IER);
1206 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1210 /* Re-init descriptors (adjust queue sizes) */
1211 ftgmac100_init_rings(priv);
1213 /* Realloc rx descriptors */
1214 err = ftgmac100_alloc_rx_buffers(priv);
1215 if (err && !ignore_alloc_err)
1218 /* Reinit and restart HW */
1219 ftgmac100_init_hw(priv);
1220 ftgmac100_start_hw(priv);
1222 /* Re-enable the device */
1223 napi_enable(&priv->napi);
1224 netif_start_queue(priv->netdev);
1226 /* Enable all interrupts */
1227 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1232 static void ftgmac100_reset_task(struct work_struct *work)
1234 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1236 struct net_device *netdev = priv->netdev;
1239 netdev_dbg(netdev, "Resetting NIC...\n");
1241 /* Lock the world */
1244 mutex_lock(&netdev->phydev->lock);
1246 mutex_lock(&priv->mii_bus->mdio_lock);
1249 /* Check if the interface is still up */
1250 if (!netif_running(netdev))
1253 /* Stop the network stack */
1254 netif_trans_update(netdev);
1255 napi_disable(&priv->napi);
1256 netif_tx_disable(netdev);
1258 /* Stop and reset the MAC */
1259 ftgmac100_stop_hw(priv);
1260 err = ftgmac100_reset_and_config_mac(priv);
1262 /* Not much we can do ... it might come back... */
1263 netdev_err(netdev, "attempting to continue...\n");
1266 /* Free all rx and tx buffers */
1267 ftgmac100_free_buffers(priv);
1269 /* Setup everything again and restart chip */
1270 ftgmac100_init_all(priv, true);
1272 netdev_dbg(netdev, "Reset done !\n");
1275 mutex_unlock(&priv->mii_bus->mdio_lock);
1277 mutex_unlock(&netdev->phydev->lock);
1281 static int ftgmac100_open(struct net_device *netdev)
1283 struct ftgmac100 *priv = netdev_priv(netdev);
1286 /* Allocate ring buffers */
1287 err = ftgmac100_alloc_rings(priv);
1289 netdev_err(netdev, "Failed to allocate descriptors\n");
1293 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1295 * Otherwise we leave it set to 0 (no link), the link
1296 * message from the PHY layer will handle setting it up to
1297 * something else if needed.
1299 if (priv->use_ncsi) {
1300 priv->cur_duplex = DUPLEX_FULL;
1301 priv->cur_speed = SPEED_100;
1303 priv->cur_duplex = 0;
1304 priv->cur_speed = 0;
1307 /* Reset the hardware */
1308 err = ftgmac100_reset_and_config_mac(priv);
1312 /* Initialize NAPI */
1313 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1315 /* Grab our interrupt */
1316 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1318 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1322 /* Start things up */
1323 err = ftgmac100_init_all(priv, false);
1325 netdev_err(netdev, "Failed to allocate packet buffers\n");
1329 if (netdev->phydev) {
1330 /* If we have a PHY, start polling */
1331 phy_start(netdev->phydev);
1332 } else if (priv->use_ncsi) {
1333 /* If using NC-SI, set our carrier on and start the stack */
1334 netif_carrier_on(netdev);
1336 /* Start the NCSI device */
1337 err = ncsi_start_dev(priv->ndev);
1345 napi_disable(&priv->napi);
1346 netif_stop_queue(netdev);
1348 ftgmac100_free_buffers(priv);
1349 free_irq(netdev->irq, netdev);
1351 netif_napi_del(&priv->napi);
1353 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1354 ftgmac100_free_rings(priv);
1358 static int ftgmac100_stop(struct net_device *netdev)
1360 struct ftgmac100 *priv = netdev_priv(netdev);
1362 /* Note about the reset task: We are called with the rtnl lock
1363 * held, so we are synchronized against the core of the reset
1364 * task. We must not try to synchronously cancel it otherwise
1365 * we can deadlock. But since it will test for netif_running()
1366 * which has already been cleared by the net core, we don't
1367 * anything special to do.
1370 /* disable all interrupts */
1371 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1373 netif_stop_queue(netdev);
1374 napi_disable(&priv->napi);
1375 netif_napi_del(&priv->napi);
1377 phy_stop(netdev->phydev);
1378 else if (priv->use_ncsi)
1379 ncsi_stop_dev(priv->ndev);
1381 ftgmac100_stop_hw(priv);
1382 free_irq(netdev->irq, netdev);
1383 ftgmac100_free_buffers(priv);
1384 ftgmac100_free_rings(priv);
1390 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1392 if (!netdev->phydev)
1395 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1398 static void ftgmac100_tx_timeout(struct net_device *netdev)
1400 struct ftgmac100 *priv = netdev_priv(netdev);
1402 /* Disable all interrupts */
1403 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1405 /* Do the reset outside of interrupt context */
1406 schedule_work(&priv->reset_task);
1409 static const struct net_device_ops ftgmac100_netdev_ops = {
1410 .ndo_open = ftgmac100_open,
1411 .ndo_stop = ftgmac100_stop,
1412 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1413 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1414 .ndo_validate_addr = eth_validate_addr,
1415 .ndo_do_ioctl = ftgmac100_do_ioctl,
1416 .ndo_tx_timeout = ftgmac100_tx_timeout,
1419 static int ftgmac100_setup_mdio(struct net_device *netdev)
1421 struct ftgmac100 *priv = netdev_priv(netdev);
1422 struct platform_device *pdev = to_platform_device(priv->dev);
1426 /* initialize mdio bus */
1427 priv->mii_bus = mdiobus_alloc();
1431 if (priv->is_aspeed) {
1432 /* This driver supports the old MDIO interface */
1433 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1434 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1435 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1438 priv->mii_bus->name = "ftgmac100_mdio";
1439 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1440 pdev->name, pdev->id);
1441 priv->mii_bus->priv = priv->netdev;
1442 priv->mii_bus->read = ftgmac100_mdiobus_read;
1443 priv->mii_bus->write = ftgmac100_mdiobus_write;
1445 for (i = 0; i < PHY_MAX_ADDR; i++)
1446 priv->mii_bus->irq[i] = PHY_POLL;
1448 err = mdiobus_register(priv->mii_bus);
1450 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1451 goto err_register_mdiobus;
1454 err = ftgmac100_mii_probe(priv);
1456 dev_err(priv->dev, "MII Probe failed!\n");
1463 mdiobus_unregister(priv->mii_bus);
1464 err_register_mdiobus:
1465 mdiobus_free(priv->mii_bus);
1469 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1471 struct ftgmac100 *priv = netdev_priv(netdev);
1473 if (!netdev->phydev)
1476 phy_disconnect(netdev->phydev);
1477 mdiobus_unregister(priv->mii_bus);
1478 mdiobus_free(priv->mii_bus);
1481 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1483 if (unlikely(nd->state != ncsi_dev_state_functional))
1486 netdev_info(nd->dev, "NCSI interface %s\n",
1487 nd->link_up ? "up" : "down");
1490 static int ftgmac100_probe(struct platform_device *pdev)
1492 struct resource *res;
1494 struct net_device *netdev;
1495 struct ftgmac100 *priv;
1496 struct device_node *np;
1502 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1506 irq = platform_get_irq(pdev, 0);
1510 /* setup net_device */
1511 netdev = alloc_etherdev(sizeof(*priv));
1514 goto err_alloc_etherdev;
1517 SET_NETDEV_DEV(netdev, &pdev->dev);
1519 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1520 netdev->netdev_ops = &ftgmac100_netdev_ops;
1521 netdev->watchdog_timeo = 5 * HZ;
1523 platform_set_drvdata(pdev, netdev);
1525 /* setup private data */
1526 priv = netdev_priv(netdev);
1527 priv->netdev = netdev;
1528 priv->dev = &pdev->dev;
1529 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1532 priv->res = request_mem_region(res->start, resource_size(res),
1533 dev_name(&pdev->dev));
1535 dev_err(&pdev->dev, "Could not reserve memory region\n");
1540 priv->base = ioremap(res->start, resource_size(res));
1542 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1549 /* MAC address from chip or random one */
1550 ftgmac100_initial_mac(priv);
1552 np = pdev->dev.of_node;
1553 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1554 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1555 priv->rxdes0_edorr_mask = BIT(30);
1556 priv->txdes0_edotr_mask = BIT(30);
1557 priv->is_aspeed = true;
1559 priv->rxdes0_edorr_mask = BIT(15);
1560 priv->txdes0_edotr_mask = BIT(15);
1563 if (np && of_get_property(np, "use-ncsi", NULL)) {
1564 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1565 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1569 dev_info(&pdev->dev, "Using NCSI interface\n");
1570 priv->use_ncsi = true;
1571 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1575 priv->use_ncsi = false;
1576 err = ftgmac100_setup_mdio(netdev);
1578 goto err_setup_mdio;
1581 /* Default ring sizes */
1582 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1583 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1585 /* Base feature set */
1586 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1587 NETIF_F_GRO | NETIF_F_SG;
1589 /* AST2400 doesn't have working HW checksum generation */
1590 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1591 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1592 if (np && of_get_property(np, "no-hw-checksum", NULL))
1593 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1594 netdev->features |= netdev->hw_features;
1596 /* register network device */
1597 err = register_netdev(netdev);
1599 dev_err(&pdev->dev, "Failed to register netdev\n");
1600 goto err_register_netdev;
1603 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1608 err_register_netdev:
1609 ftgmac100_destroy_mdio(netdev);
1611 iounmap(priv->base);
1613 release_resource(priv->res);
1615 netif_napi_del(&priv->napi);
1616 free_netdev(netdev);
1621 static int ftgmac100_remove(struct platform_device *pdev)
1623 struct net_device *netdev;
1624 struct ftgmac100 *priv;
1626 netdev = platform_get_drvdata(pdev);
1627 priv = netdev_priv(netdev);
1629 unregister_netdev(netdev);
1631 /* There's a small chance the reset task will have been re-queued,
1632 * during stop, make sure it's gone before we free the structure.
1634 cancel_work_sync(&priv->reset_task);
1636 ftgmac100_destroy_mdio(netdev);
1638 iounmap(priv->base);
1639 release_resource(priv->res);
1641 netif_napi_del(&priv->napi);
1642 free_netdev(netdev);
1646 static const struct of_device_id ftgmac100_of_match[] = {
1647 { .compatible = "faraday,ftgmac100" },
1650 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1652 static struct platform_driver ftgmac100_driver = {
1653 .probe = ftgmac100_probe,
1654 .remove = ftgmac100_remove,
1657 .of_match_table = ftgmac100_of_match,
1660 module_platform_driver(ftgmac100_driver);
1662 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1663 MODULE_DESCRIPTION("FTGMAC100 driver");
1664 MODULE_LICENSE("GPL");