2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1518
47 #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */
49 struct ftgmac100_descs {
50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
59 struct ftgmac100_descs *descs;
60 dma_addr_t descs_dma_addr;
63 struct page *rx_pages[RX_QUEUE_ENTRIES];
64 unsigned int rx_pointer;
65 u32 rxdes0_edorr_mask;
68 unsigned int tx_clean_pointer;
69 unsigned int tx_pointer;
70 unsigned int tx_pending;
71 u32 txdes0_edotr_mask;
74 /* Scratch page to use when rx skb alloc fails */
76 dma_addr_t rx_scratch_dma;
78 /* Component structures */
79 struct net_device *netdev;
81 struct ncsi_dev *ndev;
82 struct napi_struct napi;
83 struct work_struct reset_task;
84 struct mii_bus *mii_bus;
92 bool need_mac_restart;
95 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
97 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
100 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
103 size = FTGMAC100_RBSR_SIZE(size);
104 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
107 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
110 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
113 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
115 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
118 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
120 struct net_device *netdev = priv->netdev;
123 /* NOTE: reset clears all registers */
124 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
125 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
126 priv->base + FTGMAC100_OFFSET_MACCR);
127 for (i = 0; i < 50; i++) {
130 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
131 if (!(maccr & FTGMAC100_MACCR_SW_RST))
137 netdev_err(netdev, "Hardware reset failed\n");
141 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
145 switch (priv->cur_speed) {
147 case 0: /* no link */
151 maccr |= FTGMAC100_MACCR_FAST_MODE;
155 maccr |= FTGMAC100_MACCR_GIGA_MODE;
158 netdev_err(priv->netdev, "Unknown speed %d !\n",
163 /* (Re)initialize the queue pointers */
164 priv->rx_pointer = 0;
165 priv->tx_clean_pointer = 0;
166 priv->tx_pointer = 0;
167 priv->tx_pending = 0;
169 /* The doc says reset twice with 10us interval */
170 if (ftgmac100_reset_mac(priv, maccr))
172 usleep_range(10, 1000);
173 return ftgmac100_reset_mac(priv, maccr);
176 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
178 unsigned int maddr = mac[0] << 8 | mac[1];
179 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
181 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
182 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
185 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
192 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
194 ether_addr_copy(priv->netdev->dev_addr, mac);
195 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
200 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
201 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
203 mac[0] = (m >> 8) & 0xff;
205 mac[2] = (l >> 24) & 0xff;
206 mac[3] = (l >> 16) & 0xff;
207 mac[4] = (l >> 8) & 0xff;
210 if (is_valid_ether_addr(mac)) {
211 ether_addr_copy(priv->netdev->dev_addr, mac);
212 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
214 eth_hw_addr_random(priv->netdev);
215 dev_info(priv->dev, "Generated random MAC address %pM\n",
216 priv->netdev->dev_addr);
220 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
224 ret = eth_prepare_mac_addr_change(dev, p);
228 eth_commit_mac_addr_change(dev, p);
229 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
234 static void ftgmac100_init_hw(struct ftgmac100 *priv)
236 /* setup ring buffer base registers */
237 ftgmac100_set_rx_ring_base(priv,
238 priv->descs_dma_addr +
239 offsetof(struct ftgmac100_descs, rxdes));
240 ftgmac100_set_normal_prio_tx_ring_base(priv,
241 priv->descs_dma_addr +
242 offsetof(struct ftgmac100_descs, txdes));
244 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
246 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
248 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
251 static void ftgmac100_start_hw(struct ftgmac100 *priv)
253 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
255 /* Keep the original GMAC and FAST bits */
256 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
258 /* Add all the main enable bits */
259 maccr |= FTGMAC100_MACCR_TXDMA_EN |
260 FTGMAC100_MACCR_RXDMA_EN |
261 FTGMAC100_MACCR_TXMAC_EN |
262 FTGMAC100_MACCR_RXMAC_EN |
263 FTGMAC100_MACCR_CRC_APD |
264 FTGMAC100_MACCR_PHY_LINK_LEVEL |
265 FTGMAC100_MACCR_RX_RUNT |
266 FTGMAC100_MACCR_RX_BROADPKT;
268 /* Add other bits as needed */
269 if (priv->cur_duplex == DUPLEX_FULL)
270 maccr |= FTGMAC100_MACCR_FULLDUP;
273 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
276 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
278 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
281 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
283 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
286 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
288 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
291 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
293 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
296 static void ftgmac100_rxdes_set_dma_own(const struct ftgmac100 *priv,
297 struct ftgmac100_rxdes *rxdes)
299 /* clear status bits */
300 rxdes->rxdes0 &= cpu_to_le32(priv->rxdes0_edorr_mask);
303 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
305 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
308 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
310 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
313 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
315 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
318 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
320 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
323 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
325 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
328 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
330 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
333 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
335 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
338 static void ftgmac100_rxdes_set_end_of_ring(const struct ftgmac100 *priv,
339 struct ftgmac100_rxdes *rxdes)
341 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
344 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
347 rxdes->rxdes3 = cpu_to_le32(addr);
350 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
352 return le32_to_cpu(rxdes->rxdes3);
355 static inline bool ftgmac100_rxdes_csum_err(struct ftgmac100_rxdes *rxdes)
357 return !!(rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
358 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
359 FTGMAC100_RXDES1_IP_CHKSUM_ERR));
362 static inline struct page **ftgmac100_rxdes_page_slot(struct ftgmac100 *priv,
363 struct ftgmac100_rxdes *rxdes)
365 return &priv->rx_pages[rxdes - priv->descs->rxdes];
369 * rxdes2 is not used by hardware. We use it to keep track of page.
370 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
372 static void ftgmac100_rxdes_set_page(struct ftgmac100 *priv,
373 struct ftgmac100_rxdes *rxdes,
376 *ftgmac100_rxdes_page_slot(priv, rxdes) = page;
379 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100 *priv,
380 struct ftgmac100_rxdes *rxdes)
382 return *ftgmac100_rxdes_page_slot(priv, rxdes);
385 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
386 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
388 struct net_device *netdev = priv->netdev;
393 page = alloc_page(gfp);
396 netdev_err(netdev, "failed to allocate rx page\n");
398 map = priv->rx_scratch_dma;
401 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
402 if (unlikely(dma_mapping_error(priv->dev, map))) {
404 netdev_err(netdev, "failed to map rx page\n");
407 map = priv->rx_scratch_dma;
411 ftgmac100_rxdes_set_page(priv, rxdes, page);
412 ftgmac100_rxdes_set_dma_addr(rxdes, map);
413 ftgmac100_rxdes_set_dma_own(priv, rxdes);
417 static int ftgmac100_next_rx_pointer(int pointer)
419 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
422 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
424 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
427 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
429 return &priv->descs->rxdes[priv->rx_pointer];
432 static struct ftgmac100_rxdes *
433 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
435 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
437 while (ftgmac100_rxdes_packet_ready(rxdes)) {
438 if (ftgmac100_rxdes_first_segment(rxdes))
441 ftgmac100_rxdes_set_dma_own(priv, rxdes);
442 ftgmac100_rx_pointer_advance(priv);
443 rxdes = ftgmac100_current_rxdes(priv);
449 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
450 struct ftgmac100_rxdes *rxdes)
452 struct net_device *netdev = priv->netdev;
455 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
457 netdev_info(netdev, "rx err\n");
459 netdev->stats.rx_errors++;
463 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
465 netdev_info(netdev, "rx crc err\n");
467 netdev->stats.rx_crc_errors++;
471 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
473 netdev_info(netdev, "rx frame too long\n");
475 netdev->stats.rx_length_errors++;
477 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
479 netdev_info(netdev, "rx runt\n");
481 netdev->stats.rx_length_errors++;
483 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
485 netdev_info(netdev, "rx odd nibble\n");
487 netdev->stats.rx_length_errors++;
494 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
496 struct net_device *netdev = priv->netdev;
497 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
501 netdev_dbg(netdev, "drop packet %p\n", rxdes);
504 if (ftgmac100_rxdes_last_segment(rxdes))
507 ftgmac100_rxdes_set_dma_own(priv, rxdes);
508 ftgmac100_rx_pointer_advance(priv);
509 rxdes = ftgmac100_current_rxdes(priv);
510 } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
512 netdev->stats.rx_dropped++;
515 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
517 struct net_device *netdev = priv->netdev;
518 struct ftgmac100_rxdes *rxdes;
524 rxdes = ftgmac100_rx_locate_first_segment(priv);
528 /* We don't support segmented rx frames, so drop these
529 * along with packets with errors.
531 if (unlikely(!ftgmac100_rxdes_last_segment(rxdes) ||
532 ftgmac100_rx_packet_error(priv, rxdes))) {
533 ftgmac100_rx_drop_packet(priv);
537 /* If the packet had no buffer (failed to allocate earlier)
538 * then try to allocate one and skip
540 page = ftgmac100_rxdes_get_page(priv, rxdes);
542 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
543 ftgmac100_rx_pointer_advance(priv);
547 /* start processing */
548 skb = netdev_alloc_skb_ip_align(netdev, 128);
549 if (unlikely(!skb)) {
551 netdev_err(netdev, "rx skb alloc failed\n");
553 ftgmac100_rx_drop_packet(priv);
557 if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
558 netdev->stats.multicast++;
560 /* If the HW found checksum errors, bounce it to software.
562 * If we didn't, we need to see if the packet was recognized
563 * by HW as one of the supported checksummed protocols before
564 * we accept the HW test results.
566 if (netdev->features & NETIF_F_RXCSUM) {
567 __le32 csum_vlan = rxdes->rxdes1;
568 __le32 err_bits = cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
569 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
570 FTGMAC100_RXDES1_IP_CHKSUM_ERR);
571 if ((csum_vlan & err_bits) ||
572 !(csum_vlan & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)))
573 skb->ip_summed = CHECKSUM_NONE;
575 skb->ip_summed = CHECKSUM_UNNECESSARY;
578 map = ftgmac100_rxdes_get_dma_addr(rxdes);
580 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
582 size = ftgmac100_rxdes_data_length(rxdes);
583 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
586 skb->data_len += size;
587 skb->truesize += PAGE_SIZE;
589 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
591 ftgmac100_rx_pointer_advance(priv);
592 rxdes = ftgmac100_current_rxdes(priv);
594 /* Small frames are copied into linear part of skb to free one page */
595 if (skb->len <= 128) {
596 skb->truesize -= PAGE_SIZE;
597 __pskb_pull_tail(skb, skb->len);
599 /* We pull the minimum amount into linear part */
600 __pskb_pull_tail(skb, ETH_HLEN);
602 skb->protocol = eth_type_trans(skb, netdev);
604 netdev->stats.rx_packets++;
605 netdev->stats.rx_bytes += skb->len;
607 /* push packet to protocol stack */
608 if (skb->ip_summed == CHECKSUM_NONE)
609 netif_receive_skb(skb);
611 napi_gro_receive(&priv->napi, skb);
617 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
618 struct ftgmac100_txdes *txdes)
620 /* clear all except end of ring bit */
621 txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask);
627 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
629 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
632 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
635 * Make sure dma own bit will not be set before any other
639 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
642 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv,
643 struct ftgmac100_txdes *txdes)
645 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
648 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
650 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
653 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
655 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
658 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
661 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
664 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
666 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
669 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
671 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
674 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
676 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
679 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
681 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
684 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
687 txdes->txdes3 = cpu_to_le32(addr);
690 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
692 return le32_to_cpu(txdes->txdes3);
696 * txdes2 is not used by hardware. We use it to keep track of socket buffer.
697 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
699 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
702 txdes->txdes2 = (unsigned int)skb;
705 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
707 return (struct sk_buff *)txdes->txdes2;
710 static int ftgmac100_next_tx_pointer(int pointer)
712 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
715 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
717 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
720 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
722 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
725 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
727 return &priv->descs->txdes[priv->tx_pointer];
730 static struct ftgmac100_txdes *
731 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
733 return &priv->descs->txdes[priv->tx_clean_pointer];
736 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
738 struct net_device *netdev = priv->netdev;
739 struct ftgmac100_txdes *txdes;
743 if (priv->tx_pending == 0)
746 txdes = ftgmac100_current_clean_txdes(priv);
748 if (ftgmac100_txdes_owned_by_dma(txdes))
751 skb = ftgmac100_txdes_get_skb(txdes);
752 map = ftgmac100_txdes_get_dma_addr(txdes);
754 netdev->stats.tx_packets++;
755 netdev->stats.tx_bytes += skb->len;
757 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
761 ftgmac100_txdes_reset(priv, txdes);
763 ftgmac100_tx_clean_pointer_advance(priv);
765 spin_lock(&priv->tx_lock);
767 spin_unlock(&priv->tx_lock);
768 netif_wake_queue(netdev);
773 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
775 while (ftgmac100_tx_complete_packet(priv))
779 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
782 struct net_device *netdev = priv->netdev;
783 struct ftgmac100_txdes *txdes;
784 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
786 txdes = ftgmac100_current_txdes(priv);
787 ftgmac100_tx_pointer_advance(priv);
789 /* setup TX descriptor */
790 ftgmac100_txdes_set_skb(txdes, skb);
791 ftgmac100_txdes_set_dma_addr(txdes, map);
792 ftgmac100_txdes_set_buffer_size(txdes, len);
794 ftgmac100_txdes_set_first_segment(txdes);
795 ftgmac100_txdes_set_last_segment(txdes);
796 ftgmac100_txdes_set_txint(txdes);
797 if (skb->ip_summed == CHECKSUM_PARTIAL) {
798 __be16 protocol = skb->protocol;
800 if (protocol == cpu_to_be16(ETH_P_IP)) {
801 u8 ip_proto = ip_hdr(skb)->protocol;
803 ftgmac100_txdes_set_ipcs(txdes);
804 if (ip_proto == IPPROTO_TCP)
805 ftgmac100_txdes_set_tcpcs(txdes);
806 else if (ip_proto == IPPROTO_UDP)
807 ftgmac100_txdes_set_udpcs(txdes);
811 spin_lock(&priv->tx_lock);
813 if (priv->tx_pending == TX_QUEUE_ENTRIES)
814 netif_stop_queue(netdev);
817 ftgmac100_txdes_set_dma_own(txdes);
818 spin_unlock(&priv->tx_lock);
820 ftgmac100_txdma_normal_prio_start_polling(priv);
825 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
829 /* Free all RX buffers */
830 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
831 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
832 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
833 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
838 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
842 /* Free all TX buffers */
843 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
844 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
845 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
846 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
851 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
856 static void ftgmac100_free_rings(struct ftgmac100 *priv)
858 /* Free descriptors */
860 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
861 priv->descs, priv->descs_dma_addr);
863 /* Free scratch packet buffer */
864 if (priv->rx_scratch)
865 dma_free_coherent(priv->dev, RX_BUF_SIZE,
866 priv->rx_scratch, priv->rx_scratch_dma);
869 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
871 /* Allocate descriptors */
872 priv->descs = dma_zalloc_coherent(priv->dev,
873 sizeof(struct ftgmac100_descs),
874 &priv->descs_dma_addr, GFP_KERNEL);
878 /* Allocate scratch packet buffer */
879 priv->rx_scratch = dma_alloc_coherent(priv->dev,
881 &priv->rx_scratch_dma,
883 if (!priv->rx_scratch)
889 static void ftgmac100_init_rings(struct ftgmac100 *priv)
893 /* Initialize RX ring */
894 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
895 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
896 ftgmac100_rxdes_set_dma_addr(rxdes, priv->rx_scratch_dma);
899 ftgmac100_rxdes_set_end_of_ring(priv, &priv->descs->rxdes[i - 1]);
901 /* Initialize TX ring */
902 for (i = 0; i < TX_QUEUE_ENTRIES; i++)
903 priv->descs->txdes[i].txdes0 = 0;
904 ftgmac100_txdes_set_end_of_ring(priv, &priv->descs->txdes[i -1]);
907 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
911 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
912 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
914 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
920 static void ftgmac100_adjust_link(struct net_device *netdev)
922 struct ftgmac100 *priv = netdev_priv(netdev);
923 struct phy_device *phydev = netdev->phydev;
926 /* We store "no link" as speed 0 */
930 new_speed = phydev->speed;
932 if (phydev->speed == priv->cur_speed &&
933 phydev->duplex == priv->cur_duplex)
936 /* Print status if we have a link or we had one and just lost it,
937 * don't print otherwise.
939 if (new_speed || priv->cur_speed)
940 phy_print_status(phydev);
942 priv->cur_speed = new_speed;
943 priv->cur_duplex = phydev->duplex;
945 /* Link is down, do nothing else */
949 /* Disable all interrupts */
950 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
952 /* Reset the adapter asynchronously */
953 schedule_work(&priv->reset_task);
956 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
958 struct net_device *netdev = priv->netdev;
959 struct phy_device *phydev;
961 phydev = phy_find_first(priv->mii_bus);
963 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
967 phydev = phy_connect(netdev, phydev_name(phydev),
968 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
970 if (IS_ERR(phydev)) {
971 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
972 return PTR_ERR(phydev);
978 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
980 struct net_device *netdev = bus->priv;
981 struct ftgmac100 *priv = netdev_priv(netdev);
985 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
987 /* preserve MDC cycle threshold */
988 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
990 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
991 FTGMAC100_PHYCR_REGAD(regnum) |
992 FTGMAC100_PHYCR_MIIRD;
994 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
996 for (i = 0; i < 10; i++) {
997 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
999 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1002 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1003 return FTGMAC100_PHYDATA_MIIRDATA(data);
1009 netdev_err(netdev, "mdio read timed out\n");
1013 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1014 int regnum, u16 value)
1016 struct net_device *netdev = bus->priv;
1017 struct ftgmac100 *priv = netdev_priv(netdev);
1022 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1024 /* preserve MDC cycle threshold */
1025 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1027 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1028 FTGMAC100_PHYCR_REGAD(regnum) |
1029 FTGMAC100_PHYCR_MIIWR;
1031 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1033 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1034 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1036 for (i = 0; i < 10; i++) {
1037 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1039 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1045 netdev_err(netdev, "mdio write timed out\n");
1049 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1050 struct ethtool_drvinfo *info)
1052 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1053 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1054 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1057 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1058 .get_drvinfo = ftgmac100_get_drvinfo,
1059 .get_link = ethtool_op_get_link,
1060 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1061 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1064 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1066 struct net_device *netdev = dev_id;
1067 struct ftgmac100 *priv = netdev_priv(netdev);
1068 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1070 /* Fetch and clear interrupt bits, process abnormal ones */
1071 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1072 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1073 if (unlikely(status & FTGMAC100_INT_BAD)) {
1075 /* RX buffer unavailable */
1076 if (status & FTGMAC100_INT_NO_RXBUF)
1077 netdev->stats.rx_over_errors++;
1079 /* received packet lost due to RX FIFO full */
1080 if (status & FTGMAC100_INT_RPKT_LOST)
1081 netdev->stats.rx_fifo_errors++;
1083 /* sent packet lost due to excessive TX collision */
1084 if (status & FTGMAC100_INT_XPKT_LOST)
1085 netdev->stats.tx_fifo_errors++;
1087 /* AHB error -> Reset the chip */
1088 if (status & FTGMAC100_INT_AHB_ERR) {
1089 if (net_ratelimit())
1091 "AHB bus error ! Resetting chip.\n");
1092 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1093 schedule_work(&priv->reset_task);
1097 /* We may need to restart the MAC after such errors, delay
1098 * this until after we have freed some Rx buffers though
1100 priv->need_mac_restart = true;
1102 /* Disable those errors until we restart */
1103 new_mask &= ~status;
1106 /* Only enable "bad" interrupts while NAPI is on */
1107 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1109 /* Schedule NAPI bh */
1110 napi_schedule_irqoff(&priv->napi);
1115 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1117 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1118 bool more, completed = true;
1121 ftgmac100_tx_complete(priv);
1124 more = ftgmac100_rx_packet(priv, &rx);
1125 } while (more && rx < budget);
1127 if (more && rx == budget)
1131 /* The interrupt is telling us to kick the MAC back to life
1132 * after an RX overflow
1134 if (unlikely(priv->need_mac_restart)) {
1135 ftgmac100_start_hw(priv);
1137 /* Re-enable "bad" interrupts */
1138 iowrite32(FTGMAC100_INT_BAD,
1139 priv->base + FTGMAC100_OFFSET_IER);
1142 /* Keep NAPI going if we have still packets to reclaim */
1143 if (priv->tx_pending)
1147 /* We are about to re-enable all interrupts. However
1148 * the HW has been latching RX/TX packet interrupts while
1149 * they were masked. So we clear them first, then we need
1150 * to re-check if there's something to process
1152 iowrite32(FTGMAC100_INT_RXTX,
1153 priv->base + FTGMAC100_OFFSET_ISR);
1154 if (ftgmac100_rxdes_packet_ready
1155 (ftgmac100_current_rxdes(priv)) || priv->tx_pending)
1158 /* deschedule NAPI */
1159 napi_complete(napi);
1161 /* enable all interrupts */
1162 iowrite32(FTGMAC100_INT_ALL,
1163 priv->base + FTGMAC100_OFFSET_IER);
1169 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1173 /* Re-init descriptors (adjust queue sizes) */
1174 ftgmac100_init_rings(priv);
1176 /* Realloc rx descriptors */
1177 err = ftgmac100_alloc_rx_buffers(priv);
1178 if (err && !ignore_alloc_err)
1181 /* Reinit and restart HW */
1182 ftgmac100_init_hw(priv);
1183 ftgmac100_start_hw(priv);
1185 /* Re-enable the device */
1186 napi_enable(&priv->napi);
1187 netif_start_queue(priv->netdev);
1189 /* Enable all interrupts */
1190 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1195 static void ftgmac100_reset_task(struct work_struct *work)
1197 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1199 struct net_device *netdev = priv->netdev;
1202 netdev_dbg(netdev, "Resetting NIC...\n");
1204 /* Lock the world */
1207 mutex_lock(&netdev->phydev->lock);
1209 mutex_lock(&priv->mii_bus->mdio_lock);
1212 /* Check if the interface is still up */
1213 if (!netif_running(netdev))
1216 /* Stop the network stack */
1217 netif_trans_update(netdev);
1218 napi_disable(&priv->napi);
1219 netif_tx_disable(netdev);
1221 /* Stop and reset the MAC */
1222 ftgmac100_stop_hw(priv);
1223 err = ftgmac100_reset_and_config_mac(priv);
1225 /* Not much we can do ... it might come back... */
1226 netdev_err(netdev, "attempting to continue...\n");
1229 /* Free all rx and tx buffers */
1230 ftgmac100_free_buffers(priv);
1232 /* Setup everything again and restart chip */
1233 ftgmac100_init_all(priv, true);
1235 netdev_dbg(netdev, "Reset done !\n");
1238 mutex_unlock(&priv->mii_bus->mdio_lock);
1240 mutex_unlock(&netdev->phydev->lock);
1244 static int ftgmac100_open(struct net_device *netdev)
1246 struct ftgmac100 *priv = netdev_priv(netdev);
1249 /* Allocate ring buffers */
1250 err = ftgmac100_alloc_rings(priv);
1252 netdev_err(netdev, "Failed to allocate descriptors\n");
1256 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1258 * Otherwise we leave it set to 0 (no link), the link
1259 * message from the PHY layer will handle setting it up to
1260 * something else if needed.
1262 if (priv->use_ncsi) {
1263 priv->cur_duplex = DUPLEX_FULL;
1264 priv->cur_speed = SPEED_100;
1266 priv->cur_duplex = 0;
1267 priv->cur_speed = 0;
1270 /* Reset the hardware */
1271 err = ftgmac100_reset_and_config_mac(priv);
1275 /* Initialize NAPI */
1276 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1278 /* Grab our interrupt */
1279 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1281 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1285 /* Start things up */
1286 err = ftgmac100_init_all(priv, false);
1288 netdev_err(netdev, "Failed to allocate packet buffers\n");
1292 if (netdev->phydev) {
1293 /* If we have a PHY, start polling */
1294 phy_start(netdev->phydev);
1295 } else if (priv->use_ncsi) {
1296 /* If using NC-SI, set our carrier on and start the stack */
1297 netif_carrier_on(netdev);
1299 /* Start the NCSI device */
1300 err = ncsi_start_dev(priv->ndev);
1308 napi_disable(&priv->napi);
1309 netif_stop_queue(netdev);
1311 ftgmac100_free_buffers(priv);
1312 free_irq(netdev->irq, netdev);
1314 netif_napi_del(&priv->napi);
1316 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1317 ftgmac100_free_rings(priv);
1321 static int ftgmac100_stop(struct net_device *netdev)
1323 struct ftgmac100 *priv = netdev_priv(netdev);
1325 /* Note about the reset task: We are called with the rtnl lock
1326 * held, so we are synchronized against the core of the reset
1327 * task. We must not try to synchronously cancel it otherwise
1328 * we can deadlock. But since it will test for netif_running()
1329 * which has already been cleared by the net core, we don't
1330 * anything special to do.
1333 /* disable all interrupts */
1334 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1336 netif_stop_queue(netdev);
1337 napi_disable(&priv->napi);
1338 netif_napi_del(&priv->napi);
1340 phy_stop(netdev->phydev);
1341 else if (priv->use_ncsi)
1342 ncsi_stop_dev(priv->ndev);
1344 ftgmac100_stop_hw(priv);
1345 free_irq(netdev->irq, netdev);
1346 ftgmac100_free_buffers(priv);
1347 ftgmac100_free_rings(priv);
1352 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1353 struct net_device *netdev)
1355 struct ftgmac100 *priv = netdev_priv(netdev);
1358 if (unlikely(skb->len > MAX_PKT_SIZE)) {
1359 if (net_ratelimit())
1360 netdev_dbg(netdev, "tx packet too big\n");
1362 netdev->stats.tx_dropped++;
1364 return NETDEV_TX_OK;
1367 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1368 if (unlikely(dma_mapping_error(priv->dev, map))) {
1370 if (net_ratelimit())
1371 netdev_err(netdev, "map socket buffer failed\n");
1373 netdev->stats.tx_dropped++;
1375 return NETDEV_TX_OK;
1378 return ftgmac100_xmit(priv, skb, map);
1382 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1384 if (!netdev->phydev)
1387 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1390 static const struct net_device_ops ftgmac100_netdev_ops = {
1391 .ndo_open = ftgmac100_open,
1392 .ndo_stop = ftgmac100_stop,
1393 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1394 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1395 .ndo_validate_addr = eth_validate_addr,
1396 .ndo_do_ioctl = ftgmac100_do_ioctl,
1399 static int ftgmac100_setup_mdio(struct net_device *netdev)
1401 struct ftgmac100 *priv = netdev_priv(netdev);
1402 struct platform_device *pdev = to_platform_device(priv->dev);
1406 /* initialize mdio bus */
1407 priv->mii_bus = mdiobus_alloc();
1411 if (of_machine_is_compatible("aspeed,ast2400") ||
1412 of_machine_is_compatible("aspeed,ast2500")) {
1413 /* This driver supports the old MDIO interface */
1414 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1415 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1416 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1419 priv->mii_bus->name = "ftgmac100_mdio";
1420 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1421 pdev->name, pdev->id);
1422 priv->mii_bus->priv = priv->netdev;
1423 priv->mii_bus->read = ftgmac100_mdiobus_read;
1424 priv->mii_bus->write = ftgmac100_mdiobus_write;
1426 for (i = 0; i < PHY_MAX_ADDR; i++)
1427 priv->mii_bus->irq[i] = PHY_POLL;
1429 err = mdiobus_register(priv->mii_bus);
1431 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1432 goto err_register_mdiobus;
1435 err = ftgmac100_mii_probe(priv);
1437 dev_err(priv->dev, "MII Probe failed!\n");
1444 mdiobus_unregister(priv->mii_bus);
1445 err_register_mdiobus:
1446 mdiobus_free(priv->mii_bus);
1450 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1452 struct ftgmac100 *priv = netdev_priv(netdev);
1454 if (!netdev->phydev)
1457 phy_disconnect(netdev->phydev);
1458 mdiobus_unregister(priv->mii_bus);
1459 mdiobus_free(priv->mii_bus);
1462 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1464 if (unlikely(nd->state != ncsi_dev_state_functional))
1467 netdev_info(nd->dev, "NCSI interface %s\n",
1468 nd->link_up ? "up" : "down");
1471 static int ftgmac100_probe(struct platform_device *pdev)
1473 struct resource *res;
1475 struct net_device *netdev;
1476 struct ftgmac100 *priv;
1482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1486 irq = platform_get_irq(pdev, 0);
1490 /* setup net_device */
1491 netdev = alloc_etherdev(sizeof(*priv));
1494 goto err_alloc_etherdev;
1497 SET_NETDEV_DEV(netdev, &pdev->dev);
1499 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1500 netdev->netdev_ops = &ftgmac100_netdev_ops;
1502 platform_set_drvdata(pdev, netdev);
1504 /* setup private data */
1505 priv = netdev_priv(netdev);
1506 priv->netdev = netdev;
1507 priv->dev = &pdev->dev;
1508 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1510 spin_lock_init(&priv->tx_lock);
1513 priv->res = request_mem_region(res->start, resource_size(res),
1514 dev_name(&pdev->dev));
1516 dev_err(&pdev->dev, "Could not reserve memory region\n");
1521 priv->base = ioremap(res->start, resource_size(res));
1523 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1530 /* MAC address from chip or random one */
1531 ftgmac100_setup_mac(priv);
1533 if (of_machine_is_compatible("aspeed,ast2400") ||
1534 of_machine_is_compatible("aspeed,ast2500")) {
1535 priv->rxdes0_edorr_mask = BIT(30);
1536 priv->txdes0_edotr_mask = BIT(30);
1538 priv->rxdes0_edorr_mask = BIT(15);
1539 priv->txdes0_edotr_mask = BIT(15);
1542 if (pdev->dev.of_node &&
1543 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1544 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1545 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1549 dev_info(&pdev->dev, "Using NCSI interface\n");
1550 priv->use_ncsi = true;
1551 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1555 priv->use_ncsi = false;
1556 err = ftgmac100_setup_mdio(netdev);
1558 goto err_setup_mdio;
1561 /* We have to disable on-chip IP checksum functionality
1562 * when NCSI is enabled on the interface. It doesn't work
1565 netdev->features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_GRO;
1566 if (priv->use_ncsi &&
1567 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1568 netdev->features &= ~NETIF_F_IP_CSUM;
1571 /* register network device */
1572 err = register_netdev(netdev);
1574 dev_err(&pdev->dev, "Failed to register netdev\n");
1575 goto err_register_netdev;
1578 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1583 err_register_netdev:
1584 ftgmac100_destroy_mdio(netdev);
1586 iounmap(priv->base);
1588 release_resource(priv->res);
1590 netif_napi_del(&priv->napi);
1591 free_netdev(netdev);
1596 static int ftgmac100_remove(struct platform_device *pdev)
1598 struct net_device *netdev;
1599 struct ftgmac100 *priv;
1601 netdev = platform_get_drvdata(pdev);
1602 priv = netdev_priv(netdev);
1604 unregister_netdev(netdev);
1606 /* There's a small chance the reset task will have been re-queued,
1607 * during stop, make sure it's gone before we free the structure.
1609 cancel_work_sync(&priv->reset_task);
1611 ftgmac100_destroy_mdio(netdev);
1613 iounmap(priv->base);
1614 release_resource(priv->res);
1616 netif_napi_del(&priv->napi);
1617 free_netdev(netdev);
1621 static const struct of_device_id ftgmac100_of_match[] = {
1622 { .compatible = "faraday,ftgmac100" },
1625 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1627 static struct platform_driver ftgmac100_driver = {
1628 .probe = ftgmac100_probe,
1629 .remove = ftgmac100_remove,
1632 .of_match_table = ftgmac100_of_match,
1635 module_platform_driver(ftgmac100_driver);
1637 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1638 MODULE_DESCRIPTION("FTGMAC100 driver");
1639 MODULE_LICENSE("GPL");