2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 /* Arbitrary values, I am not sure the HW has limits */
44 #define MAX_RX_QUEUE_ENTRIES 1024
45 #define MAX_TX_QUEUE_ENTRIES 1024
46 #define MIN_RX_QUEUE_ENTRIES 32
47 #define MIN_TX_QUEUE_ENTRIES 32
50 #define DEF_RX_QUEUE_ENTRIES 128
51 #define DEF_TX_QUEUE_ENTRIES 128
53 #define MAX_PKT_SIZE 1536
54 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
56 /* Min number of tx ring entries before stopping queue */
57 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
65 unsigned int rx_q_entries;
66 struct ftgmac100_rxdes *rxdes;
68 struct sk_buff **rx_skbs;
69 unsigned int rx_pointer;
70 u32 rxdes0_edorr_mask;
73 unsigned int tx_q_entries;
74 struct ftgmac100_txdes *txdes;
76 struct sk_buff **tx_skbs;
77 unsigned int tx_clean_pointer;
78 unsigned int tx_pointer;
79 u32 txdes0_edotr_mask;
81 /* Used to signal the reset task of ring change request */
82 unsigned int new_rx_q_entries;
83 unsigned int new_tx_q_entries;
85 /* Scratch page to use when rx skb alloc fails */
87 dma_addr_t rx_scratch_dma;
89 /* Component structures */
90 struct net_device *netdev;
92 struct ncsi_dev *ndev;
93 struct napi_struct napi;
94 struct work_struct reset_task;
95 struct mii_bus *mii_bus;
102 /* Flow control settings */
108 bool need_mac_restart;
112 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
114 struct net_device *netdev = priv->netdev;
117 /* NOTE: reset clears all registers */
118 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
119 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
120 priv->base + FTGMAC100_OFFSET_MACCR);
121 for (i = 0; i < 50; i++) {
124 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
125 if (!(maccr & FTGMAC100_MACCR_SW_RST))
131 netdev_err(netdev, "Hardware reset failed\n");
135 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
139 switch (priv->cur_speed) {
141 case 0: /* no link */
145 maccr |= FTGMAC100_MACCR_FAST_MODE;
149 maccr |= FTGMAC100_MACCR_GIGA_MODE;
152 netdev_err(priv->netdev, "Unknown speed %d !\n",
157 /* (Re)initialize the queue pointers */
158 priv->rx_pointer = 0;
159 priv->tx_clean_pointer = 0;
160 priv->tx_pointer = 0;
162 /* The doc says reset twice with 10us interval */
163 if (ftgmac100_reset_mac(priv, maccr))
165 usleep_range(10, 1000);
166 return ftgmac100_reset_mac(priv, maccr);
169 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
171 unsigned int maddr = mac[0] << 8 | mac[1];
172 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
174 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
175 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
178 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
185 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
187 ether_addr_copy(priv->netdev->dev_addr, mac);
188 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
193 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
194 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
196 mac[0] = (m >> 8) & 0xff;
198 mac[2] = (l >> 24) & 0xff;
199 mac[3] = (l >> 16) & 0xff;
200 mac[4] = (l >> 8) & 0xff;
203 if (is_valid_ether_addr(mac)) {
204 ether_addr_copy(priv->netdev->dev_addr, mac);
205 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
207 eth_hw_addr_random(priv->netdev);
208 dev_info(priv->dev, "Generated random MAC address %pM\n",
209 priv->netdev->dev_addr);
213 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
217 ret = eth_prepare_mac_addr_change(dev, p);
221 eth_commit_mac_addr_change(dev, p);
222 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
227 static void ftgmac100_config_pause(struct ftgmac100 *priv)
229 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
231 /* Throttle tx queue when receiving pause frames */
233 fcr |= FTGMAC100_FCR_FC_EN;
235 /* Enables sending pause frames when the RX queue is past a
239 fcr |= FTGMAC100_FCR_FCTHR_EN;
241 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
244 static void ftgmac100_init_hw(struct ftgmac100 *priv)
246 u32 reg, rfifo_sz, tfifo_sz;
248 /* Clear stale interrupts */
249 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
250 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
252 /* Setup RX ring buffer base */
253 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
255 /* Setup TX ring buffer base */
256 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
258 /* Configure RX buffer size */
259 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
260 priv->base + FTGMAC100_OFFSET_RBSR);
262 /* Set RX descriptor autopoll */
263 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
264 priv->base + FTGMAC100_OFFSET_APTC);
266 /* Write MAC address */
267 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
269 /* Configure descriptor sizes and increase burst sizes according
270 * to values in Aspeed SDK. The FIFO arbitration is enabled and
271 * the thresholds set based on the recommended values in the
272 * AST2400 specification.
274 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
275 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
276 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
277 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
278 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
279 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
280 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
281 priv->base + FTGMAC100_OFFSET_DBLAC);
283 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
284 * mitigation doesn't seem to provide any benefit with NAPI so leave
287 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
288 FTGMAC100_ITC_TXINT_THR(1),
289 priv->base + FTGMAC100_OFFSET_ITC);
291 /* Configure FIFO sizes in the TPAFCR register */
292 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
293 rfifo_sz = reg & 0x00000007;
294 tfifo_sz = (reg >> 3) & 0x00000007;
295 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
297 reg |= (tfifo_sz << 27);
298 reg |= (rfifo_sz << 24);
299 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
302 static void ftgmac100_start_hw(struct ftgmac100 *priv)
304 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
306 /* Keep the original GMAC and FAST bits */
307 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
309 /* Add all the main enable bits */
310 maccr |= FTGMAC100_MACCR_TXDMA_EN |
311 FTGMAC100_MACCR_RXDMA_EN |
312 FTGMAC100_MACCR_TXMAC_EN |
313 FTGMAC100_MACCR_RXMAC_EN |
314 FTGMAC100_MACCR_CRC_APD |
315 FTGMAC100_MACCR_PHY_LINK_LEVEL |
316 FTGMAC100_MACCR_RX_RUNT |
317 FTGMAC100_MACCR_RX_BROADPKT;
319 /* Add other bits as needed */
320 if (priv->cur_duplex == DUPLEX_FULL)
321 maccr |= FTGMAC100_MACCR_FULLDUP;
324 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
327 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
329 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
332 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
333 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
335 struct net_device *netdev = priv->netdev;
340 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
341 if (unlikely(!skb)) {
343 netdev_warn(netdev, "failed to allocate rx skb\n");
345 map = priv->rx_scratch_dma;
347 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
349 if (unlikely(dma_mapping_error(priv->dev, map))) {
351 netdev_err(netdev, "failed to map rx page\n");
352 dev_kfree_skb_any(skb);
353 map = priv->rx_scratch_dma;
360 priv->rx_skbs[entry] = skb;
362 /* Store DMA address into RX desc */
363 rxdes->rxdes3 = cpu_to_le32(map);
365 /* Ensure the above is ordered vs clearing the OWN bit */
368 /* Clean status (which resets own bit) */
369 if (entry == (priv->rx_q_entries - 1))
370 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
377 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
378 unsigned int pointer)
380 return (pointer + 1) & (priv->rx_q_entries - 1);
383 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
385 struct net_device *netdev = priv->netdev;
387 if (status & FTGMAC100_RXDES0_RX_ERR)
388 netdev->stats.rx_errors++;
390 if (status & FTGMAC100_RXDES0_CRC_ERR)
391 netdev->stats.rx_crc_errors++;
393 if (status & (FTGMAC100_RXDES0_FTL |
394 FTGMAC100_RXDES0_RUNT |
395 FTGMAC100_RXDES0_RX_ODD_NB))
396 netdev->stats.rx_length_errors++;
399 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
401 struct net_device *netdev = priv->netdev;
402 struct ftgmac100_rxdes *rxdes;
404 unsigned int pointer, size;
405 u32 status, csum_vlan;
408 /* Grab next RX descriptor */
409 pointer = priv->rx_pointer;
410 rxdes = &priv->rxdes[pointer];
412 /* Grab descriptor status */
413 status = le32_to_cpu(rxdes->rxdes0);
415 /* Do we have a packet ? */
416 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
419 /* Order subsequent reads with the test for the ready bit */
422 /* We don't cope with fragmented RX packets */
423 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
424 !(status & FTGMAC100_RXDES0_LRS)))
427 /* Grab received size and csum vlan field in the descriptor */
428 size = status & FTGMAC100_RXDES0_VDBC;
429 csum_vlan = le32_to_cpu(rxdes->rxdes1);
431 /* Any error (other than csum offload) flagged ? */
432 if (unlikely(status & RXDES0_ANY_ERROR)) {
433 /* Correct for incorrect flagging of runt packets
434 * with vlan tags... Just accept a runt packet that
435 * has been flagged as vlan and whose size is at
438 if ((status & FTGMAC100_RXDES0_RUNT) &&
439 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
441 status &= ~FTGMAC100_RXDES0_RUNT;
443 /* Any error still in there ? */
444 if (status & RXDES0_ANY_ERROR) {
445 ftgmac100_rx_packet_error(priv, status);
450 /* If the packet had no skb (failed to allocate earlier)
451 * then try to allocate one and skip
453 skb = priv->rx_skbs[pointer];
454 if (!unlikely(skb)) {
455 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
459 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
460 netdev->stats.multicast++;
462 /* If the HW found checksum errors, bounce it to software.
464 * If we didn't, we need to see if the packet was recognized
465 * by HW as one of the supported checksummed protocols before
466 * we accept the HW test results.
468 if (netdev->features & NETIF_F_RXCSUM) {
469 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
470 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
471 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
472 if ((csum_vlan & err_bits) ||
473 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
474 skb->ip_summed = CHECKSUM_NONE;
476 skb->ip_summed = CHECKSUM_UNNECESSARY;
479 /* Transfer received size to skb */
482 /* Tear down DMA mapping, do necessary cache management */
483 map = le32_to_cpu(rxdes->rxdes3);
485 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
486 /* When we don't have an iommu, we can save cycles by not
487 * invalidating the cache for the part of the packet that
490 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
492 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
496 /* Resplenish rx ring */
497 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
498 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
500 skb->protocol = eth_type_trans(skb, netdev);
502 netdev->stats.rx_packets++;
503 netdev->stats.rx_bytes += size;
505 /* push packet to protocol stack */
506 if (skb->ip_summed == CHECKSUM_NONE)
507 netif_receive_skb(skb);
509 napi_gro_receive(&priv->napi, skb);
515 /* Clean rxdes0 (which resets own bit) */
516 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
517 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
518 netdev->stats.rx_dropped++;
522 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
525 if (index == (priv->tx_q_entries - 1))
526 return priv->txdes0_edotr_mask;
531 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
532 unsigned int pointer)
534 return (pointer + 1) & (priv->tx_q_entries - 1);
537 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
539 /* Returns the number of available slots in the TX queue
541 * This always leaves one free slot so we don't have to
542 * worry about empty vs. full, and this simplifies the
543 * test for ftgmac100_tx_buf_cleanable() below
545 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
546 (priv->tx_q_entries - 1);
549 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
551 return priv->tx_pointer != priv->tx_clean_pointer;
554 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
555 unsigned int pointer,
557 struct ftgmac100_txdes *txdes,
560 dma_addr_t map = le32_to_cpu(txdes->txdes3);
563 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
564 len = skb_headlen(skb);
565 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
567 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
568 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
571 /* Free SKB on last segment */
572 if (ctl_stat & FTGMAC100_TXDES0_LTS)
574 priv->tx_skbs[pointer] = NULL;
577 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
579 struct net_device *netdev = priv->netdev;
580 struct ftgmac100_txdes *txdes;
582 unsigned int pointer;
585 pointer = priv->tx_clean_pointer;
586 txdes = &priv->txdes[pointer];
588 ctl_stat = le32_to_cpu(txdes->txdes0);
589 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
592 skb = priv->tx_skbs[pointer];
593 netdev->stats.tx_packets++;
594 netdev->stats.tx_bytes += skb->len;
595 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
596 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
598 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
603 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
605 struct net_device *netdev = priv->netdev;
607 /* Process all completed packets */
608 while (ftgmac100_tx_buf_cleanable(priv) &&
609 ftgmac100_tx_complete_packet(priv))
612 /* Restart queue if needed */
614 if (unlikely(netif_queue_stopped(netdev) &&
615 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
616 struct netdev_queue *txq;
618 txq = netdev_get_tx_queue(netdev, 0);
619 __netif_tx_lock(txq, smp_processor_id());
620 if (netif_queue_stopped(netdev) &&
621 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
622 netif_wake_queue(netdev);
623 __netif_tx_unlock(txq);
627 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
629 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
630 u8 ip_proto = ip_hdr(skb)->protocol;
632 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
635 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
638 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
644 return skb_checksum_help(skb) == 0;
647 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
648 struct net_device *netdev)
650 struct ftgmac100 *priv = netdev_priv(netdev);
651 struct ftgmac100_txdes *txdes, *first;
652 unsigned int pointer, nfrags, len, i, j;
653 u32 f_ctl_stat, ctl_stat, csum_vlan;
656 /* The HW doesn't pad small frames */
657 if (eth_skb_pad(skb)) {
658 netdev->stats.tx_dropped++;
662 /* Reject oversize packets */
663 if (unlikely(skb->len > MAX_PKT_SIZE)) {
665 netdev_dbg(netdev, "tx packet too big\n");
669 /* Do we have a limit on #fragments ? I yet have to get a reply
670 * from Aspeed. If there's one I haven't hit it.
672 nfrags = skb_shinfo(skb)->nr_frags;
675 len = skb_headlen(skb);
677 /* Map the packet head */
678 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
679 if (dma_mapping_error(priv->dev, map)) {
681 netdev_err(netdev, "map tx packet head failed\n");
685 /* Grab the next free tx descriptor */
686 pointer = priv->tx_pointer;
687 txdes = first = &priv->txdes[pointer];
689 /* Setup it up with the packet head. Don't write the head to the
692 priv->tx_skbs[pointer] = skb;
693 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
694 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
695 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
696 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
698 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
699 txdes->txdes3 = cpu_to_le32(map);
701 /* Setup HW checksumming */
703 if (skb->ip_summed == CHECKSUM_PARTIAL &&
704 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
706 txdes->txdes1 = cpu_to_le32(csum_vlan);
708 /* Next descriptor */
709 pointer = ftgmac100_next_tx_pointer(priv, pointer);
711 /* Add the fragments */
712 for (i = 0; i < nfrags; i++) {
713 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
718 map = skb_frag_dma_map(priv->dev, frag, 0, len,
720 if (dma_mapping_error(priv->dev, map))
723 /* Setup descriptor */
724 priv->tx_skbs[pointer] = skb;
725 txdes = &priv->txdes[pointer];
726 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
727 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
728 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
729 if (i == (nfrags - 1))
730 ctl_stat |= FTGMAC100_TXDES0_LTS;
731 txdes->txdes0 = cpu_to_le32(ctl_stat);
733 txdes->txdes3 = cpu_to_le32(map);
736 pointer = ftgmac100_next_tx_pointer(priv, pointer);
739 /* Order the previous packet and descriptor udpates
740 * before setting the OWN bit on the first descriptor.
743 first->txdes0 = cpu_to_le32(f_ctl_stat);
745 /* Update next TX pointer */
746 priv->tx_pointer = pointer;
748 /* If there isn't enough room for all the fragments of a new packet
749 * in the TX ring, stop the queue. The sequence below is race free
750 * vs. a concurrent restart in ftgmac100_poll()
752 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
753 netif_stop_queue(netdev);
754 /* Order the queue stop with the test below */
756 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
757 netif_wake_queue(netdev);
760 /* Poke transmitter to read the updated TX descriptors */
761 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
767 netdev_err(netdev, "map tx fragment failed\n");
770 pointer = priv->tx_pointer;
771 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
772 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
774 /* Then all fragments */
775 for (j = 0; j < i; j++) {
776 pointer = ftgmac100_next_tx_pointer(priv, pointer);
777 txdes = &priv->txdes[pointer];
778 ctl_stat = le32_to_cpu(txdes->txdes0);
779 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
780 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
783 /* This cannot be reached if we successfully mapped the
784 * last fragment, so we know ftgmac100_free_tx_packet()
785 * hasn't freed the skb yet.
788 /* Drop the packet */
789 dev_kfree_skb_any(skb);
790 netdev->stats.tx_dropped++;
795 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
799 /* Free all RX buffers */
800 for (i = 0; i < priv->rx_q_entries; i++) {
801 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
802 struct sk_buff *skb = priv->rx_skbs[i];
803 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
808 priv->rx_skbs[i] = NULL;
809 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
810 dev_kfree_skb_any(skb);
813 /* Free all TX buffers */
814 for (i = 0; i < priv->tx_q_entries; i++) {
815 struct ftgmac100_txdes *txdes = &priv->txdes[i];
816 struct sk_buff *skb = priv->tx_skbs[i];
820 ftgmac100_free_tx_packet(priv, i, skb, txdes,
821 le32_to_cpu(txdes->txdes0));
825 static void ftgmac100_free_rings(struct ftgmac100 *priv)
827 /* Free skb arrays */
828 kfree(priv->rx_skbs);
829 kfree(priv->tx_skbs);
831 /* Free descriptors */
833 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
834 sizeof(struct ftgmac100_rxdes),
835 priv->rxdes, priv->rxdes_dma);
839 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
840 sizeof(struct ftgmac100_txdes),
841 priv->txdes, priv->txdes_dma);
844 /* Free scratch packet buffer */
845 if (priv->rx_scratch)
846 dma_free_coherent(priv->dev, RX_BUF_SIZE,
847 priv->rx_scratch, priv->rx_scratch_dma);
850 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
852 /* Allocate skb arrays */
853 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
857 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
862 /* Allocate descriptors */
863 priv->rxdes = dma_zalloc_coherent(priv->dev,
864 MAX_RX_QUEUE_ENTRIES *
865 sizeof(struct ftgmac100_rxdes),
866 &priv->rxdes_dma, GFP_KERNEL);
869 priv->txdes = dma_zalloc_coherent(priv->dev,
870 MAX_TX_QUEUE_ENTRIES *
871 sizeof(struct ftgmac100_txdes),
872 &priv->txdes_dma, GFP_KERNEL);
876 /* Allocate scratch packet buffer */
877 priv->rx_scratch = dma_alloc_coherent(priv->dev,
879 &priv->rx_scratch_dma,
881 if (!priv->rx_scratch)
887 static void ftgmac100_init_rings(struct ftgmac100 *priv)
889 struct ftgmac100_rxdes *rxdes = NULL;
890 struct ftgmac100_txdes *txdes = NULL;
893 /* Update entries counts */
894 priv->rx_q_entries = priv->new_rx_q_entries;
895 priv->tx_q_entries = priv->new_tx_q_entries;
897 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
900 /* Initialize RX ring */
901 for (i = 0; i < priv->rx_q_entries; i++) {
902 rxdes = &priv->rxdes[i];
904 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
906 /* Mark the end of the ring */
907 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
909 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
912 /* Initialize TX ring */
913 for (i = 0; i < priv->tx_q_entries; i++) {
914 txdes = &priv->txdes[i];
917 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
920 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
924 for (i = 0; i < priv->rx_q_entries; i++) {
925 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
927 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
933 static void ftgmac100_adjust_link(struct net_device *netdev)
935 struct ftgmac100 *priv = netdev_priv(netdev);
936 struct phy_device *phydev = netdev->phydev;
937 bool tx_pause, rx_pause;
940 /* We store "no link" as speed 0 */
944 new_speed = phydev->speed;
946 /* Grab pause settings from PHY if configured to do so */
947 if (priv->aneg_pause) {
948 rx_pause = tx_pause = phydev->pause;
949 if (phydev->asym_pause)
950 tx_pause = !rx_pause;
952 rx_pause = priv->rx_pause;
953 tx_pause = priv->tx_pause;
956 /* Link hasn't changed, do nothing */
957 if (phydev->speed == priv->cur_speed &&
958 phydev->duplex == priv->cur_duplex &&
959 rx_pause == priv->rx_pause &&
960 tx_pause == priv->tx_pause)
963 /* Print status if we have a link or we had one and just lost it,
964 * don't print otherwise.
966 if (new_speed || priv->cur_speed)
967 phy_print_status(phydev);
969 priv->cur_speed = new_speed;
970 priv->cur_duplex = phydev->duplex;
971 priv->rx_pause = rx_pause;
972 priv->tx_pause = tx_pause;
974 /* Link is down, do nothing else */
978 /* Disable all interrupts */
979 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
981 /* Reset the adapter asynchronously */
982 schedule_work(&priv->reset_task);
985 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
987 struct net_device *netdev = priv->netdev;
988 struct phy_device *phydev;
990 phydev = phy_find_first(priv->mii_bus);
992 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
996 phydev = phy_connect(netdev, phydev_name(phydev),
997 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
999 if (IS_ERR(phydev)) {
1000 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1001 return PTR_ERR(phydev);
1004 /* Indicate that we support PAUSE frames (see comment in
1005 * Documentation/networking/phy.txt)
1007 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1008 phydev->advertising = phydev->supported;
1013 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1015 struct net_device *netdev = bus->priv;
1016 struct ftgmac100 *priv = netdev_priv(netdev);
1020 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1022 /* preserve MDC cycle threshold */
1023 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1025 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1026 FTGMAC100_PHYCR_REGAD(regnum) |
1027 FTGMAC100_PHYCR_MIIRD;
1029 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1031 for (i = 0; i < 10; i++) {
1032 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1034 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1037 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1038 return FTGMAC100_PHYDATA_MIIRDATA(data);
1044 netdev_err(netdev, "mdio read timed out\n");
1048 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1049 int regnum, u16 value)
1051 struct net_device *netdev = bus->priv;
1052 struct ftgmac100 *priv = netdev_priv(netdev);
1057 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1059 /* preserve MDC cycle threshold */
1060 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1062 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1063 FTGMAC100_PHYCR_REGAD(regnum) |
1064 FTGMAC100_PHYCR_MIIWR;
1066 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1068 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1069 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1071 for (i = 0; i < 10; i++) {
1072 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1074 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1080 netdev_err(netdev, "mdio write timed out\n");
1084 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1085 struct ethtool_drvinfo *info)
1087 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1088 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1089 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1092 static void ftgmac100_get_ringparam(struct net_device *netdev,
1093 struct ethtool_ringparam *ering)
1095 struct ftgmac100 *priv = netdev_priv(netdev);
1097 memset(ering, 0, sizeof(*ering));
1098 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1099 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1100 ering->rx_pending = priv->rx_q_entries;
1101 ering->tx_pending = priv->tx_q_entries;
1104 static int ftgmac100_set_ringparam(struct net_device *netdev,
1105 struct ethtool_ringparam *ering)
1107 struct ftgmac100 *priv = netdev_priv(netdev);
1109 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1110 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1111 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1112 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1113 !is_power_of_2(ering->rx_pending) ||
1114 !is_power_of_2(ering->tx_pending))
1117 priv->new_rx_q_entries = ering->rx_pending;
1118 priv->new_tx_q_entries = ering->tx_pending;
1119 if (netif_running(netdev))
1120 schedule_work(&priv->reset_task);
1125 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1126 struct ethtool_pauseparam *pause)
1128 struct ftgmac100 *priv = netdev_priv(netdev);
1130 pause->autoneg = priv->aneg_pause;
1131 pause->tx_pause = priv->tx_pause;
1132 pause->rx_pause = priv->rx_pause;
1135 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1136 struct ethtool_pauseparam *pause)
1138 struct ftgmac100 *priv = netdev_priv(netdev);
1139 struct phy_device *phydev = netdev->phydev;
1141 priv->aneg_pause = pause->autoneg;
1142 priv->tx_pause = pause->tx_pause;
1143 priv->rx_pause = pause->rx_pause;
1146 phydev->advertising &= ~ADVERTISED_Pause;
1147 phydev->advertising &= ~ADVERTISED_Asym_Pause;
1149 if (pause->rx_pause) {
1150 phydev->advertising |= ADVERTISED_Pause;
1151 phydev->advertising |= ADVERTISED_Asym_Pause;
1154 if (pause->tx_pause)
1155 phydev->advertising ^= ADVERTISED_Asym_Pause;
1157 if (netif_running(netdev)) {
1158 if (phydev && priv->aneg_pause)
1159 phy_start_aneg(phydev);
1161 ftgmac100_config_pause(priv);
1167 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1168 .get_drvinfo = ftgmac100_get_drvinfo,
1169 .get_link = ethtool_op_get_link,
1170 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1171 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1172 .nway_reset = phy_ethtool_nway_reset,
1173 .get_ringparam = ftgmac100_get_ringparam,
1174 .set_ringparam = ftgmac100_set_ringparam,
1175 .get_pauseparam = ftgmac100_get_pauseparam,
1176 .set_pauseparam = ftgmac100_set_pauseparam,
1179 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1181 struct net_device *netdev = dev_id;
1182 struct ftgmac100 *priv = netdev_priv(netdev);
1183 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1185 /* Fetch and clear interrupt bits, process abnormal ones */
1186 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1187 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1188 if (unlikely(status & FTGMAC100_INT_BAD)) {
1190 /* RX buffer unavailable */
1191 if (status & FTGMAC100_INT_NO_RXBUF)
1192 netdev->stats.rx_over_errors++;
1194 /* received packet lost due to RX FIFO full */
1195 if (status & FTGMAC100_INT_RPKT_LOST)
1196 netdev->stats.rx_fifo_errors++;
1198 /* sent packet lost due to excessive TX collision */
1199 if (status & FTGMAC100_INT_XPKT_LOST)
1200 netdev->stats.tx_fifo_errors++;
1202 /* AHB error -> Reset the chip */
1203 if (status & FTGMAC100_INT_AHB_ERR) {
1204 if (net_ratelimit())
1206 "AHB bus error ! Resetting chip.\n");
1207 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1208 schedule_work(&priv->reset_task);
1212 /* We may need to restart the MAC after such errors, delay
1213 * this until after we have freed some Rx buffers though
1215 priv->need_mac_restart = true;
1217 /* Disable those errors until we restart */
1218 new_mask &= ~status;
1221 /* Only enable "bad" interrupts while NAPI is on */
1222 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1224 /* Schedule NAPI bh */
1225 napi_schedule_irqoff(&priv->napi);
1230 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1232 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1234 /* Do we have a packet ? */
1235 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1238 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1240 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1244 /* Handle TX completions */
1245 if (ftgmac100_tx_buf_cleanable(priv))
1246 ftgmac100_tx_complete(priv);
1248 /* Handle RX packets */
1250 more = ftgmac100_rx_packet(priv, &work_done);
1251 } while (more && work_done < budget);
1254 /* The interrupt is telling us to kick the MAC back to life
1255 * after an RX overflow
1257 if (unlikely(priv->need_mac_restart)) {
1258 ftgmac100_start_hw(priv);
1260 /* Re-enable "bad" interrupts */
1261 iowrite32(FTGMAC100_INT_BAD,
1262 priv->base + FTGMAC100_OFFSET_IER);
1265 /* As long as we are waiting for transmit packets to be
1266 * completed we keep NAPI going
1268 if (ftgmac100_tx_buf_cleanable(priv))
1271 if (work_done < budget) {
1272 /* We are about to re-enable all interrupts. However
1273 * the HW has been latching RX/TX packet interrupts while
1274 * they were masked. So we clear them first, then we need
1275 * to re-check if there's something to process
1277 iowrite32(FTGMAC100_INT_RXTX,
1278 priv->base + FTGMAC100_OFFSET_ISR);
1279 if (ftgmac100_check_rx(priv) ||
1280 ftgmac100_tx_buf_cleanable(priv))
1283 /* deschedule NAPI */
1284 napi_complete(napi);
1286 /* enable all interrupts */
1287 iowrite32(FTGMAC100_INT_ALL,
1288 priv->base + FTGMAC100_OFFSET_IER);
1294 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1298 /* Re-init descriptors (adjust queue sizes) */
1299 ftgmac100_init_rings(priv);
1301 /* Realloc rx descriptors */
1302 err = ftgmac100_alloc_rx_buffers(priv);
1303 if (err && !ignore_alloc_err)
1306 /* Reinit and restart HW */
1307 ftgmac100_init_hw(priv);
1308 ftgmac100_config_pause(priv);
1309 ftgmac100_start_hw(priv);
1311 /* Re-enable the device */
1312 napi_enable(&priv->napi);
1313 netif_start_queue(priv->netdev);
1315 /* Enable all interrupts */
1316 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1321 static void ftgmac100_reset_task(struct work_struct *work)
1323 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1325 struct net_device *netdev = priv->netdev;
1328 netdev_dbg(netdev, "Resetting NIC...\n");
1330 /* Lock the world */
1333 mutex_lock(&netdev->phydev->lock);
1335 mutex_lock(&priv->mii_bus->mdio_lock);
1338 /* Check if the interface is still up */
1339 if (!netif_running(netdev))
1342 /* Stop the network stack */
1343 netif_trans_update(netdev);
1344 napi_disable(&priv->napi);
1345 netif_tx_disable(netdev);
1347 /* Stop and reset the MAC */
1348 ftgmac100_stop_hw(priv);
1349 err = ftgmac100_reset_and_config_mac(priv);
1351 /* Not much we can do ... it might come back... */
1352 netdev_err(netdev, "attempting to continue...\n");
1355 /* Free all rx and tx buffers */
1356 ftgmac100_free_buffers(priv);
1358 /* Setup everything again and restart chip */
1359 ftgmac100_init_all(priv, true);
1361 netdev_dbg(netdev, "Reset done !\n");
1364 mutex_unlock(&priv->mii_bus->mdio_lock);
1366 mutex_unlock(&netdev->phydev->lock);
1370 static int ftgmac100_open(struct net_device *netdev)
1372 struct ftgmac100 *priv = netdev_priv(netdev);
1375 /* Allocate ring buffers */
1376 err = ftgmac100_alloc_rings(priv);
1378 netdev_err(netdev, "Failed to allocate descriptors\n");
1382 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1384 * Otherwise we leave it set to 0 (no link), the link
1385 * message from the PHY layer will handle setting it up to
1386 * something else if needed.
1388 if (priv->use_ncsi) {
1389 priv->cur_duplex = DUPLEX_FULL;
1390 priv->cur_speed = SPEED_100;
1392 priv->cur_duplex = 0;
1393 priv->cur_speed = 0;
1396 /* Reset the hardware */
1397 err = ftgmac100_reset_and_config_mac(priv);
1401 /* Initialize NAPI */
1402 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1404 /* Grab our interrupt */
1405 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1407 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1411 /* Start things up */
1412 err = ftgmac100_init_all(priv, false);
1414 netdev_err(netdev, "Failed to allocate packet buffers\n");
1418 if (netdev->phydev) {
1419 /* If we have a PHY, start polling */
1420 phy_start(netdev->phydev);
1421 } else if (priv->use_ncsi) {
1422 /* If using NC-SI, set our carrier on and start the stack */
1423 netif_carrier_on(netdev);
1425 /* Start the NCSI device */
1426 err = ncsi_start_dev(priv->ndev);
1434 napi_disable(&priv->napi);
1435 netif_stop_queue(netdev);
1437 ftgmac100_free_buffers(priv);
1438 free_irq(netdev->irq, netdev);
1440 netif_napi_del(&priv->napi);
1442 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1443 ftgmac100_free_rings(priv);
1447 static int ftgmac100_stop(struct net_device *netdev)
1449 struct ftgmac100 *priv = netdev_priv(netdev);
1451 /* Note about the reset task: We are called with the rtnl lock
1452 * held, so we are synchronized against the core of the reset
1453 * task. We must not try to synchronously cancel it otherwise
1454 * we can deadlock. But since it will test for netif_running()
1455 * which has already been cleared by the net core, we don't
1456 * anything special to do.
1459 /* disable all interrupts */
1460 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1462 netif_stop_queue(netdev);
1463 napi_disable(&priv->napi);
1464 netif_napi_del(&priv->napi);
1466 phy_stop(netdev->phydev);
1467 else if (priv->use_ncsi)
1468 ncsi_stop_dev(priv->ndev);
1470 ftgmac100_stop_hw(priv);
1471 free_irq(netdev->irq, netdev);
1472 ftgmac100_free_buffers(priv);
1473 ftgmac100_free_rings(priv);
1479 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1481 if (!netdev->phydev)
1484 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1487 static void ftgmac100_tx_timeout(struct net_device *netdev)
1489 struct ftgmac100 *priv = netdev_priv(netdev);
1491 /* Disable all interrupts */
1492 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1494 /* Do the reset outside of interrupt context */
1495 schedule_work(&priv->reset_task);
1498 static const struct net_device_ops ftgmac100_netdev_ops = {
1499 .ndo_open = ftgmac100_open,
1500 .ndo_stop = ftgmac100_stop,
1501 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1502 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1503 .ndo_validate_addr = eth_validate_addr,
1504 .ndo_do_ioctl = ftgmac100_do_ioctl,
1505 .ndo_tx_timeout = ftgmac100_tx_timeout,
1508 static int ftgmac100_setup_mdio(struct net_device *netdev)
1510 struct ftgmac100 *priv = netdev_priv(netdev);
1511 struct platform_device *pdev = to_platform_device(priv->dev);
1515 /* initialize mdio bus */
1516 priv->mii_bus = mdiobus_alloc();
1520 if (priv->is_aspeed) {
1521 /* This driver supports the old MDIO interface */
1522 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1523 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1524 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1527 priv->mii_bus->name = "ftgmac100_mdio";
1528 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1529 pdev->name, pdev->id);
1530 priv->mii_bus->priv = priv->netdev;
1531 priv->mii_bus->read = ftgmac100_mdiobus_read;
1532 priv->mii_bus->write = ftgmac100_mdiobus_write;
1534 for (i = 0; i < PHY_MAX_ADDR; i++)
1535 priv->mii_bus->irq[i] = PHY_POLL;
1537 err = mdiobus_register(priv->mii_bus);
1539 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1540 goto err_register_mdiobus;
1543 err = ftgmac100_mii_probe(priv);
1545 dev_err(priv->dev, "MII Probe failed!\n");
1552 mdiobus_unregister(priv->mii_bus);
1553 err_register_mdiobus:
1554 mdiobus_free(priv->mii_bus);
1558 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1560 struct ftgmac100 *priv = netdev_priv(netdev);
1562 if (!netdev->phydev)
1565 phy_disconnect(netdev->phydev);
1566 mdiobus_unregister(priv->mii_bus);
1567 mdiobus_free(priv->mii_bus);
1570 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1572 if (unlikely(nd->state != ncsi_dev_state_functional))
1575 netdev_info(nd->dev, "NCSI interface %s\n",
1576 nd->link_up ? "up" : "down");
1579 static int ftgmac100_probe(struct platform_device *pdev)
1581 struct resource *res;
1583 struct net_device *netdev;
1584 struct ftgmac100 *priv;
1585 struct device_node *np;
1591 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1595 irq = platform_get_irq(pdev, 0);
1599 /* setup net_device */
1600 netdev = alloc_etherdev(sizeof(*priv));
1603 goto err_alloc_etherdev;
1606 SET_NETDEV_DEV(netdev, &pdev->dev);
1608 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1609 netdev->netdev_ops = &ftgmac100_netdev_ops;
1610 netdev->watchdog_timeo = 5 * HZ;
1612 platform_set_drvdata(pdev, netdev);
1614 /* setup private data */
1615 priv = netdev_priv(netdev);
1616 priv->netdev = netdev;
1617 priv->dev = &pdev->dev;
1618 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1621 priv->res = request_mem_region(res->start, resource_size(res),
1622 dev_name(&pdev->dev));
1624 dev_err(&pdev->dev, "Could not reserve memory region\n");
1629 priv->base = ioremap(res->start, resource_size(res));
1631 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1639 priv->tx_pause = true;
1640 priv->rx_pause = true;
1641 priv->aneg_pause = true;
1643 /* MAC address from chip or random one */
1644 ftgmac100_initial_mac(priv);
1646 np = pdev->dev.of_node;
1647 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1648 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1649 priv->rxdes0_edorr_mask = BIT(30);
1650 priv->txdes0_edotr_mask = BIT(30);
1651 priv->is_aspeed = true;
1653 priv->rxdes0_edorr_mask = BIT(15);
1654 priv->txdes0_edotr_mask = BIT(15);
1657 if (np && of_get_property(np, "use-ncsi", NULL)) {
1658 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1659 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1663 dev_info(&pdev->dev, "Using NCSI interface\n");
1664 priv->use_ncsi = true;
1665 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1669 priv->use_ncsi = false;
1670 err = ftgmac100_setup_mdio(netdev);
1672 goto err_setup_mdio;
1675 /* Default ring sizes */
1676 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1677 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1679 /* Base feature set */
1680 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1681 NETIF_F_GRO | NETIF_F_SG;
1683 /* AST2400 doesn't have working HW checksum generation */
1684 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1685 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1686 if (np && of_get_property(np, "no-hw-checksum", NULL))
1687 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1688 netdev->features |= netdev->hw_features;
1690 /* register network device */
1691 err = register_netdev(netdev);
1693 dev_err(&pdev->dev, "Failed to register netdev\n");
1694 goto err_register_netdev;
1697 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1702 err_register_netdev:
1703 ftgmac100_destroy_mdio(netdev);
1705 iounmap(priv->base);
1707 release_resource(priv->res);
1709 netif_napi_del(&priv->napi);
1710 free_netdev(netdev);
1715 static int ftgmac100_remove(struct platform_device *pdev)
1717 struct net_device *netdev;
1718 struct ftgmac100 *priv;
1720 netdev = platform_get_drvdata(pdev);
1721 priv = netdev_priv(netdev);
1723 unregister_netdev(netdev);
1725 /* There's a small chance the reset task will have been re-queued,
1726 * during stop, make sure it's gone before we free the structure.
1728 cancel_work_sync(&priv->reset_task);
1730 ftgmac100_destroy_mdio(netdev);
1732 iounmap(priv->base);
1733 release_resource(priv->res);
1735 netif_napi_del(&priv->napi);
1736 free_netdev(netdev);
1740 static const struct of_device_id ftgmac100_of_match[] = {
1741 { .compatible = "faraday,ftgmac100" },
1744 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1746 static struct platform_driver ftgmac100_driver = {
1747 .probe = ftgmac100_probe,
1748 .remove = ftgmac100_remove,
1751 .of_match_table = ftgmac100_of_match,
1754 module_platform_driver(ftgmac100_driver);
1756 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1757 MODULE_DESCRIPTION("FTGMAC100 driver");
1758 MODULE_LICENSE("GPL");