2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
49 /* Min number of tx ring entries before stopping queue */
50 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
52 struct ftgmac100_descs {
53 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
54 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
62 struct ftgmac100_descs *descs;
63 dma_addr_t descs_dma_addr;
66 struct sk_buff *rx_skbs[RX_QUEUE_ENTRIES];
67 unsigned int rx_pointer;
68 u32 rxdes0_edorr_mask;
71 struct sk_buff *tx_skbs[TX_QUEUE_ENTRIES];
72 unsigned int tx_clean_pointer;
73 unsigned int tx_pointer;
74 u32 txdes0_edotr_mask;
76 /* Scratch page to use when rx skb alloc fails */
78 dma_addr_t rx_scratch_dma;
80 /* Component structures */
81 struct net_device *netdev;
83 struct ncsi_dev *ndev;
84 struct napi_struct napi;
85 struct work_struct reset_task;
86 struct mii_bus *mii_bus;
94 bool need_mac_restart;
98 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
100 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
103 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
106 size = FTGMAC100_RBSR_SIZE(size);
107 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
110 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
113 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
116 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
118 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
121 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
123 struct net_device *netdev = priv->netdev;
126 /* NOTE: reset clears all registers */
127 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
128 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
129 priv->base + FTGMAC100_OFFSET_MACCR);
130 for (i = 0; i < 50; i++) {
133 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
134 if (!(maccr & FTGMAC100_MACCR_SW_RST))
140 netdev_err(netdev, "Hardware reset failed\n");
144 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
148 switch (priv->cur_speed) {
150 case 0: /* no link */
154 maccr |= FTGMAC100_MACCR_FAST_MODE;
158 maccr |= FTGMAC100_MACCR_GIGA_MODE;
161 netdev_err(priv->netdev, "Unknown speed %d !\n",
166 /* (Re)initialize the queue pointers */
167 priv->rx_pointer = 0;
168 priv->tx_clean_pointer = 0;
169 priv->tx_pointer = 0;
171 /* The doc says reset twice with 10us interval */
172 if (ftgmac100_reset_mac(priv, maccr))
174 usleep_range(10, 1000);
175 return ftgmac100_reset_mac(priv, maccr);
178 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
180 unsigned int maddr = mac[0] << 8 | mac[1];
181 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
183 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
184 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
187 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
194 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
196 ether_addr_copy(priv->netdev->dev_addr, mac);
197 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
202 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
203 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
205 mac[0] = (m >> 8) & 0xff;
207 mac[2] = (l >> 24) & 0xff;
208 mac[3] = (l >> 16) & 0xff;
209 mac[4] = (l >> 8) & 0xff;
212 if (is_valid_ether_addr(mac)) {
213 ether_addr_copy(priv->netdev->dev_addr, mac);
214 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
216 eth_hw_addr_random(priv->netdev);
217 dev_info(priv->dev, "Generated random MAC address %pM\n",
218 priv->netdev->dev_addr);
222 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
226 ret = eth_prepare_mac_addr_change(dev, p);
230 eth_commit_mac_addr_change(dev, p);
231 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
236 static void ftgmac100_init_hw(struct ftgmac100 *priv)
238 /* setup ring buffer base registers */
239 ftgmac100_set_rx_ring_base(priv,
240 priv->descs_dma_addr +
241 offsetof(struct ftgmac100_descs, rxdes));
242 ftgmac100_set_normal_prio_tx_ring_base(priv,
243 priv->descs_dma_addr +
244 offsetof(struct ftgmac100_descs, txdes));
246 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
248 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
250 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
253 static void ftgmac100_start_hw(struct ftgmac100 *priv)
255 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
257 /* Keep the original GMAC and FAST bits */
258 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
260 /* Add all the main enable bits */
261 maccr |= FTGMAC100_MACCR_TXDMA_EN |
262 FTGMAC100_MACCR_RXDMA_EN |
263 FTGMAC100_MACCR_TXMAC_EN |
264 FTGMAC100_MACCR_RXMAC_EN |
265 FTGMAC100_MACCR_CRC_APD |
266 FTGMAC100_MACCR_PHY_LINK_LEVEL |
267 FTGMAC100_MACCR_RX_RUNT |
268 FTGMAC100_MACCR_RX_BROADPKT;
270 /* Add other bits as needed */
271 if (priv->cur_duplex == DUPLEX_FULL)
272 maccr |= FTGMAC100_MACCR_FULLDUP;
275 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
278 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
280 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
283 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
284 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
286 struct net_device *netdev = priv->netdev;
291 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
292 if (unlikely(!skb)) {
294 netdev_warn(netdev, "failed to allocate rx skb\n");
296 map = priv->rx_scratch_dma;
298 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
300 if (unlikely(dma_mapping_error(priv->dev, map))) {
302 netdev_err(netdev, "failed to map rx page\n");
303 dev_kfree_skb_any(skb);
304 map = priv->rx_scratch_dma;
311 priv->rx_skbs[entry] = skb;
313 /* Store DMA address into RX desc */
314 rxdes->rxdes3 = cpu_to_le32(map);
316 /* Ensure the above is ordered vs clearing the OWN bit */
319 /* Clean status (which resets own bit) */
320 if (entry == (RX_QUEUE_ENTRIES - 1))
321 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
328 static int ftgmac100_next_rx_pointer(int pointer)
330 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
333 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
335 struct net_device *netdev = priv->netdev;
337 if (status & FTGMAC100_RXDES0_RX_ERR)
338 netdev->stats.rx_errors++;
340 if (status & FTGMAC100_RXDES0_CRC_ERR)
341 netdev->stats.rx_crc_errors++;
343 if (status & (FTGMAC100_RXDES0_FTL |
344 FTGMAC100_RXDES0_RUNT |
345 FTGMAC100_RXDES0_RX_ODD_NB))
346 netdev->stats.rx_length_errors++;
349 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
351 struct net_device *netdev = priv->netdev;
352 struct ftgmac100_rxdes *rxdes;
354 unsigned int pointer, size;
355 u32 status, csum_vlan;
358 /* Grab next RX descriptor */
359 pointer = priv->rx_pointer;
360 rxdes = &priv->descs->rxdes[pointer];
362 /* Grab descriptor status */
363 status = le32_to_cpu(rxdes->rxdes0);
365 /* Do we have a packet ? */
366 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
369 /* Order subsequent reads with the test for the ready bit */
372 /* We don't cope with fragmented RX packets */
373 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
374 !(status & FTGMAC100_RXDES0_LRS)))
377 /* Grab received size and csum vlan field in the descriptor */
378 size = status & FTGMAC100_RXDES0_VDBC;
379 csum_vlan = le32_to_cpu(rxdes->rxdes1);
381 /* Any error (other than csum offload) flagged ? */
382 if (unlikely(status & RXDES0_ANY_ERROR)) {
383 /* Correct for incorrect flagging of runt packets
384 * with vlan tags... Just accept a runt packet that
385 * has been flagged as vlan and whose size is at
388 if ((status & FTGMAC100_RXDES0_RUNT) &&
389 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
391 status &= ~FTGMAC100_RXDES0_RUNT;
393 /* Any error still in there ? */
394 if (status & RXDES0_ANY_ERROR) {
395 ftgmac100_rx_packet_error(priv, status);
400 /* If the packet had no skb (failed to allocate earlier)
401 * then try to allocate one and skip
403 skb = priv->rx_skbs[pointer];
404 if (!unlikely(skb)) {
405 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
409 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
410 netdev->stats.multicast++;
412 /* If the HW found checksum errors, bounce it to software.
414 * If we didn't, we need to see if the packet was recognized
415 * by HW as one of the supported checksummed protocols before
416 * we accept the HW test results.
418 if (netdev->features & NETIF_F_RXCSUM) {
419 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
420 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
421 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
422 if ((csum_vlan & err_bits) ||
423 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
424 skb->ip_summed = CHECKSUM_NONE;
426 skb->ip_summed = CHECKSUM_UNNECESSARY;
429 /* Transfer received size to skb */
432 /* Tear down DMA mapping, do necessary cache management */
433 map = le32_to_cpu(rxdes->rxdes3);
435 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
436 /* When we don't have an iommu, we can save cycles by not
437 * invalidating the cache for the part of the packet that
440 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
442 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
446 /* Resplenish rx ring */
447 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
448 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
450 skb->protocol = eth_type_trans(skb, netdev);
452 netdev->stats.rx_packets++;
453 netdev->stats.rx_bytes += size;
455 /* push packet to protocol stack */
456 if (skb->ip_summed == CHECKSUM_NONE)
457 netif_receive_skb(skb);
459 napi_gro_receive(&priv->napi, skb);
465 /* Clean rxdes0 (which resets own bit) */
466 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
467 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
468 netdev->stats.rx_dropped++;
472 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
475 if (index == (TX_QUEUE_ENTRIES - 1))
476 return priv->txdes0_edotr_mask;
481 static int ftgmac100_next_tx_pointer(int pointer)
483 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
486 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
488 /* Returns the number of available slots in the TX queue
490 * This always leaves one free slot so we don't have to
491 * worry about empty vs. full, and this simplifies the
492 * test for ftgmac100_tx_buf_cleanable() below
494 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
495 (TX_QUEUE_ENTRIES - 1);
498 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
500 return priv->tx_pointer != priv->tx_clean_pointer;
503 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
504 unsigned int pointer,
506 struct ftgmac100_txdes *txdes,
509 dma_addr_t map = le32_to_cpu(txdes->txdes3);
512 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
513 len = skb_headlen(skb);
514 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
516 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
517 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
520 /* Free SKB on last segment */
521 if (ctl_stat & FTGMAC100_TXDES0_LTS)
523 priv->tx_skbs[pointer] = NULL;
526 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
528 struct net_device *netdev = priv->netdev;
529 struct ftgmac100_txdes *txdes;
531 unsigned int pointer;
534 pointer = priv->tx_clean_pointer;
535 txdes = &priv->descs->txdes[pointer];
537 ctl_stat = le32_to_cpu(txdes->txdes0);
538 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
541 skb = priv->tx_skbs[pointer];
542 netdev->stats.tx_packets++;
543 netdev->stats.tx_bytes += skb->len;
544 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
545 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
547 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(pointer);
552 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
554 struct net_device *netdev = priv->netdev;
556 /* Process all completed packets */
557 while (ftgmac100_tx_buf_cleanable(priv) &&
558 ftgmac100_tx_complete_packet(priv))
561 /* Restart queue if needed */
563 if (unlikely(netif_queue_stopped(netdev) &&
564 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
565 struct netdev_queue *txq;
567 txq = netdev_get_tx_queue(netdev, 0);
568 __netif_tx_lock(txq, smp_processor_id());
569 if (netif_queue_stopped(netdev) &&
570 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
571 netif_wake_queue(netdev);
572 __netif_tx_unlock(txq);
576 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
578 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
579 u8 ip_proto = ip_hdr(skb)->protocol;
581 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
584 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
587 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
593 return skb_checksum_help(skb) == 0;
596 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
597 struct net_device *netdev)
599 struct ftgmac100 *priv = netdev_priv(netdev);
600 struct ftgmac100_txdes *txdes, *first;
601 unsigned int pointer, nfrags, len, i, j;
602 u32 f_ctl_stat, ctl_stat, csum_vlan;
605 /* The HW doesn't pad small frames */
606 if (eth_skb_pad(skb)) {
607 netdev->stats.tx_dropped++;
611 /* Reject oversize packets */
612 if (unlikely(skb->len > MAX_PKT_SIZE)) {
614 netdev_dbg(netdev, "tx packet too big\n");
618 /* Do we have a limit on #fragments ? I yet have to get a reply
619 * from Aspeed. If there's one I haven't hit it.
621 nfrags = skb_shinfo(skb)->nr_frags;
624 len = skb_headlen(skb);
626 /* Map the packet head */
627 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
628 if (dma_mapping_error(priv->dev, map)) {
630 netdev_err(netdev, "map tx packet head failed\n");
634 /* Grab the next free tx descriptor */
635 pointer = priv->tx_pointer;
636 txdes = first = &priv->descs->txdes[pointer];
638 /* Setup it up with the packet head. Don't write the head to the
641 priv->tx_skbs[pointer] = skb;
642 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
643 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
644 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
645 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
647 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
648 txdes->txdes3 = cpu_to_le32(map);
650 /* Setup HW checksumming */
652 if (skb->ip_summed == CHECKSUM_PARTIAL &&
653 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
655 txdes->txdes1 = cpu_to_le32(csum_vlan);
657 /* Next descriptor */
658 pointer = ftgmac100_next_tx_pointer(pointer);
660 /* Add the fragments */
661 for (i = 0; i < nfrags; i++) {
662 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
667 map = skb_frag_dma_map(priv->dev, frag, 0, len,
669 if (dma_mapping_error(priv->dev, map))
672 /* Setup descriptor */
673 priv->tx_skbs[pointer] = skb;
674 txdes = &priv->descs->txdes[pointer];
675 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
676 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
677 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
678 if (i == (nfrags - 1))
679 ctl_stat |= FTGMAC100_TXDES0_LTS;
680 txdes->txdes0 = cpu_to_le32(ctl_stat);
682 txdes->txdes3 = cpu_to_le32(map);
685 pointer = ftgmac100_next_tx_pointer(pointer);
688 /* Order the previous packet and descriptor udpates
689 * before setting the OWN bit on the first descriptor.
692 first->txdes0 = cpu_to_le32(f_ctl_stat);
694 /* Update next TX pointer */
695 priv->tx_pointer = pointer;
697 /* If there isn't enough room for all the fragments of a new packet
698 * in the TX ring, stop the queue. The sequence below is race free
699 * vs. a concurrent restart in ftgmac100_poll()
701 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
702 netif_stop_queue(netdev);
703 /* Order the queue stop with the test below */
705 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
706 netif_wake_queue(netdev);
709 ftgmac100_txdma_normal_prio_start_polling(priv);
715 netdev_err(netdev, "map tx fragment failed\n");
718 pointer = priv->tx_pointer;
719 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
720 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
722 /* Then all fragments */
723 for (j = 0; j < i; j++) {
724 pointer = ftgmac100_next_tx_pointer(pointer);
725 txdes = &priv->descs->txdes[pointer];
726 ctl_stat = le32_to_cpu(txdes->txdes0);
727 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
728 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
731 /* This cannot be reached if we successfully mapped the
732 * last fragment, so we know ftgmac100_free_tx_packet()
733 * hasn't freed the skb yet.
736 /* Drop the packet */
737 dev_kfree_skb_any(skb);
738 netdev->stats.tx_dropped++;
743 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
747 /* Free all RX buffers */
748 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
749 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
750 struct sk_buff *skb = priv->rx_skbs[i];
751 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
756 priv->rx_skbs[i] = NULL;
757 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
758 dev_kfree_skb_any(skb);
761 /* Free all TX buffers */
762 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
763 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
764 struct sk_buff *skb = priv->tx_skbs[i];
768 ftgmac100_free_tx_packet(priv, i, skb, txdes,
769 le32_to_cpu(txdes->txdes0));
773 static void ftgmac100_free_rings(struct ftgmac100 *priv)
775 /* Free descriptors */
777 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
778 priv->descs, priv->descs_dma_addr);
780 /* Free scratch packet buffer */
781 if (priv->rx_scratch)
782 dma_free_coherent(priv->dev, RX_BUF_SIZE,
783 priv->rx_scratch, priv->rx_scratch_dma);
786 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
788 /* Allocate descriptors */
789 priv->descs = dma_zalloc_coherent(priv->dev,
790 sizeof(struct ftgmac100_descs),
791 &priv->descs_dma_addr, GFP_KERNEL);
795 /* Allocate scratch packet buffer */
796 priv->rx_scratch = dma_alloc_coherent(priv->dev,
798 &priv->rx_scratch_dma,
800 if (!priv->rx_scratch)
806 static void ftgmac100_init_rings(struct ftgmac100 *priv)
808 struct ftgmac100_rxdes *rxdes;
809 struct ftgmac100_txdes *txdes;
812 /* Initialize RX ring */
813 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
814 rxdes = &priv->descs->rxdes[i];
816 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
818 /* Mark the end of the ring */
819 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
821 /* Initialize TX ring */
822 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
823 txdes = &priv->descs->txdes[i];
826 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
829 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
833 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
834 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
836 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
842 static void ftgmac100_adjust_link(struct net_device *netdev)
844 struct ftgmac100 *priv = netdev_priv(netdev);
845 struct phy_device *phydev = netdev->phydev;
848 /* We store "no link" as speed 0 */
852 new_speed = phydev->speed;
854 if (phydev->speed == priv->cur_speed &&
855 phydev->duplex == priv->cur_duplex)
858 /* Print status if we have a link or we had one and just lost it,
859 * don't print otherwise.
861 if (new_speed || priv->cur_speed)
862 phy_print_status(phydev);
864 priv->cur_speed = new_speed;
865 priv->cur_duplex = phydev->duplex;
867 /* Link is down, do nothing else */
871 /* Disable all interrupts */
872 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
874 /* Reset the adapter asynchronously */
875 schedule_work(&priv->reset_task);
878 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
880 struct net_device *netdev = priv->netdev;
881 struct phy_device *phydev;
883 phydev = phy_find_first(priv->mii_bus);
885 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
889 phydev = phy_connect(netdev, phydev_name(phydev),
890 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
892 if (IS_ERR(phydev)) {
893 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
894 return PTR_ERR(phydev);
900 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
902 struct net_device *netdev = bus->priv;
903 struct ftgmac100 *priv = netdev_priv(netdev);
907 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
909 /* preserve MDC cycle threshold */
910 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
912 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
913 FTGMAC100_PHYCR_REGAD(regnum) |
914 FTGMAC100_PHYCR_MIIRD;
916 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
918 for (i = 0; i < 10; i++) {
919 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
921 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
924 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
925 return FTGMAC100_PHYDATA_MIIRDATA(data);
931 netdev_err(netdev, "mdio read timed out\n");
935 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
936 int regnum, u16 value)
938 struct net_device *netdev = bus->priv;
939 struct ftgmac100 *priv = netdev_priv(netdev);
944 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
946 /* preserve MDC cycle threshold */
947 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
949 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
950 FTGMAC100_PHYCR_REGAD(regnum) |
951 FTGMAC100_PHYCR_MIIWR;
953 data = FTGMAC100_PHYDATA_MIIWDATA(value);
955 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
956 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
958 for (i = 0; i < 10; i++) {
959 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
961 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
967 netdev_err(netdev, "mdio write timed out\n");
971 static void ftgmac100_get_drvinfo(struct net_device *netdev,
972 struct ethtool_drvinfo *info)
974 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
975 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
976 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
979 static const struct ethtool_ops ftgmac100_ethtool_ops = {
980 .get_drvinfo = ftgmac100_get_drvinfo,
981 .get_link = ethtool_op_get_link,
982 .get_link_ksettings = phy_ethtool_get_link_ksettings,
983 .set_link_ksettings = phy_ethtool_set_link_ksettings,
986 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
988 struct net_device *netdev = dev_id;
989 struct ftgmac100 *priv = netdev_priv(netdev);
990 unsigned int status, new_mask = FTGMAC100_INT_BAD;
992 /* Fetch and clear interrupt bits, process abnormal ones */
993 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
994 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
995 if (unlikely(status & FTGMAC100_INT_BAD)) {
997 /* RX buffer unavailable */
998 if (status & FTGMAC100_INT_NO_RXBUF)
999 netdev->stats.rx_over_errors++;
1001 /* received packet lost due to RX FIFO full */
1002 if (status & FTGMAC100_INT_RPKT_LOST)
1003 netdev->stats.rx_fifo_errors++;
1005 /* sent packet lost due to excessive TX collision */
1006 if (status & FTGMAC100_INT_XPKT_LOST)
1007 netdev->stats.tx_fifo_errors++;
1009 /* AHB error -> Reset the chip */
1010 if (status & FTGMAC100_INT_AHB_ERR) {
1011 if (net_ratelimit())
1013 "AHB bus error ! Resetting chip.\n");
1014 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1015 schedule_work(&priv->reset_task);
1019 /* We may need to restart the MAC after such errors, delay
1020 * this until after we have freed some Rx buffers though
1022 priv->need_mac_restart = true;
1024 /* Disable those errors until we restart */
1025 new_mask &= ~status;
1028 /* Only enable "bad" interrupts while NAPI is on */
1029 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1031 /* Schedule NAPI bh */
1032 napi_schedule_irqoff(&priv->napi);
1037 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1039 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[priv->rx_pointer];
1041 /* Do we have a packet ? */
1042 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1045 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1047 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1051 /* Handle TX completions */
1052 if (ftgmac100_tx_buf_cleanable(priv))
1053 ftgmac100_tx_complete(priv);
1055 /* Handle RX packets */
1057 more = ftgmac100_rx_packet(priv, &work_done);
1058 } while (more && work_done < budget);
1061 /* The interrupt is telling us to kick the MAC back to life
1062 * after an RX overflow
1064 if (unlikely(priv->need_mac_restart)) {
1065 ftgmac100_start_hw(priv);
1067 /* Re-enable "bad" interrupts */
1068 iowrite32(FTGMAC100_INT_BAD,
1069 priv->base + FTGMAC100_OFFSET_IER);
1072 /* As long as we are waiting for transmit packets to be
1073 * completed we keep NAPI going
1075 if (ftgmac100_tx_buf_cleanable(priv))
1078 if (work_done < budget) {
1079 /* We are about to re-enable all interrupts. However
1080 * the HW has been latching RX/TX packet interrupts while
1081 * they were masked. So we clear them first, then we need
1082 * to re-check if there's something to process
1084 iowrite32(FTGMAC100_INT_RXTX,
1085 priv->base + FTGMAC100_OFFSET_ISR);
1086 if (ftgmac100_check_rx(priv) ||
1087 ftgmac100_tx_buf_cleanable(priv))
1090 /* deschedule NAPI */
1091 napi_complete(napi);
1093 /* enable all interrupts */
1094 iowrite32(FTGMAC100_INT_ALL,
1095 priv->base + FTGMAC100_OFFSET_IER);
1101 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1105 /* Re-init descriptors (adjust queue sizes) */
1106 ftgmac100_init_rings(priv);
1108 /* Realloc rx descriptors */
1109 err = ftgmac100_alloc_rx_buffers(priv);
1110 if (err && !ignore_alloc_err)
1113 /* Reinit and restart HW */
1114 ftgmac100_init_hw(priv);
1115 ftgmac100_start_hw(priv);
1117 /* Re-enable the device */
1118 napi_enable(&priv->napi);
1119 netif_start_queue(priv->netdev);
1121 /* Enable all interrupts */
1122 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1127 static void ftgmac100_reset_task(struct work_struct *work)
1129 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1131 struct net_device *netdev = priv->netdev;
1134 netdev_dbg(netdev, "Resetting NIC...\n");
1136 /* Lock the world */
1139 mutex_lock(&netdev->phydev->lock);
1141 mutex_lock(&priv->mii_bus->mdio_lock);
1144 /* Check if the interface is still up */
1145 if (!netif_running(netdev))
1148 /* Stop the network stack */
1149 netif_trans_update(netdev);
1150 napi_disable(&priv->napi);
1151 netif_tx_disable(netdev);
1153 /* Stop and reset the MAC */
1154 ftgmac100_stop_hw(priv);
1155 err = ftgmac100_reset_and_config_mac(priv);
1157 /* Not much we can do ... it might come back... */
1158 netdev_err(netdev, "attempting to continue...\n");
1161 /* Free all rx and tx buffers */
1162 ftgmac100_free_buffers(priv);
1164 /* Setup everything again and restart chip */
1165 ftgmac100_init_all(priv, true);
1167 netdev_dbg(netdev, "Reset done !\n");
1170 mutex_unlock(&priv->mii_bus->mdio_lock);
1172 mutex_unlock(&netdev->phydev->lock);
1176 static int ftgmac100_open(struct net_device *netdev)
1178 struct ftgmac100 *priv = netdev_priv(netdev);
1181 /* Allocate ring buffers */
1182 err = ftgmac100_alloc_rings(priv);
1184 netdev_err(netdev, "Failed to allocate descriptors\n");
1188 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1190 * Otherwise we leave it set to 0 (no link), the link
1191 * message from the PHY layer will handle setting it up to
1192 * something else if needed.
1194 if (priv->use_ncsi) {
1195 priv->cur_duplex = DUPLEX_FULL;
1196 priv->cur_speed = SPEED_100;
1198 priv->cur_duplex = 0;
1199 priv->cur_speed = 0;
1202 /* Reset the hardware */
1203 err = ftgmac100_reset_and_config_mac(priv);
1207 /* Initialize NAPI */
1208 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1210 /* Grab our interrupt */
1211 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1213 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1217 /* Start things up */
1218 err = ftgmac100_init_all(priv, false);
1220 netdev_err(netdev, "Failed to allocate packet buffers\n");
1224 if (netdev->phydev) {
1225 /* If we have a PHY, start polling */
1226 phy_start(netdev->phydev);
1227 } else if (priv->use_ncsi) {
1228 /* If using NC-SI, set our carrier on and start the stack */
1229 netif_carrier_on(netdev);
1231 /* Start the NCSI device */
1232 err = ncsi_start_dev(priv->ndev);
1240 napi_disable(&priv->napi);
1241 netif_stop_queue(netdev);
1243 ftgmac100_free_buffers(priv);
1244 free_irq(netdev->irq, netdev);
1246 netif_napi_del(&priv->napi);
1248 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1249 ftgmac100_free_rings(priv);
1253 static int ftgmac100_stop(struct net_device *netdev)
1255 struct ftgmac100 *priv = netdev_priv(netdev);
1257 /* Note about the reset task: We are called with the rtnl lock
1258 * held, so we are synchronized against the core of the reset
1259 * task. We must not try to synchronously cancel it otherwise
1260 * we can deadlock. But since it will test for netif_running()
1261 * which has already been cleared by the net core, we don't
1262 * anything special to do.
1265 /* disable all interrupts */
1266 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1268 netif_stop_queue(netdev);
1269 napi_disable(&priv->napi);
1270 netif_napi_del(&priv->napi);
1272 phy_stop(netdev->phydev);
1273 else if (priv->use_ncsi)
1274 ncsi_stop_dev(priv->ndev);
1276 ftgmac100_stop_hw(priv);
1277 free_irq(netdev->irq, netdev);
1278 ftgmac100_free_buffers(priv);
1279 ftgmac100_free_rings(priv);
1285 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1287 if (!netdev->phydev)
1290 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1293 static void ftgmac100_tx_timeout(struct net_device *netdev)
1295 struct ftgmac100 *priv = netdev_priv(netdev);
1297 /* Disable all interrupts */
1298 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1300 /* Do the reset outside of interrupt context */
1301 schedule_work(&priv->reset_task);
1304 static const struct net_device_ops ftgmac100_netdev_ops = {
1305 .ndo_open = ftgmac100_open,
1306 .ndo_stop = ftgmac100_stop,
1307 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1308 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1309 .ndo_validate_addr = eth_validate_addr,
1310 .ndo_do_ioctl = ftgmac100_do_ioctl,
1311 .ndo_tx_timeout = ftgmac100_tx_timeout,
1314 static int ftgmac100_setup_mdio(struct net_device *netdev)
1316 struct ftgmac100 *priv = netdev_priv(netdev);
1317 struct platform_device *pdev = to_platform_device(priv->dev);
1321 /* initialize mdio bus */
1322 priv->mii_bus = mdiobus_alloc();
1326 if (priv->is_aspeed) {
1327 /* This driver supports the old MDIO interface */
1328 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1329 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1330 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1333 priv->mii_bus->name = "ftgmac100_mdio";
1334 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1335 pdev->name, pdev->id);
1336 priv->mii_bus->priv = priv->netdev;
1337 priv->mii_bus->read = ftgmac100_mdiobus_read;
1338 priv->mii_bus->write = ftgmac100_mdiobus_write;
1340 for (i = 0; i < PHY_MAX_ADDR; i++)
1341 priv->mii_bus->irq[i] = PHY_POLL;
1343 err = mdiobus_register(priv->mii_bus);
1345 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1346 goto err_register_mdiobus;
1349 err = ftgmac100_mii_probe(priv);
1351 dev_err(priv->dev, "MII Probe failed!\n");
1358 mdiobus_unregister(priv->mii_bus);
1359 err_register_mdiobus:
1360 mdiobus_free(priv->mii_bus);
1364 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1366 struct ftgmac100 *priv = netdev_priv(netdev);
1368 if (!netdev->phydev)
1371 phy_disconnect(netdev->phydev);
1372 mdiobus_unregister(priv->mii_bus);
1373 mdiobus_free(priv->mii_bus);
1376 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1378 if (unlikely(nd->state != ncsi_dev_state_functional))
1381 netdev_info(nd->dev, "NCSI interface %s\n",
1382 nd->link_up ? "up" : "down");
1385 static int ftgmac100_probe(struct platform_device *pdev)
1387 struct resource *res;
1389 struct net_device *netdev;
1390 struct ftgmac100 *priv;
1391 struct device_node *np;
1397 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1401 irq = platform_get_irq(pdev, 0);
1405 /* setup net_device */
1406 netdev = alloc_etherdev(sizeof(*priv));
1409 goto err_alloc_etherdev;
1412 SET_NETDEV_DEV(netdev, &pdev->dev);
1414 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1415 netdev->netdev_ops = &ftgmac100_netdev_ops;
1416 netdev->watchdog_timeo = 5 * HZ;
1418 platform_set_drvdata(pdev, netdev);
1420 /* setup private data */
1421 priv = netdev_priv(netdev);
1422 priv->netdev = netdev;
1423 priv->dev = &pdev->dev;
1424 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1427 priv->res = request_mem_region(res->start, resource_size(res),
1428 dev_name(&pdev->dev));
1430 dev_err(&pdev->dev, "Could not reserve memory region\n");
1435 priv->base = ioremap(res->start, resource_size(res));
1437 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1444 /* MAC address from chip or random one */
1445 ftgmac100_setup_mac(priv);
1447 np = pdev->dev.of_node;
1448 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1449 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1450 priv->rxdes0_edorr_mask = BIT(30);
1451 priv->txdes0_edotr_mask = BIT(30);
1452 priv->is_aspeed = true;
1454 priv->rxdes0_edorr_mask = BIT(15);
1455 priv->txdes0_edotr_mask = BIT(15);
1458 if (np && of_get_property(np, "use-ncsi", NULL)) {
1459 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1460 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1464 dev_info(&pdev->dev, "Using NCSI interface\n");
1465 priv->use_ncsi = true;
1466 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1470 priv->use_ncsi = false;
1471 err = ftgmac100_setup_mdio(netdev);
1473 goto err_setup_mdio;
1476 /* We have to disable on-chip IP checksum functionality
1477 * when NCSI is enabled on the interface. It doesn't work
1480 netdev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1481 NETIF_F_GRO | NETIF_F_SG;
1482 if (priv->use_ncsi &&
1483 of_get_property(np, "no-hw-checksum", NULL))
1484 netdev->features &= ~NETIF_F_HW_CSUM;
1486 /* register network device */
1487 err = register_netdev(netdev);
1489 dev_err(&pdev->dev, "Failed to register netdev\n");
1490 goto err_register_netdev;
1493 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1498 err_register_netdev:
1499 ftgmac100_destroy_mdio(netdev);
1501 iounmap(priv->base);
1503 release_resource(priv->res);
1505 netif_napi_del(&priv->napi);
1506 free_netdev(netdev);
1511 static int ftgmac100_remove(struct platform_device *pdev)
1513 struct net_device *netdev;
1514 struct ftgmac100 *priv;
1516 netdev = platform_get_drvdata(pdev);
1517 priv = netdev_priv(netdev);
1519 unregister_netdev(netdev);
1521 /* There's a small chance the reset task will have been re-queued,
1522 * during stop, make sure it's gone before we free the structure.
1524 cancel_work_sync(&priv->reset_task);
1526 ftgmac100_destroy_mdio(netdev);
1528 iounmap(priv->base);
1529 release_resource(priv->res);
1531 netif_napi_del(&priv->napi);
1532 free_netdev(netdev);
1536 static const struct of_device_id ftgmac100_of_match[] = {
1537 { .compatible = "faraday,ftgmac100" },
1540 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1542 static struct platform_driver ftgmac100_driver = {
1543 .probe = ftgmac100_probe,
1544 .remove = ftgmac100_remove,
1547 .of_match_table = ftgmac100_of_match,
1550 module_platform_driver(ftgmac100_driver);
1552 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1553 MODULE_DESCRIPTION("FTGMAC100 driver");
1554 MODULE_LICENSE("GPL");