2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/regulator/consumer.h>
54 #include <asm/cacheflush.h>
57 #include <asm/coldfire.h>
58 #include <asm/mcfsim.h>
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
66 #define FEC_ALIGNMENT 0x3
69 #define DRIVER_NAME "fec"
71 /* Controller is ENET-MAC */
72 #define FEC_QUIRK_ENET_MAC (1 << 0)
73 /* Controller needs driver to swap frame */
74 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
75 /* Controller uses gasket */
76 #define FEC_QUIRK_USE_GASKET (1 << 2)
77 /* Controller has GBIT support */
78 #define FEC_QUIRK_HAS_GBIT (1 << 3)
80 static struct platform_device_id fec_devtype[] = {
82 /* keep it for coldfire */
87 .driver_data = FEC_QUIRK_USE_GASKET,
93 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
96 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT,
101 MODULE_DEVICE_TABLE(platform, fec_devtype);
104 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
105 IMX27_FEC, /* runs on i.mx27/35/51 */
110 static const struct of_device_id fec_dt_ids[] = {
111 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
112 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
113 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
114 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
117 MODULE_DEVICE_TABLE(of, fec_dt_ids);
119 static unsigned char macaddr[ETH_ALEN];
120 module_param_array(macaddr, byte, NULL, 0);
121 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
123 #if defined(CONFIG_M5272)
125 * Some hardware gets it MAC address out of local flash memory.
126 * if this is non-zero then assume it is the address to get MAC from.
128 #if defined(CONFIG_NETtel)
129 #define FEC_FLASHMAC 0xf0006006
130 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
131 #define FEC_FLASHMAC 0xf0006000
132 #elif defined(CONFIG_CANCam)
133 #define FEC_FLASHMAC 0xf0020000
134 #elif defined (CONFIG_M5272C3)
135 #define FEC_FLASHMAC (0xffe04000 + 4)
136 #elif defined(CONFIG_MOD5272)
137 #define FEC_FLASHMAC 0xffc0406b
139 #define FEC_FLASHMAC 0
141 #endif /* CONFIG_M5272 */
143 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
144 #error "FEC: descriptor ring size constants too large"
147 /* Interrupt events/masks. */
148 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
149 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
150 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
151 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
152 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
153 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
154 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
155 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
156 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
157 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
159 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
161 /* The FEC stores dest/src/type, data, and checksum for receive packets.
163 #define PKT_MAXBUF_SIZE 1518
164 #define PKT_MINBUF_SIZE 64
165 #define PKT_MAXBLR_SIZE 1520
168 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
169 * size bits. Other FEC hardware does not, so we need to take that into
170 * account when setting it.
172 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
173 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
174 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
176 #define OPT_FRAME_SIZE 0
179 /* FEC MII MMFR bits definition */
180 #define FEC_MMFR_ST (1 << 30)
181 #define FEC_MMFR_OP_READ (2 << 28)
182 #define FEC_MMFR_OP_WRITE (1 << 28)
183 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
184 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
185 #define FEC_MMFR_TA (2 << 16)
186 #define FEC_MMFR_DATA(v) (v & 0xffff)
188 #define FEC_MII_TIMEOUT 30000 /* us */
190 /* Transmitter timeout */
191 #define TX_TIMEOUT (2 * HZ)
195 static void *swap_buffer(void *bufaddr, int len)
198 unsigned int *buf = bufaddr;
200 for (i = 0; i < (len + 3) / 4; i++, buf++)
201 *buf = cpu_to_be32(*buf);
207 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
209 struct fec_enet_private *fep = netdev_priv(ndev);
210 const struct platform_device_id *id_entry =
211 platform_get_device_id(fep->pdev);
214 unsigned short status;
218 /* Link is down or autonegotiation is in progress. */
219 return NETDEV_TX_BUSY;
222 spin_lock_irqsave(&fep->hw_lock, flags);
223 /* Fill in a Tx ring entry */
226 status = bdp->cbd_sc;
228 if (status & BD_ENET_TX_READY) {
229 /* Ooops. All transmit buffers are full. Bail out.
230 * This should not happen, since ndev->tbusy should be set.
232 printk("%s: tx queue full!.\n", ndev->name);
233 spin_unlock_irqrestore(&fep->hw_lock, flags);
234 return NETDEV_TX_BUSY;
237 /* Clear all of the status flags */
238 status &= ~BD_ENET_TX_STATS;
240 /* Set buffer length and buffer pointer */
242 bdp->cbd_datlen = skb->len;
245 * On some FEC implementations data must be aligned on
246 * 4-byte boundaries. Use bounce buffers to copy data
247 * and get it aligned. Ugh.
249 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
251 index = bdp - fep->tx_bd_base;
252 memcpy(fep->tx_bounce[index], skb->data, skb->len);
253 bufaddr = fep->tx_bounce[index];
257 * Some design made an incorrect assumption on endian mode of
258 * the system that it's running on. As the result, driver has to
259 * swap every frame going to and coming from the controller.
261 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
262 swap_buffer(bufaddr, skb->len);
264 /* Save skb pointer */
265 fep->tx_skbuff[fep->skb_cur] = skb;
267 ndev->stats.tx_bytes += skb->len;
268 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
270 /* Push the data cache so the CPM does not get stale memory
273 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
274 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
276 /* Send it on its way. Tell FEC it's ready, interrupt when done,
277 * it's the last BD of the frame, and to put the CRC on the end.
279 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
280 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
281 bdp->cbd_sc = status;
283 #ifdef CONFIG_FEC_PTP
285 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
287 bdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
288 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
291 bdp->cbd_esc = BD_ENET_TX_INT;
294 /* Trigger transmission start */
295 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
297 /* If this was the last BD in the ring, start at the beginning again. */
298 if (status & BD_ENET_TX_WRAP)
299 bdp = fep->tx_bd_base;
303 if (bdp == fep->dirty_tx) {
305 netif_stop_queue(ndev);
310 skb_tx_timestamp(skb);
312 spin_unlock_irqrestore(&fep->hw_lock, flags);
317 /* This function is called to start or restart the FEC during a link
318 * change. This only happens when switching between half and full
322 fec_restart(struct net_device *ndev, int duplex)
324 struct fec_enet_private *fep = netdev_priv(ndev);
325 const struct platform_device_id *id_entry =
326 platform_get_device_id(fep->pdev);
329 u32 rcntl = OPT_FRAME_SIZE | 0x04;
330 u32 ecntl = 0x2; /* ETHEREN */
332 /* Whack a reset. We should wait for this. */
333 writel(1, fep->hwp + FEC_ECNTRL);
337 * enet-mac reset will reset mac address registers too,
338 * so need to reconfigure it.
340 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
341 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
342 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
343 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
346 /* Clear any outstanding interrupt. */
347 writel(0xffc00000, fep->hwp + FEC_IEVENT);
349 /* Reset all multicast. */
350 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
351 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
353 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
354 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
357 /* Set maximum receive buffer size. */
358 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
360 /* Set receive and transmit descriptor base. */
361 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
362 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
363 fep->hwp + FEC_X_DES_START);
365 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
366 fep->cur_rx = fep->rx_bd_base;
368 /* Reset SKB transmit buffers. */
369 fep->skb_cur = fep->skb_dirty = 0;
370 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
371 if (fep->tx_skbuff[i]) {
372 dev_kfree_skb_any(fep->tx_skbuff[i]);
373 fep->tx_skbuff[i] = NULL;
377 /* Enable MII mode */
380 writel(0x04, fep->hwp + FEC_X_CNTRL);
384 writel(0x0, fep->hwp + FEC_X_CNTRL);
387 fep->full_duplex = duplex;
390 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
393 * The phy interface and speed need to get configured
394 * differently on enet-mac.
396 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
397 /* Enable flow control and length check */
398 rcntl |= 0x40000000 | 0x00000020;
400 /* RGMII, RMII or MII */
401 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
403 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
408 /* 1G, 100M or 10M */
410 if (fep->phy_dev->speed == SPEED_1000)
412 else if (fep->phy_dev->speed == SPEED_100)
418 #ifdef FEC_MIIGSK_ENR
419 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
421 /* disable the gasket and wait */
422 writel(0, fep->hwp + FEC_MIIGSK_ENR);
423 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
427 * configure the gasket:
428 * RMII, 50 MHz, no loopback, no echo
429 * MII, 25 MHz, no loopback, no echo
431 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
432 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
433 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
434 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
435 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
437 /* re-enable the gasket */
438 writel(2, fep->hwp + FEC_MIIGSK_ENR);
442 writel(rcntl, fep->hwp + FEC_R_CNTRL);
444 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
445 /* enable ENET endian swap */
447 /* enable ENET store and forward mode */
448 writel(1 << 8, fep->hwp + FEC_X_WMRK);
451 #ifdef CONFIG_FEC_PTP
455 /* And last, enable the transmit and receive processing */
456 writel(ecntl, fep->hwp + FEC_ECNTRL);
457 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
459 #ifdef CONFIG_FEC_PTP
460 fec_ptp_start_cyclecounter(ndev);
462 /* Enable interrupts we wish to service */
463 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
467 fec_stop(struct net_device *ndev)
469 struct fec_enet_private *fep = netdev_priv(ndev);
470 const struct platform_device_id *id_entry =
471 platform_get_device_id(fep->pdev);
472 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
474 /* We cannot expect a graceful transmit stop without link !!! */
476 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
478 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
479 printk("fec_stop : Graceful transmit stop did not complete !\n");
482 /* Whack a reset. We should wait for this. */
483 writel(1, fep->hwp + FEC_ECNTRL);
485 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
486 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
488 /* We have to keep ENET enabled to have MII interrupt stay working */
489 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
490 writel(2, fep->hwp + FEC_ECNTRL);
491 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
497 fec_timeout(struct net_device *ndev)
499 struct fec_enet_private *fep = netdev_priv(ndev);
501 ndev->stats.tx_errors++;
503 fec_restart(ndev, fep->full_duplex);
504 netif_wake_queue(ndev);
508 fec_enet_tx(struct net_device *ndev)
510 struct fec_enet_private *fep;
512 unsigned short status;
515 fep = netdev_priv(ndev);
516 spin_lock(&fep->hw_lock);
519 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
520 if (bdp == fep->cur_tx && fep->tx_full == 0)
523 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
524 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
525 bdp->cbd_bufaddr = 0;
527 skb = fep->tx_skbuff[fep->skb_dirty];
528 /* Check for errors. */
529 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
530 BD_ENET_TX_RL | BD_ENET_TX_UN |
532 ndev->stats.tx_errors++;
533 if (status & BD_ENET_TX_HB) /* No heartbeat */
534 ndev->stats.tx_heartbeat_errors++;
535 if (status & BD_ENET_TX_LC) /* Late collision */
536 ndev->stats.tx_window_errors++;
537 if (status & BD_ENET_TX_RL) /* Retrans limit */
538 ndev->stats.tx_aborted_errors++;
539 if (status & BD_ENET_TX_UN) /* Underrun */
540 ndev->stats.tx_fifo_errors++;
541 if (status & BD_ENET_TX_CSL) /* Carrier lost */
542 ndev->stats.tx_carrier_errors++;
544 ndev->stats.tx_packets++;
547 #ifdef CONFIG_FEC_PTP
548 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
549 struct skb_shared_hwtstamps shhwtstamps;
552 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
553 spin_lock_irqsave(&fep->tmreg_lock, flags);
554 shhwtstamps.hwtstamp = ns_to_ktime(
555 timecounter_cyc2time(&fep->tc, bdp->ts));
556 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
557 skb_tstamp_tx(skb, &shhwtstamps);
560 if (status & BD_ENET_TX_READY)
561 printk("HEY! Enet xmit interrupt and TX_READY.\n");
563 /* Deferred means some collisions occurred during transmit,
564 * but we eventually sent the packet OK.
566 if (status & BD_ENET_TX_DEF)
567 ndev->stats.collisions++;
569 /* Free the sk buffer associated with this last transmit */
570 dev_kfree_skb_any(skb);
571 fep->tx_skbuff[fep->skb_dirty] = NULL;
572 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
574 /* Update pointer to next buffer descriptor to be transmitted */
575 if (status & BD_ENET_TX_WRAP)
576 bdp = fep->tx_bd_base;
580 /* Since we have freed up a buffer, the ring is no longer full
584 if (netif_queue_stopped(ndev))
585 netif_wake_queue(ndev);
589 spin_unlock(&fep->hw_lock);
593 /* During a receive, the cur_rx points to the current incoming buffer.
594 * When we update through the ring, if the next incoming buffer has
595 * not been given to the system, we just set the empty indicator,
596 * effectively tossing the packet.
599 fec_enet_rx(struct net_device *ndev)
601 struct fec_enet_private *fep = netdev_priv(ndev);
602 const struct platform_device_id *id_entry =
603 platform_get_device_id(fep->pdev);
605 unsigned short status;
614 spin_lock(&fep->hw_lock);
616 /* First, grab all of the stats for the incoming packet.
617 * These get messed up if we get called due to a busy condition.
621 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
623 /* Since we have allocated space to hold a complete frame,
624 * the last indicator should be set.
626 if ((status & BD_ENET_RX_LAST) == 0)
627 printk("FEC ENET: rcv is not +last\n");
630 goto rx_processing_done;
632 /* Check for errors. */
633 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
634 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
635 ndev->stats.rx_errors++;
636 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
637 /* Frame too long or too short. */
638 ndev->stats.rx_length_errors++;
640 if (status & BD_ENET_RX_NO) /* Frame alignment */
641 ndev->stats.rx_frame_errors++;
642 if (status & BD_ENET_RX_CR) /* CRC Error */
643 ndev->stats.rx_crc_errors++;
644 if (status & BD_ENET_RX_OV) /* FIFO overrun */
645 ndev->stats.rx_fifo_errors++;
648 /* Report late collisions as a frame error.
649 * On this error, the BD is closed, but we don't know what we
650 * have in the buffer. So, just drop this frame on the floor.
652 if (status & BD_ENET_RX_CL) {
653 ndev->stats.rx_errors++;
654 ndev->stats.rx_frame_errors++;
655 goto rx_processing_done;
658 /* Process the incoming frame. */
659 ndev->stats.rx_packets++;
660 pkt_len = bdp->cbd_datlen;
661 ndev->stats.rx_bytes += pkt_len;
662 data = (__u8*)__va(bdp->cbd_bufaddr);
664 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
665 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
667 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
668 swap_buffer(data, pkt_len);
670 /* This does 16 byte alignment, exactly what we need.
671 * The packet length includes FCS, but we don't want to
672 * include that when passing upstream as it messes up
673 * bridging applications.
675 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
677 if (unlikely(!skb)) {
678 printk("%s: Memory squeeze, dropping packet.\n",
680 ndev->stats.rx_dropped++;
682 skb_reserve(skb, NET_IP_ALIGN);
683 skb_put(skb, pkt_len - 4); /* Make room */
684 skb_copy_to_linear_data(skb, data, pkt_len - 4);
685 skb->protocol = eth_type_trans(skb, ndev);
686 #ifdef CONFIG_FEC_PTP
687 /* Get receive timestamp from the skb */
688 if (fep->hwts_rx_en) {
689 struct skb_shared_hwtstamps *shhwtstamps =
693 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
695 spin_lock_irqsave(&fep->tmreg_lock, flags);
696 shhwtstamps->hwtstamp = ns_to_ktime(
697 timecounter_cyc2time(&fep->tc, bdp->ts));
698 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
701 if (!skb_defer_rx_timestamp(skb))
705 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
706 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
708 /* Clear the status flags for this buffer */
709 status &= ~BD_ENET_RX_STATS;
711 /* Mark the buffer empty */
712 status |= BD_ENET_RX_EMPTY;
713 bdp->cbd_sc = status;
715 #ifdef CONFIG_FEC_PTP
716 bdp->cbd_esc = BD_ENET_RX_INT;
721 /* Update BD pointer to next entry */
722 if (status & BD_ENET_RX_WRAP)
723 bdp = fep->rx_bd_base;
726 /* Doing this here will keep the FEC running while we process
727 * incoming frames. On a heavily loaded network, we should be
728 * able to keep up at the expense of system resources.
730 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
734 spin_unlock(&fep->hw_lock);
738 fec_enet_interrupt(int irq, void *dev_id)
740 struct net_device *ndev = dev_id;
741 struct fec_enet_private *fep = netdev_priv(ndev);
743 irqreturn_t ret = IRQ_NONE;
746 int_events = readl(fep->hwp + FEC_IEVENT);
747 writel(int_events, fep->hwp + FEC_IEVENT);
749 if (int_events & FEC_ENET_RXF) {
754 /* Transmit OK, or non-fatal error. Update the buffer
755 * descriptors. FEC handles all errors, we just discover
756 * them as part of the transmit process.
758 if (int_events & FEC_ENET_TXF) {
763 if (int_events & FEC_ENET_MII) {
765 complete(&fep->mdio_done);
767 } while (int_events);
774 /* ------------------------------------------------------------------------- */
775 static void __inline__ fec_get_mac(struct net_device *ndev)
777 struct fec_enet_private *fep = netdev_priv(ndev);
778 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
779 unsigned char *iap, tmpaddr[ETH_ALEN];
782 * try to get mac address in following order:
784 * 1) module parameter via kernel command line in form
785 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
791 * 2) from device tree data
793 if (!is_valid_ether_addr(iap)) {
794 struct device_node *np = fep->pdev->dev.of_node;
796 const char *mac = of_get_mac_address(np);
798 iap = (unsigned char *) mac;
804 * 3) from flash or fuse (via platform data)
806 if (!is_valid_ether_addr(iap)) {
809 iap = (unsigned char *)FEC_FLASHMAC;
812 iap = (unsigned char *)&pdata->mac;
817 * 4) FEC mac registers set by bootloader
819 if (!is_valid_ether_addr(iap)) {
820 *((unsigned long *) &tmpaddr[0]) =
821 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
822 *((unsigned short *) &tmpaddr[4]) =
823 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
827 memcpy(ndev->dev_addr, iap, ETH_ALEN);
829 /* Adjust MAC if using macaddr */
831 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
834 /* ------------------------------------------------------------------------- */
839 static void fec_enet_adjust_link(struct net_device *ndev)
841 struct fec_enet_private *fep = netdev_priv(ndev);
842 struct phy_device *phy_dev = fep->phy_dev;
845 int status_change = 0;
847 spin_lock_irqsave(&fep->hw_lock, flags);
849 /* Prevent a state halted on mii error */
850 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
851 phy_dev->state = PHY_RESUMING;
855 /* Duplex link change */
857 if (fep->full_duplex != phy_dev->duplex) {
858 fec_restart(ndev, phy_dev->duplex);
859 /* prevent unnecessary second fec_restart() below */
860 fep->link = phy_dev->link;
865 /* Link on or off change */
866 if (phy_dev->link != fep->link) {
867 fep->link = phy_dev->link;
869 fec_restart(ndev, phy_dev->duplex);
876 spin_unlock_irqrestore(&fep->hw_lock, flags);
879 phy_print_status(phy_dev);
882 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
884 struct fec_enet_private *fep = bus->priv;
885 unsigned long time_left;
887 fep->mii_timeout = 0;
888 init_completion(&fep->mdio_done);
890 /* start a read op */
891 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
892 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
893 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
895 /* wait for end of transfer */
896 time_left = wait_for_completion_timeout(&fep->mdio_done,
897 usecs_to_jiffies(FEC_MII_TIMEOUT));
898 if (time_left == 0) {
899 fep->mii_timeout = 1;
900 printk(KERN_ERR "FEC: MDIO read timeout\n");
905 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
908 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
911 struct fec_enet_private *fep = bus->priv;
912 unsigned long time_left;
914 fep->mii_timeout = 0;
915 init_completion(&fep->mdio_done);
917 /* start a write op */
918 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
919 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
920 FEC_MMFR_TA | FEC_MMFR_DATA(value),
921 fep->hwp + FEC_MII_DATA);
923 /* wait for end of transfer */
924 time_left = wait_for_completion_timeout(&fep->mdio_done,
925 usecs_to_jiffies(FEC_MII_TIMEOUT));
926 if (time_left == 0) {
927 fep->mii_timeout = 1;
928 printk(KERN_ERR "FEC: MDIO write timeout\n");
935 static int fec_enet_mdio_reset(struct mii_bus *bus)
940 static int fec_enet_mii_probe(struct net_device *ndev)
942 struct fec_enet_private *fep = netdev_priv(ndev);
943 const struct platform_device_id *id_entry =
944 platform_get_device_id(fep->pdev);
945 struct phy_device *phy_dev = NULL;
946 char mdio_bus_id[MII_BUS_ID_SIZE];
947 char phy_name[MII_BUS_ID_SIZE + 3];
949 int dev_id = fep->dev_id;
953 /* check for attached phy */
954 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
955 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
957 if (fep->mii_bus->phy_map[phy_id] == NULL)
959 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
963 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
967 if (phy_id >= PHY_MAX_ADDR) {
969 "%s: no PHY, assuming direct connection to switch\n",
971 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
975 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
976 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
978 if (IS_ERR(phy_dev)) {
979 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
980 return PTR_ERR(phy_dev);
983 /* mask with MAC supported features */
984 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT)
985 phy_dev->supported &= PHY_GBIT_FEATURES;
987 phy_dev->supported &= PHY_BASIC_FEATURES;
989 phy_dev->advertising = phy_dev->supported;
991 fep->phy_dev = phy_dev;
993 fep->full_duplex = 0;
996 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
998 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1004 static int fec_enet_mii_init(struct platform_device *pdev)
1006 static struct mii_bus *fec0_mii_bus;
1007 struct net_device *ndev = platform_get_drvdata(pdev);
1008 struct fec_enet_private *fep = netdev_priv(ndev);
1009 const struct platform_device_id *id_entry =
1010 platform_get_device_id(fep->pdev);
1011 int err = -ENXIO, i;
1014 * The dual fec interfaces are not equivalent with enet-mac.
1015 * Here are the differences:
1017 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1018 * - fec0 acts as the 1588 time master while fec1 is slave
1019 * - external phys can only be configured by fec0
1021 * That is to say fec1 can not work independently. It only works
1022 * when fec0 is working. The reason behind this design is that the
1023 * second interface is added primarily for Switch mode.
1025 * Because of the last point above, both phys are attached on fec0
1026 * mdio interface in board design, and need to be configured by
1029 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1030 /* fec1 uses fec0 mii_bus */
1031 if (mii_cnt && fec0_mii_bus) {
1032 fep->mii_bus = fec0_mii_bus;
1039 fep->mii_timeout = 0;
1042 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1044 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1045 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1046 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1049 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1050 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1052 fep->phy_speed <<= 1;
1053 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1055 fep->mii_bus = mdiobus_alloc();
1056 if (fep->mii_bus == NULL) {
1061 fep->mii_bus->name = "fec_enet_mii_bus";
1062 fep->mii_bus->read = fec_enet_mdio_read;
1063 fep->mii_bus->write = fec_enet_mdio_write;
1064 fep->mii_bus->reset = fec_enet_mdio_reset;
1065 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1066 pdev->name, fep->dev_id + 1);
1067 fep->mii_bus->priv = fep;
1068 fep->mii_bus->parent = &pdev->dev;
1070 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1071 if (!fep->mii_bus->irq) {
1073 goto err_out_free_mdiobus;
1076 for (i = 0; i < PHY_MAX_ADDR; i++)
1077 fep->mii_bus->irq[i] = PHY_POLL;
1079 if (mdiobus_register(fep->mii_bus))
1080 goto err_out_free_mdio_irq;
1084 /* save fec0 mii_bus */
1085 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1086 fec0_mii_bus = fep->mii_bus;
1090 err_out_free_mdio_irq:
1091 kfree(fep->mii_bus->irq);
1092 err_out_free_mdiobus:
1093 mdiobus_free(fep->mii_bus);
1098 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1100 if (--mii_cnt == 0) {
1101 mdiobus_unregister(fep->mii_bus);
1102 kfree(fep->mii_bus->irq);
1103 mdiobus_free(fep->mii_bus);
1107 static int fec_enet_get_settings(struct net_device *ndev,
1108 struct ethtool_cmd *cmd)
1110 struct fec_enet_private *fep = netdev_priv(ndev);
1111 struct phy_device *phydev = fep->phy_dev;
1116 return phy_ethtool_gset(phydev, cmd);
1119 static int fec_enet_set_settings(struct net_device *ndev,
1120 struct ethtool_cmd *cmd)
1122 struct fec_enet_private *fep = netdev_priv(ndev);
1123 struct phy_device *phydev = fep->phy_dev;
1128 return phy_ethtool_sset(phydev, cmd);
1131 static void fec_enet_get_drvinfo(struct net_device *ndev,
1132 struct ethtool_drvinfo *info)
1134 struct fec_enet_private *fep = netdev_priv(ndev);
1136 strcpy(info->driver, fep->pdev->dev.driver->name);
1137 strcpy(info->version, "Revision: 1.0");
1138 strcpy(info->bus_info, dev_name(&ndev->dev));
1141 static const struct ethtool_ops fec_enet_ethtool_ops = {
1142 .get_settings = fec_enet_get_settings,
1143 .set_settings = fec_enet_set_settings,
1144 .get_drvinfo = fec_enet_get_drvinfo,
1145 .get_link = ethtool_op_get_link,
1146 .get_ts_info = ethtool_op_get_ts_info,
1149 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1151 struct fec_enet_private *fep = netdev_priv(ndev);
1152 struct phy_device *phydev = fep->phy_dev;
1154 if (!netif_running(ndev))
1160 #ifdef CONFIG_FEC_PTP
1161 if (cmd == SIOCSHWTSTAMP)
1162 return fec_ptp_ioctl(ndev, rq, cmd);
1164 return phy_mii_ioctl(phydev, rq, cmd);
1167 static void fec_enet_free_buffers(struct net_device *ndev)
1169 struct fec_enet_private *fep = netdev_priv(ndev);
1171 struct sk_buff *skb;
1172 struct bufdesc *bdp;
1174 bdp = fep->rx_bd_base;
1175 for (i = 0; i < RX_RING_SIZE; i++) {
1176 skb = fep->rx_skbuff[i];
1178 if (bdp->cbd_bufaddr)
1179 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1180 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1186 bdp = fep->tx_bd_base;
1187 for (i = 0; i < TX_RING_SIZE; i++)
1188 kfree(fep->tx_bounce[i]);
1191 static int fec_enet_alloc_buffers(struct net_device *ndev)
1193 struct fec_enet_private *fep = netdev_priv(ndev);
1195 struct sk_buff *skb;
1196 struct bufdesc *bdp;
1198 bdp = fep->rx_bd_base;
1199 for (i = 0; i < RX_RING_SIZE; i++) {
1200 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1202 fec_enet_free_buffers(ndev);
1205 fep->rx_skbuff[i] = skb;
1207 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1208 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1209 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1210 #ifdef CONFIG_FEC_PTP
1211 bdp->cbd_esc = BD_ENET_RX_INT;
1216 /* Set the last buffer to wrap. */
1218 bdp->cbd_sc |= BD_SC_WRAP;
1220 bdp = fep->tx_bd_base;
1221 for (i = 0; i < TX_RING_SIZE; i++) {
1222 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1225 bdp->cbd_bufaddr = 0;
1227 #ifdef CONFIG_FEC_PTP
1228 bdp->cbd_esc = BD_ENET_RX_INT;
1233 /* Set the last buffer to wrap. */
1235 bdp->cbd_sc |= BD_SC_WRAP;
1241 fec_enet_open(struct net_device *ndev)
1243 struct fec_enet_private *fep = netdev_priv(ndev);
1246 /* I should reset the ring buffers here, but I don't yet know
1247 * a simple way to do that.
1250 ret = fec_enet_alloc_buffers(ndev);
1254 /* Probe and connect to PHY when open the interface */
1255 ret = fec_enet_mii_probe(ndev);
1257 fec_enet_free_buffers(ndev);
1260 phy_start(fep->phy_dev);
1261 netif_start_queue(ndev);
1267 fec_enet_close(struct net_device *ndev)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1271 /* Don't know what to do yet. */
1273 netif_stop_queue(ndev);
1277 phy_stop(fep->phy_dev);
1278 phy_disconnect(fep->phy_dev);
1281 fec_enet_free_buffers(ndev);
1286 /* Set or clear the multicast filter for this adaptor.
1287 * Skeleton taken from sunlance driver.
1288 * The CPM Ethernet implementation allows Multicast as well as individual
1289 * MAC address filtering. Some of the drivers check to make sure it is
1290 * a group multicast address, and discard those that are not. I guess I
1291 * will do the same for now, but just remove the test if you want
1292 * individual filtering as well (do the upper net layers want or support
1293 * this kind of feature?).
1296 #define HASH_BITS 6 /* #bits in hash */
1297 #define CRC32_POLY 0xEDB88320
1299 static void set_multicast_list(struct net_device *ndev)
1301 struct fec_enet_private *fep = netdev_priv(ndev);
1302 struct netdev_hw_addr *ha;
1303 unsigned int i, bit, data, crc, tmp;
1306 if (ndev->flags & IFF_PROMISC) {
1307 tmp = readl(fep->hwp + FEC_R_CNTRL);
1309 writel(tmp, fep->hwp + FEC_R_CNTRL);
1313 tmp = readl(fep->hwp + FEC_R_CNTRL);
1315 writel(tmp, fep->hwp + FEC_R_CNTRL);
1317 if (ndev->flags & IFF_ALLMULTI) {
1318 /* Catch all multicast addresses, so set the
1321 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1322 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1327 /* Clear filter and add the addresses in hash register
1329 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1330 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1332 netdev_for_each_mc_addr(ha, ndev) {
1333 /* calculate crc32 value of mac address */
1336 for (i = 0; i < ndev->addr_len; i++) {
1338 for (bit = 0; bit < 8; bit++, data >>= 1) {
1340 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1344 /* only upper 6 bits (HASH_BITS) are used
1345 * which point to specific bit in he hash registers
1347 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1350 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1351 tmp |= 1 << (hash - 32);
1352 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1354 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1356 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1361 /* Set a MAC change in hardware. */
1363 fec_set_mac_address(struct net_device *ndev, void *p)
1365 struct fec_enet_private *fep = netdev_priv(ndev);
1366 struct sockaddr *addr = p;
1368 if (!is_valid_ether_addr(addr->sa_data))
1369 return -EADDRNOTAVAIL;
1371 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1373 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1374 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1375 fep->hwp + FEC_ADDR_LOW);
1376 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1377 fep->hwp + FEC_ADDR_HIGH);
1381 #ifdef CONFIG_NET_POLL_CONTROLLER
1383 * fec_poll_controller - FEC Poll controller function
1384 * @dev: The FEC network adapter
1386 * Polled functionality used by netconsole and others in non interrupt mode
1389 void fec_poll_controller(struct net_device *dev)
1392 struct fec_enet_private *fep = netdev_priv(dev);
1394 for (i = 0; i < FEC_IRQ_NUM; i++) {
1395 if (fep->irq[i] > 0) {
1396 disable_irq(fep->irq[i]);
1397 fec_enet_interrupt(fep->irq[i], dev);
1398 enable_irq(fep->irq[i]);
1404 static const struct net_device_ops fec_netdev_ops = {
1405 .ndo_open = fec_enet_open,
1406 .ndo_stop = fec_enet_close,
1407 .ndo_start_xmit = fec_enet_start_xmit,
1408 .ndo_set_rx_mode = set_multicast_list,
1409 .ndo_change_mtu = eth_change_mtu,
1410 .ndo_validate_addr = eth_validate_addr,
1411 .ndo_tx_timeout = fec_timeout,
1412 .ndo_set_mac_address = fec_set_mac_address,
1413 .ndo_do_ioctl = fec_enet_ioctl,
1414 #ifdef CONFIG_NET_POLL_CONTROLLER
1415 .ndo_poll_controller = fec_poll_controller,
1420 * XXX: We need to clean up on failure exits here.
1423 static int fec_enet_init(struct net_device *ndev)
1425 struct fec_enet_private *fep = netdev_priv(ndev);
1426 struct bufdesc *cbd_base;
1427 struct bufdesc *bdp;
1430 /* Allocate memory for buffer descriptors. */
1431 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1434 printk("FEC: allocate descriptor memory failed?\n");
1438 spin_lock_init(&fep->hw_lock);
1442 /* Get the Ethernet address */
1445 /* Set receive and transmit descriptor base. */
1446 fep->rx_bd_base = cbd_base;
1447 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1449 /* The FEC Ethernet specific entries in the device structure */
1450 ndev->watchdog_timeo = TX_TIMEOUT;
1451 ndev->netdev_ops = &fec_netdev_ops;
1452 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1454 /* Initialize the receive buffer descriptors. */
1455 bdp = fep->rx_bd_base;
1456 for (i = 0; i < RX_RING_SIZE; i++) {
1458 /* Initialize the BD for every fragment in the page. */
1463 /* Set the last buffer to wrap */
1465 bdp->cbd_sc |= BD_SC_WRAP;
1467 /* ...and the same for transmit */
1468 bdp = fep->tx_bd_base;
1469 for (i = 0; i < TX_RING_SIZE; i++) {
1471 /* Initialize the BD for every fragment in the page. */
1473 bdp->cbd_bufaddr = 0;
1477 /* Set the last buffer to wrap */
1479 bdp->cbd_sc |= BD_SC_WRAP;
1481 fec_restart(ndev, 0);
1487 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1489 struct device_node *np = pdev->dev.of_node;
1492 return of_get_phy_mode(np);
1497 static void fec_reset_phy(struct platform_device *pdev)
1501 struct device_node *np = pdev->dev.of_node;
1506 of_property_read_u32(np, "phy-reset-duration", &msec);
1507 /* A sane reset duration should not be longer than 1s */
1511 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1512 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1513 GPIOF_OUT_INIT_LOW, "phy-reset");
1515 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err);
1519 gpio_set_value(phy_reset, 1);
1521 #else /* CONFIG_OF */
1522 static inline int fec_get_phy_mode_dt(struct platform_device *pdev)
1527 static inline void fec_reset_phy(struct platform_device *pdev)
1530 * In case of platform probe, the reset has been done
1534 #endif /* CONFIG_OF */
1537 fec_probe(struct platform_device *pdev)
1539 struct fec_enet_private *fep;
1540 struct fec_platform_data *pdata;
1541 struct net_device *ndev;
1542 int i, irq, ret = 0;
1544 const struct of_device_id *of_id;
1546 struct pinctrl *pinctrl;
1547 struct regulator *reg_phy;
1549 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1551 pdev->id_entry = of_id->data;
1553 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1557 r = request_mem_region(r->start, resource_size(r), pdev->name);
1561 /* Init network device */
1562 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1565 goto failed_alloc_etherdev;
1568 SET_NETDEV_DEV(ndev, &pdev->dev);
1570 /* setup board info structure */
1571 fep = netdev_priv(ndev);
1573 fep->hwp = ioremap(r->start, resource_size(r));
1575 fep->dev_id = dev_id++;
1579 goto failed_ioremap;
1582 platform_set_drvdata(pdev, ndev);
1584 ret = fec_get_phy_mode_dt(pdev);
1586 pdata = pdev->dev.platform_data;
1588 fep->phy_interface = pdata->phy;
1590 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1592 fep->phy_interface = ret;
1595 for (i = 0; i < FEC_IRQ_NUM; i++) {
1596 irq = platform_get_irq(pdev, i);
1603 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1606 irq = platform_get_irq(pdev, i);
1607 free_irq(irq, ndev);
1613 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1614 if (IS_ERR(pinctrl)) {
1615 ret = PTR_ERR(pinctrl);
1619 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1620 if (IS_ERR(fep->clk_ipg)) {
1621 ret = PTR_ERR(fep->clk_ipg);
1625 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1626 if (IS_ERR(fep->clk_ahb)) {
1627 ret = PTR_ERR(fep->clk_ahb);
1631 #ifdef CONFIG_FEC_PTP
1632 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1633 if (IS_ERR(fep->clk_ptp)) {
1634 ret = PTR_ERR(fep->clk_ptp);
1639 clk_prepare_enable(fep->clk_ahb);
1640 clk_prepare_enable(fep->clk_ipg);
1641 #ifdef CONFIG_FEC_PTP
1642 clk_prepare_enable(fep->clk_ptp);
1644 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1645 if (!IS_ERR(reg_phy)) {
1646 ret = regulator_enable(reg_phy);
1649 "Failed to enable phy regulator: %d\n", ret);
1650 goto failed_regulator;
1654 fec_reset_phy(pdev);
1656 ret = fec_enet_init(ndev);
1660 ret = fec_enet_mii_init(pdev);
1662 goto failed_mii_init;
1664 /* Carrier starts down, phylib will bring it up */
1665 netif_carrier_off(ndev);
1667 ret = register_netdev(ndev);
1669 goto failed_register;
1671 #ifdef CONFIG_FEC_PTP
1672 fec_ptp_init(ndev, pdev);
1678 fec_enet_mii_remove(fep);
1682 clk_disable_unprepare(fep->clk_ahb);
1683 clk_disable_unprepare(fep->clk_ipg);
1684 #ifdef CONFIG_FEC_PTP
1685 clk_disable_unprepare(fep->clk_ptp);
1689 for (i = 0; i < FEC_IRQ_NUM; i++) {
1690 irq = platform_get_irq(pdev, i);
1692 free_irq(irq, ndev);
1698 failed_alloc_etherdev:
1699 release_mem_region(r->start, resource_size(r));
1705 fec_drv_remove(struct platform_device *pdev)
1707 struct net_device *ndev = platform_get_drvdata(pdev);
1708 struct fec_enet_private *fep = netdev_priv(ndev);
1712 unregister_netdev(ndev);
1713 fec_enet_mii_remove(fep);
1714 for (i = 0; i < FEC_IRQ_NUM; i++) {
1715 int irq = platform_get_irq(pdev, i);
1717 free_irq(irq, ndev);
1719 #ifdef CONFIG_FEC_PTP
1720 del_timer_sync(&fep->time_keep);
1721 clk_disable_unprepare(fep->clk_ptp);
1723 ptp_clock_unregister(fep->ptp_clock);
1725 clk_disable_unprepare(fep->clk_ahb);
1726 clk_disable_unprepare(fep->clk_ipg);
1730 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1732 release_mem_region(r->start, resource_size(r));
1734 platform_set_drvdata(pdev, NULL);
1741 fec_suspend(struct device *dev)
1743 struct net_device *ndev = dev_get_drvdata(dev);
1744 struct fec_enet_private *fep = netdev_priv(ndev);
1746 if (netif_running(ndev)) {
1748 netif_device_detach(ndev);
1750 clk_disable_unprepare(fep->clk_ahb);
1751 clk_disable_unprepare(fep->clk_ipg);
1757 fec_resume(struct device *dev)
1759 struct net_device *ndev = dev_get_drvdata(dev);
1760 struct fec_enet_private *fep = netdev_priv(ndev);
1762 clk_prepare_enable(fep->clk_ahb);
1763 clk_prepare_enable(fep->clk_ipg);
1764 if (netif_running(ndev)) {
1765 fec_restart(ndev, fep->full_duplex);
1766 netif_device_attach(ndev);
1772 static const struct dev_pm_ops fec_pm_ops = {
1773 .suspend = fec_suspend,
1774 .resume = fec_resume,
1775 .freeze = fec_suspend,
1777 .poweroff = fec_suspend,
1778 .restore = fec_resume,
1782 static struct platform_driver fec_driver = {
1784 .name = DRIVER_NAME,
1785 .owner = THIS_MODULE,
1789 .of_match_table = fec_dt_ids,
1791 .id_table = fec_devtype,
1793 .remove = fec_drv_remove,
1796 module_platform_driver(fec_driver);
1798 MODULE_LICENSE("GPL");