1 /****************************************************************************/
4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
11 /****************************************************************************/
14 /****************************************************************************/
16 #include <linux/clocksource.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
20 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
21 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
22 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
24 * Just figures, Motorola would have to change the offsets for
25 * registers in the same peripheral device on different models
28 #define FEC_IEVENT 0x004 /* Interrupt event reg */
29 #define FEC_IMASK 0x008 /* Interrupt mask reg */
30 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
31 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
32 #define FEC_ECNTRL 0x024 /* Ethernet control reg */
33 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
34 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
35 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
36 #define FEC_R_CNTRL 0x084 /* Receive control reg */
37 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
38 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
39 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
40 #define FEC_OPD 0x0ec /* Opcode + Pause duration */
41 #define FEC_TXIC0 0xF0 /* Tx Interrupt Coalescing for ring 0 */
42 #define FEC_TXIC1 0xF4 /* Tx Interrupt Coalescing for ring 1 */
43 #define FEC_TXIC2 0xF8 /* Tx Interrupt Coalescing for ring 2 */
44 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
45 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
46 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
47 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
48 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
49 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
50 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
51 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
52 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
53 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
54 #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
55 #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
56 #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */
57 #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
58 #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
59 #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */
60 #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
61 #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
62 #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */
63 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
64 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
65 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
66 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
67 #define FEC_RACC 0x1C4 /* Receive Accelerator function */
68 #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */
69 #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */
70 #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */
71 #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */
72 #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
73 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
74 #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
75 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
76 #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
77 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
78 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
80 #define BM_MIIGSK_CFGR_MII 0x00
81 #define BM_MIIGSK_CFGR_RMII 0x01
82 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40
84 #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
85 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */
86 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
87 #define RMON_T_MC_PKT 0x20C /* RMON TX multicast pkts */
88 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
89 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
90 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
91 #define RMON_T_FRAG 0x21C /* RMON TX pkts < 64 bytes, bad CRC */
92 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
93 #define RMON_T_COL 0x224 /* RMON TX collision count */
94 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
95 #define RMON_T_P65TO127 0x22C /* RMON TX 65 to 127 byte pkts */
96 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
97 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
98 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
99 #define RMON_T_P1024TO2047 0x23C /* RMON TX 1024 to 2047 byte pkts */
100 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
101 #define RMON_T_OCTETS 0x244 /* RMON TX octets */
102 #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
103 #define IEEE_T_FRAME_OK 0x24C /* Frames tx'd OK */
104 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
105 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
106 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
107 #define IEEE_T_LCOL 0x25C /* Frames tx'd with late collision */
108 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
109 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
110 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
111 #define IEEE_T_SQE 0x26C /* Frames tx'd with SQE err */
112 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
113 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
114 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */
115 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
116 #define RMON_R_MC_PKT 0x28C /* RMON RX multicast pkts */
117 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
118 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
119 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
120 #define RMON_R_FRAG 0x29C /* RMON RX pkts < 64 bytes, bad CRC */
121 #define RMON_R_JAB 0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
122 #define RMON_R_RESVD_O 0x2A4 /* Reserved */
123 #define RMON_R_P64 0x2A8 /* RMON RX 64 byte pkts */
124 #define RMON_R_P65TO127 0x2AC /* RMON RX 65 to 127 byte pkts */
125 #define RMON_R_P128TO255 0x2B0 /* RMON RX 128 to 255 byte pkts */
126 #define RMON_R_P256TO511 0x2B4 /* RMON RX 256 to 511 byte pkts */
127 #define RMON_R_P512TO1023 0x2B8 /* RMON RX 512 to 1023 byte pkts */
128 #define RMON_R_P1024TO2047 0x2BC /* RMON RX 1024 to 2047 byte pkts */
129 #define RMON_R_P_GTE2048 0x2C0 /* RMON RX pkts > 2048 bytes */
130 #define RMON_R_OCTETS 0x2C4 /* RMON RX octets */
131 #define IEEE_R_DROP 0x2C8 /* Count frames not counted correctly */
132 #define IEEE_R_FRAME_OK 0x2CC /* Frames rx'd OK */
133 #define IEEE_R_CRC 0x2D0 /* Frames rx'd with CRC err */
134 #define IEEE_R_ALIGN 0x2D4 /* Frames rx'd with alignment err */
135 #define IEEE_R_MACERR 0x2D8 /* Receive FIFO overflow count */
136 #define IEEE_R_FDXFC 0x2DC /* Flow control pause frames rx'd */
137 #define IEEE_R_OCTETS_OK 0x2E0 /* Octet cnt for frames rx'd w/o err */
141 #define FEC_ECNTRL 0x000 /* Ethernet control reg */
142 #define FEC_IEVENT 0x004 /* Interrupt even reg */
143 #define FEC_IMASK 0x008 /* Interrupt mask reg */
144 #define FEC_IVEC 0x00c /* Interrupt vec status reg */
145 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
146 #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
147 #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
148 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
149 #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
150 #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
151 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
152 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
153 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
154 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */
155 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
156 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
157 #define FEC_R_CNTRL 0x104 /* Receive control reg */
158 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
159 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */
160 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
161 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
162 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
163 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
164 #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */
165 #define FEC_R_DES_START_1 FEC_R_DES_START_0
166 #define FEC_R_DES_START_2 FEC_R_DES_START_0
167 #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */
168 #define FEC_X_DES_START_1 FEC_X_DES_START_0
169 #define FEC_X_DES_START_2 FEC_X_DES_START_0
170 #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */
171 #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
172 #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
173 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
174 /* Not existed in real chip
175 * Just for pass build.
177 #define FEC_RCMR_1 0xFFF
178 #define FEC_RCMR_2 0xFFF
179 #define FEC_DMA_CFG_1 0xFFF
180 #define FEC_DMA_CFG_2 0xFFF
181 #define FEC_TXIC0 0xFFF
182 #define FEC_TXIC1 0xFFF
183 #define FEC_TXIC2 0xFFF
184 #define FEC_RXIC0 0xFFF
185 #define FEC_RXIC1 0xFFF
186 #define FEC_RXIC2 0xFFF
187 #endif /* CONFIG_M5272 */
191 * Define the buffer descriptor structure.
193 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
195 unsigned short cbd_datlen; /* Data length */
196 unsigned short cbd_sc; /* Control and status info */
197 unsigned long cbd_bufaddr; /* Buffer address */
201 unsigned short cbd_sc; /* Control and status info */
202 unsigned short cbd_datlen; /* Data length */
203 unsigned long cbd_bufaddr; /* Buffer address */
209 unsigned long cbd_esc;
210 unsigned long cbd_prot;
211 unsigned long cbd_bdu;
213 unsigned short res0[4];
217 * The following definitions courtesy of commproc.h, which where
218 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
220 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
221 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
222 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
223 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
224 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
225 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
226 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
227 #define BD_SC_BR ((ushort)0x0020) /* Break received */
228 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
229 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
230 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
231 #define BD_SC_CD ((ushort)0x0001) /* ?? */
233 /* Buffer descriptor control/status used by Ethernet receive.
235 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
236 #define BD_ENET_RX_WRAP ((ushort)0x2000)
237 #define BD_ENET_RX_INTR ((ushort)0x1000)
238 #define BD_ENET_RX_LAST ((ushort)0x0800)
239 #define BD_ENET_RX_FIRST ((ushort)0x0400)
240 #define BD_ENET_RX_MISS ((ushort)0x0100)
241 #define BD_ENET_RX_LG ((ushort)0x0020)
242 #define BD_ENET_RX_NO ((ushort)0x0010)
243 #define BD_ENET_RX_SH ((ushort)0x0008)
244 #define BD_ENET_RX_CR ((ushort)0x0004)
245 #define BD_ENET_RX_OV ((ushort)0x0002)
246 #define BD_ENET_RX_CL ((ushort)0x0001)
247 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
249 /* Enhanced buffer descriptor control/status used by Ethernet receive */
250 #define BD_ENET_RX_VLAN 0x00000004
252 /* Buffer descriptor control/status used by Ethernet transmit.
254 #define BD_ENET_TX_READY ((ushort)0x8000)
255 #define BD_ENET_TX_PAD ((ushort)0x4000)
256 #define BD_ENET_TX_WRAP ((ushort)0x2000)
257 #define BD_ENET_TX_INTR ((ushort)0x1000)
258 #define BD_ENET_TX_LAST ((ushort)0x0800)
259 #define BD_ENET_TX_TC ((ushort)0x0400)
260 #define BD_ENET_TX_DEF ((ushort)0x0200)
261 #define BD_ENET_TX_HB ((ushort)0x0100)
262 #define BD_ENET_TX_LC ((ushort)0x0080)
263 #define BD_ENET_TX_RL ((ushort)0x0040)
264 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
265 #define BD_ENET_TX_UN ((ushort)0x0002)
266 #define BD_ENET_TX_CSL ((ushort)0x0001)
267 #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */
269 /*enhanced buffer descriptor control/status used by Ethernet transmit*/
270 #define BD_ENET_TX_INT 0x40000000
271 #define BD_ENET_TX_TS 0x20000000
272 #define BD_ENET_TX_PINS 0x10000000
273 #define BD_ENET_TX_IINS 0x08000000
276 /* This device has up to three irqs on some platforms */
277 #define FEC_IRQ_NUM 3
279 /* Maximum number of queues supported
280 * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
281 * User can point the queue number that is less than or equal to 3.
283 #define FEC_ENET_MAX_TX_QS 3
284 #define FEC_ENET_MAX_RX_QS 3
286 #define FEC_R_DES_START(X) ((X == 1) ? FEC_R_DES_START_1 : \
288 FEC_R_DES_START_2 : FEC_R_DES_START_0))
289 #define FEC_X_DES_START(X) ((X == 1) ? FEC_X_DES_START_1 : \
291 FEC_X_DES_START_2 : FEC_X_DES_START_0))
292 #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
294 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
295 #define FEC_R_DES_ACTIVE(X) ((X == 1) ? FEC_R_DES_ACTIVE_1 : \
297 FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0))
298 #define FEC_X_DES_ACTIVE(X) ((X == 1) ? FEC_X_DES_ACTIVE_1 : \
300 FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0))
302 #define FEC_DMA_CFG(X) ((X == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
304 #define DMA_CLASS_EN (1 << 16)
305 #define FEC_RCMR(X) ((X == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
306 #define IDLE_SLOPE_MASK 0xFFFF
307 #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */
308 #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */
309 #define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
310 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
311 #define RCMR_MATCHEN (0x1 << 16)
312 #define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2))
313 #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
314 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
315 #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
316 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
317 #define RCMR_CMP(X) ((X == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
318 #define FEC_TX_BD_FTYPE(X) ((X & 0xF) << 20)
320 /* The number of Tx and Rx buffers. These are allocated from the page
321 * pool. The code may assume these are power of two, so it it best
322 * to keep them that size.
323 * We don't need to allocate pages for the transmitter. We just use
324 * the skbuffer directly.
327 #define FEC_ENET_RX_PAGES 256
328 #define FEC_ENET_RX_FRSIZE 2048
329 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
330 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
331 #define FEC_ENET_TX_FRSIZE 2048
332 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
333 #define TX_RING_SIZE 512 /* Must be power of two */
334 #define TX_RING_MOD_MASK 511 /* for this to work */
336 #define BD_ENET_RX_INT 0x00800000
337 #define BD_ENET_RX_PTP ((ushort)0x0400)
338 #define BD_ENET_RX_ICE 0x00000020
339 #define BD_ENET_RX_PCR 0x00000010
340 #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
341 #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
343 /* Interrupt events/masks. */
344 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
345 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
346 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
347 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
348 #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */
349 #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */
350 #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */
351 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
352 #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */
353 #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */
354 #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */
355 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
356 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
357 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
358 #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
359 #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
360 #define FEC_ENET_TS_AVAIL ((uint)0x00010000)
361 #define FEC_ENET_TS_TIMER ((uint)0x00008000)
363 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
364 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
366 /* ENET interrupt coalescing macro define */
367 #define FEC_ITR_CLK_SEL (0x1 << 30)
368 #define FEC_ITR_EN (0x1 << 31)
369 #define FEC_ITR_ICFT(X) ((X & 0xFF) << 20)
370 #define FEC_ITR_ICTT(X) ((X) & 0xFFFF)
371 #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */
372 #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */
374 #define FEC_VLAN_TAG_LEN 0x04
375 #define FEC_ETHTYPE_LEN 0x02
377 /* Controller is ENET-MAC */
378 #define FEC_QUIRK_ENET_MAC (1 << 0)
379 /* Controller needs driver to swap frame */
380 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
381 /* Controller uses gasket */
382 #define FEC_QUIRK_USE_GASKET (1 << 2)
383 /* Controller has GBIT support */
384 #define FEC_QUIRK_HAS_GBIT (1 << 3)
385 /* Controller has extend desc buffer */
386 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
387 /* Controller has hardware checksum support */
388 #define FEC_QUIRK_HAS_CSUM (1 << 5)
389 /* Controller has hardware vlan support */
390 #define FEC_QUIRK_HAS_VLAN (1 << 6)
391 /* ENET IP errata ERR006358
393 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
394 * detected as not set during a prior frame transmission, then the
395 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
396 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
397 * frames not being transmitted until there is a 0-to-1 transition on
400 #define FEC_QUIRK_ERR006358 (1 << 7)
403 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
404 * - Two class indicators on receive with configurable priority
405 * - Two class indicators and line speed timer on transmit allowing
406 * implementation class credit based shapers externally
407 * - Additional DMA registers provisioned to allow managing up to 3
410 #define FEC_QUIRK_HAS_AVB (1 << 8)
412 * i.MX6Q/DL ENET cannot wake up system in wait mode because ENET tx & rx
413 * interrupt signal don't connect to GPC. So use pm qos to avoid cpu enter
416 #define FEC_QUIRK_BUG_WAITMODE (1 << 9)
417 /* There is a TDAR race condition for mutliQ when the software sets TDAR
418 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
419 * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
420 * The issue exist at i.MX6SX enet IP.
422 #define FEC_QUIRK_ERR007885 (1 << 10)
424 * Incorrect behavior for ENET_ATCR[Capture and Restart Bits].
425 * These bits will always read a value zero. According to SPEC, when these
426 * bits are set to 1'b1, these should hold value 1'b1 until the counter value
427 * is capture in the register clock domain.
429 #define FEC_QUIRK_TKT210590 (1 << 11)
431 struct fec_enet_priv_tx_q {
433 unsigned char *tx_bounce[TX_RING_SIZE];
434 struct sk_buff *tx_skbuff[TX_RING_SIZE];
437 struct bufdesc *tx_bd_base;
440 unsigned short tx_stop_threshold;
441 unsigned short tx_wake_threshold;
443 struct bufdesc *cur_tx;
444 struct bufdesc *dirty_tx;
446 dma_addr_t tso_hdrs_dma;
449 struct fec_enet_priv_rx_q {
451 struct sk_buff *rx_skbuff[RX_RING_SIZE];
454 struct bufdesc *rx_bd_base;
457 struct bufdesc *cur_rx;
460 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
461 * tx_bd_base always point to the base of the buffer descriptors. The
462 * cur_rx and cur_tx point to the currently available buffer.
463 * The dirty_tx tracks the current buffer that is being sent by the
464 * controller. The cur_tx and dirty_tx are equal under both completely
465 * empty and completely full conditions. The empty/ready indicator in
466 * the buffer descriptor determines the actual condition.
468 struct fec_enet_private {
469 /* Hardware registers of the FEC device */
472 struct net_device *netdev;
477 struct clk *clk_enet_out;
481 struct mutex ptp_clk_mutex;
482 unsigned int num_tx_queues;
483 unsigned int num_rx_queues;
485 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
486 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
487 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
489 unsigned int total_tx_ring_size;
490 unsigned int total_rx_ring_size;
492 unsigned long work_tx;
493 unsigned long work_rx;
494 unsigned long work_ts;
495 unsigned long work_mdio;
497 unsigned short bufdesc_size;
499 struct platform_device *pdev;
503 /* Phylib and MDIO interface */
504 struct mii_bus *mii_bus;
505 struct phy_device *phy_dev;
508 phy_interface_t phy_interface;
509 struct device_node *phy_node;
513 struct completion mdio_done;
514 int irq[FEC_IRQ_NUM];
519 struct napi_struct napi;
522 struct work_struct tx_timeout_work;
524 struct ptp_clock *ptp_clock;
525 struct ptp_clock_info ptp_caps;
526 unsigned long last_overflow_check;
527 spinlock_t tmreg_lock;
528 struct cyclecounter cc;
529 struct timecounter tc;
530 int rx_hwtstamp_filter;
535 struct delayed_work time_keep;
536 struct regulator *reg_phy;
538 unsigned int tx_align;
539 unsigned int rx_align;
541 /* hw interrupt coalesce */
542 unsigned int rx_pkts_itr;
543 unsigned int rx_time_itr;
544 unsigned int tx_pkts_itr;
545 unsigned int tx_time_itr;
546 unsigned int itr_clk_rate;
550 /* ptp clock period in ns*/
551 unsigned int ptp_inc;
555 unsigned int reload_period;
557 unsigned int next_counter;
560 void fec_ptp_init(struct platform_device *pdev);
561 void fec_ptp_start_cyclecounter(struct net_device *ndev);
562 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
563 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
564 uint fec_ptp_check_pps_event(struct fec_enet_private *fep);
566 /****************************************************************************/