1 /****************************************************************************/
4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
7 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
11 /****************************************************************************/
14 /****************************************************************************/
16 #include <linux/clocksource.h>
17 #include <linux/net_tstamp.h>
18 #include <linux/ptp_clock_kernel.h>
20 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
21 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
22 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
24 * Just figures, Motorola would have to change the offsets for
25 * registers in the same peripheral device on different models
28 #define FEC_IEVENT 0x004 /* Interrupt event reg */
29 #define FEC_IMASK 0x008 /* Interrupt mask reg */
30 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
31 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
32 #define FEC_ECNTRL 0x024 /* Ethernet control reg */
33 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
34 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
35 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
36 #define FEC_R_CNTRL 0x084 /* Receive control reg */
37 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
38 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
39 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
40 #define FEC_OPD 0x0ec /* Opcode + Pause duration */
41 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
42 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
43 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
44 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
45 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
46 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
47 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
48 #define FEC_R_DES_START 0x180 /* Receive descriptor ring */
49 #define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
50 #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
51 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
52 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
53 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
54 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
55 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
56 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
58 #define BM_MIIGSK_CFGR_MII 0x00
59 #define BM_MIIGSK_CFGR_RMII 0x01
60 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40
64 #define FEC_ECNTRL 0x000 /* Ethernet control reg */
65 #define FEC_IEVENT 0x004 /* Interrupt even reg */
66 #define FEC_IMASK 0x008 /* Interrupt mask reg */
67 #define FEC_IVEC 0x00c /* Interrupt vec status reg */
68 #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
69 #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
70 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
71 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
72 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
73 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */
74 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
75 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
76 #define FEC_R_CNTRL 0x104 /* Receive control reg */
77 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
78 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */
79 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
80 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
81 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
82 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
83 #define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
84 #define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
85 #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
86 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
88 #endif /* CONFIG_M5272 */
92 * Define the buffer descriptor structure.
94 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
96 unsigned short cbd_datlen; /* Data length */
97 unsigned short cbd_sc; /* Control and status info */
98 unsigned long cbd_bufaddr; /* Buffer address */
103 unsigned long cbd_esc;
104 unsigned long cbd_prot;
105 unsigned long cbd_bdu;
107 unsigned short res0[4];
112 unsigned short cbd_sc; /* Control and status info */
113 unsigned short cbd_datlen; /* Data length */
114 unsigned long cbd_bufaddr; /* Buffer address */
119 * The following definitions courtesy of commproc.h, which where
120 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
122 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
123 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
124 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
125 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
126 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
127 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
128 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
129 #define BD_SC_BR ((ushort)0x0020) /* Break received */
130 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
131 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
132 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
133 #define BD_SC_CD ((ushort)0x0001) /* ?? */
135 /* Buffer descriptor control/status used by Ethernet receive.
137 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
138 #define BD_ENET_RX_WRAP ((ushort)0x2000)
139 #define BD_ENET_RX_INTR ((ushort)0x1000)
140 #define BD_ENET_RX_LAST ((ushort)0x0800)
141 #define BD_ENET_RX_FIRST ((ushort)0x0400)
142 #define BD_ENET_RX_MISS ((ushort)0x0100)
143 #define BD_ENET_RX_LG ((ushort)0x0020)
144 #define BD_ENET_RX_NO ((ushort)0x0010)
145 #define BD_ENET_RX_SH ((ushort)0x0008)
146 #define BD_ENET_RX_CR ((ushort)0x0004)
147 #define BD_ENET_RX_OV ((ushort)0x0002)
148 #define BD_ENET_RX_CL ((ushort)0x0001)
149 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
151 /* Buffer descriptor control/status used by Ethernet transmit.
153 #define BD_ENET_TX_READY ((ushort)0x8000)
154 #define BD_ENET_TX_PAD ((ushort)0x4000)
155 #define BD_ENET_TX_WRAP ((ushort)0x2000)
156 #define BD_ENET_TX_INTR ((ushort)0x1000)
157 #define BD_ENET_TX_LAST ((ushort)0x0800)
158 #define BD_ENET_TX_TC ((ushort)0x0400)
159 #define BD_ENET_TX_DEF ((ushort)0x0200)
160 #define BD_ENET_TX_HB ((ushort)0x0100)
161 #define BD_ENET_TX_LC ((ushort)0x0080)
162 #define BD_ENET_TX_RL ((ushort)0x0040)
163 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
164 #define BD_ENET_TX_UN ((ushort)0x0002)
165 #define BD_ENET_TX_CSL ((ushort)0x0001)
166 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
168 /*enhanced buffer desciptor control/status used by Ethernet transmit*/
169 #define BD_ENET_TX_INT 0x40000000
170 #define BD_ENET_TX_TS 0x20000000
173 /* This device has up to three irqs on some platforms */
174 #define FEC_IRQ_NUM 3
176 /* The number of Tx and Rx buffers. These are allocated from the page
177 * pool. The code may assume these are power of two, so it it best
178 * to keep them that size.
179 * We don't need to allocate pages for the transmitter. We just use
180 * the skbuffer directly.
183 #define FEC_ENET_RX_PAGES 8
184 #define FEC_ENET_RX_FRSIZE 2048
185 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
186 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
187 #define FEC_ENET_TX_FRSIZE 2048
188 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
189 #define TX_RING_SIZE 16 /* Must be power of two */
190 #define TX_RING_MOD_MASK 15 /* for this to work */
192 #define BD_ENET_RX_INT 0x00800000
193 #define BD_ENET_RX_PTP ((ushort)0x0400)
195 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
196 * tx_bd_base always point to the base of the buffer descriptors. The
197 * cur_rx and cur_tx point to the currently available buffer.
198 * The dirty_tx tracks the current buffer that is being sent by the
199 * controller. The cur_tx and dirty_tx are equal under both completely
200 * empty and completely full conditions. The empty/ready indicator in
201 * the buffer descriptor determines the actual condition.
203 struct fec_enet_private {
204 /* Hardware registers of the FEC device */
207 struct net_device *netdev;
213 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
214 unsigned char *tx_bounce[TX_RING_SIZE];
215 struct sk_buff *tx_skbuff[TX_RING_SIZE];
216 struct sk_buff *rx_skbuff[RX_RING_SIZE];
220 /* CPM dual port RAM relative addresses */
222 /* Address of Rx and Tx buffers */
223 struct bufdesc *rx_bd_base;
224 struct bufdesc *tx_bd_base;
225 /* The next free ring entry */
226 struct bufdesc *cur_rx, *cur_tx;
227 /* The ring entries to be free()ed */
228 struct bufdesc *dirty_tx;
231 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
234 struct platform_device *pdev;
239 /* Phylib and MDIO interface */
240 struct mii_bus *mii_bus;
241 struct phy_device *phy_dev;
244 phy_interface_t phy_interface;
247 struct completion mdio_done;
248 int irq[FEC_IRQ_NUM];
252 struct napi_struct napi;
254 struct ptp_clock *ptp_clock;
255 struct ptp_clock_info ptp_caps;
256 unsigned long last_overflow_check;
257 spinlock_t tmreg_lock;
258 struct cyclecounter cc;
259 struct timecounter tc;
260 int rx_hwtstamp_filter;
265 struct timer_list time_keep;
269 void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev);
270 void fec_ptp_start_cyclecounter(struct net_device *ndev);
271 int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
273 /****************************************************************************/