2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
58 #include <asm/cacheflush.h>
62 static void set_multicast_list(struct net_device *ndev);
64 #if defined(CONFIG_ARM)
65 #define FEC_ALIGNMENT 0xf
67 #define FEC_ALIGNMENT 0x3
70 #define DRIVER_NAME "fec"
71 #define FEC_NAPI_WEIGHT 64
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
94 static struct platform_device_id fec_devtype[] = {
96 /* keep it for coldfire */
101 .driver_data = FEC_QUIRK_USE_GASKET,
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM,
113 .name = "mvf600-fec",
114 .driver_data = FEC_QUIRK_ENET_MAC,
119 MODULE_DEVICE_TABLE(platform, fec_devtype);
122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
123 IMX27_FEC, /* runs on i.mx27/35/51 */
129 static const struct of_device_id fec_dt_ids[] = {
130 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
131 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
132 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
133 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
134 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
137 MODULE_DEVICE_TABLE(of, fec_dt_ids);
139 static unsigned char macaddr[ETH_ALEN];
140 module_param_array(macaddr, byte, NULL, 0);
141 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
143 #if defined(CONFIG_M5272)
145 * Some hardware gets it MAC address out of local flash memory.
146 * if this is non-zero then assume it is the address to get MAC from.
148 #if defined(CONFIG_NETtel)
149 #define FEC_FLASHMAC 0xf0006006
150 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
151 #define FEC_FLASHMAC 0xf0006000
152 #elif defined(CONFIG_CANCam)
153 #define FEC_FLASHMAC 0xf0020000
154 #elif defined (CONFIG_M5272C3)
155 #define FEC_FLASHMAC (0xffe04000 + 4)
156 #elif defined(CONFIG_MOD5272)
157 #define FEC_FLASHMAC 0xffc0406b
159 #define FEC_FLASHMAC 0
161 #endif /* CONFIG_M5272 */
163 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
164 #error "FEC: descriptor ring size constants too large"
167 /* Interrupt events/masks. */
168 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
169 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
170 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
171 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
172 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
173 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
174 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
175 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
176 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
177 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
179 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
180 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
182 /* The FEC stores dest/src/type, data, and checksum for receive packets.
184 #define PKT_MAXBUF_SIZE 1518
185 #define PKT_MINBUF_SIZE 64
186 #define PKT_MAXBLR_SIZE 1520
188 /* FEC receive acceleration */
189 #define FEC_RACC_IPDIS (1 << 1)
190 #define FEC_RACC_PRODIS (1 << 2)
191 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
194 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
195 * size bits. Other FEC hardware does not, so we need to take that into
196 * account when setting it.
198 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
199 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
200 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
202 #define OPT_FRAME_SIZE 0
205 /* FEC MII MMFR bits definition */
206 #define FEC_MMFR_ST (1 << 30)
207 #define FEC_MMFR_OP_READ (2 << 28)
208 #define FEC_MMFR_OP_WRITE (1 << 28)
209 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
210 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
211 #define FEC_MMFR_TA (2 << 16)
212 #define FEC_MMFR_DATA(v) (v & 0xffff)
214 #define FEC_MII_TIMEOUT 30000 /* us */
216 /* Transmitter timeout */
217 #define TX_TIMEOUT (2 * HZ)
219 #define FEC_PAUSE_FLAG_AUTONEG 0x1
220 #define FEC_PAUSE_FLAG_ENABLE 0x2
224 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
226 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
228 return (struct bufdesc *)(ex + 1);
233 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
235 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
237 return (struct bufdesc *)(ex - 1);
242 static void *swap_buffer(void *bufaddr, int len)
245 unsigned int *buf = bufaddr;
247 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
248 *buf = cpu_to_be32(*buf);
254 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
256 /* Only run for packets requiring a checksum. */
257 if (skb->ip_summed != CHECKSUM_PARTIAL)
260 if (unlikely(skb_cow_head(skb, 0)))
263 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
269 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
271 struct fec_enet_private *fep = netdev_priv(ndev);
272 const struct platform_device_id *id_entry =
273 platform_get_device_id(fep->pdev);
276 unsigned short status;
280 /* Link is down or auto-negotiation is in progress. */
281 return NETDEV_TX_BUSY;
284 /* Fill in a Tx ring entry */
287 status = bdp->cbd_sc;
289 if (status & BD_ENET_TX_READY) {
290 /* Ooops. All transmit buffers are full. Bail out.
291 * This should not happen, since ndev->tbusy should be set.
293 netdev_err(ndev, "tx queue full!\n");
294 return NETDEV_TX_BUSY;
297 /* Protocol checksum off-load for TCP and UDP. */
298 if (fec_enet_clear_csum(skb, ndev)) {
303 /* Clear all of the status flags */
304 status &= ~BD_ENET_TX_STATS;
306 /* Set buffer length and buffer pointer */
308 bdp->cbd_datlen = skb->len;
311 * On some FEC implementations data must be aligned on
312 * 4-byte boundaries. Use bounce buffers to copy data
313 * and get it aligned. Ugh.
316 index = (struct bufdesc_ex *)bdp -
317 (struct bufdesc_ex *)fep->tx_bd_base;
319 index = bdp - fep->tx_bd_base;
321 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
322 memcpy(fep->tx_bounce[index], skb->data, skb->len);
323 bufaddr = fep->tx_bounce[index];
327 * Some design made an incorrect assumption on endian mode of
328 * the system that it's running on. As the result, driver has to
329 * swap every frame going to and coming from the controller.
331 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
332 swap_buffer(bufaddr, skb->len);
334 /* Save skb pointer */
335 fep->tx_skbuff[index] = skb;
337 /* Push the data cache so the CPM does not get stale memory
340 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
341 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
343 /* Send it on its way. Tell FEC it's ready, interrupt when done,
344 * it's the last BD of the frame, and to put the CRC on the end.
346 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
347 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
348 bdp->cbd_sc = status;
350 if (fep->bufdesc_ex) {
352 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
354 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
356 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
357 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
359 ebdp->cbd_esc = BD_ENET_TX_INT;
361 /* Enable protocol checksum flags
362 * We do not bother with the IP Checksum bits as they
363 * are done by the kernel
365 if (skb->ip_summed == CHECKSUM_PARTIAL)
366 ebdp->cbd_esc |= BD_ENET_TX_PINS;
369 /* If this was the last BD in the ring, start at the beginning again. */
370 if (status & BD_ENET_TX_WRAP)
371 bdp = fep->tx_bd_base;
373 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
377 if (fep->cur_tx == fep->dirty_tx)
378 netif_stop_queue(ndev);
380 /* Trigger transmission start */
381 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
383 skb_tx_timestamp(skb);
388 /* Init RX & TX buffer descriptors
390 static void fec_enet_bd_init(struct net_device *dev)
392 struct fec_enet_private *fep = netdev_priv(dev);
396 /* Initialize the receive buffer descriptors. */
397 bdp = fep->rx_bd_base;
398 for (i = 0; i < RX_RING_SIZE; i++) {
400 /* Initialize the BD for every fragment in the page. */
401 if (bdp->cbd_bufaddr)
402 bdp->cbd_sc = BD_ENET_RX_EMPTY;
405 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
408 /* Set the last buffer to wrap */
409 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
410 bdp->cbd_sc |= BD_SC_WRAP;
412 fep->cur_rx = fep->rx_bd_base;
414 /* ...and the same for transmit */
415 bdp = fep->tx_bd_base;
417 for (i = 0; i < TX_RING_SIZE; i++) {
419 /* Initialize the BD for every fragment in the page. */
421 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
422 dev_kfree_skb_any(fep->tx_skbuff[i]);
423 fep->tx_skbuff[i] = NULL;
425 bdp->cbd_bufaddr = 0;
426 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
429 /* Set the last buffer to wrap */
430 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
431 bdp->cbd_sc |= BD_SC_WRAP;
435 /* This function is called to start or restart the FEC during a link
436 * change. This only happens when switching between half and full
440 fec_restart(struct net_device *ndev, int duplex)
442 struct fec_enet_private *fep = netdev_priv(ndev);
443 const struct platform_device_id *id_entry =
444 platform_get_device_id(fep->pdev);
448 u32 rcntl = OPT_FRAME_SIZE | 0x04;
449 u32 ecntl = 0x2; /* ETHEREN */
451 if (netif_running(ndev)) {
452 netif_device_detach(ndev);
453 napi_disable(&fep->napi);
454 netif_stop_queue(ndev);
455 netif_tx_lock_bh(ndev);
458 /* Whack a reset. We should wait for this. */
459 writel(1, fep->hwp + FEC_ECNTRL);
463 * enet-mac reset will reset mac address registers too,
464 * so need to reconfigure it.
466 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
467 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
468 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
469 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
472 /* Clear any outstanding interrupt. */
473 writel(0xffc00000, fep->hwp + FEC_IEVENT);
475 /* Setup multicast filter. */
476 set_multicast_list(ndev);
478 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
479 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
482 /* Set maximum receive buffer size. */
483 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
485 fec_enet_bd_init(ndev);
487 /* Set receive and transmit descriptor base. */
488 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
490 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
491 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
493 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
494 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
497 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
498 if (fep->tx_skbuff[i]) {
499 dev_kfree_skb_any(fep->tx_skbuff[i]);
500 fep->tx_skbuff[i] = NULL;
504 /* Enable MII mode */
507 writel(0x04, fep->hwp + FEC_X_CNTRL);
511 writel(0x0, fep->hwp + FEC_X_CNTRL);
514 fep->full_duplex = duplex;
517 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
519 #if !defined(CONFIG_M5272)
520 /* set RX checksum */
521 val = readl(fep->hwp + FEC_RACC);
522 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
523 val |= FEC_RACC_OPTIONS;
525 val &= ~FEC_RACC_OPTIONS;
526 writel(val, fep->hwp + FEC_RACC);
530 * The phy interface and speed need to get configured
531 * differently on enet-mac.
533 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
534 /* Enable flow control and length check */
535 rcntl |= 0x40000000 | 0x00000020;
537 /* RGMII, RMII or MII */
538 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
540 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
545 /* 1G, 100M or 10M */
547 if (fep->phy_dev->speed == SPEED_1000)
549 else if (fep->phy_dev->speed == SPEED_100)
555 #ifdef FEC_MIIGSK_ENR
556 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
558 /* disable the gasket and wait */
559 writel(0, fep->hwp + FEC_MIIGSK_ENR);
560 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
564 * configure the gasket:
565 * RMII, 50 MHz, no loopback, no echo
566 * MII, 25 MHz, no loopback, no echo
568 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
569 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
570 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
571 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
572 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
574 /* re-enable the gasket */
575 writel(2, fep->hwp + FEC_MIIGSK_ENR);
580 #if !defined(CONFIG_M5272)
581 /* enable pause frame*/
582 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
583 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
584 fep->phy_dev && fep->phy_dev->pause)) {
585 rcntl |= FEC_ENET_FCE;
587 /* set FIFO threshold parameter to reduce overrun */
588 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
589 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
590 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
591 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
594 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
596 rcntl &= ~FEC_ENET_FCE;
598 #endif /* !defined(CONFIG_M5272) */
600 writel(rcntl, fep->hwp + FEC_R_CNTRL);
602 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
603 /* enable ENET endian swap */
605 /* enable ENET store and forward mode */
606 writel(1 << 8, fep->hwp + FEC_X_WMRK);
613 /* Enable the MIB statistic event counters */
614 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
617 /* And last, enable the transmit and receive processing */
618 writel(ecntl, fep->hwp + FEC_ECNTRL);
619 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
622 fec_ptp_start_cyclecounter(ndev);
624 /* Enable interrupts we wish to service */
625 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
627 if (netif_running(ndev)) {
628 netif_tx_unlock_bh(ndev);
629 netif_wake_queue(ndev);
630 napi_enable(&fep->napi);
631 netif_device_attach(ndev);
636 fec_stop(struct net_device *ndev)
638 struct fec_enet_private *fep = netdev_priv(ndev);
639 const struct platform_device_id *id_entry =
640 platform_get_device_id(fep->pdev);
641 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
643 /* We cannot expect a graceful transmit stop without link !!! */
645 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
647 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
648 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
651 /* Whack a reset. We should wait for this. */
652 writel(1, fep->hwp + FEC_ECNTRL);
654 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
655 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
657 /* We have to keep ENET enabled to have MII interrupt stay working */
658 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
659 writel(2, fep->hwp + FEC_ECNTRL);
660 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
666 fec_timeout(struct net_device *ndev)
668 struct fec_enet_private *fep = netdev_priv(ndev);
670 ndev->stats.tx_errors++;
672 fep->delay_work.timeout = true;
673 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
676 static void fec_enet_work(struct work_struct *work)
678 struct fec_enet_private *fep =
680 struct fec_enet_private,
681 delay_work.delay_work.work);
683 if (fep->delay_work.timeout) {
684 fep->delay_work.timeout = false;
685 fec_restart(fep->netdev, fep->full_duplex);
686 netif_wake_queue(fep->netdev);
691 fec_enet_tx(struct net_device *ndev)
693 struct fec_enet_private *fep;
695 unsigned short status;
699 fep = netdev_priv(ndev);
702 /* get next bdp of dirty_tx */
703 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
704 bdp = fep->tx_bd_base;
706 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
708 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
710 /* current queue is empty */
711 if (bdp == fep->cur_tx)
715 index = (struct bufdesc_ex *)bdp -
716 (struct bufdesc_ex *)fep->tx_bd_base;
718 index = bdp - fep->tx_bd_base;
720 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
721 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
722 bdp->cbd_bufaddr = 0;
724 skb = fep->tx_skbuff[index];
726 /* Check for errors. */
727 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
728 BD_ENET_TX_RL | BD_ENET_TX_UN |
730 ndev->stats.tx_errors++;
731 if (status & BD_ENET_TX_HB) /* No heartbeat */
732 ndev->stats.tx_heartbeat_errors++;
733 if (status & BD_ENET_TX_LC) /* Late collision */
734 ndev->stats.tx_window_errors++;
735 if (status & BD_ENET_TX_RL) /* Retrans limit */
736 ndev->stats.tx_aborted_errors++;
737 if (status & BD_ENET_TX_UN) /* Underrun */
738 ndev->stats.tx_fifo_errors++;
739 if (status & BD_ENET_TX_CSL) /* Carrier lost */
740 ndev->stats.tx_carrier_errors++;
742 ndev->stats.tx_packets++;
743 ndev->stats.tx_bytes += bdp->cbd_datlen;
746 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
748 struct skb_shared_hwtstamps shhwtstamps;
750 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
752 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
753 spin_lock_irqsave(&fep->tmreg_lock, flags);
754 shhwtstamps.hwtstamp = ns_to_ktime(
755 timecounter_cyc2time(&fep->tc, ebdp->ts));
756 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
757 skb_tstamp_tx(skb, &shhwtstamps);
760 if (status & BD_ENET_TX_READY)
761 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
763 /* Deferred means some collisions occurred during transmit,
764 * but we eventually sent the packet OK.
766 if (status & BD_ENET_TX_DEF)
767 ndev->stats.collisions++;
769 /* Free the sk buffer associated with this last transmit */
770 dev_kfree_skb_any(skb);
771 fep->tx_skbuff[index] = NULL;
775 /* Update pointer to next buffer descriptor to be transmitted */
776 if (status & BD_ENET_TX_WRAP)
777 bdp = fep->tx_bd_base;
779 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
781 /* Since we have freed up a buffer, the ring is no longer full
783 if (fep->dirty_tx != fep->cur_tx) {
784 if (netif_queue_stopped(ndev))
785 netif_wake_queue(ndev);
792 /* During a receive, the cur_rx points to the current incoming buffer.
793 * When we update through the ring, if the next incoming buffer has
794 * not been given to the system, we just set the empty indicator,
795 * effectively tossing the packet.
798 fec_enet_rx(struct net_device *ndev, int budget)
800 struct fec_enet_private *fep = netdev_priv(ndev);
801 const struct platform_device_id *id_entry =
802 platform_get_device_id(fep->pdev);
804 unsigned short status;
808 int pkt_received = 0;
814 /* First, grab all of the stats for the incoming packet.
815 * These get messed up if we get called due to a busy condition.
819 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
821 if (pkt_received >= budget)
825 /* Since we have allocated space to hold a complete frame,
826 * the last indicator should be set.
828 if ((status & BD_ENET_RX_LAST) == 0)
829 netdev_err(ndev, "rcv is not +last\n");
832 goto rx_processing_done;
834 /* Check for errors. */
835 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
836 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
837 ndev->stats.rx_errors++;
838 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
839 /* Frame too long or too short. */
840 ndev->stats.rx_length_errors++;
842 if (status & BD_ENET_RX_NO) /* Frame alignment */
843 ndev->stats.rx_frame_errors++;
844 if (status & BD_ENET_RX_CR) /* CRC Error */
845 ndev->stats.rx_crc_errors++;
846 if (status & BD_ENET_RX_OV) /* FIFO overrun */
847 ndev->stats.rx_fifo_errors++;
850 /* Report late collisions as a frame error.
851 * On this error, the BD is closed, but we don't know what we
852 * have in the buffer. So, just drop this frame on the floor.
854 if (status & BD_ENET_RX_CL) {
855 ndev->stats.rx_errors++;
856 ndev->stats.rx_frame_errors++;
857 goto rx_processing_done;
860 /* Process the incoming frame. */
861 ndev->stats.rx_packets++;
862 pkt_len = bdp->cbd_datlen;
863 ndev->stats.rx_bytes += pkt_len;
864 data = (__u8*)__va(bdp->cbd_bufaddr);
866 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
867 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
869 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
870 swap_buffer(data, pkt_len);
872 /* This does 16 byte alignment, exactly what we need.
873 * The packet length includes FCS, but we don't want to
874 * include that when passing upstream as it messes up
875 * bridging applications.
877 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
879 if (unlikely(!skb)) {
880 ndev->stats.rx_dropped++;
882 skb_reserve(skb, NET_IP_ALIGN);
883 skb_put(skb, pkt_len - 4); /* Make room */
884 skb_copy_to_linear_data(skb, data, pkt_len - 4);
885 skb->protocol = eth_type_trans(skb, ndev);
887 /* Get receive timestamp from the skb */
888 if (fep->hwts_rx_en && fep->bufdesc_ex) {
889 struct skb_shared_hwtstamps *shhwtstamps =
892 struct bufdesc_ex *ebdp =
893 (struct bufdesc_ex *)bdp;
895 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
897 spin_lock_irqsave(&fep->tmreg_lock, flags);
898 shhwtstamps->hwtstamp = ns_to_ktime(
899 timecounter_cyc2time(&fep->tc, ebdp->ts));
900 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
903 if (fep->bufdesc_ex &&
904 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
905 struct bufdesc_ex *ebdp =
906 (struct bufdesc_ex *)bdp;
907 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
909 skb->ip_summed = CHECKSUM_UNNECESSARY;
911 skb_checksum_none_assert(skb);
915 if (!skb_defer_rx_timestamp(skb))
916 napi_gro_receive(&fep->napi, skb);
919 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
920 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
922 /* Clear the status flags for this buffer */
923 status &= ~BD_ENET_RX_STATS;
925 /* Mark the buffer empty */
926 status |= BD_ENET_RX_EMPTY;
927 bdp->cbd_sc = status;
929 if (fep->bufdesc_ex) {
930 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
932 ebdp->cbd_esc = BD_ENET_RX_INT;
937 /* Update BD pointer to next entry */
938 if (status & BD_ENET_RX_WRAP)
939 bdp = fep->rx_bd_base;
941 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
942 /* Doing this here will keep the FEC running while we process
943 * incoming frames. On a heavily loaded network, we should be
944 * able to keep up at the expense of system resources.
946 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
954 fec_enet_interrupt(int irq, void *dev_id)
956 struct net_device *ndev = dev_id;
957 struct fec_enet_private *fep = netdev_priv(ndev);
959 irqreturn_t ret = IRQ_NONE;
962 int_events = readl(fep->hwp + FEC_IEVENT);
963 writel(int_events, fep->hwp + FEC_IEVENT);
965 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
968 /* Disable the RX interrupt */
969 if (napi_schedule_prep(&fep->napi)) {
970 writel(FEC_RX_DISABLED_IMASK,
971 fep->hwp + FEC_IMASK);
972 __napi_schedule(&fep->napi);
976 if (int_events & FEC_ENET_MII) {
978 complete(&fep->mdio_done);
980 } while (int_events);
985 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
987 struct net_device *ndev = napi->dev;
988 int pkts = fec_enet_rx(ndev, budget);
989 struct fec_enet_private *fep = netdev_priv(ndev);
995 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1000 /* ------------------------------------------------------------------------- */
1001 static void fec_get_mac(struct net_device *ndev)
1003 struct fec_enet_private *fep = netdev_priv(ndev);
1004 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1005 unsigned char *iap, tmpaddr[ETH_ALEN];
1008 * try to get mac address in following order:
1010 * 1) module parameter via kernel command line in form
1011 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1016 * 2) from device tree data
1018 if (!is_valid_ether_addr(iap)) {
1019 struct device_node *np = fep->pdev->dev.of_node;
1021 const char *mac = of_get_mac_address(np);
1023 iap = (unsigned char *) mac;
1028 * 3) from flash or fuse (via platform data)
1030 if (!is_valid_ether_addr(iap)) {
1033 iap = (unsigned char *)FEC_FLASHMAC;
1036 iap = (unsigned char *)&pdata->mac;
1041 * 4) FEC mac registers set by bootloader
1043 if (!is_valid_ether_addr(iap)) {
1044 *((unsigned long *) &tmpaddr[0]) =
1045 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1046 *((unsigned short *) &tmpaddr[4]) =
1047 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1052 * 5) random mac address
1054 if (!is_valid_ether_addr(iap)) {
1055 /* Report it and use a random ethernet address instead */
1056 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1057 eth_hw_addr_random(ndev);
1058 netdev_info(ndev, "Using random MAC address: %pM\n",
1063 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1065 /* Adjust MAC if using macaddr */
1067 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1070 /* ------------------------------------------------------------------------- */
1075 static void fec_enet_adjust_link(struct net_device *ndev)
1077 struct fec_enet_private *fep = netdev_priv(ndev);
1078 struct phy_device *phy_dev = fep->phy_dev;
1079 int status_change = 0;
1081 /* Prevent a state halted on mii error */
1082 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1083 phy_dev->state = PHY_RESUMING;
1087 if (phy_dev->link) {
1089 fep->link = phy_dev->link;
1093 if (fep->full_duplex != phy_dev->duplex)
1096 if (phy_dev->speed != fep->speed) {
1097 fep->speed = phy_dev->speed;
1101 /* if any of the above changed restart the FEC */
1103 fec_restart(ndev, phy_dev->duplex);
1107 fep->link = phy_dev->link;
1113 phy_print_status(phy_dev);
1116 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1118 struct fec_enet_private *fep = bus->priv;
1119 unsigned long time_left;
1121 fep->mii_timeout = 0;
1122 init_completion(&fep->mdio_done);
1124 /* start a read op */
1125 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1126 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1127 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1129 /* wait for end of transfer */
1130 time_left = wait_for_completion_timeout(&fep->mdio_done,
1131 usecs_to_jiffies(FEC_MII_TIMEOUT));
1132 if (time_left == 0) {
1133 fep->mii_timeout = 1;
1134 netdev_err(fep->netdev, "MDIO read timeout\n");
1139 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1142 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1145 struct fec_enet_private *fep = bus->priv;
1146 unsigned long time_left;
1148 fep->mii_timeout = 0;
1149 init_completion(&fep->mdio_done);
1151 /* start a write op */
1152 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1153 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1154 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1155 fep->hwp + FEC_MII_DATA);
1157 /* wait for end of transfer */
1158 time_left = wait_for_completion_timeout(&fep->mdio_done,
1159 usecs_to_jiffies(FEC_MII_TIMEOUT));
1160 if (time_left == 0) {
1161 fep->mii_timeout = 1;
1162 netdev_err(fep->netdev, "MDIO write timeout\n");
1169 static int fec_enet_mdio_reset(struct mii_bus *bus)
1174 static int fec_enet_mii_probe(struct net_device *ndev)
1176 struct fec_enet_private *fep = netdev_priv(ndev);
1177 const struct platform_device_id *id_entry =
1178 platform_get_device_id(fep->pdev);
1179 struct phy_device *phy_dev = NULL;
1180 char mdio_bus_id[MII_BUS_ID_SIZE];
1181 char phy_name[MII_BUS_ID_SIZE + 3];
1183 int dev_id = fep->dev_id;
1185 fep->phy_dev = NULL;
1187 /* check for attached phy */
1188 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1189 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1191 if (fep->mii_bus->phy_map[phy_id] == NULL)
1193 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1197 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1201 if (phy_id >= PHY_MAX_ADDR) {
1202 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1203 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1207 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1208 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1209 fep->phy_interface);
1210 if (IS_ERR(phy_dev)) {
1211 netdev_err(ndev, "could not attach to PHY\n");
1212 return PTR_ERR(phy_dev);
1215 /* mask with MAC supported features */
1216 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1217 phy_dev->supported &= PHY_GBIT_FEATURES;
1218 #if !defined(CONFIG_M5272)
1219 phy_dev->supported |= SUPPORTED_Pause;
1223 phy_dev->supported &= PHY_BASIC_FEATURES;
1225 phy_dev->advertising = phy_dev->supported;
1227 fep->phy_dev = phy_dev;
1229 fep->full_duplex = 0;
1231 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1232 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1238 static int fec_enet_mii_init(struct platform_device *pdev)
1240 static struct mii_bus *fec0_mii_bus;
1241 struct net_device *ndev = platform_get_drvdata(pdev);
1242 struct fec_enet_private *fep = netdev_priv(ndev);
1243 const struct platform_device_id *id_entry =
1244 platform_get_device_id(fep->pdev);
1245 int err = -ENXIO, i;
1248 * The dual fec interfaces are not equivalent with enet-mac.
1249 * Here are the differences:
1251 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1252 * - fec0 acts as the 1588 time master while fec1 is slave
1253 * - external phys can only be configured by fec0
1255 * That is to say fec1 can not work independently. It only works
1256 * when fec0 is working. The reason behind this design is that the
1257 * second interface is added primarily for Switch mode.
1259 * Because of the last point above, both phys are attached on fec0
1260 * mdio interface in board design, and need to be configured by
1263 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1264 /* fec1 uses fec0 mii_bus */
1265 if (mii_cnt && fec0_mii_bus) {
1266 fep->mii_bus = fec0_mii_bus;
1273 fep->mii_timeout = 0;
1276 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1278 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1279 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1280 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1283 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1284 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1286 fep->phy_speed <<= 1;
1287 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1289 fep->mii_bus = mdiobus_alloc();
1290 if (fep->mii_bus == NULL) {
1295 fep->mii_bus->name = "fec_enet_mii_bus";
1296 fep->mii_bus->read = fec_enet_mdio_read;
1297 fep->mii_bus->write = fec_enet_mdio_write;
1298 fep->mii_bus->reset = fec_enet_mdio_reset;
1299 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1300 pdev->name, fep->dev_id + 1);
1301 fep->mii_bus->priv = fep;
1302 fep->mii_bus->parent = &pdev->dev;
1304 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1305 if (!fep->mii_bus->irq) {
1307 goto err_out_free_mdiobus;
1310 for (i = 0; i < PHY_MAX_ADDR; i++)
1311 fep->mii_bus->irq[i] = PHY_POLL;
1313 if (mdiobus_register(fep->mii_bus))
1314 goto err_out_free_mdio_irq;
1318 /* save fec0 mii_bus */
1319 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1320 fec0_mii_bus = fep->mii_bus;
1324 err_out_free_mdio_irq:
1325 kfree(fep->mii_bus->irq);
1326 err_out_free_mdiobus:
1327 mdiobus_free(fep->mii_bus);
1332 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1334 if (--mii_cnt == 0) {
1335 mdiobus_unregister(fep->mii_bus);
1336 kfree(fep->mii_bus->irq);
1337 mdiobus_free(fep->mii_bus);
1341 static int fec_enet_get_settings(struct net_device *ndev,
1342 struct ethtool_cmd *cmd)
1344 struct fec_enet_private *fep = netdev_priv(ndev);
1345 struct phy_device *phydev = fep->phy_dev;
1350 return phy_ethtool_gset(phydev, cmd);
1353 static int fec_enet_set_settings(struct net_device *ndev,
1354 struct ethtool_cmd *cmd)
1356 struct fec_enet_private *fep = netdev_priv(ndev);
1357 struct phy_device *phydev = fep->phy_dev;
1362 return phy_ethtool_sset(phydev, cmd);
1365 static void fec_enet_get_drvinfo(struct net_device *ndev,
1366 struct ethtool_drvinfo *info)
1368 struct fec_enet_private *fep = netdev_priv(ndev);
1370 strlcpy(info->driver, fep->pdev->dev.driver->name,
1371 sizeof(info->driver));
1372 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1373 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1376 static int fec_enet_get_ts_info(struct net_device *ndev,
1377 struct ethtool_ts_info *info)
1379 struct fec_enet_private *fep = netdev_priv(ndev);
1381 if (fep->bufdesc_ex) {
1383 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1384 SOF_TIMESTAMPING_RX_SOFTWARE |
1385 SOF_TIMESTAMPING_SOFTWARE |
1386 SOF_TIMESTAMPING_TX_HARDWARE |
1387 SOF_TIMESTAMPING_RX_HARDWARE |
1388 SOF_TIMESTAMPING_RAW_HARDWARE;
1390 info->phc_index = ptp_clock_index(fep->ptp_clock);
1392 info->phc_index = -1;
1394 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1395 (1 << HWTSTAMP_TX_ON);
1397 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1398 (1 << HWTSTAMP_FILTER_ALL);
1401 return ethtool_op_get_ts_info(ndev, info);
1405 #if !defined(CONFIG_M5272)
1407 static void fec_enet_get_pauseparam(struct net_device *ndev,
1408 struct ethtool_pauseparam *pause)
1410 struct fec_enet_private *fep = netdev_priv(ndev);
1412 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1413 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1414 pause->rx_pause = pause->tx_pause;
1417 static int fec_enet_set_pauseparam(struct net_device *ndev,
1418 struct ethtool_pauseparam *pause)
1420 struct fec_enet_private *fep = netdev_priv(ndev);
1422 if (pause->tx_pause != pause->rx_pause) {
1424 "hardware only support enable/disable both tx and rx");
1428 fep->pause_flag = 0;
1430 /* tx pause must be same as rx pause */
1431 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1432 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1434 if (pause->rx_pause || pause->autoneg) {
1435 fep->phy_dev->supported |= ADVERTISED_Pause;
1436 fep->phy_dev->advertising |= ADVERTISED_Pause;
1438 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1439 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1442 if (pause->autoneg) {
1443 if (netif_running(ndev))
1445 phy_start_aneg(fep->phy_dev);
1447 if (netif_running(ndev))
1448 fec_restart(ndev, 0);
1453 static const struct fec_stat {
1454 char name[ETH_GSTRING_LEN];
1458 { "tx_dropped", RMON_T_DROP },
1459 { "tx_packets", RMON_T_PACKETS },
1460 { "tx_broadcast", RMON_T_BC_PKT },
1461 { "tx_multicast", RMON_T_MC_PKT },
1462 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1463 { "tx_undersize", RMON_T_UNDERSIZE },
1464 { "tx_oversize", RMON_T_OVERSIZE },
1465 { "tx_fragment", RMON_T_FRAG },
1466 { "tx_jabber", RMON_T_JAB },
1467 { "tx_collision", RMON_T_COL },
1468 { "tx_64byte", RMON_T_P64 },
1469 { "tx_65to127byte", RMON_T_P65TO127 },
1470 { "tx_128to255byte", RMON_T_P128TO255 },
1471 { "tx_256to511byte", RMON_T_P256TO511 },
1472 { "tx_512to1023byte", RMON_T_P512TO1023 },
1473 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1474 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1475 { "tx_octets", RMON_T_OCTETS },
1478 { "IEEE_tx_drop", IEEE_T_DROP },
1479 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1480 { "IEEE_tx_1col", IEEE_T_1COL },
1481 { "IEEE_tx_mcol", IEEE_T_MCOL },
1482 { "IEEE_tx_def", IEEE_T_DEF },
1483 { "IEEE_tx_lcol", IEEE_T_LCOL },
1484 { "IEEE_tx_excol", IEEE_T_EXCOL },
1485 { "IEEE_tx_macerr", IEEE_T_MACERR },
1486 { "IEEE_tx_cserr", IEEE_T_CSERR },
1487 { "IEEE_tx_sqe", IEEE_T_SQE },
1488 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1489 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1492 { "rx_packets", RMON_R_PACKETS },
1493 { "rx_broadcast", RMON_R_BC_PKT },
1494 { "rx_multicast", RMON_R_MC_PKT },
1495 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1496 { "rx_undersize", RMON_R_UNDERSIZE },
1497 { "rx_oversize", RMON_R_OVERSIZE },
1498 { "rx_fragment", RMON_R_FRAG },
1499 { "rx_jabber", RMON_R_JAB },
1500 { "rx_64byte", RMON_R_P64 },
1501 { "rx_65to127byte", RMON_R_P65TO127 },
1502 { "rx_128to255byte", RMON_R_P128TO255 },
1503 { "rx_256to511byte", RMON_R_P256TO511 },
1504 { "rx_512to1023byte", RMON_R_P512TO1023 },
1505 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1506 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1507 { "rx_octets", RMON_R_OCTETS },
1510 { "IEEE_rx_drop", IEEE_R_DROP },
1511 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1512 { "IEEE_rx_crc", IEEE_R_CRC },
1513 { "IEEE_rx_align", IEEE_R_ALIGN },
1514 { "IEEE_rx_macerr", IEEE_R_MACERR },
1515 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1516 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1519 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1520 struct ethtool_stats *stats, u64 *data)
1522 struct fec_enet_private *fep = netdev_priv(dev);
1525 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1526 data[i] = readl(fep->hwp + fec_stats[i].offset);
1529 static void fec_enet_get_strings(struct net_device *netdev,
1530 u32 stringset, u8 *data)
1533 switch (stringset) {
1535 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1536 memcpy(data + i * ETH_GSTRING_LEN,
1537 fec_stats[i].name, ETH_GSTRING_LEN);
1542 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1546 return ARRAY_SIZE(fec_stats);
1551 #endif /* !defined(CONFIG_M5272) */
1553 static int fec_enet_nway_reset(struct net_device *dev)
1555 struct fec_enet_private *fep = netdev_priv(dev);
1556 struct phy_device *phydev = fep->phy_dev;
1561 return genphy_restart_aneg(phydev);
1564 static const struct ethtool_ops fec_enet_ethtool_ops = {
1565 #if !defined(CONFIG_M5272)
1566 .get_pauseparam = fec_enet_get_pauseparam,
1567 .set_pauseparam = fec_enet_set_pauseparam,
1569 .get_settings = fec_enet_get_settings,
1570 .set_settings = fec_enet_set_settings,
1571 .get_drvinfo = fec_enet_get_drvinfo,
1572 .get_link = ethtool_op_get_link,
1573 .get_ts_info = fec_enet_get_ts_info,
1574 .nway_reset = fec_enet_nway_reset,
1575 #ifndef CONFIG_M5272
1576 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1577 .get_strings = fec_enet_get_strings,
1578 .get_sset_count = fec_enet_get_sset_count,
1582 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1584 struct fec_enet_private *fep = netdev_priv(ndev);
1585 struct phy_device *phydev = fep->phy_dev;
1587 if (!netif_running(ndev))
1593 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1594 return fec_ptp_ioctl(ndev, rq, cmd);
1596 return phy_mii_ioctl(phydev, rq, cmd);
1599 static void fec_enet_free_buffers(struct net_device *ndev)
1601 struct fec_enet_private *fep = netdev_priv(ndev);
1603 struct sk_buff *skb;
1604 struct bufdesc *bdp;
1606 bdp = fep->rx_bd_base;
1607 for (i = 0; i < RX_RING_SIZE; i++) {
1608 skb = fep->rx_skbuff[i];
1610 if (bdp->cbd_bufaddr)
1611 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1612 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1615 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1618 bdp = fep->tx_bd_base;
1619 for (i = 0; i < TX_RING_SIZE; i++)
1620 kfree(fep->tx_bounce[i]);
1623 static int fec_enet_alloc_buffers(struct net_device *ndev)
1625 struct fec_enet_private *fep = netdev_priv(ndev);
1627 struct sk_buff *skb;
1628 struct bufdesc *bdp;
1630 bdp = fep->rx_bd_base;
1631 for (i = 0; i < RX_RING_SIZE; i++) {
1632 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1634 fec_enet_free_buffers(ndev);
1637 fep->rx_skbuff[i] = skb;
1639 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1640 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1641 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1643 if (fep->bufdesc_ex) {
1644 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1645 ebdp->cbd_esc = BD_ENET_RX_INT;
1648 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1651 /* Set the last buffer to wrap. */
1652 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1653 bdp->cbd_sc |= BD_SC_WRAP;
1655 bdp = fep->tx_bd_base;
1656 for (i = 0; i < TX_RING_SIZE; i++) {
1657 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1660 bdp->cbd_bufaddr = 0;
1662 if (fep->bufdesc_ex) {
1663 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1664 ebdp->cbd_esc = BD_ENET_TX_INT;
1667 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1670 /* Set the last buffer to wrap. */
1671 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1672 bdp->cbd_sc |= BD_SC_WRAP;
1678 fec_enet_open(struct net_device *ndev)
1680 struct fec_enet_private *fep = netdev_priv(ndev);
1683 napi_enable(&fep->napi);
1685 /* I should reset the ring buffers here, but I don't yet know
1686 * a simple way to do that.
1689 ret = fec_enet_alloc_buffers(ndev);
1693 /* Probe and connect to PHY when open the interface */
1694 ret = fec_enet_mii_probe(ndev);
1696 fec_enet_free_buffers(ndev);
1699 phy_start(fep->phy_dev);
1700 netif_start_queue(ndev);
1706 fec_enet_close(struct net_device *ndev)
1708 struct fec_enet_private *fep = netdev_priv(ndev);
1710 /* Don't know what to do yet. */
1711 napi_disable(&fep->napi);
1713 netif_stop_queue(ndev);
1717 phy_stop(fep->phy_dev);
1718 phy_disconnect(fep->phy_dev);
1721 fec_enet_free_buffers(ndev);
1726 /* Set or clear the multicast filter for this adaptor.
1727 * Skeleton taken from sunlance driver.
1728 * The CPM Ethernet implementation allows Multicast as well as individual
1729 * MAC address filtering. Some of the drivers check to make sure it is
1730 * a group multicast address, and discard those that are not. I guess I
1731 * will do the same for now, but just remove the test if you want
1732 * individual filtering as well (do the upper net layers want or support
1733 * this kind of feature?).
1736 #define HASH_BITS 6 /* #bits in hash */
1737 #define CRC32_POLY 0xEDB88320
1739 static void set_multicast_list(struct net_device *ndev)
1741 struct fec_enet_private *fep = netdev_priv(ndev);
1742 struct netdev_hw_addr *ha;
1743 unsigned int i, bit, data, crc, tmp;
1746 if (ndev->flags & IFF_PROMISC) {
1747 tmp = readl(fep->hwp + FEC_R_CNTRL);
1749 writel(tmp, fep->hwp + FEC_R_CNTRL);
1753 tmp = readl(fep->hwp + FEC_R_CNTRL);
1755 writel(tmp, fep->hwp + FEC_R_CNTRL);
1757 if (ndev->flags & IFF_ALLMULTI) {
1758 /* Catch all multicast addresses, so set the
1761 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1762 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1767 /* Clear filter and add the addresses in hash register
1769 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1770 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1772 netdev_for_each_mc_addr(ha, ndev) {
1773 /* calculate crc32 value of mac address */
1776 for (i = 0; i < ndev->addr_len; i++) {
1778 for (bit = 0; bit < 8; bit++, data >>= 1) {
1780 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1784 /* only upper 6 bits (HASH_BITS) are used
1785 * which point to specific bit in he hash registers
1787 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1790 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1791 tmp |= 1 << (hash - 32);
1792 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1794 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1796 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1801 /* Set a MAC change in hardware. */
1803 fec_set_mac_address(struct net_device *ndev, void *p)
1805 struct fec_enet_private *fep = netdev_priv(ndev);
1806 struct sockaddr *addr = p;
1808 if (!is_valid_ether_addr(addr->sa_data))
1809 return -EADDRNOTAVAIL;
1811 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1813 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1814 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1815 fep->hwp + FEC_ADDR_LOW);
1816 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1817 fep->hwp + FEC_ADDR_HIGH);
1821 #ifdef CONFIG_NET_POLL_CONTROLLER
1823 * fec_poll_controller - FEC Poll controller function
1824 * @dev: The FEC network adapter
1826 * Polled functionality used by netconsole and others in non interrupt mode
1829 static void fec_poll_controller(struct net_device *dev)
1832 struct fec_enet_private *fep = netdev_priv(dev);
1834 for (i = 0; i < FEC_IRQ_NUM; i++) {
1835 if (fep->irq[i] > 0) {
1836 disable_irq(fep->irq[i]);
1837 fec_enet_interrupt(fep->irq[i], dev);
1838 enable_irq(fep->irq[i]);
1844 static int fec_set_features(struct net_device *netdev,
1845 netdev_features_t features)
1847 struct fec_enet_private *fep = netdev_priv(netdev);
1848 netdev_features_t changed = features ^ netdev->features;
1850 netdev->features = features;
1852 /* Receive checksum has been changed */
1853 if (changed & NETIF_F_RXCSUM) {
1854 if (features & NETIF_F_RXCSUM)
1855 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1857 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1859 if (netif_running(netdev)) {
1861 fec_restart(netdev, fep->phy_dev->duplex);
1862 netif_wake_queue(netdev);
1864 fec_restart(netdev, fep->phy_dev->duplex);
1871 static const struct net_device_ops fec_netdev_ops = {
1872 .ndo_open = fec_enet_open,
1873 .ndo_stop = fec_enet_close,
1874 .ndo_start_xmit = fec_enet_start_xmit,
1875 .ndo_set_rx_mode = set_multicast_list,
1876 .ndo_change_mtu = eth_change_mtu,
1877 .ndo_validate_addr = eth_validate_addr,
1878 .ndo_tx_timeout = fec_timeout,
1879 .ndo_set_mac_address = fec_set_mac_address,
1880 .ndo_do_ioctl = fec_enet_ioctl,
1881 #ifdef CONFIG_NET_POLL_CONTROLLER
1882 .ndo_poll_controller = fec_poll_controller,
1884 .ndo_set_features = fec_set_features,
1888 * XXX: We need to clean up on failure exits here.
1891 static int fec_enet_init(struct net_device *ndev)
1893 struct fec_enet_private *fep = netdev_priv(ndev);
1894 const struct platform_device_id *id_entry =
1895 platform_get_device_id(fep->pdev);
1896 struct bufdesc *cbd_base;
1898 /* Allocate memory for buffer descriptors. */
1899 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1904 memset(cbd_base, 0, PAGE_SIZE);
1908 /* Get the Ethernet address */
1911 /* Set receive and transmit descriptor base. */
1912 fep->rx_bd_base = cbd_base;
1913 if (fep->bufdesc_ex)
1914 fep->tx_bd_base = (struct bufdesc *)
1915 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1917 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1919 /* The FEC Ethernet specific entries in the device structure */
1920 ndev->watchdog_timeo = TX_TIMEOUT;
1921 ndev->netdev_ops = &fec_netdev_ops;
1922 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1924 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1925 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1927 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
1928 /* enable hw accelerator */
1929 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1931 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1933 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1936 fec_restart(ndev, 0);
1942 static void fec_reset_phy(struct platform_device *pdev)
1946 struct device_node *np = pdev->dev.of_node;
1951 of_property_read_u32(np, "phy-reset-duration", &msec);
1952 /* A sane reset duration should not be longer than 1s */
1956 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1957 if (!gpio_is_valid(phy_reset))
1960 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1961 GPIOF_OUT_INIT_LOW, "phy-reset");
1963 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1967 gpio_set_value(phy_reset, 1);
1969 #else /* CONFIG_OF */
1970 static void fec_reset_phy(struct platform_device *pdev)
1973 * In case of platform probe, the reset has been done
1977 #endif /* CONFIG_OF */
1980 fec_probe(struct platform_device *pdev)
1982 struct fec_enet_private *fep;
1983 struct fec_platform_data *pdata;
1984 struct net_device *ndev;
1985 int i, irq, ret = 0;
1987 const struct of_device_id *of_id;
1990 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1992 pdev->id_entry = of_id->data;
1994 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1998 /* Init network device */
1999 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2003 SET_NETDEV_DEV(ndev, &pdev->dev);
2005 /* setup board info structure */
2006 fep = netdev_priv(ndev);
2008 #if !defined(CONFIG_M5272)
2009 /* default enable pause frame auto negotiation */
2010 if (pdev->id_entry &&
2011 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2012 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2015 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2016 if (IS_ERR(fep->hwp)) {
2017 ret = PTR_ERR(fep->hwp);
2018 goto failed_ioremap;
2022 fep->dev_id = dev_id++;
2024 fep->bufdesc_ex = 0;
2026 platform_set_drvdata(pdev, ndev);
2028 ret = of_get_phy_mode(pdev->dev.of_node);
2030 pdata = pdev->dev.platform_data;
2032 fep->phy_interface = pdata->phy;
2034 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2036 fep->phy_interface = ret;
2039 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2040 if (IS_ERR(fep->clk_ipg)) {
2041 ret = PTR_ERR(fep->clk_ipg);
2045 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2046 if (IS_ERR(fep->clk_ahb)) {
2047 ret = PTR_ERR(fep->clk_ahb);
2051 /* enet_out is optional, depends on board */
2052 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2053 if (IS_ERR(fep->clk_enet_out))
2054 fep->clk_enet_out = NULL;
2056 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2058 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2059 if (IS_ERR(fep->clk_ptp)) {
2060 fep->clk_ptp = NULL;
2061 fep->bufdesc_ex = 0;
2064 clk_prepare_enable(fep->clk_ahb);
2065 clk_prepare_enable(fep->clk_ipg);
2066 clk_prepare_enable(fep->clk_enet_out);
2067 clk_prepare_enable(fep->clk_ptp);
2069 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2070 if (!IS_ERR(fep->reg_phy)) {
2071 ret = regulator_enable(fep->reg_phy);
2074 "Failed to enable phy regulator: %d\n", ret);
2075 goto failed_regulator;
2078 fep->reg_phy = NULL;
2081 fec_reset_phy(pdev);
2083 if (fep->bufdesc_ex)
2086 ret = fec_enet_init(ndev);
2090 for (i = 0; i < FEC_IRQ_NUM; i++) {
2091 irq = platform_get_irq(pdev, i);
2098 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
2101 irq = platform_get_irq(pdev, i);
2102 free_irq(irq, ndev);
2108 ret = fec_enet_mii_init(pdev);
2110 goto failed_mii_init;
2112 /* Carrier starts down, phylib will bring it up */
2113 netif_carrier_off(ndev);
2115 ret = register_netdev(ndev);
2117 goto failed_register;
2119 if (fep->bufdesc_ex && fep->ptp_clock)
2120 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2122 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2126 fec_enet_mii_remove(fep);
2129 for (i = 0; i < FEC_IRQ_NUM; i++) {
2130 irq = platform_get_irq(pdev, i);
2132 free_irq(irq, ndev);
2136 regulator_disable(fep->reg_phy);
2138 clk_disable_unprepare(fep->clk_ahb);
2139 clk_disable_unprepare(fep->clk_ipg);
2140 clk_disable_unprepare(fep->clk_enet_out);
2141 clk_disable_unprepare(fep->clk_ptp);
2150 fec_drv_remove(struct platform_device *pdev)
2152 struct net_device *ndev = platform_get_drvdata(pdev);
2153 struct fec_enet_private *fep = netdev_priv(ndev);
2156 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2157 unregister_netdev(ndev);
2158 fec_enet_mii_remove(fep);
2159 del_timer_sync(&fep->time_keep);
2160 for (i = 0; i < FEC_IRQ_NUM; i++) {
2161 int irq = platform_get_irq(pdev, i);
2163 free_irq(irq, ndev);
2166 regulator_disable(fep->reg_phy);
2167 clk_disable_unprepare(fep->clk_ptp);
2169 ptp_clock_unregister(fep->ptp_clock);
2170 clk_disable_unprepare(fep->clk_enet_out);
2171 clk_disable_unprepare(fep->clk_ahb);
2172 clk_disable_unprepare(fep->clk_ipg);
2178 #ifdef CONFIG_PM_SLEEP
2180 fec_suspend(struct device *dev)
2182 struct net_device *ndev = dev_get_drvdata(dev);
2183 struct fec_enet_private *fep = netdev_priv(ndev);
2185 if (netif_running(ndev)) {
2187 netif_device_detach(ndev);
2189 clk_disable_unprepare(fep->clk_enet_out);
2190 clk_disable_unprepare(fep->clk_ahb);
2191 clk_disable_unprepare(fep->clk_ipg);
2194 regulator_disable(fep->reg_phy);
2200 fec_resume(struct device *dev)
2202 struct net_device *ndev = dev_get_drvdata(dev);
2203 struct fec_enet_private *fep = netdev_priv(ndev);
2207 ret = regulator_enable(fep->reg_phy);
2212 clk_prepare_enable(fep->clk_enet_out);
2213 clk_prepare_enable(fep->clk_ahb);
2214 clk_prepare_enable(fep->clk_ipg);
2215 if (netif_running(ndev)) {
2216 fec_restart(ndev, fep->full_duplex);
2217 netif_device_attach(ndev);
2222 #endif /* CONFIG_PM_SLEEP */
2224 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2226 static struct platform_driver fec_driver = {
2228 .name = DRIVER_NAME,
2229 .owner = THIS_MODULE,
2231 .of_match_table = fec_dt_ids,
2233 .id_table = fec_devtype,
2235 .remove = fec_drv_remove,
2238 module_platform_driver(fec_driver);
2240 MODULE_LICENSE("GPL");