2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63 #include <soc/imx/cpuidle.h>
65 #include <asm/cacheflush.h>
69 static void set_multicast_list(struct net_device *ndev);
70 static void fec_enet_itr_coal_init(struct net_device *ndev);
72 #define DRIVER_NAME "fec"
74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
76 /* Pause frame feild and FIFO threshold */
77 #define FEC_ENET_FCE (1 << 5)
78 #define FEC_ENET_RSEM_V 0x84
79 #define FEC_ENET_RSFL_V 16
80 #define FEC_ENET_RAEM_V 0x8
81 #define FEC_ENET_RAFL_V 0x8
82 #define FEC_ENET_OPD_V 0xFFF0
83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
85 static struct platform_device_id fec_devtype[] = {
87 /* keep it for coldfire */
92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR,
95 .driver_data = FEC_QUIRK_MIB_CLEAR,
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
107 .name = "mvf600-fec",
108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
110 .name = "imx6sx-fec",
111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
115 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
117 .name = "imx6ul-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
119 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
120 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
121 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
122 FEC_QUIRK_HAS_COALESCE,
127 MODULE_DEVICE_TABLE(platform, fec_devtype);
130 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
131 IMX27_FEC, /* runs on i.mx27/35/51 */
139 static const struct of_device_id fec_dt_ids[] = {
140 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
141 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
142 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
143 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
144 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
145 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
146 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
149 MODULE_DEVICE_TABLE(of, fec_dt_ids);
151 static unsigned char macaddr[ETH_ALEN];
152 module_param_array(macaddr, byte, NULL, 0);
153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
155 #if defined(CONFIG_M5272)
157 * Some hardware gets it MAC address out of local flash memory.
158 * if this is non-zero then assume it is the address to get MAC from.
160 #if defined(CONFIG_NETtel)
161 #define FEC_FLASHMAC 0xf0006006
162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
163 #define FEC_FLASHMAC 0xf0006000
164 #elif defined(CONFIG_CANCam)
165 #define FEC_FLASHMAC 0xf0020000
166 #elif defined (CONFIG_M5272C3)
167 #define FEC_FLASHMAC (0xffe04000 + 4)
168 #elif defined(CONFIG_MOD5272)
169 #define FEC_FLASHMAC 0xffc0406b
171 #define FEC_FLASHMAC 0
173 #endif /* CONFIG_M5272 */
175 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
177 #define PKT_MAXBUF_SIZE 1522
178 #define PKT_MINBUF_SIZE 64
179 #define PKT_MAXBLR_SIZE 1536
181 /* FEC receive acceleration */
182 #define FEC_RACC_IPDIS (1 << 1)
183 #define FEC_RACC_PRODIS (1 << 2)
184 #define FEC_RACC_SHIFT16 BIT(7)
185 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
187 /* MIB Control Register */
188 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
191 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
192 * size bits. Other FEC hardware does not, so we need to take that into
193 * account when setting it.
195 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
196 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
197 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
199 #define OPT_FRAME_SIZE 0
202 /* FEC MII MMFR bits definition */
203 #define FEC_MMFR_ST (1 << 30)
204 #define FEC_MMFR_OP_READ (2 << 28)
205 #define FEC_MMFR_OP_WRITE (1 << 28)
206 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
207 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
208 #define FEC_MMFR_TA (2 << 16)
209 #define FEC_MMFR_DATA(v) (v & 0xffff)
210 /* FEC ECR bits definition */
211 #define FEC_ECR_MAGICEN (1 << 2)
212 #define FEC_ECR_SLEEP (1 << 3)
214 #define FEC_MII_TIMEOUT 30000 /* us */
216 /* Transmitter timeout */
217 #define TX_TIMEOUT (2 * HZ)
219 #define FEC_PAUSE_FLAG_AUTONEG 0x1
220 #define FEC_PAUSE_FLAG_ENABLE 0x2
221 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
222 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
223 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
225 #define COPYBREAK_DEFAULT 256
227 #define TSO_HEADER_SIZE 128
228 /* Max number of allowed TCP segments for software TSO */
229 #define FEC_MAX_TSO_SEGS 100
230 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
232 #define IS_TSO_HEADER(txq, addr) \
233 ((addr >= txq->tso_hdrs_dma) && \
234 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
238 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
239 struct bufdesc_prop *bd)
241 return (bdp >= bd->last) ? bd->base
242 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
245 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
246 struct bufdesc_prop *bd)
248 return (bdp <= bd->base) ? bd->last
249 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
252 static int fec_enet_get_bd_index(struct bufdesc *bdp,
253 struct bufdesc_prop *bd)
255 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
258 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
262 entries = (((const char *)txq->dirty_tx -
263 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
265 return entries >= 0 ? entries : entries + txq->bd.ring_size;
268 static void swap_buffer(void *bufaddr, int len)
271 unsigned int *buf = bufaddr;
273 for (i = 0; i < len; i += 4, buf++)
277 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
280 unsigned int *src = src_buf;
281 unsigned int *dst = dst_buf;
283 for (i = 0; i < len; i += 4, src++, dst++)
287 static void fec_dump(struct net_device *ndev)
289 struct fec_enet_private *fep = netdev_priv(ndev);
291 struct fec_enet_priv_tx_q *txq;
294 netdev_info(ndev, "TX ring dump\n");
295 pr_info("Nr SC addr len SKB\n");
297 txq = fep->tx_queue[0];
301 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
303 bdp == txq->bd.cur ? 'S' : ' ',
304 bdp == txq->dirty_tx ? 'H' : ' ',
305 fec16_to_cpu(bdp->cbd_sc),
306 fec32_to_cpu(bdp->cbd_bufaddr),
307 fec16_to_cpu(bdp->cbd_datlen),
308 txq->tx_skbuff[index]);
309 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
311 } while (bdp != txq->bd.base);
314 static inline bool is_ipv4_pkt(struct sk_buff *skb)
316 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
320 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
322 /* Only run for packets requiring a checksum. */
323 if (skb->ip_summed != CHECKSUM_PARTIAL)
326 if (unlikely(skb_cow_head(skb, 0)))
329 if (is_ipv4_pkt(skb))
330 ip_hdr(skb)->check = 0;
331 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
336 static struct bufdesc *
337 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
339 struct net_device *ndev)
341 struct fec_enet_private *fep = netdev_priv(ndev);
342 struct bufdesc *bdp = txq->bd.cur;
343 struct bufdesc_ex *ebdp;
344 int nr_frags = skb_shinfo(skb)->nr_frags;
346 unsigned short status;
347 unsigned int estatus = 0;
348 skb_frag_t *this_frag;
354 for (frag = 0; frag < nr_frags; frag++) {
355 this_frag = &skb_shinfo(skb)->frags[frag];
356 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
357 ebdp = (struct bufdesc_ex *)bdp;
359 status = fec16_to_cpu(bdp->cbd_sc);
360 status &= ~BD_ENET_TX_STATS;
361 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
362 frag_len = skb_shinfo(skb)->frags[frag].size;
364 /* Handle the last BD specially */
365 if (frag == nr_frags - 1) {
366 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
367 if (fep->bufdesc_ex) {
368 estatus |= BD_ENET_TX_INT;
369 if (unlikely(skb_shinfo(skb)->tx_flags &
370 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
371 estatus |= BD_ENET_TX_TS;
375 if (fep->bufdesc_ex) {
376 if (fep->quirks & FEC_QUIRK_HAS_AVB)
377 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
378 if (skb->ip_summed == CHECKSUM_PARTIAL)
379 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
381 ebdp->cbd_esc = cpu_to_fec32(estatus);
384 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
386 index = fec_enet_get_bd_index(bdp, &txq->bd);
387 if (((unsigned long) bufaddr) & fep->tx_align ||
388 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
389 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
390 bufaddr = txq->tx_bounce[index];
392 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
393 swap_buffer(bufaddr, frag_len);
396 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
398 if (dma_mapping_error(&fep->pdev->dev, addr)) {
400 netdev_err(ndev, "Tx DMA memory map failed\n");
401 goto dma_mapping_error;
404 bdp->cbd_bufaddr = cpu_to_fec32(addr);
405 bdp->cbd_datlen = cpu_to_fec16(frag_len);
406 /* Make sure the updates to rest of the descriptor are
407 * performed before transferring ownership.
410 bdp->cbd_sc = cpu_to_fec16(status);
416 for (i = 0; i < frag; i++) {
417 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
418 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
419 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
421 return ERR_PTR(-ENOMEM);
424 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
425 struct sk_buff *skb, struct net_device *ndev)
427 struct fec_enet_private *fep = netdev_priv(ndev);
428 int nr_frags = skb_shinfo(skb)->nr_frags;
429 struct bufdesc *bdp, *last_bdp;
432 unsigned short status;
433 unsigned short buflen;
434 unsigned int estatus = 0;
438 entries_free = fec_enet_get_free_txdesc_num(txq);
439 if (entries_free < MAX_SKB_FRAGS + 1) {
440 dev_kfree_skb_any(skb);
442 netdev_err(ndev, "NOT enough BD for SG!\n");
446 /* Protocol checksum off-load for TCP and UDP. */
447 if (fec_enet_clear_csum(skb, ndev)) {
448 dev_kfree_skb_any(skb);
452 /* Fill in a Tx ring entry */
455 status = fec16_to_cpu(bdp->cbd_sc);
456 status &= ~BD_ENET_TX_STATS;
458 /* Set buffer length and buffer pointer */
460 buflen = skb_headlen(skb);
462 index = fec_enet_get_bd_index(bdp, &txq->bd);
463 if (((unsigned long) bufaddr) & fep->tx_align ||
464 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
465 memcpy(txq->tx_bounce[index], skb->data, buflen);
466 bufaddr = txq->tx_bounce[index];
468 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
469 swap_buffer(bufaddr, buflen);
472 /* Push the data cache so the CPM does not get stale memory data. */
473 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
474 if (dma_mapping_error(&fep->pdev->dev, addr)) {
475 dev_kfree_skb_any(skb);
477 netdev_err(ndev, "Tx DMA memory map failed\n");
482 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
483 if (IS_ERR(last_bdp)) {
484 dma_unmap_single(&fep->pdev->dev, addr,
485 buflen, DMA_TO_DEVICE);
486 dev_kfree_skb_any(skb);
490 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
491 if (fep->bufdesc_ex) {
492 estatus = BD_ENET_TX_INT;
493 if (unlikely(skb_shinfo(skb)->tx_flags &
494 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
495 estatus |= BD_ENET_TX_TS;
498 bdp->cbd_bufaddr = cpu_to_fec32(addr);
499 bdp->cbd_datlen = cpu_to_fec16(buflen);
501 if (fep->bufdesc_ex) {
503 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
505 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
507 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
509 if (fep->quirks & FEC_QUIRK_HAS_AVB)
510 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
512 if (skb->ip_summed == CHECKSUM_PARTIAL)
513 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
516 ebdp->cbd_esc = cpu_to_fec32(estatus);
519 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
520 /* Save skb pointer */
521 txq->tx_skbuff[index] = skb;
523 /* Make sure the updates to rest of the descriptor are performed before
524 * transferring ownership.
528 /* Send it on its way. Tell FEC it's ready, interrupt when done,
529 * it's the last BD of the frame, and to put the CRC on the end.
531 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
532 bdp->cbd_sc = cpu_to_fec16(status);
534 /* If this was the last BD in the ring, start at the beginning again. */
535 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
537 skb_tx_timestamp(skb);
539 /* Make sure the update to bdp and tx_skbuff are performed before
545 /* Trigger transmission start */
546 writel(0, txq->bd.reg_desc_active);
552 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
553 struct net_device *ndev,
554 struct bufdesc *bdp, int index, char *data,
555 int size, bool last_tcp, bool is_last)
557 struct fec_enet_private *fep = netdev_priv(ndev);
558 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
559 unsigned short status;
560 unsigned int estatus = 0;
563 status = fec16_to_cpu(bdp->cbd_sc);
564 status &= ~BD_ENET_TX_STATS;
566 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
568 if (((unsigned long) data) & fep->tx_align ||
569 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
570 memcpy(txq->tx_bounce[index], data, size);
571 data = txq->tx_bounce[index];
573 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
574 swap_buffer(data, size);
577 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
578 if (dma_mapping_error(&fep->pdev->dev, addr)) {
579 dev_kfree_skb_any(skb);
581 netdev_err(ndev, "Tx DMA memory map failed\n");
582 return NETDEV_TX_BUSY;
585 bdp->cbd_datlen = cpu_to_fec16(size);
586 bdp->cbd_bufaddr = cpu_to_fec32(addr);
588 if (fep->bufdesc_ex) {
589 if (fep->quirks & FEC_QUIRK_HAS_AVB)
590 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
591 if (skb->ip_summed == CHECKSUM_PARTIAL)
592 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
594 ebdp->cbd_esc = cpu_to_fec32(estatus);
597 /* Handle the last BD specially */
599 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
601 status |= BD_ENET_TX_INTR;
603 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
606 bdp->cbd_sc = cpu_to_fec16(status);
612 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
613 struct sk_buff *skb, struct net_device *ndev,
614 struct bufdesc *bdp, int index)
616 struct fec_enet_private *fep = netdev_priv(ndev);
617 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
618 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
620 unsigned long dmabuf;
621 unsigned short status;
622 unsigned int estatus = 0;
624 status = fec16_to_cpu(bdp->cbd_sc);
625 status &= ~BD_ENET_TX_STATS;
626 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
628 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
629 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
630 if (((unsigned long)bufaddr) & fep->tx_align ||
631 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
632 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
633 bufaddr = txq->tx_bounce[index];
635 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
636 swap_buffer(bufaddr, hdr_len);
638 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
639 hdr_len, DMA_TO_DEVICE);
640 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
641 dev_kfree_skb_any(skb);
643 netdev_err(ndev, "Tx DMA memory map failed\n");
644 return NETDEV_TX_BUSY;
648 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
649 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
651 if (fep->bufdesc_ex) {
652 if (fep->quirks & FEC_QUIRK_HAS_AVB)
653 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
654 if (skb->ip_summed == CHECKSUM_PARTIAL)
655 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
657 ebdp->cbd_esc = cpu_to_fec32(estatus);
660 bdp->cbd_sc = cpu_to_fec16(status);
665 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
667 struct net_device *ndev)
669 struct fec_enet_private *fep = netdev_priv(ndev);
670 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
671 int total_len, data_left;
672 struct bufdesc *bdp = txq->bd.cur;
674 unsigned int index = 0;
677 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
678 dev_kfree_skb_any(skb);
680 netdev_err(ndev, "NOT enough BD for TSO!\n");
684 /* Protocol checksum off-load for TCP and UDP. */
685 if (fec_enet_clear_csum(skb, ndev)) {
686 dev_kfree_skb_any(skb);
690 /* Initialize the TSO handler, and prepare the first payload */
691 tso_start(skb, &tso);
693 total_len = skb->len - hdr_len;
694 while (total_len > 0) {
697 index = fec_enet_get_bd_index(bdp, &txq->bd);
698 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
699 total_len -= data_left;
701 /* prepare packet headers: MAC + IP + TCP */
702 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
703 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
704 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
708 while (data_left > 0) {
711 size = min_t(int, tso.size, data_left);
712 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
713 index = fec_enet_get_bd_index(bdp, &txq->bd);
714 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
723 tso_build_data(skb, &tso, size);
726 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
729 /* Save skb pointer */
730 txq->tx_skbuff[index] = skb;
732 skb_tx_timestamp(skb);
735 /* Trigger transmission start */
736 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
737 !readl(txq->bd.reg_desc_active) ||
738 !readl(txq->bd.reg_desc_active) ||
739 !readl(txq->bd.reg_desc_active) ||
740 !readl(txq->bd.reg_desc_active))
741 writel(0, txq->bd.reg_desc_active);
746 /* TODO: Release all used data descriptors for TSO */
751 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
753 struct fec_enet_private *fep = netdev_priv(ndev);
755 unsigned short queue;
756 struct fec_enet_priv_tx_q *txq;
757 struct netdev_queue *nq;
760 queue = skb_get_queue_mapping(skb);
761 txq = fep->tx_queue[queue];
762 nq = netdev_get_tx_queue(ndev, queue);
765 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
767 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
771 entries_free = fec_enet_get_free_txdesc_num(txq);
772 if (entries_free <= txq->tx_stop_threshold)
773 netif_tx_stop_queue(nq);
778 /* Init RX & TX buffer descriptors
780 static void fec_enet_bd_init(struct net_device *dev)
782 struct fec_enet_private *fep = netdev_priv(dev);
783 struct fec_enet_priv_tx_q *txq;
784 struct fec_enet_priv_rx_q *rxq;
789 for (q = 0; q < fep->num_rx_queues; q++) {
790 /* Initialize the receive buffer descriptors. */
791 rxq = fep->rx_queue[q];
794 for (i = 0; i < rxq->bd.ring_size; i++) {
796 /* Initialize the BD for every fragment in the page. */
797 if (bdp->cbd_bufaddr)
798 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
800 bdp->cbd_sc = cpu_to_fec16(0);
801 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
804 /* Set the last buffer to wrap */
805 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
806 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
808 rxq->bd.cur = rxq->bd.base;
811 for (q = 0; q < fep->num_tx_queues; q++) {
812 /* ...and the same for transmit */
813 txq = fep->tx_queue[q];
817 for (i = 0; i < txq->bd.ring_size; i++) {
818 /* Initialize the BD for every fragment in the page. */
819 bdp->cbd_sc = cpu_to_fec16(0);
820 if (txq->tx_skbuff[i]) {
821 dev_kfree_skb_any(txq->tx_skbuff[i]);
822 txq->tx_skbuff[i] = NULL;
824 bdp->cbd_bufaddr = cpu_to_fec32(0);
825 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
828 /* Set the last buffer to wrap */
829 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
830 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
835 static void fec_enet_active_rxring(struct net_device *ndev)
837 struct fec_enet_private *fep = netdev_priv(ndev);
840 for (i = 0; i < fep->num_rx_queues; i++)
841 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
844 static void fec_enet_enable_ring(struct net_device *ndev)
846 struct fec_enet_private *fep = netdev_priv(ndev);
847 struct fec_enet_priv_tx_q *txq;
848 struct fec_enet_priv_rx_q *rxq;
851 for (i = 0; i < fep->num_rx_queues; i++) {
852 rxq = fep->rx_queue[i];
853 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
854 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
858 writel(RCMR_MATCHEN | RCMR_CMP(i),
859 fep->hwp + FEC_RCMR(i));
862 for (i = 0; i < fep->num_tx_queues; i++) {
863 txq = fep->tx_queue[i];
864 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
868 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
869 fep->hwp + FEC_DMA_CFG(i));
873 static void fec_enet_reset_skb(struct net_device *ndev)
875 struct fec_enet_private *fep = netdev_priv(ndev);
876 struct fec_enet_priv_tx_q *txq;
879 for (i = 0; i < fep->num_tx_queues; i++) {
880 txq = fep->tx_queue[i];
882 for (j = 0; j < txq->bd.ring_size; j++) {
883 if (txq->tx_skbuff[j]) {
884 dev_kfree_skb_any(txq->tx_skbuff[j]);
885 txq->tx_skbuff[j] = NULL;
892 * This function is called to start or restart the FEC during a link
893 * change, transmit timeout, or to reconfigure the FEC. The network
894 * packet processing for this device must be stopped before this call.
897 fec_restart(struct net_device *ndev)
899 struct fec_enet_private *fep = netdev_priv(ndev);
902 u32 rcntl = OPT_FRAME_SIZE | 0x04;
903 u32 ecntl = 0x2; /* ETHEREN */
905 /* Whack a reset. We should wait for this.
906 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
907 * instead of reset MAC itself.
909 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
910 writel(0, fep->hwp + FEC_ECNTRL);
912 writel(1, fep->hwp + FEC_ECNTRL);
917 * enet-mac reset will reset mac address registers too,
918 * so need to reconfigure it.
920 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
921 writel((__force u32)cpu_to_be32(temp_mac[0]),
922 fep->hwp + FEC_ADDR_LOW);
923 writel((__force u32)cpu_to_be32(temp_mac[1]),
924 fep->hwp + FEC_ADDR_HIGH);
926 /* Clear any outstanding interrupt. */
927 writel(0xffffffff, fep->hwp + FEC_IEVENT);
929 fec_enet_bd_init(ndev);
931 fec_enet_enable_ring(ndev);
933 /* Reset tx SKB buffers. */
934 fec_enet_reset_skb(ndev);
936 /* Enable MII mode */
937 if (fep->full_duplex == DUPLEX_FULL) {
939 writel(0x04, fep->hwp + FEC_X_CNTRL);
943 writel(0x0, fep->hwp + FEC_X_CNTRL);
947 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
949 #if !defined(CONFIG_M5272)
950 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
951 val = readl(fep->hwp + FEC_RACC);
952 /* align IP header */
953 val |= FEC_RACC_SHIFT16;
954 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
955 /* set RX checksum */
956 val |= FEC_RACC_OPTIONS;
958 val &= ~FEC_RACC_OPTIONS;
959 writel(val, fep->hwp + FEC_RACC);
960 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
965 * The phy interface and speed need to get configured
966 * differently on enet-mac.
968 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
969 /* Enable flow control and length check */
970 rcntl |= 0x40000000 | 0x00000020;
972 /* RGMII, RMII or MII */
973 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
974 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
975 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
976 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
978 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
983 /* 1G, 100M or 10M */
985 if (ndev->phydev->speed == SPEED_1000)
987 else if (ndev->phydev->speed == SPEED_100)
993 #ifdef FEC_MIIGSK_ENR
994 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
996 /* disable the gasket and wait */
997 writel(0, fep->hwp + FEC_MIIGSK_ENR);
998 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1002 * configure the gasket:
1003 * RMII, 50 MHz, no loopback, no echo
1004 * MII, 25 MHz, no loopback, no echo
1006 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1007 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1008 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1009 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1010 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1012 /* re-enable the gasket */
1013 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1018 #if !defined(CONFIG_M5272)
1019 /* enable pause frame*/
1020 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1021 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1022 ndev->phydev && ndev->phydev->pause)) {
1023 rcntl |= FEC_ENET_FCE;
1025 /* set FIFO threshold parameter to reduce overrun */
1026 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1027 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1028 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1029 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1032 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1034 rcntl &= ~FEC_ENET_FCE;
1036 #endif /* !defined(CONFIG_M5272) */
1038 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1040 /* Setup multicast filter. */
1041 set_multicast_list(ndev);
1042 #ifndef CONFIG_M5272
1043 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1044 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1047 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1048 /* enable ENET endian swap */
1050 /* enable ENET store and forward mode */
1051 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1054 if (fep->bufdesc_ex)
1057 #ifndef CONFIG_M5272
1058 /* Enable the MIB statistic event counters */
1059 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1062 /* And last, enable the transmit and receive processing */
1063 writel(ecntl, fep->hwp + FEC_ECNTRL);
1064 fec_enet_active_rxring(ndev);
1066 if (fep->bufdesc_ex)
1067 fec_ptp_start_cyclecounter(ndev);
1069 /* Enable interrupts we wish to service */
1071 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1073 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1075 /* Init the interrupt coalescing */
1076 fec_enet_itr_coal_init(ndev);
1081 fec_stop(struct net_device *ndev)
1083 struct fec_enet_private *fep = netdev_priv(ndev);
1084 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1085 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1088 /* We cannot expect a graceful transmit stop without link !!! */
1090 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1092 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1093 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1096 /* Whack a reset. We should wait for this.
1097 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1098 * instead of reset MAC itself.
1100 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1101 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1102 writel(0, fep->hwp + FEC_ECNTRL);
1104 writel(1, fep->hwp + FEC_ECNTRL);
1107 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1109 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1110 val = readl(fep->hwp + FEC_ECNTRL);
1111 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1112 writel(val, fep->hwp + FEC_ECNTRL);
1114 if (pdata && pdata->sleep_mode_enable)
1115 pdata->sleep_mode_enable(true);
1117 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1119 /* We have to keep ENET enabled to have MII interrupt stay working */
1120 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1121 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1122 writel(2, fep->hwp + FEC_ECNTRL);
1123 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1129 fec_timeout(struct net_device *ndev)
1131 struct fec_enet_private *fep = netdev_priv(ndev);
1135 ndev->stats.tx_errors++;
1137 schedule_work(&fep->tx_timeout_work);
1140 static void fec_enet_timeout_work(struct work_struct *work)
1142 struct fec_enet_private *fep =
1143 container_of(work, struct fec_enet_private, tx_timeout_work);
1144 struct net_device *ndev = fep->netdev;
1147 if (netif_device_present(ndev) || netif_running(ndev)) {
1148 napi_disable(&fep->napi);
1149 netif_tx_lock_bh(ndev);
1151 netif_wake_queue(ndev);
1152 netif_tx_unlock_bh(ndev);
1153 napi_enable(&fep->napi);
1159 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1160 struct skb_shared_hwtstamps *hwtstamps)
1162 unsigned long flags;
1165 spin_lock_irqsave(&fep->tmreg_lock, flags);
1166 ns = timecounter_cyc2time(&fep->tc, ts);
1167 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1169 memset(hwtstamps, 0, sizeof(*hwtstamps));
1170 hwtstamps->hwtstamp = ns_to_ktime(ns);
1174 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1176 struct fec_enet_private *fep;
1177 struct bufdesc *bdp;
1178 unsigned short status;
1179 struct sk_buff *skb;
1180 struct fec_enet_priv_tx_q *txq;
1181 struct netdev_queue *nq;
1185 fep = netdev_priv(ndev);
1187 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1189 txq = fep->tx_queue[queue_id];
1190 /* get next bdp of dirty_tx */
1191 nq = netdev_get_tx_queue(ndev, queue_id);
1192 bdp = txq->dirty_tx;
1194 /* get next bdp of dirty_tx */
1195 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1197 while (bdp != READ_ONCE(txq->bd.cur)) {
1198 /* Order the load of bd.cur and cbd_sc */
1200 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1201 if (status & BD_ENET_TX_READY)
1204 index = fec_enet_get_bd_index(bdp, &txq->bd);
1206 skb = txq->tx_skbuff[index];
1207 txq->tx_skbuff[index] = NULL;
1208 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1209 dma_unmap_single(&fep->pdev->dev,
1210 fec32_to_cpu(bdp->cbd_bufaddr),
1211 fec16_to_cpu(bdp->cbd_datlen),
1213 bdp->cbd_bufaddr = cpu_to_fec32(0);
1217 /* Check for errors. */
1218 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1219 BD_ENET_TX_RL | BD_ENET_TX_UN |
1221 ndev->stats.tx_errors++;
1222 if (status & BD_ENET_TX_HB) /* No heartbeat */
1223 ndev->stats.tx_heartbeat_errors++;
1224 if (status & BD_ENET_TX_LC) /* Late collision */
1225 ndev->stats.tx_window_errors++;
1226 if (status & BD_ENET_TX_RL) /* Retrans limit */
1227 ndev->stats.tx_aborted_errors++;
1228 if (status & BD_ENET_TX_UN) /* Underrun */
1229 ndev->stats.tx_fifo_errors++;
1230 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1231 ndev->stats.tx_carrier_errors++;
1233 ndev->stats.tx_packets++;
1234 ndev->stats.tx_bytes += skb->len;
1237 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1239 struct skb_shared_hwtstamps shhwtstamps;
1240 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1242 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1243 skb_tstamp_tx(skb, &shhwtstamps);
1246 /* Deferred means some collisions occurred during transmit,
1247 * but we eventually sent the packet OK.
1249 if (status & BD_ENET_TX_DEF)
1250 ndev->stats.collisions++;
1252 /* Free the sk buffer associated with this last transmit */
1253 dev_kfree_skb_any(skb);
1255 /* Make sure the update to bdp and tx_skbuff are performed
1259 txq->dirty_tx = bdp;
1261 /* Update pointer to next buffer descriptor to be transmitted */
1262 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1264 /* Since we have freed up a buffer, the ring is no longer full
1266 if (netif_queue_stopped(ndev)) {
1267 entries_free = fec_enet_get_free_txdesc_num(txq);
1268 if (entries_free >= txq->tx_wake_threshold)
1269 netif_tx_wake_queue(nq);
1273 /* ERR006358: Keep the transmitter going */
1274 if (bdp != txq->bd.cur &&
1275 readl(txq->bd.reg_desc_active) == 0)
1276 writel(0, txq->bd.reg_desc_active);
1280 fec_enet_tx(struct net_device *ndev)
1282 struct fec_enet_private *fep = netdev_priv(ndev);
1284 /* First process class A queue, then Class B and Best Effort queue */
1285 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1286 clear_bit(queue_id, &fep->work_tx);
1287 fec_enet_tx_queue(ndev, queue_id);
1293 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1295 struct fec_enet_private *fep = netdev_priv(ndev);
1298 off = ((unsigned long)skb->data) & fep->rx_align;
1300 skb_reserve(skb, fep->rx_align + 1 - off);
1302 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1303 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1304 if (net_ratelimit())
1305 netdev_err(ndev, "Rx DMA memory map failed\n");
1312 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1313 struct bufdesc *bdp, u32 length, bool swap)
1315 struct fec_enet_private *fep = netdev_priv(ndev);
1316 struct sk_buff *new_skb;
1318 if (length > fep->rx_copybreak)
1321 new_skb = netdev_alloc_skb(ndev, length);
1325 dma_sync_single_for_cpu(&fep->pdev->dev,
1326 fec32_to_cpu(bdp->cbd_bufaddr),
1327 FEC_ENET_RX_FRSIZE - fep->rx_align,
1330 memcpy(new_skb->data, (*skb)->data, length);
1332 swap_buffer2(new_skb->data, (*skb)->data, length);
1338 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1339 * When we update through the ring, if the next incoming buffer has
1340 * not been given to the system, we just set the empty indicator,
1341 * effectively tossing the packet.
1344 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1346 struct fec_enet_private *fep = netdev_priv(ndev);
1347 struct fec_enet_priv_rx_q *rxq;
1348 struct bufdesc *bdp;
1349 unsigned short status;
1350 struct sk_buff *skb_new = NULL;
1351 struct sk_buff *skb;
1354 int pkt_received = 0;
1355 struct bufdesc_ex *ebdp = NULL;
1356 bool vlan_packet_rcvd = false;
1360 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1365 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1366 rxq = fep->rx_queue[queue_id];
1368 /* First, grab all of the stats for the incoming packet.
1369 * These get messed up if we get called due to a busy condition.
1373 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1375 if (pkt_received >= budget)
1379 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1381 /* Check for errors. */
1382 status ^= BD_ENET_RX_LAST;
1383 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1384 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1386 ndev->stats.rx_errors++;
1387 if (status & BD_ENET_RX_OV) {
1389 ndev->stats.rx_fifo_errors++;
1390 goto rx_processing_done;
1392 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1393 | BD_ENET_RX_LAST)) {
1394 /* Frame too long or too short. */
1395 ndev->stats.rx_length_errors++;
1396 if (status & BD_ENET_RX_LAST)
1397 netdev_err(ndev, "rcv is not +last\n");
1399 if (status & BD_ENET_RX_CR) /* CRC Error */
1400 ndev->stats.rx_crc_errors++;
1401 /* Report late collisions as a frame error. */
1402 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1403 ndev->stats.rx_frame_errors++;
1404 goto rx_processing_done;
1407 /* Process the incoming frame. */
1408 ndev->stats.rx_packets++;
1409 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1410 ndev->stats.rx_bytes += pkt_len;
1412 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1413 skb = rxq->rx_skbuff[index];
1415 /* The packet length includes FCS, but we don't want to
1416 * include that when passing upstream as it messes up
1417 * bridging applications.
1419 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1421 if (!is_copybreak) {
1422 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1423 if (unlikely(!skb_new)) {
1424 ndev->stats.rx_dropped++;
1425 goto rx_processing_done;
1427 dma_unmap_single(&fep->pdev->dev,
1428 fec32_to_cpu(bdp->cbd_bufaddr),
1429 FEC_ENET_RX_FRSIZE - fep->rx_align,
1433 prefetch(skb->data - NET_IP_ALIGN);
1434 skb_put(skb, pkt_len - 4);
1437 if (!is_copybreak && need_swap)
1438 swap_buffer(data, pkt_len);
1440 #if !defined(CONFIG_M5272)
1441 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1442 data = skb_pull_inline(skb, 2);
1445 /* Extract the enhanced buffer descriptor */
1447 if (fep->bufdesc_ex)
1448 ebdp = (struct bufdesc_ex *)bdp;
1450 /* If this is a VLAN packet remove the VLAN Tag */
1451 vlan_packet_rcvd = false;
1452 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1454 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1455 /* Push and remove the vlan tag */
1456 struct vlan_hdr *vlan_header =
1457 (struct vlan_hdr *) (data + ETH_HLEN);
1458 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1460 vlan_packet_rcvd = true;
1462 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1463 skb_pull(skb, VLAN_HLEN);
1466 skb->protocol = eth_type_trans(skb, ndev);
1468 /* Get receive timestamp from the skb */
1469 if (fep->hwts_rx_en && fep->bufdesc_ex)
1470 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1471 skb_hwtstamps(skb));
1473 if (fep->bufdesc_ex &&
1474 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1475 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1476 /* don't check it */
1477 skb->ip_summed = CHECKSUM_UNNECESSARY;
1479 skb_checksum_none_assert(skb);
1483 /* Handle received VLAN packets */
1484 if (vlan_packet_rcvd)
1485 __vlan_hwaccel_put_tag(skb,
1489 napi_gro_receive(&fep->napi, skb);
1492 dma_sync_single_for_device(&fep->pdev->dev,
1493 fec32_to_cpu(bdp->cbd_bufaddr),
1494 FEC_ENET_RX_FRSIZE - fep->rx_align,
1497 rxq->rx_skbuff[index] = skb_new;
1498 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1502 /* Clear the status flags for this buffer */
1503 status &= ~BD_ENET_RX_STATS;
1505 /* Mark the buffer empty */
1506 status |= BD_ENET_RX_EMPTY;
1508 if (fep->bufdesc_ex) {
1509 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1511 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1515 /* Make sure the updates to rest of the descriptor are
1516 * performed before transferring ownership.
1519 bdp->cbd_sc = cpu_to_fec16(status);
1521 /* Update BD pointer to next entry */
1522 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1524 /* Doing this here will keep the FEC running while we process
1525 * incoming frames. On a heavily loaded network, we should be
1526 * able to keep up at the expense of system resources.
1528 writel(0, rxq->bd.reg_desc_active);
1531 return pkt_received;
1535 fec_enet_rx(struct net_device *ndev, int budget)
1537 int pkt_received = 0;
1539 struct fec_enet_private *fep = netdev_priv(ndev);
1541 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1544 ret = fec_enet_rx_queue(ndev,
1545 budget - pkt_received, queue_id);
1547 if (ret < budget - pkt_received)
1548 clear_bit(queue_id, &fep->work_rx);
1550 pkt_received += ret;
1552 return pkt_received;
1556 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1558 if (int_events == 0)
1561 if (int_events & FEC_ENET_RXF)
1562 fep->work_rx |= (1 << 2);
1563 if (int_events & FEC_ENET_RXF_1)
1564 fep->work_rx |= (1 << 0);
1565 if (int_events & FEC_ENET_RXF_2)
1566 fep->work_rx |= (1 << 1);
1568 if (int_events & FEC_ENET_TXF)
1569 fep->work_tx |= (1 << 2);
1570 if (int_events & FEC_ENET_TXF_1)
1571 fep->work_tx |= (1 << 0);
1572 if (int_events & FEC_ENET_TXF_2)
1573 fep->work_tx |= (1 << 1);
1579 fec_enet_interrupt(int irq, void *dev_id)
1581 struct net_device *ndev = dev_id;
1582 struct fec_enet_private *fep = netdev_priv(ndev);
1584 irqreturn_t ret = IRQ_NONE;
1586 int_events = readl(fep->hwp + FEC_IEVENT);
1587 writel(int_events, fep->hwp + FEC_IEVENT);
1588 fec_enet_collect_events(fep, int_events);
1590 if ((fep->work_tx || fep->work_rx) && fep->link) {
1593 if (napi_schedule_prep(&fep->napi)) {
1594 /* Disable the NAPI interrupts */
1595 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1596 __napi_schedule(&fep->napi);
1600 if (int_events & FEC_ENET_MII) {
1602 complete(&fep->mdio_done);
1606 fec_ptp_check_pps_event(fep);
1611 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1613 struct net_device *ndev = napi->dev;
1614 struct fec_enet_private *fep = netdev_priv(ndev);
1617 pkts = fec_enet_rx(ndev, budget);
1621 if (pkts < budget) {
1622 napi_complete_done(napi, pkts);
1623 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1628 /* ------------------------------------------------------------------------- */
1629 static void fec_get_mac(struct net_device *ndev)
1631 struct fec_enet_private *fep = netdev_priv(ndev);
1632 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1633 unsigned char *iap, tmpaddr[ETH_ALEN];
1636 * try to get mac address in following order:
1638 * 1) module parameter via kernel command line in form
1639 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1644 * 2) from device tree data
1646 if (!is_valid_ether_addr(iap)) {
1647 struct device_node *np = fep->pdev->dev.of_node;
1649 const char *mac = of_get_mac_address(np);
1651 iap = (unsigned char *) mac;
1656 * 3) from flash or fuse (via platform data)
1658 if (!is_valid_ether_addr(iap)) {
1661 iap = (unsigned char *)FEC_FLASHMAC;
1664 iap = (unsigned char *)&pdata->mac;
1669 * 4) FEC mac registers set by bootloader
1671 if (!is_valid_ether_addr(iap)) {
1672 *((__be32 *) &tmpaddr[0]) =
1673 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1674 *((__be16 *) &tmpaddr[4]) =
1675 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1680 * 5) random mac address
1682 if (!is_valid_ether_addr(iap)) {
1683 /* Report it and use a random ethernet address instead */
1684 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1685 eth_hw_addr_random(ndev);
1686 netdev_info(ndev, "Using random MAC address: %pM\n",
1691 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1693 /* Adjust MAC if using macaddr */
1695 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1698 /* ------------------------------------------------------------------------- */
1703 static void fec_enet_adjust_link(struct net_device *ndev)
1705 struct fec_enet_private *fep = netdev_priv(ndev);
1706 struct phy_device *phy_dev = ndev->phydev;
1707 int status_change = 0;
1709 /* Prevent a state halted on mii error */
1710 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1711 phy_dev->state = PHY_RESUMING;
1716 * If the netdev is down, or is going down, we're not interested
1717 * in link state events, so just mark our idea of the link as down
1718 * and ignore the event.
1720 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1722 } else if (phy_dev->link) {
1724 fep->link = phy_dev->link;
1728 if (fep->full_duplex != phy_dev->duplex) {
1729 fep->full_duplex = phy_dev->duplex;
1733 if (phy_dev->speed != fep->speed) {
1734 fep->speed = phy_dev->speed;
1738 /* if any of the above changed restart the FEC */
1739 if (status_change) {
1740 napi_disable(&fep->napi);
1741 netif_tx_lock_bh(ndev);
1743 netif_wake_queue(ndev);
1744 netif_tx_unlock_bh(ndev);
1745 napi_enable(&fep->napi);
1749 napi_disable(&fep->napi);
1750 netif_tx_lock_bh(ndev);
1752 netif_tx_unlock_bh(ndev);
1753 napi_enable(&fep->napi);
1754 fep->link = phy_dev->link;
1760 phy_print_status(phy_dev);
1763 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1765 struct fec_enet_private *fep = bus->priv;
1766 struct device *dev = &fep->pdev->dev;
1767 unsigned long time_left;
1770 ret = pm_runtime_get_sync(dev);
1774 fep->mii_timeout = 0;
1775 reinit_completion(&fep->mdio_done);
1777 /* start a read op */
1778 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1779 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1780 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1782 /* wait for end of transfer */
1783 time_left = wait_for_completion_timeout(&fep->mdio_done,
1784 usecs_to_jiffies(FEC_MII_TIMEOUT));
1785 if (time_left == 0) {
1786 fep->mii_timeout = 1;
1787 netdev_err(fep->netdev, "MDIO read timeout\n");
1792 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1795 pm_runtime_mark_last_busy(dev);
1796 pm_runtime_put_autosuspend(dev);
1801 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1804 struct fec_enet_private *fep = bus->priv;
1805 struct device *dev = &fep->pdev->dev;
1806 unsigned long time_left;
1809 ret = pm_runtime_get_sync(dev);
1815 fep->mii_timeout = 0;
1816 reinit_completion(&fep->mdio_done);
1818 /* start a write op */
1819 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1820 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1821 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1822 fep->hwp + FEC_MII_DATA);
1824 /* wait for end of transfer */
1825 time_left = wait_for_completion_timeout(&fep->mdio_done,
1826 usecs_to_jiffies(FEC_MII_TIMEOUT));
1827 if (time_left == 0) {
1828 fep->mii_timeout = 1;
1829 netdev_err(fep->netdev, "MDIO write timeout\n");
1833 pm_runtime_mark_last_busy(dev);
1834 pm_runtime_put_autosuspend(dev);
1839 static void fec_reset_phy(struct fec_enet_private *fep);
1841 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1843 struct fec_enet_private *fep = netdev_priv(ndev);
1847 ret = clk_prepare_enable(fep->clk_ahb);
1851 if (fep->clk_enet_out) {
1852 ret = clk_prepare_enable(fep->clk_enet_out);
1854 goto failed_clk_enet_out;
1860 mutex_lock(&fep->ptp_clk_mutex);
1861 ret = clk_prepare_enable(fep->clk_ptp);
1863 mutex_unlock(&fep->ptp_clk_mutex);
1864 goto failed_clk_ptp;
1866 fep->ptp_clk_on = true;
1868 mutex_unlock(&fep->ptp_clk_mutex);
1871 ret = clk_prepare_enable(fep->clk_ref);
1873 goto failed_clk_ref;
1875 clk_disable_unprepare(fep->clk_ahb);
1876 clk_disable_unprepare(fep->clk_enet_out);
1878 mutex_lock(&fep->ptp_clk_mutex);
1879 clk_disable_unprepare(fep->clk_ptp);
1880 fep->ptp_clk_on = false;
1881 mutex_unlock(&fep->ptp_clk_mutex);
1883 clk_disable_unprepare(fep->clk_ref);
1890 clk_disable_unprepare(fep->clk_ref);
1892 if (fep->clk_enet_out)
1893 clk_disable_unprepare(fep->clk_enet_out);
1894 failed_clk_enet_out:
1895 clk_disable_unprepare(fep->clk_ahb);
1900 static int fec_enet_mii_probe(struct net_device *ndev)
1902 struct fec_enet_private *fep = netdev_priv(ndev);
1903 struct phy_device *phy_dev = NULL;
1904 char mdio_bus_id[MII_BUS_ID_SIZE];
1905 char phy_name[MII_BUS_ID_SIZE + 3];
1907 int dev_id = fep->dev_id;
1909 if (fep->phy_node) {
1910 phy_dev = of_phy_connect(ndev, fep->phy_node,
1911 &fec_enet_adjust_link, 0,
1912 fep->phy_interface);
1916 /* check for attached phy */
1917 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1918 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1922 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1926 if (phy_id >= PHY_MAX_ADDR) {
1927 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1928 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1932 snprintf(phy_name, sizeof(phy_name),
1933 PHY_ID_FMT, mdio_bus_id, phy_id);
1934 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1935 fep->phy_interface);
1938 if (IS_ERR(phy_dev)) {
1939 netdev_err(ndev, "could not attach to PHY\n");
1940 return PTR_ERR(phy_dev);
1943 /* mask with MAC supported features */
1944 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1945 phy_dev->supported &= PHY_GBIT_FEATURES;
1946 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1947 #if !defined(CONFIG_M5272)
1948 phy_dev->supported |= SUPPORTED_Pause;
1952 phy_dev->supported &= PHY_BASIC_FEATURES;
1954 phy_dev->advertising = phy_dev->supported;
1957 fep->full_duplex = 0;
1959 phy_attached_info(phy_dev);
1964 static int fec_enet_mii_init(struct platform_device *pdev)
1966 static struct mii_bus *fec0_mii_bus;
1967 struct net_device *ndev = platform_get_drvdata(pdev);
1968 struct fec_enet_private *fep = netdev_priv(ndev);
1969 struct device_node *node;
1971 u32 mii_speed, holdtime;
1974 * The i.MX28 dual fec interfaces are not equal.
1975 * Here are the differences:
1977 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1978 * - fec0 acts as the 1588 time master while fec1 is slave
1979 * - external phys can only be configured by fec0
1981 * That is to say fec1 can not work independently. It only works
1982 * when fec0 is working. The reason behind this design is that the
1983 * second interface is added primarily for Switch mode.
1985 * Because of the last point above, both phys are attached on fec0
1986 * mdio interface in board design, and need to be configured by
1989 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1990 /* fec1 uses fec0 mii_bus */
1991 if (mii_cnt && fec0_mii_bus) {
1992 fep->mii_bus = fec0_mii_bus;
1999 fep->mii_timeout = 0;
2002 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2004 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2005 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2006 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2009 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2010 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2012 if (mii_speed > 63) {
2014 "fec clock (%lu) too fast to get right mii speed\n",
2015 clk_get_rate(fep->clk_ipg));
2021 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2022 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2023 * versions are RAZ there, so just ignore the difference and write the
2025 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2026 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2028 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2029 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2030 * holdtime cannot result in a value greater than 3.
2032 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2034 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2036 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2038 fep->mii_bus = mdiobus_alloc();
2039 if (fep->mii_bus == NULL) {
2044 fep->mii_bus->name = "fec_enet_mii_bus";
2045 fep->mii_bus->read = fec_enet_mdio_read;
2046 fep->mii_bus->write = fec_enet_mdio_write;
2047 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2048 pdev->name, fep->dev_id + 1);
2049 fep->mii_bus->priv = fep;
2050 fep->mii_bus->parent = &pdev->dev;
2052 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2054 err = of_mdiobus_register(fep->mii_bus, node);
2057 err = mdiobus_register(fep->mii_bus);
2061 goto err_out_free_mdiobus;
2065 /* save fec0 mii_bus */
2066 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2067 fec0_mii_bus = fep->mii_bus;
2071 err_out_free_mdiobus:
2072 mdiobus_free(fep->mii_bus);
2077 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2079 if (--mii_cnt == 0) {
2080 mdiobus_unregister(fep->mii_bus);
2081 mdiobus_free(fep->mii_bus);
2085 static void fec_enet_get_drvinfo(struct net_device *ndev,
2086 struct ethtool_drvinfo *info)
2088 struct fec_enet_private *fep = netdev_priv(ndev);
2090 strlcpy(info->driver, fep->pdev->dev.driver->name,
2091 sizeof(info->driver));
2092 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2093 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2096 static int fec_enet_get_regs_len(struct net_device *ndev)
2098 struct fec_enet_private *fep = netdev_priv(ndev);
2102 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2104 s = resource_size(r);
2109 /* List of registers that can be safety be read to dump them with ethtool */
2110 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2111 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2112 static u32 fec_enet_register_offset[] = {
2113 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2114 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2115 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2116 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2117 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2118 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2119 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2120 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2121 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2122 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2123 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2124 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2125 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2126 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2127 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2128 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2129 RMON_T_P_GTE2048, RMON_T_OCTETS,
2130 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2131 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2132 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2133 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2134 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2135 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2136 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2137 RMON_R_P_GTE2048, RMON_R_OCTETS,
2138 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2139 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2142 static u32 fec_enet_register_offset[] = {
2143 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2144 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2145 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2146 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2147 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2148 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2149 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2150 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2151 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2155 static void fec_enet_get_regs(struct net_device *ndev,
2156 struct ethtool_regs *regs, void *regbuf)
2158 struct fec_enet_private *fep = netdev_priv(ndev);
2159 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2160 u32 *buf = (u32 *)regbuf;
2163 memset(buf, 0, regs->len);
2165 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2166 off = fec_enet_register_offset[i] / 4;
2167 buf[off] = readl(&theregs[off]);
2171 static int fec_enet_get_ts_info(struct net_device *ndev,
2172 struct ethtool_ts_info *info)
2174 struct fec_enet_private *fep = netdev_priv(ndev);
2176 if (fep->bufdesc_ex) {
2178 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2179 SOF_TIMESTAMPING_RX_SOFTWARE |
2180 SOF_TIMESTAMPING_SOFTWARE |
2181 SOF_TIMESTAMPING_TX_HARDWARE |
2182 SOF_TIMESTAMPING_RX_HARDWARE |
2183 SOF_TIMESTAMPING_RAW_HARDWARE;
2185 info->phc_index = ptp_clock_index(fep->ptp_clock);
2187 info->phc_index = -1;
2189 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2190 (1 << HWTSTAMP_TX_ON);
2192 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2193 (1 << HWTSTAMP_FILTER_ALL);
2196 return ethtool_op_get_ts_info(ndev, info);
2200 #if !defined(CONFIG_M5272)
2202 static void fec_enet_get_pauseparam(struct net_device *ndev,
2203 struct ethtool_pauseparam *pause)
2205 struct fec_enet_private *fep = netdev_priv(ndev);
2207 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2208 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2209 pause->rx_pause = pause->tx_pause;
2212 static int fec_enet_set_pauseparam(struct net_device *ndev,
2213 struct ethtool_pauseparam *pause)
2215 struct fec_enet_private *fep = netdev_priv(ndev);
2220 if (pause->tx_pause != pause->rx_pause) {
2222 "hardware only support enable/disable both tx and rx");
2226 fep->pause_flag = 0;
2228 /* tx pause must be same as rx pause */
2229 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2230 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2232 if (pause->rx_pause || pause->autoneg) {
2233 ndev->phydev->supported |= ADVERTISED_Pause;
2234 ndev->phydev->advertising |= ADVERTISED_Pause;
2236 ndev->phydev->supported &= ~ADVERTISED_Pause;
2237 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2240 if (pause->autoneg) {
2241 if (netif_running(ndev))
2243 phy_start_aneg(ndev->phydev);
2245 if (netif_running(ndev)) {
2246 napi_disable(&fep->napi);
2247 netif_tx_lock_bh(ndev);
2249 netif_wake_queue(ndev);
2250 netif_tx_unlock_bh(ndev);
2251 napi_enable(&fep->napi);
2257 static const struct fec_stat {
2258 char name[ETH_GSTRING_LEN];
2262 { "tx_dropped", RMON_T_DROP },
2263 { "tx_packets", RMON_T_PACKETS },
2264 { "tx_broadcast", RMON_T_BC_PKT },
2265 { "tx_multicast", RMON_T_MC_PKT },
2266 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2267 { "tx_undersize", RMON_T_UNDERSIZE },
2268 { "tx_oversize", RMON_T_OVERSIZE },
2269 { "tx_fragment", RMON_T_FRAG },
2270 { "tx_jabber", RMON_T_JAB },
2271 { "tx_collision", RMON_T_COL },
2272 { "tx_64byte", RMON_T_P64 },
2273 { "tx_65to127byte", RMON_T_P65TO127 },
2274 { "tx_128to255byte", RMON_T_P128TO255 },
2275 { "tx_256to511byte", RMON_T_P256TO511 },
2276 { "tx_512to1023byte", RMON_T_P512TO1023 },
2277 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2278 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2279 { "tx_octets", RMON_T_OCTETS },
2282 { "IEEE_tx_drop", IEEE_T_DROP },
2283 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2284 { "IEEE_tx_1col", IEEE_T_1COL },
2285 { "IEEE_tx_mcol", IEEE_T_MCOL },
2286 { "IEEE_tx_def", IEEE_T_DEF },
2287 { "IEEE_tx_lcol", IEEE_T_LCOL },
2288 { "IEEE_tx_excol", IEEE_T_EXCOL },
2289 { "IEEE_tx_macerr", IEEE_T_MACERR },
2290 { "IEEE_tx_cserr", IEEE_T_CSERR },
2291 { "IEEE_tx_sqe", IEEE_T_SQE },
2292 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2293 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2296 { "rx_packets", RMON_R_PACKETS },
2297 { "rx_broadcast", RMON_R_BC_PKT },
2298 { "rx_multicast", RMON_R_MC_PKT },
2299 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2300 { "rx_undersize", RMON_R_UNDERSIZE },
2301 { "rx_oversize", RMON_R_OVERSIZE },
2302 { "rx_fragment", RMON_R_FRAG },
2303 { "rx_jabber", RMON_R_JAB },
2304 { "rx_64byte", RMON_R_P64 },
2305 { "rx_65to127byte", RMON_R_P65TO127 },
2306 { "rx_128to255byte", RMON_R_P128TO255 },
2307 { "rx_256to511byte", RMON_R_P256TO511 },
2308 { "rx_512to1023byte", RMON_R_P512TO1023 },
2309 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2310 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2311 { "rx_octets", RMON_R_OCTETS },
2314 { "IEEE_rx_drop", IEEE_R_DROP },
2315 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2316 { "IEEE_rx_crc", IEEE_R_CRC },
2317 { "IEEE_rx_align", IEEE_R_ALIGN },
2318 { "IEEE_rx_macerr", IEEE_R_MACERR },
2319 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2320 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2323 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2325 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2327 struct fec_enet_private *fep = netdev_priv(dev);
2330 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2331 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2334 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2335 struct ethtool_stats *stats, u64 *data)
2337 struct fec_enet_private *fep = netdev_priv(dev);
2339 if (netif_running(dev))
2340 fec_enet_update_ethtool_stats(dev);
2342 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2345 static void fec_enet_get_strings(struct net_device *netdev,
2346 u32 stringset, u8 *data)
2349 switch (stringset) {
2351 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2352 memcpy(data + i * ETH_GSTRING_LEN,
2353 fec_stats[i].name, ETH_GSTRING_LEN);
2358 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2362 return ARRAY_SIZE(fec_stats);
2368 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2370 struct fec_enet_private *fep = netdev_priv(dev);
2373 /* Disable MIB statistics counters */
2374 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2376 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2377 writel(0, fep->hwp + fec_stats[i].offset);
2379 /* Don't disable MIB statistics counters */
2380 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2383 #else /* !defined(CONFIG_M5272) */
2384 #define FEC_STATS_SIZE 0
2385 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2389 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2392 #endif /* !defined(CONFIG_M5272) */
2394 /* ITR clock source is enet system clock (clk_ahb).
2395 * TCTT unit is cycle_ns * 64 cycle
2396 * So, the ICTT value = X us / (cycle_ns * 64)
2398 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2400 struct fec_enet_private *fep = netdev_priv(ndev);
2402 return us * (fep->itr_clk_rate / 64000) / 1000;
2405 /* Set threshold for interrupt coalescing */
2406 static void fec_enet_itr_coal_set(struct net_device *ndev)
2408 struct fec_enet_private *fep = netdev_priv(ndev);
2411 /* Must be greater than zero to avoid unpredictable behavior */
2412 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2413 !fep->tx_time_itr || !fep->tx_pkts_itr)
2416 /* Select enet system clock as Interrupt Coalescing
2417 * timer Clock Source
2419 rx_itr = FEC_ITR_CLK_SEL;
2420 tx_itr = FEC_ITR_CLK_SEL;
2422 /* set ICFT and ICTT */
2423 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2424 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2425 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2426 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2428 rx_itr |= FEC_ITR_EN;
2429 tx_itr |= FEC_ITR_EN;
2431 writel(tx_itr, fep->hwp + FEC_TXIC0);
2432 writel(rx_itr, fep->hwp + FEC_RXIC0);
2433 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2434 writel(tx_itr, fep->hwp + FEC_TXIC1);
2435 writel(rx_itr, fep->hwp + FEC_RXIC1);
2436 writel(tx_itr, fep->hwp + FEC_TXIC2);
2437 writel(rx_itr, fep->hwp + FEC_RXIC2);
2442 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2444 struct fec_enet_private *fep = netdev_priv(ndev);
2446 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2449 ec->rx_coalesce_usecs = fep->rx_time_itr;
2450 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2452 ec->tx_coalesce_usecs = fep->tx_time_itr;
2453 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2459 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2461 struct fec_enet_private *fep = netdev_priv(ndev);
2464 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2467 if (ec->rx_max_coalesced_frames > 255) {
2468 pr_err("Rx coalesced frames exceed hardware limitation\n");
2472 if (ec->tx_max_coalesced_frames > 255) {
2473 pr_err("Tx coalesced frame exceed hardware limitation\n");
2477 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2478 if (cycle > 0xFFFF) {
2479 pr_err("Rx coalesced usec exceed hardware limitation\n");
2483 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2484 if (cycle > 0xFFFF) {
2485 pr_err("Rx coalesced usec exceed hardware limitation\n");
2489 fep->rx_time_itr = ec->rx_coalesce_usecs;
2490 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2492 fep->tx_time_itr = ec->tx_coalesce_usecs;
2493 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2495 fec_enet_itr_coal_set(ndev);
2500 static void fec_enet_itr_coal_init(struct net_device *ndev)
2502 struct ethtool_coalesce ec;
2504 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2505 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2507 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2508 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2510 fec_enet_set_coalesce(ndev, &ec);
2513 static int fec_enet_get_tunable(struct net_device *netdev,
2514 const struct ethtool_tunable *tuna,
2517 struct fec_enet_private *fep = netdev_priv(netdev);
2521 case ETHTOOL_RX_COPYBREAK:
2522 *(u32 *)data = fep->rx_copybreak;
2532 static int fec_enet_set_tunable(struct net_device *netdev,
2533 const struct ethtool_tunable *tuna,
2536 struct fec_enet_private *fep = netdev_priv(netdev);
2540 case ETHTOOL_RX_COPYBREAK:
2541 fep->rx_copybreak = *(u32 *)data;
2552 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2554 struct fec_enet_private *fep = netdev_priv(ndev);
2556 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2557 wol->supported = WAKE_MAGIC;
2558 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2560 wol->supported = wol->wolopts = 0;
2565 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2567 struct fec_enet_private *fep = netdev_priv(ndev);
2569 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2572 if (wol->wolopts & ~WAKE_MAGIC)
2575 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2576 if (device_may_wakeup(&ndev->dev)) {
2577 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2578 if (fep->irq[0] > 0)
2579 enable_irq_wake(fep->irq[0]);
2581 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2582 if (fep->irq[0] > 0)
2583 disable_irq_wake(fep->irq[0]);
2589 static const struct ethtool_ops fec_enet_ethtool_ops = {
2590 .get_drvinfo = fec_enet_get_drvinfo,
2591 .get_regs_len = fec_enet_get_regs_len,
2592 .get_regs = fec_enet_get_regs,
2593 .nway_reset = phy_ethtool_nway_reset,
2594 .get_link = ethtool_op_get_link,
2595 .get_coalesce = fec_enet_get_coalesce,
2596 .set_coalesce = fec_enet_set_coalesce,
2597 #ifndef CONFIG_M5272
2598 .get_pauseparam = fec_enet_get_pauseparam,
2599 .set_pauseparam = fec_enet_set_pauseparam,
2600 .get_strings = fec_enet_get_strings,
2601 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2602 .get_sset_count = fec_enet_get_sset_count,
2604 .get_ts_info = fec_enet_get_ts_info,
2605 .get_tunable = fec_enet_get_tunable,
2606 .set_tunable = fec_enet_set_tunable,
2607 .get_wol = fec_enet_get_wol,
2608 .set_wol = fec_enet_set_wol,
2609 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2610 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2613 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2615 struct fec_enet_private *fep = netdev_priv(ndev);
2616 struct phy_device *phydev = ndev->phydev;
2618 if (!netif_running(ndev))
2624 if (fep->bufdesc_ex) {
2625 if (cmd == SIOCSHWTSTAMP)
2626 return fec_ptp_set(ndev, rq);
2627 if (cmd == SIOCGHWTSTAMP)
2628 return fec_ptp_get(ndev, rq);
2631 return phy_mii_ioctl(phydev, rq, cmd);
2634 static void fec_enet_free_buffers(struct net_device *ndev)
2636 struct fec_enet_private *fep = netdev_priv(ndev);
2638 struct sk_buff *skb;
2639 struct bufdesc *bdp;
2640 struct fec_enet_priv_tx_q *txq;
2641 struct fec_enet_priv_rx_q *rxq;
2644 for (q = 0; q < fep->num_rx_queues; q++) {
2645 rxq = fep->rx_queue[q];
2647 for (i = 0; i < rxq->bd.ring_size; i++) {
2648 skb = rxq->rx_skbuff[i];
2649 rxq->rx_skbuff[i] = NULL;
2651 dma_unmap_single(&fep->pdev->dev,
2652 fec32_to_cpu(bdp->cbd_bufaddr),
2653 FEC_ENET_RX_FRSIZE - fep->rx_align,
2657 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2661 for (q = 0; q < fep->num_tx_queues; q++) {
2662 txq = fep->tx_queue[q];
2664 for (i = 0; i < txq->bd.ring_size; i++) {
2665 kfree(txq->tx_bounce[i]);
2666 txq->tx_bounce[i] = NULL;
2667 skb = txq->tx_skbuff[i];
2668 txq->tx_skbuff[i] = NULL;
2674 static void fec_enet_free_queue(struct net_device *ndev)
2676 struct fec_enet_private *fep = netdev_priv(ndev);
2678 struct fec_enet_priv_tx_q *txq;
2680 for (i = 0; i < fep->num_tx_queues; i++)
2681 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2682 txq = fep->tx_queue[i];
2683 dma_free_coherent(&fep->pdev->dev,
2684 txq->bd.ring_size * TSO_HEADER_SIZE,
2689 for (i = 0; i < fep->num_rx_queues; i++)
2690 kfree(fep->rx_queue[i]);
2691 for (i = 0; i < fep->num_tx_queues; i++)
2692 kfree(fep->tx_queue[i]);
2695 static int fec_enet_alloc_queue(struct net_device *ndev)
2697 struct fec_enet_private *fep = netdev_priv(ndev);
2700 struct fec_enet_priv_tx_q *txq;
2702 for (i = 0; i < fep->num_tx_queues; i++) {
2703 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2709 fep->tx_queue[i] = txq;
2710 txq->bd.ring_size = TX_RING_SIZE;
2711 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2713 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2714 txq->tx_wake_threshold =
2715 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2717 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2718 txq->bd.ring_size * TSO_HEADER_SIZE,
2721 if (!txq->tso_hdrs) {
2727 for (i = 0; i < fep->num_rx_queues; i++) {
2728 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2730 if (!fep->rx_queue[i]) {
2735 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2736 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2741 fec_enet_free_queue(ndev);
2746 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2748 struct fec_enet_private *fep = netdev_priv(ndev);
2750 struct sk_buff *skb;
2751 struct bufdesc *bdp;
2752 struct fec_enet_priv_rx_q *rxq;
2754 rxq = fep->rx_queue[queue];
2756 for (i = 0; i < rxq->bd.ring_size; i++) {
2757 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2761 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2766 rxq->rx_skbuff[i] = skb;
2767 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2769 if (fep->bufdesc_ex) {
2770 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2771 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2774 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2777 /* Set the last buffer to wrap. */
2778 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2779 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2783 fec_enet_free_buffers(ndev);
2788 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2790 struct fec_enet_private *fep = netdev_priv(ndev);
2792 struct bufdesc *bdp;
2793 struct fec_enet_priv_tx_q *txq;
2795 txq = fep->tx_queue[queue];
2797 for (i = 0; i < txq->bd.ring_size; i++) {
2798 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2799 if (!txq->tx_bounce[i])
2802 bdp->cbd_sc = cpu_to_fec16(0);
2803 bdp->cbd_bufaddr = cpu_to_fec32(0);
2805 if (fep->bufdesc_ex) {
2806 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2807 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2810 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2813 /* Set the last buffer to wrap. */
2814 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2815 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2820 fec_enet_free_buffers(ndev);
2824 static int fec_enet_alloc_buffers(struct net_device *ndev)
2826 struct fec_enet_private *fep = netdev_priv(ndev);
2829 for (i = 0; i < fep->num_rx_queues; i++)
2830 if (fec_enet_alloc_rxq_buffers(ndev, i))
2833 for (i = 0; i < fep->num_tx_queues; i++)
2834 if (fec_enet_alloc_txq_buffers(ndev, i))
2840 fec_enet_open(struct net_device *ndev)
2842 struct fec_enet_private *fep = netdev_priv(ndev);
2845 ret = pm_runtime_get_sync(&fep->pdev->dev);
2849 pinctrl_pm_select_default_state(&fep->pdev->dev);
2850 ret = fec_enet_clk_enable(ndev, true);
2854 /* I should reset the ring buffers here, but I don't yet know
2855 * a simple way to do that.
2858 ret = fec_enet_alloc_buffers(ndev);
2860 goto err_enet_alloc;
2862 /* Init MAC prior to mii bus probe */
2865 /* Probe and connect to PHY when open the interface */
2866 ret = fec_enet_mii_probe(ndev);
2868 goto err_enet_mii_probe;
2870 if (fep->quirks & FEC_QUIRK_ERR006687)
2871 imx6q_cpuidle_fec_irqs_used();
2873 napi_enable(&fep->napi);
2874 phy_start(ndev->phydev);
2875 netif_tx_start_all_queues(ndev);
2877 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2878 FEC_WOL_FLAG_ENABLE);
2883 fec_enet_free_buffers(ndev);
2885 fec_enet_clk_enable(ndev, false);
2887 pm_runtime_mark_last_busy(&fep->pdev->dev);
2888 pm_runtime_put_autosuspend(&fep->pdev->dev);
2889 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2894 fec_enet_close(struct net_device *ndev)
2896 struct fec_enet_private *fep = netdev_priv(ndev);
2898 phy_stop(ndev->phydev);
2900 if (netif_device_present(ndev)) {
2901 napi_disable(&fep->napi);
2902 netif_tx_disable(ndev);
2906 phy_disconnect(ndev->phydev);
2908 if (fep->quirks & FEC_QUIRK_ERR006687)
2909 imx6q_cpuidle_fec_irqs_unused();
2911 fec_enet_update_ethtool_stats(ndev);
2913 fec_enet_clk_enable(ndev, false);
2914 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2915 pm_runtime_mark_last_busy(&fep->pdev->dev);
2916 pm_runtime_put_autosuspend(&fep->pdev->dev);
2918 fec_enet_free_buffers(ndev);
2923 /* Set or clear the multicast filter for this adaptor.
2924 * Skeleton taken from sunlance driver.
2925 * The CPM Ethernet implementation allows Multicast as well as individual
2926 * MAC address filtering. Some of the drivers check to make sure it is
2927 * a group multicast address, and discard those that are not. I guess I
2928 * will do the same for now, but just remove the test if you want
2929 * individual filtering as well (do the upper net layers want or support
2930 * this kind of feature?).
2933 #define FEC_HASH_BITS 6 /* #bits in hash */
2934 #define CRC32_POLY 0xEDB88320
2936 static void set_multicast_list(struct net_device *ndev)
2938 struct fec_enet_private *fep = netdev_priv(ndev);
2939 struct netdev_hw_addr *ha;
2940 unsigned int i, bit, data, crc, tmp;
2942 unsigned int hash_high = 0, hash_low = 0;
2944 if (ndev->flags & IFF_PROMISC) {
2945 tmp = readl(fep->hwp + FEC_R_CNTRL);
2947 writel(tmp, fep->hwp + FEC_R_CNTRL);
2951 tmp = readl(fep->hwp + FEC_R_CNTRL);
2953 writel(tmp, fep->hwp + FEC_R_CNTRL);
2955 if (ndev->flags & IFF_ALLMULTI) {
2956 /* Catch all multicast addresses, so set the
2959 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2960 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2965 /* Add the addresses in hash register */
2966 netdev_for_each_mc_addr(ha, ndev) {
2967 /* calculate crc32 value of mac address */
2970 for (i = 0; i < ndev->addr_len; i++) {
2972 for (bit = 0; bit < 8; bit++, data >>= 1) {
2974 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2978 /* only upper 6 bits (FEC_HASH_BITS) are used
2979 * which point to specific bit in the hash registers
2981 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
2984 hash_high |= 1 << (hash - 32);
2986 hash_low |= 1 << hash;
2989 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2990 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2993 /* Set a MAC change in hardware. */
2995 fec_set_mac_address(struct net_device *ndev, void *p)
2997 struct fec_enet_private *fep = netdev_priv(ndev);
2998 struct sockaddr *addr = p;
3001 if (!is_valid_ether_addr(addr->sa_data))
3002 return -EADDRNOTAVAIL;
3003 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3006 /* Add netif status check here to avoid system hang in below case:
3007 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3008 * After ethx down, fec all clocks are gated off and then register
3009 * access causes system hang.
3011 if (!netif_running(ndev))
3014 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3015 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3016 fep->hwp + FEC_ADDR_LOW);
3017 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3018 fep->hwp + FEC_ADDR_HIGH);
3022 #ifdef CONFIG_NET_POLL_CONTROLLER
3024 * fec_poll_controller - FEC Poll controller function
3025 * @dev: The FEC network adapter
3027 * Polled functionality used by netconsole and others in non interrupt mode
3030 static void fec_poll_controller(struct net_device *dev)
3033 struct fec_enet_private *fep = netdev_priv(dev);
3035 for (i = 0; i < FEC_IRQ_NUM; i++) {
3036 if (fep->irq[i] > 0) {
3037 disable_irq(fep->irq[i]);
3038 fec_enet_interrupt(fep->irq[i], dev);
3039 enable_irq(fep->irq[i]);
3045 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3046 netdev_features_t features)
3048 struct fec_enet_private *fep = netdev_priv(netdev);
3049 netdev_features_t changed = features ^ netdev->features;
3051 netdev->features = features;
3053 /* Receive checksum has been changed */
3054 if (changed & NETIF_F_RXCSUM) {
3055 if (features & NETIF_F_RXCSUM)
3056 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3058 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3062 static int fec_set_features(struct net_device *netdev,
3063 netdev_features_t features)
3065 struct fec_enet_private *fep = netdev_priv(netdev);
3066 netdev_features_t changed = features ^ netdev->features;
3068 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3069 napi_disable(&fep->napi);
3070 netif_tx_lock_bh(netdev);
3072 fec_enet_set_netdev_features(netdev, features);
3073 fec_restart(netdev);
3074 netif_tx_wake_all_queues(netdev);
3075 netif_tx_unlock_bh(netdev);
3076 napi_enable(&fep->napi);
3078 fec_enet_set_netdev_features(netdev, features);
3084 static const struct net_device_ops fec_netdev_ops = {
3085 .ndo_open = fec_enet_open,
3086 .ndo_stop = fec_enet_close,
3087 .ndo_start_xmit = fec_enet_start_xmit,
3088 .ndo_set_rx_mode = set_multicast_list,
3089 .ndo_validate_addr = eth_validate_addr,
3090 .ndo_tx_timeout = fec_timeout,
3091 .ndo_set_mac_address = fec_set_mac_address,
3092 .ndo_do_ioctl = fec_enet_ioctl,
3093 #ifdef CONFIG_NET_POLL_CONTROLLER
3094 .ndo_poll_controller = fec_poll_controller,
3096 .ndo_set_features = fec_set_features,
3099 static const unsigned short offset_des_active_rxq[] = {
3100 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3103 static const unsigned short offset_des_active_txq[] = {
3104 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3108 * XXX: We need to clean up on failure exits here.
3111 static int fec_enet_init(struct net_device *ndev)
3113 struct fec_enet_private *fep = netdev_priv(ndev);
3114 struct bufdesc *cbd_base;
3118 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3119 sizeof(struct bufdesc);
3120 unsigned dsize_log2 = __fls(dsize);
3122 WARN_ON(dsize != (1 << dsize_log2));
3123 #if defined(CONFIG_ARM)
3124 fep->rx_align = 0xf;
3125 fep->tx_align = 0xf;
3127 fep->rx_align = 0x3;
3128 fep->tx_align = 0x3;
3131 fec_enet_alloc_queue(ndev);
3133 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3135 /* Allocate memory for buffer descriptors. */
3136 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3142 memset(cbd_base, 0, bd_size);
3144 /* Get the Ethernet address */
3146 /* make sure MAC we just acquired is programmed into the hw */
3147 fec_set_mac_address(ndev, NULL);
3149 /* Set receive and transmit descriptor base. */
3150 for (i = 0; i < fep->num_rx_queues; i++) {
3151 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3152 unsigned size = dsize * rxq->bd.ring_size;
3155 rxq->bd.base = cbd_base;
3156 rxq->bd.cur = cbd_base;
3157 rxq->bd.dma = bd_dma;
3158 rxq->bd.dsize = dsize;
3159 rxq->bd.dsize_log2 = dsize_log2;
3160 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3162 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3163 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3166 for (i = 0; i < fep->num_tx_queues; i++) {
3167 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3168 unsigned size = dsize * txq->bd.ring_size;
3171 txq->bd.base = cbd_base;
3172 txq->bd.cur = cbd_base;
3173 txq->bd.dma = bd_dma;
3174 txq->bd.dsize = dsize;
3175 txq->bd.dsize_log2 = dsize_log2;
3176 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3178 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3179 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3183 /* The FEC Ethernet specific entries in the device structure */
3184 ndev->watchdog_timeo = TX_TIMEOUT;
3185 ndev->netdev_ops = &fec_netdev_ops;
3186 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3188 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3189 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3191 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3192 /* enable hw VLAN support */
3193 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3195 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3196 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3198 /* enable hw accelerator */
3199 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3200 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3201 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3204 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3206 fep->rx_align = 0x3f;
3209 ndev->hw_features = ndev->features;
3213 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3214 fec_enet_clear_ethtool_stats(ndev);
3216 fec_enet_update_ethtool_stats(ndev);
3222 static void fec_reset_phy(struct fec_enet_private *fep)
3224 if (!gpio_is_valid(fep->reset_gpio))
3227 gpio_set_value_cansleep(fep->reset_gpio, fep->reset_active_high);
3229 if (fep->phy_reset_duration > 20)
3230 msleep(fep->phy_reset_duration);
3232 usleep_range(fep->phy_reset_duration * 1000,
3233 fep->phy_reset_duration * 1000 + 1000);
3235 gpio_set_value_cansleep(fep->reset_gpio, !fep->reset_active_high);
3237 if (!fep->phy_post_delay)
3239 if (fep->phy_post_delay > 20)
3240 msleep(fep->phy_post_delay);
3242 usleep_range(fep->phy_post_delay * 1000,
3243 fep->phy_post_delay * 1000 + 1000);
3246 static int fec_get_reset_gpio(struct platform_device *pdev)
3249 struct device_node *np = pdev->dev.of_node;
3250 struct net_device *ndev = platform_get_drvdata(pdev);
3251 struct fec_enet_private *fep = netdev_priv(ndev);
3253 /* Most DT files do not specify the correct polarity
3254 * of the phy-reset GPIO.
3255 * So use this special property to signal the actual
3258 fep->reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0);
3259 if (fep->reset_gpio == -EPROBE_DEFER)
3260 return -EPROBE_DEFER;
3261 if (!gpio_is_valid(fep->reset_gpio))
3264 fep->reset_active_high = of_property_read_bool(np,
3265 "phy-reset-active-high");
3267 err = devm_gpio_request_one(&pdev->dev, fep->reset_gpio,
3268 fep->reset_active_high ?
3269 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
3272 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3276 err = of_property_read_u32(np, "phy-reset-duration",
3277 &fep->phy_reset_duration);
3278 /* A sane reset duration should not be longer than 1s */
3279 if (err || fep->phy_reset_duration > 1000)
3280 fep->phy_reset_duration = 1;
3282 err = of_property_read_u32(np, "phy-reset-post-delay",
3283 &fep->phy_post_delay);
3284 /* valid post reset delay should be less than 1s */
3286 fep->phy_post_delay = 0;
3287 else if (fep->phy_post_delay > 1000)
3292 #else /* CONFIG_OF */
3293 /* In case of platform probe, the reset has been done
3296 static inline void fec_reset_phy(struct fec_enet_private *fep)
3300 static int fec_get_reset_gpio(struct platform_device *pdev)
3302 struct net_device *ndev = platform_get_drvdata(pdev);
3303 struct fec_enet_private *fep = netdev_priv(ndev);
3305 fep->reset_gpio = -EINVAL;
3308 #endif /* CONFIG_OF */
3311 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3313 struct device_node *np = pdev->dev.of_node;
3315 *num_tx = *num_rx = 1;
3317 if (!np || !of_device_is_available(np))
3320 /* parse the num of tx and rx queues */
3321 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3323 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3325 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3326 dev_warn(&pdev->dev, "Invalid fsl,num-tx-queues value %d; fall back to 1\n",
3331 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3332 dev_warn(&pdev->dev, "Invalid fsl,num-rx-queues value %d; fall back to 1\n",
3339 fec_probe(struct platform_device *pdev)
3341 struct fec_enet_private *fep;
3342 struct fec_platform_data *pdata;
3343 struct net_device *ndev;
3344 int i, irq, ret = 0;
3346 const struct of_device_id *of_id;
3348 struct device_node *np = pdev->dev.of_node, *phy_node;
3352 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3354 /* Init network device */
3355 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3356 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3360 SET_NETDEV_DEV(ndev, &pdev->dev);
3362 /* setup board info structure */
3363 fep = netdev_priv(ndev);
3365 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3367 pdev->id_entry = of_id->data;
3368 fep->quirks = pdev->id_entry->driver_data;
3371 fep->num_rx_queues = num_rx_qs;
3372 fep->num_tx_queues = num_tx_qs;
3374 #if !defined(CONFIG_M5272)
3375 /* default enable pause frame auto negotiation */
3376 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3377 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3380 /* Select default pin state */
3381 pinctrl_pm_select_default_state(&pdev->dev);
3383 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3384 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3385 if (IS_ERR(fep->hwp)) {
3386 ret = PTR_ERR(fep->hwp);
3387 goto failed_ioremap;
3391 fep->dev_id = dev_id++;
3393 platform_set_drvdata(pdev, ndev);
3395 if ((of_machine_is_compatible("fsl,imx6q") ||
3396 of_machine_is_compatible("fsl,imx6dl")) &&
3397 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3398 fep->quirks |= FEC_QUIRK_ERR006687;
3400 if (of_get_property(np, "fsl,magic-packet", NULL))
3401 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3403 phy_node = of_parse_phandle(np, "phy-handle", 0);
3404 if (!phy_node && of_phy_is_fixed_link(np)) {
3405 ret = of_phy_register_fixed_link(np);
3408 "broken fixed-link specification\n");
3411 phy_node = of_node_get(np);
3413 fep->phy_node = phy_node;
3415 ret = of_get_phy_mode(pdev->dev.of_node);
3417 pdata = dev_get_platdata(&pdev->dev);
3419 fep->phy_interface = pdata->phy;
3421 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3423 fep->phy_interface = ret;
3426 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3427 if (IS_ERR(fep->clk_ipg)) {
3428 ret = PTR_ERR(fep->clk_ipg);
3432 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3433 if (IS_ERR(fep->clk_ahb)) {
3434 ret = PTR_ERR(fep->clk_ahb);
3438 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3440 /* enet_out is optional, depends on board */
3441 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3442 if (IS_ERR(fep->clk_enet_out))
3443 fep->clk_enet_out = NULL;
3445 fep->ptp_clk_on = false;
3446 mutex_init(&fep->ptp_clk_mutex);
3448 /* clk_ref is optional, depends on board */
3449 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3450 if (IS_ERR(fep->clk_ref))
3451 fep->clk_ref = NULL;
3453 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3454 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3455 if (IS_ERR(fep->clk_ptp)) {
3456 fep->clk_ptp = NULL;
3457 fep->bufdesc_ex = false;
3460 ret = fec_enet_clk_enable(ndev, true);
3464 ret = clk_prepare_enable(fep->clk_ipg);
3466 goto failed_clk_ipg;
3468 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3469 if (!IS_ERR(fep->reg_phy)) {
3470 ret = regulator_enable(fep->reg_phy);
3473 "Failed to enable phy regulator: %d\n", ret);
3474 clk_disable_unprepare(fep->clk_ipg);
3475 goto failed_regulator;
3478 fep->reg_phy = NULL;
3481 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3482 pm_runtime_use_autosuspend(&pdev->dev);
3483 pm_runtime_get_noresume(&pdev->dev);
3484 pm_runtime_set_active(&pdev->dev);
3485 pm_runtime_enable(&pdev->dev);
3487 ret = fec_get_reset_gpio(pdev);
3492 if (fep->bufdesc_ex)
3495 ret = fec_enet_init(ndev);
3499 for (i = 0; i < FEC_IRQ_NUM; i++) {
3500 irq = platform_get_irq(pdev, i);
3507 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3508 0, pdev->name, ndev);
3515 init_completion(&fep->mdio_done);
3516 ret = fec_enet_mii_init(pdev);
3518 goto failed_mii_init;
3520 /* Carrier starts down, phylib will bring it up */
3521 netif_carrier_off(ndev);
3522 fec_enet_clk_enable(ndev, false);
3523 pinctrl_pm_select_sleep_state(&pdev->dev);
3525 ret = register_netdev(ndev);
3527 goto failed_register;
3529 device_init_wakeup(&ndev->dev, fep->wol_flag &
3530 FEC_WOL_HAS_MAGIC_PACKET);
3532 if (fep->bufdesc_ex && fep->ptp_clock)
3533 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3535 fep->rx_copybreak = COPYBREAK_DEFAULT;
3536 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3538 pm_runtime_mark_last_busy(&pdev->dev);
3539 pm_runtime_put_autosuspend(&pdev->dev);
3544 fec_enet_mii_remove(fep);
3550 regulator_disable(fep->reg_phy);
3552 pm_runtime_put(&pdev->dev);
3553 pm_runtime_disable(&pdev->dev);
3556 fec_enet_clk_enable(ndev, false);
3558 if (of_phy_is_fixed_link(np))
3559 of_phy_deregister_fixed_link(np);
3561 of_node_put(phy_node);
3569 fec_drv_remove(struct platform_device *pdev)
3571 struct net_device *ndev = platform_get_drvdata(pdev);
3572 struct fec_enet_private *fep = netdev_priv(ndev);
3573 struct device_node *np = pdev->dev.of_node;
3575 cancel_work_sync(&fep->tx_timeout_work);
3577 unregister_netdev(ndev);
3578 fec_enet_mii_remove(fep);
3580 regulator_disable(fep->reg_phy);
3581 if (of_phy_is_fixed_link(np))
3582 of_phy_deregister_fixed_link(np);
3583 of_node_put(fep->phy_node);
3589 static int __maybe_unused fec_suspend(struct device *dev)
3591 struct net_device *ndev = dev_get_drvdata(dev);
3592 struct fec_enet_private *fep = netdev_priv(ndev);
3595 if (netif_running(ndev)) {
3596 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3597 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3598 phy_stop(ndev->phydev);
3599 napi_disable(&fep->napi);
3600 netif_tx_lock_bh(ndev);
3601 netif_device_detach(ndev);
3602 netif_tx_unlock_bh(ndev);
3604 fec_enet_clk_enable(ndev, false);
3605 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3606 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3610 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3611 regulator_disable(fep->reg_phy);
3613 /* SOC supply clock to phy, when clock is disabled, phy link down
3614 * SOC control phy regulator, when regulator is disabled, phy link down
3616 if (fep->clk_enet_out || fep->reg_phy)
3622 static int __maybe_unused fec_resume(struct device *dev)
3624 struct net_device *ndev = dev_get_drvdata(dev);
3625 struct fec_enet_private *fep = netdev_priv(ndev);
3626 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3630 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3631 ret = regulator_enable(fep->reg_phy);
3637 if (netif_running(ndev)) {
3638 ret = fec_enet_clk_enable(ndev, true);
3643 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3644 if (pdata && pdata->sleep_mode_enable)
3645 pdata->sleep_mode_enable(false);
3646 val = readl(fep->hwp + FEC_ECNTRL);
3647 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3648 writel(val, fep->hwp + FEC_ECNTRL);
3649 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3651 pinctrl_pm_select_default_state(&fep->pdev->dev);
3654 netif_tx_lock_bh(ndev);
3655 netif_device_attach(ndev);
3656 netif_tx_unlock_bh(ndev);
3657 napi_enable(&fep->napi);
3658 phy_start(ndev->phydev);
3666 regulator_disable(fep->reg_phy);
3670 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3672 struct net_device *ndev = dev_get_drvdata(dev);
3673 struct fec_enet_private *fep = netdev_priv(ndev);
3675 clk_disable_unprepare(fep->clk_ipg);
3680 static int __maybe_unused fec_runtime_resume(struct device *dev)
3682 struct net_device *ndev = dev_get_drvdata(dev);
3683 struct fec_enet_private *fep = netdev_priv(ndev);
3685 return clk_prepare_enable(fep->clk_ipg);
3688 static const struct dev_pm_ops fec_pm_ops = {
3689 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3690 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3693 static struct platform_driver fec_driver = {
3695 .name = DRIVER_NAME,
3697 .of_match_table = fec_dt_ids,
3699 .id_table = fec_devtype,
3701 .remove = fec_drv_remove,
3704 module_platform_driver(fec_driver);
3706 MODULE_ALIAS("platform:"DRIVER_NAME);
3707 MODULE_LICENSE("GPL");