2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/workqueue.h>
39 #include <linux/bitops.h>
41 #include <linux/irq.h>
42 #include <linux/clk.h>
43 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/fec.h>
47 #include <linux/of_device.h>
48 #include <linux/of_gpio.h>
49 #include <linux/of_net.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/regulator/consumer.h>
53 #include <asm/cacheflush.h>
56 #include <asm/coldfire.h>
57 #include <asm/mcfsim.h>
62 #if defined(CONFIG_ARM)
63 #define FEC_ALIGNMENT 0xf
65 #define FEC_ALIGNMENT 0x3
68 #define DRIVER_NAME "fec"
69 #define FEC_NAPI_WEIGHT 64
71 /* Pause frame feild and FIFO threshold */
72 #define FEC_ENET_FCE (1 << 5)
73 #define FEC_ENET_RSEM_V 0x84
74 #define FEC_ENET_RSFL_V 16
75 #define FEC_ENET_RAEM_V 0x8
76 #define FEC_ENET_RAFL_V 0x8
77 #define FEC_ENET_OPD_V 0xFFF0
79 /* Controller is ENET-MAC */
80 #define FEC_QUIRK_ENET_MAC (1 << 0)
81 /* Controller needs driver to swap frame */
82 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
83 /* Controller uses gasket */
84 #define FEC_QUIRK_USE_GASKET (1 << 2)
85 /* Controller has GBIT support */
86 #define FEC_QUIRK_HAS_GBIT (1 << 3)
87 /* Controller has extend desc buffer */
88 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 static struct platform_device_id fec_devtype[] = {
92 /* keep it for coldfire */
97 .driver_data = FEC_QUIRK_USE_GASKET,
103 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX,
112 MODULE_DEVICE_TABLE(platform, fec_devtype);
115 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
116 IMX27_FEC, /* runs on i.mx27/35/51 */
121 static const struct of_device_id fec_dt_ids[] = {
122 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
123 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
124 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
125 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
128 MODULE_DEVICE_TABLE(of, fec_dt_ids);
130 static unsigned char macaddr[ETH_ALEN];
131 module_param_array(macaddr, byte, NULL, 0);
132 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
134 #if defined(CONFIG_M5272)
136 * Some hardware gets it MAC address out of local flash memory.
137 * if this is non-zero then assume it is the address to get MAC from.
139 #if defined(CONFIG_NETtel)
140 #define FEC_FLASHMAC 0xf0006006
141 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
142 #define FEC_FLASHMAC 0xf0006000
143 #elif defined(CONFIG_CANCam)
144 #define FEC_FLASHMAC 0xf0020000
145 #elif defined (CONFIG_M5272C3)
146 #define FEC_FLASHMAC (0xffe04000 + 4)
147 #elif defined(CONFIG_MOD5272)
148 #define FEC_FLASHMAC 0xffc0406b
150 #define FEC_FLASHMAC 0
152 #endif /* CONFIG_M5272 */
154 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
155 #error "FEC: descriptor ring size constants too large"
158 /* Interrupt events/masks. */
159 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
160 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
161 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
162 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
163 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
164 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
165 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
166 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
167 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
168 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
170 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
171 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
173 /* The FEC stores dest/src/type, data, and checksum for receive packets.
175 #define PKT_MAXBUF_SIZE 1518
176 #define PKT_MINBUF_SIZE 64
177 #define PKT_MAXBLR_SIZE 1520
180 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
181 * size bits. Other FEC hardware does not, so we need to take that into
182 * account when setting it.
184 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
185 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
186 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
188 #define OPT_FRAME_SIZE 0
191 /* FEC MII MMFR bits definition */
192 #define FEC_MMFR_ST (1 << 30)
193 #define FEC_MMFR_OP_READ (2 << 28)
194 #define FEC_MMFR_OP_WRITE (1 << 28)
195 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
196 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
197 #define FEC_MMFR_TA (2 << 16)
198 #define FEC_MMFR_DATA(v) (v & 0xffff)
200 #define FEC_MII_TIMEOUT 30000 /* us */
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
210 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
212 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
214 return (struct bufdesc *)(ex + 1);
219 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
221 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
223 return (struct bufdesc *)(ex - 1);
228 static void *swap_buffer(void *bufaddr, int len)
231 unsigned int *buf = bufaddr;
233 for (i = 0; i < (len + 3) / 4; i++, buf++)
234 *buf = cpu_to_be32(*buf);
240 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
242 struct fec_enet_private *fep = netdev_priv(ndev);
243 const struct platform_device_id *id_entry =
244 platform_get_device_id(fep->pdev);
247 unsigned short status;
251 /* Link is down or autonegotiation is in progress. */
252 return NETDEV_TX_BUSY;
255 /* Fill in a Tx ring entry */
258 status = bdp->cbd_sc;
260 if (status & BD_ENET_TX_READY) {
261 /* Ooops. All transmit buffers are full. Bail out.
262 * This should not happen, since ndev->tbusy should be set.
264 printk("%s: tx queue full!.\n", ndev->name);
265 return NETDEV_TX_BUSY;
268 /* Clear all of the status flags */
269 status &= ~BD_ENET_TX_STATS;
271 /* Set buffer length and buffer pointer */
273 bdp->cbd_datlen = skb->len;
276 * On some FEC implementations data must be aligned on
277 * 4-byte boundaries. Use bounce buffers to copy data
278 * and get it aligned. Ugh.
281 index = (struct bufdesc_ex *)bdp -
282 (struct bufdesc_ex *)fep->tx_bd_base;
284 index = bdp - fep->tx_bd_base;
286 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
287 memcpy(fep->tx_bounce[index], skb->data, skb->len);
288 bufaddr = fep->tx_bounce[index];
292 * Some design made an incorrect assumption on endian mode of
293 * the system that it's running on. As the result, driver has to
294 * swap every frame going to and coming from the controller.
296 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
297 swap_buffer(bufaddr, skb->len);
299 /* Save skb pointer */
300 fep->tx_skbuff[index] = skb;
302 /* Push the data cache so the CPM does not get stale memory
305 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
306 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
308 /* Send it on its way. Tell FEC it's ready, interrupt when done,
309 * it's the last BD of the frame, and to put the CRC on the end.
311 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
312 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
313 bdp->cbd_sc = status;
315 if (fep->bufdesc_ex) {
317 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
319 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
321 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
322 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
325 ebdp->cbd_esc = BD_ENET_TX_INT;
328 /* If this was the last BD in the ring, start at the beginning again. */
329 if (status & BD_ENET_TX_WRAP)
330 bdp = fep->tx_bd_base;
332 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
336 if (fep->cur_tx == fep->dirty_tx)
337 netif_stop_queue(ndev);
339 /* Trigger transmission start */
340 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
342 skb_tx_timestamp(skb);
347 /* This function is called to start or restart the FEC during a link
348 * change. This only happens when switching between half and full
352 fec_restart(struct net_device *ndev, int duplex)
354 struct fec_enet_private *fep = netdev_priv(ndev);
355 const struct platform_device_id *id_entry =
356 platform_get_device_id(fep->pdev);
359 u32 rcntl = OPT_FRAME_SIZE | 0x04;
360 u32 ecntl = 0x2; /* ETHEREN */
362 /* Whack a reset. We should wait for this. */
363 writel(1, fep->hwp + FEC_ECNTRL);
367 * enet-mac reset will reset mac address registers too,
368 * so need to reconfigure it.
370 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
371 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
372 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
373 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
376 /* Clear any outstanding interrupt. */
377 writel(0xffc00000, fep->hwp + FEC_IEVENT);
379 /* Reset all multicast. */
380 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
381 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
383 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
384 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
387 /* Set maximum receive buffer size. */
388 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
390 /* Set receive and transmit descriptor base. */
391 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
393 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
394 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
396 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
397 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
399 fep->cur_rx = fep->rx_bd_base;
401 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
402 if (fep->tx_skbuff[i]) {
403 dev_kfree_skb_any(fep->tx_skbuff[i]);
404 fep->tx_skbuff[i] = NULL;
408 /* Enable MII mode */
411 writel(0x04, fep->hwp + FEC_X_CNTRL);
415 writel(0x0, fep->hwp + FEC_X_CNTRL);
418 fep->full_duplex = duplex;
421 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
424 * The phy interface and speed need to get configured
425 * differently on enet-mac.
427 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
428 /* Enable flow control and length check */
429 rcntl |= 0x40000000 | 0x00000020;
431 /* RGMII, RMII or MII */
432 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
434 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
439 /* 1G, 100M or 10M */
441 if (fep->phy_dev->speed == SPEED_1000)
443 else if (fep->phy_dev->speed == SPEED_100)
449 #ifdef FEC_MIIGSK_ENR
450 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
452 /* disable the gasket and wait */
453 writel(0, fep->hwp + FEC_MIIGSK_ENR);
454 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
458 * configure the gasket:
459 * RMII, 50 MHz, no loopback, no echo
460 * MII, 25 MHz, no loopback, no echo
462 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
463 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
464 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
465 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
466 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
468 /* re-enable the gasket */
469 writel(2, fep->hwp + FEC_MIIGSK_ENR);
474 /* enable pause frame*/
475 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
476 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
477 fep->phy_dev && fep->phy_dev->pause)) {
478 rcntl |= FEC_ENET_FCE;
480 /* set FIFO thresh hold parameter to reduce overrun */
481 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
482 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
483 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
484 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
487 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
489 rcntl &= ~FEC_ENET_FCE;
492 writel(rcntl, fep->hwp + FEC_R_CNTRL);
494 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
495 /* enable ENET endian swap */
497 /* enable ENET store and forward mode */
498 writel(1 << 8, fep->hwp + FEC_X_WMRK);
504 /* And last, enable the transmit and receive processing */
505 writel(ecntl, fep->hwp + FEC_ECNTRL);
506 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
509 fec_ptp_start_cyclecounter(ndev);
511 /* Enable interrupts we wish to service */
512 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
516 fec_stop(struct net_device *ndev)
518 struct fec_enet_private *fep = netdev_priv(ndev);
519 const struct platform_device_id *id_entry =
520 platform_get_device_id(fep->pdev);
521 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
523 /* We cannot expect a graceful transmit stop without link !!! */
525 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
527 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
528 printk("fec_stop : Graceful transmit stop did not complete !\n");
531 /* Whack a reset. We should wait for this. */
532 writel(1, fep->hwp + FEC_ECNTRL);
534 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
535 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
537 /* We have to keep ENET enabled to have MII interrupt stay working */
538 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
539 writel(2, fep->hwp + FEC_ECNTRL);
540 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
546 fec_timeout(struct net_device *ndev)
548 struct fec_enet_private *fep = netdev_priv(ndev);
550 ndev->stats.tx_errors++;
552 fec_restart(ndev, fep->full_duplex);
553 netif_wake_queue(ndev);
557 fec_enet_tx(struct net_device *ndev)
559 struct fec_enet_private *fep;
561 unsigned short status;
565 fep = netdev_priv(ndev);
568 /* get next bdp of dirty_tx */
569 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
570 bdp = fep->tx_bd_base;
572 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
574 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
576 /* current queue is empty */
577 if (bdp == fep->cur_tx)
581 index = (struct bufdesc_ex *)bdp -
582 (struct bufdesc_ex *)fep->tx_bd_base;
584 index = bdp - fep->tx_bd_base;
586 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
587 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
588 bdp->cbd_bufaddr = 0;
590 skb = fep->tx_skbuff[index];
592 /* Check for errors. */
593 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
594 BD_ENET_TX_RL | BD_ENET_TX_UN |
596 ndev->stats.tx_errors++;
597 if (status & BD_ENET_TX_HB) /* No heartbeat */
598 ndev->stats.tx_heartbeat_errors++;
599 if (status & BD_ENET_TX_LC) /* Late collision */
600 ndev->stats.tx_window_errors++;
601 if (status & BD_ENET_TX_RL) /* Retrans limit */
602 ndev->stats.tx_aborted_errors++;
603 if (status & BD_ENET_TX_UN) /* Underrun */
604 ndev->stats.tx_fifo_errors++;
605 if (status & BD_ENET_TX_CSL) /* Carrier lost */
606 ndev->stats.tx_carrier_errors++;
608 ndev->stats.tx_packets++;
611 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
613 struct skb_shared_hwtstamps shhwtstamps;
615 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
617 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
618 spin_lock_irqsave(&fep->tmreg_lock, flags);
619 shhwtstamps.hwtstamp = ns_to_ktime(
620 timecounter_cyc2time(&fep->tc, ebdp->ts));
621 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
622 skb_tstamp_tx(skb, &shhwtstamps);
625 if (status & BD_ENET_TX_READY)
626 printk("HEY! Enet xmit interrupt and TX_READY.\n");
628 /* Deferred means some collisions occurred during transmit,
629 * but we eventually sent the packet OK.
631 if (status & BD_ENET_TX_DEF)
632 ndev->stats.collisions++;
634 /* Free the sk buffer associated with this last transmit */
635 dev_kfree_skb_any(skb);
636 fep->tx_skbuff[index] = NULL;
640 /* Update pointer to next buffer descriptor to be transmitted */
641 if (status & BD_ENET_TX_WRAP)
642 bdp = fep->tx_bd_base;
644 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
646 /* Since we have freed up a buffer, the ring is no longer full
648 if (fep->dirty_tx != fep->cur_tx) {
649 if (netif_queue_stopped(ndev))
650 netif_wake_queue(ndev);
657 /* During a receive, the cur_rx points to the current incoming buffer.
658 * When we update through the ring, if the next incoming buffer has
659 * not been given to the system, we just set the empty indicator,
660 * effectively tossing the packet.
663 fec_enet_rx(struct net_device *ndev, int budget)
665 struct fec_enet_private *fep = netdev_priv(ndev);
666 const struct platform_device_id *id_entry =
667 platform_get_device_id(fep->pdev);
669 unsigned short status;
673 int pkt_received = 0;
679 /* First, grab all of the stats for the incoming packet.
680 * These get messed up if we get called due to a busy condition.
684 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
686 if (pkt_received >= budget)
690 /* Since we have allocated space to hold a complete frame,
691 * the last indicator should be set.
693 if ((status & BD_ENET_RX_LAST) == 0)
694 printk("FEC ENET: rcv is not +last\n");
697 goto rx_processing_done;
699 /* Check for errors. */
700 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
701 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
702 ndev->stats.rx_errors++;
703 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
704 /* Frame too long or too short. */
705 ndev->stats.rx_length_errors++;
707 if (status & BD_ENET_RX_NO) /* Frame alignment */
708 ndev->stats.rx_frame_errors++;
709 if (status & BD_ENET_RX_CR) /* CRC Error */
710 ndev->stats.rx_crc_errors++;
711 if (status & BD_ENET_RX_OV) /* FIFO overrun */
712 ndev->stats.rx_fifo_errors++;
715 /* Report late collisions as a frame error.
716 * On this error, the BD is closed, but we don't know what we
717 * have in the buffer. So, just drop this frame on the floor.
719 if (status & BD_ENET_RX_CL) {
720 ndev->stats.rx_errors++;
721 ndev->stats.rx_frame_errors++;
722 goto rx_processing_done;
725 /* Process the incoming frame. */
726 ndev->stats.rx_packets++;
727 pkt_len = bdp->cbd_datlen;
728 ndev->stats.rx_bytes += pkt_len;
729 data = (__u8*)__va(bdp->cbd_bufaddr);
731 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
732 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
734 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
735 swap_buffer(data, pkt_len);
737 /* This does 16 byte alignment, exactly what we need.
738 * The packet length includes FCS, but we don't want to
739 * include that when passing upstream as it messes up
740 * bridging applications.
742 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
744 if (unlikely(!skb)) {
745 ndev->stats.rx_dropped++;
747 skb_reserve(skb, NET_IP_ALIGN);
748 skb_put(skb, pkt_len - 4); /* Make room */
749 skb_copy_to_linear_data(skb, data, pkt_len - 4);
750 skb->protocol = eth_type_trans(skb, ndev);
752 /* Get receive timestamp from the skb */
753 if (fep->hwts_rx_en && fep->bufdesc_ex) {
754 struct skb_shared_hwtstamps *shhwtstamps =
757 struct bufdesc_ex *ebdp =
758 (struct bufdesc_ex *)bdp;
760 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
762 spin_lock_irqsave(&fep->tmreg_lock, flags);
763 shhwtstamps->hwtstamp = ns_to_ktime(
764 timecounter_cyc2time(&fep->tc, ebdp->ts));
765 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
768 if (!skb_defer_rx_timestamp(skb))
769 napi_gro_receive(&fep->napi, skb);
772 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
773 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
775 /* Clear the status flags for this buffer */
776 status &= ~BD_ENET_RX_STATS;
778 /* Mark the buffer empty */
779 status |= BD_ENET_RX_EMPTY;
780 bdp->cbd_sc = status;
782 if (fep->bufdesc_ex) {
783 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
785 ebdp->cbd_esc = BD_ENET_RX_INT;
790 /* Update BD pointer to next entry */
791 if (status & BD_ENET_RX_WRAP)
792 bdp = fep->rx_bd_base;
794 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
795 /* Doing this here will keep the FEC running while we process
796 * incoming frames. On a heavily loaded network, we should be
797 * able to keep up at the expense of system resources.
799 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
807 fec_enet_interrupt(int irq, void *dev_id)
809 struct net_device *ndev = dev_id;
810 struct fec_enet_private *fep = netdev_priv(ndev);
812 irqreturn_t ret = IRQ_NONE;
815 int_events = readl(fep->hwp + FEC_IEVENT);
816 writel(int_events, fep->hwp + FEC_IEVENT);
818 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
821 /* Disable the RX interrupt */
822 if (napi_schedule_prep(&fep->napi)) {
823 writel(FEC_RX_DISABLED_IMASK,
824 fep->hwp + FEC_IMASK);
825 __napi_schedule(&fep->napi);
829 if (int_events & FEC_ENET_MII) {
831 complete(&fep->mdio_done);
833 } while (int_events);
838 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
840 struct net_device *ndev = napi->dev;
841 int pkts = fec_enet_rx(ndev, budget);
842 struct fec_enet_private *fep = netdev_priv(ndev);
848 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
853 /* ------------------------------------------------------------------------- */
854 static void fec_get_mac(struct net_device *ndev)
856 struct fec_enet_private *fep = netdev_priv(ndev);
857 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
858 unsigned char *iap, tmpaddr[ETH_ALEN];
861 * try to get mac address in following order:
863 * 1) module parameter via kernel command line in form
864 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
870 * 2) from device tree data
872 if (!is_valid_ether_addr(iap)) {
873 struct device_node *np = fep->pdev->dev.of_node;
875 const char *mac = of_get_mac_address(np);
877 iap = (unsigned char *) mac;
883 * 3) from flash or fuse (via platform data)
885 if (!is_valid_ether_addr(iap)) {
888 iap = (unsigned char *)FEC_FLASHMAC;
891 iap = (unsigned char *)&pdata->mac;
896 * 4) FEC mac registers set by bootloader
898 if (!is_valid_ether_addr(iap)) {
899 *((unsigned long *) &tmpaddr[0]) =
900 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
901 *((unsigned short *) &tmpaddr[4]) =
902 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
906 memcpy(ndev->dev_addr, iap, ETH_ALEN);
908 /* Adjust MAC if using macaddr */
910 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
913 /* ------------------------------------------------------------------------- */
918 static void fec_enet_adjust_link(struct net_device *ndev)
920 struct fec_enet_private *fep = netdev_priv(ndev);
921 struct phy_device *phy_dev = fep->phy_dev;
924 int status_change = 0;
926 spin_lock_irqsave(&fep->hw_lock, flags);
928 /* Prevent a state halted on mii error */
929 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
930 phy_dev->state = PHY_RESUMING;
936 fep->link = phy_dev->link;
940 if (fep->full_duplex != phy_dev->duplex)
943 if (phy_dev->speed != fep->speed) {
944 fep->speed = phy_dev->speed;
948 /* if any of the above changed restart the FEC */
950 fec_restart(ndev, phy_dev->duplex);
959 spin_unlock_irqrestore(&fep->hw_lock, flags);
962 phy_print_status(phy_dev);
965 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
967 struct fec_enet_private *fep = bus->priv;
968 unsigned long time_left;
970 fep->mii_timeout = 0;
971 init_completion(&fep->mdio_done);
973 /* start a read op */
974 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
975 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
976 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
978 /* wait for end of transfer */
979 time_left = wait_for_completion_timeout(&fep->mdio_done,
980 usecs_to_jiffies(FEC_MII_TIMEOUT));
981 if (time_left == 0) {
982 fep->mii_timeout = 1;
983 printk(KERN_ERR "FEC: MDIO read timeout\n");
988 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
991 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
994 struct fec_enet_private *fep = bus->priv;
995 unsigned long time_left;
997 fep->mii_timeout = 0;
998 init_completion(&fep->mdio_done);
1000 /* start a write op */
1001 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1002 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1003 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1004 fep->hwp + FEC_MII_DATA);
1006 /* wait for end of transfer */
1007 time_left = wait_for_completion_timeout(&fep->mdio_done,
1008 usecs_to_jiffies(FEC_MII_TIMEOUT));
1009 if (time_left == 0) {
1010 fep->mii_timeout = 1;
1011 printk(KERN_ERR "FEC: MDIO write timeout\n");
1018 static int fec_enet_mdio_reset(struct mii_bus *bus)
1023 static int fec_enet_mii_probe(struct net_device *ndev)
1025 struct fec_enet_private *fep = netdev_priv(ndev);
1026 const struct platform_device_id *id_entry =
1027 platform_get_device_id(fep->pdev);
1028 struct phy_device *phy_dev = NULL;
1029 char mdio_bus_id[MII_BUS_ID_SIZE];
1030 char phy_name[MII_BUS_ID_SIZE + 3];
1032 int dev_id = fep->dev_id;
1034 fep->phy_dev = NULL;
1036 /* check for attached phy */
1037 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1038 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1040 if (fep->mii_bus->phy_map[phy_id] == NULL)
1042 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1046 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1050 if (phy_id >= PHY_MAX_ADDR) {
1052 "%s: no PHY, assuming direct connection to switch\n",
1054 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1058 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1059 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1060 fep->phy_interface);
1061 if (IS_ERR(phy_dev)) {
1062 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1063 return PTR_ERR(phy_dev);
1066 /* mask with MAC supported features */
1067 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1068 phy_dev->supported &= PHY_GBIT_FEATURES;
1069 phy_dev->supported |= SUPPORTED_Pause;
1072 phy_dev->supported &= PHY_BASIC_FEATURES;
1074 phy_dev->advertising = phy_dev->supported;
1076 fep->phy_dev = phy_dev;
1078 fep->full_duplex = 0;
1081 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1083 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1089 static int fec_enet_mii_init(struct platform_device *pdev)
1091 static struct mii_bus *fec0_mii_bus;
1092 struct net_device *ndev = platform_get_drvdata(pdev);
1093 struct fec_enet_private *fep = netdev_priv(ndev);
1094 const struct platform_device_id *id_entry =
1095 platform_get_device_id(fep->pdev);
1096 int err = -ENXIO, i;
1099 * The dual fec interfaces are not equivalent with enet-mac.
1100 * Here are the differences:
1102 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1103 * - fec0 acts as the 1588 time master while fec1 is slave
1104 * - external phys can only be configured by fec0
1106 * That is to say fec1 can not work independently. It only works
1107 * when fec0 is working. The reason behind this design is that the
1108 * second interface is added primarily for Switch mode.
1110 * Because of the last point above, both phys are attached on fec0
1111 * mdio interface in board design, and need to be configured by
1114 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1115 /* fec1 uses fec0 mii_bus */
1116 if (mii_cnt && fec0_mii_bus) {
1117 fep->mii_bus = fec0_mii_bus;
1124 fep->mii_timeout = 0;
1127 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1129 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1130 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1131 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1134 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1135 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1137 fep->phy_speed <<= 1;
1138 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1140 fep->mii_bus = mdiobus_alloc();
1141 if (fep->mii_bus == NULL) {
1146 fep->mii_bus->name = "fec_enet_mii_bus";
1147 fep->mii_bus->read = fec_enet_mdio_read;
1148 fep->mii_bus->write = fec_enet_mdio_write;
1149 fep->mii_bus->reset = fec_enet_mdio_reset;
1150 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1151 pdev->name, fep->dev_id + 1);
1152 fep->mii_bus->priv = fep;
1153 fep->mii_bus->parent = &pdev->dev;
1155 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1156 if (!fep->mii_bus->irq) {
1158 goto err_out_free_mdiobus;
1161 for (i = 0; i < PHY_MAX_ADDR; i++)
1162 fep->mii_bus->irq[i] = PHY_POLL;
1164 if (mdiobus_register(fep->mii_bus))
1165 goto err_out_free_mdio_irq;
1169 /* save fec0 mii_bus */
1170 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1171 fec0_mii_bus = fep->mii_bus;
1175 err_out_free_mdio_irq:
1176 kfree(fep->mii_bus->irq);
1177 err_out_free_mdiobus:
1178 mdiobus_free(fep->mii_bus);
1183 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1185 if (--mii_cnt == 0) {
1186 mdiobus_unregister(fep->mii_bus);
1187 kfree(fep->mii_bus->irq);
1188 mdiobus_free(fep->mii_bus);
1192 static int fec_enet_get_settings(struct net_device *ndev,
1193 struct ethtool_cmd *cmd)
1195 struct fec_enet_private *fep = netdev_priv(ndev);
1196 struct phy_device *phydev = fep->phy_dev;
1201 return phy_ethtool_gset(phydev, cmd);
1204 static int fec_enet_set_settings(struct net_device *ndev,
1205 struct ethtool_cmd *cmd)
1207 struct fec_enet_private *fep = netdev_priv(ndev);
1208 struct phy_device *phydev = fep->phy_dev;
1213 return phy_ethtool_sset(phydev, cmd);
1216 static void fec_enet_get_drvinfo(struct net_device *ndev,
1217 struct ethtool_drvinfo *info)
1219 struct fec_enet_private *fep = netdev_priv(ndev);
1221 strlcpy(info->driver, fep->pdev->dev.driver->name,
1222 sizeof(info->driver));
1223 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1224 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1227 static int fec_enet_get_ts_info(struct net_device *ndev,
1228 struct ethtool_ts_info *info)
1230 struct fec_enet_private *fep = netdev_priv(ndev);
1232 if (fep->bufdesc_ex) {
1234 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1235 SOF_TIMESTAMPING_RX_SOFTWARE |
1236 SOF_TIMESTAMPING_SOFTWARE |
1237 SOF_TIMESTAMPING_TX_HARDWARE |
1238 SOF_TIMESTAMPING_RX_HARDWARE |
1239 SOF_TIMESTAMPING_RAW_HARDWARE;
1241 info->phc_index = ptp_clock_index(fep->ptp_clock);
1243 info->phc_index = -1;
1245 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1246 (1 << HWTSTAMP_TX_ON);
1248 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1249 (1 << HWTSTAMP_FILTER_ALL);
1252 return ethtool_op_get_ts_info(ndev, info);
1256 static void fec_enet_get_pauseparam(struct net_device *ndev,
1257 struct ethtool_pauseparam *pause)
1259 struct fec_enet_private *fep = netdev_priv(ndev);
1261 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1262 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1263 pause->rx_pause = pause->tx_pause;
1266 static int fec_enet_set_pauseparam(struct net_device *ndev,
1267 struct ethtool_pauseparam *pause)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1271 if (pause->tx_pause != pause->rx_pause) {
1273 "hardware only support enable/disable both tx and rx");
1277 fep->pause_flag = 0;
1279 /* tx pause must be same as rx pause */
1280 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1281 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1283 if (pause->rx_pause || pause->autoneg) {
1284 fep->phy_dev->supported |= ADVERTISED_Pause;
1285 fep->phy_dev->advertising |= ADVERTISED_Pause;
1287 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1288 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1291 if (pause->autoneg) {
1292 if (netif_running(ndev))
1294 phy_start_aneg(fep->phy_dev);
1296 if (netif_running(ndev))
1297 fec_restart(ndev, 0);
1302 static const struct ethtool_ops fec_enet_ethtool_ops = {
1303 .get_pauseparam = fec_enet_get_pauseparam,
1304 .set_pauseparam = fec_enet_set_pauseparam,
1305 .get_settings = fec_enet_get_settings,
1306 .set_settings = fec_enet_set_settings,
1307 .get_drvinfo = fec_enet_get_drvinfo,
1308 .get_link = ethtool_op_get_link,
1309 .get_ts_info = fec_enet_get_ts_info,
1312 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1314 struct fec_enet_private *fep = netdev_priv(ndev);
1315 struct phy_device *phydev = fep->phy_dev;
1317 if (!netif_running(ndev))
1323 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1324 return fec_ptp_ioctl(ndev, rq, cmd);
1326 return phy_mii_ioctl(phydev, rq, cmd);
1329 static void fec_enet_free_buffers(struct net_device *ndev)
1331 struct fec_enet_private *fep = netdev_priv(ndev);
1333 struct sk_buff *skb;
1334 struct bufdesc *bdp;
1336 bdp = fep->rx_bd_base;
1337 for (i = 0; i < RX_RING_SIZE; i++) {
1338 skb = fep->rx_skbuff[i];
1340 if (bdp->cbd_bufaddr)
1341 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1342 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1345 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1348 bdp = fep->tx_bd_base;
1349 for (i = 0; i < TX_RING_SIZE; i++)
1350 kfree(fep->tx_bounce[i]);
1353 static int fec_enet_alloc_buffers(struct net_device *ndev)
1355 struct fec_enet_private *fep = netdev_priv(ndev);
1357 struct sk_buff *skb;
1358 struct bufdesc *bdp;
1360 bdp = fep->rx_bd_base;
1361 for (i = 0; i < RX_RING_SIZE; i++) {
1362 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1364 fec_enet_free_buffers(ndev);
1367 fep->rx_skbuff[i] = skb;
1369 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1370 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1371 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1373 if (fep->bufdesc_ex) {
1374 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1375 ebdp->cbd_esc = BD_ENET_RX_INT;
1378 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1381 /* Set the last buffer to wrap. */
1382 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1383 bdp->cbd_sc |= BD_SC_WRAP;
1385 bdp = fep->tx_bd_base;
1386 for (i = 0; i < TX_RING_SIZE; i++) {
1387 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1390 bdp->cbd_bufaddr = 0;
1392 if (fep->bufdesc_ex) {
1393 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1394 ebdp->cbd_esc = BD_ENET_RX_INT;
1397 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1400 /* Set the last buffer to wrap. */
1401 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1402 bdp->cbd_sc |= BD_SC_WRAP;
1408 fec_enet_open(struct net_device *ndev)
1410 struct fec_enet_private *fep = netdev_priv(ndev);
1413 napi_enable(&fep->napi);
1415 /* I should reset the ring buffers here, but I don't yet know
1416 * a simple way to do that.
1419 ret = fec_enet_alloc_buffers(ndev);
1423 /* Probe and connect to PHY when open the interface */
1424 ret = fec_enet_mii_probe(ndev);
1426 fec_enet_free_buffers(ndev);
1429 phy_start(fep->phy_dev);
1430 netif_start_queue(ndev);
1436 fec_enet_close(struct net_device *ndev)
1438 struct fec_enet_private *fep = netdev_priv(ndev);
1440 /* Don't know what to do yet. */
1441 napi_disable(&fep->napi);
1443 netif_stop_queue(ndev);
1447 phy_stop(fep->phy_dev);
1448 phy_disconnect(fep->phy_dev);
1451 fec_enet_free_buffers(ndev);
1456 /* Set or clear the multicast filter for this adaptor.
1457 * Skeleton taken from sunlance driver.
1458 * The CPM Ethernet implementation allows Multicast as well as individual
1459 * MAC address filtering. Some of the drivers check to make sure it is
1460 * a group multicast address, and discard those that are not. I guess I
1461 * will do the same for now, but just remove the test if you want
1462 * individual filtering as well (do the upper net layers want or support
1463 * this kind of feature?).
1466 #define HASH_BITS 6 /* #bits in hash */
1467 #define CRC32_POLY 0xEDB88320
1469 static void set_multicast_list(struct net_device *ndev)
1471 struct fec_enet_private *fep = netdev_priv(ndev);
1472 struct netdev_hw_addr *ha;
1473 unsigned int i, bit, data, crc, tmp;
1476 if (ndev->flags & IFF_PROMISC) {
1477 tmp = readl(fep->hwp + FEC_R_CNTRL);
1479 writel(tmp, fep->hwp + FEC_R_CNTRL);
1483 tmp = readl(fep->hwp + FEC_R_CNTRL);
1485 writel(tmp, fep->hwp + FEC_R_CNTRL);
1487 if (ndev->flags & IFF_ALLMULTI) {
1488 /* Catch all multicast addresses, so set the
1491 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1492 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1497 /* Clear filter and add the addresses in hash register
1499 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1500 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1502 netdev_for_each_mc_addr(ha, ndev) {
1503 /* calculate crc32 value of mac address */
1506 for (i = 0; i < ndev->addr_len; i++) {
1508 for (bit = 0; bit < 8; bit++, data >>= 1) {
1510 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1514 /* only upper 6 bits (HASH_BITS) are used
1515 * which point to specific bit in he hash registers
1517 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1520 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1521 tmp |= 1 << (hash - 32);
1522 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1524 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1526 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1531 /* Set a MAC change in hardware. */
1533 fec_set_mac_address(struct net_device *ndev, void *p)
1535 struct fec_enet_private *fep = netdev_priv(ndev);
1536 struct sockaddr *addr = p;
1538 if (!is_valid_ether_addr(addr->sa_data))
1539 return -EADDRNOTAVAIL;
1541 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1543 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1544 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1545 fep->hwp + FEC_ADDR_LOW);
1546 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1547 fep->hwp + FEC_ADDR_HIGH);
1551 #ifdef CONFIG_NET_POLL_CONTROLLER
1553 * fec_poll_controller - FEC Poll controller function
1554 * @dev: The FEC network adapter
1556 * Polled functionality used by netconsole and others in non interrupt mode
1559 static void fec_poll_controller(struct net_device *dev)
1562 struct fec_enet_private *fep = netdev_priv(dev);
1564 for (i = 0; i < FEC_IRQ_NUM; i++) {
1565 if (fep->irq[i] > 0) {
1566 disable_irq(fep->irq[i]);
1567 fec_enet_interrupt(fep->irq[i], dev);
1568 enable_irq(fep->irq[i]);
1574 static const struct net_device_ops fec_netdev_ops = {
1575 .ndo_open = fec_enet_open,
1576 .ndo_stop = fec_enet_close,
1577 .ndo_start_xmit = fec_enet_start_xmit,
1578 .ndo_set_rx_mode = set_multicast_list,
1579 .ndo_change_mtu = eth_change_mtu,
1580 .ndo_validate_addr = eth_validate_addr,
1581 .ndo_tx_timeout = fec_timeout,
1582 .ndo_set_mac_address = fec_set_mac_address,
1583 .ndo_do_ioctl = fec_enet_ioctl,
1584 #ifdef CONFIG_NET_POLL_CONTROLLER
1585 .ndo_poll_controller = fec_poll_controller,
1590 * XXX: We need to clean up on failure exits here.
1593 static int fec_enet_init(struct net_device *ndev)
1595 struct fec_enet_private *fep = netdev_priv(ndev);
1596 struct bufdesc *cbd_base;
1597 struct bufdesc *bdp;
1600 /* Allocate memory for buffer descriptors. */
1601 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1606 spin_lock_init(&fep->hw_lock);
1610 /* Get the Ethernet address */
1613 /* Set receive and transmit descriptor base. */
1614 fep->rx_bd_base = cbd_base;
1615 if (fep->bufdesc_ex)
1616 fep->tx_bd_base = (struct bufdesc *)
1617 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1619 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1621 /* The FEC Ethernet specific entries in the device structure */
1622 ndev->watchdog_timeo = TX_TIMEOUT;
1623 ndev->netdev_ops = &fec_netdev_ops;
1624 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1626 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1627 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1629 /* Initialize the receive buffer descriptors. */
1630 bdp = fep->rx_bd_base;
1631 for (i = 0; i < RX_RING_SIZE; i++) {
1633 /* Initialize the BD for every fragment in the page. */
1635 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1638 /* Set the last buffer to wrap */
1639 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1640 bdp->cbd_sc |= BD_SC_WRAP;
1642 /* ...and the same for transmit */
1643 bdp = fep->tx_bd_base;
1645 for (i = 0; i < TX_RING_SIZE; i++) {
1647 /* Initialize the BD for every fragment in the page. */
1649 bdp->cbd_bufaddr = 0;
1650 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1653 /* Set the last buffer to wrap */
1654 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1655 bdp->cbd_sc |= BD_SC_WRAP;
1656 fep->dirty_tx = bdp;
1658 fec_restart(ndev, 0);
1664 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1666 struct device_node *np = pdev->dev.of_node;
1669 return of_get_phy_mode(np);
1674 static void fec_reset_phy(struct platform_device *pdev)
1678 struct device_node *np = pdev->dev.of_node;
1683 of_property_read_u32(np, "phy-reset-duration", &msec);
1684 /* A sane reset duration should not be longer than 1s */
1688 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1689 if (!gpio_is_valid(phy_reset))
1692 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1693 GPIOF_OUT_INIT_LOW, "phy-reset");
1695 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1699 gpio_set_value(phy_reset, 1);
1701 #else /* CONFIG_OF */
1702 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1707 static void fec_reset_phy(struct platform_device *pdev)
1710 * In case of platform probe, the reset has been done
1714 #endif /* CONFIG_OF */
1717 fec_probe(struct platform_device *pdev)
1719 struct fec_enet_private *fep;
1720 struct fec_platform_data *pdata;
1721 struct net_device *ndev;
1722 int i, irq, ret = 0;
1724 const struct of_device_id *of_id;
1726 struct pinctrl *pinctrl;
1727 struct regulator *reg_phy;
1729 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1731 pdev->id_entry = of_id->data;
1733 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1737 /* Init network device */
1738 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1742 SET_NETDEV_DEV(ndev, &pdev->dev);
1744 /* setup board info structure */
1745 fep = netdev_priv(ndev);
1747 /* default enable pause frame auto negotiation */
1748 if (pdev->id_entry &&
1749 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1750 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1752 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1754 fep->dev_id = dev_id++;
1756 fep->bufdesc_ex = 0;
1760 goto failed_ioremap;
1763 platform_set_drvdata(pdev, ndev);
1765 ret = fec_get_phy_mode_dt(pdev);
1767 pdata = pdev->dev.platform_data;
1769 fep->phy_interface = pdata->phy;
1771 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1773 fep->phy_interface = ret;
1776 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1777 if (IS_ERR(pinctrl)) {
1778 ret = PTR_ERR(pinctrl);
1782 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1783 if (IS_ERR(fep->clk_ipg)) {
1784 ret = PTR_ERR(fep->clk_ipg);
1788 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1789 if (IS_ERR(fep->clk_ahb)) {
1790 ret = PTR_ERR(fep->clk_ahb);
1794 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1796 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1797 if (IS_ERR(fep->clk_ptp)) {
1798 ret = PTR_ERR(fep->clk_ptp);
1799 fep->bufdesc_ex = 0;
1802 clk_prepare_enable(fep->clk_ahb);
1803 clk_prepare_enable(fep->clk_ipg);
1804 if (!IS_ERR(fep->clk_ptp))
1805 clk_prepare_enable(fep->clk_ptp);
1807 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1808 if (!IS_ERR(reg_phy)) {
1809 ret = regulator_enable(reg_phy);
1812 "Failed to enable phy regulator: %d\n", ret);
1813 goto failed_regulator;
1817 fec_reset_phy(pdev);
1819 if (fep->bufdesc_ex)
1820 fec_ptp_init(ndev, pdev);
1822 ret = fec_enet_init(ndev);
1826 for (i = 0; i < FEC_IRQ_NUM; i++) {
1827 irq = platform_get_irq(pdev, i);
1834 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1837 irq = platform_get_irq(pdev, i);
1838 free_irq(irq, ndev);
1844 ret = fec_enet_mii_init(pdev);
1846 goto failed_mii_init;
1848 /* Carrier starts down, phylib will bring it up */
1849 netif_carrier_off(ndev);
1851 ret = register_netdev(ndev);
1853 goto failed_register;
1858 fec_enet_mii_remove(fep);
1861 for (i = 0; i < FEC_IRQ_NUM; i++) {
1862 irq = platform_get_irq(pdev, i);
1864 free_irq(irq, ndev);
1868 clk_disable_unprepare(fep->clk_ahb);
1869 clk_disable_unprepare(fep->clk_ipg);
1870 if (!IS_ERR(fep->clk_ptp))
1871 clk_disable_unprepare(fep->clk_ptp);
1881 fec_drv_remove(struct platform_device *pdev)
1883 struct net_device *ndev = platform_get_drvdata(pdev);
1884 struct fec_enet_private *fep = netdev_priv(ndev);
1887 unregister_netdev(ndev);
1888 fec_enet_mii_remove(fep);
1889 del_timer_sync(&fep->time_keep);
1890 clk_disable_unprepare(fep->clk_ptp);
1892 ptp_clock_unregister(fep->ptp_clock);
1893 clk_disable_unprepare(fep->clk_ahb);
1894 clk_disable_unprepare(fep->clk_ipg);
1895 for (i = 0; i < FEC_IRQ_NUM; i++) {
1896 int irq = platform_get_irq(pdev, i);
1898 free_irq(irq, ndev);
1902 platform_set_drvdata(pdev, NULL);
1909 fec_suspend(struct device *dev)
1911 struct net_device *ndev = dev_get_drvdata(dev);
1912 struct fec_enet_private *fep = netdev_priv(ndev);
1914 if (netif_running(ndev)) {
1916 netif_device_detach(ndev);
1918 clk_disable_unprepare(fep->clk_ahb);
1919 clk_disable_unprepare(fep->clk_ipg);
1925 fec_resume(struct device *dev)
1927 struct net_device *ndev = dev_get_drvdata(dev);
1928 struct fec_enet_private *fep = netdev_priv(ndev);
1930 clk_prepare_enable(fep->clk_ahb);
1931 clk_prepare_enable(fep->clk_ipg);
1932 if (netif_running(ndev)) {
1933 fec_restart(ndev, fep->full_duplex);
1934 netif_device_attach(ndev);
1940 static const struct dev_pm_ops fec_pm_ops = {
1941 .suspend = fec_suspend,
1942 .resume = fec_resume,
1943 .freeze = fec_suspend,
1945 .poweroff = fec_suspend,
1946 .restore = fec_resume,
1950 static struct platform_driver fec_driver = {
1952 .name = DRIVER_NAME,
1953 .owner = THIS_MODULE,
1957 .of_match_table = fec_dt_ids,
1959 .id_table = fec_devtype,
1961 .remove = fec_drv_remove,
1964 module_platform_driver(fec_driver);
1966 MODULE_LICENSE("GPL");