2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57 #include <linux/pinctrl/consumer.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
106 static struct platform_device_id fec_devtype[] = {
108 /* keep it for coldfire */
113 .driver_data = FEC_QUIRK_USE_GASKET,
119 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
126 .name = "mvf600-fec",
127 .driver_data = FEC_QUIRK_ENET_MAC,
132 MODULE_DEVICE_TABLE(platform, fec_devtype);
135 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
136 IMX27_FEC, /* runs on i.mx27/35/51 */
142 static const struct of_device_id fec_dt_ids[] = {
143 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
144 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
145 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
146 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
147 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
150 MODULE_DEVICE_TABLE(of, fec_dt_ids);
152 static unsigned char macaddr[ETH_ALEN];
153 module_param_array(macaddr, byte, NULL, 0);
154 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
156 #if defined(CONFIG_M5272)
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
161 #if defined(CONFIG_NETtel)
162 #define FEC_FLASHMAC 0xf0006006
163 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164 #define FEC_FLASHMAC 0xf0006000
165 #elif defined(CONFIG_CANCam)
166 #define FEC_FLASHMAC 0xf0020000
167 #elif defined (CONFIG_M5272C3)
168 #define FEC_FLASHMAC (0xffe04000 + 4)
169 #elif defined(CONFIG_MOD5272)
170 #define FEC_FLASHMAC 0xffc0406b
172 #define FEC_FLASHMAC 0
174 #endif /* CONFIG_M5272 */
176 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
177 #error "FEC: descriptor ring size constants too large"
180 /* Interrupt events/masks. */
181 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
182 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
183 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
184 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
185 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
186 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
187 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
188 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
189 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
190 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
192 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
193 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
195 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
197 #define PKT_MAXBUF_SIZE 1522
198 #define PKT_MINBUF_SIZE 64
199 #define PKT_MAXBLR_SIZE 1536
201 /* FEC receive acceleration */
202 #define FEC_RACC_IPDIS (1 << 1)
203 #define FEC_RACC_PRODIS (1 << 2)
204 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
207 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
208 * size bits. Other FEC hardware does not, so we need to take that into
209 * account when setting it.
211 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
212 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
213 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
215 #define OPT_FRAME_SIZE 0
218 /* FEC MII MMFR bits definition */
219 #define FEC_MMFR_ST (1 << 30)
220 #define FEC_MMFR_OP_READ (2 << 28)
221 #define FEC_MMFR_OP_WRITE (1 << 28)
222 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
223 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
224 #define FEC_MMFR_TA (2 << 16)
225 #define FEC_MMFR_DATA(v) (v & 0xffff)
227 #define FEC_MII_TIMEOUT 30000 /* us */
229 /* Transmitter timeout */
230 #define TX_TIMEOUT (2 * HZ)
232 #define FEC_PAUSE_FLAG_AUTONEG 0x1
233 #define FEC_PAUSE_FLAG_ENABLE 0x2
238 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
240 struct bufdesc *new_bd = bdp + 1;
241 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
242 struct bufdesc_ex *ex_base;
243 struct bufdesc *base;
246 if (bdp >= fep->tx_bd_base) {
247 base = fep->tx_bd_base;
248 ring_size = fep->tx_ring_size;
249 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
251 base = fep->rx_bd_base;
252 ring_size = fep->rx_ring_size;
253 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
257 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
258 ex_base : ex_new_bd);
260 return (new_bd >= (base + ring_size)) ?
265 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
267 struct bufdesc *new_bd = bdp - 1;
268 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
269 struct bufdesc_ex *ex_base;
270 struct bufdesc *base;
273 if (bdp >= fep->tx_bd_base) {
274 base = fep->tx_bd_base;
275 ring_size = fep->tx_ring_size;
276 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
278 base = fep->rx_bd_base;
279 ring_size = fep->rx_ring_size;
280 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
284 return (struct bufdesc *)((ex_new_bd < ex_base) ?
285 (ex_new_bd + ring_size) : ex_new_bd);
287 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
290 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
291 struct fec_enet_private *fep)
293 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
296 static void *swap_buffer(void *bufaddr, int len)
299 unsigned int *buf = bufaddr;
301 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
302 *buf = cpu_to_be32(*buf);
308 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
310 /* Only run for packets requiring a checksum. */
311 if (skb->ip_summed != CHECKSUM_PARTIAL)
314 if (unlikely(skb_cow_head(skb, 0)))
317 ip_hdr(skb)->check = 0;
318 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
323 static int txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
325 struct fec_enet_private *fep = netdev_priv(ndev);
326 const struct platform_device_id *id_entry =
327 platform_get_device_id(fep->pdev);
328 struct bufdesc *bdp, *bdp_pre;
330 unsigned short status;
333 /* Fill in a Tx ring entry */
336 status = bdp->cbd_sc;
338 /* Protocol checksum off-load for TCP and UDP. */
339 if (fec_enet_clear_csum(skb, ndev)) {
340 dev_kfree_skb_any(skb);
344 /* Clear all of the status flags */
345 status &= ~BD_ENET_TX_STATS;
347 /* Set buffer length and buffer pointer */
349 bdp->cbd_datlen = skb->len;
351 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
353 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
354 memcpy(fep->tx_bounce[index], skb->data, skb->len);
355 bufaddr = fep->tx_bounce[index];
359 * Some design made an incorrect assumption on endian mode of
360 * the system that it's running on. As the result, driver has to
361 * swap every frame going to and coming from the controller.
363 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
364 swap_buffer(bufaddr, skb->len);
366 /* Save skb pointer */
367 fep->tx_skbuff[index] = skb;
369 /* Push the data cache so the CPM does not get stale memory
372 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
373 skb->len, DMA_TO_DEVICE);
374 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
375 bdp->cbd_bufaddr = 0;
376 fep->tx_skbuff[index] = NULL;
377 dev_kfree_skb_any(skb);
379 netdev_err(ndev, "Tx DMA memory map failed\n");
383 if (fep->bufdesc_ex) {
385 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
387 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
389 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
390 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
392 ebdp->cbd_esc = BD_ENET_TX_INT;
394 /* Enable protocol checksum flags
395 * We do not bother with the IP Checksum bits as they
396 * are done by the kernel
398 if (skb->ip_summed == CHECKSUM_PARTIAL)
399 ebdp->cbd_esc |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
403 /* Send it on its way. Tell FEC it's ready, interrupt when done,
404 * it's the last BD of the frame, and to put the CRC on the end.
406 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
407 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
408 bdp->cbd_sc = status;
410 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
411 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
412 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
413 fep->delay_work.trig_tx = true;
414 schedule_delayed_work(&(fep->delay_work.delay_work),
415 msecs_to_jiffies(1));
418 /* If this was the last BD in the ring, start at the beginning again. */
419 bdp = fec_enet_get_nextdesc(bdp, fep);
421 skb_tx_timestamp(skb);
425 /* Trigger transmission start */
426 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
432 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
434 struct fec_enet_private *fep = netdev_priv(ndev);
436 unsigned short status;
439 /* Fill in a Tx ring entry */
442 status = bdp->cbd_sc;
444 if (status & BD_ENET_TX_READY) {
445 /* Ooops. All transmit buffers are full. Bail out.
446 * This should not happen, since ndev->tbusy should be set.
448 netdev_err(ndev, "tx queue full!\n");
449 return NETDEV_TX_BUSY;
452 ret = txq_submit_skb(skb, ndev);
454 return NETDEV_TX_BUSY;
456 if (fep->cur_tx == fep->dirty_tx)
457 netif_stop_queue(ndev);
462 /* Init RX & TX buffer descriptors
464 static void fec_enet_bd_init(struct net_device *dev)
466 struct fec_enet_private *fep = netdev_priv(dev);
470 /* Initialize the receive buffer descriptors. */
471 bdp = fep->rx_bd_base;
472 for (i = 0; i < fep->rx_ring_size; i++) {
474 /* Initialize the BD for every fragment in the page. */
475 if (bdp->cbd_bufaddr)
476 bdp->cbd_sc = BD_ENET_RX_EMPTY;
479 bdp = fec_enet_get_nextdesc(bdp, fep);
482 /* Set the last buffer to wrap */
483 bdp = fec_enet_get_prevdesc(bdp, fep);
484 bdp->cbd_sc |= BD_SC_WRAP;
486 fep->cur_rx = fep->rx_bd_base;
488 /* ...and the same for transmit */
489 bdp = fep->tx_bd_base;
491 for (i = 0; i < fep->tx_ring_size; i++) {
493 /* Initialize the BD for every fragment in the page. */
495 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
496 dev_kfree_skb_any(fep->tx_skbuff[i]);
497 fep->tx_skbuff[i] = NULL;
499 bdp->cbd_bufaddr = 0;
500 bdp = fec_enet_get_nextdesc(bdp, fep);
503 /* Set the last buffer to wrap */
504 bdp = fec_enet_get_prevdesc(bdp, fep);
505 bdp->cbd_sc |= BD_SC_WRAP;
509 /* This function is called to start or restart the FEC during a link
510 * change. This only happens when switching between half and full
514 fec_restart(struct net_device *ndev, int duplex)
516 struct fec_enet_private *fep = netdev_priv(ndev);
517 const struct platform_device_id *id_entry =
518 platform_get_device_id(fep->pdev);
522 u32 rcntl = OPT_FRAME_SIZE | 0x04;
523 u32 ecntl = 0x2; /* ETHEREN */
525 if (netif_running(ndev)) {
526 netif_device_detach(ndev);
527 napi_disable(&fep->napi);
528 netif_stop_queue(ndev);
529 netif_tx_lock_bh(ndev);
532 /* Whack a reset. We should wait for this. */
533 writel(1, fep->hwp + FEC_ECNTRL);
537 * enet-mac reset will reset mac address registers too,
538 * so need to reconfigure it.
540 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
541 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
542 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
543 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
546 /* Clear any outstanding interrupt. */
547 writel(0xffc00000, fep->hwp + FEC_IEVENT);
549 /* Set maximum receive buffer size. */
550 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
552 fec_enet_bd_init(ndev);
554 /* Set receive and transmit descriptor base. */
555 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
557 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
558 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
560 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
561 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
564 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
565 if (fep->tx_skbuff[i]) {
566 dev_kfree_skb_any(fep->tx_skbuff[i]);
567 fep->tx_skbuff[i] = NULL;
571 /* Enable MII mode */
574 writel(0x04, fep->hwp + FEC_X_CNTRL);
578 writel(0x0, fep->hwp + FEC_X_CNTRL);
581 fep->full_duplex = duplex;
584 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
586 #if !defined(CONFIG_M5272)
587 /* set RX checksum */
588 val = readl(fep->hwp + FEC_RACC);
589 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
590 val |= FEC_RACC_OPTIONS;
592 val &= ~FEC_RACC_OPTIONS;
593 writel(val, fep->hwp + FEC_RACC);
597 * The phy interface and speed need to get configured
598 * differently on enet-mac.
600 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
601 /* Enable flow control and length check */
602 rcntl |= 0x40000000 | 0x00000020;
604 /* RGMII, RMII or MII */
605 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
607 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
612 /* 1G, 100M or 10M */
614 if (fep->phy_dev->speed == SPEED_1000)
616 else if (fep->phy_dev->speed == SPEED_100)
622 #ifdef FEC_MIIGSK_ENR
623 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
625 /* disable the gasket and wait */
626 writel(0, fep->hwp + FEC_MIIGSK_ENR);
627 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
631 * configure the gasket:
632 * RMII, 50 MHz, no loopback, no echo
633 * MII, 25 MHz, no loopback, no echo
635 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
636 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
637 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
638 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
639 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
641 /* re-enable the gasket */
642 writel(2, fep->hwp + FEC_MIIGSK_ENR);
647 #if !defined(CONFIG_M5272)
648 /* enable pause frame*/
649 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
650 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
651 fep->phy_dev && fep->phy_dev->pause)) {
652 rcntl |= FEC_ENET_FCE;
654 /* set FIFO threshold parameter to reduce overrun */
655 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
656 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
657 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
658 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
661 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
663 rcntl &= ~FEC_ENET_FCE;
665 #endif /* !defined(CONFIG_M5272) */
667 writel(rcntl, fep->hwp + FEC_R_CNTRL);
669 /* Setup multicast filter. */
670 set_multicast_list(ndev);
672 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
673 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
676 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
677 /* enable ENET endian swap */
679 /* enable ENET store and forward mode */
680 writel(1 << 8, fep->hwp + FEC_X_WMRK);
687 /* Enable the MIB statistic event counters */
688 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
691 /* And last, enable the transmit and receive processing */
692 writel(ecntl, fep->hwp + FEC_ECNTRL);
693 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
696 fec_ptp_start_cyclecounter(ndev);
698 /* Enable interrupts we wish to service */
699 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
701 if (netif_running(ndev)) {
702 netif_tx_unlock_bh(ndev);
703 netif_wake_queue(ndev);
704 napi_enable(&fep->napi);
705 netif_device_attach(ndev);
710 fec_stop(struct net_device *ndev)
712 struct fec_enet_private *fep = netdev_priv(ndev);
713 const struct platform_device_id *id_entry =
714 platform_get_device_id(fep->pdev);
715 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
717 /* We cannot expect a graceful transmit stop without link !!! */
719 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
721 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
722 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
725 /* Whack a reset. We should wait for this. */
726 writel(1, fep->hwp + FEC_ECNTRL);
728 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
729 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
731 /* We have to keep ENET enabled to have MII interrupt stay working */
732 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
733 writel(2, fep->hwp + FEC_ECNTRL);
734 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
740 fec_timeout(struct net_device *ndev)
742 struct fec_enet_private *fep = netdev_priv(ndev);
744 ndev->stats.tx_errors++;
746 fep->delay_work.timeout = true;
747 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
750 static void fec_enet_work(struct work_struct *work)
752 struct fec_enet_private *fep =
754 struct fec_enet_private,
755 delay_work.delay_work.work);
757 if (fep->delay_work.timeout) {
758 fep->delay_work.timeout = false;
759 fec_restart(fep->netdev, fep->full_duplex);
760 netif_wake_queue(fep->netdev);
763 if (fep->delay_work.trig_tx) {
764 fep->delay_work.trig_tx = false;
765 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
770 fec_enet_tx(struct net_device *ndev)
772 struct fec_enet_private *fep;
774 unsigned short status;
778 fep = netdev_priv(ndev);
781 /* get next bdp of dirty_tx */
782 bdp = fec_enet_get_nextdesc(bdp, fep);
784 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
786 /* current queue is empty */
787 if (bdp == fep->cur_tx)
790 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
792 skb = fep->tx_skbuff[index];
793 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
795 bdp->cbd_bufaddr = 0;
797 /* Check for errors. */
798 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
799 BD_ENET_TX_RL | BD_ENET_TX_UN |
801 ndev->stats.tx_errors++;
802 if (status & BD_ENET_TX_HB) /* No heartbeat */
803 ndev->stats.tx_heartbeat_errors++;
804 if (status & BD_ENET_TX_LC) /* Late collision */
805 ndev->stats.tx_window_errors++;
806 if (status & BD_ENET_TX_RL) /* Retrans limit */
807 ndev->stats.tx_aborted_errors++;
808 if (status & BD_ENET_TX_UN) /* Underrun */
809 ndev->stats.tx_fifo_errors++;
810 if (status & BD_ENET_TX_CSL) /* Carrier lost */
811 ndev->stats.tx_carrier_errors++;
813 ndev->stats.tx_packets++;
814 ndev->stats.tx_bytes += bdp->cbd_datlen;
817 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
819 struct skb_shared_hwtstamps shhwtstamps;
821 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
823 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
824 spin_lock_irqsave(&fep->tmreg_lock, flags);
825 shhwtstamps.hwtstamp = ns_to_ktime(
826 timecounter_cyc2time(&fep->tc, ebdp->ts));
827 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
828 skb_tstamp_tx(skb, &shhwtstamps);
831 if (status & BD_ENET_TX_READY)
832 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
834 /* Deferred means some collisions occurred during transmit,
835 * but we eventually sent the packet OK.
837 if (status & BD_ENET_TX_DEF)
838 ndev->stats.collisions++;
840 /* Free the sk buffer associated with this last transmit */
841 dev_kfree_skb_any(skb);
842 fep->tx_skbuff[index] = NULL;
846 /* Update pointer to next buffer descriptor to be transmitted */
847 bdp = fec_enet_get_nextdesc(bdp, fep);
849 /* Since we have freed up a buffer, the ring is no longer full
851 if (fep->dirty_tx != fep->cur_tx) {
852 if (netif_queue_stopped(ndev))
853 netif_wake_queue(ndev);
860 /* During a receive, the cur_rx points to the current incoming buffer.
861 * When we update through the ring, if the next incoming buffer has
862 * not been given to the system, we just set the empty indicator,
863 * effectively tossing the packet.
866 fec_enet_rx(struct net_device *ndev, int budget)
868 struct fec_enet_private *fep = netdev_priv(ndev);
869 const struct platform_device_id *id_entry =
870 platform_get_device_id(fep->pdev);
872 unsigned short status;
876 int pkt_received = 0;
877 struct bufdesc_ex *ebdp = NULL;
878 bool vlan_packet_rcvd = false;
886 /* First, grab all of the stats for the incoming packet.
887 * These get messed up if we get called due to a busy condition.
891 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
893 if (pkt_received >= budget)
897 /* Since we have allocated space to hold a complete frame,
898 * the last indicator should be set.
900 if ((status & BD_ENET_RX_LAST) == 0)
901 netdev_err(ndev, "rcv is not +last\n");
904 goto rx_processing_done;
906 /* Check for errors. */
907 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
908 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
909 ndev->stats.rx_errors++;
910 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
911 /* Frame too long or too short. */
912 ndev->stats.rx_length_errors++;
914 if (status & BD_ENET_RX_NO) /* Frame alignment */
915 ndev->stats.rx_frame_errors++;
916 if (status & BD_ENET_RX_CR) /* CRC Error */
917 ndev->stats.rx_crc_errors++;
918 if (status & BD_ENET_RX_OV) /* FIFO overrun */
919 ndev->stats.rx_fifo_errors++;
922 /* Report late collisions as a frame error.
923 * On this error, the BD is closed, but we don't know what we
924 * have in the buffer. So, just drop this frame on the floor.
926 if (status & BD_ENET_RX_CL) {
927 ndev->stats.rx_errors++;
928 ndev->stats.rx_frame_errors++;
929 goto rx_processing_done;
932 /* Process the incoming frame. */
933 ndev->stats.rx_packets++;
934 pkt_len = bdp->cbd_datlen;
935 ndev->stats.rx_bytes += pkt_len;
937 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
938 data = fep->rx_skbuff[index]->data;
939 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
940 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
942 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
943 swap_buffer(data, pkt_len);
945 /* Extract the enhanced buffer descriptor */
948 ebdp = (struct bufdesc_ex *)bdp;
950 /* If this is a VLAN packet remove the VLAN Tag */
951 vlan_packet_rcvd = false;
952 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
953 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
954 /* Push and remove the vlan tag */
955 struct vlan_hdr *vlan_header =
956 (struct vlan_hdr *) (data + ETH_HLEN);
957 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
958 pkt_len -= VLAN_HLEN;
960 vlan_packet_rcvd = true;
963 /* This does 16 byte alignment, exactly what we need.
964 * The packet length includes FCS, but we don't want to
965 * include that when passing upstream as it messes up
966 * bridging applications.
968 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
970 if (unlikely(!skb)) {
971 ndev->stats.rx_dropped++;
973 int payload_offset = (2 * ETH_ALEN);
974 skb_reserve(skb, NET_IP_ALIGN);
975 skb_put(skb, pkt_len - 4); /* Make room */
977 /* Extract the frame data without the VLAN header. */
978 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
979 if (vlan_packet_rcvd)
980 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
981 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
982 data + payload_offset,
983 pkt_len - 4 - (2 * ETH_ALEN));
985 skb->protocol = eth_type_trans(skb, ndev);
987 /* Get receive timestamp from the skb */
988 if (fep->hwts_rx_en && fep->bufdesc_ex) {
989 struct skb_shared_hwtstamps *shhwtstamps =
993 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
995 spin_lock_irqsave(&fep->tmreg_lock, flags);
996 shhwtstamps->hwtstamp = ns_to_ktime(
997 timecounter_cyc2time(&fep->tc, ebdp->ts));
998 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1001 if (fep->bufdesc_ex &&
1002 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1003 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1004 /* don't check it */
1005 skb->ip_summed = CHECKSUM_UNNECESSARY;
1007 skb_checksum_none_assert(skb);
1011 /* Handle received VLAN packets */
1012 if (vlan_packet_rcvd)
1013 __vlan_hwaccel_put_tag(skb,
1017 napi_gro_receive(&fep->napi, skb);
1020 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1021 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1023 /* Clear the status flags for this buffer */
1024 status &= ~BD_ENET_RX_STATS;
1026 /* Mark the buffer empty */
1027 status |= BD_ENET_RX_EMPTY;
1028 bdp->cbd_sc = status;
1030 if (fep->bufdesc_ex) {
1031 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1033 ebdp->cbd_esc = BD_ENET_RX_INT;
1038 /* Update BD pointer to next entry */
1039 bdp = fec_enet_get_nextdesc(bdp, fep);
1041 /* Doing this here will keep the FEC running while we process
1042 * incoming frames. On a heavily loaded network, we should be
1043 * able to keep up at the expense of system resources.
1045 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1049 return pkt_received;
1053 fec_enet_interrupt(int irq, void *dev_id)
1055 struct net_device *ndev = dev_id;
1056 struct fec_enet_private *fep = netdev_priv(ndev);
1058 irqreturn_t ret = IRQ_NONE;
1061 int_events = readl(fep->hwp + FEC_IEVENT);
1062 writel(int_events, fep->hwp + FEC_IEVENT);
1064 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1067 /* Disable the RX interrupt */
1068 if (napi_schedule_prep(&fep->napi)) {
1069 writel(FEC_RX_DISABLED_IMASK,
1070 fep->hwp + FEC_IMASK);
1071 __napi_schedule(&fep->napi);
1075 if (int_events & FEC_ENET_MII) {
1077 complete(&fep->mdio_done);
1079 } while (int_events);
1084 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1086 struct net_device *ndev = napi->dev;
1087 int pkts = fec_enet_rx(ndev, budget);
1088 struct fec_enet_private *fep = netdev_priv(ndev);
1092 if (pkts < budget) {
1093 napi_complete(napi);
1094 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1099 /* ------------------------------------------------------------------------- */
1100 static void fec_get_mac(struct net_device *ndev)
1102 struct fec_enet_private *fep = netdev_priv(ndev);
1103 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1104 unsigned char *iap, tmpaddr[ETH_ALEN];
1107 * try to get mac address in following order:
1109 * 1) module parameter via kernel command line in form
1110 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1115 * 2) from device tree data
1117 if (!is_valid_ether_addr(iap)) {
1118 struct device_node *np = fep->pdev->dev.of_node;
1120 const char *mac = of_get_mac_address(np);
1122 iap = (unsigned char *) mac;
1127 * 3) from flash or fuse (via platform data)
1129 if (!is_valid_ether_addr(iap)) {
1132 iap = (unsigned char *)FEC_FLASHMAC;
1135 iap = (unsigned char *)&pdata->mac;
1140 * 4) FEC mac registers set by bootloader
1142 if (!is_valid_ether_addr(iap)) {
1143 *((__be32 *) &tmpaddr[0]) =
1144 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1145 *((__be16 *) &tmpaddr[4]) =
1146 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1151 * 5) random mac address
1153 if (!is_valid_ether_addr(iap)) {
1154 /* Report it and use a random ethernet address instead */
1155 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1156 eth_hw_addr_random(ndev);
1157 netdev_info(ndev, "Using random MAC address: %pM\n",
1162 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1164 /* Adjust MAC if using macaddr */
1166 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1169 /* ------------------------------------------------------------------------- */
1174 static void fec_enet_adjust_link(struct net_device *ndev)
1176 struct fec_enet_private *fep = netdev_priv(ndev);
1177 struct phy_device *phy_dev = fep->phy_dev;
1178 int status_change = 0;
1180 /* Prevent a state halted on mii error */
1181 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1182 phy_dev->state = PHY_RESUMING;
1186 if (phy_dev->link) {
1188 fep->link = phy_dev->link;
1192 if (fep->full_duplex != phy_dev->duplex)
1195 if (phy_dev->speed != fep->speed) {
1196 fep->speed = phy_dev->speed;
1200 /* if any of the above changed restart the FEC */
1202 fec_restart(ndev, phy_dev->duplex);
1206 fep->link = phy_dev->link;
1212 phy_print_status(phy_dev);
1215 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1217 struct fec_enet_private *fep = bus->priv;
1218 unsigned long time_left;
1220 fep->mii_timeout = 0;
1221 init_completion(&fep->mdio_done);
1223 /* start a read op */
1224 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1225 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1226 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1228 /* wait for end of transfer */
1229 time_left = wait_for_completion_timeout(&fep->mdio_done,
1230 usecs_to_jiffies(FEC_MII_TIMEOUT));
1231 if (time_left == 0) {
1232 fep->mii_timeout = 1;
1233 netdev_err(fep->netdev, "MDIO read timeout\n");
1238 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1241 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1244 struct fec_enet_private *fep = bus->priv;
1245 unsigned long time_left;
1247 fep->mii_timeout = 0;
1248 init_completion(&fep->mdio_done);
1250 /* start a write op */
1251 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1252 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1253 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1254 fep->hwp + FEC_MII_DATA);
1256 /* wait for end of transfer */
1257 time_left = wait_for_completion_timeout(&fep->mdio_done,
1258 usecs_to_jiffies(FEC_MII_TIMEOUT));
1259 if (time_left == 0) {
1260 fep->mii_timeout = 1;
1261 netdev_err(fep->netdev, "MDIO write timeout\n");
1268 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1270 struct fec_enet_private *fep = netdev_priv(ndev);
1274 ret = clk_prepare_enable(fep->clk_ahb);
1277 ret = clk_prepare_enable(fep->clk_ipg);
1279 goto failed_clk_ipg;
1280 if (fep->clk_enet_out) {
1281 ret = clk_prepare_enable(fep->clk_enet_out);
1283 goto failed_clk_enet_out;
1286 ret = clk_prepare_enable(fep->clk_ptp);
1288 goto failed_clk_ptp;
1291 clk_disable_unprepare(fep->clk_ahb);
1292 clk_disable_unprepare(fep->clk_ipg);
1293 if (fep->clk_enet_out)
1294 clk_disable_unprepare(fep->clk_enet_out);
1296 clk_disable_unprepare(fep->clk_ptp);
1301 if (fep->clk_enet_out)
1302 clk_disable_unprepare(fep->clk_enet_out);
1303 failed_clk_enet_out:
1304 clk_disable_unprepare(fep->clk_ipg);
1306 clk_disable_unprepare(fep->clk_ahb);
1311 static int fec_enet_mii_probe(struct net_device *ndev)
1313 struct fec_enet_private *fep = netdev_priv(ndev);
1314 const struct platform_device_id *id_entry =
1315 platform_get_device_id(fep->pdev);
1316 struct phy_device *phy_dev = NULL;
1317 char mdio_bus_id[MII_BUS_ID_SIZE];
1318 char phy_name[MII_BUS_ID_SIZE + 3];
1320 int dev_id = fep->dev_id;
1322 fep->phy_dev = NULL;
1324 /* check for attached phy */
1325 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1326 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1328 if (fep->mii_bus->phy_map[phy_id] == NULL)
1330 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1334 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1338 if (phy_id >= PHY_MAX_ADDR) {
1339 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1340 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1344 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1345 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1346 fep->phy_interface);
1347 if (IS_ERR(phy_dev)) {
1348 netdev_err(ndev, "could not attach to PHY\n");
1349 return PTR_ERR(phy_dev);
1352 /* mask with MAC supported features */
1353 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1354 phy_dev->supported &= PHY_GBIT_FEATURES;
1355 #if !defined(CONFIG_M5272)
1356 phy_dev->supported |= SUPPORTED_Pause;
1360 phy_dev->supported &= PHY_BASIC_FEATURES;
1362 phy_dev->advertising = phy_dev->supported;
1364 fep->phy_dev = phy_dev;
1366 fep->full_duplex = 0;
1368 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1369 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1375 static int fec_enet_mii_init(struct platform_device *pdev)
1377 static struct mii_bus *fec0_mii_bus;
1378 struct net_device *ndev = platform_get_drvdata(pdev);
1379 struct fec_enet_private *fep = netdev_priv(ndev);
1380 const struct platform_device_id *id_entry =
1381 platform_get_device_id(fep->pdev);
1382 int err = -ENXIO, i;
1385 * The dual fec interfaces are not equivalent with enet-mac.
1386 * Here are the differences:
1388 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1389 * - fec0 acts as the 1588 time master while fec1 is slave
1390 * - external phys can only be configured by fec0
1392 * That is to say fec1 can not work independently. It only works
1393 * when fec0 is working. The reason behind this design is that the
1394 * second interface is added primarily for Switch mode.
1396 * Because of the last point above, both phys are attached on fec0
1397 * mdio interface in board design, and need to be configured by
1400 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1401 /* fec1 uses fec0 mii_bus */
1402 if (mii_cnt && fec0_mii_bus) {
1403 fep->mii_bus = fec0_mii_bus;
1410 fep->mii_timeout = 0;
1413 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1415 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1416 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1417 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1420 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1421 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1423 fep->phy_speed <<= 1;
1424 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1426 fep->mii_bus = mdiobus_alloc();
1427 if (fep->mii_bus == NULL) {
1432 fep->mii_bus->name = "fec_enet_mii_bus";
1433 fep->mii_bus->read = fec_enet_mdio_read;
1434 fep->mii_bus->write = fec_enet_mdio_write;
1435 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1436 pdev->name, fep->dev_id + 1);
1437 fep->mii_bus->priv = fep;
1438 fep->mii_bus->parent = &pdev->dev;
1440 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1441 if (!fep->mii_bus->irq) {
1443 goto err_out_free_mdiobus;
1446 for (i = 0; i < PHY_MAX_ADDR; i++)
1447 fep->mii_bus->irq[i] = PHY_POLL;
1449 if (mdiobus_register(fep->mii_bus))
1450 goto err_out_free_mdio_irq;
1454 /* save fec0 mii_bus */
1455 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1456 fec0_mii_bus = fep->mii_bus;
1460 err_out_free_mdio_irq:
1461 kfree(fep->mii_bus->irq);
1462 err_out_free_mdiobus:
1463 mdiobus_free(fep->mii_bus);
1468 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1470 if (--mii_cnt == 0) {
1471 mdiobus_unregister(fep->mii_bus);
1472 kfree(fep->mii_bus->irq);
1473 mdiobus_free(fep->mii_bus);
1477 static int fec_enet_get_settings(struct net_device *ndev,
1478 struct ethtool_cmd *cmd)
1480 struct fec_enet_private *fep = netdev_priv(ndev);
1481 struct phy_device *phydev = fep->phy_dev;
1486 return phy_ethtool_gset(phydev, cmd);
1489 static int fec_enet_set_settings(struct net_device *ndev,
1490 struct ethtool_cmd *cmd)
1492 struct fec_enet_private *fep = netdev_priv(ndev);
1493 struct phy_device *phydev = fep->phy_dev;
1498 return phy_ethtool_sset(phydev, cmd);
1501 static void fec_enet_get_drvinfo(struct net_device *ndev,
1502 struct ethtool_drvinfo *info)
1504 struct fec_enet_private *fep = netdev_priv(ndev);
1506 strlcpy(info->driver, fep->pdev->dev.driver->name,
1507 sizeof(info->driver));
1508 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1509 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1512 static int fec_enet_get_ts_info(struct net_device *ndev,
1513 struct ethtool_ts_info *info)
1515 struct fec_enet_private *fep = netdev_priv(ndev);
1517 if (fep->bufdesc_ex) {
1519 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1520 SOF_TIMESTAMPING_RX_SOFTWARE |
1521 SOF_TIMESTAMPING_SOFTWARE |
1522 SOF_TIMESTAMPING_TX_HARDWARE |
1523 SOF_TIMESTAMPING_RX_HARDWARE |
1524 SOF_TIMESTAMPING_RAW_HARDWARE;
1526 info->phc_index = ptp_clock_index(fep->ptp_clock);
1528 info->phc_index = -1;
1530 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1531 (1 << HWTSTAMP_TX_ON);
1533 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1534 (1 << HWTSTAMP_FILTER_ALL);
1537 return ethtool_op_get_ts_info(ndev, info);
1541 #if !defined(CONFIG_M5272)
1543 static void fec_enet_get_pauseparam(struct net_device *ndev,
1544 struct ethtool_pauseparam *pause)
1546 struct fec_enet_private *fep = netdev_priv(ndev);
1548 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1549 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1550 pause->rx_pause = pause->tx_pause;
1553 static int fec_enet_set_pauseparam(struct net_device *ndev,
1554 struct ethtool_pauseparam *pause)
1556 struct fec_enet_private *fep = netdev_priv(ndev);
1558 if (pause->tx_pause != pause->rx_pause) {
1560 "hardware only support enable/disable both tx and rx");
1564 fep->pause_flag = 0;
1566 /* tx pause must be same as rx pause */
1567 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1568 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1570 if (pause->rx_pause || pause->autoneg) {
1571 fep->phy_dev->supported |= ADVERTISED_Pause;
1572 fep->phy_dev->advertising |= ADVERTISED_Pause;
1574 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1575 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1578 if (pause->autoneg) {
1579 if (netif_running(ndev))
1581 phy_start_aneg(fep->phy_dev);
1583 if (netif_running(ndev))
1584 fec_restart(ndev, 0);
1589 static const struct fec_stat {
1590 char name[ETH_GSTRING_LEN];
1594 { "tx_dropped", RMON_T_DROP },
1595 { "tx_packets", RMON_T_PACKETS },
1596 { "tx_broadcast", RMON_T_BC_PKT },
1597 { "tx_multicast", RMON_T_MC_PKT },
1598 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1599 { "tx_undersize", RMON_T_UNDERSIZE },
1600 { "tx_oversize", RMON_T_OVERSIZE },
1601 { "tx_fragment", RMON_T_FRAG },
1602 { "tx_jabber", RMON_T_JAB },
1603 { "tx_collision", RMON_T_COL },
1604 { "tx_64byte", RMON_T_P64 },
1605 { "tx_65to127byte", RMON_T_P65TO127 },
1606 { "tx_128to255byte", RMON_T_P128TO255 },
1607 { "tx_256to511byte", RMON_T_P256TO511 },
1608 { "tx_512to1023byte", RMON_T_P512TO1023 },
1609 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1610 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1611 { "tx_octets", RMON_T_OCTETS },
1614 { "IEEE_tx_drop", IEEE_T_DROP },
1615 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1616 { "IEEE_tx_1col", IEEE_T_1COL },
1617 { "IEEE_tx_mcol", IEEE_T_MCOL },
1618 { "IEEE_tx_def", IEEE_T_DEF },
1619 { "IEEE_tx_lcol", IEEE_T_LCOL },
1620 { "IEEE_tx_excol", IEEE_T_EXCOL },
1621 { "IEEE_tx_macerr", IEEE_T_MACERR },
1622 { "IEEE_tx_cserr", IEEE_T_CSERR },
1623 { "IEEE_tx_sqe", IEEE_T_SQE },
1624 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1625 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1628 { "rx_packets", RMON_R_PACKETS },
1629 { "rx_broadcast", RMON_R_BC_PKT },
1630 { "rx_multicast", RMON_R_MC_PKT },
1631 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1632 { "rx_undersize", RMON_R_UNDERSIZE },
1633 { "rx_oversize", RMON_R_OVERSIZE },
1634 { "rx_fragment", RMON_R_FRAG },
1635 { "rx_jabber", RMON_R_JAB },
1636 { "rx_64byte", RMON_R_P64 },
1637 { "rx_65to127byte", RMON_R_P65TO127 },
1638 { "rx_128to255byte", RMON_R_P128TO255 },
1639 { "rx_256to511byte", RMON_R_P256TO511 },
1640 { "rx_512to1023byte", RMON_R_P512TO1023 },
1641 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1642 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1643 { "rx_octets", RMON_R_OCTETS },
1646 { "IEEE_rx_drop", IEEE_R_DROP },
1647 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1648 { "IEEE_rx_crc", IEEE_R_CRC },
1649 { "IEEE_rx_align", IEEE_R_ALIGN },
1650 { "IEEE_rx_macerr", IEEE_R_MACERR },
1651 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1652 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1655 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1656 struct ethtool_stats *stats, u64 *data)
1658 struct fec_enet_private *fep = netdev_priv(dev);
1661 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1662 data[i] = readl(fep->hwp + fec_stats[i].offset);
1665 static void fec_enet_get_strings(struct net_device *netdev,
1666 u32 stringset, u8 *data)
1669 switch (stringset) {
1671 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1672 memcpy(data + i * ETH_GSTRING_LEN,
1673 fec_stats[i].name, ETH_GSTRING_LEN);
1678 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1682 return ARRAY_SIZE(fec_stats);
1687 #endif /* !defined(CONFIG_M5272) */
1689 static int fec_enet_nway_reset(struct net_device *dev)
1691 struct fec_enet_private *fep = netdev_priv(dev);
1692 struct phy_device *phydev = fep->phy_dev;
1697 return genphy_restart_aneg(phydev);
1700 static const struct ethtool_ops fec_enet_ethtool_ops = {
1701 #if !defined(CONFIG_M5272)
1702 .get_pauseparam = fec_enet_get_pauseparam,
1703 .set_pauseparam = fec_enet_set_pauseparam,
1705 .get_settings = fec_enet_get_settings,
1706 .set_settings = fec_enet_set_settings,
1707 .get_drvinfo = fec_enet_get_drvinfo,
1708 .get_link = ethtool_op_get_link,
1709 .get_ts_info = fec_enet_get_ts_info,
1710 .nway_reset = fec_enet_nway_reset,
1711 #ifndef CONFIG_M5272
1712 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1713 .get_strings = fec_enet_get_strings,
1714 .get_sset_count = fec_enet_get_sset_count,
1718 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1720 struct fec_enet_private *fep = netdev_priv(ndev);
1721 struct phy_device *phydev = fep->phy_dev;
1723 if (!netif_running(ndev))
1729 if (fep->bufdesc_ex) {
1730 if (cmd == SIOCSHWTSTAMP)
1731 return fec_ptp_set(ndev, rq);
1732 if (cmd == SIOCGHWTSTAMP)
1733 return fec_ptp_get(ndev, rq);
1736 return phy_mii_ioctl(phydev, rq, cmd);
1739 static void fec_enet_free_buffers(struct net_device *ndev)
1741 struct fec_enet_private *fep = netdev_priv(ndev);
1743 struct sk_buff *skb;
1744 struct bufdesc *bdp;
1746 bdp = fep->rx_bd_base;
1747 for (i = 0; i < fep->rx_ring_size; i++) {
1748 skb = fep->rx_skbuff[i];
1750 if (bdp->cbd_bufaddr)
1751 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1752 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1755 bdp = fec_enet_get_nextdesc(bdp, fep);
1758 bdp = fep->tx_bd_base;
1759 for (i = 0; i < fep->tx_ring_size; i++)
1760 kfree(fep->tx_bounce[i]);
1763 static int fec_enet_alloc_buffers(struct net_device *ndev)
1765 struct fec_enet_private *fep = netdev_priv(ndev);
1767 struct sk_buff *skb;
1768 struct bufdesc *bdp;
1770 bdp = fep->rx_bd_base;
1771 for (i = 0; i < fep->rx_ring_size; i++) {
1772 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1774 fec_enet_free_buffers(ndev);
1777 fep->rx_skbuff[i] = skb;
1779 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1780 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1781 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1782 fec_enet_free_buffers(ndev);
1783 if (net_ratelimit())
1784 netdev_err(ndev, "Rx DMA memory map failed\n");
1787 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1789 if (fep->bufdesc_ex) {
1790 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1791 ebdp->cbd_esc = BD_ENET_RX_INT;
1794 bdp = fec_enet_get_nextdesc(bdp, fep);
1797 /* Set the last buffer to wrap. */
1798 bdp = fec_enet_get_prevdesc(bdp, fep);
1799 bdp->cbd_sc |= BD_SC_WRAP;
1801 bdp = fep->tx_bd_base;
1802 for (i = 0; i < fep->tx_ring_size; i++) {
1803 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1806 bdp->cbd_bufaddr = 0;
1808 if (fep->bufdesc_ex) {
1809 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1810 ebdp->cbd_esc = BD_ENET_TX_INT;
1813 bdp = fec_enet_get_nextdesc(bdp, fep);
1816 /* Set the last buffer to wrap. */
1817 bdp = fec_enet_get_prevdesc(bdp, fep);
1818 bdp->cbd_sc |= BD_SC_WRAP;
1824 fec_enet_open(struct net_device *ndev)
1826 struct fec_enet_private *fep = netdev_priv(ndev);
1829 pinctrl_pm_select_default_state(&fep->pdev->dev);
1830 ret = fec_enet_clk_enable(ndev, true);
1834 /* I should reset the ring buffers here, but I don't yet know
1835 * a simple way to do that.
1838 ret = fec_enet_alloc_buffers(ndev);
1842 /* Probe and connect to PHY when open the interface */
1843 ret = fec_enet_mii_probe(ndev);
1845 fec_enet_free_buffers(ndev);
1849 napi_enable(&fep->napi);
1850 phy_start(fep->phy_dev);
1851 netif_start_queue(ndev);
1857 fec_enet_close(struct net_device *ndev)
1859 struct fec_enet_private *fep = netdev_priv(ndev);
1861 /* Don't know what to do yet. */
1862 napi_disable(&fep->napi);
1864 netif_stop_queue(ndev);
1868 phy_stop(fep->phy_dev);
1869 phy_disconnect(fep->phy_dev);
1872 fec_enet_clk_enable(ndev, false);
1873 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
1874 fec_enet_free_buffers(ndev);
1879 /* Set or clear the multicast filter for this adaptor.
1880 * Skeleton taken from sunlance driver.
1881 * The CPM Ethernet implementation allows Multicast as well as individual
1882 * MAC address filtering. Some of the drivers check to make sure it is
1883 * a group multicast address, and discard those that are not. I guess I
1884 * will do the same for now, but just remove the test if you want
1885 * individual filtering as well (do the upper net layers want or support
1886 * this kind of feature?).
1889 #define HASH_BITS 6 /* #bits in hash */
1890 #define CRC32_POLY 0xEDB88320
1892 static void set_multicast_list(struct net_device *ndev)
1894 struct fec_enet_private *fep = netdev_priv(ndev);
1895 struct netdev_hw_addr *ha;
1896 unsigned int i, bit, data, crc, tmp;
1899 if (ndev->flags & IFF_PROMISC) {
1900 tmp = readl(fep->hwp + FEC_R_CNTRL);
1902 writel(tmp, fep->hwp + FEC_R_CNTRL);
1906 tmp = readl(fep->hwp + FEC_R_CNTRL);
1908 writel(tmp, fep->hwp + FEC_R_CNTRL);
1910 if (ndev->flags & IFF_ALLMULTI) {
1911 /* Catch all multicast addresses, so set the
1914 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1915 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1920 /* Clear filter and add the addresses in hash register
1922 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1923 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1925 netdev_for_each_mc_addr(ha, ndev) {
1926 /* calculate crc32 value of mac address */
1929 for (i = 0; i < ndev->addr_len; i++) {
1931 for (bit = 0; bit < 8; bit++, data >>= 1) {
1933 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1937 /* only upper 6 bits (HASH_BITS) are used
1938 * which point to specific bit in he hash registers
1940 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1943 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1944 tmp |= 1 << (hash - 32);
1945 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1947 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1949 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1954 /* Set a MAC change in hardware. */
1956 fec_set_mac_address(struct net_device *ndev, void *p)
1958 struct fec_enet_private *fep = netdev_priv(ndev);
1959 struct sockaddr *addr = p;
1962 if (!is_valid_ether_addr(addr->sa_data))
1963 return -EADDRNOTAVAIL;
1964 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1967 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1968 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1969 fep->hwp + FEC_ADDR_LOW);
1970 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1971 fep->hwp + FEC_ADDR_HIGH);
1975 #ifdef CONFIG_NET_POLL_CONTROLLER
1977 * fec_poll_controller - FEC Poll controller function
1978 * @dev: The FEC network adapter
1980 * Polled functionality used by netconsole and others in non interrupt mode
1983 static void fec_poll_controller(struct net_device *dev)
1986 struct fec_enet_private *fep = netdev_priv(dev);
1988 for (i = 0; i < FEC_IRQ_NUM; i++) {
1989 if (fep->irq[i] > 0) {
1990 disable_irq(fep->irq[i]);
1991 fec_enet_interrupt(fep->irq[i], dev);
1992 enable_irq(fep->irq[i]);
1998 static int fec_set_features(struct net_device *netdev,
1999 netdev_features_t features)
2001 struct fec_enet_private *fep = netdev_priv(netdev);
2002 netdev_features_t changed = features ^ netdev->features;
2004 netdev->features = features;
2006 /* Receive checksum has been changed */
2007 if (changed & NETIF_F_RXCSUM) {
2008 if (features & NETIF_F_RXCSUM)
2009 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2011 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2013 if (netif_running(netdev)) {
2015 fec_restart(netdev, fep->phy_dev->duplex);
2016 netif_wake_queue(netdev);
2018 fec_restart(netdev, fep->phy_dev->duplex);
2025 static const struct net_device_ops fec_netdev_ops = {
2026 .ndo_open = fec_enet_open,
2027 .ndo_stop = fec_enet_close,
2028 .ndo_start_xmit = fec_enet_start_xmit,
2029 .ndo_set_rx_mode = set_multicast_list,
2030 .ndo_change_mtu = eth_change_mtu,
2031 .ndo_validate_addr = eth_validate_addr,
2032 .ndo_tx_timeout = fec_timeout,
2033 .ndo_set_mac_address = fec_set_mac_address,
2034 .ndo_do_ioctl = fec_enet_ioctl,
2035 #ifdef CONFIG_NET_POLL_CONTROLLER
2036 .ndo_poll_controller = fec_poll_controller,
2038 .ndo_set_features = fec_set_features,
2042 * XXX: We need to clean up on failure exits here.
2045 static int fec_enet_init(struct net_device *ndev)
2047 struct fec_enet_private *fep = netdev_priv(ndev);
2048 const struct platform_device_id *id_entry =
2049 platform_get_device_id(fep->pdev);
2050 struct bufdesc *cbd_base;
2052 /* Allocate memory for buffer descriptors. */
2053 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
2058 memset(cbd_base, 0, PAGE_SIZE);
2062 /* Get the Ethernet address */
2064 /* make sure MAC we just acquired is programmed into the hw */
2065 fec_set_mac_address(ndev, NULL);
2067 /* init the tx & rx ring size */
2068 fep->tx_ring_size = TX_RING_SIZE;
2069 fep->rx_ring_size = RX_RING_SIZE;
2071 /* Set receive and transmit descriptor base. */
2072 fep->rx_bd_base = cbd_base;
2073 if (fep->bufdesc_ex) {
2074 fep->tx_bd_base = (struct bufdesc *)
2075 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2076 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2078 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2079 fep->bufdesc_size = sizeof(struct bufdesc);
2082 /* The FEC Ethernet specific entries in the device structure */
2083 ndev->watchdog_timeo = TX_TIMEOUT;
2084 ndev->netdev_ops = &fec_netdev_ops;
2085 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2087 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2088 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2090 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2091 /* enable hw VLAN support */
2092 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2093 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2096 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2097 /* enable hw accelerator */
2098 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2100 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2102 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2105 fec_restart(ndev, 0);
2111 static void fec_reset_phy(struct platform_device *pdev)
2115 struct device_node *np = pdev->dev.of_node;
2120 of_property_read_u32(np, "phy-reset-duration", &msec);
2121 /* A sane reset duration should not be longer than 1s */
2125 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2126 if (!gpio_is_valid(phy_reset))
2129 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2130 GPIOF_OUT_INIT_LOW, "phy-reset");
2132 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2136 gpio_set_value(phy_reset, 1);
2138 #else /* CONFIG_OF */
2139 static void fec_reset_phy(struct platform_device *pdev)
2142 * In case of platform probe, the reset has been done
2146 #endif /* CONFIG_OF */
2149 fec_probe(struct platform_device *pdev)
2151 struct fec_enet_private *fep;
2152 struct fec_platform_data *pdata;
2153 struct net_device *ndev;
2154 int i, irq, ret = 0;
2156 const struct of_device_id *of_id;
2159 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2161 pdev->id_entry = of_id->data;
2163 /* Init network device */
2164 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2168 SET_NETDEV_DEV(ndev, &pdev->dev);
2170 /* setup board info structure */
2171 fep = netdev_priv(ndev);
2173 #if !defined(CONFIG_M5272)
2174 /* default enable pause frame auto negotiation */
2175 if (pdev->id_entry &&
2176 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2177 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2180 /* Select default pin state */
2181 pinctrl_pm_select_default_state(&pdev->dev);
2183 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2184 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2185 if (IS_ERR(fep->hwp)) {
2186 ret = PTR_ERR(fep->hwp);
2187 goto failed_ioremap;
2191 fep->dev_id = dev_id++;
2193 fep->bufdesc_ex = 0;
2195 platform_set_drvdata(pdev, ndev);
2197 ret = of_get_phy_mode(pdev->dev.of_node);
2199 pdata = dev_get_platdata(&pdev->dev);
2201 fep->phy_interface = pdata->phy;
2203 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2205 fep->phy_interface = ret;
2208 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2209 if (IS_ERR(fep->clk_ipg)) {
2210 ret = PTR_ERR(fep->clk_ipg);
2214 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2215 if (IS_ERR(fep->clk_ahb)) {
2216 ret = PTR_ERR(fep->clk_ahb);
2220 /* enet_out is optional, depends on board */
2221 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2222 if (IS_ERR(fep->clk_enet_out))
2223 fep->clk_enet_out = NULL;
2225 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2227 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2228 if (IS_ERR(fep->clk_ptp)) {
2229 fep->clk_ptp = NULL;
2230 fep->bufdesc_ex = 0;
2233 ret = fec_enet_clk_enable(ndev, true);
2237 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2238 if (!IS_ERR(fep->reg_phy)) {
2239 ret = regulator_enable(fep->reg_phy);
2242 "Failed to enable phy regulator: %d\n", ret);
2243 goto failed_regulator;
2246 fep->reg_phy = NULL;
2249 fec_reset_phy(pdev);
2251 if (fep->bufdesc_ex)
2254 ret = fec_enet_init(ndev);
2258 for (i = 0; i < FEC_IRQ_NUM; i++) {
2259 irq = platform_get_irq(pdev, i);
2266 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2267 0, pdev->name, ndev);
2272 ret = fec_enet_mii_init(pdev);
2274 goto failed_mii_init;
2276 /* Carrier starts down, phylib will bring it up */
2277 netif_carrier_off(ndev);
2278 fec_enet_clk_enable(ndev, false);
2279 pinctrl_pm_select_sleep_state(&pdev->dev);
2281 ret = register_netdev(ndev);
2283 goto failed_register;
2285 if (fep->bufdesc_ex && fep->ptp_clock)
2286 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2288 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2292 fec_enet_mii_remove(fep);
2297 regulator_disable(fep->reg_phy);
2299 fec_enet_clk_enable(ndev, false);
2308 fec_drv_remove(struct platform_device *pdev)
2310 struct net_device *ndev = platform_get_drvdata(pdev);
2311 struct fec_enet_private *fep = netdev_priv(ndev);
2313 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2314 unregister_netdev(ndev);
2315 fec_enet_mii_remove(fep);
2316 del_timer_sync(&fep->time_keep);
2318 regulator_disable(fep->reg_phy);
2320 ptp_clock_unregister(fep->ptp_clock);
2321 fec_enet_clk_enable(ndev, false);
2327 #ifdef CONFIG_PM_SLEEP
2329 fec_suspend(struct device *dev)
2331 struct net_device *ndev = dev_get_drvdata(dev);
2332 struct fec_enet_private *fep = netdev_priv(ndev);
2334 if (netif_running(ndev)) {
2336 netif_device_detach(ndev);
2338 fec_enet_clk_enable(ndev, false);
2339 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2342 regulator_disable(fep->reg_phy);
2348 fec_resume(struct device *dev)
2350 struct net_device *ndev = dev_get_drvdata(dev);
2351 struct fec_enet_private *fep = netdev_priv(ndev);
2355 ret = regulator_enable(fep->reg_phy);
2360 pinctrl_pm_select_default_state(&fep->pdev->dev);
2361 ret = fec_enet_clk_enable(ndev, true);
2365 if (netif_running(ndev)) {
2366 fec_restart(ndev, fep->full_duplex);
2367 netif_device_attach(ndev);
2374 regulator_disable(fep->reg_phy);
2377 #endif /* CONFIG_PM_SLEEP */
2379 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2381 static struct platform_driver fec_driver = {
2383 .name = DRIVER_NAME,
2384 .owner = THIS_MODULE,
2386 .of_match_table = fec_dt_ids,
2388 .id_table = fec_devtype,
2390 .remove = fec_drv_remove,
2393 module_platform_driver(fec_driver);
2395 MODULE_ALIAS("platform:"DRIVER_NAME);
2396 MODULE_LICENSE("GPL");