2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57 #include <linux/pinctrl/consumer.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
106 static struct platform_device_id fec_devtype[] = {
108 /* keep it for coldfire */
113 .driver_data = FEC_QUIRK_USE_GASKET,
119 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
126 .name = "mvf600-fec",
127 .driver_data = FEC_QUIRK_ENET_MAC,
132 MODULE_DEVICE_TABLE(platform, fec_devtype);
135 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
136 IMX27_FEC, /* runs on i.mx27/35/51 */
142 static const struct of_device_id fec_dt_ids[] = {
143 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
144 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
145 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
146 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
147 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
150 MODULE_DEVICE_TABLE(of, fec_dt_ids);
152 static unsigned char macaddr[ETH_ALEN];
153 module_param_array(macaddr, byte, NULL, 0);
154 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
156 #if defined(CONFIG_M5272)
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
161 #if defined(CONFIG_NETtel)
162 #define FEC_FLASHMAC 0xf0006006
163 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164 #define FEC_FLASHMAC 0xf0006000
165 #elif defined(CONFIG_CANCam)
166 #define FEC_FLASHMAC 0xf0020000
167 #elif defined (CONFIG_M5272C3)
168 #define FEC_FLASHMAC (0xffe04000 + 4)
169 #elif defined(CONFIG_MOD5272)
170 #define FEC_FLASHMAC 0xffc0406b
172 #define FEC_FLASHMAC 0
174 #endif /* CONFIG_M5272 */
176 /* Interrupt events/masks. */
177 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
178 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
179 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
180 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
181 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
182 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
183 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
184 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
185 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
186 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
189 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
191 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
193 #define PKT_MAXBUF_SIZE 1522
194 #define PKT_MINBUF_SIZE 64
195 #define PKT_MAXBLR_SIZE 1536
197 /* FEC receive acceleration */
198 #define FEC_RACC_IPDIS (1 << 1)
199 #define FEC_RACC_PRODIS (1 << 2)
200 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
203 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
204 * size bits. Other FEC hardware does not, so we need to take that into
205 * account when setting it.
207 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
208 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
209 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211 #define OPT_FRAME_SIZE 0
214 /* FEC MII MMFR bits definition */
215 #define FEC_MMFR_ST (1 << 30)
216 #define FEC_MMFR_OP_READ (2 << 28)
217 #define FEC_MMFR_OP_WRITE (1 << 28)
218 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
219 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
220 #define FEC_MMFR_TA (2 << 16)
221 #define FEC_MMFR_DATA(v) (v & 0xffff)
223 #define FEC_MII_TIMEOUT 30000 /* us */
225 /* Transmitter timeout */
226 #define TX_TIMEOUT (2 * HZ)
228 #define FEC_PAUSE_FLAG_AUTONEG 0x1
229 #define FEC_PAUSE_FLAG_ENABLE 0x2
234 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
236 struct bufdesc *new_bd = bdp + 1;
237 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
238 struct bufdesc_ex *ex_base;
239 struct bufdesc *base;
242 if (bdp >= fep->tx_bd_base) {
243 base = fep->tx_bd_base;
244 ring_size = fep->tx_ring_size;
245 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
247 base = fep->rx_bd_base;
248 ring_size = fep->rx_ring_size;
249 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
253 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
254 ex_base : ex_new_bd);
256 return (new_bd >= (base + ring_size)) ?
261 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
263 struct bufdesc *new_bd = bdp - 1;
264 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
265 struct bufdesc_ex *ex_base;
266 struct bufdesc *base;
269 if (bdp >= fep->tx_bd_base) {
270 base = fep->tx_bd_base;
271 ring_size = fep->tx_ring_size;
272 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
274 base = fep->rx_bd_base;
275 ring_size = fep->rx_ring_size;
276 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
280 return (struct bufdesc *)((ex_new_bd < ex_base) ?
281 (ex_new_bd + ring_size) : ex_new_bd);
283 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
286 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
287 struct fec_enet_private *fep)
289 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
292 static void *swap_buffer(void *bufaddr, int len)
295 unsigned int *buf = bufaddr;
297 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
298 *buf = cpu_to_be32(*buf);
304 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
306 /* Only run for packets requiring a checksum. */
307 if (skb->ip_summed != CHECKSUM_PARTIAL)
310 if (unlikely(skb_cow_head(skb, 0)))
313 ip_hdr(skb)->check = 0;
314 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
319 static int txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
321 struct fec_enet_private *fep = netdev_priv(ndev);
322 const struct platform_device_id *id_entry =
323 platform_get_device_id(fep->pdev);
324 struct bufdesc *bdp, *bdp_pre;
326 unsigned short status;
329 /* Fill in a Tx ring entry */
332 status = bdp->cbd_sc;
334 /* Protocol checksum off-load for TCP and UDP. */
335 if (fec_enet_clear_csum(skb, ndev)) {
336 dev_kfree_skb_any(skb);
340 /* Clear all of the status flags */
341 status &= ~BD_ENET_TX_STATS;
343 /* Set buffer length and buffer pointer */
345 bdp->cbd_datlen = skb->len;
347 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
349 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
350 memcpy(fep->tx_bounce[index], skb->data, skb->len);
351 bufaddr = fep->tx_bounce[index];
355 * Some design made an incorrect assumption on endian mode of
356 * the system that it's running on. As the result, driver has to
357 * swap every frame going to and coming from the controller.
359 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
360 swap_buffer(bufaddr, skb->len);
362 /* Save skb pointer */
363 fep->tx_skbuff[index] = skb;
365 /* Push the data cache so the CPM does not get stale memory
368 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
369 skb->len, DMA_TO_DEVICE);
370 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
371 bdp->cbd_bufaddr = 0;
372 fep->tx_skbuff[index] = NULL;
373 dev_kfree_skb_any(skb);
375 netdev_err(ndev, "Tx DMA memory map failed\n");
379 if (fep->bufdesc_ex) {
381 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
383 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
385 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
386 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
388 ebdp->cbd_esc = BD_ENET_TX_INT;
390 /* Enable protocol checksum flags
391 * We do not bother with the IP Checksum bits as they
392 * are done by the kernel
394 if (skb->ip_summed == CHECKSUM_PARTIAL)
395 ebdp->cbd_esc |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
399 /* Send it on its way. Tell FEC it's ready, interrupt when done,
400 * it's the last BD of the frame, and to put the CRC on the end.
402 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
403 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
404 bdp->cbd_sc = status;
406 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
407 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
408 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
409 fep->delay_work.trig_tx = true;
410 schedule_delayed_work(&(fep->delay_work.delay_work),
411 msecs_to_jiffies(1));
414 /* If this was the last BD in the ring, start at the beginning again. */
415 bdp = fec_enet_get_nextdesc(bdp, fep);
417 skb_tx_timestamp(skb);
421 /* Trigger transmission start */
422 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
428 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
430 struct fec_enet_private *fep = netdev_priv(ndev);
432 unsigned short status;
435 /* Fill in a Tx ring entry */
438 status = bdp->cbd_sc;
440 if (status & BD_ENET_TX_READY) {
441 /* Ooops. All transmit buffers are full. Bail out.
442 * This should not happen, since ndev->tbusy should be set.
444 netdev_err(ndev, "tx queue full!\n");
445 return NETDEV_TX_BUSY;
448 ret = txq_submit_skb(skb, ndev);
450 return NETDEV_TX_BUSY;
452 if (fep->cur_tx == fep->dirty_tx)
453 netif_stop_queue(ndev);
458 /* Init RX & TX buffer descriptors
460 static void fec_enet_bd_init(struct net_device *dev)
462 struct fec_enet_private *fep = netdev_priv(dev);
466 /* Initialize the receive buffer descriptors. */
467 bdp = fep->rx_bd_base;
468 for (i = 0; i < fep->rx_ring_size; i++) {
470 /* Initialize the BD for every fragment in the page. */
471 if (bdp->cbd_bufaddr)
472 bdp->cbd_sc = BD_ENET_RX_EMPTY;
475 bdp = fec_enet_get_nextdesc(bdp, fep);
478 /* Set the last buffer to wrap */
479 bdp = fec_enet_get_prevdesc(bdp, fep);
480 bdp->cbd_sc |= BD_SC_WRAP;
482 fep->cur_rx = fep->rx_bd_base;
484 /* ...and the same for transmit */
485 bdp = fep->tx_bd_base;
487 for (i = 0; i < fep->tx_ring_size; i++) {
489 /* Initialize the BD for every fragment in the page. */
491 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
492 dev_kfree_skb_any(fep->tx_skbuff[i]);
493 fep->tx_skbuff[i] = NULL;
495 bdp->cbd_bufaddr = 0;
496 bdp = fec_enet_get_nextdesc(bdp, fep);
499 /* Set the last buffer to wrap */
500 bdp = fec_enet_get_prevdesc(bdp, fep);
501 bdp->cbd_sc |= BD_SC_WRAP;
505 /* This function is called to start or restart the FEC during a link
506 * change. This only happens when switching between half and full
510 fec_restart(struct net_device *ndev, int duplex)
512 struct fec_enet_private *fep = netdev_priv(ndev);
513 const struct platform_device_id *id_entry =
514 platform_get_device_id(fep->pdev);
518 u32 rcntl = OPT_FRAME_SIZE | 0x04;
519 u32 ecntl = 0x2; /* ETHEREN */
521 if (netif_running(ndev)) {
522 netif_device_detach(ndev);
523 napi_disable(&fep->napi);
524 netif_stop_queue(ndev);
525 netif_tx_lock_bh(ndev);
528 /* Whack a reset. We should wait for this. */
529 writel(1, fep->hwp + FEC_ECNTRL);
533 * enet-mac reset will reset mac address registers too,
534 * so need to reconfigure it.
536 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
537 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
538 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
539 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
542 /* Clear any outstanding interrupt. */
543 writel(0xffc00000, fep->hwp + FEC_IEVENT);
545 /* Set maximum receive buffer size. */
546 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
548 fec_enet_bd_init(ndev);
550 /* Set receive and transmit descriptor base. */
551 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
553 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
554 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
556 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
557 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
560 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
561 if (fep->tx_skbuff[i]) {
562 dev_kfree_skb_any(fep->tx_skbuff[i]);
563 fep->tx_skbuff[i] = NULL;
567 /* Enable MII mode */
570 writel(0x04, fep->hwp + FEC_X_CNTRL);
574 writel(0x0, fep->hwp + FEC_X_CNTRL);
577 fep->full_duplex = duplex;
580 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
582 #if !defined(CONFIG_M5272)
583 /* set RX checksum */
584 val = readl(fep->hwp + FEC_RACC);
585 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
586 val |= FEC_RACC_OPTIONS;
588 val &= ~FEC_RACC_OPTIONS;
589 writel(val, fep->hwp + FEC_RACC);
593 * The phy interface and speed need to get configured
594 * differently on enet-mac.
596 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
597 /* Enable flow control and length check */
598 rcntl |= 0x40000000 | 0x00000020;
600 /* RGMII, RMII or MII */
601 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
603 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
608 /* 1G, 100M or 10M */
610 if (fep->phy_dev->speed == SPEED_1000)
612 else if (fep->phy_dev->speed == SPEED_100)
618 #ifdef FEC_MIIGSK_ENR
619 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
621 /* disable the gasket and wait */
622 writel(0, fep->hwp + FEC_MIIGSK_ENR);
623 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
627 * configure the gasket:
628 * RMII, 50 MHz, no loopback, no echo
629 * MII, 25 MHz, no loopback, no echo
631 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
632 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
633 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
634 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
635 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
637 /* re-enable the gasket */
638 writel(2, fep->hwp + FEC_MIIGSK_ENR);
643 #if !defined(CONFIG_M5272)
644 /* enable pause frame*/
645 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
646 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
647 fep->phy_dev && fep->phy_dev->pause)) {
648 rcntl |= FEC_ENET_FCE;
650 /* set FIFO threshold parameter to reduce overrun */
651 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
652 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
653 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
654 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
657 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
659 rcntl &= ~FEC_ENET_FCE;
661 #endif /* !defined(CONFIG_M5272) */
663 writel(rcntl, fep->hwp + FEC_R_CNTRL);
665 /* Setup multicast filter. */
666 set_multicast_list(ndev);
668 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
669 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
672 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
673 /* enable ENET endian swap */
675 /* enable ENET store and forward mode */
676 writel(1 << 8, fep->hwp + FEC_X_WMRK);
683 /* Enable the MIB statistic event counters */
684 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
687 /* And last, enable the transmit and receive processing */
688 writel(ecntl, fep->hwp + FEC_ECNTRL);
689 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
692 fec_ptp_start_cyclecounter(ndev);
694 /* Enable interrupts we wish to service */
695 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
697 if (netif_running(ndev)) {
698 netif_tx_unlock_bh(ndev);
699 netif_wake_queue(ndev);
700 napi_enable(&fep->napi);
701 netif_device_attach(ndev);
706 fec_stop(struct net_device *ndev)
708 struct fec_enet_private *fep = netdev_priv(ndev);
709 const struct platform_device_id *id_entry =
710 platform_get_device_id(fep->pdev);
711 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
713 /* We cannot expect a graceful transmit stop without link !!! */
715 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
717 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
718 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
721 /* Whack a reset. We should wait for this. */
722 writel(1, fep->hwp + FEC_ECNTRL);
724 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
725 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
727 /* We have to keep ENET enabled to have MII interrupt stay working */
728 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
729 writel(2, fep->hwp + FEC_ECNTRL);
730 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
736 fec_timeout(struct net_device *ndev)
738 struct fec_enet_private *fep = netdev_priv(ndev);
740 ndev->stats.tx_errors++;
742 fep->delay_work.timeout = true;
743 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
746 static void fec_enet_work(struct work_struct *work)
748 struct fec_enet_private *fep =
750 struct fec_enet_private,
751 delay_work.delay_work.work);
753 if (fep->delay_work.timeout) {
754 fep->delay_work.timeout = false;
755 fec_restart(fep->netdev, fep->full_duplex);
756 netif_wake_queue(fep->netdev);
759 if (fep->delay_work.trig_tx) {
760 fep->delay_work.trig_tx = false;
761 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
766 fec_enet_tx(struct net_device *ndev)
768 struct fec_enet_private *fep;
770 unsigned short status;
774 fep = netdev_priv(ndev);
777 /* get next bdp of dirty_tx */
778 bdp = fec_enet_get_nextdesc(bdp, fep);
780 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
782 /* current queue is empty */
783 if (bdp == fep->cur_tx)
786 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
788 skb = fep->tx_skbuff[index];
789 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
791 bdp->cbd_bufaddr = 0;
793 /* Check for errors. */
794 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
795 BD_ENET_TX_RL | BD_ENET_TX_UN |
797 ndev->stats.tx_errors++;
798 if (status & BD_ENET_TX_HB) /* No heartbeat */
799 ndev->stats.tx_heartbeat_errors++;
800 if (status & BD_ENET_TX_LC) /* Late collision */
801 ndev->stats.tx_window_errors++;
802 if (status & BD_ENET_TX_RL) /* Retrans limit */
803 ndev->stats.tx_aborted_errors++;
804 if (status & BD_ENET_TX_UN) /* Underrun */
805 ndev->stats.tx_fifo_errors++;
806 if (status & BD_ENET_TX_CSL) /* Carrier lost */
807 ndev->stats.tx_carrier_errors++;
809 ndev->stats.tx_packets++;
810 ndev->stats.tx_bytes += bdp->cbd_datlen;
813 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
815 struct skb_shared_hwtstamps shhwtstamps;
817 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
819 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
820 spin_lock_irqsave(&fep->tmreg_lock, flags);
821 shhwtstamps.hwtstamp = ns_to_ktime(
822 timecounter_cyc2time(&fep->tc, ebdp->ts));
823 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
824 skb_tstamp_tx(skb, &shhwtstamps);
827 if (status & BD_ENET_TX_READY)
828 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
830 /* Deferred means some collisions occurred during transmit,
831 * but we eventually sent the packet OK.
833 if (status & BD_ENET_TX_DEF)
834 ndev->stats.collisions++;
836 /* Free the sk buffer associated with this last transmit */
837 dev_kfree_skb_any(skb);
838 fep->tx_skbuff[index] = NULL;
842 /* Update pointer to next buffer descriptor to be transmitted */
843 bdp = fec_enet_get_nextdesc(bdp, fep);
845 /* Since we have freed up a buffer, the ring is no longer full
847 if (fep->dirty_tx != fep->cur_tx) {
848 if (netif_queue_stopped(ndev))
849 netif_wake_queue(ndev);
856 /* During a receive, the cur_rx points to the current incoming buffer.
857 * When we update through the ring, if the next incoming buffer has
858 * not been given to the system, we just set the empty indicator,
859 * effectively tossing the packet.
862 fec_enet_rx(struct net_device *ndev, int budget)
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 const struct platform_device_id *id_entry =
866 platform_get_device_id(fep->pdev);
868 unsigned short status;
872 int pkt_received = 0;
873 struct bufdesc_ex *ebdp = NULL;
874 bool vlan_packet_rcvd = false;
882 /* First, grab all of the stats for the incoming packet.
883 * These get messed up if we get called due to a busy condition.
887 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
889 if (pkt_received >= budget)
893 /* Since we have allocated space to hold a complete frame,
894 * the last indicator should be set.
896 if ((status & BD_ENET_RX_LAST) == 0)
897 netdev_err(ndev, "rcv is not +last\n");
900 goto rx_processing_done;
902 /* Check for errors. */
903 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
904 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
905 ndev->stats.rx_errors++;
906 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
907 /* Frame too long or too short. */
908 ndev->stats.rx_length_errors++;
910 if (status & BD_ENET_RX_NO) /* Frame alignment */
911 ndev->stats.rx_frame_errors++;
912 if (status & BD_ENET_RX_CR) /* CRC Error */
913 ndev->stats.rx_crc_errors++;
914 if (status & BD_ENET_RX_OV) /* FIFO overrun */
915 ndev->stats.rx_fifo_errors++;
918 /* Report late collisions as a frame error.
919 * On this error, the BD is closed, but we don't know what we
920 * have in the buffer. So, just drop this frame on the floor.
922 if (status & BD_ENET_RX_CL) {
923 ndev->stats.rx_errors++;
924 ndev->stats.rx_frame_errors++;
925 goto rx_processing_done;
928 /* Process the incoming frame. */
929 ndev->stats.rx_packets++;
930 pkt_len = bdp->cbd_datlen;
931 ndev->stats.rx_bytes += pkt_len;
933 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
934 data = fep->rx_skbuff[index]->data;
935 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
936 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
938 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
939 swap_buffer(data, pkt_len);
941 /* Extract the enhanced buffer descriptor */
944 ebdp = (struct bufdesc_ex *)bdp;
946 /* If this is a VLAN packet remove the VLAN Tag */
947 vlan_packet_rcvd = false;
948 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
949 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
950 /* Push and remove the vlan tag */
951 struct vlan_hdr *vlan_header =
952 (struct vlan_hdr *) (data + ETH_HLEN);
953 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
954 pkt_len -= VLAN_HLEN;
956 vlan_packet_rcvd = true;
959 /* This does 16 byte alignment, exactly what we need.
960 * The packet length includes FCS, but we don't want to
961 * include that when passing upstream as it messes up
962 * bridging applications.
964 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
966 if (unlikely(!skb)) {
967 ndev->stats.rx_dropped++;
969 int payload_offset = (2 * ETH_ALEN);
970 skb_reserve(skb, NET_IP_ALIGN);
971 skb_put(skb, pkt_len - 4); /* Make room */
973 /* Extract the frame data without the VLAN header. */
974 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
975 if (vlan_packet_rcvd)
976 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
977 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
978 data + payload_offset,
979 pkt_len - 4 - (2 * ETH_ALEN));
981 skb->protocol = eth_type_trans(skb, ndev);
983 /* Get receive timestamp from the skb */
984 if (fep->hwts_rx_en && fep->bufdesc_ex) {
985 struct skb_shared_hwtstamps *shhwtstamps =
989 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
991 spin_lock_irqsave(&fep->tmreg_lock, flags);
992 shhwtstamps->hwtstamp = ns_to_ktime(
993 timecounter_cyc2time(&fep->tc, ebdp->ts));
994 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
997 if (fep->bufdesc_ex &&
998 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
999 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1000 /* don't check it */
1001 skb->ip_summed = CHECKSUM_UNNECESSARY;
1003 skb_checksum_none_assert(skb);
1007 /* Handle received VLAN packets */
1008 if (vlan_packet_rcvd)
1009 __vlan_hwaccel_put_tag(skb,
1013 napi_gro_receive(&fep->napi, skb);
1016 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1017 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1019 /* Clear the status flags for this buffer */
1020 status &= ~BD_ENET_RX_STATS;
1022 /* Mark the buffer empty */
1023 status |= BD_ENET_RX_EMPTY;
1024 bdp->cbd_sc = status;
1026 if (fep->bufdesc_ex) {
1027 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1029 ebdp->cbd_esc = BD_ENET_RX_INT;
1034 /* Update BD pointer to next entry */
1035 bdp = fec_enet_get_nextdesc(bdp, fep);
1037 /* Doing this here will keep the FEC running while we process
1038 * incoming frames. On a heavily loaded network, we should be
1039 * able to keep up at the expense of system resources.
1041 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1045 return pkt_received;
1049 fec_enet_interrupt(int irq, void *dev_id)
1051 struct net_device *ndev = dev_id;
1052 struct fec_enet_private *fep = netdev_priv(ndev);
1054 irqreturn_t ret = IRQ_NONE;
1057 int_events = readl(fep->hwp + FEC_IEVENT);
1058 writel(int_events, fep->hwp + FEC_IEVENT);
1060 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1063 /* Disable the RX interrupt */
1064 if (napi_schedule_prep(&fep->napi)) {
1065 writel(FEC_RX_DISABLED_IMASK,
1066 fep->hwp + FEC_IMASK);
1067 __napi_schedule(&fep->napi);
1071 if (int_events & FEC_ENET_MII) {
1073 complete(&fep->mdio_done);
1075 } while (int_events);
1080 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1082 struct net_device *ndev = napi->dev;
1083 int pkts = fec_enet_rx(ndev, budget);
1084 struct fec_enet_private *fep = netdev_priv(ndev);
1088 if (pkts < budget) {
1089 napi_complete(napi);
1090 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1095 /* ------------------------------------------------------------------------- */
1096 static void fec_get_mac(struct net_device *ndev)
1098 struct fec_enet_private *fep = netdev_priv(ndev);
1099 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1100 unsigned char *iap, tmpaddr[ETH_ALEN];
1103 * try to get mac address in following order:
1105 * 1) module parameter via kernel command line in form
1106 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1111 * 2) from device tree data
1113 if (!is_valid_ether_addr(iap)) {
1114 struct device_node *np = fep->pdev->dev.of_node;
1116 const char *mac = of_get_mac_address(np);
1118 iap = (unsigned char *) mac;
1123 * 3) from flash or fuse (via platform data)
1125 if (!is_valid_ether_addr(iap)) {
1128 iap = (unsigned char *)FEC_FLASHMAC;
1131 iap = (unsigned char *)&pdata->mac;
1136 * 4) FEC mac registers set by bootloader
1138 if (!is_valid_ether_addr(iap)) {
1139 *((__be32 *) &tmpaddr[0]) =
1140 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1141 *((__be16 *) &tmpaddr[4]) =
1142 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1147 * 5) random mac address
1149 if (!is_valid_ether_addr(iap)) {
1150 /* Report it and use a random ethernet address instead */
1151 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1152 eth_hw_addr_random(ndev);
1153 netdev_info(ndev, "Using random MAC address: %pM\n",
1158 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1160 /* Adjust MAC if using macaddr */
1162 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1165 /* ------------------------------------------------------------------------- */
1170 static void fec_enet_adjust_link(struct net_device *ndev)
1172 struct fec_enet_private *fep = netdev_priv(ndev);
1173 struct phy_device *phy_dev = fep->phy_dev;
1174 int status_change = 0;
1176 /* Prevent a state halted on mii error */
1177 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1178 phy_dev->state = PHY_RESUMING;
1182 if (phy_dev->link) {
1184 fep->link = phy_dev->link;
1188 if (fep->full_duplex != phy_dev->duplex)
1191 if (phy_dev->speed != fep->speed) {
1192 fep->speed = phy_dev->speed;
1196 /* if any of the above changed restart the FEC */
1198 fec_restart(ndev, phy_dev->duplex);
1202 fep->link = phy_dev->link;
1208 phy_print_status(phy_dev);
1211 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1213 struct fec_enet_private *fep = bus->priv;
1214 unsigned long time_left;
1216 fep->mii_timeout = 0;
1217 init_completion(&fep->mdio_done);
1219 /* start a read op */
1220 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1221 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1222 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1224 /* wait for end of transfer */
1225 time_left = wait_for_completion_timeout(&fep->mdio_done,
1226 usecs_to_jiffies(FEC_MII_TIMEOUT));
1227 if (time_left == 0) {
1228 fep->mii_timeout = 1;
1229 netdev_err(fep->netdev, "MDIO read timeout\n");
1234 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1237 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1240 struct fec_enet_private *fep = bus->priv;
1241 unsigned long time_left;
1243 fep->mii_timeout = 0;
1244 init_completion(&fep->mdio_done);
1246 /* start a write op */
1247 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1248 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1249 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1250 fep->hwp + FEC_MII_DATA);
1252 /* wait for end of transfer */
1253 time_left = wait_for_completion_timeout(&fep->mdio_done,
1254 usecs_to_jiffies(FEC_MII_TIMEOUT));
1255 if (time_left == 0) {
1256 fep->mii_timeout = 1;
1257 netdev_err(fep->netdev, "MDIO write timeout\n");
1264 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1266 struct fec_enet_private *fep = netdev_priv(ndev);
1270 ret = clk_prepare_enable(fep->clk_ahb);
1273 ret = clk_prepare_enable(fep->clk_ipg);
1275 goto failed_clk_ipg;
1276 if (fep->clk_enet_out) {
1277 ret = clk_prepare_enable(fep->clk_enet_out);
1279 goto failed_clk_enet_out;
1282 ret = clk_prepare_enable(fep->clk_ptp);
1284 goto failed_clk_ptp;
1287 clk_disable_unprepare(fep->clk_ahb);
1288 clk_disable_unprepare(fep->clk_ipg);
1289 if (fep->clk_enet_out)
1290 clk_disable_unprepare(fep->clk_enet_out);
1292 clk_disable_unprepare(fep->clk_ptp);
1297 if (fep->clk_enet_out)
1298 clk_disable_unprepare(fep->clk_enet_out);
1299 failed_clk_enet_out:
1300 clk_disable_unprepare(fep->clk_ipg);
1302 clk_disable_unprepare(fep->clk_ahb);
1307 static int fec_enet_mii_probe(struct net_device *ndev)
1309 struct fec_enet_private *fep = netdev_priv(ndev);
1310 const struct platform_device_id *id_entry =
1311 platform_get_device_id(fep->pdev);
1312 struct phy_device *phy_dev = NULL;
1313 char mdio_bus_id[MII_BUS_ID_SIZE];
1314 char phy_name[MII_BUS_ID_SIZE + 3];
1316 int dev_id = fep->dev_id;
1318 fep->phy_dev = NULL;
1320 /* check for attached phy */
1321 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1322 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1324 if (fep->mii_bus->phy_map[phy_id] == NULL)
1326 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1330 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1334 if (phy_id >= PHY_MAX_ADDR) {
1335 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1336 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1340 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1341 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1342 fep->phy_interface);
1343 if (IS_ERR(phy_dev)) {
1344 netdev_err(ndev, "could not attach to PHY\n");
1345 return PTR_ERR(phy_dev);
1348 /* mask with MAC supported features */
1349 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1350 phy_dev->supported &= PHY_GBIT_FEATURES;
1351 #if !defined(CONFIG_M5272)
1352 phy_dev->supported |= SUPPORTED_Pause;
1356 phy_dev->supported &= PHY_BASIC_FEATURES;
1358 phy_dev->advertising = phy_dev->supported;
1360 fep->phy_dev = phy_dev;
1362 fep->full_duplex = 0;
1364 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1365 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1371 static int fec_enet_mii_init(struct platform_device *pdev)
1373 static struct mii_bus *fec0_mii_bus;
1374 struct net_device *ndev = platform_get_drvdata(pdev);
1375 struct fec_enet_private *fep = netdev_priv(ndev);
1376 const struct platform_device_id *id_entry =
1377 platform_get_device_id(fep->pdev);
1378 int err = -ENXIO, i;
1381 * The dual fec interfaces are not equivalent with enet-mac.
1382 * Here are the differences:
1384 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1385 * - fec0 acts as the 1588 time master while fec1 is slave
1386 * - external phys can only be configured by fec0
1388 * That is to say fec1 can not work independently. It only works
1389 * when fec0 is working. The reason behind this design is that the
1390 * second interface is added primarily for Switch mode.
1392 * Because of the last point above, both phys are attached on fec0
1393 * mdio interface in board design, and need to be configured by
1396 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1397 /* fec1 uses fec0 mii_bus */
1398 if (mii_cnt && fec0_mii_bus) {
1399 fep->mii_bus = fec0_mii_bus;
1406 fep->mii_timeout = 0;
1409 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1411 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1412 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1413 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1416 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1417 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1419 fep->phy_speed <<= 1;
1420 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1422 fep->mii_bus = mdiobus_alloc();
1423 if (fep->mii_bus == NULL) {
1428 fep->mii_bus->name = "fec_enet_mii_bus";
1429 fep->mii_bus->read = fec_enet_mdio_read;
1430 fep->mii_bus->write = fec_enet_mdio_write;
1431 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1432 pdev->name, fep->dev_id + 1);
1433 fep->mii_bus->priv = fep;
1434 fep->mii_bus->parent = &pdev->dev;
1436 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1437 if (!fep->mii_bus->irq) {
1439 goto err_out_free_mdiobus;
1442 for (i = 0; i < PHY_MAX_ADDR; i++)
1443 fep->mii_bus->irq[i] = PHY_POLL;
1445 if (mdiobus_register(fep->mii_bus))
1446 goto err_out_free_mdio_irq;
1450 /* save fec0 mii_bus */
1451 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1452 fec0_mii_bus = fep->mii_bus;
1456 err_out_free_mdio_irq:
1457 kfree(fep->mii_bus->irq);
1458 err_out_free_mdiobus:
1459 mdiobus_free(fep->mii_bus);
1464 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1466 if (--mii_cnt == 0) {
1467 mdiobus_unregister(fep->mii_bus);
1468 kfree(fep->mii_bus->irq);
1469 mdiobus_free(fep->mii_bus);
1473 static int fec_enet_get_settings(struct net_device *ndev,
1474 struct ethtool_cmd *cmd)
1476 struct fec_enet_private *fep = netdev_priv(ndev);
1477 struct phy_device *phydev = fep->phy_dev;
1482 return phy_ethtool_gset(phydev, cmd);
1485 static int fec_enet_set_settings(struct net_device *ndev,
1486 struct ethtool_cmd *cmd)
1488 struct fec_enet_private *fep = netdev_priv(ndev);
1489 struct phy_device *phydev = fep->phy_dev;
1494 return phy_ethtool_sset(phydev, cmd);
1497 static void fec_enet_get_drvinfo(struct net_device *ndev,
1498 struct ethtool_drvinfo *info)
1500 struct fec_enet_private *fep = netdev_priv(ndev);
1502 strlcpy(info->driver, fep->pdev->dev.driver->name,
1503 sizeof(info->driver));
1504 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1505 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1508 static int fec_enet_get_ts_info(struct net_device *ndev,
1509 struct ethtool_ts_info *info)
1511 struct fec_enet_private *fep = netdev_priv(ndev);
1513 if (fep->bufdesc_ex) {
1515 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1516 SOF_TIMESTAMPING_RX_SOFTWARE |
1517 SOF_TIMESTAMPING_SOFTWARE |
1518 SOF_TIMESTAMPING_TX_HARDWARE |
1519 SOF_TIMESTAMPING_RX_HARDWARE |
1520 SOF_TIMESTAMPING_RAW_HARDWARE;
1522 info->phc_index = ptp_clock_index(fep->ptp_clock);
1524 info->phc_index = -1;
1526 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1527 (1 << HWTSTAMP_TX_ON);
1529 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1530 (1 << HWTSTAMP_FILTER_ALL);
1533 return ethtool_op_get_ts_info(ndev, info);
1537 #if !defined(CONFIG_M5272)
1539 static void fec_enet_get_pauseparam(struct net_device *ndev,
1540 struct ethtool_pauseparam *pause)
1542 struct fec_enet_private *fep = netdev_priv(ndev);
1544 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1545 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1546 pause->rx_pause = pause->tx_pause;
1549 static int fec_enet_set_pauseparam(struct net_device *ndev,
1550 struct ethtool_pauseparam *pause)
1552 struct fec_enet_private *fep = netdev_priv(ndev);
1554 if (pause->tx_pause != pause->rx_pause) {
1556 "hardware only support enable/disable both tx and rx");
1560 fep->pause_flag = 0;
1562 /* tx pause must be same as rx pause */
1563 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1564 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1566 if (pause->rx_pause || pause->autoneg) {
1567 fep->phy_dev->supported |= ADVERTISED_Pause;
1568 fep->phy_dev->advertising |= ADVERTISED_Pause;
1570 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1571 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1574 if (pause->autoneg) {
1575 if (netif_running(ndev))
1577 phy_start_aneg(fep->phy_dev);
1579 if (netif_running(ndev))
1580 fec_restart(ndev, 0);
1585 static const struct fec_stat {
1586 char name[ETH_GSTRING_LEN];
1590 { "tx_dropped", RMON_T_DROP },
1591 { "tx_packets", RMON_T_PACKETS },
1592 { "tx_broadcast", RMON_T_BC_PKT },
1593 { "tx_multicast", RMON_T_MC_PKT },
1594 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1595 { "tx_undersize", RMON_T_UNDERSIZE },
1596 { "tx_oversize", RMON_T_OVERSIZE },
1597 { "tx_fragment", RMON_T_FRAG },
1598 { "tx_jabber", RMON_T_JAB },
1599 { "tx_collision", RMON_T_COL },
1600 { "tx_64byte", RMON_T_P64 },
1601 { "tx_65to127byte", RMON_T_P65TO127 },
1602 { "tx_128to255byte", RMON_T_P128TO255 },
1603 { "tx_256to511byte", RMON_T_P256TO511 },
1604 { "tx_512to1023byte", RMON_T_P512TO1023 },
1605 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1606 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1607 { "tx_octets", RMON_T_OCTETS },
1610 { "IEEE_tx_drop", IEEE_T_DROP },
1611 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1612 { "IEEE_tx_1col", IEEE_T_1COL },
1613 { "IEEE_tx_mcol", IEEE_T_MCOL },
1614 { "IEEE_tx_def", IEEE_T_DEF },
1615 { "IEEE_tx_lcol", IEEE_T_LCOL },
1616 { "IEEE_tx_excol", IEEE_T_EXCOL },
1617 { "IEEE_tx_macerr", IEEE_T_MACERR },
1618 { "IEEE_tx_cserr", IEEE_T_CSERR },
1619 { "IEEE_tx_sqe", IEEE_T_SQE },
1620 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1621 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1624 { "rx_packets", RMON_R_PACKETS },
1625 { "rx_broadcast", RMON_R_BC_PKT },
1626 { "rx_multicast", RMON_R_MC_PKT },
1627 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1628 { "rx_undersize", RMON_R_UNDERSIZE },
1629 { "rx_oversize", RMON_R_OVERSIZE },
1630 { "rx_fragment", RMON_R_FRAG },
1631 { "rx_jabber", RMON_R_JAB },
1632 { "rx_64byte", RMON_R_P64 },
1633 { "rx_65to127byte", RMON_R_P65TO127 },
1634 { "rx_128to255byte", RMON_R_P128TO255 },
1635 { "rx_256to511byte", RMON_R_P256TO511 },
1636 { "rx_512to1023byte", RMON_R_P512TO1023 },
1637 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1638 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1639 { "rx_octets", RMON_R_OCTETS },
1642 { "IEEE_rx_drop", IEEE_R_DROP },
1643 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1644 { "IEEE_rx_crc", IEEE_R_CRC },
1645 { "IEEE_rx_align", IEEE_R_ALIGN },
1646 { "IEEE_rx_macerr", IEEE_R_MACERR },
1647 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1648 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1651 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1652 struct ethtool_stats *stats, u64 *data)
1654 struct fec_enet_private *fep = netdev_priv(dev);
1657 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1658 data[i] = readl(fep->hwp + fec_stats[i].offset);
1661 static void fec_enet_get_strings(struct net_device *netdev,
1662 u32 stringset, u8 *data)
1665 switch (stringset) {
1667 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1668 memcpy(data + i * ETH_GSTRING_LEN,
1669 fec_stats[i].name, ETH_GSTRING_LEN);
1674 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1678 return ARRAY_SIZE(fec_stats);
1683 #endif /* !defined(CONFIG_M5272) */
1685 static int fec_enet_nway_reset(struct net_device *dev)
1687 struct fec_enet_private *fep = netdev_priv(dev);
1688 struct phy_device *phydev = fep->phy_dev;
1693 return genphy_restart_aneg(phydev);
1696 static const struct ethtool_ops fec_enet_ethtool_ops = {
1697 #if !defined(CONFIG_M5272)
1698 .get_pauseparam = fec_enet_get_pauseparam,
1699 .set_pauseparam = fec_enet_set_pauseparam,
1701 .get_settings = fec_enet_get_settings,
1702 .set_settings = fec_enet_set_settings,
1703 .get_drvinfo = fec_enet_get_drvinfo,
1704 .get_link = ethtool_op_get_link,
1705 .get_ts_info = fec_enet_get_ts_info,
1706 .nway_reset = fec_enet_nway_reset,
1707 #ifndef CONFIG_M5272
1708 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1709 .get_strings = fec_enet_get_strings,
1710 .get_sset_count = fec_enet_get_sset_count,
1714 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1716 struct fec_enet_private *fep = netdev_priv(ndev);
1717 struct phy_device *phydev = fep->phy_dev;
1719 if (!netif_running(ndev))
1725 if (fep->bufdesc_ex) {
1726 if (cmd == SIOCSHWTSTAMP)
1727 return fec_ptp_set(ndev, rq);
1728 if (cmd == SIOCGHWTSTAMP)
1729 return fec_ptp_get(ndev, rq);
1732 return phy_mii_ioctl(phydev, rq, cmd);
1735 static void fec_enet_free_buffers(struct net_device *ndev)
1737 struct fec_enet_private *fep = netdev_priv(ndev);
1739 struct sk_buff *skb;
1740 struct bufdesc *bdp;
1742 bdp = fep->rx_bd_base;
1743 for (i = 0; i < fep->rx_ring_size; i++) {
1744 skb = fep->rx_skbuff[i];
1746 if (bdp->cbd_bufaddr)
1747 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1748 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1751 bdp = fec_enet_get_nextdesc(bdp, fep);
1754 bdp = fep->tx_bd_base;
1755 for (i = 0; i < fep->tx_ring_size; i++)
1756 kfree(fep->tx_bounce[i]);
1759 static int fec_enet_alloc_buffers(struct net_device *ndev)
1761 struct fec_enet_private *fep = netdev_priv(ndev);
1763 struct sk_buff *skb;
1764 struct bufdesc *bdp;
1766 bdp = fep->rx_bd_base;
1767 for (i = 0; i < fep->rx_ring_size; i++) {
1768 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1770 fec_enet_free_buffers(ndev);
1773 fep->rx_skbuff[i] = skb;
1775 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1776 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1777 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1778 fec_enet_free_buffers(ndev);
1779 if (net_ratelimit())
1780 netdev_err(ndev, "Rx DMA memory map failed\n");
1783 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1785 if (fep->bufdesc_ex) {
1786 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1787 ebdp->cbd_esc = BD_ENET_RX_INT;
1790 bdp = fec_enet_get_nextdesc(bdp, fep);
1793 /* Set the last buffer to wrap. */
1794 bdp = fec_enet_get_prevdesc(bdp, fep);
1795 bdp->cbd_sc |= BD_SC_WRAP;
1797 bdp = fep->tx_bd_base;
1798 for (i = 0; i < fep->tx_ring_size; i++) {
1799 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1802 bdp->cbd_bufaddr = 0;
1804 if (fep->bufdesc_ex) {
1805 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1806 ebdp->cbd_esc = BD_ENET_TX_INT;
1809 bdp = fec_enet_get_nextdesc(bdp, fep);
1812 /* Set the last buffer to wrap. */
1813 bdp = fec_enet_get_prevdesc(bdp, fep);
1814 bdp->cbd_sc |= BD_SC_WRAP;
1820 fec_enet_open(struct net_device *ndev)
1822 struct fec_enet_private *fep = netdev_priv(ndev);
1825 pinctrl_pm_select_default_state(&fep->pdev->dev);
1826 ret = fec_enet_clk_enable(ndev, true);
1830 /* I should reset the ring buffers here, but I don't yet know
1831 * a simple way to do that.
1834 ret = fec_enet_alloc_buffers(ndev);
1838 /* Probe and connect to PHY when open the interface */
1839 ret = fec_enet_mii_probe(ndev);
1841 fec_enet_free_buffers(ndev);
1845 napi_enable(&fep->napi);
1846 phy_start(fep->phy_dev);
1847 netif_start_queue(ndev);
1853 fec_enet_close(struct net_device *ndev)
1855 struct fec_enet_private *fep = netdev_priv(ndev);
1857 /* Don't know what to do yet. */
1858 napi_disable(&fep->napi);
1860 netif_stop_queue(ndev);
1864 phy_stop(fep->phy_dev);
1865 phy_disconnect(fep->phy_dev);
1868 fec_enet_clk_enable(ndev, false);
1869 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
1870 fec_enet_free_buffers(ndev);
1875 /* Set or clear the multicast filter for this adaptor.
1876 * Skeleton taken from sunlance driver.
1877 * The CPM Ethernet implementation allows Multicast as well as individual
1878 * MAC address filtering. Some of the drivers check to make sure it is
1879 * a group multicast address, and discard those that are not. I guess I
1880 * will do the same for now, but just remove the test if you want
1881 * individual filtering as well (do the upper net layers want or support
1882 * this kind of feature?).
1885 #define HASH_BITS 6 /* #bits in hash */
1886 #define CRC32_POLY 0xEDB88320
1888 static void set_multicast_list(struct net_device *ndev)
1890 struct fec_enet_private *fep = netdev_priv(ndev);
1891 struct netdev_hw_addr *ha;
1892 unsigned int i, bit, data, crc, tmp;
1895 if (ndev->flags & IFF_PROMISC) {
1896 tmp = readl(fep->hwp + FEC_R_CNTRL);
1898 writel(tmp, fep->hwp + FEC_R_CNTRL);
1902 tmp = readl(fep->hwp + FEC_R_CNTRL);
1904 writel(tmp, fep->hwp + FEC_R_CNTRL);
1906 if (ndev->flags & IFF_ALLMULTI) {
1907 /* Catch all multicast addresses, so set the
1910 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1911 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1916 /* Clear filter and add the addresses in hash register
1918 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1919 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1921 netdev_for_each_mc_addr(ha, ndev) {
1922 /* calculate crc32 value of mac address */
1925 for (i = 0; i < ndev->addr_len; i++) {
1927 for (bit = 0; bit < 8; bit++, data >>= 1) {
1929 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1933 /* only upper 6 bits (HASH_BITS) are used
1934 * which point to specific bit in he hash registers
1936 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1939 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1940 tmp |= 1 << (hash - 32);
1941 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1943 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1945 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1950 /* Set a MAC change in hardware. */
1952 fec_set_mac_address(struct net_device *ndev, void *p)
1954 struct fec_enet_private *fep = netdev_priv(ndev);
1955 struct sockaddr *addr = p;
1958 if (!is_valid_ether_addr(addr->sa_data))
1959 return -EADDRNOTAVAIL;
1960 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1963 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1964 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1965 fep->hwp + FEC_ADDR_LOW);
1966 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1967 fep->hwp + FEC_ADDR_HIGH);
1971 #ifdef CONFIG_NET_POLL_CONTROLLER
1973 * fec_poll_controller - FEC Poll controller function
1974 * @dev: The FEC network adapter
1976 * Polled functionality used by netconsole and others in non interrupt mode
1979 static void fec_poll_controller(struct net_device *dev)
1982 struct fec_enet_private *fep = netdev_priv(dev);
1984 for (i = 0; i < FEC_IRQ_NUM; i++) {
1985 if (fep->irq[i] > 0) {
1986 disable_irq(fep->irq[i]);
1987 fec_enet_interrupt(fep->irq[i], dev);
1988 enable_irq(fep->irq[i]);
1994 static int fec_set_features(struct net_device *netdev,
1995 netdev_features_t features)
1997 struct fec_enet_private *fep = netdev_priv(netdev);
1998 netdev_features_t changed = features ^ netdev->features;
2000 netdev->features = features;
2002 /* Receive checksum has been changed */
2003 if (changed & NETIF_F_RXCSUM) {
2004 if (features & NETIF_F_RXCSUM)
2005 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2007 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2009 if (netif_running(netdev)) {
2011 fec_restart(netdev, fep->phy_dev->duplex);
2012 netif_wake_queue(netdev);
2014 fec_restart(netdev, fep->phy_dev->duplex);
2021 static const struct net_device_ops fec_netdev_ops = {
2022 .ndo_open = fec_enet_open,
2023 .ndo_stop = fec_enet_close,
2024 .ndo_start_xmit = fec_enet_start_xmit,
2025 .ndo_set_rx_mode = set_multicast_list,
2026 .ndo_change_mtu = eth_change_mtu,
2027 .ndo_validate_addr = eth_validate_addr,
2028 .ndo_tx_timeout = fec_timeout,
2029 .ndo_set_mac_address = fec_set_mac_address,
2030 .ndo_do_ioctl = fec_enet_ioctl,
2031 #ifdef CONFIG_NET_POLL_CONTROLLER
2032 .ndo_poll_controller = fec_poll_controller,
2034 .ndo_set_features = fec_set_features,
2038 * XXX: We need to clean up on failure exits here.
2041 static int fec_enet_init(struct net_device *ndev)
2043 struct fec_enet_private *fep = netdev_priv(ndev);
2044 const struct platform_device_id *id_entry =
2045 platform_get_device_id(fep->pdev);
2046 struct bufdesc *cbd_base;
2049 /* init the tx & rx ring size */
2050 fep->tx_ring_size = TX_RING_SIZE;
2051 fep->rx_ring_size = RX_RING_SIZE;
2053 if (fep->bufdesc_ex)
2054 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2056 fep->bufdesc_size = sizeof(struct bufdesc);
2057 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2060 /* Allocate memory for buffer descriptors. */
2061 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
2066 memset(cbd_base, 0, PAGE_SIZE);
2070 /* Get the Ethernet address */
2072 /* make sure MAC we just acquired is programmed into the hw */
2073 fec_set_mac_address(ndev, NULL);
2075 /* Set receive and transmit descriptor base. */
2076 fep->rx_bd_base = cbd_base;
2077 if (fep->bufdesc_ex)
2078 fep->tx_bd_base = (struct bufdesc *)
2079 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2081 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2083 /* The FEC Ethernet specific entries in the device structure */
2084 ndev->watchdog_timeo = TX_TIMEOUT;
2085 ndev->netdev_ops = &fec_netdev_ops;
2086 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2088 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2089 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2091 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
2092 /* enable hw VLAN support */
2093 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2095 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2096 /* enable hw accelerator */
2097 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2099 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2102 ndev->hw_features = ndev->features;
2104 fec_restart(ndev, 0);
2110 static void fec_reset_phy(struct platform_device *pdev)
2114 struct device_node *np = pdev->dev.of_node;
2119 of_property_read_u32(np, "phy-reset-duration", &msec);
2120 /* A sane reset duration should not be longer than 1s */
2124 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2125 if (!gpio_is_valid(phy_reset))
2128 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2129 GPIOF_OUT_INIT_LOW, "phy-reset");
2131 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2135 gpio_set_value(phy_reset, 1);
2137 #else /* CONFIG_OF */
2138 static void fec_reset_phy(struct platform_device *pdev)
2141 * In case of platform probe, the reset has been done
2145 #endif /* CONFIG_OF */
2148 fec_probe(struct platform_device *pdev)
2150 struct fec_enet_private *fep;
2151 struct fec_platform_data *pdata;
2152 struct net_device *ndev;
2153 int i, irq, ret = 0;
2155 const struct of_device_id *of_id;
2158 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2160 pdev->id_entry = of_id->data;
2162 /* Init network device */
2163 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2167 SET_NETDEV_DEV(ndev, &pdev->dev);
2169 /* setup board info structure */
2170 fep = netdev_priv(ndev);
2172 #if !defined(CONFIG_M5272)
2173 /* default enable pause frame auto negotiation */
2174 if (pdev->id_entry &&
2175 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2176 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2179 /* Select default pin state */
2180 pinctrl_pm_select_default_state(&pdev->dev);
2182 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2183 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2184 if (IS_ERR(fep->hwp)) {
2185 ret = PTR_ERR(fep->hwp);
2186 goto failed_ioremap;
2190 fep->dev_id = dev_id++;
2192 fep->bufdesc_ex = 0;
2194 platform_set_drvdata(pdev, ndev);
2196 ret = of_get_phy_mode(pdev->dev.of_node);
2198 pdata = dev_get_platdata(&pdev->dev);
2200 fep->phy_interface = pdata->phy;
2202 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2204 fep->phy_interface = ret;
2207 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2208 if (IS_ERR(fep->clk_ipg)) {
2209 ret = PTR_ERR(fep->clk_ipg);
2213 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2214 if (IS_ERR(fep->clk_ahb)) {
2215 ret = PTR_ERR(fep->clk_ahb);
2219 /* enet_out is optional, depends on board */
2220 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2221 if (IS_ERR(fep->clk_enet_out))
2222 fep->clk_enet_out = NULL;
2224 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2226 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2227 if (IS_ERR(fep->clk_ptp)) {
2228 fep->clk_ptp = NULL;
2229 fep->bufdesc_ex = 0;
2232 ret = fec_enet_clk_enable(ndev, true);
2236 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2237 if (!IS_ERR(fep->reg_phy)) {
2238 ret = regulator_enable(fep->reg_phy);
2241 "Failed to enable phy regulator: %d\n", ret);
2242 goto failed_regulator;
2245 fep->reg_phy = NULL;
2248 fec_reset_phy(pdev);
2250 if (fep->bufdesc_ex)
2253 ret = fec_enet_init(ndev);
2257 for (i = 0; i < FEC_IRQ_NUM; i++) {
2258 irq = platform_get_irq(pdev, i);
2265 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2266 0, pdev->name, ndev);
2271 ret = fec_enet_mii_init(pdev);
2273 goto failed_mii_init;
2275 /* Carrier starts down, phylib will bring it up */
2276 netif_carrier_off(ndev);
2277 fec_enet_clk_enable(ndev, false);
2278 pinctrl_pm_select_sleep_state(&pdev->dev);
2280 ret = register_netdev(ndev);
2282 goto failed_register;
2284 if (fep->bufdesc_ex && fep->ptp_clock)
2285 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2287 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2291 fec_enet_mii_remove(fep);
2296 regulator_disable(fep->reg_phy);
2298 fec_enet_clk_enable(ndev, false);
2307 fec_drv_remove(struct platform_device *pdev)
2309 struct net_device *ndev = platform_get_drvdata(pdev);
2310 struct fec_enet_private *fep = netdev_priv(ndev);
2312 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2313 unregister_netdev(ndev);
2314 fec_enet_mii_remove(fep);
2315 del_timer_sync(&fep->time_keep);
2317 regulator_disable(fep->reg_phy);
2319 ptp_clock_unregister(fep->ptp_clock);
2320 fec_enet_clk_enable(ndev, false);
2326 #ifdef CONFIG_PM_SLEEP
2328 fec_suspend(struct device *dev)
2330 struct net_device *ndev = dev_get_drvdata(dev);
2331 struct fec_enet_private *fep = netdev_priv(ndev);
2333 if (netif_running(ndev)) {
2335 netif_device_detach(ndev);
2337 fec_enet_clk_enable(ndev, false);
2338 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2341 regulator_disable(fep->reg_phy);
2347 fec_resume(struct device *dev)
2349 struct net_device *ndev = dev_get_drvdata(dev);
2350 struct fec_enet_private *fep = netdev_priv(ndev);
2354 ret = regulator_enable(fep->reg_phy);
2359 pinctrl_pm_select_default_state(&fep->pdev->dev);
2360 ret = fec_enet_clk_enable(ndev, true);
2364 if (netif_running(ndev)) {
2365 fec_restart(ndev, fep->full_duplex);
2366 netif_device_attach(ndev);
2373 regulator_disable(fep->reg_phy);
2376 #endif /* CONFIG_PM_SLEEP */
2378 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2380 static struct platform_driver fec_driver = {
2382 .name = DRIVER_NAME,
2383 .owner = THIS_MODULE,
2385 .of_match_table = fec_dt_ids,
2387 .id_table = fec_devtype,
2389 .remove = fec_drv_remove,
2392 module_platform_driver(fec_driver);
2394 MODULE_ALIAS("platform:"DRIVER_NAME);
2395 MODULE_LICENSE("GPL");