2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57 #include <linux/pinctrl/consumer.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
106 static struct platform_device_id fec_devtype[] = {
108 /* keep it for coldfire */
113 .driver_data = FEC_QUIRK_USE_GASKET,
119 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
126 .name = "mvf600-fec",
127 .driver_data = FEC_QUIRK_ENET_MAC,
132 MODULE_DEVICE_TABLE(platform, fec_devtype);
135 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
136 IMX27_FEC, /* runs on i.mx27/35/51 */
142 static const struct of_device_id fec_dt_ids[] = {
143 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
144 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
145 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
146 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
147 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
150 MODULE_DEVICE_TABLE(of, fec_dt_ids);
152 static unsigned char macaddr[ETH_ALEN];
153 module_param_array(macaddr, byte, NULL, 0);
154 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
156 #if defined(CONFIG_M5272)
158 * Some hardware gets it MAC address out of local flash memory.
159 * if this is non-zero then assume it is the address to get MAC from.
161 #if defined(CONFIG_NETtel)
162 #define FEC_FLASHMAC 0xf0006006
163 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
164 #define FEC_FLASHMAC 0xf0006000
165 #elif defined(CONFIG_CANCam)
166 #define FEC_FLASHMAC 0xf0020000
167 #elif defined (CONFIG_M5272C3)
168 #define FEC_FLASHMAC (0xffe04000 + 4)
169 #elif defined(CONFIG_MOD5272)
170 #define FEC_FLASHMAC 0xffc0406b
172 #define FEC_FLASHMAC 0
174 #endif /* CONFIG_M5272 */
176 /* Interrupt events/masks. */
177 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
178 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
179 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
180 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
181 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
182 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
183 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
184 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
185 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
186 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
189 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
191 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
193 #define PKT_MAXBUF_SIZE 1522
194 #define PKT_MINBUF_SIZE 64
195 #define PKT_MAXBLR_SIZE 1536
197 /* FEC receive acceleration */
198 #define FEC_RACC_IPDIS (1 << 1)
199 #define FEC_RACC_PRODIS (1 << 2)
200 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
203 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
204 * size bits. Other FEC hardware does not, so we need to take that into
205 * account when setting it.
207 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
208 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
209 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211 #define OPT_FRAME_SIZE 0
214 /* FEC MII MMFR bits definition */
215 #define FEC_MMFR_ST (1 << 30)
216 #define FEC_MMFR_OP_READ (2 << 28)
217 #define FEC_MMFR_OP_WRITE (1 << 28)
218 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
219 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
220 #define FEC_MMFR_TA (2 << 16)
221 #define FEC_MMFR_DATA(v) (v & 0xffff)
223 #define FEC_MII_TIMEOUT 30000 /* us */
225 /* Transmitter timeout */
226 #define TX_TIMEOUT (2 * HZ)
228 #define FEC_PAUSE_FLAG_AUTONEG 0x1
229 #define FEC_PAUSE_FLAG_ENABLE 0x2
234 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
236 struct bufdesc *new_bd = bdp + 1;
237 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
238 struct bufdesc_ex *ex_base;
239 struct bufdesc *base;
242 if (bdp >= fep->tx_bd_base) {
243 base = fep->tx_bd_base;
244 ring_size = fep->tx_ring_size;
245 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
247 base = fep->rx_bd_base;
248 ring_size = fep->rx_ring_size;
249 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
253 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
254 ex_base : ex_new_bd);
256 return (new_bd >= (base + ring_size)) ?
261 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
263 struct bufdesc *new_bd = bdp - 1;
264 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
265 struct bufdesc_ex *ex_base;
266 struct bufdesc *base;
269 if (bdp >= fep->tx_bd_base) {
270 base = fep->tx_bd_base;
271 ring_size = fep->tx_ring_size;
272 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
274 base = fep->rx_bd_base;
275 ring_size = fep->rx_ring_size;
276 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
280 return (struct bufdesc *)((ex_new_bd < ex_base) ?
281 (ex_new_bd + ring_size) : ex_new_bd);
283 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
286 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
287 struct fec_enet_private *fep)
289 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
292 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
296 entries = ((const char *)fep->dirty_tx -
297 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
299 return entries > 0 ? entries : entries + fep->tx_ring_size;
302 static void *swap_buffer(void *bufaddr, int len)
305 unsigned int *buf = bufaddr;
307 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
308 *buf = cpu_to_be32(*buf);
314 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
316 /* Only run for packets requiring a checksum. */
317 if (skb->ip_summed != CHECKSUM_PARTIAL)
320 if (unlikely(skb_cow_head(skb, 0)))
323 ip_hdr(skb)->check = 0;
324 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
330 fec_enet_submit_work(struct bufdesc *bdp, struct fec_enet_private *fep)
332 const struct platform_device_id *id_entry =
333 platform_get_device_id(fep->pdev);
334 struct bufdesc *bdp_pre;
336 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
337 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
338 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
339 fep->delay_work.trig_tx = true;
340 schedule_delayed_work(&(fep->delay_work.delay_work),
341 msecs_to_jiffies(1));
346 fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
348 struct fec_enet_private *fep = netdev_priv(ndev);
349 const struct platform_device_id *id_entry =
350 platform_get_device_id(fep->pdev);
351 struct bufdesc *bdp = fep->cur_tx;
352 struct bufdesc_ex *ebdp;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
355 unsigned short status;
356 unsigned int estatus = 0;
357 skb_frag_t *this_frag;
362 for (frag = 0; frag < nr_frags; frag++) {
363 this_frag = &skb_shinfo(skb)->frags[frag];
364 bdp = fec_enet_get_nextdesc(bdp, fep);
365 ebdp = (struct bufdesc_ex *)bdp;
367 status = bdp->cbd_sc;
368 status &= ~BD_ENET_TX_STATS;
369 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
370 frag_len = skb_shinfo(skb)->frags[frag].size;
372 /* Handle the last BD specially */
373 if (frag == nr_frags - 1) {
374 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
375 if (fep->bufdesc_ex) {
376 estatus |= BD_ENET_TX_INT;
377 if (unlikely(skb_shinfo(skb)->tx_flags &
378 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
379 estatus |= BD_ENET_TX_TS;
383 if (fep->bufdesc_ex) {
384 if (skb->ip_summed == CHECKSUM_PARTIAL)
385 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
387 ebdp->cbd_esc = estatus;
390 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
392 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
393 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
394 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
395 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
396 bufaddr = fep->tx_bounce[index];
398 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
399 swap_buffer(bufaddr, frag_len);
402 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
403 frag_len, DMA_TO_DEVICE);
404 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
405 dev_kfree_skb_any(skb);
407 netdev_err(ndev, "Tx DMA memory map failed\n");
408 goto dma_mapping_error;
411 bdp->cbd_datlen = frag_len;
412 bdp->cbd_sc = status;
421 for (i = 0; i < frag; i++) {
422 bdp = fec_enet_get_nextdesc(bdp, fep);
423 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
424 bdp->cbd_datlen, DMA_TO_DEVICE);
429 static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
431 struct fec_enet_private *fep = netdev_priv(ndev);
432 const struct platform_device_id *id_entry =
433 platform_get_device_id(fep->pdev);
434 int nr_frags = skb_shinfo(skb)->nr_frags;
435 struct bufdesc *bdp, *last_bdp;
437 unsigned short status;
438 unsigned short buflen;
439 unsigned int estatus = 0;
443 /* Protocol checksum off-load for TCP and UDP. */
444 if (fec_enet_clear_csum(skb, ndev)) {
445 dev_kfree_skb_any(skb);
449 /* Fill in a Tx ring entry */
451 status = bdp->cbd_sc;
452 status &= ~BD_ENET_TX_STATS;
454 /* Set buffer length and buffer pointer */
456 buflen = skb_headlen(skb);
458 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
459 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
460 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
461 memcpy(fep->tx_bounce[index], skb->data, buflen);
462 bufaddr = fep->tx_bounce[index];
464 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
465 swap_buffer(bufaddr, buflen);
468 /* Push the data cache so the CPM does not get stale memory
471 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
472 buflen, DMA_TO_DEVICE);
473 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
474 dev_kfree_skb_any(skb);
476 netdev_err(ndev, "Tx DMA memory map failed\n");
481 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
485 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
486 if (fep->bufdesc_ex) {
487 estatus = BD_ENET_TX_INT;
488 if (unlikely(skb_shinfo(skb)->tx_flags &
489 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
490 estatus |= BD_ENET_TX_TS;
494 if (fep->bufdesc_ex) {
496 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
498 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
500 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
502 if (skb->ip_summed == CHECKSUM_PARTIAL)
503 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
506 ebdp->cbd_esc = estatus;
509 last_bdp = fep->cur_tx;
510 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
511 /* Save skb pointer */
512 fep->tx_skbuff[index] = skb;
514 bdp->cbd_datlen = buflen;
516 /* Send it on its way. Tell FEC it's ready, interrupt when done,
517 * it's the last BD of the frame, and to put the CRC on the end.
519 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
520 bdp->cbd_sc = status;
522 fec_enet_submit_work(bdp, fep);
524 /* If this was the last BD in the ring, start at the beginning again. */
525 bdp = fec_enet_get_nextdesc(last_bdp, fep);
527 skb_tx_timestamp(skb);
531 /* Trigger transmission start */
532 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
538 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
540 struct fec_enet_private *fep = netdev_priv(ndev);
542 unsigned short status;
546 /* Fill in a Tx ring entry */
549 status = bdp->cbd_sc;
551 if (status & BD_ENET_TX_READY) {
552 /* Ooops. All transmit buffers are full. Bail out.
553 * This should not happen, since ndev->tbusy should be set.
556 netdev_err(ndev, "tx queue full!\n");
557 return NETDEV_TX_BUSY;
560 ret = fec_enet_txq_submit_skb(skb, ndev);
564 entries_free = fec_enet_get_free_txdesc_num(fep);
565 if (entries_free < MAX_SKB_FRAGS + 1)
566 netif_stop_queue(ndev);
571 /* Init RX & TX buffer descriptors
573 static void fec_enet_bd_init(struct net_device *dev)
575 struct fec_enet_private *fep = netdev_priv(dev);
579 /* Initialize the receive buffer descriptors. */
580 bdp = fep->rx_bd_base;
581 for (i = 0; i < fep->rx_ring_size; i++) {
583 /* Initialize the BD for every fragment in the page. */
584 if (bdp->cbd_bufaddr)
585 bdp->cbd_sc = BD_ENET_RX_EMPTY;
588 bdp = fec_enet_get_nextdesc(bdp, fep);
591 /* Set the last buffer to wrap */
592 bdp = fec_enet_get_prevdesc(bdp, fep);
593 bdp->cbd_sc |= BD_SC_WRAP;
595 fep->cur_rx = fep->rx_bd_base;
597 /* ...and the same for transmit */
598 bdp = fep->tx_bd_base;
600 for (i = 0; i < fep->tx_ring_size; i++) {
602 /* Initialize the BD for every fragment in the page. */
604 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
605 dev_kfree_skb_any(fep->tx_skbuff[i]);
606 fep->tx_skbuff[i] = NULL;
608 bdp->cbd_bufaddr = 0;
609 bdp = fec_enet_get_nextdesc(bdp, fep);
612 /* Set the last buffer to wrap */
613 bdp = fec_enet_get_prevdesc(bdp, fep);
614 bdp->cbd_sc |= BD_SC_WRAP;
618 /* This function is called to start or restart the FEC during a link
619 * change. This only happens when switching between half and full
623 fec_restart(struct net_device *ndev, int duplex)
625 struct fec_enet_private *fep = netdev_priv(ndev);
626 const struct platform_device_id *id_entry =
627 platform_get_device_id(fep->pdev);
631 u32 rcntl = OPT_FRAME_SIZE | 0x04;
632 u32 ecntl = 0x2; /* ETHEREN */
634 if (netif_running(ndev)) {
635 netif_device_detach(ndev);
636 napi_disable(&fep->napi);
637 netif_stop_queue(ndev);
638 netif_tx_lock_bh(ndev);
641 /* Whack a reset. We should wait for this. */
642 writel(1, fep->hwp + FEC_ECNTRL);
646 * enet-mac reset will reset mac address registers too,
647 * so need to reconfigure it.
649 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
650 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
651 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
652 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
655 /* Clear any outstanding interrupt. */
656 writel(0xffc00000, fep->hwp + FEC_IEVENT);
658 /* Set maximum receive buffer size. */
659 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
661 fec_enet_bd_init(ndev);
663 /* Set receive and transmit descriptor base. */
664 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
666 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
667 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
669 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
670 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
673 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
674 if (fep->tx_skbuff[i]) {
675 dev_kfree_skb_any(fep->tx_skbuff[i]);
676 fep->tx_skbuff[i] = NULL;
680 /* Enable MII mode */
683 writel(0x04, fep->hwp + FEC_X_CNTRL);
687 writel(0x0, fep->hwp + FEC_X_CNTRL);
690 fep->full_duplex = duplex;
693 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
695 #if !defined(CONFIG_M5272)
696 /* set RX checksum */
697 val = readl(fep->hwp + FEC_RACC);
698 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
699 val |= FEC_RACC_OPTIONS;
701 val &= ~FEC_RACC_OPTIONS;
702 writel(val, fep->hwp + FEC_RACC);
706 * The phy interface and speed need to get configured
707 * differently on enet-mac.
709 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
710 /* Enable flow control and length check */
711 rcntl |= 0x40000000 | 0x00000020;
713 /* RGMII, RMII or MII */
714 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
716 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
721 /* 1G, 100M or 10M */
723 if (fep->phy_dev->speed == SPEED_1000)
725 else if (fep->phy_dev->speed == SPEED_100)
731 #ifdef FEC_MIIGSK_ENR
732 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
734 /* disable the gasket and wait */
735 writel(0, fep->hwp + FEC_MIIGSK_ENR);
736 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
740 * configure the gasket:
741 * RMII, 50 MHz, no loopback, no echo
742 * MII, 25 MHz, no loopback, no echo
744 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
745 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
746 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
747 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
748 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
750 /* re-enable the gasket */
751 writel(2, fep->hwp + FEC_MIIGSK_ENR);
756 #if !defined(CONFIG_M5272)
757 /* enable pause frame*/
758 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
759 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
760 fep->phy_dev && fep->phy_dev->pause)) {
761 rcntl |= FEC_ENET_FCE;
763 /* set FIFO threshold parameter to reduce overrun */
764 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
765 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
766 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
767 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
770 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
772 rcntl &= ~FEC_ENET_FCE;
774 #endif /* !defined(CONFIG_M5272) */
776 writel(rcntl, fep->hwp + FEC_R_CNTRL);
778 /* Setup multicast filter. */
779 set_multicast_list(ndev);
781 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
782 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
785 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
786 /* enable ENET endian swap */
788 /* enable ENET store and forward mode */
789 writel(1 << 8, fep->hwp + FEC_X_WMRK);
796 /* Enable the MIB statistic event counters */
797 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
800 /* And last, enable the transmit and receive processing */
801 writel(ecntl, fep->hwp + FEC_ECNTRL);
802 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
805 fec_ptp_start_cyclecounter(ndev);
807 /* Enable interrupts we wish to service */
808 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
810 if (netif_running(ndev)) {
811 netif_tx_unlock_bh(ndev);
812 netif_wake_queue(ndev);
813 napi_enable(&fep->napi);
814 netif_device_attach(ndev);
819 fec_stop(struct net_device *ndev)
821 struct fec_enet_private *fep = netdev_priv(ndev);
822 const struct platform_device_id *id_entry =
823 platform_get_device_id(fep->pdev);
824 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
826 /* We cannot expect a graceful transmit stop without link !!! */
828 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
830 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
831 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
834 /* Whack a reset. We should wait for this. */
835 writel(1, fep->hwp + FEC_ECNTRL);
837 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
838 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
840 /* We have to keep ENET enabled to have MII interrupt stay working */
841 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
842 writel(2, fep->hwp + FEC_ECNTRL);
843 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
849 fec_timeout(struct net_device *ndev)
851 struct fec_enet_private *fep = netdev_priv(ndev);
853 ndev->stats.tx_errors++;
855 fep->delay_work.timeout = true;
856 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
859 static void fec_enet_work(struct work_struct *work)
861 struct fec_enet_private *fep =
863 struct fec_enet_private,
864 delay_work.delay_work.work);
866 if (fep->delay_work.timeout) {
867 fep->delay_work.timeout = false;
868 fec_restart(fep->netdev, fep->full_duplex);
869 netif_wake_queue(fep->netdev);
872 if (fep->delay_work.trig_tx) {
873 fep->delay_work.trig_tx = false;
874 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
879 fec_enet_tx(struct net_device *ndev)
881 struct fec_enet_private *fep;
883 unsigned short status;
888 fep = netdev_priv(ndev);
891 /* get next bdp of dirty_tx */
892 bdp = fec_enet_get_nextdesc(bdp, fep);
894 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
896 /* current queue is empty */
897 if (bdp == fep->cur_tx)
900 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
902 skb = fep->tx_skbuff[index];
903 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, bdp->cbd_datlen,
905 bdp->cbd_bufaddr = 0;
907 bdp = fec_enet_get_nextdesc(bdp, fep);
911 /* Check for errors. */
912 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
913 BD_ENET_TX_RL | BD_ENET_TX_UN |
915 ndev->stats.tx_errors++;
916 if (status & BD_ENET_TX_HB) /* No heartbeat */
917 ndev->stats.tx_heartbeat_errors++;
918 if (status & BD_ENET_TX_LC) /* Late collision */
919 ndev->stats.tx_window_errors++;
920 if (status & BD_ENET_TX_RL) /* Retrans limit */
921 ndev->stats.tx_aborted_errors++;
922 if (status & BD_ENET_TX_UN) /* Underrun */
923 ndev->stats.tx_fifo_errors++;
924 if (status & BD_ENET_TX_CSL) /* Carrier lost */
925 ndev->stats.tx_carrier_errors++;
927 ndev->stats.tx_packets++;
928 ndev->stats.tx_bytes += skb->len;
931 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
933 struct skb_shared_hwtstamps shhwtstamps;
935 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
937 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
938 spin_lock_irqsave(&fep->tmreg_lock, flags);
939 shhwtstamps.hwtstamp = ns_to_ktime(
940 timecounter_cyc2time(&fep->tc, ebdp->ts));
941 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
942 skb_tstamp_tx(skb, &shhwtstamps);
945 if (status & BD_ENET_TX_READY)
946 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
948 /* Deferred means some collisions occurred during transmit,
949 * but we eventually sent the packet OK.
951 if (status & BD_ENET_TX_DEF)
952 ndev->stats.collisions++;
954 /* Free the sk buffer associated with this last transmit */
955 dev_kfree_skb_any(skb);
956 fep->tx_skbuff[index] = NULL;
960 /* Update pointer to next buffer descriptor to be transmitted */
961 bdp = fec_enet_get_nextdesc(bdp, fep);
963 /* Since we have freed up a buffer, the ring is no longer full
965 entries = fec_enet_get_free_txdesc_num(fep);
966 if (entries >= MAX_SKB_FRAGS + 1 && netif_queue_stopped(ndev))
967 netif_wake_queue(ndev);
972 /* During a receive, the cur_rx points to the current incoming buffer.
973 * When we update through the ring, if the next incoming buffer has
974 * not been given to the system, we just set the empty indicator,
975 * effectively tossing the packet.
978 fec_enet_rx(struct net_device *ndev, int budget)
980 struct fec_enet_private *fep = netdev_priv(ndev);
981 const struct platform_device_id *id_entry =
982 platform_get_device_id(fep->pdev);
984 unsigned short status;
988 int pkt_received = 0;
989 struct bufdesc_ex *ebdp = NULL;
990 bool vlan_packet_rcvd = false;
998 /* First, grab all of the stats for the incoming packet.
999 * These get messed up if we get called due to a busy condition.
1003 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1005 if (pkt_received >= budget)
1009 /* Since we have allocated space to hold a complete frame,
1010 * the last indicator should be set.
1012 if ((status & BD_ENET_RX_LAST) == 0)
1013 netdev_err(ndev, "rcv is not +last\n");
1016 goto rx_processing_done;
1018 /* Check for errors. */
1019 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1020 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1021 ndev->stats.rx_errors++;
1022 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1023 /* Frame too long or too short. */
1024 ndev->stats.rx_length_errors++;
1026 if (status & BD_ENET_RX_NO) /* Frame alignment */
1027 ndev->stats.rx_frame_errors++;
1028 if (status & BD_ENET_RX_CR) /* CRC Error */
1029 ndev->stats.rx_crc_errors++;
1030 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1031 ndev->stats.rx_fifo_errors++;
1034 /* Report late collisions as a frame error.
1035 * On this error, the BD is closed, but we don't know what we
1036 * have in the buffer. So, just drop this frame on the floor.
1038 if (status & BD_ENET_RX_CL) {
1039 ndev->stats.rx_errors++;
1040 ndev->stats.rx_frame_errors++;
1041 goto rx_processing_done;
1044 /* Process the incoming frame. */
1045 ndev->stats.rx_packets++;
1046 pkt_len = bdp->cbd_datlen;
1047 ndev->stats.rx_bytes += pkt_len;
1049 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
1050 data = fep->rx_skbuff[index]->data;
1051 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1052 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1054 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1055 swap_buffer(data, pkt_len);
1057 /* Extract the enhanced buffer descriptor */
1059 if (fep->bufdesc_ex)
1060 ebdp = (struct bufdesc_ex *)bdp;
1062 /* If this is a VLAN packet remove the VLAN Tag */
1063 vlan_packet_rcvd = false;
1064 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1065 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1066 /* Push and remove the vlan tag */
1067 struct vlan_hdr *vlan_header =
1068 (struct vlan_hdr *) (data + ETH_HLEN);
1069 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1070 pkt_len -= VLAN_HLEN;
1072 vlan_packet_rcvd = true;
1075 /* This does 16 byte alignment, exactly what we need.
1076 * The packet length includes FCS, but we don't want to
1077 * include that when passing upstream as it messes up
1078 * bridging applications.
1080 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1082 if (unlikely(!skb)) {
1083 ndev->stats.rx_dropped++;
1085 int payload_offset = (2 * ETH_ALEN);
1086 skb_reserve(skb, NET_IP_ALIGN);
1087 skb_put(skb, pkt_len - 4); /* Make room */
1089 /* Extract the frame data without the VLAN header. */
1090 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1091 if (vlan_packet_rcvd)
1092 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1093 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1094 data + payload_offset,
1095 pkt_len - 4 - (2 * ETH_ALEN));
1097 skb->protocol = eth_type_trans(skb, ndev);
1099 /* Get receive timestamp from the skb */
1100 if (fep->hwts_rx_en && fep->bufdesc_ex) {
1101 struct skb_shared_hwtstamps *shhwtstamps =
1103 unsigned long flags;
1105 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1107 spin_lock_irqsave(&fep->tmreg_lock, flags);
1108 shhwtstamps->hwtstamp = ns_to_ktime(
1109 timecounter_cyc2time(&fep->tc, ebdp->ts));
1110 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1113 if (fep->bufdesc_ex &&
1114 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1115 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1116 /* don't check it */
1117 skb->ip_summed = CHECKSUM_UNNECESSARY;
1119 skb_checksum_none_assert(skb);
1123 /* Handle received VLAN packets */
1124 if (vlan_packet_rcvd)
1125 __vlan_hwaccel_put_tag(skb,
1129 napi_gro_receive(&fep->napi, skb);
1132 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1133 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1135 /* Clear the status flags for this buffer */
1136 status &= ~BD_ENET_RX_STATS;
1138 /* Mark the buffer empty */
1139 status |= BD_ENET_RX_EMPTY;
1140 bdp->cbd_sc = status;
1142 if (fep->bufdesc_ex) {
1143 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1145 ebdp->cbd_esc = BD_ENET_RX_INT;
1150 /* Update BD pointer to next entry */
1151 bdp = fec_enet_get_nextdesc(bdp, fep);
1153 /* Doing this here will keep the FEC running while we process
1154 * incoming frames. On a heavily loaded network, we should be
1155 * able to keep up at the expense of system resources.
1157 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1161 return pkt_received;
1165 fec_enet_interrupt(int irq, void *dev_id)
1167 struct net_device *ndev = dev_id;
1168 struct fec_enet_private *fep = netdev_priv(ndev);
1170 irqreturn_t ret = IRQ_NONE;
1173 int_events = readl(fep->hwp + FEC_IEVENT);
1174 writel(int_events, fep->hwp + FEC_IEVENT);
1176 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1179 /* Disable the RX interrupt */
1180 if (napi_schedule_prep(&fep->napi)) {
1181 writel(FEC_RX_DISABLED_IMASK,
1182 fep->hwp + FEC_IMASK);
1183 __napi_schedule(&fep->napi);
1187 if (int_events & FEC_ENET_MII) {
1189 complete(&fep->mdio_done);
1191 } while (int_events);
1196 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1198 struct net_device *ndev = napi->dev;
1199 int pkts = fec_enet_rx(ndev, budget);
1200 struct fec_enet_private *fep = netdev_priv(ndev);
1204 if (pkts < budget) {
1205 napi_complete(napi);
1206 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1211 /* ------------------------------------------------------------------------- */
1212 static void fec_get_mac(struct net_device *ndev)
1214 struct fec_enet_private *fep = netdev_priv(ndev);
1215 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1216 unsigned char *iap, tmpaddr[ETH_ALEN];
1219 * try to get mac address in following order:
1221 * 1) module parameter via kernel command line in form
1222 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1227 * 2) from device tree data
1229 if (!is_valid_ether_addr(iap)) {
1230 struct device_node *np = fep->pdev->dev.of_node;
1232 const char *mac = of_get_mac_address(np);
1234 iap = (unsigned char *) mac;
1239 * 3) from flash or fuse (via platform data)
1241 if (!is_valid_ether_addr(iap)) {
1244 iap = (unsigned char *)FEC_FLASHMAC;
1247 iap = (unsigned char *)&pdata->mac;
1252 * 4) FEC mac registers set by bootloader
1254 if (!is_valid_ether_addr(iap)) {
1255 *((__be32 *) &tmpaddr[0]) =
1256 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1257 *((__be16 *) &tmpaddr[4]) =
1258 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1263 * 5) random mac address
1265 if (!is_valid_ether_addr(iap)) {
1266 /* Report it and use a random ethernet address instead */
1267 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1268 eth_hw_addr_random(ndev);
1269 netdev_info(ndev, "Using random MAC address: %pM\n",
1274 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1276 /* Adjust MAC if using macaddr */
1278 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1281 /* ------------------------------------------------------------------------- */
1286 static void fec_enet_adjust_link(struct net_device *ndev)
1288 struct fec_enet_private *fep = netdev_priv(ndev);
1289 struct phy_device *phy_dev = fep->phy_dev;
1290 int status_change = 0;
1292 /* Prevent a state halted on mii error */
1293 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1294 phy_dev->state = PHY_RESUMING;
1298 if (phy_dev->link) {
1300 fep->link = phy_dev->link;
1304 if (fep->full_duplex != phy_dev->duplex)
1307 if (phy_dev->speed != fep->speed) {
1308 fep->speed = phy_dev->speed;
1312 /* if any of the above changed restart the FEC */
1314 fec_restart(ndev, phy_dev->duplex);
1318 fep->link = phy_dev->link;
1324 phy_print_status(phy_dev);
1327 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1329 struct fec_enet_private *fep = bus->priv;
1330 unsigned long time_left;
1332 fep->mii_timeout = 0;
1333 init_completion(&fep->mdio_done);
1335 /* start a read op */
1336 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1337 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1338 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1340 /* wait for end of transfer */
1341 time_left = wait_for_completion_timeout(&fep->mdio_done,
1342 usecs_to_jiffies(FEC_MII_TIMEOUT));
1343 if (time_left == 0) {
1344 fep->mii_timeout = 1;
1345 netdev_err(fep->netdev, "MDIO read timeout\n");
1350 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1353 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1356 struct fec_enet_private *fep = bus->priv;
1357 unsigned long time_left;
1359 fep->mii_timeout = 0;
1360 init_completion(&fep->mdio_done);
1362 /* start a write op */
1363 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1364 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1365 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1366 fep->hwp + FEC_MII_DATA);
1368 /* wait for end of transfer */
1369 time_left = wait_for_completion_timeout(&fep->mdio_done,
1370 usecs_to_jiffies(FEC_MII_TIMEOUT));
1371 if (time_left == 0) {
1372 fep->mii_timeout = 1;
1373 netdev_err(fep->netdev, "MDIO write timeout\n");
1380 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1382 struct fec_enet_private *fep = netdev_priv(ndev);
1386 ret = clk_prepare_enable(fep->clk_ahb);
1389 ret = clk_prepare_enable(fep->clk_ipg);
1391 goto failed_clk_ipg;
1392 if (fep->clk_enet_out) {
1393 ret = clk_prepare_enable(fep->clk_enet_out);
1395 goto failed_clk_enet_out;
1398 ret = clk_prepare_enable(fep->clk_ptp);
1400 goto failed_clk_ptp;
1403 clk_disable_unprepare(fep->clk_ahb);
1404 clk_disable_unprepare(fep->clk_ipg);
1405 if (fep->clk_enet_out)
1406 clk_disable_unprepare(fep->clk_enet_out);
1408 clk_disable_unprepare(fep->clk_ptp);
1413 if (fep->clk_enet_out)
1414 clk_disable_unprepare(fep->clk_enet_out);
1415 failed_clk_enet_out:
1416 clk_disable_unprepare(fep->clk_ipg);
1418 clk_disable_unprepare(fep->clk_ahb);
1423 static int fec_enet_mii_probe(struct net_device *ndev)
1425 struct fec_enet_private *fep = netdev_priv(ndev);
1426 const struct platform_device_id *id_entry =
1427 platform_get_device_id(fep->pdev);
1428 struct phy_device *phy_dev = NULL;
1429 char mdio_bus_id[MII_BUS_ID_SIZE];
1430 char phy_name[MII_BUS_ID_SIZE + 3];
1432 int dev_id = fep->dev_id;
1434 fep->phy_dev = NULL;
1436 /* check for attached phy */
1437 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1438 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1440 if (fep->mii_bus->phy_map[phy_id] == NULL)
1442 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1446 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1450 if (phy_id >= PHY_MAX_ADDR) {
1451 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1452 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1456 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1457 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1458 fep->phy_interface);
1459 if (IS_ERR(phy_dev)) {
1460 netdev_err(ndev, "could not attach to PHY\n");
1461 return PTR_ERR(phy_dev);
1464 /* mask with MAC supported features */
1465 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1466 phy_dev->supported &= PHY_GBIT_FEATURES;
1467 #if !defined(CONFIG_M5272)
1468 phy_dev->supported |= SUPPORTED_Pause;
1472 phy_dev->supported &= PHY_BASIC_FEATURES;
1474 phy_dev->advertising = phy_dev->supported;
1476 fep->phy_dev = phy_dev;
1478 fep->full_duplex = 0;
1480 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1481 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1487 static int fec_enet_mii_init(struct platform_device *pdev)
1489 static struct mii_bus *fec0_mii_bus;
1490 struct net_device *ndev = platform_get_drvdata(pdev);
1491 struct fec_enet_private *fep = netdev_priv(ndev);
1492 const struct platform_device_id *id_entry =
1493 platform_get_device_id(fep->pdev);
1494 int err = -ENXIO, i;
1497 * The dual fec interfaces are not equivalent with enet-mac.
1498 * Here are the differences:
1500 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1501 * - fec0 acts as the 1588 time master while fec1 is slave
1502 * - external phys can only be configured by fec0
1504 * That is to say fec1 can not work independently. It only works
1505 * when fec0 is working. The reason behind this design is that the
1506 * second interface is added primarily for Switch mode.
1508 * Because of the last point above, both phys are attached on fec0
1509 * mdio interface in board design, and need to be configured by
1512 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1513 /* fec1 uses fec0 mii_bus */
1514 if (mii_cnt && fec0_mii_bus) {
1515 fep->mii_bus = fec0_mii_bus;
1522 fep->mii_timeout = 0;
1525 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1527 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1528 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1529 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1532 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1533 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1535 fep->phy_speed <<= 1;
1536 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1538 fep->mii_bus = mdiobus_alloc();
1539 if (fep->mii_bus == NULL) {
1544 fep->mii_bus->name = "fec_enet_mii_bus";
1545 fep->mii_bus->read = fec_enet_mdio_read;
1546 fep->mii_bus->write = fec_enet_mdio_write;
1547 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1548 pdev->name, fep->dev_id + 1);
1549 fep->mii_bus->priv = fep;
1550 fep->mii_bus->parent = &pdev->dev;
1552 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1553 if (!fep->mii_bus->irq) {
1555 goto err_out_free_mdiobus;
1558 for (i = 0; i < PHY_MAX_ADDR; i++)
1559 fep->mii_bus->irq[i] = PHY_POLL;
1561 if (mdiobus_register(fep->mii_bus))
1562 goto err_out_free_mdio_irq;
1566 /* save fec0 mii_bus */
1567 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1568 fec0_mii_bus = fep->mii_bus;
1572 err_out_free_mdio_irq:
1573 kfree(fep->mii_bus->irq);
1574 err_out_free_mdiobus:
1575 mdiobus_free(fep->mii_bus);
1580 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1582 if (--mii_cnt == 0) {
1583 mdiobus_unregister(fep->mii_bus);
1584 kfree(fep->mii_bus->irq);
1585 mdiobus_free(fep->mii_bus);
1589 static int fec_enet_get_settings(struct net_device *ndev,
1590 struct ethtool_cmd *cmd)
1592 struct fec_enet_private *fep = netdev_priv(ndev);
1593 struct phy_device *phydev = fep->phy_dev;
1598 return phy_ethtool_gset(phydev, cmd);
1601 static int fec_enet_set_settings(struct net_device *ndev,
1602 struct ethtool_cmd *cmd)
1604 struct fec_enet_private *fep = netdev_priv(ndev);
1605 struct phy_device *phydev = fep->phy_dev;
1610 return phy_ethtool_sset(phydev, cmd);
1613 static void fec_enet_get_drvinfo(struct net_device *ndev,
1614 struct ethtool_drvinfo *info)
1616 struct fec_enet_private *fep = netdev_priv(ndev);
1618 strlcpy(info->driver, fep->pdev->dev.driver->name,
1619 sizeof(info->driver));
1620 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1621 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1624 static int fec_enet_get_ts_info(struct net_device *ndev,
1625 struct ethtool_ts_info *info)
1627 struct fec_enet_private *fep = netdev_priv(ndev);
1629 if (fep->bufdesc_ex) {
1631 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1632 SOF_TIMESTAMPING_RX_SOFTWARE |
1633 SOF_TIMESTAMPING_SOFTWARE |
1634 SOF_TIMESTAMPING_TX_HARDWARE |
1635 SOF_TIMESTAMPING_RX_HARDWARE |
1636 SOF_TIMESTAMPING_RAW_HARDWARE;
1638 info->phc_index = ptp_clock_index(fep->ptp_clock);
1640 info->phc_index = -1;
1642 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1643 (1 << HWTSTAMP_TX_ON);
1645 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1646 (1 << HWTSTAMP_FILTER_ALL);
1649 return ethtool_op_get_ts_info(ndev, info);
1653 #if !defined(CONFIG_M5272)
1655 static void fec_enet_get_pauseparam(struct net_device *ndev,
1656 struct ethtool_pauseparam *pause)
1658 struct fec_enet_private *fep = netdev_priv(ndev);
1660 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1661 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1662 pause->rx_pause = pause->tx_pause;
1665 static int fec_enet_set_pauseparam(struct net_device *ndev,
1666 struct ethtool_pauseparam *pause)
1668 struct fec_enet_private *fep = netdev_priv(ndev);
1670 if (pause->tx_pause != pause->rx_pause) {
1672 "hardware only support enable/disable both tx and rx");
1676 fep->pause_flag = 0;
1678 /* tx pause must be same as rx pause */
1679 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1680 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1682 if (pause->rx_pause || pause->autoneg) {
1683 fep->phy_dev->supported |= ADVERTISED_Pause;
1684 fep->phy_dev->advertising |= ADVERTISED_Pause;
1686 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1687 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1690 if (pause->autoneg) {
1691 if (netif_running(ndev))
1693 phy_start_aneg(fep->phy_dev);
1695 if (netif_running(ndev))
1696 fec_restart(ndev, 0);
1701 static const struct fec_stat {
1702 char name[ETH_GSTRING_LEN];
1706 { "tx_dropped", RMON_T_DROP },
1707 { "tx_packets", RMON_T_PACKETS },
1708 { "tx_broadcast", RMON_T_BC_PKT },
1709 { "tx_multicast", RMON_T_MC_PKT },
1710 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1711 { "tx_undersize", RMON_T_UNDERSIZE },
1712 { "tx_oversize", RMON_T_OVERSIZE },
1713 { "tx_fragment", RMON_T_FRAG },
1714 { "tx_jabber", RMON_T_JAB },
1715 { "tx_collision", RMON_T_COL },
1716 { "tx_64byte", RMON_T_P64 },
1717 { "tx_65to127byte", RMON_T_P65TO127 },
1718 { "tx_128to255byte", RMON_T_P128TO255 },
1719 { "tx_256to511byte", RMON_T_P256TO511 },
1720 { "tx_512to1023byte", RMON_T_P512TO1023 },
1721 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1722 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1723 { "tx_octets", RMON_T_OCTETS },
1726 { "IEEE_tx_drop", IEEE_T_DROP },
1727 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1728 { "IEEE_tx_1col", IEEE_T_1COL },
1729 { "IEEE_tx_mcol", IEEE_T_MCOL },
1730 { "IEEE_tx_def", IEEE_T_DEF },
1731 { "IEEE_tx_lcol", IEEE_T_LCOL },
1732 { "IEEE_tx_excol", IEEE_T_EXCOL },
1733 { "IEEE_tx_macerr", IEEE_T_MACERR },
1734 { "IEEE_tx_cserr", IEEE_T_CSERR },
1735 { "IEEE_tx_sqe", IEEE_T_SQE },
1736 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1737 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1740 { "rx_packets", RMON_R_PACKETS },
1741 { "rx_broadcast", RMON_R_BC_PKT },
1742 { "rx_multicast", RMON_R_MC_PKT },
1743 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1744 { "rx_undersize", RMON_R_UNDERSIZE },
1745 { "rx_oversize", RMON_R_OVERSIZE },
1746 { "rx_fragment", RMON_R_FRAG },
1747 { "rx_jabber", RMON_R_JAB },
1748 { "rx_64byte", RMON_R_P64 },
1749 { "rx_65to127byte", RMON_R_P65TO127 },
1750 { "rx_128to255byte", RMON_R_P128TO255 },
1751 { "rx_256to511byte", RMON_R_P256TO511 },
1752 { "rx_512to1023byte", RMON_R_P512TO1023 },
1753 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1754 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1755 { "rx_octets", RMON_R_OCTETS },
1758 { "IEEE_rx_drop", IEEE_R_DROP },
1759 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1760 { "IEEE_rx_crc", IEEE_R_CRC },
1761 { "IEEE_rx_align", IEEE_R_ALIGN },
1762 { "IEEE_rx_macerr", IEEE_R_MACERR },
1763 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1764 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1767 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1768 struct ethtool_stats *stats, u64 *data)
1770 struct fec_enet_private *fep = netdev_priv(dev);
1773 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1774 data[i] = readl(fep->hwp + fec_stats[i].offset);
1777 static void fec_enet_get_strings(struct net_device *netdev,
1778 u32 stringset, u8 *data)
1781 switch (stringset) {
1783 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1784 memcpy(data + i * ETH_GSTRING_LEN,
1785 fec_stats[i].name, ETH_GSTRING_LEN);
1790 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1794 return ARRAY_SIZE(fec_stats);
1799 #endif /* !defined(CONFIG_M5272) */
1801 static int fec_enet_nway_reset(struct net_device *dev)
1803 struct fec_enet_private *fep = netdev_priv(dev);
1804 struct phy_device *phydev = fep->phy_dev;
1809 return genphy_restart_aneg(phydev);
1812 static const struct ethtool_ops fec_enet_ethtool_ops = {
1813 #if !defined(CONFIG_M5272)
1814 .get_pauseparam = fec_enet_get_pauseparam,
1815 .set_pauseparam = fec_enet_set_pauseparam,
1817 .get_settings = fec_enet_get_settings,
1818 .set_settings = fec_enet_set_settings,
1819 .get_drvinfo = fec_enet_get_drvinfo,
1820 .get_link = ethtool_op_get_link,
1821 .get_ts_info = fec_enet_get_ts_info,
1822 .nway_reset = fec_enet_nway_reset,
1823 #ifndef CONFIG_M5272
1824 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1825 .get_strings = fec_enet_get_strings,
1826 .get_sset_count = fec_enet_get_sset_count,
1830 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1832 struct fec_enet_private *fep = netdev_priv(ndev);
1833 struct phy_device *phydev = fep->phy_dev;
1835 if (!netif_running(ndev))
1841 if (fep->bufdesc_ex) {
1842 if (cmd == SIOCSHWTSTAMP)
1843 return fec_ptp_set(ndev, rq);
1844 if (cmd == SIOCGHWTSTAMP)
1845 return fec_ptp_get(ndev, rq);
1848 return phy_mii_ioctl(phydev, rq, cmd);
1851 static void fec_enet_free_buffers(struct net_device *ndev)
1853 struct fec_enet_private *fep = netdev_priv(ndev);
1855 struct sk_buff *skb;
1856 struct bufdesc *bdp;
1858 bdp = fep->rx_bd_base;
1859 for (i = 0; i < fep->rx_ring_size; i++) {
1860 skb = fep->rx_skbuff[i];
1862 if (bdp->cbd_bufaddr)
1863 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1864 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1867 bdp = fec_enet_get_nextdesc(bdp, fep);
1870 bdp = fep->tx_bd_base;
1871 for (i = 0; i < fep->tx_ring_size; i++)
1872 kfree(fep->tx_bounce[i]);
1875 static int fec_enet_alloc_buffers(struct net_device *ndev)
1877 struct fec_enet_private *fep = netdev_priv(ndev);
1879 struct sk_buff *skb;
1880 struct bufdesc *bdp;
1882 bdp = fep->rx_bd_base;
1883 for (i = 0; i < fep->rx_ring_size; i++) {
1884 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1886 fec_enet_free_buffers(ndev);
1889 fep->rx_skbuff[i] = skb;
1891 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1892 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1893 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1894 fec_enet_free_buffers(ndev);
1895 if (net_ratelimit())
1896 netdev_err(ndev, "Rx DMA memory map failed\n");
1899 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1901 if (fep->bufdesc_ex) {
1902 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1903 ebdp->cbd_esc = BD_ENET_RX_INT;
1906 bdp = fec_enet_get_nextdesc(bdp, fep);
1909 /* Set the last buffer to wrap. */
1910 bdp = fec_enet_get_prevdesc(bdp, fep);
1911 bdp->cbd_sc |= BD_SC_WRAP;
1913 bdp = fep->tx_bd_base;
1914 for (i = 0; i < fep->tx_ring_size; i++) {
1915 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1918 bdp->cbd_bufaddr = 0;
1920 if (fep->bufdesc_ex) {
1921 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1922 ebdp->cbd_esc = BD_ENET_TX_INT;
1925 bdp = fec_enet_get_nextdesc(bdp, fep);
1928 /* Set the last buffer to wrap. */
1929 bdp = fec_enet_get_prevdesc(bdp, fep);
1930 bdp->cbd_sc |= BD_SC_WRAP;
1936 fec_enet_open(struct net_device *ndev)
1938 struct fec_enet_private *fep = netdev_priv(ndev);
1941 pinctrl_pm_select_default_state(&fep->pdev->dev);
1942 ret = fec_enet_clk_enable(ndev, true);
1946 /* I should reset the ring buffers here, but I don't yet know
1947 * a simple way to do that.
1950 ret = fec_enet_alloc_buffers(ndev);
1954 /* Probe and connect to PHY when open the interface */
1955 ret = fec_enet_mii_probe(ndev);
1957 fec_enet_free_buffers(ndev);
1961 napi_enable(&fep->napi);
1962 phy_start(fep->phy_dev);
1963 netif_start_queue(ndev);
1969 fec_enet_close(struct net_device *ndev)
1971 struct fec_enet_private *fep = netdev_priv(ndev);
1973 /* Don't know what to do yet. */
1974 napi_disable(&fep->napi);
1976 netif_stop_queue(ndev);
1980 phy_stop(fep->phy_dev);
1981 phy_disconnect(fep->phy_dev);
1984 fec_enet_clk_enable(ndev, false);
1985 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
1986 fec_enet_free_buffers(ndev);
1991 /* Set or clear the multicast filter for this adaptor.
1992 * Skeleton taken from sunlance driver.
1993 * The CPM Ethernet implementation allows Multicast as well as individual
1994 * MAC address filtering. Some of the drivers check to make sure it is
1995 * a group multicast address, and discard those that are not. I guess I
1996 * will do the same for now, but just remove the test if you want
1997 * individual filtering as well (do the upper net layers want or support
1998 * this kind of feature?).
2001 #define HASH_BITS 6 /* #bits in hash */
2002 #define CRC32_POLY 0xEDB88320
2004 static void set_multicast_list(struct net_device *ndev)
2006 struct fec_enet_private *fep = netdev_priv(ndev);
2007 struct netdev_hw_addr *ha;
2008 unsigned int i, bit, data, crc, tmp;
2011 if (ndev->flags & IFF_PROMISC) {
2012 tmp = readl(fep->hwp + FEC_R_CNTRL);
2014 writel(tmp, fep->hwp + FEC_R_CNTRL);
2018 tmp = readl(fep->hwp + FEC_R_CNTRL);
2020 writel(tmp, fep->hwp + FEC_R_CNTRL);
2022 if (ndev->flags & IFF_ALLMULTI) {
2023 /* Catch all multicast addresses, so set the
2026 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2027 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2032 /* Clear filter and add the addresses in hash register
2034 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2035 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2037 netdev_for_each_mc_addr(ha, ndev) {
2038 /* calculate crc32 value of mac address */
2041 for (i = 0; i < ndev->addr_len; i++) {
2043 for (bit = 0; bit < 8; bit++, data >>= 1) {
2045 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2049 /* only upper 6 bits (HASH_BITS) are used
2050 * which point to specific bit in he hash registers
2052 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2055 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2056 tmp |= 1 << (hash - 32);
2057 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2059 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2061 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2066 /* Set a MAC change in hardware. */
2068 fec_set_mac_address(struct net_device *ndev, void *p)
2070 struct fec_enet_private *fep = netdev_priv(ndev);
2071 struct sockaddr *addr = p;
2074 if (!is_valid_ether_addr(addr->sa_data))
2075 return -EADDRNOTAVAIL;
2076 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2079 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2080 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2081 fep->hwp + FEC_ADDR_LOW);
2082 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2083 fep->hwp + FEC_ADDR_HIGH);
2087 #ifdef CONFIG_NET_POLL_CONTROLLER
2089 * fec_poll_controller - FEC Poll controller function
2090 * @dev: The FEC network adapter
2092 * Polled functionality used by netconsole and others in non interrupt mode
2095 static void fec_poll_controller(struct net_device *dev)
2098 struct fec_enet_private *fep = netdev_priv(dev);
2100 for (i = 0; i < FEC_IRQ_NUM; i++) {
2101 if (fep->irq[i] > 0) {
2102 disable_irq(fep->irq[i]);
2103 fec_enet_interrupt(fep->irq[i], dev);
2104 enable_irq(fep->irq[i]);
2110 static int fec_set_features(struct net_device *netdev,
2111 netdev_features_t features)
2113 struct fec_enet_private *fep = netdev_priv(netdev);
2114 netdev_features_t changed = features ^ netdev->features;
2116 netdev->features = features;
2118 /* Receive checksum has been changed */
2119 if (changed & NETIF_F_RXCSUM) {
2120 if (features & NETIF_F_RXCSUM)
2121 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2123 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2125 if (netif_running(netdev)) {
2127 fec_restart(netdev, fep->phy_dev->duplex);
2128 netif_wake_queue(netdev);
2130 fec_restart(netdev, fep->phy_dev->duplex);
2137 static const struct net_device_ops fec_netdev_ops = {
2138 .ndo_open = fec_enet_open,
2139 .ndo_stop = fec_enet_close,
2140 .ndo_start_xmit = fec_enet_start_xmit,
2141 .ndo_set_rx_mode = set_multicast_list,
2142 .ndo_change_mtu = eth_change_mtu,
2143 .ndo_validate_addr = eth_validate_addr,
2144 .ndo_tx_timeout = fec_timeout,
2145 .ndo_set_mac_address = fec_set_mac_address,
2146 .ndo_do_ioctl = fec_enet_ioctl,
2147 #ifdef CONFIG_NET_POLL_CONTROLLER
2148 .ndo_poll_controller = fec_poll_controller,
2150 .ndo_set_features = fec_set_features,
2154 * XXX: We need to clean up on failure exits here.
2157 static int fec_enet_init(struct net_device *ndev)
2159 struct fec_enet_private *fep = netdev_priv(ndev);
2160 const struct platform_device_id *id_entry =
2161 platform_get_device_id(fep->pdev);
2162 struct bufdesc *cbd_base;
2165 /* init the tx & rx ring size */
2166 fep->tx_ring_size = TX_RING_SIZE;
2167 fep->rx_ring_size = RX_RING_SIZE;
2169 if (fep->bufdesc_ex)
2170 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2172 fep->bufdesc_size = sizeof(struct bufdesc);
2173 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2176 /* Allocate memory for buffer descriptors. */
2177 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
2182 memset(cbd_base, 0, PAGE_SIZE);
2186 /* Get the Ethernet address */
2188 /* make sure MAC we just acquired is programmed into the hw */
2189 fec_set_mac_address(ndev, NULL);
2191 /* Set receive and transmit descriptor base. */
2192 fep->rx_bd_base = cbd_base;
2193 if (fep->bufdesc_ex)
2194 fep->tx_bd_base = (struct bufdesc *)
2195 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2197 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2199 /* The FEC Ethernet specific entries in the device structure */
2200 ndev->watchdog_timeo = TX_TIMEOUT;
2201 ndev->netdev_ops = &fec_netdev_ops;
2202 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2204 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2205 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2207 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
2208 /* enable hw VLAN support */
2209 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2211 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2212 /* enable hw accelerator */
2213 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2214 | NETIF_F_RXCSUM | NETIF_F_SG);
2215 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2218 ndev->hw_features = ndev->features;
2220 fec_restart(ndev, 0);
2226 static void fec_reset_phy(struct platform_device *pdev)
2230 struct device_node *np = pdev->dev.of_node;
2235 of_property_read_u32(np, "phy-reset-duration", &msec);
2236 /* A sane reset duration should not be longer than 1s */
2240 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2241 if (!gpio_is_valid(phy_reset))
2244 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2245 GPIOF_OUT_INIT_LOW, "phy-reset");
2247 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2251 gpio_set_value(phy_reset, 1);
2253 #else /* CONFIG_OF */
2254 static void fec_reset_phy(struct platform_device *pdev)
2257 * In case of platform probe, the reset has been done
2261 #endif /* CONFIG_OF */
2264 fec_probe(struct platform_device *pdev)
2266 struct fec_enet_private *fep;
2267 struct fec_platform_data *pdata;
2268 struct net_device *ndev;
2269 int i, irq, ret = 0;
2271 const struct of_device_id *of_id;
2274 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2276 pdev->id_entry = of_id->data;
2278 /* Init network device */
2279 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2283 SET_NETDEV_DEV(ndev, &pdev->dev);
2285 /* setup board info structure */
2286 fep = netdev_priv(ndev);
2288 #if !defined(CONFIG_M5272)
2289 /* default enable pause frame auto negotiation */
2290 if (pdev->id_entry &&
2291 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2292 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2295 /* Select default pin state */
2296 pinctrl_pm_select_default_state(&pdev->dev);
2298 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2299 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2300 if (IS_ERR(fep->hwp)) {
2301 ret = PTR_ERR(fep->hwp);
2302 goto failed_ioremap;
2306 fep->dev_id = dev_id++;
2308 fep->bufdesc_ex = 0;
2310 platform_set_drvdata(pdev, ndev);
2312 ret = of_get_phy_mode(pdev->dev.of_node);
2314 pdata = dev_get_platdata(&pdev->dev);
2316 fep->phy_interface = pdata->phy;
2318 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2320 fep->phy_interface = ret;
2323 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2324 if (IS_ERR(fep->clk_ipg)) {
2325 ret = PTR_ERR(fep->clk_ipg);
2329 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2330 if (IS_ERR(fep->clk_ahb)) {
2331 ret = PTR_ERR(fep->clk_ahb);
2335 /* enet_out is optional, depends on board */
2336 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2337 if (IS_ERR(fep->clk_enet_out))
2338 fep->clk_enet_out = NULL;
2340 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2342 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2343 if (IS_ERR(fep->clk_ptp)) {
2344 fep->clk_ptp = NULL;
2345 fep->bufdesc_ex = 0;
2348 ret = fec_enet_clk_enable(ndev, true);
2352 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2353 if (!IS_ERR(fep->reg_phy)) {
2354 ret = regulator_enable(fep->reg_phy);
2357 "Failed to enable phy regulator: %d\n", ret);
2358 goto failed_regulator;
2361 fep->reg_phy = NULL;
2364 fec_reset_phy(pdev);
2366 if (fep->bufdesc_ex)
2369 ret = fec_enet_init(ndev);
2373 for (i = 0; i < FEC_IRQ_NUM; i++) {
2374 irq = platform_get_irq(pdev, i);
2381 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2382 0, pdev->name, ndev);
2387 ret = fec_enet_mii_init(pdev);
2389 goto failed_mii_init;
2391 /* Carrier starts down, phylib will bring it up */
2392 netif_carrier_off(ndev);
2393 fec_enet_clk_enable(ndev, false);
2394 pinctrl_pm_select_sleep_state(&pdev->dev);
2396 ret = register_netdev(ndev);
2398 goto failed_register;
2400 if (fep->bufdesc_ex && fep->ptp_clock)
2401 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2403 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2407 fec_enet_mii_remove(fep);
2412 regulator_disable(fep->reg_phy);
2414 fec_enet_clk_enable(ndev, false);
2423 fec_drv_remove(struct platform_device *pdev)
2425 struct net_device *ndev = platform_get_drvdata(pdev);
2426 struct fec_enet_private *fep = netdev_priv(ndev);
2428 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2429 unregister_netdev(ndev);
2430 fec_enet_mii_remove(fep);
2431 del_timer_sync(&fep->time_keep);
2433 regulator_disable(fep->reg_phy);
2435 ptp_clock_unregister(fep->ptp_clock);
2436 fec_enet_clk_enable(ndev, false);
2442 #ifdef CONFIG_PM_SLEEP
2444 fec_suspend(struct device *dev)
2446 struct net_device *ndev = dev_get_drvdata(dev);
2447 struct fec_enet_private *fep = netdev_priv(ndev);
2449 if (netif_running(ndev)) {
2451 netif_device_detach(ndev);
2453 fec_enet_clk_enable(ndev, false);
2454 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2457 regulator_disable(fep->reg_phy);
2463 fec_resume(struct device *dev)
2465 struct net_device *ndev = dev_get_drvdata(dev);
2466 struct fec_enet_private *fep = netdev_priv(ndev);
2470 ret = regulator_enable(fep->reg_phy);
2475 pinctrl_pm_select_default_state(&fep->pdev->dev);
2476 ret = fec_enet_clk_enable(ndev, true);
2480 if (netif_running(ndev)) {
2481 fec_restart(ndev, fep->full_duplex);
2482 netif_device_attach(ndev);
2489 regulator_disable(fep->reg_phy);
2492 #endif /* CONFIG_PM_SLEEP */
2494 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2496 static struct platform_driver fec_driver = {
2498 .name = DRIVER_NAME,
2499 .owner = THIS_MODULE,
2501 .of_match_table = fec_dt_ids,
2503 .id_table = fec_devtype,
2505 .remove = fec_drv_remove,
2508 module_platform_driver(fec_driver);
2510 MODULE_ALIAS("platform:"DRIVER_NAME);
2511 MODULE_LICENSE("GPL");